1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
|
From 6ddb5d4e28801907af7be39e47d502fd5c8e73e1 Mon Sep 17 00:00:00 2001
From: Mans Rullgard <mans@mansr.com>
Date: Wed, 14 Apr 2010 16:49:57 +0100
Subject: [PATCH 29/37] OMAP3: convert setup_auxcr() to pure asm
This function consists entirely of inline asm statements, so writing
it directly in a .S file is simpler. Additionally, the inline asm is
not safe as is, since registers are not guaranteed to be preserved
between asm() statements.
Signed-off-by: Mans Rullgard <mans@mansr.com>
---
cpu/arm_cortexa8/omap3/board.c | 35 -----------------------------------
cpu/arm_cortexa8/omap3/cache.S | 19 +++++++++++++++++++
2 files changed, 19 insertions(+), 35 deletions(-)
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index 0126152..7f49199 100644
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@ -122,41 +122,6 @@ void secureworld_exit()
}
/******************************************************************************
- * Routine: setup_auxcr()
- * Description: Write to AuxCR desired value using SMI.
- * general use.
- *****************************************************************************/
-void setup_auxcr()
-{
- unsigned long i;
- volatile unsigned int j;
- /* Save r0, r12 and restore them after usage */
- __asm__ __volatile__("mov %0, r12":"=r"(j));
- __asm__ __volatile__("mov %0, r0":"=r"(i));
-
- /*
- * GP Device ROM code API usage here
- * r12 = AUXCR Write function and r0 value
- */
- __asm__ __volatile__("mov r12, #0x3");
- __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
- /* Enabling ASA */
- __asm__ __volatile__("orr r0, r0, #0x10");
- /* Enable L1NEON */
- __asm__ __volatile__("orr r0, r0, #1 << 5");
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(".word 0xE1600070");
- /* Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround) */
- __asm__ __volatile__("mov r12, #0x2");
- __asm__ __volatile__("mrc p15, 1, r0, c9, c0, 2");
- __asm__ __volatile__("orr r0, r0, #1 << 27");
- /* SMI instruction to call ROM Code API */
- __asm__ __volatile__(".word 0xE1600070");
- __asm__ __volatile__("mov r0, %0":"=r"(i));
- __asm__ __volatile__("mov r12, %0":"=r"(j));
-}
-
-/******************************************************************************
* Routine: try_unlock_sram()
* Description: If chip is GP/EMU(special) type, unlock the SRAM for
* general use.
diff --git a/cpu/arm_cortexa8/omap3/cache.S b/cpu/arm_cortexa8/omap3/cache.S
index 16afb5d..61e6946 100644
--- a/cpu/arm_cortexa8/omap3/cache.S
+++ b/cpu/arm_cortexa8/omap3/cache.S
@@ -43,6 +43,7 @@
.global invalidate_dcache
.global l2_cache_enable
.global l2_cache_disable
+.global setup_auxcr
/*
* invalidate_dcache()
@@ -155,3 +156,21 @@ l2_cache_enable:
l2_cache_disable:
mov r0, #0
b l2_cache_set
+
+/******************************************************************************
+ * Routine: setup_auxcr()
+ * Description: Write to AuxCR desired value using SMI.
+ * general use.
+ *****************************************************************************/
+setup_auxcr:
+ mov r12, #0x3
+ mrc p15, 0, r0, c1, c0, 1
+ orr r0, r0, #0x10 @ Enable ASA
+ orr r0, r0, #1 << 5 @ Enable L1NEON
+ .word 0xE1600070 @ SMC
+ mov r12, #0x2
+ mrc p15, 1, r0, c9, c0, 2
+ @ Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround)
+ orr r0, r0, #1 << 27
+ .word 0xE1600070 @ SMC
+ bx lr
--
1.6.6.1
|
