diff options
| -rw-r--r-- | recipes/gcc/gcc-4.4.1.inc | 5 | ||||
| -rw-r--r-- | recipes/gcc/gcc-4.4.1/gcc-ppc_add_d_constraint.patch | 1216 | ||||
| -rw-r--r-- | recipes/gcc/gcc-4.4.1/gcc-ppc_single_precision_regs.patch | 60 | ||||
| -rw-r--r-- | recipes/gcc/gcc-4.4.1/gcc-pr41175.patch | 1172 |
4 files changed, 2452 insertions, 1 deletions
diff --git a/recipes/gcc/gcc-4.4.1.inc b/recipes/gcc/gcc-4.4.1.inc index f32f749ce6..9b47127486 100644 --- a/recipes/gcc/gcc-4.4.1.inc +++ b/recipes/gcc/gcc-4.4.1.inc @@ -7,7 +7,7 @@ LICENSE = "GPLv3" DEPENDS = "mpfr gmp" -INC_PR = "r5" +INC_PR = "r6" FILESPATHPKG .= ":gcc-$PV" @@ -20,6 +20,9 @@ SRC_URI = "${GNU_MIRROR}/gcc/gcc-${PV}/gcc-${PV}.tar.bz2 \ file://gcc-improve-tls-macro.patch;patch=1 \ file://cache-amnesia.patch;patch=1 \ file://gcc-flags-for-build.patch;patch=1 \ + file://gcc-ppc_single_precision_regs.patch;patch=1 \ + file://gcc-ppc_add_d_constraint.patch;patch=1 \ + file://gcc-pr41175.patch;patch=1 \ " # Language Overrides FORTRAN = "" diff --git a/recipes/gcc/gcc-4.4.1/gcc-ppc_add_d_constraint.patch b/recipes/gcc/gcc-4.4.1/gcc-ppc_add_d_constraint.patch new file mode 100644 index 0000000000..5e1da1ad09 --- /dev/null +++ b/recipes/gcc/gcc-4.4.1/gcc-ppc_add_d_constraint.patch @@ -0,0 +1,1216 @@ +Index: gcc-4.4.1/gcc/doc/md.texi +=================================================================== +--- gcc-4.4.1.orig/gcc/doc/md.texi 2009-10-06 14:08:35.847313399 -0700 ++++ gcc-4.4.1/gcc/doc/md.texi 2009-10-06 14:09:12.087313658 -0700 +@@ -1901,8 +1901,11 @@ Any constant whose absolute value is no + @item b + Address base register + ++@item d ++Floating point register (containing 64-bit value) ++ + @item f +-Floating point register ++Floating point register (containing 32-bit value) + + @item v + Vector register +Index: gcc-4.4.1/gcc/config/rs6000/constraints.md +=================================================================== +--- gcc-4.4.1.orig/gcc/config/rs6000/constraints.md 2009-10-06 14:08:35.827340958 -0700 ++++ gcc-4.4.1/gcc/config/rs6000/constraints.md 2009-10-06 14:09:12.087313658 -0700 +@@ -23,6 +23,10 @@ + ? FLOAT_REGS : NO_REGS" + "@internal") + ++(define_register_constraint "d" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT ++ ? FLOAT_REGS : NO_REGS" ++ "@internal") ++ + (define_register_constraint "b" "BASE_REGS" + "@internal") + +Index: gcc-4.4.1/gcc/config/rs6000/dfp.md +=================================================================== +--- gcc-4.4.1.orig/gcc/config/rs6000/dfp.md 2009-10-06 14:08:35.797315564 -0700 ++++ gcc-4.4.1/gcc/config/rs6000/dfp.md 2009-10-06 14:09:12.087313658 -0700 +@@ -105,7 +105,7 @@ + + (define_insn "movsd_store" + [(set (match_operand:DD 0 "nonimmediate_operand" "=m") +- (unspec:DD [(match_operand:SD 1 "input_operand" "f")] ++ (unspec:DD [(match_operand:SD 1 "input_operand" "d")] + UNSPEC_MOVSD_STORE))] + "(gpc_reg_operand (operands[0], DDmode) + || gpc_reg_operand (operands[1], SDmode)) +@@ -128,15 +128,15 @@ + ;; Hardware support for decimal floating point operations. + + (define_insn "extendsddd2" +- [(set (match_operand:DD 0 "gpc_reg_operand" "=f") ++ [(set (match_operand:DD 0 "gpc_reg_operand" "=d") + (float_extend:DD (match_operand:SD 1 "gpc_reg_operand" "f")))] + "TARGET_DFP" + "dctdp %0,%1" + [(set_attr "type" "fp")]) + + (define_expand "extendsdtd2" +- [(set (match_operand:TD 0 "gpc_reg_operand" "=f") +- (float_extend:TD (match_operand:SD 1 "gpc_reg_operand" "f")))] ++ [(set (match_operand:TD 0 "gpc_reg_operand" "=d") ++ (float_extend:TD (match_operand:SD 1 "gpc_reg_operand" "d")))] + "TARGET_DFP" + { + rtx tmp = gen_reg_rtx (DDmode); +@@ -147,7 +147,7 @@ + + (define_insn "truncddsd2" + [(set (match_operand:SD 0 "gpc_reg_operand" "=f") +- (float_truncate:SD (match_operand:DD 1 "gpc_reg_operand" "f")))] ++ (float_truncate:SD (match_operand:DD 1 "gpc_reg_operand" "d")))] + "TARGET_DFP" + "drsp %0,%1" + [(set_attr "type" "fp")]) +@@ -159,8 +159,8 @@ + "") + + (define_insn "*negdd2_fpr" +- [(set (match_operand:DD 0 "gpc_reg_operand" "=f") +- (neg:DD (match_operand:DD 1 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DD 0 "gpc_reg_operand" "=d") ++ (neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))] + "TARGET_HARD_FLOAT && TARGET_FPRS" + "fneg %0,%1" + [(set_attr "type" "fp")]) +@@ -172,15 +172,15 @@ + "") + + (define_insn "*absdd2_fpr" +- [(set (match_operand:DD 0 "gpc_reg_operand" "=f") +- (abs:DD (match_operand:DD 1 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DD 0 "gpc_reg_operand" "=d") ++ (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))] + "TARGET_HARD_FLOAT && TARGET_FPRS" + "fabs %0,%1" + [(set_attr "type" "fp")]) + + (define_insn "*nabsdd2_fpr" +- [(set (match_operand:DD 0 "gpc_reg_operand" "=f") +- (neg:DD (abs:DD (match_operand:DF 1 "gpc_reg_operand" "f"))))] ++ [(set (match_operand:DD 0 "gpc_reg_operand" "=d") ++ (neg:DD (abs:DD (match_operand:DF 1 "gpc_reg_operand" "d"))))] + "TARGET_HARD_FLOAT && TARGET_FPRS" + "fnabs %0,%1" + [(set_attr "type" "fp")]) +@@ -281,8 +281,8 @@ + ;; The "??" is a kludge until we can figure out a more reasonable way + ;; of handling these non-offsettable values. + (define_insn "*movdd_hardfloat32" +- [(set (match_operand:DD 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") +- (match_operand:DD 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] ++ [(set (match_operand:DD 0 "nonimmediate_operand" "=!r,??r,m,d,d,m,!r,!r,!r") ++ (match_operand:DD 1 "input_operand" "r,m,r,d,m,d,G,H,F"))] + "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS + && (gpc_reg_operand (operands[0], DDmode) + || gpc_reg_operand (operands[1], DDmode))" +@@ -417,8 +417,8 @@ + ; ld/std require word-aligned displacements -> 'Y' constraint. + ; List Y->r and r->Y before r->r for reload. + (define_insn "*movdd_hardfloat64_mfpgpr" +- [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f") +- (match_operand:DD 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))] ++ [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r,r,d") ++ (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F,d,r"))] + "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS + && (gpc_reg_operand (operands[0], DDmode) + || gpc_reg_operand (operands[1], DDmode))" +@@ -443,8 +443,8 @@ + ; ld/std require word-aligned displacements -> 'Y' constraint. + ; List Y->r and r->Y before r->r for reload. + (define_insn "*movdd_hardfloat64" +- [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r") +- (match_operand:DD 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))] ++ [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r") ++ (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F"))] + "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS + && (gpc_reg_operand (operands[0], DDmode) + || gpc_reg_operand (operands[1], DDmode))" +@@ -490,8 +490,8 @@ + "") + + (define_insn "*negtd2_fpr" +- [(set (match_operand:TD 0 "gpc_reg_operand" "=f") +- (neg:TD (match_operand:TD 1 "gpc_reg_operand" "f")))] ++ [(set (match_operand:TD 0 "gpc_reg_operand" "=d") ++ (neg:TD (match_operand:TD 1 "gpc_reg_operand" "d")))] + "TARGET_HARD_FLOAT && TARGET_FPRS" + "fneg %0,%1" + [(set_attr "type" "fp")]) +@@ -503,15 +503,15 @@ + "") + + (define_insn "*abstd2_fpr" +- [(set (match_operand:TD 0 "gpc_reg_operand" "=f") +- (abs:TD (match_operand:TD 1 "gpc_reg_operand" "f")))] ++ [(set (match_operand:TD 0 "gpc_reg_operand" "=d") ++ (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d")))] + "TARGET_HARD_FLOAT && TARGET_FPRS" + "fabs %0,%1" + [(set_attr "type" "fp")]) + + (define_insn "*nabstd2_fpr" +- [(set (match_operand:TD 0 "gpc_reg_operand" "=f") +- (neg:TD (abs:TD (match_operand:DF 1 "gpc_reg_operand" "f"))))] ++ [(set (match_operand:TD 0 "gpc_reg_operand" "=d") ++ (neg:TD (abs:TD (match_operand:DF 1 "gpc_reg_operand" "d"))))] + "TARGET_HARD_FLOAT && TARGET_FPRS" + "fnabs %0,%1" + [(set_attr "type" "fp")]) +@@ -526,8 +526,8 @@ + ; otherwise reload, given m->f, will try to pick f->f and reload it, + ; which doesn't make progress. Likewise r->Y must be before r->r. + (define_insn_and_split "*movtd_internal" +- [(set (match_operand:TD 0 "nonimmediate_operand" "=o,f,f,r,Y,r") +- (match_operand:TD 1 "input_operand" "f,o,f,YGHF,r,r"))] ++ [(set (match_operand:TD 0 "nonimmediate_operand" "=o,d,d,r,Y,r") ++ (match_operand:TD 1 "input_operand" "d,o,d,YGHF,r,r"))] + "TARGET_HARD_FLOAT && TARGET_FPRS + && (gpc_reg_operand (operands[0], TDmode) + || gpc_reg_operand (operands[1], TDmode))" +@@ -540,8 +540,8 @@ + ;; Hardware support for decimal floating point operations. + + (define_insn "extendddtd2" +- [(set (match_operand:TD 0 "gpc_reg_operand" "=f") +- (float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "f")))] ++ [(set (match_operand:TD 0 "gpc_reg_operand" "=d") ++ (float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "d")))] + "TARGET_DFP" + "dctqpq %0,%1" + [(set_attr "type" "fp")]) +@@ -552,96 +552,96 @@ + ;; that the result is the first of the pair receiving the result of drdpq. + + (define_insn "trunctddd2" +- [(set (match_operand:DD 0 "gpc_reg_operand" "=f") +- (float_truncate:DD (match_operand:TD 1 "gpc_reg_operand" "f"))) +- (clobber (match_scratch:TD 2 "=f"))] ++ [(set (match_operand:DD 0 "gpc_reg_operand" "=d") ++ (float_truncate:DD (match_operand:TD 1 "gpc_reg_operand" "d"))) ++ (clobber (match_scratch:TD 2 "=d"))] + "TARGET_DFP" + "drdpq %2,%1\;fmr %0,%2" + [(set_attr "type" "fp")]) + + (define_insn "adddd3" +- [(set (match_operand:DD 0 "gpc_reg_operand" "=f") +- (plus:DD (match_operand:DD 1 "gpc_reg_operand" "%f") +- (match_operand:DD 2 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DD 0 "gpc_reg_operand" "=d") ++ (plus:DD (match_operand:DD 1 "gpc_reg_operand" "%d") ++ (match_operand:DD 2 "gpc_reg_operand" "d")))] + "TARGET_DFP" + "dadd %0,%1,%2" + [(set_attr "type" "fp")]) + + (define_insn "addtd3" +- [(set (match_operand:TD 0 "gpc_reg_operand" "=f") +- (plus:TD (match_operand:TD 1 "gpc_reg_operand" "%f") +- (match_operand:TD 2 "gpc_reg_operand" "f")))] ++ [(set (match_operand:TD 0 "gpc_reg_operand" "=d") ++ (plus:TD (match_operand:TD 1 "gpc_reg_operand" "%d") ++ (match_operand:TD 2 "gpc_reg_operand" "d")))] + "TARGET_DFP" + "daddq %0,%1,%2" + [(set_attr "type" "fp")]) + + (define_insn "subdd3" +- [(set (match_operand:DD 0 "gpc_reg_operand" "=f") +- (minus:DD (match_operand:DD 1 "gpc_reg_operand" "f") +- (match_operand:DD 2 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DD 0 "gpc_reg_operand" "=d") ++ (minus:DD (match_operand:DD 1 "gpc_reg_operand" "d") ++ (match_operand:DD 2 "gpc_reg_operand" "d")))] + "TARGET_DFP" + "dsub %0,%1,%2" + [(set_attr "type" "fp")]) + + (define_insn "subtd3" +- [(set (match_operand:TD 0 "gpc_reg_operand" "=f") +- (minus:TD (match_operand:TD 1 "gpc_reg_operand" "f") +- (match_operand:TD 2 "gpc_reg_operand" "f")))] ++ [(set (match_operand:TD 0 "gpc_reg_operand" "=d") ++ (minus:TD (match_operand:TD 1 "gpc_reg_operand" "d") ++ (match_operand:TD 2 "gpc_reg_operand" "d")))] + "TARGET_DFP" + "dsubq %0,%1,%2" + [(set_attr "type" "fp")]) + + (define_insn "muldd3" +- [(set (match_operand:DD 0 "gpc_reg_operand" "=f") +- (mult:DD (match_operand:DD 1 "gpc_reg_operand" "%f") +- (match_operand:DD 2 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DD 0 "gpc_reg_operand" "=d") ++ (mult:DD (match_operand:DD 1 "gpc_reg_operand" "%d") ++ (match_operand:DD 2 "gpc_reg_operand" "d")))] + "TARGET_DFP" + "dmul %0,%1,%2" + [(set_attr "type" "fp")]) + + (define_insn "multd3" +- [(set (match_operand:TD 0 "gpc_reg_operand" "=f") +- (mult:TD (match_operand:TD 1 "gpc_reg_operand" "%f") +- (match_operand:TD 2 "gpc_reg_operand" "f")))] ++ [(set (match_operand:TD 0 "gpc_reg_operand" "=d") ++ (mult:TD (match_operand:TD 1 "gpc_reg_operand" "%d") ++ (match_operand:TD 2 "gpc_reg_operand" "d")))] + "TARGET_DFP" + "dmulq %0,%1,%2" + [(set_attr "type" "fp")]) + + (define_insn "divdd3" +- [(set (match_operand:DD 0 "gpc_reg_operand" "=f") +- (div:DD (match_operand:DD 1 "gpc_reg_operand" "f") +- (match_operand:DD 2 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DD 0 "gpc_reg_operand" "=d") ++ (div:DD (match_operand:DD 1 "gpc_reg_operand" "d") ++ (match_operand:DD 2 "gpc_reg_operand" "d")))] + "TARGET_DFP" + "ddiv %0,%1,%2" + [(set_attr "type" "fp")]) + + (define_insn "divtd3" +- [(set (match_operand:TD 0 "gpc_reg_operand" "=f") +- (div:TD (match_operand:TD 1 "gpc_reg_operand" "f") +- (match_operand:TD 2 "gpc_reg_operand" "f")))] ++ [(set (match_operand:TD 0 "gpc_reg_operand" "=d") ++ (div:TD (match_operand:TD 1 "gpc_reg_operand" "d") ++ (match_operand:TD 2 "gpc_reg_operand" "d")))] + "TARGET_DFP" + "ddivq %0,%1,%2" + [(set_attr "type" "fp")]) + + (define_insn "*cmpdd_internal1" + [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") +- (compare:CCFP (match_operand:DD 1 "gpc_reg_operand" "f") +- (match_operand:DD 2 "gpc_reg_operand" "f")))] ++ (compare:CCFP (match_operand:DD 1 "gpc_reg_operand" "d") ++ (match_operand:DD 2 "gpc_reg_operand" "d")))] + "TARGET_DFP" + "dcmpu %0,%1,%2" + [(set_attr "type" "fpcompare")]) + + (define_insn "*cmptd_internal1" + [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") +- (compare:CCFP (match_operand:TD 1 "gpc_reg_operand" "f") +- (match_operand:TD 2 "gpc_reg_operand" "f")))] ++ (compare:CCFP (match_operand:TD 1 "gpc_reg_operand" "d") ++ (match_operand:TD 2 "gpc_reg_operand" "d")))] + "TARGET_DFP" + "dcmpuq %0,%1,%2" + [(set_attr "type" "fpcompare")]) + + (define_insn "floatditd2" +- [(set (match_operand:TD 0 "gpc_reg_operand" "=f") +- (float:TD (match_operand:DI 1 "gpc_reg_operand" "f")))] ++ [(set (match_operand:TD 0 "gpc_reg_operand" "=d") ++ (float:TD (match_operand:DI 1 "gpc_reg_operand" "d")))] + "TARGET_DFP" + "dcffixq %0,%1" + [(set_attr "type" "fp")]) +@@ -650,8 +650,8 @@ + ;; This is the first stage of converting it to an integer type. + + (define_insn "ftruncdd2" +- [(set (match_operand:DD 0 "gpc_reg_operand" "=f") +- (fix:DD (match_operand:DD 1 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DD 0 "gpc_reg_operand" "=d") ++ (fix:DD (match_operand:DD 1 "gpc_reg_operand" "d")))] + "TARGET_DFP" + "drintn. 0,%0,%1,1" + [(set_attr "type" "fp")]) +@@ -660,8 +660,8 @@ + ;; This is the second stage of converting decimal float to integer type. + + (define_insn "fixdddi2" +- [(set (match_operand:DI 0 "gpc_reg_operand" "=f") +- (fix:DI (match_operand:DD 1 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DI 0 "gpc_reg_operand" "=d") ++ (fix:DI (match_operand:DD 1 "gpc_reg_operand" "d")))] + "TARGET_DFP" + "dctfix %0,%1" + [(set_attr "type" "fp")]) +@@ -670,8 +670,8 @@ + ;; This is the first stage of converting it to an integer type. + + (define_insn "ftrunctd2" +- [(set (match_operand:TD 0 "gpc_reg_operand" "=f") +- (fix:TD (match_operand:TD 1 "gpc_reg_operand" "f")))] ++ [(set (match_operand:TD 0 "gpc_reg_operand" "=d") ++ (fix:TD (match_operand:TD 1 "gpc_reg_operand" "d")))] + "TARGET_DFP" + "drintnq. 0,%0,%1,1" + [(set_attr "type" "fp")]) +@@ -680,8 +680,8 @@ + ;; This is the second stage of converting decimal float to integer type. + + (define_insn "fixtddi2" +- [(set (match_operand:DI 0 "gpc_reg_operand" "=f") +- (fix:DI (match_operand:TD 1 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DI 0 "gpc_reg_operand" "=d") ++ (fix:DI (match_operand:TD 1 "gpc_reg_operand" "d")))] + "TARGET_DFP" + "dctfixq %0,%1" + [(set_attr "type" "fp")]) +Index: gcc-4.4.1/gcc/config/rs6000/rs6000.md +=================================================================== +--- gcc-4.4.1.orig/gcc/config/rs6000/rs6000.md 2009-10-06 14:09:04.737313663 -0700 ++++ gcc-4.4.1/gcc/config/rs6000/rs6000.md 2009-10-06 14:09:12.087313658 -0700 +@@ -5119,7 +5119,7 @@ + "") + + (define_insn_and_split "*extendsfdf2_fpr" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f") ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d") + (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" + "@ +@@ -5142,7 +5142,7 @@ + + (define_insn "*truncdfsf2_fpr" + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") +- (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] ++ (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" + "frsp %0,%1" + [(set_attr "type" "fp")]) +@@ -5616,7 +5616,7 @@ + + (define_insn "*fseldfsf4" + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") +- (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") ++ (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d") + (match_operand:DF 4 "zero_fp_constant" "F")) + (match_operand:SF 2 "gpc_reg_operand" "f") + (match_operand:SF 3 "gpc_reg_operand" "f")))] +@@ -5631,8 +5631,8 @@ + "") + + (define_insn "*negdf2_fpr" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" + "fneg %0,%1" + [(set_attr "type" "fp")]) +@@ -5644,15 +5644,15 @@ + "") + + (define_insn "*absdf2_fpr" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" + "fabs %0,%1" + [(set_attr "type" "fp")]) + + (define_insn "*nabsdf2_fpr" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" + "fnabs %0,%1" + [(set_attr "type" "fp")]) +@@ -5665,9 +5665,9 @@ + "") + + (define_insn "*adddf3_fpr" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") +- (match_operand:DF 2 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d") ++ (match_operand:DF 2 "gpc_reg_operand" "d")))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" + "{fa|fadd} %0,%1,%2" + [(set_attr "type" "fp") +@@ -5681,9 +5681,9 @@ + "") + + (define_insn "*subdf3_fpr" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") +- (match_operand:DF 2 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d") ++ (match_operand:DF 2 "gpc_reg_operand" "d")))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" + "{fs|fsub} %0,%1,%2" + [(set_attr "type" "fp") +@@ -5697,9 +5697,9 @@ + "") + + (define_insn "*muldf3_fpr" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") +- (match_operand:DF 2 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d") ++ (match_operand:DF 2 "gpc_reg_operand" "d")))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" + "{fm|fmul} %0,%1,%2" + [(set_attr "type" "dmul") +@@ -5715,17 +5715,17 @@ + "") + + (define_insn "*divdf3_fpr" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") +- (match_operand:DF 2 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (div:DF (match_operand:DF 1 "gpc_reg_operand" "d") ++ (match_operand:DF 2 "gpc_reg_operand" "d")))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU" + "{fd|fdiv} %0,%1,%2" + [(set_attr "type" "ddiv")]) + + (define_expand "recipdf3" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f") +- (match_operand:DF 2 "gpc_reg_operand" "f")] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d") ++ (match_operand:DF 2 "gpc_reg_operand" "d")] + UNSPEC_FRES))] + "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size + && flag_finite_math_only && !flag_trapping_math" +@@ -5735,37 +5735,37 @@ + }) + + (define_insn "fred" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRES))] + "TARGET_POPCNTB && flag_finite_math_only" + "fre %0,%1" + [(set_attr "type" "fp")]) + + (define_insn "" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") +- (match_operand:DF 2 "gpc_reg_operand" "f")) +- (match_operand:DF 3 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d") ++ (match_operand:DF 2 "gpc_reg_operand" "d")) ++ (match_operand:DF 3 "gpc_reg_operand" "d")))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT" + "{fma|fmadd} %0,%1,%2,%3" + [(set_attr "type" "dmul") + (set_attr "fp_type" "fp_maddsub_d")]) + + (define_insn "" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") +- (match_operand:DF 2 "gpc_reg_operand" "f")) +- (match_operand:DF 3 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d") ++ (match_operand:DF 2 "gpc_reg_operand" "d")) ++ (match_operand:DF 3 "gpc_reg_operand" "d")))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT" + "{fms|fmsub} %0,%1,%2,%3" + [(set_attr "type" "dmul") + (set_attr "fp_type" "fp_maddsub_d")]) + + (define_insn "" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") +- (match_operand:DF 2 "gpc_reg_operand" "f")) +- (match_operand:DF 3 "gpc_reg_operand" "f"))))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d") ++ (match_operand:DF 2 "gpc_reg_operand" "d")) ++ (match_operand:DF 3 "gpc_reg_operand" "d"))))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT + && HONOR_SIGNED_ZEROS (DFmode)" + "{fnma|fnmadd} %0,%1,%2,%3" +@@ -5773,10 +5773,10 @@ + (set_attr "fp_type" "fp_maddsub_d")]) + + (define_insn "" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")) +- (match_operand:DF 2 "gpc_reg_operand" "f")) +- (match_operand:DF 3 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")) ++ (match_operand:DF 2 "gpc_reg_operand" "d")) ++ (match_operand:DF 3 "gpc_reg_operand" "d")))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT + && ! HONOR_SIGNED_ZEROS (DFmode)" + "{fnma|fnmadd} %0,%1,%2,%3" +@@ -5784,10 +5784,10 @@ + (set_attr "fp_type" "fp_maddsub_d")]) + + (define_insn "" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") +- (match_operand:DF 2 "gpc_reg_operand" "f")) +- (match_operand:DF 3 "gpc_reg_operand" "f"))))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d") ++ (match_operand:DF 2 "gpc_reg_operand" "d")) ++ (match_operand:DF 3 "gpc_reg_operand" "d"))))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT + && HONOR_SIGNED_ZEROS (DFmode)" + "{fnms|fnmsub} %0,%1,%2,%3" +@@ -5795,10 +5795,10 @@ + (set_attr "fp_type" "fp_maddsub_d")]) + + (define_insn "" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f") +- (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") +- (match_operand:DF 2 "gpc_reg_operand" "f"))))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (minus:DF (match_operand:DF 3 "gpc_reg_operand" "d") ++ (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d") ++ (match_operand:DF 2 "gpc_reg_operand" "d"))))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT + && ! HONOR_SIGNED_ZEROS (DFmode)" + "{fnms|fnmsub} %0,%1,%2,%3" +@@ -5806,8 +5806,8 @@ + (set_attr "fp_type" "fp_maddsub_d")]) + + (define_insn "sqrtdf2" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))] + "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS + && TARGET_DOUBLE_FLOAT" + "fsqrt %0,%1" +@@ -5865,21 +5865,21 @@ + }") + + (define_insn "*fseldfdf4" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d") + (match_operand:DF 4 "zero_fp_constant" "F")) +- (match_operand:DF 2 "gpc_reg_operand" "f") +- (match_operand:DF 3 "gpc_reg_operand" "f")))] ++ (match_operand:DF 2 "gpc_reg_operand" "d") ++ (match_operand:DF 3 "gpc_reg_operand" "d")))] + "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" + "fsel %0,%1,%2,%3" + [(set_attr "type" "fp")]) + + (define_insn "*fselsfdf4" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") + (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") + (match_operand:SF 4 "zero_fp_constant" "F")) +- (match_operand:DF 2 "gpc_reg_operand" "f") +- (match_operand:DF 3 "gpc_reg_operand" "f")))] ++ (match_operand:DF 2 "gpc_reg_operand" "d") ++ (match_operand:DF 3 "gpc_reg_operand" "d")))] + "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT" + "fsel %0,%1,%2,%3" + [(set_attr "type" "fp")]) +@@ -5935,12 +5935,12 @@ + }") + + (define_insn_and_split "*floatsidf2_internal" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=&d") + (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) + (use (match_operand:SI 2 "gpc_reg_operand" "r")) +- (use (match_operand:DF 3 "gpc_reg_operand" "f")) ++ (use (match_operand:DF 3 "gpc_reg_operand" "d")) + (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o")) +- (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f")) ++ (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d")) + (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))] + "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" + "#" +@@ -6003,12 +6003,12 @@ + }") + + (define_insn_and_split "*floatunssidf2_internal" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=&d") + (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) + (use (match_operand:SI 2 "gpc_reg_operand" "r")) +- (use (match_operand:DF 3 "gpc_reg_operand" "f")) ++ (use (match_operand:DF 3 "gpc_reg_operand" "d")) + (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o")) +- (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))] ++ (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))] + "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" + "#" + "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))" +@@ -6072,8 +6072,8 @@ + + (define_insn_and_split "*fix_truncdfsi2_internal" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +- (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) +- (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) ++ (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d"))) ++ (clobber (match_operand:DI 2 "gpc_reg_operand" "=d")) + (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))] + "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS + && TARGET_DOUBLE_FLOAT" +@@ -6095,8 +6095,8 @@ + + (define_insn_and_split "fix_truncdfsi2_internal_gfxopt" + [(set (match_operand:SI 0 "memory_operand" "=Z") +- (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) +- (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))] ++ (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d"))) ++ (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))] + "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS + && TARGET_DOUBLE_FLOAT + && TARGET_PPC_GFXOPT" +@@ -6113,8 +6113,8 @@ + + (define_insn_and_split "fix_truncdfsi2_mfpgpr" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +- (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) +- (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) ++ (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d"))) ++ (clobber (match_operand:DI 2 "gpc_reg_operand" "=d")) + (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))] + "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS + && TARGET_DOUBLE_FLOAT" +@@ -6131,8 +6131,8 @@ + ; because the first makes it clear that operand 0 is not live + ; before the instruction. + (define_insn "fctiwz" +- [(set (match_operand:DI 0 "gpc_reg_operand" "=f") +- (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] ++ [(set (match_operand:DI 0 "gpc_reg_operand" "=d") ++ (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "d"))] + UNSPEC_FCTIWZ))] + "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS + && TARGET_DOUBLE_FLOAT" +@@ -6140,8 +6140,8 @@ + [(set_attr "type" "fp")]) + + (define_insn "btruncdf2" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIZ))] + "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" + "friz %0,%1" + [(set_attr "type" "fp")]) +@@ -6154,8 +6154,8 @@ + [(set_attr "type" "fp")]) + + (define_insn "ceildf2" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIP))] + "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" + "frip %0,%1" + [(set_attr "type" "fp")]) +@@ -6168,8 +6168,8 @@ + [(set_attr "type" "fp")]) + + (define_insn "floordf2" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIM))] + "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" + "frim %0,%1" + [(set_attr "type" "fp")]) +@@ -6182,8 +6182,8 @@ + [(set_attr "type" "fp")]) + + (define_insn "rounddf2" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIN))] + "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" + "frin %0,%1" + [(set_attr "type" "fp")]) +@@ -6198,7 +6198,7 @@ + ; An UNSPEC is used so we don't have to support SImode in FP registers. + (define_insn "stfiwx" + [(set (match_operand:SI 0 "memory_operand" "=Z") +- (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")] ++ (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")] + UNSPEC_STFIWX))] + "TARGET_PPC_GFXOPT" + "stfiwx %1,%y0" +@@ -6211,15 +6211,15 @@ + "") + + (define_insn "floatdidf2" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (float:DF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (float:DF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))] + "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS" + "fcfid %0,%1" + [(set_attr "type" "fp")]) + + (define_insn "fix_truncdfdi2" +- [(set (match_operand:DI 0 "gpc_reg_operand" "=!f#r") +- (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DI 0 "gpc_reg_operand" "=!d#r") ++ (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d")))] + "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS" + "fctidz %0,%1" + [(set_attr "type" "fp")]) +@@ -6247,8 +6247,8 @@ + ;; from double rounding. + (define_insn_and_split "floatdisf2_internal1" + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") +- (float:SF (match_operand:DI 1 "gpc_reg_operand" "!f#r"))) +- (clobber (match_scratch:DF 2 "=f"))] ++ (float:SF (match_operand:DI 1 "gpc_reg_operand" "!d#r"))) ++ (clobber (match_scratch:DF 2 "=d"))] + "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" + "#" + "&& reload_completed" +@@ -8497,8 +8497,8 @@ + ;; The "??" is a kludge until we can figure out a more reasonable way + ;; of handling these non-offsettable values. + (define_insn "*movdf_hardfloat32" +- [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") +- (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] ++ [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,d,d,m,!r,!r,!r") ++ (match_operand:DF 1 "input_operand" "r,m,r,d,m,d,G,H,F"))] + "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT + && (gpc_reg_operand (operands[0], DFmode) + || gpc_reg_operand (operands[1], DFmode))" +@@ -8637,8 +8637,8 @@ + ; ld/std require word-aligned displacements -> 'Y' constraint. + ; List Y->r and r->Y before r->r for reload. + (define_insn "*movdf_hardfloat64_mfpgpr" +- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f") +- (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))] ++ [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r,r,d") ++ (match_operand:DF 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F,d,r"))] + "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS + && TARGET_DOUBLE_FLOAT + && (gpc_reg_operand (operands[0], DFmode) +@@ -8664,8 +8664,8 @@ + ; ld/std require word-aligned displacements -> 'Y' constraint. + ; List Y->r and r->Y before r->r for reload. + (define_insn "*movdf_hardfloat64" +- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r") +- (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))] ++ [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r") ++ (match_operand:DF 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F"))] + "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS + && TARGET_DOUBLE_FLOAT + && (gpc_reg_operand (operands[0], DFmode) +@@ -8715,8 +8715,8 @@ + ; otherwise reload, given m->f, will try to pick f->f and reload it, + ; which doesn't make progress. Likewise r->Y must be before r->r. + (define_insn_and_split "*movtf_internal" +- [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r") +- (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))] ++ [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r") ++ (match_operand:TF 1 "input_operand" "d,o,d,YGHF,r,r"))] + "!TARGET_IEEEQUAD + && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 + && (gpc_reg_operand (operands[0], TFmode) +@@ -8770,9 +8770,9 @@ + }) + + (define_insn_and_split "*extenddftf2_internal" +- [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r") +- (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF"))) +- (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))] ++ [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r") ++ (float_extend:TF (match_operand:DF 1 "input_operand" "dr,md,md,rmGHF"))) ++ (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))] + "!TARGET_IEEEQUAD + && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT + && TARGET_LONG_DOUBLE_128" +@@ -8813,8 +8813,8 @@ + "") + + (define_insn_and_split "trunctfdf2_internal1" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f") +- (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d") ++ (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))] + "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT + && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" + "@ +@@ -8829,8 +8829,8 @@ + [(set_attr "type" "fp")]) + + (define_insn "trunctfdf2_internal2" +- [(set (match_operand:DF 0 "gpc_reg_operand" "=f") +- (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] ++ [(set (match_operand:DF 0 "gpc_reg_operand" "=d") ++ (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))] + "!TARGET_IEEEQUAD && TARGET_XL_COMPAT + && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT + && TARGET_LONG_DO |