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-rw-r--r--classes/scons.bbclass22
-rw-r--r--conf/distro/include/sane-srcrevs.inc2
-rw-r--r--recipes/opencv/artoolkitplus_2.2.0.bb17
-rw-r--r--recipes/python/python-scons/toolchain-from-env.SConscript12
-rw-r--r--recipes/python/python-scons_1.3.0.bb23
-rw-r--r--recipes/u-boot/u-boot-git/beagleboard/0001-Minimal-Display-driver-for-OMAP3.patch (renamed from recipes/u-boot/u-boot-git/beagleboard/dss.patch)1111
-rw-r--r--recipes/u-boot/u-boot-git/beagleboard/0001-omap3-clock.c-don-t-reprogram-clocks-when-trying-to-.patch50
-rw-r--r--recipes/u-boot/u-boot-git/beagleboard/0002-beagleboard-add-pinmuxing-for-beagleboard-XM.patch69
-rw-r--r--recipes/u-boot/u-boot-git/beagleboard/0003-beagleboard-move-muxing-into-revision-print-switch.patch53
-rw-r--r--recipes/u-boot/u-boot-git/beagleboard/720MHz.patch166
-rw-r--r--recipes/u-boot/u-boot-git/beagleboard/i2c.patch141
-rw-r--r--recipes/u-boot/u-boot-git/beagleboard/revision-detection.patch144
-rw-r--r--recipes/u-boot/u-boot_git.bb21
13 files changed, 580 insertions, 1251 deletions
diff --git a/classes/scons.bbclass b/classes/scons.bbclass
index b139411c19..2a935e4685 100644
--- a/classes/scons.bbclass
+++ b/classes/scons.bbclass
@@ -1,8 +1,18 @@
DEPENDS += "python-scons-native"
+export TARGET_LINK_HASH_STYLE
+
scons_do_compile() {
- ${STAGING_BINDIR_NATIVE}/scons ${PARALLEL_MAKE} PREFIX=${prefix} prefix=${prefix} || \
- oefatal "scons build execution failed."
+ if [ "${SCONS_FIX_ENV}" = "1" ] ; then
+ if grep "toolchain-from-env" ${S}/SConstruct ; then
+ echo "Toolchain overrides already applied"
+ else
+ cat ${STAGING_DATADIR_NATIVE}/scons/toolchain-from-env.SConscript >> ${S}/SConstruct
+ fi
+ fi
+
+ ${STAGING_BINDIR_NATIVE}/scons ${PARALLEL_MAKE} CXX="${CXX}" PREFIX=${prefix} prefix=${prefix} || \
+ oefatal "scons build execution failed."
}
scons_do_install() {
@@ -11,10 +21,4 @@ scons_do_install() {
oefatal "scons install execution failed."
}
-scons_do_stage() {
- install -d ${D}${prefix}
- ${STAGING_BINDIR_NATIVE}/scons PREFIX=${STAGING_DIR_HOST}/${prefix} prefix=${STAGING_DIR_HOST}/${prefix} install || \
- oefatal "scons stage execution failed."
-}
-
-EXPORT_FUNCTIONS do_compile do_install do_stage
+EXPORT_FUNCTIONS do_compile do_install
diff --git a/conf/distro/include/sane-srcrevs.inc b/conf/distro/include/sane-srcrevs.inc
index 34673c35ca..c4d1e093aa 100644
--- a/conf/distro/include/sane-srcrevs.inc
+++ b/conf/distro/include/sane-srcrevs.inc
@@ -219,7 +219,7 @@ SRCREV_pn-xserver-kdrive-glamo ?= "9b28d998424c77fbc057dd3a022ccbb122793a52"
# Enlightenment Foundation Libraries
# Caution: This is not alphabetically, but (roughly) dependency-sorted.
# Please leave it like that.
-EFL_SRCREV ?= "47555"
+EFL_SRCREV ?= "47589"
SRCREV_pn-edb-native ?= "${EFL_SRCREV}"
SRCREV_pn-edb ?= "${EFL_SRCREV}"
SRCREV_pn-eina-native ?= "${EFL_SRCREV}"
diff --git a/recipes/opencv/artoolkitplus_2.2.0.bb b/recipes/opencv/artoolkitplus_2.2.0.bb
new file mode 100644
index 0000000000..98880c8f2c
--- /dev/null
+++ b/recipes/opencv/artoolkitplus_2.2.0.bb
@@ -0,0 +1,17 @@
+DESCRIPTION = "ARToolKitPlus is a software library that can be used to calculate camera position and orientation relative to physical markers in real time. This enables the easy development of a wide range of Augmented Reality applications."
+LICENSE = "GPLv3"
+
+DEPENDS = "libxi gstreamer virtual/libx11 freeglut virtual/libgl"
+
+SRC_URI = "http://edge.launchpad.net/artoolkitplus/trunk/${PV}/+download/artoolkitplus-${PV}.tar.bz2;name=archive \
+"
+
+SRC_URI[archive.md5sum] = "385d72a3222702d775c9517a18d8fd83"
+SRC_URI[archive.sha256sum] = "e1189ab1eaba97cecb043875137046efe03b8d6aceed0916933f2d7776c1a971"
+
+
+SCONS_FIX_ENV = "1"
+inherit scons
+
+FILES_${PN} += "${libdir}/*.so"
+
diff --git a/recipes/python/python-scons/toolchain-from-env.SConscript b/recipes/python/python-scons/toolchain-from-env.SConscript
new file mode 100644
index 0000000000..051ccec79e
--- /dev/null
+++ b/recipes/python/python-scons/toolchain-from-env.SConscript
@@ -0,0 +1,12 @@
+#toolchain-from-env
+
+import os
+env['CC'] = os.environ['CC']
+env['CXX'] = os.environ['CXX']
+env['CPP'] = os.environ['CPP']
+env['AR'] = os.environ['AR']
+env['LD'] = os.environ['LD']
+env['CCLD'] = os.environ['CCLD']
+env['ENV']['PATH'] = os.environ['PATH']
+
+env['LINKFLAGS'] = os.environ['TARGET_LINK_HASH_STYLE'] + " " + env['LINKFLAGS']
diff --git a/recipes/python/python-scons_1.3.0.bb b/recipes/python/python-scons_1.3.0.bb
new file mode 100644
index 0000000000..792e3a54f7
--- /dev/null
+++ b/recipes/python/python-scons_1.3.0.bb
@@ -0,0 +1,23 @@
+DESCRIPTION = "A Software Construction Tool"
+SECTION = "devel/python"
+PRIORITY = "optional"
+LICENSE = "GPL"
+SRCNAME = "scons"
+
+SRC_URI = "${SOURCEFORGE_MIRROR}/scons/scons-${PV}.tar.gz;name=scons \
+ file://toolchain-from-env.SConscript \
+"
+SRC_URI[scons.md5sum] = "ad6838c867abd2ad5bf371b353d594f7"
+SRC_URI[scons.sha256sum] = "4bde47b9a40fe767f089f5996d56b6e85a2d4929309b9c07a2dff363a78b0002"
+
+S = "${WORKDIR}/${SRCNAME}-${PV}"
+
+inherit distutils
+
+do_install_append() {
+ install -d ${D}${datadir}/scons/
+ install -m 0644 ${WORKDIR}/toolchain-from-env.SConscript ${D}${datadir}/scons/
+}
+
+NATIVE_INSTALL_WORKS = "1"
+BBCLASSEXTEND = "native"
diff --git a/recipes/u-boot/u-boot-git/beagleboard/dss.patch b/recipes/u-boot/u-boot-git/beagleboard/0001-Minimal-Display-driver-for-OMAP3.patch
index ddb248d410..f3a17b745c 100644
--- a/recipes/u-boot/u-boot-git/beagleboard/dss.patch
+++ b/recipes/u-boot/u-boot-git/beagleboard/0001-Minimal-Display-driver-for-OMAP3.patch
@@ -1,603 +1,508 @@
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-Date: Fri, 8 Jan 2010 21:10:56 +0530
-Message-ID: <a8ca84ad1001080740q210440d5t6e93a9cff1ee2c23@mail.gmail.com>
-Subject: [beagleboard] TI:OMAP: [PATCH 4/4] Minimal Display driver for OMAP3
-From: Khasim Syed Mohammed <khasim@beagleboard.org>
-To: u-boot@lists.denx.de, beagleboard@googlegroups.com
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---0016e64cc3d48ed9db047ca903b2
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-
-From 239c47a4180fb4d5b5217f892955524d476916cf Mon Sep 17 00:00:00 2001
-From: Syed Mohammed Khasim <khasim@ti.com>
-Date: Fri, 8 Jan 2010 21:01:44 +0530
-Subject: [PATCH] Minimal Display driver for OMAP3
-
-Supports dynamic configuration of Panel and Video Encoder
-Supports Background color on DVID
-Supports Color bar on S-Video
-
-Signed-off-by: Syed Mohammed Khasim <khasim@ti.com>
----
- board/ti/beagle/beagle.c | 13 +++
- board/ti/beagle/beagle.h | 73 ++++++++++++++
- drivers/video/Makefile | 1 +
- drivers/video/omap3_dss.c | 128 +++++++++++++++++++++++++
- include/asm-arm/arch-omap3/dss.h | 193 ++++++++++++++++++++++++++++++++++++++
- include/configs/omap3_beagle.h | 1 +
- 6 files changed, 409 insertions(+), 0 deletions(-)
- create mode 100644 drivers/video/omap3_dss.c
- create mode 100644 include/asm-arm/arch-omap3/dss.h
-
-diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
-index 7985ee9..29e47c8 100644
---- a/board/ti/beagle/beagle.c
-+++ b/board/ti/beagle/beagle.c
-@@ -114,6 +114,17 @@ void beagle_identify(void)
- }
-
- /*
-+ * Configure DSS to display background color on DVID
-+ * Configure VENC to display color bar on S-Video
-+ */
-+void display_init(void)
-+{
-+ omap3_dss_venc_config(&venc_config_std_tv);
-+ omap3_dss_panel_config(&dvid_cfg);
-+ omap3_dss_set_background_col(DVI_BEAGLE_ORANGE_COL);
-+}
-+
-+/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-@@ -122,6 +133,7 @@ int misc_init_r(void)
- struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
- struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
-
-+ display_init();
- beagle_identify();
-
- twl4030_power_init();
-@@ -154,6 +166,7 @@ int misc_init_r(void)
- writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
- GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
-
-+ omap3_dss_enable();
- dieid_num_r();
-
- return 0;
-diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
-index b1720c9..7f6769f 100644
---- a/board/ti/beagle/beagle.h
-+++ b/board/ti/beagle/beagle.h
-@@ -23,6 +23,8 @@
- #ifndef _BEAGLE_H_
- #define _BEAGLE_H_
-
-+#include <asm/arch/dss.h>
-+
- const omap3_sysinfo sysinfo = {
- DDR_STACKED,
- "OMAP3 Beagle board",
-@@ -385,4 +387,75 @@ const omap3_sysinfo sysinfo = {
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/
-
-+/*
-+ * Display Configuration
-+ */
-+
-+#define DVI_BEAGLE_ORANGE_COL 0x00FF8000
-+
-+/*
-+ * Configure VENC in DSS for Beagle to generate Color Bar
-+ *
-+ * Kindly refer to OMAP TRM for definition of these values.
-+ */
-+static const struct venc_config venc_config_std_tv = {
-+ .status = 0x0000001B,
-+ .f_control = 0x00000040,
-+ .vidout_ctrl = 0x00000000,
-+ .sync_ctrl = 0x00008000,
-+ .llen = 0x00008359,
-+ .flens = 0x0000020C,
-+ .hfltr_ctrl = 0x00000000,
-+ .cc_carr_wss_carr = 0x043F2631,
-+ .c_phase = 0x00000024,
-+ .gain_u = 0x00000130,
-+ .gain_v = 0x00000198,
-+ .gain_y = 0x000001C0,
-+ .black_level = 0x0000006A,
-+ .blank_level = 0x0000005C,
-+ .x_color = 0x00000000,
-+ .m_control = 0x00000001,
-+ .bstamp_wss_data = 0x0000003F,
-+ .s_carr = 0x21F07C1F,
-+ .line21 = 0x00000000,
-+ .ln_sel = 0x00000015,
-+ .l21__wc_ctl = 0x00001400,
-+ .htrigger_vtrigger = 0x00000000,
-+ .savid__eavid = 0x069300F4,
-+ .flen__fal = 0x0016020C,
-+ .lal__phase_reset = 0x00060107,
-+ .hs_int_start_stop_x = 0x008D034E,
-+ .hs_ext_start_stop_x = 0x000F0359,
-+ .vs_int_start_x = 0x01A00000,
-+ .vs_int_stop_x__vs_int_start_y = 0x020501A0,
-+ .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
-+ .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
-+ .vs_ext_stop_y = 0x00000006,
-+ .avid_start_stop_x = 0x03480079,
-+ .avid_start_stop_y = 0x02040024,
-+ .fid_int_start_x__fid_int_start_y = 0x0001008A,
-+ .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
-+ .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
-+ .tvdetgp_int_start_stop_x = 0x00140001,
-+ .tvdetgp_int_start_stop_y = 0x00010001,
-+ .gen_ctrl = 0x00FF0000,
-+ .output_control = 0x0000000D,
-+ .dac_b__dac_c = 0x00000000,
-+ .height_width = 0x00ef027f
-+};
-+
-+/*
-+ * Configure Timings for DVI D
-+ */
-+static const struct panel_config dvid_cfg = {
-+ .timing_h = 0x0ff03f31, /* Horizantal timing */
-+ .timing_v = 0x01400504, /* Vertical timing */
-+ .pol_freq = 0x00007028, /* Pol Freq */
-+ .divisor = 0x00010006, /* 72Mhz Pixel Clock */
-+ .lcd_size = 0x02ff03ff, /* 1024x768 */
-+ .panel_type = 0x01, /* TFT */
-+ .data_lines = 0x03, /* 24 Bit RGB */
-+ .load_mode = 0x02 /* Frame Mode */
-+};
-+
- #endif
-diff --git a/drivers/video/Makefile b/drivers/video/Makefile
-index bb6b5a0..cb15dc2 100644
---- a/drivers/video/Makefile
-+++ b/drivers/video/Makefile
-@@ -37,6 +37,7 @@ COBJS-$(CONFIG_SED156X) += sed156x.o
- COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
- COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o
- COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
-+COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
- COBJS-y += videomodes.o
-
- COBJS := $(COBJS-y)
-diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c
-new file mode 100644
-index 0000000..2ead7b9
---- /dev/null
-+++ b/drivers/video/omap3_dss.c
-@@ -0,0 +1,128 @@
-+/*
-+ * (C) Copyright 2010
-+ * Texas Instruments, <www.ti.com>
-+ * Syed Mohammed Khasim <khasim@ti.com>
-+ *
-+ * Referred to Linux DSS driver files for OMAP3
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation's version 2 of
-+ * the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#include <common.h>
-+#include <asm/io.h>
-+#include <asm/arch/dss.h>
-+
-+/*
-+ * VENC configuration
-+ */
-+void omap3_dss_venc_config(const struct venc_config *venc_cfg)
-+{
-+ dss_write_reg(VENC_STATUS, venc_cfg->status);
-+ dss_write_reg(VENC_F_CONTROL, venc_cfg->f_control);
-+ dss_write_reg(VENC_VIDOUT_CTRL, venc_cfg->vidout_ctrl);
-+ dss_write_reg(VENC_SYNC_CTRL, venc_cfg->sync_ctrl);
-+ dss_write_reg(VENC_LLEN, venc_cfg->llen);
-+ dss_write_reg(VENC_FLENS, venc_cfg->flens);
-+ dss_write_reg(VENC_HFLTR_CTRL, venc_cfg->hfltr_ctrl);
-+ dss_write_reg(VENC_CC_CARR_WSS_CARR, venc_cfg->cc_carr_wss_carr);
-+ dss_write_reg(VENC_C_PHASE, venc_cfg->c_phase);
-+ dss_write_reg(VENC_GAIN_U, venc_cfg->gain_u);
-+ dss_write_reg(VENC_GAIN_V, venc_cfg->gain_v);
-+ dss_write_reg(VENC_GAIN_Y, venc_cfg->gain_y);
-+ dss_write_reg(VENC_BLACK_LEVEL, venc_cfg->black_level);
-+ dss_write_reg(VENC_BLANK_LEVEL, venc_cfg->blank_level);
-+ dss_write_reg(VENC_X_COLOR, venc_cfg->x_color);
-+ dss_write_reg(VENC_M_CONTROL, venc_cfg->m_control);
-+ dss_write_reg(VENC_BSTAMP_WSS_DATA, venc_cfg->bstamp_wss_data);
-+ dss_write_reg(VENC_S_CARR, venc_cfg->s_carr);
-+ dss_write_reg(VENC_LINE21, venc_cfg->line21);
-+ dss_write_reg(VENC_LN_SEL, venc_cfg->ln_sel);
-+ dss_write_reg(VENC_L21__WC_CTL, venc_cfg->l21__wc_ctl);
-+ dss_write_reg(VENC_HTRIGGER_VTRIGGER, venc_cfg->htrigger_vtrigger);
-+ dss_write_reg(VENC_SAVID__EAVID, venc_cfg->savid__eavid);
-+ dss_write_reg(VENC_FLEN__FAL, venc_cfg->flen__fal);
-+ dss_write_reg(VENC_LAL__PHASE_RESET, venc_cfg->lal__phase_reset);
-+ dss_write_reg(VENC_HS_INT_START_STOP_X,
-+ venc_cfg->hs_int_start_stop_x);
-+ dss_write_reg(VENC_HS_EXT_START_STOP_X,
-+ venc_cfg->hs_ext_start_stop_x);
-+ dss_write_reg(VENC_VS_INT_START_X, venc_cfg->vs_int_start_x);
-+ dss_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
-+ venc_cfg->vs_int_stop_x__vs_int_start_y);
-+ dss_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
-+ venc_cfg->vs_int_stop_y__vs_ext_start_x);
-+ dss_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
-+ venc_cfg->vs_ext_stop_x__vs_ext_start_y);
-+ dss_write_reg(VENC_VS_EXT_STOP_Y, venc_cfg->vs_ext_stop_y);
-+ dss_write_reg(VENC_AVID_START_STOP_X, venc_cfg->avid_start_stop_x);
-+ dss_write_reg(VENC_AVID_START_STOP_Y, venc_cfg->avid_start_stop_y);
-+ dss_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
-+ venc_cfg->fid_int_start_x__fid_int_start_y);
-+ dss_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
-+ venc_cfg->fid_int_offset_y__fid_ext_start_x);
-+ dss_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
-+ venc_cfg->fid_ext_start_y__fid_ext_offset_y);
-+ dss_write_reg(VENC_TVDETGP_INT_START_STOP_X,
-+ venc_cfg->tvdetgp_int_start_stop_x);
-+ dss_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
-+ venc_cfg->tvdetgp_int_start_stop_y);
-+ dss_write_reg(VENC_GEN_CTRL, venc_cfg->gen_ctrl);
-+ dss_write_reg(VENC_OUTPUT_CONTROL, venc_cfg->output_control);
-+ dss_write_reg(VENC_DAC_B__DAC_C, venc_cfg->dac_b__dac_c);
-+ dss_write_reg(DISPC_SIZE_DIG, venc_cfg->height_width);
-+ dss_write_reg(DSS_CONTROL, VENC_DSS_CONFIG);
-+}
-+
-+/*
-+ * Configure Panel Specific parameters
-+ */
-+void omap3_dss_panel_config(const struct panel_config *panel_cfg)
-+{
-+ dss_write_reg(DISPC_TIMING_H, panel_cfg->timing_h);
-+ dss_write_reg(DISPC_TIMING_V, panel_cfg->timing_v);
-+ dss_write_reg(DISPC_POL_FREQ, panel_cfg->pol_freq);
-+ dss_write_reg(DISPC_DIVISOR, panel_cfg->divisor);
-+ dss_write_reg(DISPC_SIZE_LCD, panel_cfg->lcd_size);
-+ dss_write_reg(DISPC_CONFIG,
-+ (panel_cfg->load_mode << FRAME_MODE_OFFSET));
-+ dss_write_reg(DISPC_CONTROL,
-+ ((panel_cfg->panel_type << TFTSTN_OFFSET) |
-+ (panel_cfg->data_lines << DATALINES_OFFSET)));
-+}
-+
-+/*
-+ * Enable LCD and DIGITAL OUT in DSS
-+ */
-+void omap3_dss_enable(void)
-+{
-+ u32 l = 0;
-+
-+ l = dss_read_reg(DISPC_CONTROL);
-+ l |= DISPC_ENABLE;
-+
-+ dss_write_reg(DISPC_CONTROL, l);
-+}
-+
-+/*
-+ * Set Background Color in DISPC
-+ */
-+void omap3_dss_set_background_col(u32 color)
-+{
-+ dss_write_reg(DISPC_DEFAULT_COLOR0, color);
-+}
-diff --git a/include/asm-arm/arch-omap3/dss.h b/include/asm-arm/arch-omap3/dss.h
-new file mode 100644
-index 0000000..08c7d8d
---- /dev/null
-+++ b/include/asm-arm/arch-omap3/dss.h
-@@ -0,0 +1,193 @@
-+/*
-+ * (C) Copyright 2010
-+ * Texas Instruments, <www.ti.com>
-+ * Syed Mohammed Khasim <khasim@ti.com>
-+ *
-+ * Referred to Linux DSS driver files for OMAP3
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation's version 2 of
-+ * the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#ifndef DSS_H
-+#define DSS_H
-+
-+/* VENC Register address */
-+#define VENC_REV_ID 0x48050C00
-+#define VENC_STATUS 0x48050C04
-+#define VENC_F_CONTROL 0x48050C08
-+#define VENC_VIDOUT_CTRL 0x48050C10
-+#define VENC_SYNC_CTRL 0x48050C14
-+#define VENC_LLEN 0x48050C1C
-+#define VENC_FLENS 0x48050C20
-+#define VENC_HFLTR_CTRL 0x48050C24
-+#define VENC_CC_CARR_WSS_CARR 0x48050C28
-+#define VENC_C_PHASE 0x48050C2C
-+#define VENC_GAIN_U 0x48050C30
-+#define VENC_GAIN_V 0x48050C34
-+#define VENC_GAIN_Y 0x48050C38
-+#define VENC_BLACK_LEVEL 0x48050C3C
-+#define VENC_BLANK_LEVEL 0x48050C40
-+#define VENC_X_COLOR 0x48050C44
-+#define VENC_M_CONTROL 0x48050C48
-+#define VENC_BSTAMP_WSS_DATA 0x48050C4C
-+#define VENC_S_CARR 0x48050C50
-+#define VENC_LINE21 0x48050C54
-+#define VENC_LN_SEL 0x48050C58
-+#define VENC_L21__WC_CTL 0x48050C5C
-+#define VENC_HTRIGGER_VTRIGGER 0x48050C60
-+#define VENC_SAVID__EAVID 0x48050C64
-+#define VENC_FLEN__FAL 0x48050C68
-+#define VENC_LAL__PHASE_RESET 0x48050C6C
-+#define VENC_HS_INT_START_STOP_X 0x48050C70
-+#define VENC_HS_EXT_START_STOP_X 0x48050C74
-+#define VENC_VS_INT_START_X 0x48050C78
-+#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x48050C7C
-+#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x48050C80
-+#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x48050C84
-+#define VENC_VS_EXT_STOP_Y 0x48050C88
-+#define VENC_AVID_START_STOP_X 0x48050C90
-+#define VENC_AVID_START_STOP_Y 0x48050C94
-+#define VENC_FID_INT_START_X__FID_INT_START_Y 0x48050CA0
-+#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0x48050CA4
-+#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0x48050CA8
-+#define VENC_TVDETGP_INT_START_STOP_X 0x48050CB0
-+#define VENC_TVDETGP_INT_START_STOP_Y 0x48050CB4
-+#define VENC_GEN_CTRL 0x48050CB8
-+#define VENC_OUTPUT_CONTROL 0x48050CC4
-+#define VENC_DAC_B__DAC_C 0x48050CC8
-+
-+/* DSS register addresses */
-+#define DSS_SYSCONFIG 0x48050010
-+#define DSS_CONTROL 0x48050040
-+
-+/* DISPC register addresses */
-+#define DISPC_SYSCONFIG 0x48050410
-+#define DISPC_SYSSTATUS 0x48050414
-+#define DISPC_CONTROL 0x48050440
-+#define DISPC_CONFIG 0x48050444
-+#define DISPC_DEFAULT_COLOR0 0x4805044c
-+#define DISPC_DEFAULT_COLOR1 0x48050450
-+#define DISPC_TRANS_COLOR0 0x48050454
-+#define DISPC_TRANS_COLOR1 0x48050458
-+#define DISPC_TIMING_H 0x48050464
-+#define DISPC_TIMING_V 0x48050468
-+#define DISPC_POL_FREQ 0x4805046c
-+#define DISPC_DIVISOR 0x48050470
-+#define DISPC_SIZE_DIG 0x48050478
-+#define DISPC_SIZE_LCD 0x4805047c
-+
-+/* Few Register Offsets */
-+#define FRAME_MODE_OFFSET 1
-+#define TFTSTN_OFFSET 3
-+#define DATALINES_OFFSET 8
-+
-+/* Enabling Display controller */
-+#define LCD_ENABLE 1
-+#define DIG_ENABLE (1 << 1)
-+#define GO_LCD (1 << 5)
-+#define GO_DIG (1 << 6)
-+#define GP_OUT0 (1 << 15)
-+#define GP_OUT1 (1 << 16)
-+
-+#define DISPC_ENABLE (LCD_ENABLE | \
-+ DIG_ENABLE | \
-+ GO_LCD | \
-+ GO_DIG | \
-+ GP_OUT0| \
-+ GP_OUT1)
-+/* Configure VENC DSS Params */
-+#define VENC_CLK_ENABLE (1 << 3)
-+#define DAC_DEMEN (1 << 4)
-+#define DAC_POWERDN (1 << 5)
-+#define VENC_OUT_SEL (1 << 6)
-+
-+#define VENC_DSS_CONFIG (VENC_CLK_ENABLE | \
-+ DAC_DEMEN | \
-+ DAC_POWERDN | \
-+ VENC_OUT_SEL)
-+
-+struct venc_config {
-+ u32 status;
-+ u32 f_control;
-+ u32 vidout_ctrl;
-+ u32 sync_ctrl;
-+ u32 llen;
-+ u32 flens;
-+ u32 hfltr_ctrl;
-+ u32 cc_carr_wss_carr;
-+ u32 c_phase;
-+ u32 gain_u;
-+ u32 gain_v;
-+ u32 gain_y;
-+ u32 black_level;
-+ u32 blank_level;
-+ u32 x_color;
-+ u32 m_control;
-+ u32 bstamp_wss_data;
-+ u32 s_carr;
-+ u32 line21;
-+ u32 ln_sel;
-+ u32 l21__wc_ctl;
-+ u32 htrigger_vtrigger;
-+ u32 savid__eavid;
-+ u32 flen__fal;
-+ u32 lal__phase_reset;
-+ u32 hs_int_start_stop_x;
-+ u32 hs_ext_start_stop_x;
-+ u32 vs_int_start_x;
-+ u32 vs_int_stop_x__vs_int_start_y;
-+ u32 vs_int_stop_y__vs_ext_start_x;
-+ u32 vs_ext_stop_x__vs_ext_start_y;
-+ u32 vs_ext_stop_y;
-+ u32 avid_start_stop_x;
-+ u32 avid_start_stop_y;
-+ u32 fid_int_start_x__fid_int_start_y;
-+ u32 fid_int_offset_y__fid_ext_start_x;
-+ u32 fid_ext_start_y__fid_ext_offset_y;
-+ u32 tvdetgp_int_start_stop_x;
-+ u32 tvdetgp_int_start_stop_y;
-+ u32 gen_ctrl;
-+ u32 output_control;
-+ u32 dac_b__dac_c;
-+ u32 height_width;
-+};
-+
-+struct panel_config {
-+ u32 timing_h;
-+ u32 timing_v;
-+ u32 pol_freq;
-+ u32 divisor;
-+ u32 lcd_size;
-+ u32 panel_type;
-+ u32 data_lines;
-+ u32 load_mode;
-+};
-+
-+static inline void dss_write_reg(int reg, u32 val)
-+{
-+ __raw_writel(val, reg);
-+}
-+
-+static inline u32 dss_read_reg(int reg)
-+{
-+ u32 l = __raw_readl(reg);
-+ return l;
-+}
-+
-+#endif /* DSS_H */
-diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
-index ff6d432..2c15df9 100644
---- a/include/configs/omap3_beagle.h
-+++ b/include/configs/omap3_beagle.h
-@@ -120,6 +120,7 @@
- #define CONFIG_CMD_I2C /* I2C serial bus support */
- #define CONFIG_CMD_MMC /* MMC support */
- #define CONFIG_CMD_NAND /* NAND support */
-+#define CONFIG_VIDEO_OMAP3 /* DSS Support */
-
- #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
- #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
---
-1.5.6.3
-
---0016e64cc3d48ed9db047ca903b2
-Content-Type: text/plain; charset=ISO-8859-1
-
---
-You received this message because you are subscribed to the Google Groups "Beagle Board" group.
-To post to this group, send email to beagleboard@googlegroups.com.
-To unsubscribe from this group, send email to beagleboard+unsubscribe@googlegroups.com.
-For more options, visit this group at http://groups.google.com/group/beagleboard?hl=en.
-
-
-
---0016e64cc3d48ed9db047ca903b2--
+From 6f539e0a265bbf009c35ca7474454aa2306fdd1a Mon Sep 17 00:00:00 2001
+From: Syed Mohammed Khasim <khasim@ti.com>
+Date: Sun, 28 Mar 2010 22:03:30 +0200
+Subject: [PATCH] Minimal Display driver for OMAP3
+
+Supports dynamic configuration of Panel and Video Encoder
+Supports Background color on DVID
+Supports Color bar on S-Video
+
+Signed-off-by: Syed Mohammed Khasim <khasim@ti.com>
+---
+ board/ti/beagle/beagle.c | 13 +++
+ board/ti/beagle/beagle.h | 73 ++++++++++++++
+ drivers/video/Makefile | 1 +
+ drivers/video/omap3_dss.c | 128 +++++++++++++++++++++++++
+ include/asm-arm/arch-omap3/dss.h | 193 ++++++++++++++++++++++++++++++++++++++
+ include/configs/omap3_beagle.h | 1 +
+ 6 files changed, 409 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/video/omap3_dss.c
+ create mode 100644 include/asm-arm/arch-omap3/dss.h
+
+diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
+index 8c5b88c..b6ddc8e 100644
+--- a/board/ti/beagle/beagle.c
++++ b/board/ti/beagle/beagle.c
+@@ -141,6 +141,17 @@ unsigned int get_expansion_id(void)
+ }
+
+ /*
++ * Configure DSS to display background color on DVID
++ * Configure VENC to display color bar on S-Video
++ */
++void display_init(void)
++{
++ omap3_dss_venc_config(&venc_config_std_tv);
++ omap3_dss_panel_config(&dvid_cfg);
++ omap3_dss_set_background_col(DVI_BEAGLE_ORANGE_COL);
++}
++
++/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+@@ -149,6 +160,7 @@ int misc_init_r(void)
+ struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+ struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
+
++ display_init();
+ beagle_identify();
+ switch (get_expansion_id()) {
+ case TINCANTOOLS_ZIPPY:
+@@ -185,6 +197,7 @@ int misc_init_r(void)
+
+ twl4030_power_init();
+ twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
++ omap3_dss_enable();
+
+ switch (beagle_revision) {
+ case REVISION_AXBX:
+diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
+index ec4f831..8ceea61 100644
+--- a/board/ti/beagle/beagle.h
++++ b/board/ti/beagle/beagle.h
+@@ -23,6 +23,8 @@
+ #ifndef _BEAGLE_H_
+ #define _BEAGLE_H_
+
++#include <asm/arch/dss.h>
++
+ const omap3_sysinfo sysinfo = {
+ DDR_STACKED,
+ "OMAP3 Beagle board",
+@@ -433,4 +435,75 @@ const omap3_sysinfo sysinfo = {
+ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
+
++/*
++ * Display Configuration
++ */
++
++#define DVI_BEAGLE_ORANGE_COL 0x00FF8000
++
++/*
++ * Configure VENC in DSS for Beagle to generate Color Bar
++ *
++ * Kindly refer to OMAP TRM for definition of these values.
++ */
++static const struct venc_config venc_config_std_tv = {
++ .status = 0x0000001B,
++ .f_control = 0x00000040,
++ .vidout_ctrl = 0x00000000,
++ .sync_ctrl = 0x00008000,
++ .llen = 0x00008359,
++ .flens = 0x0000020C,
++ .hfltr_ctrl = 0x00000000,
++ .cc_carr_wss_carr = 0x043F2631,
++ .c_phase = 0x00000024,
++ .gain_u = 0x00000130,
++ .gain_v = 0x00000198,
++ .gain_y = 0x000001C0,
++ .black_level = 0x0000006A,
++ .blank_level = 0x0000005C,
++ .x_color = 0x00000000,
++ .m_control = 0x00000001,
++ .bstamp_wss_data = 0x0000003F,
++ .s_carr = 0x21F07C1F,
++ .line21 = 0x00000000,
++ .ln_sel = 0x00000015,
++ .l21__wc_ctl = 0x00001400,
++ .htrigger_vtrigger = 0x00000000,
++ .savid__eavid = 0x069300F4,
++ .flen__fal = 0x0016020C,
++ .lal__phase_reset = 0x00060107,
++ .hs_int_start_stop_x = 0x008D034E,
++ .hs_ext_start_stop_x = 0x000F0359,
++ .vs_int_start_x = 0x01A00000,
++ .vs_int_stop_x__vs_int_start_y = 0x020501A0,
++ .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
++ .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
++ .vs_ext_stop_y = 0x00000006,
++ .avid_start_stop_x = 0x03480079,
++ .avid_start_stop_y = 0x02040024,
++ .fid_int_start_x__fid_int_start_y = 0x0001008A,
++ .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
++ .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
++ .tvdetgp_int_start_stop_x = 0x00140001,
++ .tvdetgp_int_start_stop_y = 0x00010001,
++ .gen_ctrl = 0x00FF0000,
++ .output_control = 0x0000000D,
++ .dac_b__dac_c = 0x00000000,
++ .height_width = 0x00ef027f
++};
++
++/*
++ * Configure Timings for DVI D
++ */
++static const struct panel_config dvid_cfg = {
++ .timing_h = 0x0ff03f31, /* Horizantal timing */
++ .timing_v = 0x01400504, /* Vertical timing */
++ .pol_freq = 0x00007028, /* Pol Freq */
++ .divisor = 0x00010006, /* 72Mhz Pixel Clock */
++ .lcd_size = 0x02ff03ff, /* 1024x768 */
++ .panel_type = 0x01, /* TFT */
++ .data_lines = 0x03, /* 24 Bit RGB */
++ .load_mode = 0x02 /* Frame Mode */
++};
++
+ #endif
+diff --git a/drivers/video/Makefile b/drivers/video/Makefile
+index a5e339a..44d7ae8 100644
+--- a/drivers/video/Makefile
++++ b/drivers/video/Makefile
+@@ -38,6 +38,7 @@ COBJS-$(CONFIG_SED156X) += sed156x.o
+ COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
+ COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o
+ COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
++COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
+ COBJS-y += videomodes.o
+
+ COBJS := $(COBJS-y)
+diff --git a/drivers/video/omap3_dss.c b/drivers/video/omap3_dss.c
+new file mode 100644
+index 0000000..2ead7b9
+--- /dev/null
++++ b/drivers/video/omap3_dss.c
+@@ -0,0 +1,128 @@
++/*
++ * (C) Copyright 2010
++ * Texas Instruments, <www.ti.com>
++ * Syed Mohammed Khasim <khasim@ti.com>
++ *
++ * Referred to Linux DSS driver files for OMAP3
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation's version 2 of
++ * the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/io.h>
++#include <asm/arch/dss.h>
++
++/*
++ * VENC configuration
++ */
++void omap3_dss_venc_config(const struct venc_config *venc_cfg)
++{
++ dss_write_reg(VENC_STATUS, venc_cfg->status);
++ dss_write_reg(VENC_F_CONTROL, venc_cfg->f_control);
++ dss_write_reg(VENC_VIDOUT_CTRL, venc_cfg->vidout_ctrl);
++ dss_write_reg(VENC_SYNC_CTRL, venc_cfg->sync_ctrl);
++ dss_write_reg(VENC_LLEN, venc_cfg->llen);
++ dss_write_reg(VENC_FLENS, venc_cfg->flens);
++ dss_write_reg(VENC_HFLTR_CTRL, venc_cfg->hfltr_ctrl);
++ dss_write_reg(VENC_CC_CARR_WSS_CARR, venc_cfg->cc_carr_wss_carr);
++ dss_write_reg(VENC_C_PHASE, venc_cfg->c_phase);
++ dss_write_reg(VENC_GAIN_U, venc_cfg->gain_u);
++ dss_write_reg(VENC_GAIN_V, venc_cfg->gain_v);
++ dss_write_reg(VENC_GAIN_Y, venc_cfg->gain_y);
++ dss_write_reg(VENC_BLACK_LEVEL, venc_cfg->black_level);
++ dss_write_reg(VENC_BLANK_LEVEL, venc_cfg->blank_level);
++ dss_write_reg(VENC_X_COLOR, venc_cfg->x_color);
++ dss_write_reg(VENC_M_CONTROL, venc_cfg->m_control);
++ dss_write_reg(VENC_BSTAMP_WSS_DATA, venc_cfg->bstamp_wss_data);
++ dss_write_reg(VENC_S_CARR, venc_cfg->s_carr);
++ dss_write_reg(VENC_LINE21, venc_cfg->line21);
++ dss_write_reg(VENC_LN_SEL, venc_cfg->ln_sel);
++ dss_write_reg(VENC_L21__WC_CTL, venc_cfg->l21__wc_ctl);
++ dss_write_reg(VENC_HTRIGGER_VTRIGGER, venc_cfg->htrigger_vtrigger);
++ dss_write_reg(VENC_SAVID__EAVID, venc_cfg->savid__eavid);
++ dss_write_reg(VENC_FLEN__FAL, venc_cfg->flen__fal);
++ dss_write_reg(VENC_LAL__PHASE_RESET, venc_cfg->lal__phase_reset);
++ dss_write_reg(VENC_HS_INT_START_STOP_X,
++ venc_cfg->hs_int_start_stop_x);
++ dss_write_reg(VENC_HS_EXT_START_STOP_X,
++ venc_cfg->hs_ext_start_stop_x);
++ dss_write_reg(VENC_VS_INT_START_X, venc_cfg->vs_int_start_x);
++ dss_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
++ venc_cfg->vs_int_stop_x__vs_int_start_y);
++ dss_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
++ venc_cfg->vs_int_stop_y__vs_ext_start_x);
++ dss_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
++ venc_cfg->vs_ext_stop_x__vs_ext_start_y);
++ dss_write_reg(VENC_VS_EXT_STOP_Y, venc_cfg->vs_ext_stop_y);
++ dss_write_reg(VENC_AVID_START_STOP_X, venc_cfg->avid_start_stop_x);
++ dss_write_reg(VENC_AVID_START_STOP_Y, venc_cfg->avid_start_stop_y);
++ dss_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
++ venc_cfg->fid_int_start_x__fid_int_start_y);
++ dss_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
++ venc_cfg->fid_int_offset_y__fid_ext_start_x);
++ dss_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
++ venc_cfg->fid_ext_start_y__fid_ext_offset_y);
++ dss_write_reg(VENC_TVDETGP_INT_START_STOP_X,
++ venc_cfg->tvdetgp_int_start_stop_x);
++ dss_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
++ venc_cfg->tvdetgp_int_start_stop_y);
++ dss_write_reg(VENC_GEN_CTRL, venc_cfg->gen_ctrl);
++ dss_write_reg(VENC_OUTPUT_CONTROL, venc_cfg->output_control);
++ dss_write_reg(VENC_DAC_B__DAC_C, venc_cfg->dac_b__dac_c);
++ dss_write_reg(DISPC_SIZE_DIG, venc_cfg->height_width);
++ dss_write_reg(DSS_CONTROL, VENC_DSS_CONFIG);
++}
++
++/*
++ * Configure Panel Specific parameters
++ */
++void omap3_dss_panel_config(const struct panel_config *panel_cfg)
++{
++ dss_write_reg(DISPC_TIMING_H, panel_cfg->timing_h);
++ dss_write_reg(DISPC_TIMING_V, panel_cfg->timing_v);
++ dss_write_reg(DISPC_POL_FREQ, panel_cfg->pol_freq);
++ dss_write_reg(DISPC_DIVISOR, panel_cfg->divisor);
++ dss_write_reg(DISPC_SIZE_LCD, panel_cfg->lcd_size);
++ dss_write_reg(DISPC_CONFIG,
++ (panel_cfg->load_mode << FRAME_MODE_OFFSET));
++ dss_write_reg(DISPC_CONTROL,
++ ((panel_cfg->panel_type << TFTSTN_OFFSET) |
++ (panel_cfg->data_lines << DATALINES_OFFSET)));
++}
++
++/*
++ * Enable LCD and DIGITAL OUT in DSS
++ */
++void omap3_dss_enable(void)
++{
++ u32 l = 0;
++
++ l = dss_read_reg(DISPC_CONTROL);
++ l |= DISPC_ENABLE;
++
++ dss_write_reg(DISPC_CONTROL, l);
++}
++
++/*
++ * Set Background Color in DISPC
++ */
++void omap3_dss_set_background_col(u32 color)
++{
++ dss_write_reg(DISPC_DEFAULT_COLOR0, color);
++}
+diff --git a/include/asm-arm/arch-omap3/dss.h b/include/asm-arm/arch-omap3/dss.h
+new file mode 100644
+index 0000000..08c7d8d
+--- /dev/null
++++ b/include/asm-arm/arch-omap3/dss.h
+@@ -0,0 +1,193 @@
++/*
++ * (C) Copyright 2010
++ * Texas Instruments, <www.ti.com>
++ * Syed Mohammed Khasim <khasim@ti.com>
++ *
++ * Referred to Linux DSS driver files for OMAP3
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation's version 2 of
++ * the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef DSS_H
++#define DSS_H
++
++/* VENC Register address */
++#define VENC_REV_ID 0x48050C00
++#define VENC_STATUS 0x48050C04
++#define VENC_F_CONTROL 0x48050C08
++#define VENC_VIDOUT_CTRL 0x48050C10
++#define VENC_SYNC_CTRL 0x48050C14
++#define VENC_LLEN 0x48050C1C
++#define VENC_FLENS 0x48050C20
++#define VENC_HFLTR_CTRL 0x48050C24
++#define VENC_CC_CARR_WSS_CARR 0x48050C28
++#define VENC_C_PHASE 0x48050C2C
++#define VENC_GAIN_U 0x48050C30
++#define VENC_GAIN_V 0x48050C34
++#define VENC_GAIN_Y 0x48050C38
++#define VENC_BLACK_LEVEL 0x48050C3C
++#define VENC_BLANK_LEVEL 0x48050C40
++#define VENC_X_COLOR 0x48050C44
++#define VENC_M_CONTROL 0x48050C48
++#define VENC_BSTAMP_WSS_DATA 0x48050C4C
++#define VENC_S_CARR 0x48050C50
++#define VENC_LINE21 0x48050C54
++#define VENC_LN_SEL 0x48050C58
++#define VENC_L21__WC_CTL 0x48050C5C
++#define VENC_HTRIGGER_VTRIGGER 0x48050C60
++#define VENC_SAVID__EAVID 0x48050C64
++#define VENC_FLEN__FAL 0x48050C68
++#define VENC_LAL__PHASE_RESET 0x48050C6C
++#define VENC_HS_INT_START_STOP_X 0x48050C70
++#define VENC_HS_EXT_START_STOP_X 0x48050C74
++#define VENC_VS_INT_START_X 0x48050C78
++#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x48050C7C
++#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x48050C80
++#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x48050C84
++#define VENC_VS_EXT_STOP_Y 0x48050C88
++#define VENC_AVID_START_STOP_X 0x48050C90
++#define VENC_AVID_START_STOP_Y 0x48050C94
++#define VENC_FID_INT_START_X__FID_INT_START_Y 0x48050CA0
++#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0x48050CA4
++#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0x48050CA8
++#define VENC_TVDETGP_INT_START_STOP_X 0x48050CB0
++#define VENC_TVDETGP_INT_START_STOP_Y 0x48050CB4
++#define VENC_GEN_CTRL 0x48050CB8
++#define VENC_OUTPUT_CONTROL 0x48050CC4
++#define VENC_DAC_B__DAC_C 0x48050CC8
++
++/* DSS register addresses */
++#define DSS_SYSCONFIG 0x48050010
++#define DSS_CONTROL 0x48050040
++
++/* DISPC register addresses */
++#define DISPC_SYSCONFIG 0x48050410
++#define DISPC_SYSSTATUS 0x48050414
++#define DISPC_CONTROL 0x48050440
++#define DISPC_CONFIG 0x48050444
++#define DISPC_DEFAULT_COLOR0 0x4805044c
++#define DISPC_DEFAULT_COLOR1 0x48050450
++#define DISPC_TRANS_COLOR0 0x48050454
++#define DISPC_TRANS_COLOR1 0x48050458
++#define DISPC_TIMING_H 0x48050464
++#define DISPC_TIMING_V 0x48050468
++#define DISPC_POL_FREQ 0x4805046c
++#define DISPC_DIVISOR 0x48050470
++#define DISPC_SIZE_DIG 0x48050478
++#define DISPC_SIZE_LCD 0x4805047c
++
++/* Few Register Offsets */
++#define FRAME_MODE_OFFSET 1
++#define TFTSTN_OFFSET 3
++#define DATALINES_OFFSET 8
++
++/* Enabling Display controller */
++#define LCD_ENABLE 1
++#define DIG_ENABLE (1 << 1)
++#define GO_LCD (1 << 5)
++#define GO_DIG (1 << 6)
++#define GP_OUT0 (1 << 15)
++#define GP_OUT1 (1 << 16)
++
++#define DISPC_ENABLE (LCD_ENABLE | \
++ DIG_ENABLE | \
++ GO_LCD | \
++ GO_DIG | \
++ GP_OUT0| \
++ GP_OUT1)
++/* Configure VENC DSS Params */
++#define VENC_CLK_ENABLE (1 << 3)
++#define DAC_DEMEN (1 << 4)
++#define DAC_POWERDN (1 << 5)
++#define VENC_OUT_SEL (1 << 6)
++
++#define VENC_DSS_CONFIG (VENC_CLK_ENABLE | \
++ DAC_DEMEN | \
++ DAC_POWERDN | \
++ VENC_OUT_SEL)
++
++struct venc_config {
++ u32 status;
++ u32 f_control;
++ u32 vidout_ctrl;
++ u32 sync_ctrl;
++ u32 llen;
++ u32 flens;
++ u32 hfltr_ctrl;
++ u32 cc_carr_wss_carr;
++ u32 c_phase;
++ u32 gain_u;
++ u32 gain_v;
++ u32 gain_y;
++ u32 black_level;
++ u32 blank_level;
++ u32 x_color;
++ u32 m_control;
++ u32 bstamp_wss_data;
++ u32 s_carr;
++ u32 line21;
++ u32 ln_sel;
++ u32 l21__wc_ctl;
++ u32 htrigger_vtrigger;
++ u32 savid__eavid;
++ u32 flen__fal;
++ u32 lal__phase_reset;
++ u32 hs_int_start_stop_x;
++ u32 hs_ext_start_stop_x;
++ u32 vs_int_start_x;
++ u32 vs_int_stop_x__vs_int_start_y;
++ u32 vs_int_stop_y__vs_ext_start_x;
++ u32 vs_ext_stop_x__vs_ext_start_y;
++ u32 vs_ext_stop_y;
++ u32 avid_start_stop_x;
++ u32 avid_start_stop_y;
++ u32 fid_int_start_x__fid_int_start_y;
++ u32 fid_int_offset_y__fid_ext_start_x;
++ u32 fid_ext_start_y__fid_ext_offset_y;
++ u32 tvdetgp_int_start_stop_x;
++ u32 tvdetgp_int_start_stop_y;
++ u32 gen_ctrl;
++ u32 output_control;
++ u32 dac_b__dac_c;
++ u32 height_width;
++};
++
++struct panel_config {
++ u32 timing_h;
++ u32 timing_v;
++ u32 pol_freq;
++ u32 divisor;
++ u32 lcd_size;
++ u32 panel_type;
++ u32 data_lines;
++ u32 load_mode;
++};
++
++static inline void dss_write_reg(int reg, u32 val)
++{
++ __raw_writel(val, reg);
++}
++
++static inline u32 dss_read_reg(int reg)
++{
++ u32 l = __raw_readl(reg);
++ return l;
++}
++
++#endif /* DSS_H */
+diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
+index c156cea..a3092ef 100644
+--- a/include/configs/omap3_beagle.h
++++ b/include/configs/omap3_beagle.h
+@@ -131,6 +131,7 @@
+ #define CONFIG_CMD_I2C /* I2C serial bus support */
+ #define CONFIG_CMD_MMC /* MMC support */
+ #define CONFIG_CMD_NAND /* NAND support */
++#define CONFIG_VIDEO_OMAP3 /* DSS Support */
+
+ #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+ #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+--
+1.6.6.1
+
diff --git a/recipes/u-boot/u-boot-git/beagleboard/0001-omap3-clock.c-don-t-reprogram-clocks-when-trying-to-.patch b/recipes/u-boot/u-boot-git/beagleboard/0001-omap3-clock.c-don-t-reprogram-clocks-when-trying-to-.patch
deleted file mode 100644
index eead4b9d7c..0000000000
--- a/recipes/u-boot/u-boot-git/beagleboard/0001-omap3-clock.c-don-t-reprogram-clocks-when-trying-to-.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From 0c597fe20bab64deca7d71e7da6c0a7e553a2a7b Mon Sep 17 00:00:00 2001
-From: Koen Kooi <koen@dominion.thruhere.net>
-Date: Thu, 18 Feb 2010 11:05:49 +0100
-Subject: [PATCH 1/2] omap3 clock.c: don't reprogram clocks when trying to find out clock divider
-
----
- cpu/arm_cortexa8/omap3/clock.c | 14 +++++++++-----
- 1 files changed, 9 insertions(+), 5 deletions(-)
-
-diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c
-index d67517a..40bd679 100644
---- a/cpu/arm_cortexa8/omap3/clock.c
-+++ b/cpu/arm_cortexa8/omap3/clock.c
-@@ -40,17 +40,19 @@
- *****************************************************************************/
- u32 get_osc_clk_speed(void)
- {
-- u32 start, cstart, cend, cdiff, val;
-+ u32 start, cstart, cend, cdiff, cdiv, val;
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- struct prm *prm_base = (struct prm *)PRM_BASE;
- struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
- struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
-
- val = readl(&prm_base->clksrc_ctrl);
--
-- /* If SYS_CLK is being divided by 2, remove for now */
-- val = (val & (~SYSCLKDIV_2)) | SYSCLKDIV_1;
-- writel(val, &prm_base->clksrc_ctrl);
-+ if (val & SYSCLKDIV_2)
-+ cdiv = 2;
-+ else if (val & SYSCLKDIV_1)
-+ cdiv = 1;
-+ else
-+ cdiv = 1;
-
- /* enable timer2 */
- val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
-@@ -83,6 +85,8 @@ u32 get_osc_clk_speed(void)
- cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */
- cdiff = cend - cstart; /* get elapsed ticks */
-
-+ cdiff *= cdiv;
-+
- /* based on number of ticks assign speed */
- if (cdiff > 19000)
- return S38_4M;
---
-1.6.6.1
-
diff --git a/recipes/u-boot/u-boot-git/beagleboard/0002-beagleboard-add-pinmuxing-for-beagleboard-XM.patch b/recipes/u-boot/u-boot-git/beagleboard/0002-beagleboard-add-pinmuxing-for-beagleboard-XM.patch
deleted file mode 100644
index fe014084d8..0000000000
--- a/recipes/u-boot/u-boot-git/beagleboard/0002-beagleboard-add-pinmuxing-for-beagleboard-XM.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From 8698ae8de6be63c35d8816e78b0e53c6a4b74933 Mon Sep 17 00:00:00 2001
-From: Koen Kooi <koen@dominion.thruhere.net>
-Date: Thu, 18 Feb 2010 11:19:50 +0100
-Subject: [PATCH 2/2] beagleboard: add pinmuxing for beagleboard XM
-
----
- board/ti/beagle/beagle.c | 16 ++++++++++++++--
- board/ti/beagle/beagle.h | 20 ++++++++++++++++++++
- 2 files changed, 34 insertions(+), 2 deletions(-)
-
-diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
-index 1d91c76..8b5243b 100644
---- a/board/ti/beagle/beagle.c
-+++ b/board/ti/beagle/beagle.c
-@@ -182,6 +182,18 @@ void set_muxconf_regs(void)
- {
- MUX_BEAGLE();
-
-- if (beagle_revision != REVISION_AXBX)
-- MUX_BEAGLE_C();
-+ switch(beagle_revision) {
-+ case REVISION_AXBX:
-+ break;
-+ case REVISION_CX:
-+ MUX_BEAGLE_C();
-+ break;
-+ case REVISION_C4:
-+ MUX_BEAGLE_C();
-+ break;
-+ case REVISION_XM:
-+ MUX_BEAGLE_C();
-+ MUX_BEAGLE_XM();
-+ break;
-+ }
- }
-diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
-index db17160..adf8c5a 100644
---- a/board/ti/beagle/beagle.h
-+++ b/board/ti/beagle/beagle.h
-@@ -387,6 +387,26 @@ const omap3_sysinfo sysinfo = {
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/
-
-+#define MUX_BEAGLE_XM() \
-+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
-+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
-+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
-+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
-+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
-+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M7)) /*safe_mode*/\
-+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
-+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
-+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
-+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
-+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
-+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
-+ MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
-+ MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
-+ MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
-+ MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
-+ MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
-+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/
-+
- /*
- * Display Configuration
- */
---
-1.6.6.1
-
diff --git a/recipes/u-boot/u-boot-git/beagleboard/0003-beagleboard-move-muxing-into-revision-print-switch.patch b/recipes/u-boot/u-boot-git/beagleboard/0003-beagleboard-move-muxing-into-revision-print-switch.patch
deleted file mode 100644
index 3750cf8990..0000000000
--- a/recipes/u-boot/u-boot-git/beagleboard/0003-beagleboard-move-muxing-into-revision-print-switch.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 24e335a1457da32a1d79621d3a24462d6fb96853 Mon Sep 17 00:00:00 2001
-From: Koen Kooi <koen@dominion.thruhere.net>
-Date: Thu, 18 Feb 2010 11:55:26 +0100
-Subject: [PATCH] beagleboard: move muxing into revision print switch()
-
----
- board/ti/beagle/beagle.c | 19 ++++---------------
- 1 files changed, 4 insertions(+), 15 deletions(-)
-
-diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
-index 8b5243b..8fac6b2 100644
---- a/board/ti/beagle/beagle.c
-+++ b/board/ti/beagle/beagle.c
-@@ -101,12 +101,16 @@ void beagle_identify(void)
- break;
- case REVISION_CX:
- printf("C1/C2/C3\n");
-+ MUX_BEAGLE_C();
- break;
- case REVISION_C4:
- printf("C4\n");
-+ MUX_BEAGLE_C();
- break;
- case REVISION_XM:
- printf("XM\n");
-+ MUX_BEAGLE_C();
-+ MUX_BEAGLE_XM();
- break;
- default:
- printf("unknown 0x%02x\n", beagle_revision);
-@@ -181,19 +185,4 @@ int misc_init_r(void)
- void set_muxconf_regs(void)
- {
- MUX_BEAGLE();
--
-- switch(beagle_revision) {
-- case REVISION_AXBX:
-- break;
-- case REVISION_CX:
-- MUX_BEAGLE_C();
-- break;
-- case REVISION_C4:
-- MUX_BEAGLE_C();
-- break;
-- case REVISION_XM:
-- MUX_BEAGLE_C();
-- MUX_BEAGLE_XM();
-- break;
-- }
- }
---
-1.6.6.1
-
diff --git a/recipes/u-boot/u-boot-git/beagleboard/720MHz.patch b/recipes/u-boot/u-boot-git/beagleboard/720MHz.patch
deleted file mode 100644
index c50e0bd793..0000000000
--- a/recipes/u-boot/u-boot-git/beagleboard/720MHz.patch
+++ /dev/null
@@ -1,166 +0,0 @@
-From bba669562fa208d12f4c7cd8188446e8576cd6ee Mon Sep 17 00:00:00 2001
-From: Syed Mohammed Khasim <khasim@ti.com>
-Date: Fri, 8 Jan 2010 20:34:37 +0530
-Subject: [PATCH] Support 720Mhz configuration for OMAP35xx
-
-Adds a new API "twl4030_pmrecv_vsel_cfg" to select voltage and group
-Adds support for 720Mhz in clock.c
-Board file modified to use these new APIs and boot at 720Mhz
-
-Signed-off-by: Syed Mohammed Khasim <khasim@ti.com>
----
- board/ti/beagle/beagle.c | 20 ++++++++++++++++++--
- cpu/arm_cortexa8/omap3/clock.c | 21 +++++++++++++++++++++
- drivers/power/twl4030.c | 24 +++++++++++++++---------
- include/twl4030.h | 16 ++++++++++++++++
- 4 files changed, 70 insertions(+), 11 deletions(-)
-
-diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
-index 0def5a6..7985ee9 100644
---- a/board/ti/beagle/beagle.c
-+++ b/board/ti/beagle/beagle.c
-@@ -122,9 +122,27 @@ int misc_init_r(void)
- struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
- struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
-
-+ beagle_identify();
-+
- twl4030_power_init();
- twl4030_led_init();
-
-+ if ((beagle_revision == REVISION_C4) || (beagle_revision == REVISION_XM)) {
-+
-+ /* Select TWL4030 VSEL to support 720Mhz */
-+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
-+ VAUX2_VSEL_18,
-+ TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
-+ DEV_GRP_P1);
-+
-+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VDD1_VSEL,
-+ VDD1_VSEL_14,
-+ TWL4030_PM_RECEIVER_VDD1_DEV_GRP,
-+ DEV_GRP_P1);
-+
-+ prcm_config_720mhz();
-+ }
-+
- /* Configure GPIOs to output */
- writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
- writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
-@@ -136,8 +154,6 @@ int misc_init_r(void)
- writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
- GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
-
-- beagle_identify();
--
- dieid_num_r();
-
- return 0;
-diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c
-index 174c453..d67517a 100644
---- a/cpu/arm_cortexa8/omap3/clock.c
-+++ b/cpu/arm_cortexa8/omap3/clock.c
-@@ -402,3 +402,24 @@ void per_clocks_enable(void)
-
- sdelay(1000);
- }
-+
-+/*
-+ * Configure PRCM registers to get 720 Mhz
-+ *
-+ * NOTE: N value doesn't change, only M gets affected
-+ */
-+void prcm_config_720mhz(void)
-+{
-+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-+
-+ /* Unlock MPU DPLL (slows things down, and needed later) */
-+ sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
-+ wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, LDELAY);
-+
-+ /* Set M */
-+ sr32(&prcm_base->clksel1_pll_mpu, 8, 11, 0x2D0);
-+
-+ /* lock mode */
-+ sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
-+ wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, LDELAY);
-+}
-diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c
-index eb066cb..d68e515 100644
---- a/drivers/power/twl4030.c
-+++ b/drivers/power/twl4030.c
-@@ -59,16 +59,9 @@ void twl4030_power_reset_init(void)
- }
- }
-
--
- /*
- * Power Init
- */
--#define DEV_GRP_P1 0x20
--#define VAUX3_VSEL_28 0x03
--#define DEV_GRP_ALL 0xE0
--#define VPLL2_VSEL_18 0x05
--#define VDAC_VSEL_18 0x03
--
- void twl4030_power_init(void)
- {
- unsigned char byte;
-@@ -98,8 +91,6 @@ void twl4030_power_init(void)
- TWL4030_PM_RECEIVER_VDAC_DEDICATED);
- }
-
--#define VMMC1_VSEL_30 0x02
--
- void twl4030_power_mmc_init(void)
- {
- unsigned char byte;
-@@ -113,3 +104,18 @@ void twl4030_power_mmc_init(void)
- twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, byte,
- TWL4030_PM_RECEIVER_VMMC1_DEDICATED);
- }
-+
-+/*
-+ * Generic function to select Device Group and Voltage
-+ */
-+void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
-+ u8 dev_grp, u8 dev_grp_sel)
-+{
-+ /* Select the Device Group */
-+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp_sel,
-+ dev_grp);
-+
-+ /* Select the Voltage */
-+ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_val,
-+ vsel_reg);
-+}
-diff --git a/include/twl4030.h b/include/twl4030.h
-index f260ecb..b96c96c 100644
---- a/include/twl4030.h
-+++ b/include/twl4030.h
-@@ -359,6 +359,22 @@
- #define TWL4030_USB_PHY_DPLL_CLK (1 << 0)
-
- /*
-+ * Voltage Selection in PM Receiver Module
-+ */
-+#define VAUX2_VSEL_18 0x05
-+#define VDD1_VSEL_14 0x40
-+#define VAUX3_VSEL_28 0x03
-+#define VPLL2_VSEL_18 0x05
-+#define VDAC_VSEL_18 0x03
-+#define VMMC1_VSEL_30 0x02
-+
-+/*
-+ * Device Selection
-+ */
-+#define DEV_GRP_P1 0x20
-+#define DEV_GRP_ALL 0xE0
-+
-+/*
- * Convience functions to read and write from TWL4030
- *
- * chip_no is the i2c address, it must be one of the chip addresses
---
-1.5.6.3
-
diff --git a/recipes/u-boot/u-boot-git/beagleboard/i2c.patch b/recipes/u-boot/u-boot-git/beagleboard/i2c.patch
deleted file mode 100644
index e4b466af1b..0000000000
--- a/recipes/u-boot/u-boot-git/beagleboard/i2c.patch
+++ /dev/null
@@ -1,141 +0,0 @@
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-Date: Fri, 8 Jan 2010 21:08:59 +0530
-Message-ID: <a8ca84ad1001080738q6f5aeca1gd276ed5846b0db43@mail.gmail.com>
-Subject: [beagleboard] TI:OMAP: [PATCH 2/4] Enable I2C bus switching
-From: Khasim Syed Mohammed <khasim@beagleboard.org>
-To: u-boot@lists.denx.de, beagleboard@googlegroups.com
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---0016e64cc3d48ce7bb047ca8fca8
-Content-Type: text/plain; charset=ISO-8859-1
-
-From 9045377f255e8a59450a6957e63366b4963281ae Mon Sep 17 00:00:00 2001
-From: Syed Mohammed Khasim <khasim@ti.com>
-Date: Fri, 8 Jan 2010 20:20:41 +0530
-Subject: [PATCH] Enable I2C bus switching
-
-OMAP3 supports Multiple I2C channels, this patch allows
-us to use i2c dev <bus no> command to switch between busses.
-
-Signed-off-by: Syed Mohammed Khasim <khasim@ti.com>
-Acked-by: Heiko Schocher <hs@denx.de>
----
- drivers/i2c/omap24xx_i2c.c | 5 +++++
- include/configs/omap3_beagle.h | 4 ++++
- 2 files changed, 9 insertions(+), 0 deletions(-)
-
-diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
-index ff18991..e8c8184 100644
---- a/drivers/i2c/omap24xx_i2c.c
-+++ b/drivers/i2c/omap24xx_i2c.c
-@@ -435,3 +435,8 @@ int i2c_set_bus_num(unsigned int bus)
-
- return 0;
- }
-+
-+int i2c_get_bus_num(void)
-+{
-+ return (int) current_bus;
-+}
-diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
-index d1c9cd0..ff6d432 100644
---- a/include/configs/omap3_beagle.h
-+++ b/include/configs/omap3_beagle.h
-@@ -100,6 +100,10 @@
- /* DDR - I use Micron DDR */
- #define CONFIG_OMAP3_MICRON_DDR 1
-
-+/* Enable Multi Bus support for I2C */
-+#define CONFIG_I2C_MULTI_BUS 1
-+#define CONFIG_SYS_I2C_NOPROBES {0x0, 0x0}
-+
- /* commands to include */
- #include <config_cmd_default.h>
-
---
-1.5.6.3
-
---0016e64cc3d48ce7bb047ca8fca8
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-
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-
---0016e64cc3d48ce7bb047ca8fca8--
diff --git a/recipes/u-boot/u-boot-git/beagleboard/revision-detection.patch b/recipes/u-boot/u-boot-git/beagleboard/revision-detection.patch
deleted file mode 100644
index 634efda385..0000000000
--- a/recipes/u-boot/u-boot-git/beagleboard/revision-detection.patch
+++ /dev/null
@@ -1,144 +0,0 @@
-From 15fbe5ff9ee2fd2f8da4c16805d6c7ccf7244bae Mon Sep 17 00:00:00 2001
-From: Syed Mohammed Khasim <khasim@ti.com>
-Date: Fri, 8 Jan 2010 20:13:47 +0530
-Subject: [PATCH] OMAP3 Beagle Update revision detection
-
-New BeagleBoard revision C4 uses a new ID. Update revision detection.
-
-Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
-Signed-off-by: Syed Mohammed Khasim <khasim@ti.com>
----
- board/ti/beagle/beagle.c | 65 ++++++++++++++++++++++++++++-----------------
- board/ti/beagle/beagle.h | 8 ++++-
- 2 files changed, 46 insertions(+), 27 deletions(-)
-
-diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
-index 32d501e..0def5a6 100644
---- a/board/ti/beagle/beagle.c
-+++ b/board/ti/beagle/beagle.c
-@@ -38,7 +38,7 @@
- #include <asm/mach-types.h>
- #include "beagle.h"
-
--static int beagle_revision_c;
-+static int beagle_revision;
-
- /*
- * Routine: board_init
-@@ -60,41 +60,57 @@ int board_init(void)
- /*
- * Routine: beagle_get_revision
- * Description: Return the revision of the BeagleBoard this code is running on.
-- * If it is a revision Ax/Bx board, this function returns 0,
-- * on a revision C board you will get a 1.
- */
- int beagle_get_revision(void)
- {
-- return beagle_revision_c;
-+ return beagle_revision;
- }
-
- /*
- * Routine: beagle_identify
-- * Description: Detect if we are running on a Beagle revision Ax/Bx or
-- * Cx. This can be done by GPIO_171. If this is low, we are
-- * running on a revision C board.
-+ * Description: Detect if we are running on a Beagle revision Ax/Bx,
-+ * C1/2/3, C4 or D. This can be done by reading
-+ * the level of GPIO173, GPIO172 and GPIO171. This should
-+ * result in
-+ * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
-+ * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
-+ * GPIO173, GPIO172, GPIO171: 1 0 1 => C4
-+ * GPIO173, GPIO172, GPIO171: 0 0 0 => XM
- */
- void beagle_identify(void)
- {
-- beagle_revision_c = 0;
-- if (!omap_request_gpio(171)) {
-- unsigned int val;
--
-- omap_set_gpio_direction(171, 1);
-- val = omap_get_gpio_datain(171);
-- omap_free_gpio(171);
--
-- if (val)
-- beagle_revision_c = 0;
-- else
-- beagle_revision_c = 1;
-- }
-+ omap_request_gpio(171);
-+ omap_request_gpio(172);
-+ omap_request_gpio(173);
-+ omap_set_gpio_direction(171, 1);
-+ omap_set_gpio_direction(172, 1);
-+ omap_set_gpio_direction(173, 1);
-+
-+ beagle_revision = omap_get_gpio_datain(173) << 2 |
-+ omap_get_gpio_datain(172) << 1 |
-+ omap_get_gpio_datain(171);
-+ omap_free_gpio(171);
-+ omap_free_gpio(172);
-+ omap_free_gpio(173);
-
- printf("Board revision ");
-- if (beagle_revision_c)
-- printf("C\n");
-- else
-+
-+ switch (beagle_revision) {
-+ case REVISION_AXBX:
- printf("Ax/Bx\n");
-+ break;
-+ case REVISION_CX:
-+ printf("C1/C2/C3\n");
-+ break;
-+ case REVISION_C4:
-+ printf("C4\n");
-+ break;
-+ case REVISION_XM:
-+ printf("XM\n");
-+ break;
-+ default:
-+ printf("unknown 0x%02x\n", beagle_revision);
-+ }
- }
-
- /*
-@@ -137,7 +153,6 @@ void set_muxconf_regs(void)
- {
- MUX_BEAGLE();
-
-- if (beagle_revision_c) {
-+ if (beagle_revision != REVISION_AXBX)
- MUX_BEAGLE_C();
-- }
- }
-diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
-index 7fe6275..b1720c9 100644
---- a/board/ti/beagle/beagle.h
-+++ b/board/ti/beagle/beagle.h
-@@ -33,7 +33,11 @@ const omap3_sysinfo sysinfo = {
- #endif
- };
-
--#define BOARD_REVISION_MASK (0x1 << 11)
-+/* BeagleBoard revisions */
-+#define REVISION_AXBX 0x7
-+#define REVISION_CX 0x6
-+#define REVISION_C4 0x5
-+#define REVISION_XM 0x0
-
- /*
- * IEN - Input Enable
-@@ -264,7 +268,7 @@ const omap3_sysinfo sysinfo = {
- MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\
-- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI*/\
-+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTU | EN | M4)) /*GPIO_173*/\
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
- MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
- MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
---
-1.5.6.3
diff --git a/recipes/u-boot/u-boot_git.bb b/recipes/u-boot/u-boot_git.bb
index 928642dbbb..c3da2c528c 100644
--- a/recipes/u-boot/u-boot_git.bb
+++ b/recipes/u-boot/u-boot_git.bb
@@ -1,5 +1,5 @@
require u-boot.inc
-PR ="r43"
+PR ="r44"
FILESPATHPKG =. "u-boot-git:"
@@ -18,21 +18,12 @@ SRC_URI_append_afeb9260 = " file://AFEB9260-network-fix.patch;patch=1"
SRC_URI_append_afeb9260-180 = " file://AFEB9260-network-fix.patch;patch=1"
SRC_URI_append_cm-t35 = "file://cm-t35/cm-t35.patch;patch=1"
-SRC_URI_beagleboard = "git://git.denx.de/u-boot-ti.git;protocol=git \
- file://fw_env.config \
- file://new-pinmux.patch;patch=1 \
-file://revision-detection.patch;patch=1 \
-file://i2c.patch;patch=1 \
-file://720MHz.patch;patch=1 \
-file://dss.patch;patch=1 \
-file://0001-omap3-clock.c-don-t-reprogram-clocks-when-trying-to-.patch;patch=1 \
-file://0002-beagleboard-add-pinmuxing-for-beagleboard-XM.patch;patch=1 \
-file://0003-beagleboard-move-muxing-into-revision-print-switch.patch;patch=1 \
-file://Cortex-A8-erratum-725233.diff;patch=1 \
+SRC_URI_beagleboard = "git://www.sakoman.com/git/u-boot.git;branch=omap3-v2010.3;protocol=git \
+ file://0001-Minimal-Display-driver-for-OMAP3.patch;patch=1 \
+ file://fw_env.config \
"
-
-SRCREV_beagleboard = "a5cf522a91ba479d459f8221135bdb3e9ae97479"
-PV_beagleboard = "2009.11-rc1+${PR}+gitr${SRCREV}"
+SRCREV_beagleboard = "946351081bd14e8bf5816fc38b82e004a0e6b4fe"
+PV_beagleboard = "2010.03-rc1+${PR}+gitr${SRCREV}"
SRCREV_calamari = "533cf3a024947aaf74c16573a6d951cd0c3d0a7d"
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 03:31:24 +0000