linux-omap-psp: Add latest pending kernel patches

   * Fixes for 1GHz operation
   * EHCI
   * Build
   * DSS

   * Bump Kernel PR

Signed-off-by: Roger Monk <r-monk@ti.com>
Signed-off-by: Koen Kooi <k-kooi@ti.com>

11 files changed, 1386 insertions, 1 deletions

diff --git a/conf/machine/include/omap3.inc b/conf/machine/include/omap3.inc
index 60ec0ff42a..193e31e8f9 100644
--- a/conf/machine/include/omap3.inc
+++ b/conf/machine/include/omap3.inc
@@ -3,7 +3,7 @@ SOC_FAMILY = "omap3"
 require conf/machine/include/tune-cortexa8.inc
 PREFERRED_PROVIDER_virtual/kernel = "linux-omap"
 # Increase this everytime you change something in the kernel
-MACHINE_KERNEL_PR = "r89"
+MACHINE_KERNEL_PR = "r90"
 
 KERNEL_IMAGETYPE = "uImage"
 
diff --git a/recipes/linux/linux-omap-psp-2.6.32/pending/0001-OMAP3-SDRC-add-100MHz-timing-data-for-Hynix-H8KDS0.patch b/recipes/linux/linux-omap-psp-2.6.32/pending/0001-OMAP3-SDRC-add-100MHz-timing-data-for-Hynix-H8KDS0.patch
new file mode 100644
index 0000000000..4f37f603a7
--- /dev/null
+++ b/recipes/linux/linux-omap-psp-2.6.32/pending/0001-OMAP3-SDRC-add-100MHz-timing-data-for-Hynix-H8KDS0.patch
@@ -0,0 +1,39 @@
+From 908b7949544571e9acc1fe0cce918f6e338926c9 Mon Sep 17 00:00:00 2001
+From: Ranjith Lohithakshan <ranjithl@ti.com>
+Date: Fri, 28 May 2010 15:13:18 +0530
+Subject: [PATCH 1/9] OMAP3: SDRC: add 100MHz timing data for Hynix H8KDS0UN0MER-4EM
+
+Also, the refresh control value used at 200MHz was incorrect. Fixed
+that as well.
+
+Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
+---
+ arch/arm/mach-omap2/sdram-hynix-h8kds0un0mer-4em.h |    9 ++++++++-
+ 1 files changed, 8 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/sdram-hynix-h8kds0un0mer-4em.h b/arch/arm/mach-omap2/sdram-hynix-h8kds0un0mer-4em.h
+index 06433e6..c147586 100644
+--- a/arch/arm/mach-omap2/sdram-hynix-h8kds0un0mer-4em.h
++++ b/arch/arm/mach-omap2/sdram-hynix-h8kds0un0mer-4em.h
+@@ -19,10 +19,17 @@ static struct omap_sdrc_params h8kds0un0mer4em_sdrc_params[] = {
+ 		.rate        = 200000000,
+ 		.actim_ctrla = 0x92e1c4c6,
+ 		.actim_ctrlb = 0x0002111c,
+-		.rfr_ctrl    = 0x0004dc01,
++		.rfr_ctrl    = 0x0005e601,
+ 		.mr          = 0x00000032,
+ 	},
+ 	[1] = {
++		.rate        = 100000000,
++		.actim_ctrla = 0x49912283,
++		.actim_ctrlb = 0x0002110e,
++		.rfr_ctrl    = 0x0002da01,
++		.mr          = 0x00000032,
++    },
++	[2] = {
+ 		.rate        = 0
+ 	},
+ };
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-psp-2.6.32/pending/0002-omap3-Fix-voltage-and-frequency-scaling-order-when.patch b/recipes/linux/linux-omap-psp-2.6.32/pending/0002-omap3-Fix-voltage-and-frequency-scaling-order-when.patch
new file mode 100644
index 0000000000..bd16d29aaf
--- /dev/null
+++ b/recipes/linux/linux-omap-psp-2.6.32/pending/0002-omap3-Fix-voltage-and-frequency-scaling-order-when.patch
@@ -0,0 +1,152 @@
+From d247a112a9ffbad1057a2c8bede5727940ac2045 Mon Sep 17 00:00:00 2001
+From: Ranjith Lohithakshan <ranjithl@ti.com>
+Date: Fri, 28 May 2010 15:20:32 +0530
+Subject: [PATCH 2/9] omap3: Fix voltage and frequency scaling order when changing OPP via mpurate
+
+When lowering an OPP via mpurate from what is being set by bootloader,
+the frequency need to be lowered before voltage is ramped down. The
+current code was not taking this into consideration and was always
+adjusting the voltage before the frequency adjustments.
+
+This was leading to crashes on 3730 when mpurate was set to 300MHz
+because the voltage was lowered before the frequency.
+
+This patch fixes these issues by tracking the direction of OPP change
+and doing the voltage and frequency change in the right order.
+
+Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
+---
+ arch/arm/mach-omap2/clock34xx.c   |   51 +++++++++++++++++++++++-------------
+ arch/arm/mach-omap2/smartreflex.c |   11 +++++---
+ 2 files changed, 39 insertions(+), 23 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
+index 2bb7182..dd408eb 100644
+--- a/arch/arm/mach-omap2/clock34xx.c
++++ b/arch/arm/mach-omap2/clock34xx.c
+@@ -65,6 +65,7 @@ struct clk *sdrc_ick_p, *arm_fck_p;
+  */
+ unsigned int vdd1_opp = 0;
+ unsigned int vdd2_opp = 0;
++bool vdd_scale_down = false;
+ 
+ /**
+  * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
+@@ -429,6 +430,24 @@ static void __init omap2_clk_iva_init_to_idle(void)
+ 
+ }
+ 
++static u16 get_opp(struct omap_opp *opp_freq_table,
++					unsigned long freq)
++{
++	struct omap_opp *prcm_config;
++
++	prcm_config = opp_freq_table;
++
++	if (prcm_config->rate <= freq)
++		return prcm_config->opp_id; /* Return the Highest OPP */
++	for (; prcm_config->rate; prcm_config--)
++		if (prcm_config->rate < freq)
++			return (prcm_config+1)->opp_id;
++		else if (prcm_config->rate == freq)
++			return prcm_config->opp_id;
++	/* Return the least OPP */
++	return (prcm_config+1)->opp_id;
++}
++
+ /* REVISIT: Move this init stuff out into clock.c */
+ 
+ /*
+@@ -444,8 +463,10 @@ static void __init omap2_clk_iva_init_to_idle(void)
+  */
+ static int __init omap2_clk_arch_init(void)
+ {
+-	struct omap_opp *opp_table;
+-	short valid=0, err=0, i;
++	short err=0;
++	u16	current_vdd1_opp;
++	struct clk *arm_fck;
++	unsigned long current_mpu_rate;
+ 
+ 	if (!mpurate)
+ 		return -EINVAL;
+@@ -463,6 +484,10 @@ static int __init omap2_clk_arch_init(void)
+ 	if (WARN((!l3_opps), "OPP table not defined for L3\n"))
+ 		err = 1;
+ 
++	arm_fck = clk_get(NULL, "arm_fck");
++	if (WARN(IS_ERR(arm_fck), "Failed to get arm_fck.\n"))
++		err = 1;
++
+ 	if (err)
+ 		return -ENOENT;
+ 
+@@ -475,24 +500,12 @@ static int __init omap2_clk_arch_init(void)
+ 		pr_err("This silicon doesn't support 720MHz\n");
+ 	}
+ 
+-	/*
+-	 * Select VDD1 OPP corresponding to mpurate
+-	 */
+-	opp_table = mpu_opps;
+-
+-	for (i = 1; opp_table[i].opp_id <= get_max_vdd1(); i++) {
+-		if (opp_table[i].rate == mpurate) {
+-			valid = 1;
+-			break;
+-		}
+-	}
++	current_mpu_rate = clk_get_rate(arm_fck);
++	current_vdd1_opp = get_opp(mpu_opps + get_max_vdd1(), current_mpu_rate);
++	vdd1_opp = get_opp(mpu_opps + get_max_vdd1(), mpurate);
+ 
+-	if (valid) {
+-		vdd1_opp = opp_table[i].opp_id;
+-	} else {
+-		pr_err("Invalid MPU rate (%u)\n", mpurate);
+-		return -EINVAL;
+-	}
++	if (vdd1_opp < current_vdd1_opp)
++		vdd_scale_down = true;
+ 
+ 	/*
+ 	 * Match lowest OPP setting for VDD1 with lowest OPP for VDD2 as well.
+diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
+index 3b6ddf8..fd34af2 100644
+--- a/arch/arm/mach-omap2/smartreflex.c
++++ b/arch/arm/mach-omap2/smartreflex.c
+@@ -48,6 +48,7 @@
+  */
+ extern unsigned int vdd1_opp;
+ extern unsigned int vdd2_opp;
++extern bool vdd_scale_down;
+ 
+ extern int __init omap2_clk_set_freq(void);
+ 
+@@ -1082,6 +1083,10 @@ static int __init omap3_sr_init(void)
+ 	sr_set_clk_length(&sr1);
+ 	sr_set_clk_length(&sr2);
+ 
++	/* For OPP scale down, scale down frequency before voltage */
++	if (cpu_is_omap34xx() && vdd_scale_down)
++        omap2_clk_set_freq();
++
+ 	/* Call the VPConfig, VCConfig, set N Values. */
+ 	sr_set_nvalues(&sr1);
+ 	sr_configure_vp(SR1);
+@@ -1089,10 +1094,8 @@ static int __init omap3_sr_init(void)
+ 	sr_set_nvalues(&sr2);
+ 	sr_configure_vp(SR2);
+ 
+-	/*
+-	 * With voltages matching target OPP, set corresponding frequency.
+-	 */
+-	if (cpu_is_omap34xx())
++	/* For OPP scale up, scale up the frequency after voltage */
++	if (cpu_is_omap34xx() && !vdd_scale_down)
+ 		omap2_clk_set_freq();
+ 
+ 	ret = sysfs_create_file(power_kobj, &sr_vdd1_autocomp.attr);
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-psp-2.6.32/pending/0003-OMAP3-PM-Introduce-Smartreflex-support-on-OMAP3630.patch b/recipes/linux/linux-omap-psp-2.6.32/pending/0003-OMAP3-PM-Introduce-Smartreflex-support-on-OMAP3630.patch
new file mode 100644
index 0000000000..020d012bd6
--- /dev/null
+++ b/recipes/linux/linux-omap-psp-2.6.32/pending/0003-OMAP3-PM-Introduce-Smartreflex-support-on-OMAP3630.patch
@@ -0,0 +1,362 @@
+From bf679a27766de623815d820431e1049326f7cac1 Mon Sep 17 00:00:00 2001
+From: Ranjith Lohithakshan <ranjithl@ti.com>
+Date: Fri, 9 Jul 2010 15:55:41 +0530
+Subject: [PATCH 3/9] OMAP3: PM: Introduce Smartreflex support on OMAP3630/DM3730
+
+OMAP3630 has a newer version of Smartreflex IP called Smartreflex2. There are
+new register additions and bit definition differences in this version of the IP.
+This patch introduces the Class3 driver support for Smartreflex2 on OMAP3630.
+
+Smartreflex2 has the following registers added
+IRQ_EOI, IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR
+
+And following register offsets are different from Smartreflex1
+SENERROR, ERRCONFIG
+
+Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
+---
+ arch/arm/mach-omap2/smartreflex.c         |  190 +++++++++++++++++++----------
+ arch/arm/mach-omap2/smartreflex.h         |   16 +++
+ arch/arm/plat-omap/include/plat/control.h |   13 ++
+ 3 files changed, 157 insertions(+), 62 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
+index fd34af2..fdd9540 100644
+--- a/arch/arm/mach-omap2/smartreflex.c
++++ b/arch/arm/mach-omap2/smartreflex.c
+@@ -99,18 +99,26 @@ static int sr_clk_enable(struct omap_sr *sr)
+ 		return -1;
+ 	}
+ 
+-	/* set fclk- active , iclk- idle */
+-	sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
+-		      SR_CLKACTIVITY_IOFF_FON);
++	if (cpu_is_omap3630())
++		sr_modify_reg(sr, ERRCONFIG_36XX, SR_IDLEMODE_MASK,
++				SR_SMART_IDLE);
++	else
++		/* set fclk- active , iclk- idle */
++		sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
++			SR_CLKACTIVITY_IOFF_FON);
+ 
+ 	return 0;
+ }
+ 
+ static void sr_clk_disable(struct omap_sr *sr)
+ {
+-	/* set fclk, iclk- idle */
+-	sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
+-		      SR_CLKACTIVITY_IOFF_FOFF);
++	if (cpu_is_omap3630())
++		sr_modify_reg(sr, ERRCONFIG_36XX, SR_IDLEMODE_MASK,
++				SR_FORCE_IDLE);
++	else
++		/* set fclk, iclk- idle */
++		sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
++				SR_CLKACTIVITY_IOFF_FOFF);
+ 
+ 	clk_disable(sr->clk);
+ 	sr->is_sr_reset = 1;
+@@ -285,39 +293,55 @@ static u32 swcalc_opp6_nvalue(void)
+ static void sr_set_efuse_nvalues(struct omap_sr *sr)
+ {
+ 	if (sr->srid == SR1) {
+-		sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
+-					OMAP343X_SR1_SENNENABLE_MASK) >>
+-					OMAP343X_SR1_SENNENABLE_SHIFT;
+-		sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
+-					OMAP343X_SR1_SENPENABLE_MASK) >>
+-					OMAP343X_SR1_SENPENABLE_SHIFT;
+-
+-		sr->opp6_nvalue = swcalc_opp6_nvalue();
+-		sr->opp5_nvalue = omap_ctrl_readl(
+-					OMAP343X_CONTROL_FUSE_OPP5_VDD1);
+-		sr->opp4_nvalue = omap_ctrl_readl(
+-					OMAP343X_CONTROL_FUSE_OPP4_VDD1);
+-		sr->opp3_nvalue = omap_ctrl_readl(
+-					OMAP343X_CONTROL_FUSE_OPP3_VDD1);
+-		sr->opp2_nvalue = omap_ctrl_readl(
+-					OMAP343X_CONTROL_FUSE_OPP2_VDD1);
+-		sr->opp1_nvalue = omap_ctrl_readl(
+-					OMAP343X_CONTROL_FUSE_OPP1_VDD1);
++		if (cpu_is_omap3630()) {
++			sr->senn_mod = sr->senp_mod = 0x1;
++
++			sr->opp4_nvalue = omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP4_VDD1);
++			sr->opp3_nvalue = omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP3_VDD1);
++			sr->opp2_nvalue = omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP2_VDD1);
++			sr->opp1_nvalue = omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP1_VDD1);
++		} else {
++			sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
++						OMAP343X_SR1_SENNENABLE_MASK) >>
++						OMAP343X_SR1_SENNENABLE_SHIFT;
++			sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
++						OMAP343X_SR1_SENPENABLE_MASK) >>
++						OMAP343X_SR1_SENPENABLE_SHIFT;
++
++			sr->opp6_nvalue = swcalc_opp6_nvalue();
++			sr->opp5_nvalue = omap_ctrl_readl(
++						OMAP343X_CONTROL_FUSE_OPP5_VDD1);
++			sr->opp4_nvalue = omap_ctrl_readl(
++						OMAP343X_CONTROL_FUSE_OPP4_VDD1);
++			sr->opp3_nvalue = omap_ctrl_readl(
++						OMAP343X_CONTROL_FUSE_OPP3_VDD1);
++			sr->opp2_nvalue = omap_ctrl_readl(
++						OMAP343X_CONTROL_FUSE_OPP2_VDD1);
++			sr->opp1_nvalue = omap_ctrl_readl(
++						OMAP343X_CONTROL_FUSE_OPP1_VDD1);
++		}
+ 	} else if (sr->srid == SR2) {
+-		sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
+-					OMAP343X_SR2_SENNENABLE_MASK) >>
+-					OMAP343X_SR2_SENNENABLE_SHIFT;
+-
+-		sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
+-					OMAP343X_SR2_SENPENABLE_MASK) >>
+-					OMAP343X_SR2_SENPENABLE_SHIFT;
+-
+-		sr->opp3_nvalue = omap_ctrl_readl(
+-					OMAP343X_CONTROL_FUSE_OPP3_VDD2);
+-		sr->opp2_nvalue = omap_ctrl_readl(
+-					OMAP343X_CONTROL_FUSE_OPP2_VDD2);
+-		sr->opp1_nvalue = omap_ctrl_readl(
+-					OMAP343X_CONTROL_FUSE_OPP1_VDD2);
++		if (cpu_is_omap3630()) {
++			sr->senn_mod = sr->senp_mod = 0x1;
++
++			sr->opp1_nvalue = omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP1_VDD2);
++			sr->opp2_nvalue = omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP2_VDD2);
++		} else {
++			sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
++						OMAP343X_SR2_SENNENABLE_MASK) >>
++						OMAP343X_SR2_SENNENABLE_SHIFT;
++
++			sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
++						OMAP343X_SR2_SENPENABLE_MASK) >>
++						OMAP343X_SR2_SENPENABLE_SHIFT;
++
++			sr->opp3_nvalue = omap_ctrl_readl(
++						OMAP343X_CONTROL_FUSE_OPP3_VDD2);
++			sr->opp2_nvalue = omap_ctrl_readl(
++						OMAP343X_CONTROL_FUSE_OPP2_VDD2);
++			sr->opp1_nvalue = omap_ctrl_readl(
++						OMAP343X_CONTROL_FUSE_OPP1_VDD2);
++		}
+ 	}
+ }
+ 
+@@ -325,22 +349,42 @@ static void sr_set_efuse_nvalues(struct omap_sr *sr)
+ static void sr_set_testing_nvalues(struct omap_sr *sr)
+ {
+ 	if (sr->srid == SR1) {
+-		sr->senp_mod = 0x03;	/* SenN-M5 enabled */
+-		sr->senn_mod = 0x03;
+-
+-		/* calculate nvalues for each opp */
+-		sr->opp5_nvalue = cal_test_nvalue(0xacd + 0x330, 0x848 + 0x330);
+-		sr->opp4_nvalue = cal_test_nvalue(0x964 + 0x2a0, 0x727 + 0x2a0);
+-		sr->opp3_nvalue = cal_test_nvalue(0x85b + 0x200, 0x655 + 0x200);
+-		sr->opp2_nvalue = cal_test_nvalue(0x506 + 0x1a0, 0x3be + 0x1a0);
+-		sr->opp1_nvalue = cal_test_nvalue(0x373 + 0x100, 0x28c + 0x100);
++		if (cpu_is_omap3630()) {
++			sr->senp_mod = 0x1;
++			sr->senn_mod = 0x1;
++
++			/* calculate nvalues for each opp */
++			sr->opp1_nvalue = cal_test_nvalue(581, 489);
++			sr->opp2_nvalue = cal_test_nvalue(1072, 910);
++			sr->opp3_nvalue = cal_test_nvalue(1405, 1200);
++			sr->opp4_nvalue = cal_test_nvalue(1842, 1580);
++			sr->opp5_nvalue = cal_test_nvalue(1842, 1580);
++        } else {
++			sr->senp_mod = 0x03;	/* SenN-M5 enabled */
++			sr->senn_mod = 0x03;
++
++			/* calculate nvalues for each opp */
++			sr->opp5_nvalue = cal_test_nvalue(0xacd + 0x330, 0x848 + 0x330);
++			sr->opp4_nvalue = cal_test_nvalue(0x964 + 0x2a0, 0x727 + 0x2a0);
++			sr->opp3_nvalue = cal_test_nvalue(0x85b + 0x200, 0x655 + 0x200);
++			sr->opp2_nvalue = cal_test_nvalue(0x506 + 0x1a0, 0x3be + 0x1a0);
++			sr->opp1_nvalue = cal_test_nvalue(0x373 + 0x100, 0x28c + 0x100);
++		}
+ 	} else if (sr->srid == SR2) {
+-		sr->senp_mod = 0x03;
+-		sr->senn_mod = 0x03;
+-
+-		sr->opp3_nvalue = cal_test_nvalue(0x76f + 0x200, 0x579 + 0x200);
+-		sr->opp2_nvalue = cal_test_nvalue(0x4f5 + 0x1c0, 0x390 + 0x1c0);
+-		sr->opp1_nvalue = cal_test_nvalue(0x359, 0x25d);
++		if (cpu_is_omap3630()) {
++			sr->senp_mod = 0x1;
++			sr->senn_mod = 0x1;
++
++			sr->opp1_nvalue = cal_test_nvalue(556, 468);
++			sr->opp2_nvalue = cal_test_nvalue(1099, 933);
++		} else {
++			sr->senp_mod = 0x03;
++			sr->senn_mod = 0x03;
++
++			sr->opp3_nvalue = cal_test_nvalue(0x76f + 0x200, 0x579 + 0x200);
++			sr->opp2_nvalue = cal_test_nvalue(0x4f5 + 0x1c0, 0x390 + 0x1c0);
++			sr->opp1_nvalue = cal_test_nvalue(0x359, 0x25d);
++		}
+ 	}
+ 
+ }
+@@ -487,6 +531,17 @@ static void sr_configure(struct omap_sr *sr)
+ {
+ 	u32 sr_config;
+ 	u32 senp_en , senn_en;
++	u32 senp_en_shift, senn_en_shift, err_config;
++
++	if (cpu_is_omap3630()) {
++		senp_en_shift = SRCONFIG_SENPENABLE_SHIFT_36XX;
++		senn_en_shift = SRCONFIG_SENNENABLE_SHIFT_36XX;
++		err_config = ERRCONFIG_36XX;
++	} else {
++		senp_en_shift = SRCONFIG_SENPENABLE_SHIFT;
++		senn_en_shift = SRCONFIG_SENNENABLE_SHIFT;
++		err_config = ERRCONFIG;
++	}
+ 
+ 	if (sr->clk_length == 0)
+ 		sr_set_clk_length(sr);
+@@ -498,15 +553,15 @@ static void sr_configure(struct omap_sr *sr)
+ 			(sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+ 			SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
+ 			SRCONFIG_MINMAXAVG_EN |
+-			(senn_en << SRCONFIG_SENNENABLE_SHIFT) |
+-			(senp_en << SRCONFIG_SENPENABLE_SHIFT) |
++			(senn_en << senn_en_shift) |
++			(senp_en << senp_en_shift) |
+ 			SRCONFIG_DELAYCTRL;
+ 
+ 		sr_write_reg(sr, SRCONFIG, sr_config);
+ 		sr_write_reg(sr, AVGWEIGHT, SR1_AVGWEIGHT_SENPAVGWEIGHT |
+ 					SR1_AVGWEIGHT_SENNAVGWEIGHT);
+ 
+-		sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
++		sr_modify_reg(sr, err_config, (SR_ERRWEIGHT_MASK |
+ 			SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
+ 			(SR1_ERRWEIGHT | SR1_ERRMAXLIMIT | SR1_ERRMINLIMIT));
+ 
+@@ -515,14 +570,14 @@ static void sr_configure(struct omap_sr *sr)
+ 			(sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+ 			SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
+ 			SRCONFIG_MINMAXAVG_EN |
+-			(senn_en << SRCONFIG_SENNENABLE_SHIFT) |
+-			(senp_en << SRCONFIG_SENPENABLE_SHIFT) |
++			(senn_en << senn_en_shift) |
++			(senp_en << senp_en_shift) |
+ 			SRCONFIG_DELAYCTRL;
+ 
+ 		sr_write_reg(sr, SRCONFIG, sr_config);
+ 		sr_write_reg(sr, AVGWEIGHT, SR2_AVGWEIGHT_SENPAVGWEIGHT |
+ 					SR2_AVGWEIGHT_SENNAVGWEIGHT);
+-		sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
++		sr_modify_reg(sr, err_config, (SR_ERRWEIGHT_MASK |
+ 			SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
+ 			(SR2_ERRWEIGHT | SR2_ERRMAXLIMIT | SR2_ERRMINLIMIT));
+ 
+@@ -604,6 +659,7 @@ static int sr_reset_voltage(int srid)
+ static int sr_enable(struct omap_sr *sr, u32 target_opp_no)
+ {
+ 	u32 nvalue_reciprocal, v;
++	u32 inten, intst, err_config;
+ 
+ 	if (!(mpu_opps && l3_opps)) {
+ 		pr_notice("VSEL values not found\n");
+@@ -662,9 +718,19 @@ static int sr_enable(struct omap_sr *sr, u32 target_opp_no)
+ 	sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
+ 
+ 	/* Enable the interrupt */
+-	sr_modify_reg(sr, ERRCONFIG,
+-			(ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST),
+-			(ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST));
++	if (cpu_is_omap3630()) {
++		inten = ERRCONFIG_VPBOUNDINTEN_36XX;
++		intst = ERRCONFIG_VPBOUNDINTST_36XX;
++		err_config = ERRCONFIG_36XX;
++	} else {
++		inten = ERRCONFIG_VPBOUNDINTEN;
++		intst = ERRCONFIG_VPBOUNDINTST;
++		err_config = ERRCONFIG;
++	}
++
++	sr_modify_reg(sr, err_config,
++			(inten | intst),
++			(inten | intst));
+ 
+ 	if (sr->srid == SR1) {
+ 		/* set/latch init voltage */
+diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
+index 2a0e823..f20406b 100644
+--- a/arch/arm/mach-omap2/smartreflex.h
++++ b/arch/arm/mach-omap2/smartreflex.h
+@@ -30,6 +30,9 @@
+ #define SENERROR	0x20
+ #define ERRCONFIG	0x24
+ 
++#define SENERROR_36XX	0x34
++#define ERRCONFIG_36XX	0x38
++
+ /* SR Modules */
+ #define SR1		1
+ #define SR2		2
+@@ -106,6 +109,9 @@
+ #define SRCONFIG_SENNENABLE_SHIFT	5
+ #define SRCONFIG_SENPENABLE_SHIFT	3
+ 
++#define SRCONFIG_SENNENABLE_SHIFT_36XX	1
++#define SRCONFIG_SENPENABLE_SHIFT_36XX	0
++
+ #define SRCONFIG_SRENABLE		BIT(11)
+ #define SRCONFIG_SENENABLE		BIT(10)
+ #define SRCONFIG_ERRGEN_EN		BIT(9)
+@@ -136,9 +142,19 @@
+ #define SR_CLKACTIVITY_IOFF_FOFF	(0x00 << 20)
+ #define SR_CLKACTIVITY_IOFF_FON		(0x02 << 20)
+ 
++/* IDLEMODE SETTINGS for OMAP3630 */
++#define SR_IDLEMODE_MASK	(0x3 << 24)
++#define SR_FORCE_IDLE			0x0
++#define SR_NO_IDLE				0x1
++#define SR_SMART_IDLE			0x2
++#define SR_SMART_IDLE_WKUP		0x3
++
+ #define ERRCONFIG_VPBOUNDINTEN		BIT(31)
+ #define ERRCONFIG_VPBOUNDINTST		BIT(30)
+ 
++#define ERRCONFIG_VPBOUNDINTEN_36XX		BIT(23)
++#define ERRCONFIG_VPBOUNDINTST_36XX		BIT(22)
++
+ #define SR1_ERRWEIGHT			(0x07 << 16)
+ #define SR1_ERRMAXLIMIT			(0x02 << 8)
+ #define SR1_ERRMINLIMIT			(0xFA << 0)
+diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
+index 20f5c98..68100d6 100644
+--- a/arch/arm/plat-omap/include/plat/control.h
++++ b/arch/arm/plat-omap/include/plat/control.h
+@@ -283,6 +283,19 @@
+ #define OMAP343X_SCRATCHPAD		(OMAP343X_CTRL_BASE + 0x910)
+ #define OMAP343X_SCRATCHPAD_ROM_OFFSET	0x19C
+ 
++/* OMAP36XX CONTROL FUSE */
++
++#define OMAP36XX_CONTROL_FUSE_OPP1_VDD1	(OMAP2_CONTROL_GENERAL + 0x0114)
++#define OMAP36XX_CONTROL_FUSE_OPP2_VDD1	(OMAP2_CONTROL_GENERAL + 0x0118)
++#define OMAP36XX_CONTROL_FUSE_OPP3_VDD1	(OMAP2_CONTROL_GENERAL + 0x0120)
++#define OMAP36XX_CONTROL_FUSE_OPP4_VDD1	(OMAP2_CONTROL_GENERAL + 0x0110)
++#define OMAP36XX_CONTROL_FUSE_OPP5_VDD1	(OMAP2_CONTROL_GENERAL + 0x0108)
++
++#define OMAP36XX_CONTROL_FUSE_OPP1_VDD2	(OMAP2_CONTROL_GENERAL + 0x0128)
++#define OMAP36XX_CONTROL_FUSE_OPP2_VDD2	(OMAP2_CONTROL_GENERAL + 0x012c)
++
++#define OMAP36XX_CONTROL_FUSE_SR		(OMAP2_CONTROL_GENERAL + 0x0130)
++
+ /*
+  * Product ID register
+  */
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-psp-2.6.32/pending/0004-OMAP3630-PM-implement-Foward-Body-Bias-for-OPP1G.patch b/recipes/linux/linux-omap-psp-2.6.32/pending/0004-OMAP3630-PM-implement-Foward-Body-Bias-for-OPP1G.patch
new file mode 100644
index 0000000000..77e9a75b62
--- /dev/null
+++ b/recipes/linux/linux-omap-psp-2.6.32/pending/0004-OMAP3630-PM-implement-Foward-Body-Bias-for-OPP1G.patch
@@ -0,0 +1,243 @@
+From 8d78b8198d220d5ebade7587caf664a0ef8c8fe7 Mon Sep 17 00:00:00 2001
+From: Ranjith Lohithakshan <ranjithl@ti.com>
+Date: Mon, 12 Jul 2010 16:25:14 +0530
+Subject: [PATCH 4/9] OMAP3630: PM: implement Foward Body-Bias for OPP1G
+
+Introduces voltscale_adaptive_body_bias function to voltage.c.
+voltscale_adaptive_body_bias is called by omap_voltage_scale after a
+voltage transition has occured.  Currently voltscale_adaptive_body_bias
+only implements Forward Body-Bias (FBB) for OMAP3630 when MPU runs at
+1GHz or higher.  In the future Reverse Body-Bias might be included.
+
+FBB is an Adaptive Body-Bias technique to boost performance for weak
+process devices at high OPPs. This results in voltage boost on the VDD1
+PMOS back gates when running at maximum OPP.  Current recommendations
+are to enable FBB on all 3630 regardless of silicon characteristics and
+EFUSE values.
+
+ABB applies to all OMAP family of devices based on 45nm process,
+which includes OMAP3630, OMAP4, TI816x and TI814x.
+
+Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
+---
+ arch/arm/mach-omap2/prm-regbits-34xx.h |   18 +++++
+ arch/arm/mach-omap2/prm.h              |    4 +
+ arch/arm/mach-omap2/smartreflex.c      |  130 ++++++++++++++++++++++++++++++++
+ 3 files changed, 152 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
+index 0066693..8dee7e0 100644
+--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
++++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
+@@ -212,6 +212,8 @@
+ /* PRM_SYSCONFIG specific bits */
+ 
+ /* PRM_IRQSTATUS_MPU specific bits */
++#define OMAP3630_ABB_LDO_TRANXDONE_ST_SHIFT			26
++#define OMAP3630_ABB_LDO_TRANXDONE_ST			(1 << 26)
+ #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT		25
+ #define OMAP3430ES2_SND_PERIPH_DPLL_ST			(1 << 25)
+ #define OMAP3430_VC_TIMEOUTERR_ST			(1 << 24)
+@@ -581,6 +583,22 @@
+ 
+ /* PRM_VP2_STATUS specific bits */
+ 
++/* PRM_LDO_ABB_SETUP specific bits */
++#define OMAP3630_SR2_IN_TRANSITION			(1 << 6)
++#define OMAP3630_SR2_STATUS_SHIFT			3
++#define OMAP3630_SR2_STATUS_MASK			(3 << 3)
++#define OMAP3630_OPP_CHANGE				(1 << 2)
++#define OMAP3630_OPP_SEL_SHIFT				0
++#define OMAP3630_OPP_SEL_MASK				(3 << 0)
++
++/* PRM_LDO_ABB_CTRL specific bits */
++#define OMAP3630_SR2_WTCNT_VALUE_SHIFT			8
++#define OMAP3630_SR2_WTCNT_VALUE_MASK			(0xff << 8)
++#define OMAP3630_SLEEP_RBB_SEL				(1 << 3)
++#define OMAP3630_ACTIVE_FBB_SEL				(1 << 2)
++#define OMAP3630_ACTIVE_RBB_SEL				(1 << 1)
++#define OMAP3630_SR2EN					(1 << 0)
++
+ /* RM_RSTST_NEON specific bits */
+ 
+ /* PM_WKDEP_NEON specific bits */
+diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
+index ea050ce..b7f95d7 100644
+--- a/arch/arm/mach-omap2/prm.h
++++ b/arch/arm/mach-omap2/prm.h
+@@ -158,6 +158,10 @@
+ #define OMAP3430_PRM_VP2_VOLTAGE	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
+ #define OMAP3_PRM_VP2_STATUS_OFFSET	0x00e4
+ #define OMAP3430_PRM_VP2_STATUS		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
++#define OMAP3_PRM_LDO_ABB_SETUP_OFFSET  0X00f0
++#define OMAP3630_PRM_LDO_ABB_SETUP  OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0X00f0)
++#define OMAP3_PRM_LDO_ABB_CTRL_OFFSET   0X00f4
++#define OMAP3630_PRM_LDO_ABB_CTRL   OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0X00f4)
+ 
+ #define OMAP3_PRM_CLKSEL_OFFSET	0x0040
+ #define OMAP3430_PRM_CLKSEL		OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
+diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
+index fdd9540..d7c8a04 100644
+--- a/arch/arm/mach-omap2/smartreflex.c
++++ b/arch/arm/mach-omap2/smartreflex.c
+@@ -42,6 +42,11 @@
+ #define SWCALC_OPP6_DELTA_NNT	379
+ #define SWCALC_OPP6_DELTA_PNT	227
+ 
++#define ABB_MAX_SETTLING_TIME	30
++
++#define ABB_FAST_OPP			1
++#define ABB_NOMINAL_OPP			2
++#define ABB_SLOW_OPP			3
+ 
+ /*
+  * VDD1 and VDD2 OPPs derived from the bootarg 'mpurate'
+@@ -397,6 +402,126 @@ static void sr_set_nvalues(struct omap_sr *sr)
+ 		sr_set_efuse_nvalues(sr);
+ }
+ 
++/**
++ * sr_voltagescale_adaptive_body_bias - controls ABB ldo during voltage scaling
++ * @target_volt: target voltage determines if ABB ldo is active or bypassed
++ *
++ * Adaptive Body-Bias is a technique in all OMAP silicon that uses the 45nm
++ * process.  ABB can boost voltage in high OPPs for silicon with weak
++ * characteristics (forward Body-Bias) as well as lower voltage in low OPPs
++ * for silicon with strong characteristics (Reverse Body-Bias).
++ *
++ * Only Foward Body-Bias for operating at high OPPs is implemented below, per
++ * recommendations from silicon team.
++ * Reverse Body-Bias for saving power in active cases and sleep cases is not
++ * yet implemented.
++ */
++static int sr_voltagescale_adaptive_body_bias(u32 target_opp_no)
++{
++	u32 sr2en_enabled;
++	int timeout;
++	int sr2_wtcnt_value;
++	struct clk *sys_ck;
++
++	sys_ck = clk_get(NULL, "sys_ck");
++	if (IS_ERR(sys_ck)) {
++		pr_warning("%s: Could not get the sys clk to calculate"
++            "SR2_WTCNT_VALUE \n", __func__);
++        return -ENOENT;
++    }
++
++	/* calculate SR2_WTCNT_VALUE settling time */
++	sr2_wtcnt_value = (ABB_MAX_SETTLING_TIME *
++		(clk_get_rate(sys_ck) / 1000000) / 8);
++
++	clk_put(sys_ck);
++
++	/* has SR2EN been enabled previously? */
++	sr2en_enabled = (prm_read_mod_reg(OMAP3430_GR_MOD,
++			OMAP3_PRM_LDO_ABB_CTRL_OFFSET) &
++			OMAP3630_SR2EN);
++
++	/* select fast, nominal or slow OPP for ABB ldo */
++	if (target_opp_no >= VDD1_OPP4) {
++		/* program for fast opp - enable FBB */
++		prm_rmw_mod_reg_bits(OMAP3630_OPP_SEL_MASK,
++				(ABB_FAST_OPP << OMAP3630_OPP_SEL_SHIFT),
++				OMAP3430_GR_MOD,
++				OMAP3_PRM_LDO_ABB_SETUP_OFFSET);
++
++		/* enable the ABB ldo if not done already */
++		if (!sr2en_enabled)
++			prm_set_mod_reg_bits(OMAP3630_SR2EN,
++					OMAP3430_GR_MOD,
++					OMAP3_PRM_LDO_ABB_CTRL_OFFSET);
++	} else if (sr2en_enabled) {
++		/* program for nominal opp - bypass ABB ldo */
++		prm_rmw_mod_reg_bits(OMAP3630_OPP_SEL_MASK,
++				(ABB_NOMINAL_OPP << OMAP3630_OPP_SEL_SHIFT),
++				OMAP3430_GR_MOD,
++				OMAP3_PRM_LDO_ABB_SETUP_OFFSET);
++	} else {
++		/* nothing to do here yet... might enable RBB here someday */
++		return 0;
++	}
++
++	/* set ACTIVE_FBB_SEL for all 45nm silicon */
++	prm_set_mod_reg_bits(OMAP3630_ACTIVE_FBB_SEL,
++			OMAP3430_GR_MOD,
++			OMAP3_PRM_LDO_ABB_CTRL_OFFSET);
++
++	/* program settling time of 30us for ABB ldo transition */
++	prm_rmw_mod_reg_bits(OMAP3630_SR2_WTCNT_VALUE_MASK,
++			(sr2_wtcnt_value << OMAP3630_SR2_WTCNT_VALUE_SHIFT),
++			OMAP3430_GR_MOD,
++			OMAP3_PRM_LDO_ABB_CTRL_OFFSET);
++
++	/* clear ABB ldo interrupt status */
++	prm_write_mod_reg(OMAP3630_ABB_LDO_TRANXDONE_ST,
++			OCP_MOD,
++			OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
++
++	/* enable ABB LDO OPP change */
++	prm_set_mod_reg_bits(OMAP3630_OPP_CHANGE,
++			OMAP3430_GR_MOD,
++			OMAP3_PRM_LDO_ABB_SETUP_OFFSET);
++
++	timeout = 0;
++
++	/* wait until OPP change completes */
++	while ((timeout < ABB_MAX_SETTLING_TIME ) &&
++			(!(prm_read_mod_reg(OCP_MOD,
++						OMAP2_PRCM_IRQSTATUS_MPU_OFFSET) &
++					OMAP3630_ABB_LDO_TRANXDONE_ST))) {
++		udelay(1);
++		timeout++;
++	}
++
++	if (timeout == ABB_MAX_SETTLING_TIME)
++		pr_debug("ABB: TRANXDONE timed out waiting for OPP change\n");
++
++	timeout = 0;
++
++	/* Clear all pending TRANXDONE interrupts/status */
++	while (timeout < ABB_MAX_SETTLING_TIME) {
++		prm_write_mod_reg(OMAP3630_ABB_LDO_TRANXDONE_ST,
++				OCP_MOD,
++				OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
++		if (!(prm_read_mod_reg(OCP_MOD,
++						OMAP2_PRCM_IRQSTATUS_MPU_OFFSET)
++					& OMAP3630_ABB_LDO_TRANXDONE_ST))
++			break;
++
++		udelay(1);
++		timeout++;
++	}
++	if (timeout == ABB_MAX_SETTLING_TIME)
++		pr_debug("ABB: TRANXDONE timed out trying to clear status\n");
++
++	return 0;
++}
++
++
+ static void sr_configure_vp(int srid)
+ {
+ 	u32 vpconfig;
+@@ -462,6 +587,8 @@ static void sr_configure_vp(int srid)
+ 		prm_clear_mod_reg_bits(OMAP3430_FORCEUPDATE, OMAP3430_GR_MOD,
+ 				       OMAP3_PRM_VP1_CONFIG_OFFSET);
+ 
++		if(cpu_is_omap3630())
++			sr_voltagescale_adaptive_body_bias(target_opp_no);
+ 	} else if (srid == SR2) {
+ 		if (vdd2_opp == 0)
+ 			target_opp_no = get_vdd2_opp();
+@@ -1031,6 +1158,9 @@ int sr_voltagescale_vcbypass(u32 target_opp, u32 current_opp,
+ 	t2_smps_delay = ((t2_smps_steps * 125) / 40) + 2;
+ 	udelay(t2_smps_delay);
+ 
++	if (cpu_is_omap3630() && (vdd == VDD1_OPP))
++		sr_voltagescale_adaptive_body_bias(target_opp_no);
++
+ 	if (sr_status) {
+ 		if (vdd == VDD1_OPP)
+ 			sr_start_vddautocomap(SR1, target_opp_no);
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-psp-2.6.32/pending/0005-Revert-Revert-OMAP-DSS2-FIFI-UNDERFLOW-issue-fix.patch b/recipes/linux/linux-omap-psp-2.6.32/pending/0005-Revert-Revert-OMAP-DSS2-FIFI-UNDERFLOW-issue-fix.patch
new file mode 100644
index 0000000000..0a041bba4e
--- /dev/null
+++ b/recipes/linux/linux-omap-psp-2.6.32/pending/0005-Revert-Revert-OMAP-DSS2-FIFI-UNDERFLOW-issue-fix.patch
@@ -0,0 +1,198 @@
+From a107c9c4bd642fd5044275ffcb00a8e20da481c7 Mon Sep 17 00:00:00 2001
+From: Vaibhav Hiremath <hvaibhav@ti.com>
+Date: Tue, 10 Aug 2010 20:05:51 +0530
+Subject: [PATCH 5/9] Revert "Revert "OMAP: DSS2: FIFI UNDERFLOW issue fixed""
+
+This reverts commit b2c74dc43741d8d824e5439f6a82c0a5aa5d1c80.
+
+There was small bug in the GFX UNDERFLOW patch, so I had reverted it and now
+since I have fix for the same so I am again commiting the fix which reverts the
+original patch with fix.
+
+Original commit - 4b58d194fd8f5a1c68803eb326e9a71621571696.
+Revert commit - b2c74dc43741d8d824e5439f6a82c0a5aa5d1c80
+---
+ drivers/video/omap2/omapfb/omapfb-main.c |   83 ++++++++++++++++++++----------
+ 1 files changed, 55 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
+index ef29983..7f47a34 100644
+--- a/drivers/video/omap2/omapfb/omapfb-main.c
++++ b/drivers/video/omap2/omapfb/omapfb-main.c
+@@ -182,6 +182,11 @@ static unsigned omapfb_get_vrfb_offset(struct omapfb_info *ofbi, int rot)
+ static u32 omapfb_get_region_rot_paddr(struct omapfb_info *ofbi, int rot)
+ {
+ 	if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
++		if (rot == FB_ROTATE_CW)
++			rot = FB_ROTATE_CCW;
++		else if (rot == FB_ROTATE_CCW)
++			rot = FB_ROTATE_CW;
++
+ 		return ofbi->region.vrfb.paddr[rot]
+ 			+ omapfb_get_vrfb_offset(ofbi, rot);
+ 	} else {
+@@ -189,20 +194,32 @@ static u32 omapfb_get_region_rot_paddr(struct omapfb_info *ofbi, int rot)
+ 	}
+ }
+ 
+-static u32 omapfb_get_region_paddr(struct omapfb_info *ofbi)
++static u32 omapfb_get_region_paddr(struct omapfb_info *ofbi, int rot)
+ {
+-	if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
+-		return ofbi->region.vrfb.paddr[0];
+-	else
++	if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
++		if (rot == FB_ROTATE_CW)
++			rot = FB_ROTATE_CCW;
++		else if (rot == FB_ROTATE_CCW)
++			rot = FB_ROTATE_CW;
++
++		return ofbi->region.vrfb.paddr[rot];
++	} else {
+ 		return ofbi->region.paddr;
++	}
+ }
+ 
+-static void __iomem *omapfb_get_region_vaddr(struct omapfb_info *ofbi)
++static void __iomem *omapfb_get_region_vaddr(struct omapfb_info *ofbi, int rot)
+ {
+-	if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
+-		return ofbi->region.vrfb.vaddr[0];
+-	else
++	if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
++		if (rot == FB_ROTATE_CW)
++			rot = FB_ROTATE_CCW;
++		else if (rot == FB_ROTATE_CCW)
++			rot = FB_ROTATE_CW;
++
++		return ofbi->region.vrfb.vaddr[rot];
++	} else {
+ 		return ofbi->region.vaddr;
++	}
+ }
+ 
+ static struct omapfb_colormode omapfb_colormodes[] = {
+@@ -501,7 +518,7 @@ static int setup_vrfb_rotation(struct fb_info *fbi)
+ 	unsigned bytespp;
+ 	bool yuv_mode;
+ 	enum omap_color_mode mode;
+-	int r;
++	int r, rotation = var->rotate;
+ 	bool reconf;
+ 
+ 	if (!rg->size || ofbi->rotation_type != OMAP_DSS_ROT_VRFB)
+@@ -509,6 +526,11 @@ static int setup_vrfb_rotation(struct fb_info *fbi)
+ 
+ 	DBG("setup_vrfb_rotation\n");
+ 
++	if (rotation == FB_ROTATE_CW)
++		rotation = FB_ROTATE_CCW;
++	else if (rotation == FB_ROTATE_CCW)
++		rotation = FB_ROTATE_CW;
++
+ 	r = fb_mode_to_dss_mode(var, &mode);
+ 	if (r)
+ 		return r;
+@@ -532,32 +554,35 @@ static int setup_vrfb_rotation(struct fb_info *fbi)
+ 			vrfb->yres != var->yres_virtual)
+ 		reconf = true;
+ 
+-	if (vrfb->vaddr[0] && reconf) {
++	if (vrfb->vaddr[rotation] && reconf) {
+ 		fbi->screen_base = NULL;
+ 		fix->smem_start = 0;
+ 		fix->smem_len = 0;
+-		iounmap(vrfb->vaddr[0]);
+-		vrfb->vaddr[0] = NULL;
++		iounmap(vrfb->vaddr[rotation]);
++		vrfb->vaddr[rotation] = NULL;
+ 		DBG("setup_vrfb_rotation: reset fb\n");
+ 	}
+ 
+-	if (vrfb->vaddr[0])
++	if (vrfb->vaddr[rotation])
+ 		return 0;
+ 
+-	omap_vrfb_setup(&rg->vrfb, rg->paddr,
+-			var->xres_virtual,
+-			var->yres_virtual,
+-			bytespp, yuv_mode);
++	if (rotation == FB_ROTATE_CW || rotation == FB_ROTATE_CCW)
++		omap_vrfb_setup(&rg->vrfb, rg->paddr,
++				var->yres_virtual, var->xres_virtual,
++				bytespp, yuv_mode);
++	else
++		omap_vrfb_setup(&rg->vrfb, rg->paddr,
++				var->xres_virtual, var->yres_virtual,
++				bytespp, yuv_mode);
+ 
+-	/* Now one can ioremap the 0 angle view */
+-	r = omap_vrfb_map_angle(vrfb, var->yres_virtual, 0);
++	/* Now one can ioremap the rotation angle view */
++	r = omap_vrfb_map_angle(vrfb, var->yres_virtual, rotation);
+ 	if (r)
+ 		return r;
+-
+ 	/* used by open/write in fbmem.c */
+-	fbi->screen_base = ofbi->region.vrfb.vaddr[0];
++	fbi->screen_base = ofbi->region.vrfb.vaddr[rotation];
+ 
+-	fix->smem_start = ofbi->region.vrfb.paddr[0];
++	fix->smem_start = ofbi->region.vrfb.paddr[rotation];
+ 
+ 	switch (var->nonstd) {
+ 	case OMAPFB_COLOR_YUV422:
+@@ -601,7 +626,8 @@ void set_fb_fix(struct fb_info *fbi)
+ 	DBG("set_fb_fix\n");
+ 
+ 	/* used by open/write in fbmem.c */
+-	fbi->screen_base = (char __iomem *)omapfb_get_region_vaddr(ofbi);
++	fbi->screen_base = (char __iomem *)omapfb_get_region_vaddr(ofbi,
++			var->rotate);
+ 
+ 	/* used by mmap in fbmem.c */
+ 	if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
+@@ -624,7 +650,7 @@ void set_fb_fix(struct fb_info *fbi)
+ 		fix->smem_len = rg->size;
+ 	}
+ 
+-	fix->smem_start = omapfb_get_region_paddr(ofbi);
++	fix->smem_start = omapfb_get_region_paddr(ofbi, var->rotate);
+ 
+ 	fix->type = FB_TYPE_PACKED_PIXELS;
+ 
+@@ -860,11 +886,11 @@ static int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
+ 
+ 
+ 	if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
+-		data_start_p = omapfb_get_region_rot_paddr(ofbi, rotation);
++		data_start_p = omapfb_get_region_rot_paddr(ofbi, 0);
+ 		data_start_v = NULL;
+ 	} else {
+-		data_start_p = omapfb_get_region_paddr(ofbi);
+-		data_start_v = omapfb_get_region_vaddr(ofbi);
++		data_start_p = omapfb_get_region_paddr(ofbi, 0);
++		data_start_v = omapfb_get_region_vaddr(ofbi, 0);
+ 	}
+ 
+ 	if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
+@@ -1076,6 +1102,7 @@ static struct vm_operations_struct mmap_user_ops = {
+ static int omapfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
+ {
+ 	struct omapfb_info *ofbi = FB2OFB(fbi);
++	struct fb_var_screeninfo *var = &fbi->var;
+ 	struct fb_fix_screeninfo *fix = &fbi->fix;
+ 	unsigned long off;
+ 	unsigned long start;
+@@ -1087,7 +1114,7 @@ static int omapfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
+ 		return -EINVAL;
+ 	off = vma->vm_pgoff << PAGE_SHIFT;
+ 
+-	start = omapfb_get_region_paddr(ofbi);
++	start = omapfb_get_region_paddr(ofbi, var->rotate);
+ 	len = fix->smem_len;
+ 	if (off >= len)
+ 		return -EINVAL;
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-psp-2.6.32/pending/0006-modules-Skip-empty-sections-when-exporting-section.patch b/recipes/linux/linux-omap-psp-2.6.32/pending/0006-modules-Skip-empty-sections-when-exporting-section.patch
new file mode 100644
index 0000000000..3ca7d2ef2b
--- /dev/null
+++ b/recipes/linux/linux-omap-psp-2.6.32/pending/0006-modules-Skip-empty-sections-when-exporting-section.patch
@@ -0,0 +1,84 @@
+From 412656ce83a2605119dc1a7bc5492a13240dc666 Mon Sep 17 00:00:00 2001
+From: Ben Hutchings <ben@decadent.org.uk>
+Date: Sat, 19 Dec 2009 14:43:01 +0000
+Subject: [PATCH 6/9] modules: Skip empty sections when exporting section notes
+
+Commit 35dead4 "modules: don't export section names of empty sections
+via sysfs" changed the set of sections that have attributes, but did
+not change the iteration over these attributes in add_notes_attrs().
+This can lead to add_notes_attrs() creating attributes with the wrong
+names or with null name pointers.
+
+Introduce a sect_empty() function and use it in both add_sect_attrs()
+and add_notes_attrs().
+
+Reported-by: Martin Michlmayr <tbm@cyrius.com>
+Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
+Tested-by: Martin Michlmayr <tbm@cyrius.com>
+Cc: stable@kernel.org
+Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+Signed-off-by: Sanjeev Premi <premi@ti.com>
+---
+ kernel/module.c |   17 ++++++++++-------
+ 1 files changed, 10 insertions(+), 7 deletions(-)
+
+diff --git a/kernel/module.c b/kernel/module.c
+index 12afc5a..a1b4a43 100644
+--- a/kernel/module.c
++++ b/kernel/module.c
+@@ -996,6 +996,12 @@ static const struct kernel_symbol *resolve_symbol(Elf_Shdr *sechdrs,
+  * J. Corbet <corbet@lwn.net>
+  */
+ #if defined(CONFIG_KALLSYMS) && defined(CONFIG_SYSFS)
++
++static inline bool sect_empty(const Elf_Shdr *sect)
++{
++	return !(sect->sh_flags & SHF_ALLOC) || sect->sh_size == 0;
++}
++
+ struct module_sect_attr
+ {
+ 	struct module_attribute mattr;
+@@ -1037,8 +1043,7 @@ static void add_sect_attrs(struct module *mod, unsigned int nsect,
+ 
+ 	/* Count loaded sections and allocate structures */
+ 	for (i = 0; i < nsect; i++)
+-		if (sechdrs[i].sh_flags & SHF_ALLOC
+-		    && sechdrs[i].sh_size)
++		if (!sect_empty(&sechdrs[i]))
+ 			nloaded++;
+ 	size[0] = ALIGN(sizeof(*sect_attrs)
+ 			+ nloaded * sizeof(sect_attrs->attrs[0]),
+@@ -1056,9 +1061,7 @@ static void add_sect_attrs(struct module *mod, unsigned int nsect,
+ 	sattr = &sect_attrs->attrs[0];
+ 	gattr = &sect_attrs->grp.attrs[0];
+ 	for (i = 0; i < nsect; i++) {
+-		if (! (sechdrs[i].sh_flags & SHF_ALLOC))
+-			continue;
+-		if (!sechdrs[i].sh_size)
++		if (sect_empty(&sechdrs[i]))
+ 			continue;
+ 		sattr->address = sechdrs[i].sh_addr;
+ 		sattr->name = kstrdup(secstrings + sechdrs[i].sh_name,
+@@ -1142,7 +1145,7 @@ static void add_notes_attrs(struct module *mod, unsigned int nsect,
+ 	/* Count notes sections and allocate structures.  */
+ 	notes = 0;
+ 	for (i = 0; i < nsect; i++)
+-		if ((sechdrs[i].sh_flags & SHF_ALLOC) &&
++		if (!sect_empty(&sechdrs[i]) &&
+ 		    (sechdrs[i].sh_type == SHT_NOTE))
+ 			++notes;
+ 
+@@ -1158,7 +1161,7 @@ static void add_notes_attrs(struct module *mod, unsigned int nsect,
+ 	notes_attrs->notes = notes;
+ 	nattr = &notes_attrs->attrs[0];
+ 	for (loaded = i = 0; i < nsect; ++i) {
+-		if (!(sechdrs[i].sh_flags & SHF_ALLOC))
++		if (sect_empty(&sechdrs[i]))
+ 			continue;
+ 		if (sechdrs[i].sh_type == SHT_NOTE) {
+ 			nattr->attr.name = mod->sect_attrs->attrs[loaded].name;
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-psp-2.6.32/pending/0007-RTC-s35390a-Bug-Fix-Pie-mode-doesn-t-work.patch b/recipes/linux/linux-omap-psp-2.6.32/pending/0007-RTC-s35390a-Bug-Fix-Pie-mode-doesn-t-work.patch
new file mode 100644
index 0000000000..6dd2b95bd0
--- /dev/null
+++ b/recipes/linux/linux-omap-psp-2.6.32/pending/0007-RTC-s35390a-Bug-Fix-Pie-mode-doesn-t-work.patch
@@ -0,0 +1,68 @@
+From 243e09d50e7a03eb9fc8e7313784f2ed96602890 Mon Sep 17 00:00:00 2001
+From: Vaibhav Hiremath <hvaibhav@ti.com>
+Date: Fri, 13 Aug 2010 19:23:23 +0530
+Subject: [PATCH 7/9] RTC:s35390a:Bug Fix: Pie mode doesn't work
+
+Due to some race condition between Work and ISR, somehow interrupt
+is not getting enabled and because of this RTC interrupt was not working.
+---
+ drivers/rtc/rtc-s35390a.c |   21 ++++++++++-----------
+ 1 files changed, 10 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/rtc/rtc-s35390a.c b/drivers/rtc/rtc-s35390a.c
+index de597c1..b30a57c 100644
+--- a/drivers/rtc/rtc-s35390a.c
++++ b/drivers/rtc/rtc-s35390a.c
+@@ -230,11 +230,15 @@ static int s35390a_freq_irq_enable(struct i2c_client *client, unsigned enabled)
+ 		return err;
+ 	}
+ 
+-	buf[0] = s35390a->rtc->irq_freq;
+-	/* This chip expects the bits of each byte to be in reverse order */
+-	buf[0] = bitrev8(buf[0]);
++	if (enabled) {
++		buf[0] = s35390a->rtc->irq_freq;
+ 
+-	return s35390a_set_reg(s35390a, S35390A_CMD_INT1_REG1, buf, sizeof(buf));
++		buf[0] = bitrev8(buf[0]);
++		err = s35390a_set_reg(s35390a, S35390A_CMD_INT1_REG1, buf,
++				sizeof(buf));
++	}
++
++	return err;
+ }
+ 
+ static int s35390a_rtc_freq_irq_enable(struct device *dev, int enabled)
+@@ -419,20 +423,14 @@ static void s35390a_work(struct work_struct *work)
+ 		/* Notify RTC core on event */
+ 		rtc_update_irq(s35390a->rtc, 1, RTC_IRQF | RTC_AF);
+ 		s35390a_alarm_irq_enable(client, 0);
+-		enable_irq(client->irq);
+ 	} else if (buf[0] & BIT(0)) {
+ 		/* Notify RTC core on event */
+ 		rtc_update_irq(s35390a->rtc, 1, RTC_PF | RTC_IRQF);
+-		s35390a_freq_irq_enable(client, 0);
+-		enable_irq(client->irq);
+-		s35390a_freq_irq_enable(client, 1);
+ 	} else if (buf[0] & BIT(1)) {
+ 		/* Notify RTC core on event */
+ 		rtc_update_irq(s35390a->rtc, 1, RTC_UF | RTC_IRQF);
+-		s35390a_update_irq_enable(client, 0);
+-		enable_irq(client->irq);
+-		s35390a_update_irq_enable(client, 1);
+ 	}
++	enable_irq(client->irq);
+ out:
+ 	return;
+ }
+@@ -559,6 +557,7 @@ static int s35390a_probe(struct i2c_client *client,
+ 	}
+ 	s35390a->rtc->irq_freq = 0;
+ 	s35390a->rtc->max_user_freq = 16;
++
+ 	return 0;
+ 
+ exit_intr:
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-psp-2.6.32/pending/0008-OMAP3EVM-Set-minimum-throughput-requirement-for-DSS.patch b/recipes/linux/linux-omap-psp-2.6.32/pending/0008-OMAP3EVM-Set-minimum-throughput-requirement-for-DSS.patch
new file mode 100644
index 0000000000..e567ed70d7
--- /dev/null
+++ b/recipes/linux/linux-omap-psp-2.6.32/pending/0008-OMAP3EVM-Set-minimum-throughput-requirement-for-DSS.patch
@@ -0,0 +1,71 @@
+From ba573a248dc8c33ff21fc4efbfea0ca85cdbc5d0 Mon Sep 17 00:00:00 2001
+From: Ranjith Lohithakshan <ranjithl@ti.com>
+Date: Tue, 7 Sep 2010 10:05:11 +0530
+Subject: [PATCH 8/9] OMAP3EVM: Set minimum throughput requirement for DSS
+
+GFX_FIFO_UNDERFLOW has been observed when the L3 rate is lowered
+below 100MHz or so. Once this underflow happens the display stops
+working.
+
+This patch puts a minimum bus throughput requirement when lcd, tv
+or dvi displays are enabled. The throughput is calculated in such
+a manner that it will translate into a minimum L3 rate of 100MHz.
+
+Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
+---
+ arch/arm/mach-omap2/board-omap3evm.c |    8 ++++++++
+ 1 files changed, 8 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
+index eb7ad1c..710a25d 100644
+--- a/arch/arm/mach-omap2/board-omap3evm.c
++++ b/arch/arm/mach-omap2/board-omap3evm.c
+@@ -422,12 +422,15 @@ static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev)
+ 	else
+ 		gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
+ 
++	omap_pm_set_min_bus_tput(&dssdev->dev, OCP_INITIATOR_AGENT, 400000);
++
+ 	lcd_enabled = 1;
+ 	return 0;
+ }
+ 
+ static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev)
+ {
++	omap_pm_set_min_bus_tput(&dssdev->dev, OCP_INITIATOR_AGENT, 0);
+ 	gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1);
+ 
+ 	if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
+@@ -449,11 +452,13 @@ static struct omap_dss_device omap3_evm_lcd_device = {
+ 
+ static int omap3_evm_enable_tv(struct omap_dss_device *dssdev)
+ {
++	omap_pm_set_min_bus_tput(&dssdev->dev, OCP_INITIATOR_AGENT, 400000);
+ 	return 0;
+ }
+ 
+ static void omap3_evm_disable_tv(struct omap_dss_device *dssdev)
+ {
++	omap_pm_set_min_bus_tput(&dssdev->dev, OCP_INITIATOR_AGENT, 0);
+ }
+ 
+ static struct omap_dss_device omap3_evm_tv_device = {
+@@ -488,12 +493,15 @@ static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev)
+ 		omap_mux_set_gpio(OMAP_MUX_MODE3, 3);
+ 	}
+ 
++	omap_pm_set_min_bus_tput(&dssdev->dev, OCP_INITIATOR_AGENT, 400000);
++
+ 	dvi_enabled = 1;
+ 	return 0;
+ }
+ 
+ static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev)
+ {
++	omap_pm_set_min_bus_tput(&dssdev->dev, OCP_INITIATOR_AGENT, 0);
+ 	gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 0);
+ 
+ 	dvi_enabled = 0;
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-psp-2.6.32/pending/0009-ehci-fix-device-detect-issue-with-modules.patch b/recipes/linux/linux-omap-psp-2.6.32/pending/0009-ehci-fix-device-detect-issue-with-modules.patch
new file mode 100644
index 0000000000..c0d4131982
--- /dev/null
+++ b/recipes/linux/linux-omap-psp-2.6.32/pending/0009-ehci-fix-device-detect-issue-with-modules.patch
@@ -0,0 +1,159 @@
+From 39bf598ec0579e3bfc55f9038eccaaa5e2755c70 Mon Sep 17 00:00:00 2001
+From: Ajay Kumar Gupta <ajay.gupta@ti.com>
+Date: Thu, 17 Jun 2010 13:58:46 +0530
+Subject: [PATCH 9/9] ehci: fix device detect issue with modules
+
+Currently devices don't get detected automatically if the ehci
+module is inserted 2nd time onward. We need to disconnect and
+reconnect the device for it to get detected and enumerated.
+
+Resetting the USB PHY after the EHCI controller has been initilized
+fixes this issue.
+
+Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
+---
+ drivers/usb/host/ehci-omap.c |   86 ++++++++++++++++++-----------------------
+ 1 files changed, 38 insertions(+), 48 deletions(-)
+
+diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
+index 0f8fbf5..7d3a150 100644
+--- a/drivers/usb/host/ehci-omap.c
++++ b/drivers/usb/host/ehci-omap.c
+@@ -411,6 +411,31 @@ static void omap_usb_utmi_init(struct ehci_hcd_omap *omap, u8 tll_channel_mask)
+ 
+ /*-------------------------------------------------------------------------*/
+ 
++void ehci_omap_phy_reset(struct ehci_hcd_omap *omap)
++{
++	if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) &&
++			gpio_is_valid(omap->reset_gpio_port[0])) {
++		gpio_request(omap->reset_gpio_port[0], "HSUSB0 reset");
++		gpio_direction_output(omap->reset_gpio_port[0], 0);
++	}
++
++	if ((omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) &&
++			gpio_is_valid(omap->reset_gpio_port[1])) {
++		gpio_request(omap->reset_gpio_port[1], "HSUSB1 reset");
++		gpio_direction_output(omap->reset_gpio_port[1], 0);
++	}
++
++	/* Hold the PHY in RESET for enough time till DIR is high */
++	udelay(10);
++
++	if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) &&
++			gpio_is_valid(omap->reset_gpio_port[0]))
++		gpio_set_value(omap->reset_gpio_port[0], 1);
++	if ((omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) &&
++			gpio_is_valid(omap->reset_gpio_port[1]))
++		gpio_set_value(omap->reset_gpio_port[1], 1);
++}
++
+ /* omap_start_ehc
+  *	- Start the TI USBHOST controller
+  */
+@@ -445,24 +470,6 @@ static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
+ 	}
+ 	clk_enable(omap->usbhost1_48m_fck);
+ 
+-	if (omap->phy_reset) {
+-		/* Refer: ISSUE1 */
+-		if (gpio_is_valid(omap->reset_gpio_port[0])) {
+-			gpio_request(omap->reset_gpio_port[0],
+-						"USB1 PHY reset");
+-			gpio_direction_output(omap->reset_gpio_port[0], 0);
+-		}
+-
+-		if (gpio_is_valid(omap->reset_gpio_port[1])) {
+-			gpio_request(omap->reset_gpio_port[1],
+-						"USB2 PHY reset");
+-			gpio_direction_output(omap->reset_gpio_port[1], 0);
+-		}
+-
+-		/* Hold the PHY in RESET for enough time till DIR is high */
+-		udelay(10);
+-	}
+-
+ 	/* Configure TLL for 60Mhz clk for ULPI */
+ 	omap->usbtll_fck = clk_get(omap->dev, "usbtll_fck");
+ 	if (IS_ERR(omap->usbtll_fck)) {
+@@ -576,20 +583,6 @@ static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
+ 		omap_usb_utmi_init(omap, tll_ch_mask);
+ 	}
+ 
+-	if (omap->phy_reset) {
+-		/* Refer ISSUE1:
+-		 * Hold the PHY in RESET for enough time till
+-		 * PHY is settled and ready
+-		 */
+-		udelay(10);
+-
+-		if (gpio_is_valid(omap->reset_gpio_port[0]))
+-			gpio_set_value(omap->reset_gpio_port[0], 1);
+-
+-		if (gpio_is_valid(omap->reset_gpio_port[1]))
+-			gpio_set_value(omap->reset_gpio_port[1], 1);
+-	}
+-
+ 	return 0;
+ 
+ err_sys_status:
+@@ -604,14 +597,6 @@ err_tll_fck:
+ 	clk_disable(omap->usbhost1_48m_fck);
+ 	clk_put(omap->usbhost1_48m_fck);
+ 
+-	if (omap->phy_reset) {
+-		if (gpio_is_valid(omap->reset_gpio_port[0]))
+-			gpio_free(omap->reset_gpio_port[0]);
+-
+-		if (gpio_is_valid(omap->reset_gpio_port[1]))
+-			gpio_free(omap->reset_gpio_port[1]);
+-	}
+-
+ err_host_48m_fck:
+ 	clk_disable(omap->usbhost2_120m_fck);
+ 	clk_put(omap->usbhost2_120m_fck);
+@@ -697,14 +682,6 @@ static void omap_stop_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
+ 		omap->usbtll_ick = NULL;
+ 	}
+ 
+-	if (omap->phy_reset) {
+-		if (gpio_is_valid(omap->reset_gpio_port[0]))
+-			gpio_free(omap->reset_gpio_port[0]);
+-
+-		if (gpio_is_valid(omap->reset_gpio_port[1]))
+-			gpio_free(omap->reset_gpio_port[1]);
+-	}
+-
+ 	dev_dbg(omap->dev, "Clock to USB host has been disabled\n");
+ }
+ 
+@@ -1033,6 +1010,10 @@ static int ehci_hcd_omap_probe(struct platform_device *pdev)
+ 	/* here we "know" root ports should always stay powered */
+ 	ehci_port_power(omap->ehci, 1);
+ 
++	/* reset the USB PHY */
++	if (omap->phy_reset)
++		ehci_omap_phy_reset(omap);
++
+ 	return 0;
+ 
+ err_add_hcd:
+@@ -1083,6 +1064,15 @@ static int ehci_hcd_omap_remove(struct platform_device *pdev)
+ 
+ 	usb_remove_hcd(hcd);
+ 	omap_stop_ehc(omap, hcd);
++
++	if (omap->phy_reset) {
++		if (gpio_is_valid(omap->reset_gpio_port[0]))
++			gpio_free(omap->reset_gpio_port[0]);
++
++		if (gpio_is_valid(omap->reset_gpio_port[1]))
++			gpio_free(omap->reset_gpio_port[1]);
++	}
++
+ 	iounmap(hcd->regs);
+ 	for (i = 0 ; i < OMAP3_HS_USB_PORTS ; i++) {
+ 		if (omap->regulator[i]) {
+-- 
+1.6.2.4
+
diff --git a/recipes/linux/linux-omap-psp_2.6.32.bb b/recipes/linux/linux-omap-psp_2.6.32.bb
index 3d31f7d973..7d0118df69 100644
--- a/recipes/linux/linux-omap-psp_2.6.32.bb
+++ b/recipes/linux/linux-omap-psp_2.6.32.bb
@@ -134,6 +134,15 @@ SRC_URI = "git://arago-project.org/git/people/sriram/ti-psp-omap.git;protocol=gi
            file://0001-BeagleBoard-Adjust-USER-button-pin-for-xM.patch \
            file://cam/0001-omap3beagle-Add-camera-bootarg.patch \
            file://porches.patch \
+           file://pending/0001-OMAP3-SDRC-add-100MHz-timing-data-for-Hynix-H8KDS0.patch \
+           file://pending/0002-omap3-Fix-voltage-and-frequency-scaling-order-when.patch \
+           file://pending/0003-OMAP3-PM-Introduce-Smartreflex-support-on-OMAP3630.patch \
+           file://pending/0004-OMAP3630-PM-implement-Foward-Body-Bias-for-OPP1G.patch \
+           file://pending/0005-Revert-Revert-OMAP-DSS2-FIFI-UNDERFLOW-issue-fix.patch \
+           file://pending/0006-modules-Skip-empty-sections-when-exporting-section.patch \
+           file://pending/0007-RTC-s35390a-Bug-Fix-Pie-mode-doesn-t-work.patch \
+           file://pending/0008-OMAP3EVM-Set-minimum-throughput-requirement-for-DSS.patch \
+           file://pending/0009-ehci-fix-device-detect-issue-with-modules.patch \
            file://defconfig"
 
 SRC_URI_append_beagleboard = " file://logo_linux_clut224.ppm \