1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
|
From 930d9fb1e5971e4012ee081c60b578b83d8dc928 Mon Sep 17 00:00:00 2001
From: Vaibhav Hiremath <hvaibhav@ti.com>
Date: Mon, 15 Jun 2009 20:59:26 +0530
Subject: [PATCH 09/16] OMAP3517PRE-ALPHA: DDR size issue fixed.
U-Boot was printing DDR size as 0, as of now hard-coded it with
macro (defined in include/configs/omap3517evm.h).
TODO:
- Ideally it should calculate the size baded on EMIF configuration
made by primary bootloader (x-loader).
---
cpu/arm_cortexa8/omap3/board.c | 13 ++-----------
cpu/arm_cortexa8/omap3/mem.c | 17 +++++++++++++++++
cpu/arm_cortexa8/omap3/sys_info.c | 5 +++++
include/configs/omap3517evm.h | 5 +++++
4 files changed, 29 insertions(+), 11 deletions(-)
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index 15834fd..ea94e59 100644
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@ -275,33 +275,24 @@ void watchdog_init(void)
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
- unsigned int size0 = 0, size1 = 0;
+ unsigned long size0 = 0, size1 = 0;
u32 btype;
btype = get_board_type();
display_board_info(btype);
+ size0 = get_sdr_cs_size(CS0);
/*
* If a second bank of DDR is attached to CS1 this is
* where it can be started. Early init code will init
* memory on CS0.
*/
if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
-#if defined (CONFIG_OMAP35XX)
- emif4_init();
- /*
- * TODO: Need to implement function to calculate
- * DDR size depending on row and coloum size
- */
- size0 = 128 * 1024 * 1024;
-#elif defined (CONFIG_OMAP34XX)
do_sdrc_init(CS1, NOT_EARLY);
make_cs1_contiguous();
- size0 = get_sdr_cs_size(CS0);
size1 = get_sdr_cs_size(CS1);
-#endif
}
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
index 7fb05eb..49047b4 100644
--- a/cpu/arm_cortexa8/omap3/mem.c
+++ b/cpu/arm_cortexa8/omap3/mem.c
@@ -254,6 +254,23 @@ void do_sdrc_init(u32 cs, u32 early)
writel(0, &sdrc_base->cs[cs].mcfg);
}
+unsigned long calc_size_from_emif4(int cs)
+{
+ unsigned int size;
+#if 0
+ unsigned int reg_pagesize, reg_ebank, reg_ibank, reg_rowsize;
+
+ /*
+ * TODO: Calculate the DDR size based on EMIF configuration
+ * done by x-loader.
+ */
+ size =
+#else
+ size = CONFIG_SYS_CS0_SIZE;
+#endif
+
+ return size;
+}
/********************************************************
* emif4 _init() - init the emif4 module for DDR access
* - early init routines, called from flash or
diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c
index b385b91..8077ecf 100644
--- a/cpu/arm_cortexa8/omap3/sys_info.c
+++ b/cpu/arm_cortexa8/omap3/sys_info.c
@@ -107,10 +107,15 @@ u32 get_sdr_cs_size(u32 cs)
{
u32 size;
+#if defined (CONFIG_OMAP35XX)
+ size = calc_size_from_emif4(cs);
+#elif defined (CONFIG_OMAP34XX)
/* get ram size field */
size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
size &= 0x3FF; /* remove unwanted bits */
size *= SZ_2M; /* find size in MB */
+#endif
+
return size;
}
diff --git a/include/configs/omap3517evm.h b/include/configs/omap3517evm.h
index 558538b..c434b71 100644
--- a/include/configs/omap3517evm.h
+++ b/include/configs/omap3517evm.h
@@ -67,6 +67,11 @@
/* initial data */
/*
+ * DDR size interfaced
+ */
+#define CONFIG_SYS_CS0_SIZE SZ_256M
+
+/*
* Hardware drivers
*/
--
1.6.2.4
|
