summaryrefslogtreecommitdiff
path: root/recipes/u-boot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-streamline-the-83xx-immr-head-file.patch
blob: 30981dc43c99839df9453bb69030909d9bac52d4 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
ce4d6db21531bc35da7180436c6f49efac7c0461
diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c
index 36d901f..9c35e22 100644
--- a/board/tqm834x/tqm834x.c
+++ b/board/tqm834x/tqm834x.c
@@ -148,14 +148,14 @@ int checkboard (void)
 	u32 w, f;
 
 	immr = (immap_t *)CFG_IMMR;
-	if (!(immr->reset.rcwh & RCWH_PCIHOST)) {
+	if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) {
 		printf("PCI:   NOT in host mode..?!\n");
 		return 0;
 	}
 
 	/* get bus width */
 	w = 32;
-	if (immr->reset.rcwh & RCWH_PCI64)
+	if (immr->reset.rcwh & HRCWH_64_BIT_PCI)
 		w = 64;
 
 	/* get clock */
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index e5725fb..7574fab 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -202,12 +202,12 @@ void cpu_init_f (volatile immap_t * im)
 	im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
 #endif
 #ifdef CFG_GPIO1_PRELIM
-	im->pgio[0].dir = CFG_GPIO1_DIR;
-	im->pgio[0].dat = CFG_GPIO1_DAT;
+	im->gpio[0].dir = CFG_GPIO1_DIR;
+	im->gpio[0].dat = CFG_GPIO1_DAT;
 #endif
 #ifdef CFG_GPIO2_PRELIM
-	im->pgio[1].dir = CFG_GPIO2_DIR;
-	im->pgio[1].dat = CFG_GPIO2_DAT;
+	im->gpio[1].dir = CFG_GPIO2_DIR;
+	im->gpio[1].dat = CFG_GPIO2_DAT;
 #endif
 }
 
diff --git a/cpu/mpc83xx/qe_io.c b/cpu/mpc83xx/qe_io.c
index ebe3487..8b3937a 100644
--- a/cpu/mpc83xx/qe_io.c
+++ b/cpu/mpc83xx/qe_io.c
@@ -35,7 +35,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
 	u32			pin_1bit_mask;
 	u32			tmp_val;
 	volatile immap_t	*im = (volatile immap_t *)CFG_IMMR;
-	volatile gpio83xx_t	*par_io =(volatile gpio83xx_t *)&im->gpio;
+	volatile qepio83xx_t	*par_io = (volatile qepio83xx_t *)&im->qepio;
 
 	/* Caculate pin location and 2bit mask and dir */
 	pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 7e53b1e..40ba6b0 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -139,7 +139,7 @@ int get_clocks(void)
 #endif
 	}
 
-	spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT);
+	spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT);
 	csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
 
 	sccr = im->clk.sccr;
@@ -251,7 +251,7 @@ int get_clocks(void)
 	}
 #if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
 	lbiu_clk = csb_clk *
-	           (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
+	           (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
 #else
 #error Unknown MPC83xx chip
 #endif
@@ -268,11 +268,11 @@ int get_clocks(void)
 	}
 #if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
 	ddr_clk = csb_clk *
-		  (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
-	corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT;
+		  (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
+	corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
 #if defined (CONFIG_MPC8360)
 	ddr_sec_clk = csb_clk * (1 +
-		       ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
+		       ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
 #endif
 #else
 #error Unknown MPC83xx chip
@@ -307,8 +307,8 @@ int get_clocks(void)
 	}
 
 #if defined (CONFIG_MPC8360)
-	qepmf = (im->reset.rcwl & RCWL_CEPMF) >> RCWL_CEPMF_SHIFT;
-	qepdf = (im->reset.rcwl & RCWL_CEPDF) >> RCWL_CEPDF_SHIFT;
+	qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT;
+	qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT;
 	qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
 	brg_clk = qe_clk / 2;
 #endif
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 43cde5e..67b035c 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -3,20 +3,11 @@
  *
  * MPC83xx Internal Memory Map
  *
- * History :
- * 20060601: Daveliu (daveliu@freescale.com)
- *	     TanyaJiang (tanya.jiang@freescale.com)
- *	     Unified variable names for mpc83xx
- * 2005	   : Mandy Lavi (mandy.lavi@freescale.com)
- *	     support for mpc8360e
- * 2004	   : Eran Liberty (liberty@freescale.com)
- *	     Initialized for mpc8349
- *	     based on:
- *	     MPC8260 Internal Memory Map
- *	     Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
- *	     MPC85xx Internal Memory Map
- *	     Copyright(c) 2002,2003 Motorola Inc.
- *	     Xianghua Xiao (x.xiao@motorola.com)
+ * Contributors:
+ *	Dave Liu <daveliu@freescale.com>
+ *	Tanya Jiang <tanya.jiang@freescale.com>
+ *	Mandy Lavi <mandy.lavi@freescale.com>
+ *	Eran Liberty <liberty@freescale.com>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -25,7 +16,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -37,36 +28,24 @@
 #ifndef __IMMAP_83xx__
 #define __IMMAP_83xx__
 
-#include <config.h>
 #include <asm/types.h>
 #include <asm/fsl_i2c.h>
 
 /*
- * Local Access Window.
+ * Local Access Window
  */
 typedef struct law83xx {
 	u32 bar;		/* LBIU local access window base address register */
-/* Identifies the 20 most-significant address bits of the base of local
- * access window n. The specified base address should be aligned to the
- * window size, as defined by LBLAWARn[SIZE].
- */
-#define LAWBAR_BAR	   0xFFFFF000
-#define LAWBAR_RES	     ~(LAWBAR_BAR)
 	u32 ar;			/* LBIU local access window attribute register */
 } law83xx_t;
 
 /*
- * System configuration registers.
+ * System configuration registers
  */
 typedef struct sysconf83xx {
 	u32 immrbar;		/* Internal memory map base address register */
 	u8 res0[0x04];
 	u32 altcbar;		/* Alternate configuration base address register */
-/* Identifies the12 most significant address bits of an alternate base
- * address used for boot sequencer configuration accesses.
- */
-#define ALTCBAR_BASE_ADDR     0xFFF00000
-#define ALTCBAR_RES	      ~(ALTCBAR_BASE_ADDR)	/* Reserved. Write has no effect, read returns 0. */
 	u8 res1[0x14];
 	law83xx_t lblaw[4];	/* LBIU local access window */
 	u8 res2[0x20];
@@ -77,115 +56,10 @@ typedef struct sysconf83xx {
 	u32 sgprl;		/* System General Purpose Register Low */
 	u32 sgprh;		/* System General Purpose Register High */
 	u32 spridr;		/* System Part and Revision ID Register */
-#define SPRIDR_PARTID	      0xFFFF0000	/* Part Identification. */
-#define SPRIDR_REVID	      0x0000FFFF	/* Revision Identification. */
 	u8 res5[0x04];
 	u32 spcr;		/* System Priority Configuration Register */
-#define SPCR_PCIHPE   0x10000000	/* PCI Highest Priority Enable. */
-#define SPCR_PCIHPE_SHIFT	(31-3)
-#define SPCR_PCIPR    0x03000000	/* PCI bridge system bus request priority. */
-#define SPCR_PCIPR_SHIFT	(31-7)
-#define SPCR_OPT      0x00800000	/* Optimize */
-#define SPCR_TBEN     0x00400000	/* E300 PowerPC core time base unit enable. */
-#define SPCR_TBEN_SHIFT		(31-9)
-#define SPCR_COREPR   0x00300000	/* E300 PowerPC Core system bus request priority. */
-#define SPCR_COREPR_SHIFT	(31-11)
-#if defined (CONFIG_MPC8349)
-#define SPCR_TSEC1DP  0x00003000	/* TSEC1 data priority. */
-#define SPCR_TSEC1DP_SHIFT	(31-19)
-#define SPCR_TSEC1BDP 0x00000C00	/* TSEC1 buffer descriptor priority. */
-#define SPCR_TSEC1BDP_SHIFT	(31-21)
-#define SPCR_TSEC1EP  0x00000300	/* TSEC1 emergency priority. */
-#define SPCR_TSEC1EP_SHIFT	(31-23)
-#define SPCR_TSEC2DP  0x00000030	/* TSEC2 data priority. */
-#define SPCR_TSEC2DP_SHIFT	(31-27)
-#define SPCR_TSEC2BDP 0x0000000C	/* TSEC2 buffer descriptor priority. */
-#define SPCR_TSEC2BDP_SHIFT	(31-29)
-#define SPCR_TSEC2EP  0x00000003	/* TSEC2 emergency priority. */
-#define SPCR_TSEC2EP_SHIFT	(31-31)
-#define SPCR_RES      ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \
-			| SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \
-			| SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP)
-#elif defined (CONFIG_MPC8360)
-#define SPCR_RES      ~(SPCR_PCIHPE|SPCR_PCIPR|SPCR_OPT|SPCR_TBEN|SPCR_COREPR)
-#endif
-	u32 sicrl;		/* System General Purpose Register Low */
-#if defined (CONFIG_MPC8349)
-#define SICRL_LDP_A   0x80000000
-#define SICRL_USB1    0x40000000
-#define SICRL_USB0    0x20000000
-#define SICRL_UART    0x0C000000
-#define SICRL_GPIO1_A 0x02000000
-#define SICRL_GPIO1_B 0x01000000
-#define SICRL_GPIO1_C 0x00800000
-#define SICRL_GPIO1_D 0x00400000
-#define SICRL_GPIO1_E 0x00200000
-#define SICRL_GPIO1_F 0x00180000
-#define SICRL_GPIO1_G 0x00040000
-#define SICRL_GPIO1_H 0x00020000
-#define SICRL_GPIO1_I 0x00010000
-#define SICRL_GPIO1_J 0x00008000
-#define SICRL_GPIO1_K 0x00004000
-#define SICRL_GPIO1_L 0x00003000
-#define SICRL_RES ~(SICRL_LDP_A | SICRL_USB0 | SICRL_USB1 | SICRL_UART \
-			| SICRL_GPIO1_A | SICRL_GPIO1_B | SICRL_GPIO1_C \
-			| SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \
-			| SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \
-			| SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L )
-#elif defined (CONFIG_MPC8360)
-#define SICRL_LDP_A   0xC0000000
-#define SICRL_LCLK_1  0x10000000
-#define SICRL_LCLK_2  0x08000000
-#define SICRL_SRCID_A 0x03000000
-#define SICRL_IRQ_CKSTP_A 0x00C00000
-#define SICRL_RES     ~(SICRL_LDP_A | SICRL_LCLK_1 | SICRL_LCLK_2 | \
-			SICRL_SRCID_A | SICRL_IRQ_CKSTP_A)
-#endif
-	u32 sicrh;		/* System General Purpose Register High */
-#define SICRH_DDR     0x80000000
-#if defined (CONFIG_MPC8349)
-#define SICRH_TSEC1_A 0x10000000
-#define SICRH_TSEC1_B 0x08000000
-#define SICRH_TSEC1_C 0x04000000
-#define SICRH_TSEC1_D 0x02000000
-#define SICRH_TSEC1_E 0x01000000
-#define SICRH_TSEC1_F 0x00800000
-#define SICRH_TSEC2_A 0x00400000
-#define SICRH_TSEC2_B 0x00200000
-#define SICRH_TSEC2_C 0x00100000
-#define SICRH_TSEC2_D 0x00080000
-#define SICRH_TSEC2_E 0x00040000
-#define SICRH_TSEC2_F 0x00020000
-#define SICRH_TSEC2_G 0x00010000
-#define SICRH_TSEC2_H 0x00008000
-#define SICRH_GPIO2_A 0x00004000
-#define SICRH_GPIO2_B 0x00002000
-#define SICRH_GPIO2_C 0x00001000
-#define SICRH_GPIO2_D 0x00000800
-#define SICRH_GPIO2_E 0x00000400
-#define SICRH_GPIO2_F 0x00000200
-#define SICRH_GPIO2_G 0x00000180
-#define SICRH_GPIO2_H 0x00000060
-#define SICRH_TSOBI1  0x00000002
-#define SICRH_TSOBI2  0x00000001
-#define SICRH_RES     ~(  SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \
-			| SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \
-			| SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \
-			| SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \
-			| SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H \
-			| SICRH_GPIO2_A | SICRH_GPIO2_B | SICRH_GPIO2_C \
-			| SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \
-			| SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \
-			| SICRH_TSOBI2)
-#elif defined (CONFIG_MPC8360)
-#define SICRH_SECONDARY_DDR 0x40000000
-#define SICRH_SDDROE   0x02000000	/* SDDRIOE bit from reset configuration word high. */
-#define SICRH_UC1EOBI  0x00000004	/* UCC1 Ethernet Output Buffer Impedance. */
-#define SICRH_UC2E1OBI 0x00000002	/* UCC2 Ethernet pin option 1 Output Buffer Impedance. */
-#define SICRH_UC2E2OBI 0x00000001	/* UCC2 Ethernet pin option 2 Output Buffer Impedance. */
-#define SICRH_RES     ~(SICRH_DDR | SICRH_SECONDARY_DDR | SICRH_SDDROE | \
-			SICRH_UC2E1OBI | SICRH_UC2E2OBI | SICRH_UC2E2OBI)
-#endif
+	u32 sicrl;		/* System I/O Configuration Register Low */
+	u32 sicrh;		/* System I/O Configuration Register High */
 	u8 res6[0xE4];
 } sysconf83xx_t;
 
@@ -196,11 +70,8 @@ typedef struct wdt83xx {
 	u8 res0[4];
 	u32 swcrr;		/* System watchdog control register */
 	u32 swcnr;		/* System watchdog count register */
-#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
-#define SWCNR_RES  ~(SWCNR_SWCN)
 	u8 res1[2];
 	u16 swsrr;		/* System watchdog service register */
-#define SWSRR_WS 0x0000FFFF	/* Software Watchdog Service Field. */
 	u8 res2[0xF0];
 } wdt83xx_t;
 
@@ -209,91 +80,46 @@ typedef struct wdt83xx {
  */
 typedef struct rtclk83xx {
 	u32 cnr;		/* control register */
-#define CNR_CLEN 0x00000080	/* Clock Enable Control Bit  */
-#define CNR_CLIN 0x00000040	/* Input Clock Control Bit  */
-#define CNR_AIM	 0x00000002	/* Alarm Interrupt Mask Bit  */
-#define CNR_SIM	 0x00000001	/* Second Interrupt Mask Bit  */
-#define CNR_RES	 ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM)
 	u32 ldr;		/* load register */
-#define LDR_CLDV 0xFFFFFFFF	/* Contains the 32-bit value to be
-				 * loaded in a 32-bit RTC counter.*/
 	u32 psr;		/* prescale register */
-#define PSR_PRSC 0xFFFFFFFF	/*  RTC Prescaler bits. */
-	u32 ctr;		/* Counter value field register */
-#define CRT_CNTV 0xFFFFFFFF	/* RTC Counter value field. */
+	u32 ctr;		/* counter value field register */
 	u32 evr;		/* event register */
-#define RTEVR_SIF  0x00000001	/* Second Interrupt Flag Bit  */
-#define RTEVR_AIF  0x00000002	/* Alarm Interrupt Flag Bit  */
-#define RTEVR_RES ~(RTEVR_SIF | RTEVR_AIF)
-#define PTEVR_PIF  0x00000001	/* Periodic interrupt flag bit. */
-#define PTEVR_RES ~(PTEVR_PIF)
 	u32 alr;		/* alarm register */
 	u8 res0[0xE8];
 } rtclk83xx_t;
 
 /*
- * Global timper module
+ * Global timer module
  */
-
 typedef struct gtm83xx {
-	u8 cfr1;		/* Timer1/2 Configuration  */
-#define CFR1_PCAS 0x80		/* Pair Cascade mode  */
-#define CFR1_BCM  0x40		/* Backward compatible mode  */
-#define CFR1_STP2 0x20		/* Stop timer  */
-#define CFR1_RST2 0x10		/* Reset timer	*/
-#define CFR1_GM2  0x08		/* Gate mode for pin 2	*/
-#define CFR1_GM1  0x04		/* Gate mode for pin 1	*/
-#define CFR1_STP1 0x02		/* Stop timer  */
-#define CFR1_RST1 0x01		/* Reset timer	*/
-#define CFR1_RES ~(CFR1_PCAS | CFR1_STP2 | CFR1_RST2 | CFR1_GM2 |\
-		 CFR1_GM1 | CFR1_STP1 | CFR1_RST1)
+	u8 cfr1;		/* Timer1/2 Configuration */
 	u8 res0[3];
-	u8 cfr2;		/* Timer3/4 Configuration  */
-#define CFR2_PCAS 0x80		/* Pair Cascade mode  */
-#define CFR2_SCAS 0x40		/* Super Cascade mode  */
-#define CFR2_STP4 0x20		/* Stop timer  */
-#define CFR2_RST4 0x10		/* Reset timer	*/
-#define CFR2_GM4  0x08		/* Gate mode for pin 4	*/
-#define CFR2_GM3  0x04		/* Gate mode for pin 3	*/
-#define CFR2_STP3 0x02		/* Stop timer  */
-#define CFR2_RST3 0x01		/* Reset timer	*/
+	u8 cfr2;		/* Timer3/4 Configuration */
 	u8 res1[10];
-	u16 mdr1;		/* Timer1 Mode Register	 */
-#define MDR_SPS	 0xff00		/* Secondary Prescaler value  */
-#define MDR_CE	 0x00c0		/* Capture edge and enable interrupt  */
-#define MDR_OM	 0x0020		/* Output mode	*/
-#define MDR_ORI	 0x0010		/* Output reference interrupt enable  */
-#define MDR_FRR	 0x0008		/* Free run/restart  */
-#define MDR_ICLK 0x0006		/* Input clock source for the timer  */
-#define MDR_GE	 0x0001		/* Gate enable	*/
-	u16 mdr2;		/* Timer2 Mode Register	 */
-	u16 rfr1;		/* Timer1 Reference Register  */
-	u16 rfr2;		/* Timer2 Reference Register  */
-	u16 cpr1;		/* Timer1 Capture Register  */
-	u16 cpr2;		/* Timer2 Capture Register  */
-	u16 cnr1;		/* Timer1 Counter Register  */
-	u16 cnr2;		/* Timer2 Counter Register  */
-	u16 mdr3;		/* Timer3 Mode Register	 */
-	u16 mdr4;		/* Timer4 Mode Register	 */
-	u16 rfr3;		/* Timer3 Reference Register  */
-	u16 rfr4;		/* Timer4 Reference Register  */
-	u16 cpr3;		/* Timer3 Capture Register  */
-	u16 cpr4;		/* Timer4 Capture Register  */
-	u16 cnr3;		/* Timer3 Counter Register  */
-	u16 cnr4;		/* Timer4 Counter Register  */
-	u16 evr1;		/* Timer1 Event Register  */
-	u16 evr2;		/* Timer2 Event Register  */
-	u16 evr3;		/* Timer3 Event Register  */
-	u16 evr4;		/* Timer4 Event Register  */
-#define GTEVR_REF 0x0002	/* Output reference event  */
-#define GTEVR_CAP 0x0001	/* Counter Capture event   */
-#define GTEVR_RES ~(EVR_CAP|EVR_REF)
-	u16 psr1;		/* Timer1 Prescaler Register  */
-	u16 psr2;		/* Timer2 Prescaler Register  */
-	u16 psr3;		/* Timer3 Prescaler Register  */
-	u16 psr4;		/* Timer4 Prescaler Register  */
-#define GTPSR_PPS  0x00FF	/* Primary Prescaler Bits. */
-#define GTPSR_RES  ~(GTPSR_PPS)
+	u16 mdr1;		/* Timer1 Mode Register */
+	u16 mdr2;		/* Timer2 Mode Register */
+	u16 rfr1;		/* Timer1 Reference Register */
+	u16 rfr2;		/* Timer2 Reference Register */
+	u16 cpr1;		/* Timer1 Capture Register */
+	u16 cpr2;		/* Timer2 Capture Register */
+	u16 cnr1;		/* Timer1 Counter Register */
+	u16 cnr2;		/* Timer2 Counter Register */
+	u16 mdr3;		/* Timer3 Mode Register */
+	u16 mdr4;		/* Timer4 Mode Register */
+	u16 rfr3;		/* Timer3 Reference Register */
+	u16 rfr4;		/* Timer4 Reference Register */
+	u16 cpr3;		/* Timer3 Capture Register */
+	u16 cpr4;		/* Timer4 Capture Register */
+	u16 cnr3;		/* Timer3 Counter Register */
+	u16 cnr4;		/* Timer4 Counter Register */
+	u16 evr1;		/* Timer1 Event Register */
+	u16 evr2;		/* Timer2 Event Register */
+	u16 evr3;		/* Timer3 Event Register */
+	u16 evr4;		/* Timer4 Event Register */
+	u16 psr1;		/* Timer1 Prescaler Register */
+	u16 psr2;		/* Timer2 Prescaler Register */
+	u16 psr3;		/* Timer3 Prescaler Register */
+	u16 psr4;		/* Timer4 Prescaler Register */
 	u8 res[0xC0];
 } gtm83xx_t;
 
@@ -301,188 +127,31 @@ typedef struct gtm83xx {
  * Integrated Programmable Interrupt Controller
  */
 typedef struct ipic83xx {
-	u32 sicfr;		/*  System Global Interrupt Configuration Register (SICFR)  */
-#define SICFR_HPI  0x7f000000	/*  Highest Priority Interrupt	*/
-#define SICFR_MPSB 0x00400000	/*  Mixed interrupts Priority Scheme for group B  */
-#define SICFR_MPSA 0x00200000	/*  Mixed interrupts Priority Scheme for group A  */
-#define SICFR_IPSD 0x00080000	/*  Internal interrupts Priority Scheme for group D  */
-#define SICFR_IPSA 0x00010000	/*  Internal interrupts Priority Scheme for group A  */
-#define SICFR_HPIT 0x00000300	/*  HPI priority position IPIC output interrupt Type  */
-#define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT)
-	u32 sivcr;		/*  System Global Interrupt Vector Register (SIVCR)  */
-#define SICVR_IVECX 0xfc000000	/*  Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation)  */
-#define SICVR_IVEC  0x0000007f	/*  Interrupt vector  */
-#define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC)
-	u32 sipnr_h;		/*  System Internal Interrupt Pending Register - High (SIPNR_H)	 */
-#if defined (CONFIG_MPC8349)
-#define SIIH_TSEC1TX 0x80000000 /*  TSEC1 Tx interrupt	*/
-#define SIIH_TSEC1RX 0x40000000 /*  TSEC1 Rx interrupt	*/
-#define SIIH_TSEC1ER 0x20000000 /*  TSEC1 Eror interrupt  */
-#define SIIH_TSEC2TX 0x10000000 /*  TSEC2 Tx interrupt	*/
-#define SIIH_TSEC2RX 0x08000000 /*  TSEC2 Rx interrupt	*/
-#define SIIH_TSEC2ER 0x04000000 /*  TSEC2 Eror interrupt  */
-#define SIIH_USB2DR  0x02000000 /*  USB2 DR interrupt  */
-#define SIIH_USB2MPH 0x01000000 /*  USB2 MPH interrupt	*/
-#endif
-#if defined (CONFIG_MPC8360)
-#define SIIH_H_QE_H   0x80000000	/*  QE high interrupt */
-#define SIIH_H_QE_L   0x40000000	/*  QE low interrupt */
-#endif
-#define SIIH_UART1   0x00000080 /*  UART1 interrupt  */
-#define SIIH_UART2   0x00000040 /*  UART2 interrupt  */
-#define SIIH_SEC     0x00000020 /*  SEC interrupt  */
-#define SIIH_I2C1    0x00000004 /*  I2C1 interrupt  */
-#define SIIH_I2C2    0x00000002 /*  I2C2 interrupt  */
-#if defined (CONFIG_MPC8349)
-#define SIIH_SPI     0x00000001 /*  SPI interrupt  */
-#define SIIH_RES	~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \
-			| SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \
-			| SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \
-			| SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \
-			| SIIH_I2C2 | SIIH_SPI)
-#endif
-#if defined (CONFIG_MPC8360)
-#define SIIH_RES       ~(SIIH_H_QE_H | SIIH_H_QE_L | SIIH_H_UART1 | \
-			SIIH_H_UART2| SIIH_H_SEC  | SIIH_H_I2C1 |SIIH_H_I2C2)
-#endif
-	u32 sipnr_l;		/*  System Internal Interrupt Pending Register - Low (SIPNR_L)	*/
-#define SIIL_RTCS  0x80000000	/*  RTC SECOND interrupt  */
-#define SIIL_PIT   0x40000000	/*  PIT interrupt  */
-#define SIIL_PCI1  0x20000000	/*  PCI1 interrupt  */
-#if defined (CONFIG_MPC8349)
-#define SIIL_PCI2  0x10000000	/*  PCI2 interrupt  */
-#endif
-#define SIIL_RTCA  0x08000000	/*  RTC ALARM interrupt	 */
-#define SIIL_MU	   0x04000000	/*  Message Unit interrupt  */
-#define SIIL_SBA   0x02000000	/*  System Bus Arbiter interrupt  */
-#define SIIL_DMA   0x01000000	/*  DMA interrupt  */
-#define SIIL_GTM4  0x00800000	/*  GTM4 interrupt  */
-#define SIIL_GTM8  0x00400000	/*  GTM8 interrupt  */
-#if defined (CONFIG_MPC8349)
-#define SIIL_GPIO1 0x00200000	/*  GPIO1 interrupt  */
-#define SIIL_GPIO2 0x00100000	/*  GPIO2 interrupt  */
-#endif
-#if defined (CONFIG_MPC8360)
-#define SIIL_QEP   0x00200000	/*  QE ports interrupt	*/
-#define SIIL_SDDR  0x00100000	/*  SDDR interrupt  */
-#endif
-#define SIIL_DDR   0x00080000	/*  DDR interrupt  */
-#define SIIL_LBC   0x00040000	/*  LBC interrupt  */
-#define SIIL_GTM2  0x00020000	/*  GTM2 interrupt  */
-#define SIIL_GTM6  0x00010000	/*  GTM6 interrupt  */
-#define SIIL_PMC   0x00008000	/*  PMC interrupt  */
-#define SIIL_GTM3  0x00000800	/*  GTM3 interrupt  */
-#define SIIL_GTM7  0x00000400	/*  GTM7 interrupt  */
-#define SIIL_GTM1  0x00000020	/*  GTM1 interrupt  */
-#define SIIL_GTM5  0x00000010	/*  GTM5 interrupt  */
-#define SIIL_DPTC  0x00000001	/*  DPTC interrupt (!!! Invisible for user !!!)	 */
-#if defined (CONFIG_MPC8349)
-#define SIIL_RES	~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \
-			| SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \
-			| SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \
-			| SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \
-			| SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \
-			| SIIL_GTM5 |SIIL_DPTC )
-#endif
-#if defined (CONFIG_MPC8360)
-#define SIIL_RES	~(SIIL_RTCS  |SIIL_PIT	|SIIL_PCI1 |SIIL_RTCALR \
-			|SIIL_MU |SIIL_SBA  |SIIL_DMA  |SIIL_GTM4 |SIIL_GTM8 \
-			|SIIL_QEP | SIIL_SDDR| SIIL_DDR	 |SIIL_LBC  |SIIL_GTM2 \
-			|SIIL_GTM6 |SIIL_PMC  |SIIL_GTM3 |SIIL_GTM7 |SIIL_GTM1 \
-			|SIIL_GTM5 )
-#endif
-	u32 siprr_a;		/*  System Internal Interrupt Group A Priority Register (PRR)  */
+	u32 sicfr;		/* System Global Interrupt Configuration Register */
+	u32 sivcr;		/* System Global Interrupt Vector Register */
+	u32 sipnr_h;		/* System Internal Interrupt Pending Register - High */
+	u32 sipnr_l;		/* System Internal Interrupt Pending Register - Low */
+	u32 siprr_a;		/* System Internal Interrupt Group A Priority Register */
 	u8 res0[8];
-	u32 siprr_d;		/*  System Internal Interrupt Group D Priority Register (PRR)  */
-	u32 simsr_h;		/*  System Internal Interrupt Mask Register - High (SIIH)  */
-	u32 simsr_l;		/*  System Internal Interrupt Mask Register - Low (SIIL)  */
+	u32 siprr_d;		/* System Internal Interrupt Group D Priority Register */
+	u32 simsr_h;		/* System Internal Interrupt Mask Register - High */
+	u32 simsr_l;		/* System Internal Interrupt Mask Register - Low */
 	u8 res1[4];
-	u32 sepnr;		/*  System External Interrupt Pending Register (SEI)  */
-	u32 smprr_a;		/*  System Mixed Interrupt Group A Priority Register (PRR)  */
-	u32 smprr_b;		/*  System Mixed Interrupt Group B Priority Register (PRR)  */
-#define PRR_0 0xe0000000	/* Priority Register, Position 0 programming */
-#define PRR_1 0x1c000000	/* Priority Register, Position 1 programming */
-#define PRR_2 0x03800000	/* Priority Register, Position 2 programming */
-#define PRR_3 0x00700000	/* Priority Register, Position 3 programming */
-#define PRR_4 0x0000e000	/* Priority Register, Position 4 programming */
-#define PRR_5 0x00001c00	/* Priority Register, Position 5 programming */
-#define PRR_6 0x00000380	/* Priority Register, Position 6 programming */
-#define PRR_7 0x00000070	/* Priority Register, Position 7 programming */
-#define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7)
-	u32 semsr;		/*  System External Interrupt Mask Register (SEI)  */
-#define SEI_IRQ0  0x80000000	/*  IRQ0 external interrupt  */
-#define SEI_IRQ1  0x40000000	/*  IRQ1 external interrupt  */
-#define SEI_IRQ2  0x20000000	/*  IRQ2 external interrupt  */
-#define SEI_IRQ3  0x10000000	/*  IRQ3 external interrupt  */
-#define SEI_IRQ4  0x08000000	/*  IRQ4 external interrupt  */
-#define SEI_IRQ5  0x04000000	/*  IRQ5 external interrupt  */
-#define SEI_IRQ6  0x02000000	/*  IRQ6 external interrupt  */
-#define SEI_IRQ7  0x01000000	/*  IRQ7 external interrupt  */
-#define SEI_SIRQ0 0x00008000	/*  SIRQ0 external interrupt  */
-#define SEI_RES		~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \
-			| SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \
-			| SEI_SIRQ0)
-	u32 secnr;		/*  System External Interrupt Control Register (SECNR) */
-#define SECNR_MIXB0T 0xc0000000 /*  MIXB0 priority position IPIC output interrupt type	*/
-#define SECNR_MIXB1T 0x30000000 /*  MIXB1 priority position IPIC output interrupt type	*/
-#define SECNR_MIXA0T 0x00c00000 /*  MIXA0 priority position IPIC output interrupt type	*/
-#define SECNR_SYSA1T 0x00300000 /*  MIXA1 priority position IPIC output interrupt type	*/
-#define SECNR_EDI0   0x00008000 /*  IRQ0 external interrupt edge/level detect  */
-#define SECNR_EDI1   0x00004000 /*  IRQ1 external interrupt edge/level detect  */
-#define SECNR_EDI2   0x00002000 /*  IRQ2 external interrupt edge/level detect  */
-#define SECNR_EDI3   0x00001000 /*  IRQ3 external interrupt edge/level detect  */
-#define SECNR_EDI4   0x00000800 /*  IRQ4 external interrupt edge/level detect  */
-#define SECNR_EDI5   0x00000400 /*  IRQ5 external interrupt edge/level detect  */
-#define SECNR_EDI6   0x00000200 /*  IRQ6 external interrupt edge/level detect  */
-#define SECNR_EDI7   0x00000100 /*  IRQ7 external interrupt edge/level detect  */
-#define SECNR_RES	~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \
-			| SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \
-			| SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \
-			| SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7)
-	u32 sersr;		/*  System Error Status Register (SERR)	 */
-	u32 sermr;		/*  System Error Mask Register (SERR)  */
-#define SERR_IRQ0 0x80000000	/*  IRQ0 MCP request  */
-#define SERR_WDT  0x40000000	/*  WDT MCP request  */
-#define SERR_SBA  0x20000000	/*  SBA MCP request  */
-#if defined (CONFIG_MPC8349)
-#define SERR_DDR  0x10000000	/*  DDR MCP request  */
-#define SERR_LBC  0x08000000	/*  LBC MCP request  */
-#define SERR_PCI1 0x04000000	/*  PCI1 MCP request  */
-#define SERR_PCI2 0x02000000	/*  PCI2 MCP request  */
-#endif
-#if defined (CONFIG_MPC8360)
-#define SERR_CIEE 0x10000000	/*  CIEE MCP request  */
-#define SERR_CMEE 0x08000000	/*  CMEEMCP request  */
-#define SERR_PCI  0x04000000	/*  PCI MCP request  */
-#endif
-#define SERR_MU	  0x01000000	/*  MU MCP request  */
-#define SERR_RNC  0x00010000	/*  MU MCP request (!!! Non-visible for users !!!)  */
-#if defined (CONFIG_MPC8349)
-#define SERR_RES	~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \
-			|SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \
-			|SERR_RNC )
-#elif defined (CONFIG_MPC8360)
-#define SERR_RES	~( SERR_IRQ0|SERR_WDT |SERR_SBA |SERR_CIEE\
-			|SERR_CMEE|SERR_PCI|SERR_MU)
-#endif
-	u32 sercr;		/*  System Error Control Register  (SERCR)  */
-#define SERCR_MCPR 0x00000001	/*  MCP Route  */
-#define SERCR_RES ~(SERCR_MCPR)
+	u32 sepnr;		/* System External Interrupt Pending Register */
+	u32 smprr_a;		/* System Mixed Interrupt Group A Priority Register */
+	u32 smprr_b;		/* System Mixed Interrupt Group B Priority Register */
+	u32 semsr;		/* System External Interrupt Mask Register */
+	u32 secnr;		/* System External Interrupt Control Register */
+	u32 sersr;		/* System Error Status Register */
+	u32 sermr;		/* System Error Mask Register */
+	u32 sercr;		/* System Error Control Register */
 	u8 res2[4];
-	u32 sifcr_h;		/*  System Internal Interrupt Force Register - High (SIIH)  */
-	u32 sifcr_l;		/*  System Internal Interrupt Force Register - Low (SIIL)  */
-	u32 sefcr;		/*  System External Interrupt Force Register (SEI)  */
-	u32 serfr;		/*  System Error Force Register (SERR)	*/
+	u32 sifcr_h;		/* System Internal Interrupt Force Register - High */
+	u32 sifcr_l;		/* System Internal Interrupt Force Register - Low */
+	u32 sefcr;		/* System External Interrupt Force Register */
+	u32 serfr;		/* System Error Force Register */
 	u32 scvcr;		/* System Critical Interrupt Vector Register */
-#define SCVCR_CVECX	0xFC000000	/* Backward (MPC8260) compatible
-					   critical interrupt vector. */
-#define SCVCR_CVEC	0x0000007F	/* Critical interrupt vector */
-#define SCVCR_RES	~(SCVCR_CVECX|SCVCR_CVEC)
 	u32 smvcr;		/* System Management Interrupt Vector Register */
-#define SMVCR_CVECX	0xFC000000	/* Backward (MPC8260) compatible
-					   critical interrupt vector. */
-#define SMVCR_CVEC	0x0000007F	/* Critical interrupt vector */
-#define SMVCR_RES	~(SMVCR_CVECX|SMVCR_CVEC)
 	u8 res3[0x98];
 } ipic83xx_t;
 
@@ -491,43 +160,14 @@ typedef struct ipic83xx {
  */
 typedef struct arbiter83xx {
 	u32 acr;		/* Arbiter Configuration Register */
-#define ACR_COREDIS    0x10000000	/* Core disable. */
-#define ACR_COREDIS_SHIFT		(31-7)
-#define ACR_PIPE_DEP   0x00070000	/* Pipeline depth (number of outstanding transactions). */
-#define ACR_PIPE_DEP_SHIFT		(31-15)
-#define ACR_PCI_RPTCNT 0x00007000	/* PCI repeat count. */
-#define ACR_PCI_RPTCNT_SHIFT		(31-19)
-#define ACR_RPTCNT     0x00000700	/* Repeat count. */
-#define ACR_RPTCNT_SHIFT		(31-23)
-#define ACR_APARK      0x00000030	/* Address parking. */
-#define ACR_APARK_SHIFT			(31-27)
-#define ACR_PARKM	   0x0000000F	/* Parking master. */
-#define ACR_PARKM_SHIFT			(31-31)
-#define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM)
 	u32 atr;		/* Arbiter Timers Register */
-#define ATR_DTO 0x00FF0000	/* Data time out. */
-#define ATR_ATO 0x000000FF	/* Address time out. */
-#define ATR_RES ~(ATR_DTO|ATR_ATO)
 	u8 res[4];
-	u32 aer;		/* Arbiter Event Register (AE) */
-	u32 aidr;		/* Arbiter Interrupt Definition Register (AE) */
-	u32 amr;		/* Arbiter Mask Register (AE) */
+	u32 aer;		/* Arbiter Event Register */
+	u32 aidr;		/* Arbiter Interrupt Definition Register */
+	u32 amr;		/* Arbiter Mask Register */
 	u32 aeatr;		/* Arbiter Event Attributes Register */
-#define AEATR_EVENT   0x07000000	/* Event type. */
-#define AEATR_MSTR_ID 0x001F0000	/* Master Id. */
-#define AEATR_TBST    0x00000800	/* Transfer burst. */
-#define AEATR_TSIZE   0x00000700	/* Transfer Size. */
-#define AEATR_TTYPE	  0x0000001F	/* Transfer Type. */
-#define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE)
 	u32 aeadr;		/* Arbiter Event Address Register */
-	u32 aerr;		/* Arbiter Event Response Register (AE) */
-#define AE_ETEA 0x00000020	/* Transfer error. */
-#define AE_RES_ 0x00000010	/* Reserved transfer type. */
-#define AE_ECW	0x00000008	/* External control word transfer type. */
-#define AE_AO	0x00000004	/* Address Only transfer type. */
-#define AE_DTO	0x00000002	/* Data time out. */
-#define AE_ATO	0x00000001	/* Address time out. */
-#define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO)
+	u32 aerr;		/* Arbiter Event Response Register */
 	u8 res1[0xDC];
 } arbiter83xx_t;
 
@@ -535,184 +175,24 @@ typedef struct arbiter83xx {
  * Reset Module
  */
 typedef struct reset83xx {
-	u32 rcwl;		/* RCWL Register  */
-#define RCWL_LBIUCM  0x80000000 /* LBIUCM  */
-#define RCWL_LBIUCM_SHIFT    31
-#define RCWL_DDRCM   0x40000000 /* DDRCM  */
-#define RCWL_DDRCM_SHIFT     30
-#if defined (CONFIG_MPC8349)
-#define RCWL_SVCOD   0x30000000 /* SVCOD  */
-#endif
-#define RCWL_SPMF    0x0f000000 /* SPMF	 */
-#define RCWL_SPMF_SHIFT	     24
-#define RCWL_COREPLL 0x007F0000 /* COREPLL  */
-#define RCWL_COREPLL_SHIFT   16
-#define RCWL_CEVCOD  0x000000C0 /* CEVCOD  */
-#define RCWL_CEPDF   0x00000020 /* CEPDF  */
-#define RCWL_CEPDF_SHIFT      5
-#define RCWL_CEPMF   0x0000001F /* CEPMF  */
-#define RCWL_CEPMF_SHIFT      0
-#if defined (CONFIG_MPC8349)
-#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF)
-#elif defined (CONFIG_MPC8360)
-#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SPMF|RCWL_COREPLL|RCWL_CEPDF|RCWL_CEPMF)
-#endif
-	u32 rcwh;		/* RCHL Register  */
-#define RCWH_PCIHOST 0x80000000 /* PCIHOST  */
-#define RCWH_PCIHOST_SHIFT   31
-#if defined (CONFIG_MPC8349)
-#define RCWH_PCI64   0x40000000 /* PCI64  */
-#define RCWH_PCI1ARB 0x20000000 /* PCI1ARB  */
-#define RCWH_PCI2ARB 0x10000000 /* PCI2ARB  */
-#elif defined (CONFIG_MPC8360)
-#define RCWH_PCIARB   0x20000000	/* PCI internal arbiter mode. */
-#define RCWH_PCICKDRV 0x10000000	/* PCI clock output drive. */
-#endif
-#define RCWH_COREDIS 0x08000000 /* COREDIS  */
-#define RCWH_BMS     0x04000000 /* BMS	*/
-#define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ  */
-#define RCWH_SWEN    0x00800000 /* SWEN	 */
-#define RCWH_ROMLOC  0x00700000 /* ROMLOC  */
-#if defined (CONFIG_MPC8349)
-#define RCWH_TSEC1M  0x0000c000 /* TSEC1M  */
-#define RCWH_TSEC2M  0x00003000 /* TSEC2M  */
-#define RCWH_TPR     0x00000100 /* TPR	*/
-#elif defined (CONFIG_MPC8360)
-#define RCWH_SDDRIOE  0x00000010	/* Secondary DDR IO Enable.  */
-#endif
-#define RCWH_TLE     0x00000008 /* TLE	*/
-#define RCWH_LALE    0x00000004 /* LALE	 */
-#if defined (CONFIG_MPC8349)
-#define RCWH_RES	~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \
-			| RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \
-			| RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \
-			| RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \
-			| RCWH_TLE | RCWH_LALE)
-#elif defined (CONFIG_MPC8360)
-#define RCWH_RES	~(RCWH_PCIHOST|RCWH_PCIARB|RCWH_PCICKDRV \
-			|RCWH_COREDIS|RCWH_BMS|RCWH_BOOTSEQ|RCWH_SWEN \
-			|RCWH_SDDRIOE |RCWH_TLE)
-#endif
+	u32 rcwl;		/* Reset Configuration Word Low Register */
+	u32 rcwh;		/* Reset Configuration Word High Register */
 	u8 res0[8];
-	u32 rsr;		/* Reset status Register  */
-#define RSR_RSTSRC 0xE0000000	/* Reset source	 */
-#define RSR_RSTSRC_SHIFT   29
-#define RSR_BSF	   0x00010000	/* Boot seq. fail  */
-#define RSR_BSF_SHIFT	   16
-#define RSR_SWSR   0x00002000	/* software soft reset	*/
-#define RSR_SWSR_SHIFT	   13
-#define RSR_SWHR   0x00001000	/* software hard reset	*/
-#define RSR_SWHR_SHIFT	   12
-#define RSR_JHRS   0x00000200	/* jtag hreset	*/
-#define RSR_JHRS_SHIFT	    9
-#define RSR_JSRS   0x00000100	/* jtag sreset status  */
-#define RSR_JSRS_SHIFT	    8
-#define RSR_CSHR   0x00000010	/* checkstop reset status  */
-#define RSR_CSHR_SHIFT	    4
-#define RSR_SWRS   0x00000008	/* software watchdog reset status  */
-#define RSR_SWRS_SHIFT	    3
-#define RSR_BMRS   0x00000004	/* bus monitop reset status  */
-#define RSR_BMRS_SHIFT	    2
-#define RSR_SRS	   0x00000002	/* soft reset status  */
-#define RSR_SRS_SHIFT	    1
-#define RSR_HRS	   0x00000001	/* hard reset status  */
-#define RSR_HRS_SHIFT	    0
-#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS)
-	u32 rmr;		/* Reset mode Register	*/
-#define RMR_CSRE   0x00000001	/* checkstop reset enable  */
-#define RMR_CSRE_SHIFT	    0
-#define RMR_RES ~(RMR_CSRE)
-	u32 rpr;		/* Reset protection Register  */
-	u32 rcr;		/* Reset Control Register  */
-#define RCR_SWHR 0x00000002	/* software hard reset	*/
-#define RCR_SWSR 0x00000001	/* software soft reset	*/
-#define RCR_RES ~(RCR_SWHR | RCR_SWSR)
-	u32 rcer;		/* Reset Control Enable Register  */
-#define RCER_CRE 0x00000001	/* software hard reset	*/
-#define RCER_RES ~(RCER_CRE)
+	u32 rsr;		/* Reset Status Register */
+	u32 rmr;		/* Reset Mode Register */
+	u32 rpr;		/* Reset protection Register */
+	u32 rcr;		/* Reset Control Register */
+	u32 rcer;		/* Reset Control Enable Register */
 	u8 res1[0xDC];
 } reset83xx_t;
 
+/*
+ * Clock Module
+ */
 typedef struct clk83xx {
-	u32 spmr;		/* system PLL mode Register  */
-#define SPMR_LBIUCM  0x80000000 /* LBIUCM  */
-#define SPMR_DDRCM   0x40000000 /* DDRCM  */
-#if defined (CONFIG_MPC8349)
-#define SPMR_SVCOD   0x30000000 /* SVCOD  */
-#endif
-#define SPMR_SPMF    0x0F000000 /* SPMF	 */
-#define SPMR_CKID    0x00800000 /* CKID	 */
-#define SPMR_CKID_SHIFT 23
-#define SPMR_COREPLL 0x007F0000 /* COREPLL  */
-#define SPMR_CEVCOD  0x000000C0 /* CEVCOD  */
-#define SPMR_CEPDF   0x00000020 /* CEPDF  */
-#define SPMR_CEPMF   0x0000001F /* CEPMF  */
-#if defined (CONFIG_MPC8349)
-#define SPMR_RES	~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \
-			| SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \
-			| SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF)
-#elif defined (CONFIG_MPC8360)
-#define SPMR_RES	~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SPMF \
-			| SPMR_CKID | SPMR_COREPLL | SPMR_CEVCOD \
-			| SPMR_CEPDF | SPMR_CEPMF)
-#endif
-	u32 occr;		/* output clock control Register  */
-#define OCCR_PCICOE0 0x80000000 /* PCICOE0  */
-#define OCCR_PCICOE1 0x40000000 /* PCICOE1  */
-#define OCCR_PCICOE2 0x20000000 /* PCICOE2  */
-#if defined (CONFIG_MPC8349)
-#define OCCR_PCICOE3 0x10000000 /* PCICOE3  */
-#define OCCR_PCICOE4 0x08000000 /* PCICOE4  */
-#define OCCR_PCICOE5 0x04000000 /* PCICOE5  */
-#define OCCR_PCICOE6 0x02000000 /* PCICOE6  */
-#define OCCR_PCICOE7 0x01000000 /* PCICOE7  */
-#endif
-#define OCCR_PCICD0  0x00800000 /* PCICD0  */
-#define OCCR_PCICD1  0x00400000 /* PCICD1  */
-#define OCCR_PCICD2  0x00200000 /* PCICD2  */
-#if defined (CONFIG_MPC8349)
-#define OCCR_PCICD3  0x00100000 /* PCICD3  */
-#define OCCR_PCICD4  0x00080000 /* PCICD4  */
-#define OCCR_PCICD5  0x00040000 /* PCICD5  */
-#define OCCR_PCICD6  0x00020000 /* PCICD6  */
-#define OCCR_PCICD7  0x00010000 /* PCICD7  */
-#define OCCR_PCI1CR  0x00000002 /* PCI1CR  */
-#define OCCR_PCI2CR  0x00000001 /* PCI2CR  */
-#define OCCR_RES	~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \
-			| OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \
-			| OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \
-			| OCCR_PCICD1 | OCCR_PCICD2  | OCCR_PCICD3 \
-			| OCCR_PCICD4  | OCCR_PCICD5 | OCCR_PCICD6  \
-			| OCCR_PCICD7  | OCCR_PCI1CR  | OCCR_PCI2CR )
-#endif
-#if defined (CONFIG_MPC8360)
-#define OCCR_PCICR	0x00000002	/* PCI clock rate  */
-#define OCCR_RES	~(OCCR_PCICOE0|OCCR_PCICOE1|OCCR_PCICOE2 \
-			|OCCR_PCICD0|OCCR_PCICD1|OCCR_PCICD2|OCCR_PCICR )
-#endif
-	u32 sccr;		/* system clock control Register  */
-#if defined (CONFIG_MPC8349)
-#define SCCR_TSEC1CM  0xc0000000	/* TSEC1CM  */
-#define SCCR_TSEC1CM_SHIFT 30
-#define SCCR_TSEC2CM  0x30000000	/* TSEC2CM  */
-#define SCCR_TSEC2CM_SHIFT 28
-#endif
-#define SCCR_ENCCM    0x03000000	/* ENCCM  */
-#define SCCR_ENCCM_SHIFT 24
-#if defined (CONFIG_MPC8349)
-#define SCCR_USBMPHCM 0x00c00000	/* USBMPHCM  */
-#define SCCR_USBMPHCM_SHIFT 22
-#define SCCR_USBDRCM  0x00300000	/* USBDRCM  */
-#define SCCR_USBDRCM_SHIFT 20
-#endif
-#define SCCR_PCICM    0x00010000	/* PCICM  */
-#if defined (CONFIG_MPC8349)
-#define SCCR_RES	~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \
-			| SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM)
-#endif
-#if defined (CONFIG_MPC8360)
-#define SCCR_RES	~(SCCR_ENCCM | SCCR_PCICM)
-#endif
+	u32 spmr;		/* system PLL mode Register */
+	u32 occr;		/* output clock control Register */
+	u32 sccr;		/* system clock control Register */
 	u8 res0[0xF4];
 } clk83xx_t;
 
@@ -720,27 +200,14 @@ typedef struct clk83xx {
  * Power Management Control Module
  */
 typedef struct pmc83xx {
-	u32 pmccr;		/* PMC Configuration Register  */
-#define PMCCR_SLPEN 0x00000001	/* System Low Power Enable  */
-#define PMCCR_DLPEN 0x00000002	/* DDR SDRAM Low Power Enable  */
-#if defined (CONFIG_MPC8360)
-#define PMCCR_SDLPEN 0x00000004 /* Secondary DDR SDRAM Low Power Enable	 */
-#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN | PMCCR_SDLPEN)
-#elif defined (CONFIG_MPC8349)
-#define PMCCR_RES    ~(PMCCR_SLPEN | PMCCR_DLPEN)
-#endif
-	u32 pmcer;		/* PMC Event Register  */
-#define PMCER_PMCI  0x00000001	/* PMC Interrupt  */
-#define PMCER_RES ~(PMCER_PMCI)
-	u32 pmcmr;		/* PMC Mask Register  */
-#define PMCMR_PMCIE 0x0001	/* PMC Interrupt Enable	 */
-#define PMCMR_RES ~(PMCMR_PMCIE)
+	u32 pmccr;		/* PMC Configuration Register */
+	u32 pmcer;		/* PMC Event Register */
+	u32 pmcmr;		/* PMC Mask Register */
 	u8 res0[0xF4];
 } pmc83xx_t;
 
-#if defined (CONFIG_MPC8349)
 /*
- * general purpose I/O module
+ * General purpose I/O module
  */
 typedef struct gpio83xx {
 	u32 dir;		/* direction register */
@@ -751,124 +218,20 @@ typedef struct gpio83xx {
 	u32 icr;		/* external interrupt control register */
 	u8 res0[0xE8];
 } gpio83xx_t;
-#endif
 
-#if defined (CONFIG_MPC8360)
 /*
  * QE Ports Interrupts Registers
  */
 typedef struct qepi83xx {
 	u8 res0[0xC];
 	u32 qepier;		/* QE Ports Interrupt Event Register */
-#define QEPIER_PA15 0x80000000
-#define QEPIER_PA16 0x40000000
-#define QEPIER_PA29 0x20000000
-#define QEPIER_PA30 0x10000000
-#define QEPIER_PB3  0x08000000
-#define QEPIER_PB5  0x04000000
-#define QEPIER_PB12 0x02000000
-#define QEPIER_PB13 0x01000000
-#define QEPIER_PB26 0x00800000
-#define QEPIER_PB27 0x00400000
-#define QEPIER_PC27 0x00200000
-#define QEPIER_PC28 0x00100000
-#define QEPIER_PC29 0x00080000
-#define QEPIER_PD12 0x00040000
-#define QEPIER_PD13 0x00020000
-#define QEPIER_PD16 0x00010000
-#define QEPIER_PD17 0x00008000
-#define QEPIER_PD26 0x00004000
-#define QEPIER_PD27 0x00002000
-#define QEPIER_PE12 0x00001000
-#define QEPIER_PE13 0x00000800
-#define QEPIER_PE24 0x00000400
-#define QEPIER_PE25 0x00000200
-#define QEPIER_PE26 0x00000100
-#define QEPIER_PE27 0x00000080
-#define QEPIER_PE31 0x00000040
-#define QEPIER_PF20 0x00000020
-#define QEPIER_PG31 0x00000010
-#define QEPIER_RES ~(QEPIER_PA15|QEPIER_PA16|QEPIER_PA29|QEPIER_PA30|QEPIER_PB3 \
-		   |QEPIER_PB5|QEPIER_PB12|QEPIER_PB13|QEPIER_PB26|QEPIER_PB27 \
-		   |QEPIER_PC27|QEPIER_PC28|QEPIER_PC29|QEPIER_PD12|QEPIER_PD13 \
-		   |QEPIER_PD16|QEPIER_PD17|QEPIER_PD26|QEPIER_PD27|QEPIER_PE12 \
-		   |QEPIER_PE13|QEPIER_PE24|QEPIER_PE25|QEPIER_PE26|QEPIER_PE27 \
-		   |QEPIER_PE31|QEPIER_PF20|QEPIER_PG31)
 	u32 qepimr;		/* QE Ports Interrupt Mask Register */
-#define QEPIMR_PA15 0x80000000
-#define QEPIMR_PA16 0x40000000
-#define QEPIMR_PA29 0x20000000
-#define QEPIMR_PA30 0x10000000
-#define QEPIMR_PB3  0x08000000
-#define QEPIMR_PB5  0x04000000
-#define QEPIMR_PB12 0x02000000
-#define QEPIMR_PB13 0x01000000
-#define QEPIMR_PB26 0x00800000
-#define QEPIMR_PB27 0x00400000
-#define QEPIMR_PC27 0x00200000
-#define QEPIMR_PC28 0x00100000
-#define QEPIMR_PC29 0x00080000
-#define QEPIMR_PD12 0x00040000
-#define QEPIMR_PD13 0x00020000
-#define QEPIMR_PD16 0x00010000
-#define QEPIMR_PD17 0x00008000
-#define QEPIMR_PD26 0x00004000
-#define QEPIMR_PD27 0x00002000
-#define QEPIMR_PE12 0x00001000
-#define QEPIMR_PE13 0x00000800
-#define QEPIMR_PE24 0x00000400
-#define QEPIMR_PE25 0x00000200
-#define QEPIMR_PE26 0x00000100
-#define QEPIMR_PE27 0x00000080
-#define QEPIMR_PE31 0x00000040
-#define QEPIMR_PF20 0x00000020
-#define QEPIMR_PG31 0x00000010
-#define QEPIMR_RES ~(QEPIMR_PA15|QEPIMR_PA16|QEPIMR_PA29|QEPIMR_PA30|QEPIMR_PB3 \
-		   |QEPIMR_PB5|QEPIMR_PB12|QEPIMR_PB13|QEPIMR_PB26|QEPIMR_PB27 \
-		   |QEPIMR_PC27|QEPIMR_PC28|QEPIMR_PC29|QEPIMR_PD12|QEPIMR_PD13 \
-		   |QEPIMR_PD16|QEPIMR_PD17|QEPIMR_PD26|QEPIMR_PD27|QEPIMR_PE12 \
-		   |QEPIMR_PE13|QEPIMR_PE24|QEPIMR_PE25|QEPIMR_PE26|QEPIMR_PE27 \
-		   |QEPIMR_PE31|QEPIMR_PF20|QEPIMR_PG31)
 	u32 qepicr;		/* QE Ports Interrupt Control Register */
-#define QEPICR_PA15 0x80000000
-#define QEPICR_PA16 0x40000000
-#define QEPICR_PA29 0x20000000
-#define QEPICR_PA30 0x10000000
-#define QEPICR_PB3  0x08000000
-#define QEPICR_PB5  0x04000000
-#define QEPICR_PB12 0x02000000
-#define QEPICR_PB13 0x01000000
-#define QEPICR_PB26 0x00800000
-#define QEPICR_PB27 0x00400000
-#define QEPICR_PC27 0x00200000
-#define QEPICR_PC28 0x00100000
-#define QEPICR_PC29 0x00080000
-#define QEPICR_PD12 0x00040000
-#define QEPICR_PD13 0x00020000
-#define QEPICR_PD16 0x00010000
-#define QEPICR_PD17 0x00008000
-#define QEPICR_PD26 0x00004000
-#define QEPICR_PD27 0x00002000
-#define QEPICR_PE12 0x00001000
-#define QEPICR_PE13 0x00000800
-#define QEPICR_PE24 0x00000400
-#define QEPICR_PE25 0x00000200
-#define QEPICR_PE26 0x00000100
-#define QEPICR_PE27 0x00000080
-#define QEPICR_PE31 0x00000040
-#define QEPICR_PF20 0x00000020
-#define QEPICR_PG31 0x00000010
-#define QEPICR_RES ~(QEPICR_PA15|QEPICR_PA16|QEPICR_PA29|QEPICR_PA30|QEPICR_PB3 \
-		   |QEPICR_PB5|QEPICR_PB12|QEPICR_PB13|QEPICR_PB26|QEPICR_PB27 \
-		   |QEPICR_PC27|QEPICR_PC28|QEPICR_PC29|QEPICR_PD12|QEPICR_PD13 \
-		   |QEPICR_PD16|QEPICR_PD17|QEPICR_PD26|QEPICR_PD27|QEPICR_PE12 \
-		   |QEPICR_PE13|QEPICR_PE24|QEPICR_PE25|QEPICR_PE26|QEPICR_PE27 \
-		   |QEPICR_PE31|QEPICR_PF20|QEPICR_PG31)
 	u8 res1[0xE8];
 } qepi83xx_t;
 
 /*
- * general purpose I/O module
+ * QE Parallel I/O Ports
  */
 typedef struct gpio_n {
 	u32 podr;		/* Open Drain Register */
@@ -879,238 +242,83 @@ typedef struct gpio_n {
 	u32 ppar2;		/* Pin Assignment Register 2 */
 } gpio_n_t;
 
-typedef struct gpio83xx {
+typedef struct qegpio83xx {
 	gpio_n_t ioport[0x7];
 	u8 res0[0x358];
-} gpio83xx_t;
+} qepio83xx_t;
 
 /*
  * QE Secondary Bus Access Windows
  */
-
 typedef struct qesba83xx {
 	u32 lbmcsar;		/* Local bus memory controller start address */
-#define LBMCSAR_SA	0x000FFFFF	/* 20 most-significant bits of the start address */
-#define LBMCSAR_RES	~(LBMCSAR_SA)
 	u32 sdmcsar;		/* Secondary DDR memory controller start address */
-#define SDMCSAR_SA	0x000FFFFF	/* 20 most-significant bits of the start address */
-#define SDMCSAR_RES	~(SDMCSAR_SA)
 	u8 res0[0x38];
 	u32 lbmcear;		/* Local bus memory controller end address */
-#define LBMCEAR_EA	0x000FFFFF	/* 20 most-significant bits of the end address */
-#define LBMCEAR_RES	~(LBMCEAR_EA)
 	u32 sdmcear;		/* Secondary DDR memory controller end address */
-#define SDMCEAR_EA	0x000FFFFF	/* 20 most-significant bits of the end address */
-#define SDMCEAR_RES	~(SDMCEAR_EA)
 	u8 res1[0x38];
-	u32 lbmcar;		/* Local bus memory controller attributes  */
-#define LBMCAR_WEN	0x00000001	/* Forward transactions to the QE local bus */
-#define LBMCAR_RES	~(LBMCAR_WEN)
+	u32 lbmcar;		/* Local bus memory controller attributes */
 	u32 sdmcar;		/* Secondary DDR memory controller attributes */
-#define SDMCAR_WEN	0x00000001	/* Forward transactions to the second DDR bus */
-#define SDMCAR_RES	~(SDMCAR_WEN)
-	u8 res2[0x778];
+	u8 res2[0x378];
 } qesba83xx_t;
-#endif
 
 /*
  * DDR Memory Controller Memory Map
  */
 typedef struct ddr_cs_bnds {
 	u32 csbnds;
-#define CSBNDS_SA 0x00FF0000
-#define CSBNDS_SA_SHIFT	   8
-#define CSBNDS_EA 0x000000FF
-#define CSBNDS_EA_SHIFT	  24
 	u8 res0[4];
 } ddr_cs_bnds_t;
 
 typedef struct ddr83xx {
-	ddr_cs_bnds_t csbnds[4];	    /**< Chip Select x Memory Bounds */
+	ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
 	u8 res0[0x60];
-	u32 cs_config[4];	/**< Chip Select x Configuration */
-#define CSCONFIG_EN	    0x80000000
-#define CSCONFIG_AP	    0x00800000
-#define CSCONFIG_ROW_BIT    0x00000700
-#define CSCONFIG_ROW_BIT_12 0x00000000
-#define CSCONFIG_ROW_BIT_13 0x00000100
-#define CSCONFIG_ROW_BIT_14 0x00000200
-#define CSCONFIG_COL_BIT    0x00000007
-#define CSCONFIG_COL_BIT_8  0x00000000
-#define CSCONFIG_COL_BIT_9  0x00000001
-#define CSCONFIG_COL_BIT_10 0x00000002
-#define CSCONFIG_COL_BIT_11 0x00000003
+	u32 cs_config[4];	/* Chip Select x Configuration */
 	u8 res1[0x78];
-	u32 timing_cfg_1;	/**< SDRAM Timing Configuration 1 */
-#define TIMING_CFG1_PRETOACT 0x70000000
-#define TIMING_CFG1_PRETOACT_SHIFT   28
-#define TIMING_CFG1_ACTTOPRE 0x0F000000
-#define TIMING_CFG1_ACTTOPRE_SHIFT   24
-#define TIMING_CFG1_ACTTORW  0x00700000
-#define TIMING_CFG1_ACTTORW_SHIFT    20
-#define TIMING_CFG1_CASLAT   0x00070000
-#define TIMING_CFG1_CASLAT_SHIFT     16
-#define TIMING_CFG1_REFREC   0x0000F000
-#define TIMING_CFG1_REFREC_SHIFT     12
-#define TIMING_CFG1_WRREC    0x00000700
-#define TIMING_CFG1_WRREC_SHIFT	      8
-#define TIMING_CFG1_ACTTOACT 0x00000070
-#define TIMING_CFG1_ACTTOACT_SHIFT    4
-#define TIMING_CFG1_WRTORD   0x00000007
-#define TIMING_CFG1_WRTORD_SHIFT      0
-#define TIMING_CFG1_CASLAT_20 0x00030000	/* CAS latency = 2.0 */
-#define TIMING_CFG1_CASLAT_25 0x00040000	/* CAS latency = 2.5 */
-
-	u32 timing_cfg_2;	/**< SDRAM Timing Configuration 2 */
-#define TIMING_CFG2_CPO		  0x0F000000
-#define TIMING_CFG2_CPO_SHIFT		  24
-#define TIMING_CFG2_ACSM	  0x00080000
-#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
-#define TIMING_CFG2_WR_DATA_DELAY_SHIFT	  10
-#define TIMING_CFG2_CPO_DEF	  0x00000000	/* default (= CASLAT + 1) */
-
-	u32 sdram_cfg;		/**< SDRAM Control Configuration */
-#define SDRAM_CFG_MEM_EN     0x80000000
-#define SDRAM_CFG_SREN	     0x40000000
-#define SDRAM_CFG_ECC_EN     0x20000000
-#define SDRAM_CFG_RD_EN	     0x10000000
-#define SDRAM_CFG_SDRAM_TYPE 0x03000000
-#define SDRAM_CFG_SDRAM_TYPE_SHIFT   24
-#define SDRAM_CFG_DYN_PWR    0x00200000
-#define SDRAM_CFG_32_BE	     0x00080000
-#define SDRAM_CFG_8_BE	     0x00040000
-#define SDRAM_CFG_NCAP	     0x00020000
-#define SDRAM_CFG_2T_EN	     0x00008000
-#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
-
+	u32 timing_cfg_1;	/* SDRAM Timing Configuration 1 */
+	u32 timing_cfg_2;	/* SDRAM Timing Configuration 2 */
+	u32 sdram_cfg;		/* SDRAM Control Configuration */
 	u8 res2[4];
-	u32 sdram_mode;		/**< SDRAM Mode Configuration */
-#define SDRAM_MODE_ESD 0xFFFF0000
-#define SDRAM_MODE_ESD_SHIFT   16
-#define SDRAM_MODE_SD  0x0000FFFF
-#define SDRAM_MODE_SD_SHIFT	0
-#define DDR_MODE_EXT_MODEREG	0x4000	/* select extended mode reg */
-#define DDR_MODE_EXT_OPMODE	0x3FF8	/* operating mode, mask */
-#define DDR_MODE_EXT_OP_NORMAL	0x0000	/* normal operation */
-#define DDR_MODE_QFC		0x0004	/* QFC / compatibility, mask */
-#define DDR_MODE_QFC_COMP	0x0000	/* compatible to older SDRAMs */
-#define DDR_MODE_WEAK		0x0002	/* weak drivers */
-#define DDR_MODE_DLL_DIS	0x0001	/* disable DLL */
-#define DDR_MODE_CASLAT		0x0070	/* CAS latency, mask */
-#define DDR_MODE_CASLAT_15	0x0010	/* CAS latency 1.5 */
-#define DDR_MODE_CASLAT_20	0x0020	/* CAS latency 2 */
-#define DDR_MODE_CASLAT_25	0x0060	/* CAS latency 2.5 */
-#define DDR_MODE_CASLAT_30	0x0030	/* CAS latency 3 */
-#define DDR_MODE_BTYPE_SEQ	0x0000	/* sequential burst */
-#define DDR_MODE_BTYPE_ILVD	0x0008	/* interleaved burst */
-#define DDR_MODE_BLEN_2		0x0001	/* burst length 2 */
-#define DDR_MODE_BLEN_4		0x0002	/* burst length 4 */
-#define DDR_REFINT_166MHZ_7US	1302	/* exact value for 7.8125 µs */
-#define DDR_BSTOPRE	256	/* use 256 cycles as a starting point */
-#define DDR_MODE_MODEREG	0x0000	/* select mode register */
-
+	u32 sdram_mode;		/* SDRAM Mode Configuration */
 	u8 res3[8];
-	u32 sdram_interval;	/**< SDRAM Interval Configuration */
-#define SDRAM_INTERVAL_REFINT  0x3FFF0000
-#define SDRAM_INTERVAL_REFINT_SHIFT    16
-#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
-#define SDRAM_INTERVAL_BSTOPRE_SHIFT	0
+	u32 sdram_interval;	/* SDRAM Interval Configuration */
 	u8 res9[8];
 	u32 sdram_clk_cntl;
-#define DDR_SDRAM_CLK_CNTL_SS_EN		0x80000000
-#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025	0x01000000
-#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05	0x02000000
-#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075	0x03000000
-#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1		0x04000000
-
 	u8 res4[0xCCC];
-	u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
-	u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
-	u32 ecc_err_inject;	/**< Memory Data Path Error Injection Mask ECC */
-#define ECC_ERR_INJECT_EMB			(0x80000000>>22)	/* ECC Mirror Byte */
-#define ECC_ERR_INJECT_EIEN			(0x80000000>>23)	/* Error Injection Enable */
-#define ECC_ERR_INJECT_EEIM			(0xff000000>>24)	/* ECC Erroe Injection Enable */
-#define ECC_ERR_INJECT_EEIM_SHIFT		0
+	u32 data_err_inject_hi;	/* Memory Data Path Error Injection Mask High */
+	u32 data_err_inject_lo;	/* Memory Data Path Error Injection Mask Low */
+	u32 ecc_err_inject;	/* Memory Data Path Error Injection Mask ECC */
 	u8 res5[0x14];
-	u32 capture_data_hi;	/**< Memory Data Path Read Capture High */
-	u32 capture_data_lo;	/**< Memory Data Path Read Capture Low */
-	u32 capture_ecc;	/**< Memory Data Path Read Capture ECC */
-#define CAPTURE_ECC_ECE				(0xff000000>>24)
-#define CAPTURE_ECC_ECE_SHIFT			0
+	u32 capture_data_hi;	/* Memory Data Path Read Capture High */
+	u32 capture_data_lo;	/* Memory Data Path Read Capture Low */
+	u32 capture_ecc;	/* Memory Data Path Read Capture ECC */
 	u8 res6[0x14];
-	u32 err_detect;		/**< Memory Error Detect */
-#define ECC_ERROR_DETECT_MME			(0x80000000>>0) /* Multiple Memory Errors */
-#define ECC_ERROR_DETECT_MBE			(0x80000000>>28)	/* Multiple-Bit Error */
-#define ECC_ERROR_DETECT_SBE			(0x80000000>>29)	/* Single-Bit ECC Error Pickup */
-#define ECC_ERROR_DETECT_MSE			(0x80000000>>31)	/* Memory Select Error */
-	u32 err_disable;	/**< Memory Error Disable */
-#define ECC_ERROR_DISABLE_MBED			(0x80000000>>28)	/* Multiple-Bit ECC Error Disable */
-#define ECC_ERROR_DISABLE_SBED			(0x80000000>>29)	/* Sinle-Bit ECC Error disable */
-#define ECC_ERROR_DISABLE_MSED			(0x80000000>>31)	/* Memory Select Error Disable */
-#define ECC_ERROR_ENABLE			~(ECC_ERROR_DISABLE_MSED|ECC_ERROR_DISABLE_SBED|ECC_ERROR_DISABLE_MBED)
-	u32 err_int_en;		/**< Memory Error Interrupt Enable */
-#define ECC_ERR_INT_EN_MBEE			(0x80000000>>28)	/* Multiple-Bit ECC Error Interrupt Enable */
-#define ECC_ERR_INT_EN_SBEE			(0x80000000>>29)	/* Single-Bit ECC Error Interrupt Enable */
-#define ECC_ERR_INT_EN_MSEE			(0x80000000>>31)	/* Memory Select Error Interrupt Enable */
-#define ECC_ERR_INT_DISABLE			~(ECC_ERR_INT_EN_MBEE|ECC_ERR_INT_EN_SBEE|ECC_ERR_INT_EN_MSEE)
-	u32 capture_attributes; /**< Memory Error Attributes Capture */
-#define ECC_CAPT_ATTR_BNUM			(0xe0000000>>1) /* Data Beat Num */
-#define ECC_CAPT_ATTR_BNUM_SHIFT		28
-#define ECC_CAPT_ATTR_TSIZ			(0xc0000000>>6) /* Transaction Size */
-#define ECC_CAPT_ATTR_TSIZ_FOUR_DW		0
-#define ECC_CAPT_ATTR_TSIZ_ONE_DW		1
-#define ECC_CAPT_ATTR_TSIZ_TWO_DW		2
-#define ECC_CAPT_ATTR_TSIZ_THREE_DW		3
-#define ECC_CAPT_ATTR_TSIZ_SHIFT		24
-#define ECC_CAPT_ATTR_TSRC			(0xf8000000>>11)	/* Transaction Source */
-#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT		0x0
-#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF		0x2
-#define ECC_CAPT_ATTR_TSRC_TSEC1		0x4
-#define ECC_CAPT_ATTR_TSRC_TSEC2		0x5
-#define ECC_CAPT_ATTR_TSRC_USB			(0x06|0x07)
-#define ECC_CAPT_ATTR_TSRC_ENCRYPT		0x8
-#define ECC_CAPT_ATTR_TSRC_I2C			0x9
-#define ECC_CAPT_ATTR_TSRC_JTAG			0xA
-#define ECC_CAPT_ATTR_TSRC_PCI1			0xD
-#define ECC_CAPT_ATTR_TSRC_PCI2			0xE
-#define ECC_CAPT_ATTR_TSRC_DMA			0xF
-#define ECC_CAPT_ATTR_TSRC_SHIFT		16
-#define ECC_CAPT_ATTR_TTYP			(0xe0000000>>18)	/* Transaction Type */
-#define ECC_CAPT_ATTR_TTYP_WRITE		0x1
-#define ECC_CAPT_ATTR_TTYP_READ			0x2
-#define ECC_CAPT_ATTR_TTYP_R_M_W		0x3
-#define ECC_CAPT_ATTR_TTYP_SHIFT		12
-#define ECC_CAPT_ATTR_VLD			(0x80000000>>31)	/* Valid */
-	u32 capture_address;	/**< Memory Error Address Capture */
-	u32 capture_ext_address;/**< Memory Error Extended Address Capture */
-	u32 err_sbe;		/**< Memory Single-Bit ECC Error Management */
-#define ECC_ERROR_MAN_SBET			(0xff000000>>8) /* Single-Bit Error Threshold 0..255 */
-#define ECC_ERROR_MAN_SBET_SHIFT		16
-#define ECC_ERROR_MAN_SBEC			(0xff000000>>24)	/* Single Bit Error Counter 0..255 */
-#define ECC_ERROR_MAN_SBEC_SHIFT		0
+	u32 err_detect;		/* Memory Error Detect */
+	u32 err_disable;	/* Memory Error Disable */
+	u32 err_int_en;		/* Memory Error Interrupt Enable */
+	u32 capture_attributes;	/* Memory Error Attributes Capture */
+	u32 capture_address;	/* Memory Error Address Capture */
+	u32 capture_ext_address;/* Memory Error Extended Address Capture */
+	u32 err_sbe;		/* Memory Single-Bit ECC Error Management */
 	u8 res7[0xA4];
 	u32 debug_reg;
 	u8 res8[0xFC];
 } ddr83xx_t;
 
 /*
- * I2C1 Controller
- */
-
-/*
  * DUART
  */
 typedef struct duart83xx {
-	u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */
-	u8 uier_udmb;	   /**< combined register for UIER and UDMB */
-	u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */
-	u8 ulcr;	/**< line control register */
-	u8 umcr;	/**< MODEM control register */
-	u8 ulsr;	/**< line status register */
-	u8 umsr;	/**< MODEM status register */
-	u8 uscr;	/**< scratch register */
+	u8 urbr_ulcr_udlb;	/* combined register for URBR, UTHR and UDLB */
+	u8 uier_udmb;		/* combined register for UIER and UDMB */
+	u8 uiir_ufcr_uafr;	/* combined register for UIIR, UFCR and UAFR */
+	u8 ulcr;		/* line control register */
+	u8 umcr;		/* MODEM control register */
+	u8 ulsr;		/* line status register */
+	u8 umsr;		/* MODEM status register */
+	u8 uscr;		/* scratch register */
 	u8 res0[8];
-	u8 udsr;	/**< DMA status register */
+	u8 udsr;		/* DMA status register */
 	u8 res1[3];
 	u8 res2[0xEC];
 } duart83xx_t;
@@ -1119,75 +327,52 @@ typedef struct duart83xx {
  * Local Bus Controller Registers
  */
 typedef struct lbus_bank {
-	u32 br;		    /**< Base Register	*/
-	u32 or;		    /**< Base Register	*/
+	u32 br;			/* Base Register */
+	u32 or;			/* Option Register */
 } lbus_bank_t;
 
 typedef struct lbus83xx {
 	lbus_bank_t bank[8];
 	u8 res0[0x28];
-	u32 mar;		/**< UPM Address Register */
+	u32 mar;		/* UPM Address Register */
 	u8 res1[0x4];
-	u32 mamr;		/**< UPMA Mode Register */
-	u32 mbmr;		/**< UPMB Mode Register */
-	u32 mcmr;		/**< UPMC Mode Register */
+	u32 mamr;		/* UPMA Mode Register */
+	u32 mbmr;		/* UPMB Mode Register */
+	u32 mcmr;		/* UPMC Mode Register */
 	u8 res2[0x8];
-	u32 mrtpr;		/**< Memory Refresh Timer Prescaler Register */
-	u32 mdr;		/**< UPM Data Register */
+	u32 mrtpr;		/* Memory Refresh Timer Prescaler Register */
+	u32 mdr;		/* UPM Data Register */
 	u8 res3[0x8];
-	u32 lsdmr;		/**< SDRAM Mode Register */
+	u32 lsdmr;		/* SDRAM Mode Register */
 	u8 res4[0x8];
-	u32 lurt;		/**< UPM Refresh Timer */
-	u32 lsrt;		/**< SDRAM Refresh Timer */
+	u32 lurt;		/* UPM Refresh Timer */
+	u32 lsrt;		/* SDRAM Refresh Timer */
 	u8 res5[0x8];
-	u32 ltesr;		/**< Transfer Error Status Register */
-	u32 ltedr;		/**< Transfer Error Disable Register */
-	u32 lteir;		/**< Transfer Error Interrupt Register */
-	u32 lteatr;		/**< Transfer Error Attributes Register */
-	u32 ltear;		/**< Transfer Error Address Register */
+	u32 ltesr;		/* Transfer Error Status Register */
+	u32 ltedr;		/* Transfer Error Disable Register */
+	u32 lteir;		/* Transfer Error Interrupt Register */
+	u32 lteatr;		/* Transfer Error Attributes Register */
+	u32 ltear;		/* Transfer Error Address Register */
 	u8 res6[0xC];
-	u32 lbcr;		/**< Configuration Register */
-#define LBCR_LDIS  0x80000000
-#define LBCR_LDIS_SHIFT	   31
-#define LBCR_BCTLC 0x00C00000
-#define LBCR_BCTLC_SHIFT   22
-#define LBCR_LPBSE 0x00020000
-#define LBCR_LPBSE_SHIFT   17
-#define LBCR_EPAR  0x00010000
-#define LBCR_EPAR_SHIFT	   16
-#define LBCR_BMT   0x0000FF00
-#define LBCR_BMT_SHIFT	    8
-	u32 lcrr;		/**< Clock Ratio Register */
-#define LCRR_DBYP    0x80000000
-#define LCRR_DBYP_SHIFT	     31
-#define LCRR_BUFCMDC 0x30000000
-#define LCRR_BUFCMDC_SHIFT   28
-#define LCRR_ECL     0x03000000
-#define LCRR_ECL_SHIFT	     24
-#define LCRR_EADC    0x00030000
-#define LCRR_EADC_SHIFT	     16
-#define LCRR_CLKDIV  0x0000000F
-#define LCRR_CLKDIV_SHIFT     0
-
+	u32 lbcr;		/* Configuration Register */
+	u32 lcrr;		/* Clock Ratio Register */
 	u8 res7[0x28];
 	u8 res8[0xF00];
 } lbus83xx_t;
 
-#if defined (CONFIG_MPC8349)
 /*
  * Serial Peripheral Interface
  */
 typedef struct spi83xx {
-	u32 mode;     /**< mode register  */
-	u32 event;    /**< event register */
-	u32 mask;     /**< mask register  */
-	u32 com;      /**< command register */
+	u32 mode;		/* mode register */
+	u32 event;		/* event register */
+	u32 mask;		/* mask register */
+	u32 com;		/* command register */
 	u8 res0[0x10];
-	u32 tx;	      /**< transmit register */
-	u32 rx;	      /**< receive register */
-	u8 res1[0xD8];
+	u32 tx;			/* transmit register */
+	u32 rx;			/* receive register */
+	u8 res1[0xFD8];
 } spi83xx_t;
-#endif
 
 /*
  * DMA/Messaging Unit
@@ -1197,21 +382,17 @@ typedef struct dma83xx {
 	u32 omisr;		/* 0x30 Outbound message interrupt status register */
 	u32 omimr;		/* 0x34 Outbound message interrupt mask register */
 	u32 res1[0x6];		/* 0x38-0x49 reserved */
-
 	u32 imr0;		/* 0x50 Inbound message register 0 */
 	u32 imr1;		/* 0x54 Inbound message register 1 */
 	u32 omr0;		/* 0x58 Outbound message register 0 */
 	u32 omr1;		/* 0x5C Outbound message register 1 */
-
 	u32 odr;		/* 0x60 Outbound doorbell register */
 	u32 res2;		/* 0x64-0x67 reserved */
 	u32 idr;		/* 0x68 Inbound doorbell register */
 	u32 res3[0x5];		/* 0x6C-0x79 reserved */
-
 	u32 imisr;		/* 0x80 Inbound message interrupt status register */
 	u32 imimr;		/* 0x84 Inbound message interrupt mask register */
 	u32 res4[0x1E];		/* 0x88-0x99 reserved */
-
 	u32 dmamr0;		/* 0x100 DMA 0 mode register */
 	u32 dmasr0;		/* 0x104 DMA 0 status register */
 	u32 dmacdar0;		/* 0x108 DMA 0 current descriptor address register */
@@ -1223,7 +404,6 @@ typedef struct dma83xx {
 	u32 dmabcr0;		/* 0x120 DMA 0 byte count register */
 	u32 dmandar0;		/* 0x124 DMA 0 next descriptor address register */
 	u32 res8[0x16];		/* 0x128-0x179 reserved */
-
 	u32 dmamr1;		/* 0x180 DMA 1 mode register */
 	u32 dmasr1;		/* 0x184 DMA 1 status register */
 	u32 dmacdar1;		/* 0x188 DMA 1 current descriptor address register */
@@ -1235,7 +415,6 @@ typedef struct dma83xx {
 	u32 dmabcr1;		/* 0x1A0 DMA 1 byte count register */
 	u32 dmandar1;		/* 0x1A4 DMA 1 next descriptor address register */
 	u32 res12[0x16];	/* 0x1A8-0x199 reserved */
-
 	u32 dmamr2;		/* 0x200 DMA 2 mode register */
 	u32 dmasr2;		/* 0x204 DMA 2 status register */
 	u32 dmacdar2;		/* 0x208 DMA 2 current descriptor address register */
@@ -1247,7 +426,6 @@ typedef struct dma83xx {
 	u32 dmabcr2;		/* 0x220 DMA 2 byte count register */
 	u32 dmandar2;		/* 0x224 DMA 2 next descriptor address register */
 	u32 res16[0x16];	/* 0x228-0x279 reserved */
-
 	u32 dmamr3;		/* 0x280 DMA 3 mode register */
 	u32 dmasr3;		/* 0x284 DMA 3 status register */
 	u32 dmacdar3;		/* 0x288 DMA 3 current descriptor address register */
@@ -1258,39 +436,15 @@ typedef struct dma83xx {
 	u32 res19;		/* 0x29C reserved */
 	u32 dmabcr3;		/* 0x2A0 DMA 3 byte count register */
 	u32 dmandar3;		/* 0x2A4 DMA 3 next descriptor address register */
-
 	u32 dmagsr;		/* 0x2A8 DMA general status register */
 	u32 res20[0x15];	/* 0x2AC-0x2FF reserved */
 } dma83xx_t;
 
-/* DMAMRn bits */
-#define DMA_CHANNEL_START			(0x00000001)	/* Bit - DMAMRn CS */
-#define DMA_CHANNEL_TRANSFER_MODE_DIRECT	(0x00000004)	/* Bit - DMAMRn CTM */
-#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN	(0x00001000)	/* Bit - DMAMRn SAHE */
-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B	(0x00000000)	/* 2Bit- DMAMRn SAHTS 1byte */
-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B	(0x00004000)	/* 2Bit- DMAMRn SAHTS 2bytes */
-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B	(0x00008000)	/* 2Bit- DMAMRn SAHTS 4bytes */
-#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B	(0x0000c000)	/* 2Bit- DMAMRn SAHTS 8bytes */
-#define DMA_CHANNEL_SNOOP			(0x00010000)	/* Bit - DMAMRn DMSEN */
-
-/* DMASRn bits */
-#define DMA_CHANNEL_BUSY			(0x00000004)	/* Bit - DMASRn CB */
-#define DMA_CHANNEL_TRANSFER_ERROR		(0x00000080)	/* Bit - DMASRn TE */
-
 /*
  * PCI Software Configuration Registers
  */
 typedef struct pciconf83xx {
 	u32 config_address;
-#define PCI_CONFIG_ADDRESS_EN	0x80000000
-#define PCI_CONFIG_ADDRESS_BN_SHIFT	16
-#define PCI_CONFIG_ADDRESS_BN_MASK	0x00ff0000
-#define PCI_CONFIG_ADDRESS_DN_SHIFT	11
-#define PCI_CONFIG_ADDRESS_DN_MASK	0x0000f800
-#define PCI_CONFIG_ADDRESS_FN_SHIFT	8
-#define PCI_CONFIG_ADDRESS_FN_MASK	0x00000700
-#define PCI_CONFIG_ADDRESS_RN_SHIFT	0
-#define PCI_CONFIG_ADDRESS_RN_MASK	0x000000fc
 	u32 config_data;
 	u32 int_ack;
 	u8 res[116];
@@ -1313,34 +467,6 @@ typedef struct pci_outbound_window {
  */
 typedef struct ios83xx {
 	pot83xx_t pot[6];
-#define POTAR_TA_MASK	0x000fffff
-#define POBAR_BA_MASK	0x000fffff
-#define POCMR_EN	0x80000000
-#define POCMR_IO	0x40000000	/* 0--memory space 1--I/O space */
-#define POCMR_SE	0x20000000	/* streaming enable */
-#define POCMR_DST	0x10000000	/* 0--PCI1 1--PCI2 */
-#define POCMR_CM_MASK	0x000fffff
-#define POCMR_CM_4G	0x00000000
-#define POCMR_CM_2G	0x00080000
-#define POCMR_CM_1G	0x000C0000
-#define POCMR_CM_512M	0x000E0000
-#define POCMR_CM_256M	0x000F0000
-#define POCMR_CM_128M	0x000F8000
-#define POCMR_CM_64M	0x000FC000
-#define POCMR_CM_32M	0x000FE000
-#define POCMR_CM_16M	0x000FF000
-#define POCMR_CM_8M	0x000FF800
-#define POCMR_CM_4M	0x000FFC00
-#define POCMR_CM_2M	0x000FFE00
-#define POCMR_CM_1M	0x000FFF00
-#define POCMR_CM_512K	0x000FFF80
-#define POCMR_CM_256K	0x000FFFC0
-#define POCMR_CM_128K	0x000FFFE0
-#define POCMR_CM_64K	0x000FFFF0
-#define POCMR_CM_32K	0x000FFFF8
-#define POCMR_CM_16K	0x000FFFFC
-#define POCMR_CM_8K	0x000FFFFE
-#define POCMR_CM_4K	0x000FFFFF
 	u8 res0[0x60];
 	u32 pmcr;
 	u8 res1[4];
@@ -1353,74 +479,13 @@ typedef struct ios83xx {
  */
 typedef struct pcictrl83xx {
 	u32 esr;
-#define ESR_MERR	0x80000000
-#define ESR_APAR	0x00000400
-#define ESR_PCISERR	0x00000200
-#define ESR_MPERR	0x00000100
-#define ESR_TPERR	0x00000080
-#define ESR_NORSP	0x00000040
-#define ESR_TABT	0x00000020
 	u32 ecdr;
-#define ECDR_APAR	0x00000400
-#define ECDR_PCISERR	0x00000200
-#define ECDR_MPERR	0x00000100
-#define ECDR_TPERR	0x00000080
-#define ECDR_NORSP	0x00000040
-#define ECDR_TABT	0x00000020
 	u32 eer;
-#define EER_APAR	0x00000400
-#define EER_PCISERR	0x00000200
-#define EER_MPERR	0x00000100
-#define EER_TPERR	0x00000080
-#define EER_NORSP	0x00000040
-#define EER_TABT	0x00000020
 	u32 eatcr;
-#define EATCR_ERRTYPR_MASK	0x70000000
-#define EATCR_ERRTYPR_APR	0x00000000	/* address parity error */
-#define EATCR_ERRTYPR_WDPR	0x10000000	/* write data parity error */
-#define EATCR_ERRTYPR_RDPR	0x20000000	/* read data parity error */
-#define EATCR_ERRTYPR_MA	0x30000000	/* master abort */
-#define EATCR_ERRTYPR_TA	0x40000000	/* target abort */
-#define EATCR_ERRTYPR_SE	0x50000000	/* system error indication received */
-#define EATCR_ERRTYPR_PEA	0x60000000	/* parity error indication received on a read */
-#define EATCR_ERRTYPR_PEW	0x70000000	/* parity error indication received on a write */
-#define EATCR_BN_MASK		0x0f000000	/* beat number */
-#define EATCR_BN_1st		0x00000000
-#define EATCR_BN_2ed		0x01000000
-#define EATCR_BN_3rd		0x02000000
-#define EATCR_BN_4th		0x03000000
-#define EATCR_BN_5th		0x0400000
-#define EATCR_BN_6th		0x05000000
-#define EATCR_BN_7th		0x06000000
-#define EATCR_BN_8th		0x07000000
-#define EATCR_BN_9th		0x08000000
-#define EATCR_TS_MASK		0x00300000	/* transaction size */
-#define EATCR_TS_4		0x00000000
-#define EATCR_TS_1		0x00100000
-#define EATCR_TS_2		0x00200000
-#define EATCR_TS_3		0x00300000
-#define EATCR_ES_MASK		0x000f0000	/* error source */
-#define EATCR_ES_EM		0x00000000	/* external master */
-#define EATCR_ES_DMA		0x00050000
-#define EATCR_CMD_MASK		0x0000f000
-#if defined (CONFIG_MPC8349)
-#define EATCR_HBE_MASK		0x00000f00	/* PCI high byte enable */
-#endif
-#define EATCR_BE_MASK		0x000000f0	/* PCI byte enable */
-#if defined (CONFIG_MPC8349)
-#define EATCR_HPB		0x00000004	/* high parity bit */
-#endif
-#define EATCR_PB		0x00000002	/* parity bit */
-#define EATCR_VI		0x00000001	/* error information valid */
 	u32 eacr;
 	u32 eeacr;
-#if defined (CONFIG_MPC8349)
 	u32 edlcr;
 	u32 edhcr;
-#elif defined (CONFIG_MPC8360)
-	u32 edcr;		/* was edlcr */
-	u8 res_edcr[0x4];
-#endif
 	u32 gcr;
 	u32 ecr;
 	u32 gsr;
@@ -1443,41 +508,8 @@ typedef struct pcictrl83xx {
 	u8 res6[4];
 	u32 piwar0;
 	u8 res7[132];
-#define PITAR_TA_MASK		0x000fffff
-#define PIBAR_MASK		0xffffffff
-#define PIEBAR_EBA_MASK		0x000fffff
-#define PIWAR_EN		0x80000000
-#define PIWAR_PF		0x20000000
-#define PIWAR_RTT_MASK		0x000f0000
-#define PIWAR_RTT_NO_SNOOP	0x00040000
-#define PIWAR_RTT_SNOOP		0x00050000
-#define PIWAR_WTT_MASK		0x0000f000
-#define PIWAR_WTT_NO_SNOOP	0x00004000
-#define PIWAR_WTT_SNOOP		0x00005000
-#define PIWAR_IWS_MASK	0x0000003F
-#define PIWAR_IWS_4K	0x0000000B
-#define PIWAR_IWS_8K	0x0000000C
-#define PIWAR_IWS_16K	0x0000000D
-#define PIWAR_IWS_32K	0x0000000E
-#define PIWAR_IWS_64K	0x0000000F
-#define PIWAR_IWS_128K	0x00000010
-#define PIWAR_IWS_256K	0x00000011
-#define PIWAR_IWS_512K	0x00000012
-#define PIWAR_IWS_1M	0x00000013
-#define PIWAR_IWS_2M	0x00000014
-#define PIWAR_IWS_4M	0x00000015
-#define PIWAR_IWS_8M	0x00000016
-#define PIWAR_IWS_16M	0x00000017
-#define PIWAR_IWS_32M	0x00000018
-#define PIWAR_IWS_64M	0x00000019
-#define PIWAR_IWS_128M	0x0000001A
-#define PIWAR_IWS_256M	0x0000001B
-#define PIWAR_IWS_512M	0x0000001C
-#define PIWAR_IWS_1G	0x0000001D
-#define PIWAR_IWS_2G	0x0000001E
 } pcictrl83xx_t;
 
-#if defined (CONFIG_MPC8349)
 /*
  * USB
  */
@@ -1491,7 +523,6 @@ typedef struct usb83xx {
 typedef struct tsec83xx {
 	u8 fixme[0x1000];
 } tsec83xx_t;
-#endif
 
 /*
  * Security
@@ -1500,581 +531,82 @@ typedef struct security83xx {
 	u8 fixme[0x10000];
 } security83xx_t;
 
-#if defined (CONFIG_MPC8360)
-/*
- * iram
- */
-typedef struct iram83xx {
-	u32 iadd;		/* I-RAM address register */
-	u32 idata;		/* I-RAM data register */
-	u8 res0[0x78];
-} iram83xx_t;
-
-/*
- * Interrupt Controller
- */
-typedef struct irq83xx {
-	u32 cicr;		/* QE system interrupt configuration */
-	u32 civec;		/* QE system interrupt vector register */
-	u32 cripnr;		/* QE RISC interrupt pending register */
-	u32 cipnr;		/*  QE system interrupt pending register */
-	u32 cipxcc;		/* QE interrupt priority register */
-	u32 cipycc;		/* QE interrupt priority register */
-	u32 cipwcc;		/* QE interrupt priority register */
-	u32 cipzcc;		/* QE interrupt priority register */
-	u32 cimr;		/* QE system interrupt mask register */
-	u32 crimr;		/* QE RISC interrupt mask register */
-	u32 cicnr;		/* QE system interrupt control register */
-	u8 res0[0x4];
-	u32 ciprta;		/* QE system interrupt priority register for RISC tasks A */
-	u32 ciprtb;		/* QE system interrupt priority register for RISC tasks B */
-	u8 res1[0x4];
-	u32 cricr;		/* QE system RISC interrupt control */
-	u8 res2[0x20];
-	u32 chivec;		/* QE high system interrupt vector */
-	u8 res3[0x1C];
-} irq83xx_t;
-
-/*
- * Communications Processor
- */
-typedef struct cp83xx {
-	u32 cecr;		/* QE command register */
-	u32 ceccr;		/* QE controller configuration register */
-	u32 cecdr;		/* QE command data register */
-	u8 res0[0xA];
-	u16 ceter;		/* QE timer event register */
-	u8 res1[0x2];
-	u16 cetmr;		/* QE timers mask register */
-	u32 cetscr;		/* QE time-stamp timer control register */
-	u32 cetsr1;		/* QE time-stamp register 1 */
-	u32 cetsr2;		/* QE time-stamp register 2 */
-	u8 res2[0x8];
-	u32 cevter;		/* QE virtual tasks event register */
-	u32 cevtmr;		/* QE virtual tasks mask register */
-	u16 cercr;		/* QE RAM control register */
-	u8 res3[0x2];
-	u8 res4[0x24];
-	u16 ceexe1;		/* QE external request 1 event register */
-	u8 res5[0x2];
-	u16 ceexm1;		/* QE external request 1 mask register */
-	u8 res6[0x2];
-	u16 ceexe2;		/* QE external request 2 event register */
-	u8 res7[0x2];
-	u16 ceexm2;		/* QE external request 2 mask register */
-	u8 res8[0x2];
-	u16 ceexe3;		/* QE external request 3 event register */
-	u8 res9[0x2];
-	u16 ceexm3;		/* QE external request 3 mask register */
-	u8 res10[0x2];
-	u16 ceexe4;		/* QE external request 4 event register */
-	u8 res11[0x2];
-	u16 ceexm4;		/* QE external request 4 mask register */
-	u8 res12[0x2];
-	u8 res13[0x280];
-} cp83xx_t;
-
-/*
- * QE Multiplexer
- */
-
-typedef struct qmx83xx {
-	u32 cmxgcr;		/* CMX general clock route register */
-	u32 cmxsi1cr_l;		/* CMX SI1 clock route low register */
-	u32 cmxsi1cr_h;		/* CMX SI1 clock route high register */
-	u32 cmxsi1syr;		/* CMX SI1 SYNC route register */
-	u32 cmxucr1;		/* CMX UCC1, UCC3 clock route register */
-	u32 cmxucr2;		/* CMX UCC5, UCC7 clock route register */
-	u32 cmxucr3;		/* CMX UCC2, UCC4 clock route register */
-	u32 cmxucr4;		/* CMX UCC6, UCC8 clock route register */
-	u32 cmxupcr;		/* CMX UPC clock route register */
-	u8 res0[0x1C];
-} qmx83xx_t;
-
-/*
-* QE Timers
-*/
-
-typedef struct qet83xx {
-	u8 gtcfr1;		/* Timer 1 and Timer 2 global configuration register */
-	u8 res0[0x3];
-	u8 gtcfr2;		/* Timer 3 and timer 4 global configuration register */
-	u8 res1[0xB];
-	u16 gtmdr1;		/* Timer 1 mode register */
-	u16 gtmdr2;		/* Timer 2 mode register */
-	u16 gtrfr1;		/* Timer 1 reference register */
-	u16 gtrfr2;		/* Timer 2 reference register */
-	u16 gtcpr1;		/* Timer 1 capture register */
-	u16 gtcpr2;		/* Timer 2 capture register */
-	u16 gtcnr1;		/* Timer 1 counter */
-	u16 gtcnr2;		/* Timer 2 counter */
-	u16 gtmdr3;		/* Timer 3 mode register */
-	u16 gtmdr4;		/* Timer 4 mode register */
-	u16 gtrfr3;		/* Timer 3 reference register */
-	u16 gtrfr4;		/* Timer 4 reference register */
-	u16 gtcpr3;		/* Timer 3 capture register */
-	u16 gtcpr4;		/* Timer 4 capture register */
-	u16 gtcnr3;		/* Timer 3 counter */
-	u16 gtcnr4;		/* Timer 4 counter */
-	u16 gtevr1;		/* Timer 1 event register */
-	u16 gtevr2;		/* Timer 2 event register */
-	u16 gtevr3;		/* Timer 3 event register */
-	u16 gtevr4;		/* Timer 4 event register */
-	u16 gtps;		/* Timer 1 prescale register */
-	u8 res2[0x46];
-} qet83xx_t;
-
-/*
-* spi
-*/
-
-typedef struct spi83xx {
-	u8 res0[0x20];
-	u32 spmode;		/* SPI mode register */
-	u8 res1[0x2];
-	u8 spie;		/* SPI event register */
-	u8 res2[0x1];
-	u8 res3[0x2];
-	u8 spim;		/* SPI mask register */
-	u8 res4[0x1];
-	u8 res5[0x1];
-	u8 spcom;		/* SPI command register	 */
-	u8 res6[0x2];
-	u32 spitd;		/* SPI transmit data register (cpu mode) */
-	u32 spird;		/* SPI receive data register (cpu mode) */
-	u8 res7[0x8];
-} spi83xx_t;
-
-/*
-* mcc
-*/
-
-typedef struct mcc83xx {
-	u32 mcce;		/* MCC event register */
-	u32 mccm;		/* MCC mask register */
-	u32 mccf;		/* MCC configuration register */
-	u32 merl;		/* MCC emergency request level register */
-	u8 res0[0xF0];
-} mcc83xx_t;
-
-/*
-* brg
-*/
-
-typedef struct brg83xx {
-	u32 brgc1;		/* BRG1 configuration register */
-	u32 brgc2;		/* BRG2 configuration register */
-	u32 brgc3;		/* BRG3 configuration register */
-	u32 brgc4;		/* BRG4 configuration register */
-	u32 brgc5;		/* BRG5 configuration register */
-	u32 brgc6;		/* BRG6 configuration register */
-	u32 brgc7;		/* BRG7 configuration register */
-	u32 brgc8;		/* BRG8 configuration register */
-	u32 brgc9;		/* BRG9 configuration register */
-	u32 brgc10;		/* BRG10 configuration register */
-	u32 brgc11;		/* BRG11 configuration register */
-	u32 brgc12;		/* BRG12 configuration register */
-	u32 brgc13;		/* BRG13 configuration register */
-	u32 brgc14;		/* BRG14 configuration register */
-	u32 brgc15;		/* BRG15 configuration register */
-	u32 brgc16;		/* BRG16 configuration register */
-	u8 res0[0x40];
-} brg83xx_t;
-
-/*
-* USB
-*/
-
-typedef struct usb83xx {
-	u8 usmod;		/* USB mode register */
-	u8 usadd;		/* USB address register */
-	u8 uscom;		/* USB command register */
-	u8 res0[0x1];
-	u16 usep0;		/* USB endpoint register 0 */
-	u16 usep1;		/* USB endpoint register 1 */
-	u16 usep2;		/* USB endpoint register 2 */
-	u16 usep3;		/* USB endpoint register 3 */
-	u8 res1[0x4];
-	u16 usber;		/* USB event register */
-	u8 res2[0x2];
-	u16 usbmr;		/* USB mask register */
-	u8 res3[0x1];
-	u8 usbs;		/* USB status register */
-	u32 ussft;		/* USB start of frame timer */
-	u8 res4[0x24];
-} usb83xx_t;
-
-/*
-* SI
-*/
-
-typedef struct si1_83xx {
-	u16 siamr1;		/* SI1 TDMA mode register */
-	u16 sibmr1;		/* SI1 TDMB mode register */
-	u16 sicmr1;		/* SI1 TDMC mode register */
-	u16 sidmr1;		/* SI1 TDMD mode register */
-	u8 siglmr1_h;		/* SI1 global mode register high */
-	u8 res0[0x1];
-	u8 sicmdr1_h;		/* SI1 command register high */
-	u8 res2[0x1];
-	u8 sistr1_h;		/* SI1 status register high */
-	u8 res3[0x1];
-	u16 sirsr1_h;		/* SI1 RAM shadow address register high */
-	u8 sitarc1;		/* SI1 RAM counter Tx TDMA */
-	u8 sitbrc1;		/* SI1 RAM counter Tx TDMB */
-	u8 sitcrc1;		/* SI1 RAM counter Tx TDMC */
-	u8 sitdrc1;		/* SI1 RAM counter Tx TDMD */
-	u8 sirarc1;		/* SI1 RAM counter Rx TDMA */
-	u8 sirbrc1;		/* SI1 RAM counter Rx TDMB */
-	u8 sircrc1;		/* SI1 RAM counter Rx TDMC */
-	u8 sirdrc1;		/* SI1 RAM counter Rx TDMD */
-	u8 res4[0x8];
-	u16 siemr1;		/* SI1 TDME mode register 16 bits */
-	u16 sifmr1;		/* SI1 TDMF mode register 16 bits */
-	u16 sigmr1;		/* SI1 TDMG mode register 16 bits */
-	u16 sihmr1;		/* SI1 TDMH mode register 16 bits */
-	u8 siglmg1_l;		/* SI1 global mode register low 8 bits */
-	u8 res5[0x1];
-	u8 sicmdr1_l;		/* SI1 command register low 8 bits */
-	u8 res6[0x1];
-	u8 sistr1_l;		/* SI1 status register low 8 bits */
-	u8 res7[0x1];
-	u16 sirsr1_l;		/* SI1 RAM shadow address register low 16 bits */
-	u8 siterc1;		/* SI1 RAM counter Tx TDME 8 bits */
-	u8 sitfrc1;		/* SI1 RAM counter Tx TDMF 8 bits */
-	u8 sitgrc1;		/* SI1 RAM counter Tx TDMG 8 bits */
-	u8 sithrc1;		/* SI1 RAM counter Tx TDMH 8 bits */
-	u8 sirerc1;		/* SI1 RAM counter Rx TDME 8 bits */
-	u8 sirfrc1;		/* SI1 RAM counter Rx TDMF 8 bits */
-	u8 sirgrc1;		/* SI1 RAM counter Rx TDMG 8 bits */
-	u8 sirhrc1;		/* SI1 RAM counter Rx TDMH 8 bits */
-	u8 res8[0x8];
-	u32 siml1;		/* SI1 multiframe limit register */
-	u8 siedm1;		/* SI1 extended diagnostic mode register */
-	u8 res9[0xBB];
-} si1_83xx_t;
-
-/*
-*  SI Routing Tables
-*/
-
-typedef struct sir83xx {
-	u8 tx[0x400];
-	u8 rx[0x400];
-	u8 res0[0x800];
-} sir83xx_t;
-
-/*
-* ucc
-*/
-
-typedef struct uslow {
-	u32 gumr_l;		/* UCCx general mode register (low) */
-	u32 gumr_h;		/* UCCx general mode register (high) */
-	u16 upsmr;		/* UCCx protocol-specific mode register */
-	u8 res0[0x2];
-	u16 utodr;		/* UCCx transmit on demand register */
-	u16 udsr;		/* UCCx data synchronization register */
-	u16 ucce;		/* UCCx event register */
-	u8 res1[0x2];
-	u16 uccm;		/* UCCx mask register */
-	u8 res2[0x1];
-	u8 uccs;		/* UCCx status register */
-	u8 res3[0x1E8];
-} uslow_t;
-
-typedef struct ufast {
-	u32 gumr;		/* UCCx general mode register */
-	u32 upsmr;		/* UCCx protocol-specific mode register	 */
-	u16 utodr;		/* UCCx transmit on demand register  */
-	u8 res0[0x2];
-	u16 udsr;		/* UCCx data synchronization register  */
-	u8 res1[0x2];
-	u32 ucce;		/* UCCx event register */
-	u32 uccm;		/* UCCx mask register.	*/
-	u8 uccs;		/* UCCx status register */
-	u8 res2[0x7];
-	u32 urfb;		/* UCC receive FIFO base  */
-	u16 urfs;		/* UCC receive FIFO size  */
-	u8 res3[0x2];
-	u16 urfet;		/* UCC receive FIFO emergency threshold	 */
-	u16 urfset;		/* UCC receive FIFO special emergency threshold	 */
-	u32 utfb;		/* UCC transmit FIFO base */
-	u16 utfs;		/* UCC transmit FIFO size  */
-	u8 res4[0x2];
-	u16 utfet;		/* UCC transmit FIFO emergency threshold */
-	u8 res5[0x2];
-	u16 utftt;		/* UCC transmit FIFO transmit threshold */
-	u8 res6[0x2];
-	u16 utpt;		/* UCC transmit polling timer */
-	u32 urtry;		/* UCC retry counter register */
-	u8 res7[0x4C];
-	u8 guemr;		/* UCC general extended mode register */
-	u8 res8[0x3];
-	u8 res9[0x6C];
-	u32 maccfg1;		/* Mac configuration register #1  */
-	u32 maccfg2;		/* Mac configuration register #2  */
-	u16 ipgifg;		/* Interframe gap register  */
-	u8 res10[0x2];
-	u32 hafdup;		/* Half-duplex register	 */
-	u8 res11[0xC];
-	u32 emtr;		/* Ethernet MAC test register  */
-	u32 miimcfg;		/* MII mgmt configuration register  */
-	u32 miimcom;		/* MII mgmt command register  */
-	u32 miimadd;		/* MII mgmt address register  */
-	u32 miimcon;		/* MII mgmt control register  */
-	u32 miistat;		/* MII mgmt status register */
-	u32 miimnd;		/* MII mgmt indication register */
-	u32 ifctl;		/* Interface control register  */
-	u32 ifstat;		/* Interface status register  */
-	u32 macstnaddr1;	/* Station address part 1 register */
-	u32 macstnaddr2;	/* Station address part 2 register */
-	u8 res12[0x8];
-	u32 uempr;		/* UCC Ethernet MAC parameter register */
-	u32 utbipa;		/* UCC TBI address */
-	u16 uescr;		/* UCC Ethernet statistics control register */
-	u8 res13[0x26];
-	u32 tx64;		/* Transmit and receive 64-byte frame counter */
-	u32 tx127;		/* Transmit and receive 65- to 127-byte frame counter */
-	u32 tx255;		/* Transmit and receive 128- to 255-byte frame counter */
-	u32 rx64;		/* Receive and receive 64-byte frame counter */
-	u32 rx127;		/* Receive and receive 65- to 127-byte frame counter */
-	u32 rx255;		/* Receive and receive 128- to 255-byte frame counter */
-	u32 txok;		/* Transmit good bytes counter */
-	u32 txcf;		/* Transmit control frame counter */
-	u32 tmca;		/* Transmit multicast control frame counter */
-	u32 tbca;		/* Transmit broadcast packet counter */
-	u32 rxfok;		/* Receive frame OK counter */
-	u32 rbyt;		/* Receive good and bad bytes counter */
-	u32 rxbok;		/* Receive bytes OK counter */
-	u32 rmca;		/* Receive multicast packet counter */
-	u32 rbca;		/* Receive broadcast packet counter */
-	u32 scar;		/* Statistics carry register */
-	u32 scam;		/* Statistics carry mask register */
-	u8 res14[0x3C];
-} ufast_t;
-
-typedef struct ucc83xx {
-	union {
-		uslow_t slow;
-		ufast_t fast;
-	};
-} ucc83xx_t;
-
-/*
-*  MultiPHY UTOPIA POS Controllers
-*/
-
-typedef struct upc83xx {
-	u32 upgcr;		/* UTOPIA/POS general configuration register  */
-#define UPGCR_PROTOCOL	0x80000000	/* protocol ul2 or pl2 */
-#define UPGCR_TMS	0x40000000	/* Transmit master/slave mode */
-#define UPGCR_RMS	0x20000000	/* Receive master/slave mode */
-#define UPGCR_ADDR	0x10000000	/* Master MPHY Addr multiplexing: */
-#define UPGCR_DIAG	0x01000000	/* Diagnostic mode */
-	u32 uplpa;		/* UTOPIA/POS last PHY address */
-	u32 uphec;		/* ATM HEC register */
-	u32 upuc;		/* UTOPIA/POS UCC configuration */
-	u32 updc1;		/* UTOPIA/POS device 1 configuration */
-	u32 updc2;		/* UTOPIA/POS device 2 configuration  */
-	u32 updc3;		/* UTOPIA/POS device 3 configuration */
-	u32 updc4;		/* UTOPIA/POS device 4 configuration  */
-	u32 upstpa;		/* UTOPIA/POS STPA threshold  */
-	u8 res0[0xC];
-	u32 updrs1_h;		/* UTOPIA/POS device 1 rate select  */
-	u32 updrs1_l;		/* UTOPIA/POS device 1 rate select  */
-	u32 updrs2_h;		/* UTOPIA/POS device 2 rate select  */
-	u32 updrs2_l;		/* UTOPIA/POS device 2 rate select */
-	u32 updrs3_h;		/* UTOPIA/POS device 3 rate select */
-	u32 updrs3_l;		/* UTOPIA/POS device 3 rate select */
-	u32 updrs4_h;		/* UTOPIA/POS device 4 rate select */
-	u32 updrs4_l;		/* UTOPIA/POS device 4 rate select */
-	u32 updrp1;		/* UTOPIA/POS device 1 receive priority low  */
-	u32 updrp2;		/* UTOPIA/POS device 2 receive priority low  */
-	u32 updrp3;		/* UTOPIA/POS device 3 receive priority low  */
-	u32 updrp4;		/* UTOPIA/POS device 4 receive priority low  */
-	u32 upde1;		/* UTOPIA/POS device 1 event */
-	u32 upde2;		/* UTOPIA/POS device 2 event */
-	u32 upde3;		/* UTOPIA/POS device 3 event */
-	u32 upde4;		/* UTOPIA/POS device 4 event */
-	u16 uprp1;
-	u16 uprp2;
-	u16 uprp3;
-	u16 uprp4;
-	u8 res1[0x8];
-	u16 uptirr1_0;		/* Device 1 transmit internal rate 0 */
-	u16 uptirr1_1;		/* Device 1 transmit internal rate 1 */
-	u16 uptirr1_2;		/* Device 1 transmit internal rate 2 */
-	u16 uptirr1_3;		/* Device 1 transmit internal rate 3 */
-	u16 uptirr2_0;		/* Device 2 transmit internal rate 0 */
-	u16 uptirr2_1;		/* Device 2 transmit internal rate 1 */
-	u16 uptirr2_2;		/* Device 2 transmit internal rate 2 */
-	u16 uptirr2_3;		/* Device 2 transmit internal rate 3 */
-	u16 uptirr3_0;		/* Device 3 transmit internal rate 0 */
-	u16 uptirr3_1;		/* Device 3 transmit internal rate 1 */
-	u16 uptirr3_2;		/* Device 3 transmit internal rate 2 */
-	u16 uptirr3_3;		/* Device 3 transmit internal rate 3 */
-	u16 uptirr4_0;		/* Device 4 transmit internal rate 0 */
-	u16 uptirr4_1;		/* Device 4 transmit internal rate 1 */
-	u16 uptirr4_2;		/* Device 4 transmit internal rate 2 */
-	u16 uptirr4_3;		/* Device 4 transmit internal rate 3 */
-	u32 uper1;		/* Device 1 port enable register */
-	u32 uper2;		/* Device 2 port enable register */
-	u32 uper3;		/* Device 3 port enable register */
-	u32 uper4;		/* Device 4 port enable register */
-	u8 res2[0x150];
-} upc83xx_t;
-
-/*
-* SDMA
-*/
-
-typedef struct sdma83xx {
-	u32 sdsr;		/* Serial DMA status register */
-	u32 sdmr;		/* Serial DMA mode register */
-	u32 sdtr1;		/* SDMA system bus threshold register */
-	u32 sdtr2;		/* SDMA secondary bus threshold register */
-	u32 sdhy1;		/* SDMA system bus hysteresis register */
-	u32 sdhy2;		/* SDMA secondary bus hysteresis register */
-	u32 sdta1;		/* SDMA system bus address register */
-	u32 sdta2;		/* SDMA secondary bus address register */
-	u32 sdtm1;		/* SDMA system bus MSNUM register */
-	u32 sdtm2;		/* SDMA secondary bus MSNUM register */
-	u8 res0[0x10];
-	u32 sdaqr;		/* SDMA address bus qualify register */
-	u32 sdaqmr;		/* SDMA address bus qualify mask register */
-	u8 res1[0x4];
-	u32 sdwbcr;		/* SDMA CAM entries base register */
-	u8 res2[0x38];
-} sdma83xx_t;
-
-/*
-* Debug Space
-*/
-
-typedef struct dbg83xx {
-	u32 bpdcr;		/* Breakpoint debug command register */
-	u32 bpdsr;		/* Breakpoint debug status register */
-	u32 bpdmr;		/* Breakpoint debug mask register */
-	u32 bprmrr0;		/* Breakpoint request mode risc register 0 */
-	u32 bprmrr1;		/* Breakpoint request mode risc register 1 */
-	u8 res0[0x8];
-	u32 bprmtr0;		/* Breakpoint request mode trb register 0 */
-	u32 bprmtr1;		/* Breakpoint request mode trb register 1 */
-	u8 res1[0x8];
-	u32 bprmir;		/* Breakpoint request mode immediate register */
-	u32 bprmsr;		/* Breakpoint request mode serial register */
-	u32 bpemr;		/* Breakpoint exit mode register */
-	u8 res2[0x48];
-} dbg83xx_t;
-
-/*
-*  RISC Special Registers (Trap and Breakpoint)
-*/
-
-typedef struct rsp83xx {
-	u8 fixme[0x100];
-} rsp83xx_t;
-#endif
+#if defined(CONFIG_MPC8349)
+typedef struct immap {
+	sysconf83xx_t		sysconf;	/* System configuration */
+	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
+	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
+	rtclk83xx_t		pit;		/* Periodic Interval Timer */
+	gtm83xx_t		gtm[2];		/* Global Timers Module */
+	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
+	reset83xx_t		reset;		/* Reset Module */
+	clk83xx_t		clk;		/* System Clock Module */
+	pmc83xx_t		pmc;		/* Power Management Control Module */
+	gpio83xx_t		gpio[2];	/* General purpose I/O module */
+	u8			res0[0x200];
+	u8			dll_ddr[0x100];
+	u8			dll_lbc[0x100];
+	u8			res1[0xE00];
+	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
+	fsl_i2c_t		i2c[2];		/* I2C Controllers */
+	u8			res2[0x1300];
+	duart83xx_t		duart[2];	/* DUART */
+	u8			res3[0x900];
+	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	u8			res4[0x1000];
+	spi83xx_t		spi;		/* Serial Peripheral Interface */
+	dma83xx_t		dma;		/* DMA */
+	pciconf83xx_t		pci_conf[2];	/* PCI Software Configuration Registers */
+	ios83xx_t		ios;		/* Sequencer */
+	pcictrl83xx_t		pci_ctrl[2];	/* PCI Controller Control and Status Registers */
+	u8			res5[0x19900];
+	usb83xx_t		usb;
+	tsec83xx_t		tsec[2];
+	u8			res6[0xA000];
+	security83xx_t		security;
+	u8			res7[0xC0000];
+} immap_t;
 
+#elif defined(CONFIG_MPC8360)
 typedef struct immap {
-	sysconf83xx_t sysconf;	/* System configuration */
-	wdt83xx_t wdt;		/* Watch Dog Timer (WDT) Registers */
-	rtclk83xx_t rtc;	/* Real Time Clock Module Registers */
-	rtclk83xx_t pit;	/* Periodic Interval Timer */
-	gtm83xx_t gtm[2];	/* Global Timers Module */
-	ipic83xx_t ipic;	/* Integrated Programmable Interrupt Controller */
-	arbiter83xx_t arbiter;	/* System Arbiter Registers */
-	reset83xx_t reset;	/* Reset Module */
-	clk83xx_t clk;		/* System Clock Module */
-	pmc83xx_t pmc;		/* Power Management Control Module */
-#if defined (CONFIG_MPC8349)
-	gpio83xx_t pgio[2];	/* general purpose I/O module */
-#elif defined (CONFIG_MPC8360)
-	qepi83xx_t qepi;	/* QE Ports Interrupts Registers */
-#endif
-	u8 res0[0x200];
-#if defined (CONFIG_MPC8360)
-	u8 DLL_LBDDR[0x100];
-#endif
-	u8 DDL_DDR[0x100];
-	u8 DDL_LBIU[0x100];
-#if defined (CONFIG_MPC8349)
-	u8 res1[0xE00];
-#elif defined (CONFIG_MPC8360)
-	u8 res1[0x200];
-	gpio83xx_t gpio;	/* General purpose I/O module */
-	qesba83xx_t qesba;	/* QE Secondary Bus Access Windows */
-#endif
-	ddr83xx_t ddr;		/* DDR Memory Controller Memory */
-	fsl_i2c_t i2c[2];	/* I2C Controllers */
-	u8 res2[0x1300];
-	duart83xx_t duart[2];	/* DUART */
-#if defined (CONFIG_MPC8349)
-	u8 res3[0x900];
-	lbus83xx_t lbus;	/* Local Bus Controller Registers */
-	u8 res4[0x1000];
-	spi83xx_t spi;		/* Serial Peripheral Interface */
-	u8 res5[0xF00];
-#elif defined (CONFIG_MPC8360)
-	u8 res3[0x900];
-	lbus83xx_t lbus;	/* Local Bus Controller */
-	u8 res4[0x2000];
-#endif
-	dma83xx_t dma;		/* DMA */
-#if defined (CONFIG_MPC8349)
-	pciconf83xx_t pci_conf[2];	/* PCI Software Configuration Registers */
-	ios83xx_t ios;		/* Sequencer */
-	pcictrl83xx_t pci_ctrl[2];	/* PCI Controller Control and Status Registers */
-	u8 res6[0x19900];
-	usb83xx_t usb;
-	tsec83xx_t tsec[2];
-	u8 res7[0xA000];
-	security83xx_t security;
-#elif defined (CONFIG_MPC8360)
-	pciconf83xx_t pci_conf[1];	/* PCI Software Configuration Registers */
-	u8 res_5[128];
-	ios83xx_t ios;		/* Sequencer (IOS) */
-	pcictrl83xx_t pci_ctrl[1];	/* PCI Controller Control and Status Registers */
-	u8 res6[0x4A00];
-	ddr83xx_t ddr_secondary;	/* Secondary DDR Memory Controller Memory Map */
-	u8 res7[0x22000];
-	security83xx_t security;
-	u8 res8[0xC0000];
-	iram83xx_t iram;	/* IRAM */
-	irq83xx_t irq;		/* Interrupt Controller */
-	cp83xx_t cp;		/* Communications Processor */
-	qmx83xx_t qmx;		/* QE Multiplexer */
-	qet83xx_t qet;		/* QE Timers */
-	spi83xx_t spi[0x2];	/* spi	*/
-	mcc83xx_t mcc;		/* mcc */
-	brg83xx_t brg;		/* brg */
-	usb83xx_t usb;		/* USB */
-	si1_83xx_t si1;		/* SI */
-	u8 res9[0x800];
-	sir83xx_t sir;		/* SI Routing Tables  */
-	ucc83xx_t ucc1;		/* ucc1 */
-	ucc83xx_t ucc3;		/* ucc3 */
-	ucc83xx_t ucc5;		/* ucc5 */
-	ucc83xx_t ucc7;		/* ucc7 */
-	u8 res10[0x600];
-	upc83xx_t upc1;		/* MultiPHY UTOPIA POS Controller 1 */
-	ucc83xx_t ucc2;		/* ucc2 */
-	ucc83xx_t ucc4;		/* ucc4 */
-	ucc83xx_t ucc6;		/* ucc6 */
-	ucc83xx_t ucc8;		/* ucc8 */
-	u8 res11[0x600];
-	upc83xx_t upc2;		/* MultiPHY UTOPIA POS Controller 2 */
-	sdma83xx_t sdma;	/* SDMA */
-	dbg83xx_t dbg;		/* Debug Space */
-	rsp83xx_t rsp[0x2];	/* RISC Special Registers (Trap and Breakpoint) */
-	u8 res12[0x300];
-	u8 res13[0x3A00];
-	u8 res14[0x8000];	/* 0x108000 -  0x110000 */
-	u8 res15[0xC000];	/* 0x110000 -  0x11C000 Multi-user RAM */
-	u8 res16[0x24000];	/* 0x11C000 -  0x140000 */
-	u8 res17[0xC0000];	/* 0x140000 -  0x200000 */
-#endif
+	sysconf83xx_t		sysconf;	/* System configuration */
+	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
+	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
+	rtclk83xx_t		pit;		/* Periodic Interval Timer */
+	u8			res0[0x200];
+	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
+	reset83xx_t		reset;		/* Reset Module */
+	clk83xx_t		clk;		/* System Clock Module */
+	pmc83xx_t		pmc;		/* Power Management Control Module */
+	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
+	u8			res1[0x300];
+	u8			dll_ddr[0x100];
+	u8			dll_lbc[0x100];
+	u8			res2[0x200];
+	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
+	qesba83xx_t		qesba;		/* QE Secondary Bus Access Windows */
+	u8			res3[0x400];
+	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
+	fsl_i2c_t		i2c[2];		/* I2C Controllers */
+	u8			res4[0x1300];
+	duart83xx_t		duart[2];	/* DUART */
+	u8			res5[0x900];
+	lbus83xx_t		lbus;		/* Local Bus Controller Registers */
+	u8			res6[0x2000];
+	dma83xx_t		dma;		/* DMA */
+	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
+	u8			res7[128];
+	ios83xx_t		ios;		/* Sequencer (IOS) */
+	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
+	u8			res8[0x4A00];
+	ddr83xx_t		ddr_secondary;	/* Secondary DDR Memory Controller Memory Map */
+	u8			res9[0x22000];
+	security83xx_t		security;
+	u8			res10[0xC0000];
+	u8			qe[0x100000];	/* QE block */
 } immap_t;
+#endif
 
 #endif				/* __IMMAP_83xx__ */
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 03dd0ca..504b6a9 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -10,12 +10,6 @@
  * the License, or (at your option) any later version.
  */
 
-/*
- * mpc83xx.h
- *
- * MPC83xx specific definitions
- */
-
 #ifndef __MPC83XX_H__
 #define __MPC83XX_H__
 
@@ -24,406 +18,941 @@
 #include <asm/e300.h>
 #endif
 
-/*
- * MPC83xx cpu provide RCR register to do reset thing specially. easier
- * to implement
+/* MPC83xx cpu provide RCR register to do reset thing specially
  */
-
 #define MPC83xx_RESET
 
-/*
- * System reset offset (PowerPC standard)
+/* System reset offset (PowerPC standard)
  */
-#define EXC_OFF_SYS_RESET	0x0100
+#define EXC_OFF_SYS_RESET		0x0100
 
-/*
- * Default Internal Memory Register Space (Freescale recomandation)
+/* IMMRBAR - Internal Memory Register Base Address
  */
-#define CONFIG_DEFAULT_IMMR 0xFF400000
+#define CONFIG_DEFAULT_IMMR		0xFF400000	/* Default IMMR base address */
+#define IMMRBAR				0x0000		/* Register offset to immr */
+#define IMMRBAR_BASE_ADDR		0xFFF00000	/* Base address mask */
+#define IMMRBAR_RES			~(IMMRBAR_BASE_ADDR)
 
-/*
- * Watchdog
+/* LAWBAR - Local Access Window Base Address Register
  */
-#define SWCRR      0x0204
-#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
-#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
-#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit. */
-#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
-#define SWCRR_RES  ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
+#define LBLAWBAR0			0x0020		/* Register offset to immr */
+#define LBLAWAR0			0x0024
+#define LBLAWBAR1			0x0028
+#define LBLAWAR1			0x002C
+#define LBLAWBAR2			0x0030
+#define LBLAWAR2			0x0034
+#define LBLAWBAR3			0x0038
+#define LBLAWAR3			0x003C
+#define LAWBAR_BAR			0xFFFFF000	/* Base address mask */
+
+/* SPRIDR - System Part and Revision ID Register
+ */
+#define SPRIDR_PARTID			0xFFFF0000	/* Part Identification */
+#define SPRIDR_REVID			0x0000FFFF	/* Revision Identification */
+
+#define SPR_8349E_REV10			0x80300100
+#define SPR_8349_REV10			0x80310100
+#define SPR_8347E_REV10_TBGA		0x80320100
+#define SPR_8347_REV10_TBGA		0x80330100
+#define SPR_8347E_REV10_PBGA		0x80340100
+#define SPR_8347_REV10_PBGA		0x80350100
+#define SPR_8343E_REV10			0x80360100
+#define SPR_8343_REV10			0x80370100
+
+#define SPR_8349E_REV11			0x80300101
+#define SPR_8349_REV11			0x80310101
+#define SPR_8347E_REV11_TBGA		0x80320101
+#define SPR_8347_REV11_TBGA		0x80330101
+#define SPR_8347E_REV11_PBGA		0x80340101
+#define SPR_8347_REV11_PBGA		0x80350101
+#define SPR_8343E_REV11			0x80360101
+#define SPR_8343_REV11			0x80370101
+
+#define SPR_8360E_REV10			0x80480010
+#define SPR_8360_REV10			0x80490010
+#define SPR_8360E_REV11			0x80480011
+#define SPR_8360_REV11			0x80490011
+#define SPR_8360E_REV12			0x80480012
+#define SPR_8360_REV12			0x80490012
+
+/* SPCR - System Priority Configuration Register
+ */
+#define SPCR_PCIHPE			0x10000000	/* PCI Highest Priority Enable */
+#define SPCR_PCIHPE_SHIFT		(31-3)
+#define SPCR_PCIPR			0x03000000	/* PCI bridge system bus request priority */
+#define SPCR_PCIPR_SHIFT		(31-7)
+#define SPCR_OPT			0x00800000	/* Optimize */
+#define SPCR_TBEN			0x00400000	/* E300 PowerPC core time base unit enable */
+#define SPCR_TBEN_SHIFT			(31-9)
+#define SPCR_COREPR			0x00300000	/* E300 PowerPC Core system bus request priority */
+#define SPCR_COREPR_SHIFT		(31-11)
+
+#if defined(CONFIG_MPC8349)
+/* SPCR bits - MPC8349 specific */
+#define SPCR_TSEC1DP			0x00003000	/* TSEC1 data priority */
+#define SPCR_TSEC1DP_SHIFT		(31-19)
+#define SPCR_TSEC1BDP			0x00000C00	/* TSEC1 buffer descriptor priority */
+#define SPCR_TSEC1BDP_SHIFT		(31-21)
+#define SPCR_TSEC1EP			0x00000300	/* TSEC1 emergency priority */
+#define SPCR_TSEC1EP_SHIFT		(31-23)
+#define SPCR_TSEC2DP			0x00000030	/* TSEC2 data priority */
+#define SPCR_TSEC2DP_SHIFT		(31-27)
+#define SPCR_TSEC2BDP			0x0000000C	/* TSEC2 buffer descriptor priority */
+#define SPCR_TSEC2BDP_SHIFT		(31-29)
+#define SPCR_TSEC2EP			0x00000003	/* TSEC2 emergency priority */
+#define SPCR_TSEC2EP_SHIFT		(31-31)
+#endif
 
-#define SWCNR      0x0208
-#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
-#define SWCNR_RES  ~(SWCNR_SWCN)
+/* SICRL/H - System I/O Configuration Register Low/High
+ */
+#if defined(CONFIG_MPC8349)
+/* SICRL bits - MPC8349 specific */
+#define SICRL_LDP_A			0x80000000
+#define SICRL_USB1			0x40000000
+#define SICRL_USB0			0x20000000
+#define SICRL_UART			0x0C000000
+#define SICRL_GPIO1_A			0x02000000
+#define SICRL_GPIO1_B			0x01000000
+#define SICRL_GPIO1_C			0x00800000
+#define SICRL_GPIO1_D			0x00400000
+#define SICRL_GPIO1_E			0x00200000
+#define SICRL_GPIO1_F			0x00180000
+#define SICRL_GPIO1_G			0x00040000
+#define SICRL_GPIO1_H			0x00020000
+#define SICRL_GPIO1_I			0x00010000
+#define SICRL_GPIO1_J			0x00008000
+#define SICRL_GPIO1_K			0x00004000
+#define SICRL_GPIO1_L			0x00003000
+
+/* SICRH bits - MPC8349 specific */
+#define SICRH_DDR			0x80000000
+#define SICRH_TSEC1_A			0x10000000
+#define SICRH_TSEC1_B			0x08000000
+#define SICRH_TSEC1_C			0x04000000
+#define SICRH_TSEC1_D			0x02000000
+#define SICRH_TSEC1_E			0x01000000
+#define SICRH_TSEC1_F			0x00800000
+#define SICRH_TSEC2_A			0x00400000
+#define SICRH_TSEC2_B			0x00200000
+#define SICRH_TSEC2_C			0x00100000
+#define SICRH_TSEC2_D			0x00080000
+#define SICRH_TSEC2_E			0x00040000
+#define SICRH_TSEC2_F			0x00020000
+#define SICRH_TSEC2_G			0x00010000
+#define SICRH_TSEC2_H			0x00008000
+#define SICRH_GPIO2_A			0x00004000
+#define SICRH_GPIO2_B			0x00002000
+#define SICRH_GPIO2_C			0x00001000
+#define SICRH_GPIO2_D			0x00000800
+#define SICRH_GPIO2_E			0x00000400
+#define SICRH_GPIO2_F			0x00000200
+#define SICRH_GPIO2_G			0x00000180
+#define SICRH_GPIO2_H			0x00000060
+#define SICRH_TSOBI1			0x00000002
+#define SICRH_TSOBI2			0x00000001
+
+#elif defined(CONFIG_MPC8360)
+/* SICRL bits - MPC8360 specific */
+#define SICRL_LDP_A			0xC0000000
+#define SICRL_LCLK_1			0x10000000
+#define SICRL_LCLK_2			0x08000000
+#define SICRL_SRCID_A			0x03000000
+#define SICRL_IRQ_CKSTP_A		0x00C00000
+
+/* SICRH bits - MPC8360 specific */
+#define SICRH_DDR			0x80000000
+#define SICRH_SECONDARY_DDR		0x40000000
+#define SICRH_SDDROE			0x20000000
+#define SICRH_IRQ3			0x10000000
+#define SICRH_UC1EOBI			0x00000004
+#define SICRH_UC2E1OBI			0x00000002
+#define SICRH_UC2E2OBI			0x00000001
+#endif
 
-#define SWSRR      0x020E
+/* SWCRR - System Watchdog Control Register
+ */
+#define SWCRR				0x0204		/* Register offset to immr */
+#define SWCRR_SWTC			0xFFFF0000	/* Software Watchdog Time Count */
+#define SWCRR_SWEN			0x00000004	/* Watchdog Enable bit */
+#define SWCRR_SWRI			0x00000002	/* Software Watchdog Reset/Interrupt Select bit */
+#define SWCRR_SWPR			0x00000001	/* Software Watchdog Counter Prescale bit */
+#define SWCRR_RES			~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
+
+/* SWCNR - System Watchdog Counter Register
+ */
+#define SWCNR				0x0208		/* Register offset to immr */
+#define SWCNR_SWCN			0x0000FFFF	/* Software Watchdog Count mask */
+#define SWCNR_RES			~(SWCNR_SWCN)
 
-/*
- * Default Internal Memory Register Space (Freescale recomandation)
+/* SWSRR - System Watchdog Service Register
  */
-#define IMMRBAR 0x0000
-#define IMMRBAR_BASE_ADDR     0xFFF00000 /* Identifies the 12 most-significant address bits of the base of the 1 MByte internal memory window. */
-#define IMMRBAR_RES           ~(IMMRBAR_BASE_ADDR)
+#define SWSRR				0x020E		/* Register offset to immr */
 
-/*
- * Default Internal Memory Register Space (Freescale recomandation)
+/* ACR - Arbiter Configuration Register
  */
-#define LBLAWBAR0 0x0020
-#define LBLAWAR0  0x0024
-#define LBLAWBAR1 0x0028
-#define LBLAWAR1  0x002C
-#define LBLAWBAR2 0x0030
-#define LBLAWAR2  0x0034
-#define LBLAWBAR3 0x0038
-#define LBLAWAR3  0x003C
+#define ACR_COREDIS			0x10000000	/* Core disable */
+#define ACR_COREDIS_SHIFT		(31-7)
+#define ACR_PIPE_DEP			0x00070000	/* Pipeline depth */
+#define ACR_PIPE_DEP_SHIFT		(31-15)
+#define ACR_PCI_RPTCNT			0x00007000	/* PCI repeat count */
+#define ACR_PCI_RPTCNT_SHIFT		(31-19)
+#define ACR_RPTCNT			0x00000700	/* Repeat count */
+#define ACR_RPTCNT_SHIFT		(31-23)
+#define ACR_APARK			0x00000030	/* Address parking */
+#define ACR_APARK_SHIFT			(31-27)
+#define ACR_PARKM			0x0000000F	/* Parking master */
+#define ACR_PARKM_SHIFT			(31-31)
+
+/* ATR - Arbiter Timers Register
+ */
+#define ATR_DTO				0x00FF0000	/* Data time out */
+#define ATR_ATO				0x000000FF	/* Address time out */
 
-/*
- * The device ID and revision numbers
- */
-#define SPR_8349E_REV10		0x80300100
-#define SPR_8349_REV10		0x80310100
-#define SPR_8347E_REV10_TBGA	0x80320100
-#define SPR_8347_REV10_TBGA	0x80330100
-#define SPR_8347E_REV10_PBGA	0x80340100
-#define SPR_8347_REV10_PBGA	0x80350100
-#define SPR_8343E_REV10		0x80360100
-#define SPR_8343_REV10		0x80370100
-
-#define SPR_8349E_REV11		0x80300101
-#define SPR_8349_REV11		0x80310101
-#define SPR_8347E_REV11_TBGA	0x80320101
-#define SPR_8347_REV11_TBGA	0x80330101
-#define SPR_8347E_REV11_PBGA	0x80340101
-#define SPR_8347_REV11_PBGA	0x80350101
-#define SPR_8343E_REV11		0x80360101
-#define SPR_8343_REV11		0x80370101
-
-#define SPR_8360E_REV10		0x80480010
-#define SPR_8360_REV10		0x80490010
-#define SPR_8360E_REV11		0x80480011
-#define SPR_8360_REV11		0x80490011
-#define SPR_8360E_REV12		0x80480012
-#define SPR_8360_REV12		0x80490012
+/* AER - Arbiter Event Register
+ */
+#define AER_ETEA			0x00000020	/* Transfer error */
+#define AER_RES				0x00000010	/* Reserved transfer type */
+#define AER_ECW				0x00000008	/* External control word transfer type */
+#define AER_AO				0x00000004	/* Address Only transfer type */
+#define AER_DTO				0x00000002	/* Data time out */
+#define AER_ATO				0x00000001	/* Address time out */
+
+/* AEATR - Arbiter Event Address Register
+ */
+#define AEATR_EVENT			0x07000000	/* Event type */
+#define AEATR_MSTR_ID			0x001F0000	/* Master Id */
+#define AEATR_TBST			0x00000800	/* Transfer burst */
+#define AEATR_TSIZE			0x00000700	/* Transfer Size */
+#define AEATR_TTYPE			0x0000001F	/* Transfer Type */
 
-/*
- * Base Registers & Option Registers
- */
-#define BR0 0x5000
-#define BR1 0x5008
-#define BR2 0x5010
-#define BR3 0x5018
-#define BR4 0x5020
-#define BR5 0x5028
-#define BR6 0x5030
-#define BR7 0x5038
-
-#define BR_BA		0xFFFF8000
-#define BR_BA_SHIFT		15
-#define BR_PS		0x00001800
-#define BR_PS_SHIFT		11
-#define BR_PS_8		0x00000800  /* Port Size 8 bit */
-#define BR_PS_16	0x00001000  /* Port Size 16 bit */
-#define BR_PS_32	0x00001800  /* Port Size 32 bit */
-#define BR_DECC		0x00000600
-#define BR_DECC_SHIFT		 9
-#define BR_WP		0x00000100
-#define BR_WP_SHIFT		 8
-#define BR_MSEL		0x000000E0
-#define BR_MSEL_SHIFT		 5
-#define BR_MS_GPCM	0x00000000  /* GPCM */
-#define BR_MS_SDRAM	0x00000060  /* SDRAM */
-#define BR_MS_UPMA	0x00000080  /* UPMA */
-#define BR_MS_UPMB	0x000000A0  /* UPMB */
-#define BR_MS_UPMC	0x000000C0  /* UPMC */
-#if defined (CONFIG_MPC8360)
-#define BR_ATOM		0x0000000C
-#define BR_ATOM_SHIFT		2
-#endif
-#define BR_V		0x00000001
-#define BR_V_SHIFT		 0
-#if defined (CONFIG_MPC8349)
-#define BR_RES		~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
-#elif defined (CONFIG_MPC8360)
-#define BR_RES		~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_ATOM|BR_V)
+/* HRCWL - Hard Reset Configuration Word Low
+ */
+#define HRCWL_LBIUCM			0x80000000
+#define HRCWL_LBIUCM_SHIFT		31
+#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1	0x00000000
+#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1	0x80000000
+
+#define HRCWL_DDRCM			0x40000000
+#define HRCWL_DDRCM_SHIFT		30
+#define HRCWL_DDR_TO_SCB_CLK_1X1	0x00000000
+#define HRCWL_DDR_TO_SCB_CLK_2X1	0x40000000
+
+#define HRCWL_SPMF			0x0f000000
+#define HRCWL_SPMF_SHIFT		24
+#define HRCWL_CSB_TO_CLKIN_16X1		0x00000000
+#define HRCWL_CSB_TO_CLKIN_1X1		0x01000000
+#define HRCWL_CSB_TO_CLKIN_2X1		0x02000000
+#define HRCWL_CSB_TO_CLKIN_3X1		0x03000000
+#define HRCWL_CSB_TO_CLKIN_4X1		0x04000000
+#define HRCWL_CSB_TO_CLKIN_5X1		0x05000000
+#define HRCWL_CSB_TO_CLKIN_6X1		0x06000000
+#define HRCWL_CSB_TO_CLKIN_7X1		0x07000000
+#define HRCWL_CSB_TO_CLKIN_8X1		0x08000000
+#define HRCWL_CSB_TO_CLKIN_9X1		0x09000000
+#define HRCWL_CSB_TO_CLKIN_10X1		0x0A000000
+#define HRCWL_CSB_TO_CLKIN_11X1		0x0B000000
+#define HRCWL_CSB_TO_CLKIN_12X1		0x0C000000
+#define HRCWL_CSB_TO_CLKIN_13X1		0x0D000000
+#define HRCWL_CSB_TO_CLKIN_14X1		0x0E000000
+#define HRCWL_CSB_TO_CLKIN_15X1		0x0F000000
+
+#define HRCWL_VCO_BYPASS		0x00000000
+#define HRCWL_VCO_1X2			0x00000000
+#define HRCWL_VCO_1X4			0x00200000
+#define HRCWL_VCO_1X8			0x00400000
+
+#define HRCWL_COREPLL			0x007F0000
+#define HRCWL_COREPLL_SHIFT		16
+#define HRCWL_CORE_TO_CSB_BYPASS	0x00000000
+#define HRCWL_CORE_TO_CSB_1X1		0x00020000
+#define HRCWL_CORE_TO_CSB_1_5X1		0x00030000
+#define HRCWL_CORE_TO_CSB_2X1		0x00040000
+#define HRCWL_CORE_TO_CSB_2_5X1		0x00050000
+#define HRCWL_CORE_TO_CSB_3X1		0x00060000
+
+#if defined(CONFIG_MPC8360)
+#define HRCWL_CEVCOD			0x000000C0
+#define HRCWL_CEVCOD_SHIFT		6
+#define HRCWL_CE_PLL_VCO_DIV_4		0x00000000
+#define HRCWL_CE_PLL_VCO_DIV_8		0x00000040
+#define HRCWL_CE_PLL_VCO_DIV_2		0x00000080
+
+#define HRCWL_CEPDF			0x00000020
+#define HRCWL_CEPDF_SHIFT		5
+#define HRCWL_CE_PLL_DIV_1X1		0x00000000
+#define HRCWL_CE_PLL_DIV_2X1		0x00000020
+
+#define HRCWL_CEPMF			0x0000001F
+#define HRCWL_CEPMF_SHIFT		0
+#define HRCWL_CE_TO_PLL_1X16_		0x00000000
+#define HRCWL_CE_TO_PLL_1X2		0x00000002
+#define HRCWL_CE_TO_PLL_1X3		0x00000003
+#define HRCWL_CE_TO_PLL_1X4		0x00000004
+#define HRCWL_CE_TO_PLL_1X5		0x00000005
+#define HRCWL_CE_TO_PLL_1X6		0x00000006
+#define HRCWL_CE_TO_PLL_1X7		0x00000007
+#define HRCWL_CE_TO_PLL_1X8		0x00000008
+#define HRCWL_CE_TO_PLL_1X9		0x00000009
+#define HRCWL_CE_TO_PLL_1X10		0x0000000A
+#define HRCWL_CE_TO_PLL_1X11		0x0000000B
+#define HRCWL_CE_TO_PLL_1X12		0x0000000C
+#define HRCWL_CE_TO_PLL_1X13		0x0000000D
+#define HRCWL_CE_TO_PLL_1X14		0x0000000E
+#define HRCWL_CE_TO_PLL_1X15		0x0000000F
+#define HRCWL_CE_TO_PLL_1X16		0x00000010
+#define HRCWL_CE_TO_PLL_1X17		0x00000011
+#define HRCWL_CE_TO_PLL_1X18		0x00000012
+#define HRCWL_CE_TO_PLL_1X19		0x00000013
+#define HRCWL_CE_TO_PLL_1X20		0x00000014
+#define HRCWL_CE_TO_PLL_1X21		0x00000015
+#define HRCWL_CE_TO_PLL_1X22		0x00000016
+#define HRCWL_CE_TO_PLL_1X23		0x00000017
+#define HRCWL_CE_TO_PLL_1X24		0x00000018
+#define HRCWL_CE_TO_PLL_1X25		0x00000019
+#define HRCWL_CE_TO_PLL_1X26		0x0000001A
+#define HRCWL_CE_TO_PLL_1X27		0x0000001B
+#define HRCWL_CE_TO_PLL_1X28		0x0000001C
+#define HRCWL_CE_TO_PLL_1X29		0x0000001D
+#define HRCWL_CE_TO_PLL_1X30		0x0000001E
+#define HRCWL_CE_TO_PLL_1X31		0x0000001F
 #endif
 
-#define OR0 0x5004
-#define OR1 0x500C
-#define OR2 0x5014
-#define OR3 0x501C
-#define OR4 0x5024
-#define OR5 0x502C
-#define OR6 0x5034
-#define OR7 0x503C
-
-#define OR_GPCM_AM		0xFFFF8000
-#define OR_GPCM_AM_SHIFT		15
-#define OR_GPCM_BCTLD		0x00001000
-#define OR_GPCM_BCTLD_SHIFT		12
-#define OR_GPCM_CSNT		0x00000800
-#define OR_GPCM_CSNT_SHIFT		11
-#define OR_GPCM_ACS		0x00000600
-#define OR_GPCM_ACS_SHIFT		 9
-#define OR_GPCM_ACS_0b10	0x00000400
-#define OR_GPCM_ACS_0b11	0x00000600
-#define OR_GPCM_XACS		0x00000100
-#define OR_GPCM_XACS_SHIFT		 8
-#define OR_GPCM_SCY		0x000000F0
-#define OR_GPCM_SCY_SHIFT		 4
-#define OR_GPCM_SCY_1		0x00000010
-#define OR_GPCM_SCY_2		0x00000020
-#define OR_GPCM_SCY_3		0x00000030
-#define OR_GPCM_SCY_4		0x00000040
-#define OR_GPCM_SCY_5		0x00000050
-#define OR_GPCM_SCY_6		0x00000060
-#define OR_GPCM_SCY_7		0x00000070
-#define OR_GPCM_SCY_8		0x00000080
-#define OR_GPCM_SCY_9		0x00000090
-#define OR_GPCM_SCY_10		0x000000a0
-#define OR_GPCM_SCY_11		0x000000b0
-#define OR_GPCM_SCY_12		0x000000c0
-#define OR_GPCM_SCY_13		0x000000d0
-#define OR_GPCM_SCY_14		0x000000e0
-#define OR_GPCM_SCY_15		0x000000f0
-#define OR_GPCM_SETA		0x00000008
-#define OR_GPCM_SETA_SHIFT		 3
-#define OR_GPCM_TRLX		0x00000004
-#define OR_GPCM_TRLX_SHIFT		 2
-#define OR_GPCM_EHTR		0x00000002
-#define OR_GPCM_EHTR_SHIFT		 1
-#define OR_GPCM_EAD		0x00000001
-#define OR_GPCM_EAD_SHIFT		 0
-
-#define OR_UPM_AM    0xFFFF8000
-#define OR_UPM_AM_SHIFT      15
-#define OR_UPM_XAM   0x00006000
-#define OR_UPM_XAM_SHIFT     13
-#define OR_UPM_BCTLD 0x00001000
-#define OR_UPM_BCTLD_SHIFT   12
-#define OR_UPM_BI    0x00000100
-#define OR_UPM_BI_SHIFT       8
-#define OR_UPM_TRLX  0x00000004
-#define OR_UPM_TRLX_SHIFT     2
-#define OR_UPM_EHTR  0x00000002
-#define OR_UPM_EHTR_SHIFT     1
-#define OR_UPM_EAD   0x00000001
-#define OR_UPM_EAD_SHIFT      0
-
-#define OR_SDRAM_AM    0xFFFF8000
-#define OR_SDRAM_AM_SHIFT      15
-#define OR_SDRAM_XAM   0x00006000
-#define OR_SDRAM_XAM_SHIFT     13
-#define OR_SDRAM_COLS  0x00001C00
-#define OR_SDRAM_COLS_SHIFT    10
-#define OR_SDRAM_ROWS  0x000001C0
-#define OR_SDRAM_ROWS_SHIFT     6
-#define OR_SDRAM_PMSEL 0x00000020
-#define OR_SDRAM_PMSEL_SHIFT    5
-#define OR_SDRAM_EAD   0x00000001
-#define OR_SDRAM_EAD_SHIFT      0
-
-/*
- * Hard Reset Configration Word - High
+/* HRCWH - Hardware Reset Configuration Word High
  */
-#define HRCWH_PCI_AGENT              0x00000000
-#define HRCWH_PCI_HOST               0x80000000
+#define HRCWH_PCI_HOST			0x80000000
+#define HRCWH_PCI_HOST_SHIFT		31
+#define HRCWH_PCI_AGENT			0x00000000
 
-#if defined (CONFIG_MPC8349)
-#define HRCWH_32_BIT_PCI             0x00000000
-#define HRCWH_64_BIT_PCI             0x40000000
+#if defined(CONFIG_MPC8349)
+#define HRCWH_32_BIT_PCI		0x00000000
+#define HRCWH_64_BIT_PCI		0x40000000
 #endif
 
-#define HRCWH_PCI1_ARBITER_DISABLE   0x00000000
-#define HRCWH_PCI1_ARBITER_ENABLE    0x20000000
+#define HRCWH_PCI1_ARBITER_DISABLE	0x00000000
+#define HRCWH_PCI1_ARBITER_ENABLE	0x20000000
+
+#define HRCWH_PCI_ARBITER_DISABLE	0x00000000
+#define HRCWH_PCI_ARBITER_ENABLE	0x20000000
 
-#if defined (CONFIG_MPC8349)
-#define HRCWH_PCI2_ARBITER_DISABLE   0x00000000
-#define HRCWH_PCI2_ARBITER_ENABLE    0x10000000
-#elif defined (CONFIG_MPC8360)
-#define HRCWH_PCICKDRV_DISABLE       0x00000000
-#define HRCWH_PCICKDRV_ENABLE        0x10000000
+#if defined(CONFIG_MPC8349)
+#define HRCWH_PCI2_ARBITER_DISABLE	0x00000000
+#define HRCWH_PCI2_ARBITER_ENABLE	0x10000000
+
+#elif defined(CONFIG_MPC8360)
+#define HRCWH_PCICKDRV_DISABLE		0x00000000
+#define HRCWH_PCICKDRV_ENABLE		0x10000000
 #endif
 
-#define HRCWH_CORE_DISABLE           0x08000000
-#define HRCWH_CORE_ENABLE            0x00000000
+#define HRCWH_CORE_DISABLE		0x08000000
+#define HRCWH_CORE_ENABLE		0x00000000
 
-#define HRCWH_FROM_0X00000100        0x00000000
-#define HRCWH_FROM_0XFFF00100        0x04000000
+#define HRCWH_FROM_0X00000100		0x00000000
+#define HRCWH_FROM_0XFFF00100		0x04000000
 
-#define HRCWH_BOOTSEQ_DISABLE        0x00000000
-#define HRCWH_BOOTSEQ_NORMAL         0x01000000
-#define HRCWH_BOOTSEQ_EXTENDED       0x02000000
+#define HRCWH_BOOTSEQ_DISABLE		0x00000000
+#define HRCWH_BOOTSEQ_NORMAL		0x01000000
+#define HRCWH_BOOTSEQ_EXTENDED		0x02000000
 
-#define HRCWH_SW_WATCHDOG_DISABLE    0x00000000
-#define HRCWH_SW_WATCHDOG_ENABLE     0x00800000
+#define HRCWH_SW_WATCHDOG_DISABLE	0x00000000
+#define HRCWH_SW_WATCHDOG_ENABLE	0x00800000
 
-#define HRCWH_ROM_LOC_DDR_SDRAM      0x00000000
-#define HRCWH_ROM_LOC_PCI1           0x00100000
-#if defined (CONFIG_MPC8349)
-#define HRCWH_ROM_LOC_PCI2           0x00200000
+#define HRCWH_ROM_LOC_DDR_SDRAM		0x00000000
+#define HRCWH_ROM_LOC_PCI1		0x00100000
+#if defined(CONFIG_MPC8349)
+#define HRCWH_ROM_LOC_PCI2		0x00200000
 #endif
-#define HRCWH_ROM_LOC_LOCAL_8BIT     0x00500000
-#define HRCWH_ROM_LOC_LOCAL_16BIT    0x00600000
-#define HRCWH_ROM_LOC_LOCAL_32BIT    0x00700000
-
-#if defined (CONFIG_MPC8349)
-#define HRCWH_TSEC1M_IN_RGMII        0x00000000
-#define HRCWH_TSEC1M_IN_RTBI         0x00004000
-#define HRCWH_TSEC1M_IN_GMII         0x00008000
-#define HRCWH_TSEC1M_IN_TBI          0x0000C000
-
-#define HRCWH_TSEC2M_IN_RGMII        0x00000000
-#define HRCWH_TSEC2M_IN_RTBI         0x00001000
-#define HRCWH_TSEC2M_IN_GMII         0x00002000
-#define HRCWH_TSEC2M_IN_TBI          0x00003000
+#define HRCWH_ROM_LOC_LOCAL_8BIT	0x00500000
+#define HRCWH_ROM_LOC_LOCAL_16BIT	0x00600000
+#define HRCWH_ROM_LOC_LOCAL_32BIT	0x00700000
+
+#if defined(CONFIG_MPC8349)
+#define HRCWH_TSEC1M_IN_RGMII		0x00000000
+#define HRCWH_TSEC1M_IN_RTBI		0x00004000
+#define HRCWH_TSEC1M_IN_GMII		0x00008000
+#define HRCWH_TSEC1M_IN_TBI		0x0000C000
+#define HRCWH_TSEC2M_IN_RGMII		0x00000000
+#define HRCWH_TSEC2M_IN_RTBI		0x00001000
+#define HRCWH_TSEC2M_IN_GMII		0x00002000
+#define HRCWH_TSEC2M_IN_TBI		0x00003000
 #endif
 
-#if defined (CONFIG_MPC8360)
-#define HRCWH_SECONDARY_DDR_DISABLE  0x00000000
-#define HRCWH_SECONDARY_DDR_ENABLE   0x00000010
+#if defined(CONFIG_MPC8360)
+#define HRCWH_SECONDARY_DDR_DISABLE	0x00000000
+#define HRCWH_SECONDARY_DDR_ENABLE	0x00000010
 #endif
 
-#define HRCWH_BIG_ENDIAN             0x00000000
-#define HRCWH_LITTLE_ENDIAN          0x00000008
+#define HRCWH_BIG_ENDIAN		0x00000000
+#define HRCWH_LITTLE_ENDIAN		0x00000008
 
-#define HRCWH_LALE_NORMAL            0x00000000
-#define HRCWH_LALE_EARLY             0x00000004
+#define HRCWH_LALE_NORMAL		0x00000000
+#define HRCWH_LALE_EARLY		0x00000004
 
-#define HRCWH_LDP_SET                0x00000000
-#define HRCWH_LDP_CLEAR              0x00000002
+#define HRCWH_LDP_SET			0x00000000
+#define HRCWH_LDP_CLEAR			0x00000002
 
-/*
- * Hard Reset Configration Word - Low
- */
-#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000
-#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000
-
-#define HRCWL_DDR_TO_SCB_CLK_1X1     0x00000000
-#define HRCWL_DDR_TO_SCB_CLK_2X1     0x40000000
-
-#define HRCWL_CSB_TO_CLKIN_16X1      0x00000000
-#define HRCWL_CSB_TO_CLKIN_1X1       0x01000000
-#define HRCWL_CSB_TO_CLKIN_2X1       0x02000000
-#define HRCWL_CSB_TO_CLKIN_3X1       0x03000000
-#define HRCWL_CSB_TO_CLKIN_4X1       0x04000000
-#define HRCWL_CSB_TO_CLKIN_5X1       0x05000000
-#define HRCWL_CSB_TO_CLKIN_6X1       0x06000000
-#define HRCWL_CSB_TO_CLKIN_7X1       0x07000000
-#define HRCWL_CSB_TO_CLKIN_8X1       0x08000000
-#define HRCWL_CSB_TO_CLKIN_9X1       0x09000000
-#define HRCWL_CSB_TO_CLKIN_10X1      0x0A000000
-#define HRCWL_CSB_TO_CLKIN_11X1      0x0B000000
-#define HRCWL_CSB_TO_CLKIN_12X1      0x0C000000
-#define HRCWL_CSB_TO_CLKIN_13X1      0x0D000000
-#define HRCWL_CSB_TO_CLKIN_14X1      0x0E000000
-#define HRCWL_CSB_TO_CLKIN_15X1      0x0F000000
-
-#define HRCWL_VCO_BYPASS             0x00000000
-#define HRCWL_VCO_1X2                0x00000000
-#define HRCWL_VCO_1X4                0x00200000
-#define HRCWL_VCO_1X8                0x00400000
-
-#define HRCWL_CORE_TO_CSB_BYPASS     0x00000000
-#define HRCWL_CORE_TO_CSB_1X1        0x00020000
-#define HRCWL_CORE_TO_CSB_1_5X1      0x00030000
-#define HRCWL_CORE_TO_CSB_2X1        0x00040000
-#define HRCWL_CORE_TO_CSB_2_5X1      0x00050000
-#define HRCWL_CORE_TO_CSB_3X1        0x00060000
-
-#if defined (CONFIG_MPC8360)
-#define HRCWL_CE_PLL_VCO_DIV_4       0x00000000
-#define HRCWL_CE_PLL_VCO_DIV_8       0x00000040
-#define HRCWL_CE_PLL_VCO_DIV_2       0x00000080
-
-#define HRCWL_CE_PLL_DIV_1X1         0x00000000
-#define HRCWL_CE_PLL_DIV_2X1         0x00000020
-
-#define HRCWL_CE_TO_PLL_1X16_        0x00000000
-#define HRCWL_CE_TO_PLL_1X2          0x00000002
-#define HRCWL_CE_TO_PLL_1X3          0x00000003
-#define HRCWL_CE_TO_PLL_1X4          0x00000004
-#define HRCWL_CE_TO_PLL_1X5          0x00000005
-#define HRCWL_CE_TO_PLL_1X6          0x00000006
-#define HRCWL_CE_TO_PLL_1X7          0x00000007
-#define HRCWL_CE_TO_PLL_1X8          0x00000008
-#define HRCWL_CE_TO_PLL_1X9          0x00000009
-#define HRCWL_CE_TO_PLL_1X10         0x0000000A
-#define HRCWL_CE_TO_PLL_1X11         0x0000000B
-#define HRCWL_CE_TO_PLL_1X12         0x0000000C
-#define HRCWL_CE_TO_PLL_1X13         0x0000000D
-#define HRCWL_CE_TO_PLL_1X14         0x0000000E
-#define HRCWL_CE_TO_PLL_1X15         0x0000000F
-#define HRCWL_CE_TO_PLL_1X16         0x00000010
-#define HRCWL_CE_TO_PLL_1X17         0x00000011
-#define HRCWL_CE_TO_PLL_1X18         0x00000012
-#define HRCWL_CE_TO_PLL_1X19         0x00000013
-#define HRCWL_CE_TO_PLL_1X20         0x00000014
-#define HRCWL_CE_TO_PLL_1X21         0x00000015
-#define HRCWL_CE_TO_PLL_1X22         0x00000016
-#define HRCWL_CE_TO_PLL_1X23         0x00000017
-#define HRCWL_CE_TO_PLL_1X24         0x00000018
-#define HRCWL_CE_TO_PLL_1X25         0x00000019
-#define HRCWL_CE_TO_PLL_1X26         0x0000001A
-#define HRCWL_CE_TO_PLL_1X27         0x0000001B
-#define HRCWL_CE_TO_PLL_1X28         0x0000001C
-#define HRCWL_CE_TO_PLL_1X29         0x0000001D
-#define HRCWL_CE_TO_PLL_1X30         0x0000001E
-#define HRCWL_CE_TO_PLL_1X31         0x0000001F
+/* RSR - Reset Status Register
+ */
+#define RSR_RSTSRC			0xE0000000	/* Reset source */
+#define RSR_RSTSRC_SHIFT		29
+#define RSR_BSF				0x00010000	/* Boot seq. fail */
+#define RSR_BSF_SHIFT			16
+#define RSR_SWSR			0x00002000	/* software soft reset */
+#define RSR_SWSR_SHIFT			13
+#define RSR_SWHR			0x00001000	/* software hard reset */
+#define RSR_SWHR_SHIFT			12
+#define RSR_JHRS			0x00000200	/* jtag hreset */
+#define RSR_JHRS_SHIFT			9
+#define RSR_JSRS			0x00000100	/* jtag sreset status */
+#define RSR_JSRS_SHIFT			8
+#define RSR_CSHR			0x00000010	/* checkstop reset status */
+#define RSR_CSHR_SHIFT			4
+#define RSR_SWRS			0x00000008	/* software watchdog reset status */
+#define RSR_SWRS_SHIFT			3
+#define RSR_BMRS			0x00000004	/* bus monitop reset status */
+#define RSR_BMRS_SHIFT			2
+#define RSR_SRS				0x00000002	/* soft reset status */
+#define RSR_SRS_SHIFT			1
+#define RSR_HRS				0x00000001	/* hard reset status */
+#define RSR_HRS_SHIFT			0
+#define RSR_RES				~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\
+					 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
+					 RSR_BMRS | RSR_SRS | RSR_HRS)
+/* RMR - Reset Mode Register
+ */
+#define RMR_CSRE			0x00000001	/* checkstop reset enable */
+#define RMR_CSRE_SHIFT			0
+#define RMR_RES				~(RMR_CSRE)
+
+/* RCR - Reset Control Register
+ */
+#define RCR_SWHR			0x00000002	/* software hard reset */
+#define RCR_SWSR			0x00000001	/* software soft reset */
+#define RCR_RES				~(RCR_SWHR | RCR_SWSR)
+
+/* RCER - Reset Control Enable Register
+ */
+#define RCER_CRE			0x00000001	/* software hard reset */
+#define RCER_RES			~(RCER_CRE)
+
+/* SPMR - System PLL Mode Register
+ */
+#define SPMR_LBIUCM			0x80000000
+#define SPMR_DDRCM			0x40000000
+#define SPMR_SPMF			0x0F000000
+#define SPMR_CKID			0x00800000
+#define SPMR_CKID_SHIFT			23
+#define SPMR_COREPLL			0x007F0000
+#define SPMR_CEVCOD			0x000000C0
+#define SPMR_CEPDF			0x00000020
+#define SPMR_CEPMF			0x0000001F
+
+/* OCCR - Output Clock Control Register
+ */
+#define OCCR_PCICOE0			0x80000000
+#define OCCR_PCICOE1			0x40000000
+#define OCCR_PCICOE2			0x20000000
+#define OCCR_PCICOE3			0x10000000
+#define OCCR_PCICOE4			0x08000000
+#define OCCR_PCICOE5			0x04000000
+#define OCCR_PCICOE6			0x02000000
+#define OCCR_PCICOE7			0x01000000
+#define OCCR_PCICD0			0x00800000
+#define OCCR_PCICD1			0x00400000
+#define OCCR_PCICD2			0x00200000
+#define OCCR_PCICD3			0x00100000
+#define OCCR_PCICD4			0x00080000
+#define OCCR_PCICD5			0x00040000
+#define OCCR_PCICD6			0x00020000
+#define OCCR_PCICD7			0x00010000
+#define OCCR_PCI1CR			0x00000002
+#define OCCR_PCI2CR			0x00000001
+#define OCCR_PCICR			OCCR_PCI1CR
+
+/* SCCR - System Clock Control Register
+ */
+#define SCCR_ENCCM			0x03000000
+#define SCCR_ENCCM_SHIFT		24
+#define SCCR_ENCCM_0			0x00000000
+#define SCCR_ENCCM_1			0x01000000
+#define SCCR_ENCCM_2			0x02000000
+#define SCCR_ENCCM_3			0x03000000
+
+#define SCCR_PCICM			0x00010000
+#define SCCR_PCICM_SHIFT		16
+
+/* SCCR bits - MPC8349 specific */
+#define SCCR_TSEC1CM			0xc0000000
+#define SCCR_TSEC1CM_SHIFT		30
+#define SCCR_TSEC1CM_0			0x00000000
+#define SCCR_TSEC1CM_1			0x40000000
+#define SCCR_TSEC1CM_2			0x80000000
+#define SCCR_TSEC1CM_3			0xC0000000
+
+#define SCCR_TSEC2CM			0x30000000
+#define SCCR_TSEC2CM_SHIFT		28
+#define SCCR_TSEC2CM_0			0x00000000
+#define SCCR_TSEC2CM_1			0x10000000
+#define SCCR_TSEC2CM_2			0x20000000
+#define SCCR_TSEC2CM_3			0x30000000
+
+#define SCCR_USBMPHCM			0x00c00000
+#define SCCR_USBMPHCM_SHIFT		22
+#define SCCR_USBDRCM			0x00300000
+#define SCCR_USBDRCM_SHIFT		20
+
+#define SCCR_USBCM_0			0x00000000
+#define SCCR_USBCM_1			0x00500000
+#define SCCR_USBCM_2			0x00A00000
+#define SCCR_USBCM_3			0x00F00000
+
+#define SCCR_CLK_MASK			( SCCR_TSEC1CM_3	\
+					| SCCR_TSEC2CM_3	\
+					| SCCR_ENCCM_3		\
+					| SCCR_USBCM_3		)
+
+#define SCCR_DEFAULT			0xFFFFFFFF
+
+/* CSn_BDNS - Chip Select memory Bounds Register
+ */
+#define CSBNDS_SA			0x00FF0000
+#define CSBNDS_SA_SHIFT			8
+#define CSBNDS_EA			0x000000FF
+#define CSBNDS_EA_SHIFT			24
+
+/* CSn_CONFIG - Chip Select Configuration Register
+ */
+#define CSCONFIG_EN			0x80000000
+#define CSCONFIG_AP			0x00800000
+#define CSCONFIG_ROW_BIT		0x00000700
+#define CSCONFIG_ROW_BIT_12		0x00000000
+#define CSCONFIG_ROW_BIT_13		0x00000100
+#define CSCONFIG_ROW_BIT_14		0x00000200
+#define CSCONFIG_COL_BIT		0x00000007
+#define CSCONFIG_COL_BIT_8		0x00000000
+#define CSCONFIG_COL_BIT_9		0x00000001
+#define CSCONFIG_COL_BIT_10		0x00000002
+#define CSCONFIG_COL_BIT_11		0x00000003
+
+/* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
+ */
+#define TIMING_CFG1_PRETOACT		0x70000000
+#define TIMING_CFG1_PRETOACT_SHIFT	28
+#define TIMING_CFG1_ACTTOPRE		0x0F000000
+#define TIMING_CFG1_ACTTOPRE_SHIFT	24
+#define TIMING_CFG1_ACTTORW		0x00700000
+#define TIMING_CFG1_ACTTORW_SHIFT	20
+#define TIMING_CFG1_CASLAT		0x00070000
+#define TIMING_CFG1_CASLAT_SHIFT	16
+#define TIMING_CFG1_REFREC		0x0000F000
+#define TIMING_CFG1_REFREC_SHIFT	12
+#define TIMING_CFG1_WRREC		0x00000700
+#define TIMING_CFG1_WRREC_SHIFT		8
+#define TIMING_CFG1_ACTTOACT		0x00000070
+#define TIMING_CFG1_ACTTOACT_SHIFT	4
+#define TIMING_CFG1_WRTORD		0x00000007
+#define TIMING_CFG1_WRTORD_SHIFT	0
+#define TIMING_CFG1_CASLAT_20		0x00030000	/* CAS latency = 2.0 */
+#define TIMING_CFG1_CASLAT_25		0x00040000	/* CAS latency = 2.5 */
+
+/* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
+ */
+#define TIMING_CFG2_CPO			0x0F000000
+#define TIMING_CFG2_CPO_SHIFT		24
+#define TIMING_CFG2_ACSM		0x00080000
+#define TIMING_CFG2_WR_DATA_DELAY	0x00001C00
+#define TIMING_CFG2_WR_DATA_DELAY_SHIFT	10
+#define TIMING_CFG2_CPO_DEF		0x00000000	/* default (= CASLAT + 1) */
+
+/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
+ */
+#define SDRAM_CFG_MEM_EN		0x80000000
+#define SDRAM_CFG_SREN			0x40000000
+#define SDRAM_CFG_ECC_EN		0x20000000
+#define SDRAM_CFG_RD_EN			0x10000000
+#define SDRAM_CFG_SDRAM_TYPE		0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
+#define SDRAM_CFG_DYN_PWR		0x00200000
+#define SDRAM_CFG_32_BE			0x00080000
+#define SDRAM_CFG_8_BE			0x00040000
+#define SDRAM_CFG_NCAP			0x00020000
+#define SDRAM_CFG_2T_EN			0x00008000
+#define SDRAM_CFG_SDRAM_TYPE_DDR	0x02000000
+
+/* DDR_SDRAM_MODE - DDR SDRAM Mode Register
+ */
+#define SDRAM_MODE_ESD			0xFFFF0000
+#define SDRAM_MODE_ESD_SHIFT		16
+#define SDRAM_MODE_SD			0x0000FFFF
+#define SDRAM_MODE_SD_SHIFT		0
+#define DDR_MODE_EXT_MODEREG		0x4000		/* select extended mode reg */
+#define DDR_MODE_EXT_OPMODE		0x3FF8		/* operating mode, mask */
+#define DDR_MODE_EXT_OP_NORMAL		0x0000		/* normal operation */
+#define DDR_MODE_QFC			0x0004		/* QFC / compatibility, mask */
+#define DDR_MODE_QFC_COMP		0x0000		/* compatible to older SDRAMs */
+#define DDR_MODE_WEAK			0x0002		/* weak drivers */
+#define DDR_MODE_DLL_DIS		0x0001		/* disable DLL */
+#define DDR_MODE_CASLAT			0x0070		/* CAS latency, mask */
+#define DDR_MODE_CASLAT_15		0x0010		/* CAS latency 1.5 */
+#define DDR_MODE_CASLAT_20		0x0020		/* CAS latency 2 */
+#define DDR_MODE_CASLAT_25		0x0060		/* CAS latency 2.5 */
+#define DDR_MODE_CASLAT_30		0x0030		/* CAS latency 3 */
+#define DDR_MODE_BTYPE_SEQ		0x0000		/* sequential burst */
+#define DDR_MODE_BTYPE_ILVD		0x0008		/* interleaved burst */
+#define DDR_MODE_BLEN_2			0x0001		/* burst length 2 */
+#define DDR_MODE_BLEN_4			0x0002		/* burst length 4 */
+#define DDR_REFINT_166MHZ_7US		1302		/* exact value for 7.8125us */
+#define DDR_BSTOPRE			256		/* use 256 cycles as a starting point */
+#define DDR_MODE_MODEREG		0x0000		/* select mode register */
+
+/* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
+ */
+#define SDRAM_INTERVAL_REFINT		0x3FFF0000
+#define SDRAM_INTERVAL_REFINT_SHIFT	16
+#define SDRAM_INTERVAL_BSTOPRE		0x00003FFF
+#define SDRAM_INTERVAL_BSTOPRE_SHIFT	0
+
+/* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
+ */
+#define DDR_SDRAM_CLK_CNTL_SS_EN		0x80000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025	0x01000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05	0x02000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075	0x03000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1		0x04000000
+
+/* ECC_ERR_INJECT - Memory data path error injection mask ECC
+ */
+#define ECC_ERR_INJECT_EMB		(0x80000000>>22)	/* ECC Mirror Byte */
+#define ECC_ERR_INJECT_EIEN		(0x80000000>>23)	/* Error Injection Enable */
+#define ECC_ERR_INJECT_EEIM		(0xff000000>>24)	/* ECC Erroe Injection Enable */
+#define ECC_ERR_INJECT_EEIM_SHIFT	0
+
+/* CAPTURE_ECC - Memory data path read capture ECC
+ */
+#define CAPTURE_ECC_ECE			(0xff000000>>24)
+#define CAPTURE_ECC_ECE_SHIFT		0
+
+/* ERR_DETECT - Memory error detect
+ */
+#define ECC_ERROR_DETECT_MME		(0x80000000>>0)		/* Multiple Memory Errors */
+#define ECC_ERROR_DETECT_MBE		(0x80000000>>28)	/* Multiple-Bit Error */
+#define ECC_ERROR_DETECT_SBE		(0x80000000>>29)	/* Single-Bit ECC Error Pickup */
+#define ECC_ERROR_DETECT_MSE		(0x80000000>>31)	/* Memory Select Error */
+
+/* ERR_DISABLE - Memory error disable
+ */
+#define ECC_ERROR_DISABLE_MBED		(0x80000000>>28)	/* Multiple-Bit ECC Error Disable */
+#define ECC_ERROR_DISABLE_SBED		(0x80000000>>29)	/* Sinle-Bit ECC Error disable */
+#define ECC_ERROR_DISABLE_MSED		(0x80000000>>31)	/* Memory Select Error Disable */
+#define ECC_ERROR_ENABLE		~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\
+					 ECC_ERROR_DISABLE_MBED)
+/* ERR_INT_EN - Memory error interrupt enable
+ */
+#define ECC_ERR_INT_EN_MBEE		(0x80000000>>28)	/* Multiple-Bit ECC Error Interrupt Enable */
+#define ECC_ERR_INT_EN_SBEE		(0x80000000>>29)	/* Single-Bit ECC Error Interrupt Enable */
+#define ECC_ERR_INT_EN_MSEE		(0x80000000>>31)	/* Memory Select Error Interrupt Enable */
+#define ECC_ERR_INT_DISABLE		~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\
+					 ECC_ERR_INT_EN_MSEE)
+/* CAPTURE_ATTRIBUTES - Memory error attributes capture
+ */
+#define ECC_CAPT_ATTR_BNUM		(0xe0000000>>1)		/* Data Beat Num */
+#define ECC_CAPT_ATTR_BNUM_SHIFT	28
+#define ECC_CAPT_ATTR_TSIZ		(0xc0000000>>6)		/* Transaction Size */
+#define ECC_CAPT_ATTR_TSIZ_FOUR_DW	0
+#define ECC_CAPT_ATTR_TSIZ_ONE_DW	1
+#define ECC_CAPT_ATTR_TSIZ_TWO_DW	2
+#define ECC_CAPT_ATTR_TSIZ_THREE_DW	3
+#define ECC_CAPT_ATTR_TSIZ_SHIFT	24
+#define ECC_CAPT_ATTR_TSRC		(0xf8000000>>11)	/* Transaction Source */
+#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT	0x0
+#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF	0x2
+#define ECC_CAPT_ATTR_TSRC_TSEC1	0x4
+#define ECC_CAPT_ATTR_TSRC_TSEC2	0x5
+#define ECC_CAPT_ATTR_TSRC_USB		(0x06|0x07)
+#define ECC_CAPT_ATTR_TSRC_ENCRYPT	0x8
+#define ECC_CAPT_ATTR_TSRC_I2C		0x9
+#define ECC_CAPT_ATTR_TSRC_JTAG		0xA
+#define ECC_CAPT_ATTR_TSRC_PCI1		0xD
+#define ECC_CAPT_ATTR_TSRC_PCI2		0xE
+#define ECC_CAPT_ATTR_TSRC_DMA		0xF
+#define ECC_CAPT_ATTR_TSRC_SHIFT	16
+#define ECC_CAPT_ATTR_TTYP		(0xe0000000>>18)	/* Transaction Type */
+#define ECC_CAPT_ATTR_TTYP_WRITE	0x1
+#define ECC_CAPT_ATTR_TTYP_READ		0x2
+#define ECC_CAPT_ATTR_TTYP_R_M_W	0x3
+#define ECC_CAPT_ATTR_TTYP_SHIFT	12
+#define ECC_CAPT_ATTR_VLD		(0x80000000>>31)	/* Valid */
+
+/* ERR_SBE - Single bit ECC memory error management
+ */
+#define ECC_ERROR_MAN_SBET		(0xff000000>>8)		/* Single-Bit Error Threshold 0..255 */
+#define ECC_ERROR_MAN_SBET_SHIFT	16
+#define ECC_ERROR_MAN_SBEC		(0xff000000>>24)	/* Single Bit Error Counter 0..255 */
+#define ECC_ERROR_MAN_SBEC_SHIFT	0
+
+/* BR - Base Registers
+ */
+#define BR0				0x5000		/* Register offset to immr */
+#define BR1				0x5008
+#define BR2				0x5010
+#define BR3				0x5018
+#define BR4				0x5020
+#define BR5				0x5028
+#define BR6				0x5030
+#define BR7				0x5038
+
+#define BR_BA				0xFFFF8000
+#define BR_BA_SHIFT			15
+#define BR_PS				0x00001800
+#define BR_PS_SHIFT			11
+#define BR_PS_8				0x00000800	/* Port Size 8 bit */
+#define BR_PS_16			0x00001000	/* Port Size 16 bit */
+#define BR_PS_32			0x00001800	/* Port Size 32 bit */
+#define BR_DECC				0x00000600
+#define BR_DECC_SHIFT			9
+#define BR_WP				0x00000100
+#define BR_WP_SHIFT			8
+#define BR_MSEL				0x000000E0
+#define BR_MSEL_SHIFT			5
+#define BR_MS_GPCM			0x00000000	/* GPCM */
+#define BR_MS_SDRAM			0x00000060	/* SDRAM */
+#define BR_MS_UPMA			0x00000080	/* UPMA */
+#define BR_MS_UPMB			0x000000A0	/* UPMB */
+#define BR_MS_UPMC			0x000000C0	/* UPMC */
+#if defined(CONFIG_MPC8360)
+#define BR_ATOM				0x0000000C
+#define BR_ATOM_SHIFT			2
 #endif
+#define BR_V				0x00000001
+#define BR_V_SHIFT			0
 
-/*
- * LCRR - Clock Ratio Register (10.3.1.16)
- */
-#define LCRR_DBYP      0x80000000
-#define LCRR_DBYP_SHIFT        31
-#define LCRR_BUFCMDC   0x30000000
-#define LCRR_BUFCMDC_1 0x10000000
-#define LCRR_BUFCMDC_2 0x20000000
-#define LCRR_BUFCMDC_3 0x30000000
-#define LCRR_BUFCMDC_4 0x00000000
-#define LCRR_BUFCMDC_SHIFT     28
-#define LCRR_ECL       0x03000000
-#define LCRR_ECL_4     0x00000000
-#define LCRR_ECL_5     0x01000000
-#define LCRR_ECL_6     0x02000000
-#define LCRR_ECL_7     0x03000000
-#define LCRR_ECL_SHIFT         24
-#define LCRR_EADC      0x00030000
-#define LCRR_EADC_1    0x00010000
-#define LCRR_EADC_2    0x00020000
-#define LCRR_EADC_3    0x00030000
-#define LCRR_EADC_4    0x00000000
-#define LCRR_EADC_SHIFT        16
-#define LCRR_CLKDIV    0x0000000F
-#define LCRR_CLKDIV_2  0x00000002
-#define LCRR_CLKDIV_4  0x00000004
-#define LCRR_CLKDIV_8  0x00000008
-#define LCRR_CLKDIV_SHIFT       0
+#if defined(CONFIG_MPC8349)
+#define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
+#elif defined(CONFIG_MPC8360)
+#define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
+#endif
 
-/*
- * SCCR-System Clock Control Register
- */
-#define SCCR_TSEC1CM_0	0x00000000
-#define SCCR_TSEC1CM_1	0x40000000
-#define SCCR_TSEC1CM_2	0x80000000
-#define SCCR_TSEC1CM_3	0xC0000000
-#define SCCR_TSEC2CM_0	0x00000000
-#define SCCR_TSEC2CM_1	0x10000000
-#define SCCR_TSEC2CM_2	0x20000000
-#define SCCR_TSEC2CM_3	0x30000000
-#define SCCR_ENCCM_0	0x00000000
-#define SCCR_ENCCM_1	0x01000000
-#define SCCR_ENCCM_2	0x02000000
-#define SCCR_ENCCM_3	0x03000000
-#define SCCR_USBCM_0	0x00000000
-#define SCCR_USBCM_1	0x00500000
-#define SCCR_USBCM_2	0x00A00000
-#define SCCR_USBCM_3	0x00F00000
-
-#define SCCR_CLK_MASK	( SCCR_TSEC1CM_3	\
-			| SCCR_TSEC2CM_3	\
-			| SCCR_ENCCM_3		\
-			| SCCR_USBCM_3		)
-
-#define SCCR_DEFAULT	0xFFFFFFFF
+/* OR - Option Registers
+ */
+#define OR0				0x5004		/* Register offset to immr */
+#define OR1				0x500C
+#define OR2				0x5014
+#define OR3				0x501C
+#define OR4				0x5024
+#define OR5				0x502C
+#define OR6				0x5034
+#define OR7				0x503C
+
+#define OR_GPCM_AM			0xFFFF8000
+#define OR_GPCM_AM_SHIFT		15
+#define OR_GPCM_BCTLD			0x00001000
+#define OR_GPCM_BCTLD_SHIFT		12
+#define OR_GPCM_CSNT			0x00000800
+#define OR_GPCM_CSNT_SHIFT		11
+#define OR_GPCM_ACS			0x00000600
+#define OR_GPCM_ACS_SHIFT		9
+#define OR_GPCM_ACS_0b10		0x00000400
+#define OR_GPCM_ACS_0b11		0x00000600
+#define OR_GPCM_XACS			0x00000100
+#define OR_GPCM_XACS_SHIFT		8
+#define OR_GPCM_SCY			0x000000F0
+#define OR_GPCM_SCY_SHIFT		4
+#define OR_GPCM_SCY_1			0x00000010
+#define OR_GPCM_SCY_2			0x00000020
+#define OR_GPCM_SCY_3			0x00000030
+#define OR_GPCM_SCY_4			0x00000040
+#define OR_GPCM_SCY_5			0x00000050
+#define OR_GPCM_SCY_6			0x00000060
+#define OR_GPCM_SCY_7			0x00000070
+#define OR_GPCM_SCY_8			0x00000080
+#define OR_GPCM_SCY_9			0x00000090
+#define OR_GPCM_SCY_10			0x000000a0
+#define OR_GPCM_SCY_11			0x000000b0
+#define OR_GPCM_SCY_12			0x000000c0
+#define OR_GPCM_SCY_13			0x000000d0
+#define OR_GPCM_SCY_14			0x000000e0
+#define OR_GPCM_SCY_15			0x000000f0
+#define OR_GPCM_SETA			0x00000008
+#define OR_GPCM_SETA_SHIFT		3
+#define OR_GPCM_TRLX			0x00000004
+#define OR_GPCM_TRLX_SHIFT		2
+#define OR_GPCM_EHTR			0x00000002
+#define OR_GPCM_EHTR_SHIFT		1
+#define OR_GPCM_EAD			0x00000001
+#define OR_GPCM_EAD_SHIFT		0
+
+#define OR_UPM_AM			0xFFFF8000
+#define OR_UPM_AM_SHIFT			15
+#define OR_UPM_XAM			0x00006000
+#define OR_UPM_XAM_SHIFT		13
+#define OR_UPM_BCTLD			0x00001000
+#define OR_UPM_BCTLD_SHIFT		12
+#define OR_UPM_BI			0x00000100
+#define OR_UPM_BI_SHIFT			8
+#define OR_UPM_TRLX			0x00000004
+#define OR_UPM_TRLX_SHIFT		2
+#define OR_UPM_EHTR			0x00000002
+#define OR_UPM_EHTR_SHIFT		1
+#define OR_UPM_EAD			0x00000001
+#define OR_UPM_EAD_SHIFT		0
+
+#define OR_SDRAM_AM			0xFFFF8000
+#define OR_SDRAM_AM_SHIFT		15
+#define OR_SDRAM_XAM			0x00006000
+#define OR_SDRAM_XAM_SHIFT		13
+#define OR_SDRAM_COLS			0x00001C00
+#define OR_SDRAM_COLS_SHIFT		10
+#define OR_SDRAM_ROWS			0x000001C0
+#define OR_SDRAM_ROWS_SHIFT		6
+#define OR_SDRAM_PMSEL			0x00000020
+#define OR_SDRAM_PMSEL_SHIFT		5
+#define OR_SDRAM_EAD			0x00000001
+#define OR_SDRAM_EAD_SHIFT		0
+
+/* LBCR - Local Bus Configuration Register
+ */
+#define LBCR_LDIS			0x80000000
+#define LBCR_LDIS_SHIFT			31
+#define LBCR_BCTLC			0x00C00000
+#define LBCR_BCTLC_SHIFT		22
+#define LBCR_LPBSE			0x00020000
+#define LBCR_LPBSE_SHIFT		17
+#define LBCR_EPAR			0x00010000
+#define LBCR_EPAR_SHIFT			16
+#define LBCR_BMT			0x0000FF00
+#define LBCR_BMT_SHIFT			8
+
+/* LCRR - Clock Ratio Register
+ */
+#define LCRR_DBYP			0x80000000
+#define LCRR_DBYP_SHIFT			31
+#define LCRR_BUFCMDC			0x30000000
+#define LCRR_BUFCMDC_SHIFT		28
+#define LCRR_BUFCMDC_1			0x10000000
+#define LCRR_BUFCMDC_2			0x20000000
+#define LCRR_BUFCMDC_3			0x30000000
+#define LCRR_BUFCMDC_4			0x00000000
+#define LCRR_ECL			0x03000000
+#define LCRR_ECL_SHIFT			24
+#define LCRR_ECL_4			0x00000000
+#define LCRR_ECL_5			0x01000000
+#define LCRR_ECL_6			0x02000000
+#define LCRR_ECL_7			0x03000000
+#define LCRR_EADC			0x00030000
+#define LCRR_EADC_SHIFT			16
+#define LCRR_EADC_1			0x00010000
+#define LCRR_EADC_2			0x00020000
+#define LCRR_EADC_3			0x00030000
+#define LCRR_EADC_4			0x00000000
+#define LCRR_CLKDIV			0x0000000F
+#define LCRR_CLKDIV_SHIFT		0
+#define LCRR_CLKDIV_2			0x00000002
+#define LCRR_CLKDIV_4			0x00000004
+#define LCRR_CLKDIV_8			0x00000008
+
+/* DMAMR - DMA Mode Register
+ */
+#define DMA_CHANNEL_START			0x00000001	/* Bit - DMAMRn CS */
+#define DMA_CHANNEL_TRANSFER_MODE_DIRECT	0x00000004	/* Bit - DMAMRn CTM */
+#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN	0x00001000	/* Bit - DMAMRn SAHE */
+#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B	0x00000000	/* 2Bit- DMAMRn SAHTS 1byte */
+#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B	0x00004000	/* 2Bit- DMAMRn SAHTS 2bytes */
+#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B	0x00008000	/* 2Bit- DMAMRn SAHTS 4bytes */
+#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B	0x0000c000	/* 2Bit- DMAMRn SAHTS 8bytes */
+#define DMA_CHANNEL_SNOOP			0x00010000	/* Bit - DMAMRn DMSEN */
+
+/* DMASR - DMA Status Register
+ */
+#define DMA_CHANNEL_BUSY			0x00000004	/* Bit - DMASRn CB */
+#define DMA_CHANNEL_TRANSFER_ERROR		0x00000080	/* Bit - DMASRn TE */
+
+/* CONFIG_ADDRESS - PCI Config Address Register
+ */
+#define PCI_CONFIG_ADDRESS_EN		0x80000000
+#define PCI_CONFIG_ADDRESS_BN_SHIFT	16
+#define PCI_CONFIG_ADDRESS_BN_MASK	0x00ff0000
+#define PCI_CONFIG_ADDRESS_DN_SHIFT	11
+#define PCI_CONFIG_ADDRESS_DN_MASK	0x0000f800
+#define PCI_CONFIG_ADDRESS_FN_SHIFT	8
+#define PCI_CONFIG_ADDRESS_FN_MASK	0x00000700
+#define PCI_CONFIG_ADDRESS_RN_SHIFT	0
+#define PCI_CONFIG_ADDRESS_RN_MASK	0x000000fc
+
+/* POTAR - PCI Outbound Translation Address Register
+ */
+#define POTAR_TA_MASK			0x000fffff
+
+/* POBAR - PCI Outbound Base Address Register
+ */
+#define POBAR_BA_MASK			0x000fffff
+
+/* POCMR - PCI Outbound Comparision Mask Register
+ */
+#define POCMR_EN			0x80000000
+#define POCMR_IO			0x40000000	/* 0-memory space 1-I/O space */
+#define POCMR_SE			0x20000000	/* streaming enable */
+#define POCMR_DST			0x10000000	/* 0-PCI1 1-PCI2 */
+#define POCMR_CM_MASK			0x000fffff
+#define POCMR_CM_4G			0x00000000
+#define POCMR_CM_2G			0x00080000
+#define POCMR_CM_1G			0x000C0000
+#define POCMR_CM_512M			0x000E0000
+#define POCMR_CM_256M			0x000F0000
+#define POCMR_CM_128M			0x000F8000
+#define POCMR_CM_64M			0x000FC000
+#define POCMR_CM_32M			0x000FE000
+#define POCMR_CM_16M			0x000FF000
+#define POCMR_CM_8M			0x000FF800
+#define POCMR_CM_4M			0x000FFC00
+#define POCMR_CM_2M			0x000FFE00
+#define POCMR_CM_1M			0x000FFF00
+#define POCMR_CM_512K			0x000FFF80
+#define POCMR_CM_256K			0x000FFFC0
+#define POCMR_CM_128K			0x000FFFE0
+#define POCMR_CM_64K			0x000FFFF0
+#define POCMR_CM_32K			0x000FFFF8
+#define POCMR_CM_16K			0x000FFFFC
+#define POCMR_CM_8K			0x000FFFFE
+#define POCMR_CM_4K			0x000FFFFF
+
+/* PITAR - PCI Inbound Translation Address Register
+ */
+#define PITAR_TA_MASK			0x000fffff
+
+/* PIBAR - PCI Inbound Base/Extended Address Register
+ */
+#define PIBAR_MASK			0xffffffff
+#define PIEBAR_EBA_MASK			0x000fffff
+
+/* PIWAR - PCI Inbound Windows Attributes Register
+ */
+#define PIWAR_EN			0x80000000
+#define PIWAR_PF			0x20000000
+#define PIWAR_RTT_MASK			0x000f0000
+#define PIWAR_RTT_NO_SNOOP		0x00040000
+#define PIWAR_RTT_SNOOP			0x00050000
+#define PIWAR_WTT_MASK			0x0000f000
+#define PIWAR_WTT_NO_SNOOP		0x00004000
+#define PIWAR_WTT_SNOOP			0x00005000
+#define PIWAR_IWS_MASK			0x0000003F
+#define PIWAR_IWS_4K			0x0000000B
+#define PIWAR_IWS_8K			0x0000000C
+#define PIWAR_IWS_16K			0x0000000D
+#define PIWAR_IWS_32K			0x0000000E
+#define PIWAR_IWS_64K			0x0000000F
+#define PIWAR_IWS_128K			0x00000010
+#define PIWAR_IWS_256K			0x00000011
+#define PIWAR_IWS_512K			0x00000012
+#define PIWAR_IWS_1M			0x00000013
+#define PIWAR_IWS_2M			0x00000014
+#define PIWAR_IWS_4M			0x00000015
+#define PIWAR_IWS_8M			0x00000016
+#define PIWAR_IWS_16M			0x00000017
+#define PIWAR_IWS_32M			0x00000018
+#define PIWAR_IWS_64M			0x00000019
+#define PIWAR_IWS_128M			0x0000001A
+#define PIWAR_IWS_256M			0x0000001B
+#define PIWAR_IWS_512M			0x0000001C
+#define PIWAR_IWS_1G			0x0000001D
+#define PIWAR_IWS_2G			0x0000001E
 
 #endif	/* __MPC83XX_H__ */