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From: Mans Rullgard <mans@mansr.com>
Date: Thu, 2 Oct 2008 01:25:35 +0000 (+0100)
Subject: OMAP3: Beagleboard can have dual-chip RAM
X-Git-Url: http://git.mansr.com/?p=u-boot;a=commitdiff_plain;h=ef6ee5af8d584bddadb2d45ad4320cef96b8a934;hp=caccdb772c3028a3e3e801fb1554788150752ffc

OMAP3: Beagleboard can have dual-chip RAM

Some Beagleboards are fitted with dual-chip RAM. Returning DDR_STACKED
from get_mem_type() causes the second chip (on CS1) to be enabled.

FIXME: need a better way to configure this.

Signed-off-by: Mans Rullgard <mans@mansr.com>
---

diff --git a/cpu/omap3/board.c b/cpu/omap3/board.c
index 804021f..f7cf289 100644
--- a/cpu/omap3/board.c
+++ b/cpu/omap3/board.c
@@ -265,15 +265,17 @@ int dram_init(void)
 	 * where it can be started.  Early init code will init
 	 * memory on CS0.
 	 */
-	if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED))
+	if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
 		do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
+		make_cs1_contiguous();
+	}
 
 	size0 = get_sdr_cs_size(SDRC_CS0_OSET);
 	size1 = get_sdr_cs_size(SDRC_CS1_OSET);
 
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = size0;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + size0;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(1);
 	gd->bd->bi_dram[1].size = size1;
 
 	return 0;
diff --git a/cpu/omap3/mem.c b/cpu/omap3/mem.c
index 955fa70..53687a5 100644
--- a/cpu/omap3/mem.c
+++ b/cpu/omap3/mem.c
@@ -114,12 +114,12 @@ void make_cs1_contiguous(void)
  *             for a part. Helps in guessing which part
  *             we are currently using.
  *******************************************************/
-u32 mem_ok(void)
+u32 mem_ok(u32 cs)
 {
 	u32 val1, val2, addr;
 	u32 pattern = 0x12345678;
 
-	addr = OMAP34XX_SDRC_CS0;
+	addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
 
 	__raw_writel(0x0, addr + 0x400);  /* clear pos A */
 	__raw_writel(pattern, addr);	  /* pattern to pos B */
@@ -156,43 +156,40 @@ void sdrc_init(void)
 
 void do_sdrc_init(u32 offset, u32 early)
 {
+	u32 actim_offs = offset? 0x28: 0;
 
-	/* reset sdrc controller */
-	__raw_writel(SOFTRESET, SDRC_SYSCONFIG);
-	wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
-	__raw_writel(0, SDRC_SYSCONFIG);
+	if (early) {
+		/* reset sdrc controller */
+		__raw_writel(SOFTRESET, SDRC_SYSCONFIG);
+		wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
+		__raw_writel(0, SDRC_SYSCONFIG);
 
-	/* setup sdrc to ball mux */
-	__raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
+		/* setup sdrc to ball mux */
+		__raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
 
-	/* SDRC_MCFG0 register */
-	(*(unsigned int *) 0x6D000080) = 0x02584099; /* from Micron */
+		/* Disble Power Down of CKE cuz of 1 CKE on combo part */
+		__raw_writel(0x00000081, SDRC_POWER);
 
-	/* SDRC_RFR_CTRL0 register */
-	(*(unsigned int *) 0x6D0000a4) = 0x54601;    /* for 166M */
+		__raw_writel(0x0000A, SDRC_DLLA_CTRL);
+		sdelay(0x20000);
+	}
 
-	/* SDRC_ACTIM_CTRLA0 register */
-	(*(unsigned int *) 0x6D00009c) = 0xa29db4c6; /* for 166M */
+	__raw_writel(0x02584099,	SDRC_MCFG_0 + offset);
+	__raw_writel(0x4e201,		SDRC_RFR_CTRL + offset);
+	__raw_writel(0xaa9db4c6,	SDRC_ACTIM_CTRLA_0 + actim_offs);
+	__raw_writel(0x11517,		SDRC_ACTIM_CTRLB_0 + actim_offs);
 
-	/* SDRC_ACTIM_CTRLB0 register */
-	(*(unsigned int *) 0x6D0000a0) = 0x12214;    /* for 166M */
+	__raw_writel(CMD_NOP,		SDRC_MANUAL_0 + offset);
+	__raw_writel(CMD_PRECHARGE,	SDRC_MANUAL_0 + offset);
+	__raw_writel(CMD_AUTOREFRESH,	SDRC_MANUAL_0 + offset);
+	__raw_writel(CMD_AUTOREFRESH,	SDRC_MANUAL_0 + offset);
 
-	/* Disble Power Down of CKE cuz of 1 CKE on combo part */
-	(*(unsigned int *) 0x6D000070) = 0x00000081;
+	/*  CAS latency 3, Write Burst = Read Burst, Serial Mode,
+	    Burst length = 4 */
+	__raw_writel(0x00000032,	SDRC_MR_0 + offset);
 
-	/* SDRC_Manual command register */
-	(*(unsigned int *) 0x6D0000a8) = 0x00000000; /* NOP command */
-	(*(unsigned int *) 0x6D0000a8) = 0x00000001; /* Precharge command */
-	(*(unsigned int *) 0x6D0000a8) = 0x00000002; /* Auto-refresh command */
-	(*(unsigned int *) 0x6D0000a8) = 0x00000002; /* Auto-refresh command */
-
-	/* SDRC MR0 register */
-	(*(int *) 0x6D000084) = 0x00000032;	/*  Burst length = 4 */
-	/* CAS latency = 3, Write Burst = Read Burst Serial Mode */
-
-	/* SDRC DLLA control register */
-	(*(unsigned int *) 0x6D000060) = 0x0000A;
-	sdelay(0x20000);
+	if (!mem_ok(offset))
+		__raw_writel(0, SDRC_MCFG_0 + offset);
 }
 
 void enable_gpmc_config(u32 *gpmc_config, u32 gpmc_base, u32 base, u32 size)
diff --git a/cpu/omap3/sys_info.c b/cpu/omap3/sys_info.c
index 12cf5ba..64d9e7e 100644
--- a/cpu/omap3/sys_info.c
+++ b/cpu/omap3/sys_info.c
@@ -90,8 +90,11 @@ u32 is_mem_sdr(void)
  ***********************************************************/
 u32 get_mem_type(void)
 {
-	/* Current SDP3430 uses 2x16 MDDR Infenion parts */
+#ifdef CONFIG_OMAP3_BEAGLE
+	return DDR_STACKED;
+#else
 	return DDR_DISCRETE;
+#endif
 }
 
 /***********************************************************************
@@ -109,6 +112,22 @@ u32 get_sdr_cs_size(u32 offset)
 }
 
 /***********************************************************************
+ * get_sdr_cs_offset() - get offset of cs from cs0 start
+ ************************************************************************/
+u32 get_sdr_cs_offset(u32 cs)
+{
+	u32 offset;
+
+	if (!cs)
+		return 0;
+
+	offset = __raw_readl(SDRC_CS_CFG);
+	offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
+
+	return offset;
+}
+
+/***********************************************************************
  * get_board_type() - get board type based on current production stats.
  *  - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info.
  *    when they are available we can get info from there.  This should
diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h
index d47defb..df2d150 100644
--- a/include/asm-arm/arch-omap3/cpu.h
+++ b/include/asm-arm/arch-omap3/cpu.h
@@ -123,7 +123,6 @@
 #define SDRC_ACTIM_CTRLA_1	(OMAP34XX_SDRC_BASE+0xC4)
 #define SDRC_ACTIM_CTRLB_1	(OMAP34XX_SDRC_BASE+0xC8)
 #define SDRC_RFR_CTRL		(OMAP34XX_SDRC_BASE+0xA4)
-#define SDRC_RFR_CTRL		(OMAP34XX_SDRC_BASE+0xA4)
 #define SDRC_MANUAL_0		(OMAP34XX_SDRC_BASE+0xA8)
 #define OMAP34XX_SDRC_CS0	0x80000000
 #define OMAP34XX_SDRC_CS1	0xA0000000
diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h
index 279bdce..5b0bd9e 100644
--- a/include/asm-arm/arch-omap3/sys_proto.h
+++ b/include/asm-arm/arch-omap3/sys_proto.h
@@ -50,6 +50,7 @@ u32 get_gpmc0_width(void);
 u32 get_board_type(void);
 void display_board_info(u32);
 u32 get_sdr_cs_size(u32 offset);
+u32 get_sdr_cs_offset(u32 cs);
 u32 running_in_sdram(void);
 u32 running_in_sram(void);
 u32 running_in_flash(void);