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From: "Syed Mohammed, Khasim" <khasim@ti.com>
To: Koen Kooi <k.kooi@student.utwente.nl>
CC: "linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>,
"Woodruff,
Richard" <r-woodruff2@ti.com>
Date: Wed, 7 May 2008 13:12:13 +0530
Subject: RE: public git l2 cache off.
The below patch should get you going with L2 Cache enabled on GIT kernel, tested on Beagle board.
Regards,
Khasim
--- my_linux_omap/arch/arm/mm/Kconfig 2008-05-06 16:37:17.000000000 +0530
+++ git/arch/arm/mm/Kconfig 2008-05-07 12:40:05.000000000 +0530
@@ -659,6 +659,20 @@ config CPU_DCACHE_SIZE
If your SoC is configured to have a different size, define the value
here with proper conditions.
+choice
+ prompt "L2 Cache Size"
+ depends on ARCH_OMAP34XX
+
+config CPU_LOCKDOWN_TO_64K_L2
+ bool "Lock down L2 Cache to 64K"
+
+config CPU_LOCKDOWN_TO_128K_L2
+ bool "Lock down L2 Cache to 128K"
+
+config CPU_LOCKDOWN_TO_256K_L2
+ bool "Lock down L2 Cache to 256K"
+endchoice
+
config CPU_DCACHE_WRITETHROUGH
bool "Force write through D-cache"
depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
@@ -674,6 +688,12 @@ config CPU_CACHE_ROUND_ROBIN
Say Y here to use the predictable round-robin cache replacement
policy. Unless you specifically require this or are unsure, say N.
+config CPU_L2CACHE_DISABLE
+ bool "Disable level 2 cache"
+ depends on CPU_V7
+ help
+ Say Y here to disable the level 2 cache. If unsure, say N.
+
config CPU_BPREDICT_DISABLE
bool "Disable branch prediction"
depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
--- /tmp/proc-v7.S 2008-05-07 10:05:37.949232951 +0200
+++ git/arch/arm/mm/proc-v7.S 2008-05-07 10:13:18.626067909 +0200
@@ -182,11 +182,72 @@
mov r10, #0x1f @ domains 0, 1 = manager
mcr p15, 0, r10, c3, c0, 0 @ load domain access register
#endif
+#if defined(CONFIG_ARCH_OMAP3)
+ @ L2 cache is enabled in the aux control register
+ mrc p15, 0, r0, c1, c0, 1
+ orr r0, r0, #0x11 @ speculative+no-alais protection
+#ifdef CONFIG_CPU_L2CACHE_DISABLE
+ bic r0, r0, #0x2 @ disable L2 Cache.
+#else
+ orr r0, r0, #0x2 @ enaable L2 Cache.
+#endif
+
+/* On 3430 ES2.0 ZeBu and silicon, Aux Ctrl Reg can be written outside
+ * Secure mode also
+ */
+ mcr p15, 0, r0, c1, c0, 1
+
+#ifdef CONFIG_ARCH_OMAP34XX
+#ifdef CONFIG_CPU_LOCKDOWN_TO_64K_L2
+ mov r10, #0xfc
+ mcr p15, 1, r10, c9, c0, 0
+#endif
+
+#ifdef CONFIG_CPU_LOCKDOWN_TO_128K_L2
+ mov r10, #0xf0
+ mcr p15, 1, r10, c9, c0, 0
+#endif
+
+#ifdef CONFIG_CPU_LOCKDOWN_TO_256K_L2
+ mov r10, #0x00
+ mcr p15, 1, r10, c9, c0, 0
+#endif
+#endif
+
adr r5, v7_crval
ldmia r5, {r5, r6}
- mrc p15, 0, r0, c1, c0, 0 @ read control register
- bic r0, r0, r5 @ clear bits them
- orr r0, r0, r6 @ set them
+ mrc p15, 0, r0, c1, c0, 0 @ read control register
+ bic r0, r0, r5 @ clear bits them
+ orr r0, r0, r6 @ set them
+ mov pc, lr @ return to head.S:__ret
+
+ /*
+ * TAT N EV F H R
+ * .EFR M.EE .UI. ..A. .RVI Z... B... .CAM
+ * 0xxx x0xx 11x0 01x1 0xxx x000 0111 1xxx < forced typical
+ * r rr rr r rr r r rrr rrrr r < always read only
+ * .000 ..00 ..0. ..0. .011 1... .... .101 < we want
+ */
+ .type v7_crval, #object
+v7_crval:
+ crval clear=0x7322f006, mmuset=0x00003805, ucset=0x00001804
+#else
+
+#ifndef CONFIG_CPU_L2CACHE_DISABLE
+ @ L2 cache configuration in the L2 aux control register
+ mrc p15, 1, r10, c9, c0, 2
+ bic r10, r10, #(1 << 16) @ L2 outer cache
+ mcr p15, 1, r10, c9, c0, 2
+ @ L2 cache is enabled in the aux control register
+ mrc p15, 0, r10, c1, c0, 1
+ orr r10, r10, #2
+ mcr p15, 0, r10, c1, c0, 1
+#endif
+ mrc p15, 0, r0, c1, c0, 0 @ read control register
+ ldr r10, cr1_clear @ get mask for bits to clear
+ bic r0, r0, r10 @ clear bits them
+ ldr r10, cr1_set @ get mask for bits to set
+ orr r0, r0, r10 @ set them
mov pc, lr @ return to head.S:__ret
/*
@@ -195,9 +256,13 @@
* rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
* 0 110 0011 1.00 .111 1101 < we want
*/
- .type v7_crval, #object
-v7_crval:
- crval clear=0x0120c302, mmuset=0x00c0387d, ucset=0x00c0187c
+ .type cr1_clear, #object
+ .type cr1_set, #object
+cr1_clear:
+ .word 0x0120c302
+cr1_set:
+ .word 0x00c0387d
+#endif
__v7_setup_stack:
.space 4 * 11 @ 11 registers
@@ -205,7 +270,6 @@
.type v7_processor_functions, #object
ENTRY(v7_processor_functions)
.word v7_early_abort
- .word pabort_ifar
.word cpu_v7_proc_init
.word cpu_v7_proc_fin
.word cpu_v7_reset
@@ -213,6 +277,7 @@
.word cpu_v7_dcache_clean_area
.word cpu_v7_switch_mm
.word cpu_v7_set_pte_ext
+ .word pabort_ifar
.size v7_processor_functions, . - v7_processor_functions
.type cpu_arch_name, #object
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