summaryrefslogtreecommitdiff
path: root/packages/at91bootstrap/files/0004-AFEB9260-133-board-support.patch
blob: c88801cc9ed4f743350250b6581c7ab6491330ea (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
From ef96ec1464569eb42788076d27c9aa9376a3c396 Mon Sep 17 00:00:00 2001
From: Sergey Lapin <slapin@slind.org>
Date: Sat, 27 Sep 2008 01:34:49 +0400
Subject: [PATCH] AFEB9260-133 board support


Signed-off-by: Sergey Lapin <slapin@ossfans.org>
---
 board/afeb9260-133/afeb9260-133.c           |  403 +++++++++++++++++++++++++++
 board/afeb9260-133/afeb9260-133.mk          |    8 +
 board/afeb9260-133/dataflash/afeb9260-133.h |  127 +++++++++
 board/afeb9260-133/nandflash/afeb9260-133.h |  151 ++++++++++
 board/afeb9260-133/pll.h                    |   35 +++
 5 files changed, 724 insertions(+), 0 deletions(-)
 create mode 100644 board/afeb9260-133/afeb9260-133.c
 create mode 100644 board/afeb9260-133/afeb9260-133.mk
 create mode 100644 board/afeb9260-133/dataflash/afeb9260-133.h
 create mode 100644 board/afeb9260-133/nandflash/afeb9260-133.h
 create mode 100644 board/afeb9260-133/pll.h

diff --git a/board/afeb9260-133/afeb9260-133.c b/board/afeb9260-133/afeb9260-133.c
new file mode 100644
index 0000000..f54f7a7
--- /dev/null
+++ b/board/afeb9260-133/afeb9260-133.c
@@ -0,0 +1,403 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support  -  ROUSSET  -
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2006, Atmel Corporation
+
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaiimer below.
+ *
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the disclaimer below in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ * File Name           : at91sam9260ek.c
+ * Object              :
+ * Creation            : NLe Jul 13th 2006
+ * ODi Nov 9th         : dstp #3507 "Bad PIO descriptors in at91samxxxek.c"
+ *-----------------------------------------------------------------------------
+ */
+#include "../../include/part.h"
+#include "../../include/gpio.h"
+#include "../../include/pmc.h"
+#include "../../include/debug.h"
+#include "../../include/sdramc.h"
+#include "../../include/main.h"
+#ifdef CFG_NANDFLASH
+#include "../../include/nandflash.h"
+#endif
+#ifdef CFG_DATAFLASH
+#include "../../include/dataflash.h"
+#endif
+#ifdef CFG_FLASH
+#include "../../include/flash.h"
+#endif
+static inline unsigned int get_cp15(void)
+{
+	unsigned int value;
+	__asm__("mrc p15, 0, %0, c1, c0, 0" : "=r" (value));
+	return value;
+}
+
+static inline void set_cp15(unsigned int value)
+{
+	__asm__("mcr p15, 0, %0, c1, c0, 0" : : "r" (value));
+}
+
+#ifdef CFG_HW_INIT
+/*----------------------------------------------------------------------------*/
+/* \fn    hw_init							      */
+/* \brief This function performs very low level HW initialization	      */
+/* This function is invoked as soon as possible during the c_startup	      */
+/* The bss segment must be initialized					      */
+/*----------------------------------------------------------------------------*/
+void hw_init(void)
+{
+	unsigned int cp15;
+	
+	/* Disable watchdog */
+	writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);
+
+	/* At this stage the main oscillator is supposed to be enabled
+	 * PCK = MCK = MOSC */
+
+	/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
+	pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
+
+	/* Switch MCK on PLLA output PCK = PLLA = 2 * MCK */
+	pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
+
+	/* Configure PLLB */
+	pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT);
+
+	/* Configure CP15 */
+	/* Using procedure from u-boot for arm926ejs */
+	cp15 = get_cp15();
+	cp15 &= ~I_CACHE;
+	set_cp15(cp15);
+
+	/* Configure the PIO controller */
+	writel(3 << 14, AT91C_BASE_PIOB + PIO_ASR(0));
+	writel(3 << 14, AT91C_BASE_PIOB + PIO_PDR(0));
+
+#ifdef CFG_DEBUG
+	/* Enable Debug messages on the DBGU */
+	dbg_init(BAUDRATE(MASTER_CLOCK, 115200));
+	/* Configure CP15 */
+	/* Using procedure from u-boot for arm926ejs */
+#if 0
+	cp15 = get_cp15();
+	cp15 |= 0xC0000000;
+	set_cp15(cp15);
+#endif
+
+	dbg_print("AT91 bootstrap loading from @< 0x8400\n\r");
+#endif /* CFG_DEBUG */
+
+#ifdef CFG_SDRAM
+	/* Initialize the matrix */
+	writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS1A_SDRAMC, AT91C_BASE_CCFG + CCFG_EBICSA);
+
+	/* Configure SDRAM Controller */
+
+#define HYNIX
+
+//#define MICRON
+#ifdef MICRON
+#define MICRON_REFRESH 1420 /* 15.625 us / 11 ns @ 180 Mhz*/
+	sdram_init(	AT91C_SDRAMC_NC_9  |
+				AT91C_SDRAMC_NR_12 |
+				AT91C_SDRAMC_CAS_2 |
+				AT91C_SDRAMC_NB_4_BANKS |
+				AT91C_SDRAMC_DBW_32_BITS |
+				AT91C_SDRAMC_TWR_2 | // 1 CLK+7ns
+				AT91C_SDRAMC_TRC_7 | // 60 ns
+				AT91C_SDRAMC_TRP_3 | // 15 ns
+				AT91C_SDRAMC_TRCD_3 | // 15 ns
+				AT91C_SDRAMC_TRAS_7 | // 37-120 ns
+				AT91C_SDRAMC_TXSR_7, /* 67ns */ /* Control Register */
+				/* 600 700 735 */ MICRON_REFRESH /* 740 1536*/ );	/* Refresh Timer Register */
+
+#endif
+/* 
+HY57V561620BT-H
+     *CAS lat		*tRCD		*tRAS		*tRC		*tRP		tAC	tOH
+133	2		2		6		8		2		5.4ns	2.7ns
+125	3		3		6		9		3		6ns	3ns
+100	2		2		5		7		2		6ns	3ns
+
+*/
+#ifdef HYNIX
+#if defined(PLLA_180MHz)
+/* CLK= 11ns */
+/* TWR = tDPL = 2 2CLK always */
+/* TRC = tRC = 65ns = 6 clk */
+/* TRP = tRP = 20ns = 2 clk */
+/* TRCD = tRCD = 20ns = 2 clk */
+/* TRAS = tRAS = 45ns = 5 clk */
+/* TXSR = tRRC = 65ns = 6 clk */
+
+	sdram_init(	AT91C_SDRAMC_NC_9  |
+				AT91C_SDRAMC_NR_13 |
+				AT91C_SDRAMC_CAS_2 |
+				AT91C_SDRAMC_NB_4_BANKS |
+				AT91C_SDRAMC_DBW_32_BITS |
+				AT91C_SDRAMC_TWR_2 |
+				AT91C_SDRAMC_TRC_6 | /* *7 */
+				AT91C_SDRAMC_TRP_2 |
+				AT91C_SDRAMC_TRCD_2 |
+				AT91C_SDRAMC_TRAS_5 | /* *5 */
+				AT91C_SDRAMC_TXSR_6, /* *8 */	/* Control Register */
+				710);	/* Refresh Timer Register */
+
+#elif defined(PLLA_120MHz)
+/* CLK= 16ns, MCLK=60MHz */
+/* TWR = tDPL = 2 2CLK always */
+/* TRC = tRC = 65ns = 4 clk */
+/* TRP = tRP = 20ns = 2 clk */
+/* TRCD = tRCD = 20ns = 2 clk */
+/* TRAS = tRAS = 45ns = 3 clk */
+/* TXSR = tRRC = 65ns = 4 clk */
+
+	sdram_init(	AT91C_SDRAMC_NC_9  |
+				AT91C_SDRAMC_NR_13 |
+				AT91C_SDRAMC_CAS_2 |
+				AT91C_SDRAMC_NB_4_BANKS |
+				AT91C_SDRAMC_DBW_32_BITS |
+				AT91C_SDRAMC_TWR_2 |
+				AT91C_SDRAMC_TRC_4 |
+				AT91C_SDRAMC_TRP_2 |
+				AT91C_SDRAMC_TRCD_2 |
+				AT91C_SDRAMC_TRAS_3 | /* *5 */
+				AT91C_SDRAMC_TXSR_4, /* *8 */	/* Control Register */
+				1032);	/* Refresh Timer Register */
+#else
+#error define PLLA180MHz
+#endif
+#endif /* HYNIX */
+#endif /* CFG_SDRAM */
+
+#ifdef	CFG_FLASH
+	flash_hw_init();
+#endif
+	nandflash_hw_init();
+	dbg_print("CP15=\r\n");
+	dbg_print_hex(get_cp15);
+}
+#endif /* CFG_HW_INIT */
+
+#ifdef CFG_SDRAM
+/*------------------------------------------------------------------------------*/
+/* \fn    sdramc_hw_init							*/
+/* \brief This function performs SDRAMC HW initialization			*/
+/*------------------------------------------------------------------------------*/
+void sdramc_hw_init(void)
+{
+	/* Configure PIOs */
+/*	const struct pio_desc sdramc_pio[] = {
+		{"D16", AT91C_PIN_PC(16), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D17", AT91C_PIN_PC(17), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D18", AT91C_PIN_PC(18), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D19", AT91C_PIN_PC(19), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D20", AT91C_PIN_PC(20), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D21", AT91C_PIN_PC(21), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D22", AT91C_PIN_PC(22), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D23", AT91C_PIN_PC(23), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D24", AT91C_PIN_PC(24), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D25", AT91C_PIN_PC(25), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D26", AT91C_PIN_PC(26), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D27", AT91C_PIN_PC(27), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D28", AT91C_PIN_PC(28), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D29", AT91C_PIN_PC(29), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D30", AT91C_PIN_PC(30), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"D31", AT91C_PIN_PC(31), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
+	};
+*/
+	/* Configure the SDRAMC PIO controller to output PCK0 */
+/*	pio_setup(sdramc_pio); */
+
+	writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_ASR(0));
+	writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_PDR(0));
+
+}
+#endif /* CFG_SDRAM */
+
+#ifdef CFG_DATAFLASH
+
+/*------------------------------------------------------------------------------*/
+/* \fn    df_recovery								*/
+/* \brief This function erases DataFlash Page 0 if BP4 is pressed 		*/
+/*        during boot sequence							*/
+/*------------------------------------------------------------------------------*/
+void df_recovery(AT91PS_DF pDf)
+{
+#if 0
+#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS1_DATAFLASH)
+	/* Configure PIOs */
+	const struct pio_desc bp4_pio[] = {
+		{"BP4", AT91C_PIN_PA(31), 0, PIO_PULLUP, PIO_INPUT},
+		{(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
+	};
+
+	/* Configure the PIO controller */
+	writel((1 << AT91C_ID_PIOA), PMC_PCER + AT91C_BASE_PMC);
+	pio_setup(bp4_pio);
+	
+	/* If BP4 is pressed during Boot sequence */
+	/* Erase NandFlash block 0*/
+	if ( !pio_get_value(AT91C_PIN_PA(31)) )
+		df_page_erase(pDf, 0);
+#endif
+#endif
+}
+
+/*------------------------------------------------------------------------------*/
+/* \fn    df_hw_init								*/
+/* \brief This function performs DataFlash HW initialization			*/
+/*------------------------------------------------------------------------------*/
+void df_hw_init(void)
+{
+#if 0
+	/* Configure PIOs */
+	const struct pio_desc df_pio[] = {
+		{"MISO",  AT91C_PIN_PA(0), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"MOSI",  AT91C_PIN_PA(1), 0, PIO_DEFAULT, PIO_PERIPH_A},
+		{"SPCK",  AT91C_PIN_PA(2), 0, PIO_DEFAULT, PIO_PERIPH_A},
+#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS0_DATAFLASH)
+		{"NPCS0", AT91C_PIN_PA(3), 0, PIO_DEFAULT, PIO_PERIPH_A},
+#endif
+#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS1_DATAFLASH)
+		{"NPCS1", AT91C_PIN_PC(11), 0, PIO_DEFAULT, PIO_PERIPH_B},
+#endif
+		{(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
+	};
+
+	/* Configure the PIO controller */
+	pio_setup(df_pio);
+#else
+	writel(0xf, 0xfffff444);
+	writel(0xf, 0xfffff460);
+	writel(0xf, 0xfffff470);
+	writel(0xf, 0xfffff404);
+	writel(1 << 11, AT91C_BASE_PIOC + PIO_BSR(0));
+	writel(1 << 11, AT91C_BASE_PIOC + PIO_PDR(0));
+#endif
+}
+#endif /* CFG_DATAFLASH */
+
+#ifdef CFG_FLASH
+
+/*------------------------------------------------------------------------------*/
+/* \fn    flash_hw_init								*/
+/* \brief This function performs Flash HW initialization			*/
+/*------------------------------------------------------------------------------*/
+void flash_hw_init(void)
+{
+	/* Configure PIOs */
+	const struct pio_desc flash_pio[] = {
+		{(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
+	};
+
+	/* Configure the PIO controller */
+	pio_setup(flash_pio);
+}
+
+#endif /* CFG_FLASH */
+
+#ifdef CFG_NANDFLASH
+/*------------------------------------------------------------------------------*/
+/* \fn    nand_recovery						*/
+/* \brief This function erases NandFlash Block 0 if BP4 is pressed 		*/
+/*        during boot sequence							*/
+/*------------------------------------------------------------------------------*/
+static void nand_recovery(void)
+{
+	/* Configure PIOs */
+	const struct pio_desc bp4_pio[] = {
+		{"BP4", AT91C_PIN_PA(31), 0, PIO_PULLUP, PIO_INPUT},
+		{(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
+	};
+
+	/* Configure the PIO controller */
+	writel((1 << AT91C_ID_PIOA), PMC_PCER + AT91C_BASE_PMC);
+	pio_setup(bp4_pio);
+	
+	/* If BP4 is pressed during Boot sequence */
+	/* Erase NandFlash block 0*/
+	if (!pio_get_value(AT91C_PIN_PA(31)) )
+		AT91F_NandEraseBlock0();
+}
+#endif
+/*------------------------------------------------------------------------------*/
+/* \fn    nandflash_hw_init							*/
+/* \brief NandFlash HW init							*/
+/*------------------------------------------------------------------------------*/
+void nandflash_hw_init(void)
+{
+#if 0
+	/* Configure PIOs */
+	const struct pio_desc nand_pio[] = {
+		{"RDY_BSY", AT91C_PIN_PC(13), 0, PIO_PULLUP, PIO_INPUT},
+		{"NANDCS",  AT91C_PIN_PC(14), 0, PIO_PULLUP, PIO_OUTPUT},
+		{(char *) 0, 0, 0,  PIO_DEFAULT, PIO_PERIPH_A},
+	};
+#endif
+	/* Setup Smart Media, first enable the address range of CS3 in HMATRIX user interface */
+	writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS3A_SM, AT91C_BASE_CCFG + CCFG_EBICSA);
+		    
+	/* Configure SMC CS3 */
+ 	writel((AT91C_SM_NWE_SETUP | AT91C_SM_NCS_WR_SETUP | AT91C_SM_NRD_SETUP | AT91C_SM_NCS_RD_SETUP), AT91C_BASE_SMC + SMC_SETUP3);
+  	writel((AT91C_SM_NWE_PULSE | AT91C_SM_NCS_WR_PULSE | AT91C_SM_NRD_PULSE | AT91C_SM_NCS_RD_PULSE), AT91C_BASE_SMC + SMC_PULSE3);
+	writel((AT91C_SM_NWE_CYCLE | AT91C_SM_NRD_CYCLE)						, AT91C_BASE_SMC + SMC_CYCLE3);
+	writel((AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE | AT91C_SMC_NWAITM_NWAIT_DISABLE | 
+  		AT91C_SMC_DBW_WIDTH_EIGTH_BITS | AT91C_SM_TDF)						, AT91C_BASE_SMC + SMC_CTRL3);
+
+	/* Configure the PIO controller */
+	writel((1 << AT91C_ID_PIOC), PMC_PCER + AT91C_BASE_PMC);
+
+	writel(1 << 13, AT91C_BASE_PIOC + PIO_IFDR(0));
+	writel(1 << 13, AT91C_BASE_PIOC + PIO_PPUER(0));
+	writel(1 << 13, AT91C_BASE_PIOC + PIO_ODR(0));
+	writel(1 << 14, AT91C_BASE_PIOC + PIO_CODR(0));
+	writel(1 << 14, AT91C_BASE_PIOC + PIO_MDDR(0));
+	writel(1 << 14, AT91C_BASE_PIOC + PIO_PPUDR(0));
+	writel(1 << 14, AT91C_BASE_PIOC + PIO_OER(0));
+	writel(3 << 13, AT91C_BASE_PIOC + PIO_IDR(0));
+	writel(3 << 13, AT91C_BASE_PIOC + PIO_PER(0));
+
+#if 0	
+	nand_recovery();
+#endif
+}
+
+
+#if 0
+/*------------------------------------------------------------------------------*/
+/* \fn    nandflash_cfg_16bits_dbw_init						*/
+/* \brief Configure SMC in 16 bits mode						*/
+/*------------------------------------------------------------------------------*/
+void nandflash_cfg_16bits_dbw_init(void)
+{
+	writel(readl(AT91C_BASE_SMC + SMC_CTRL3) | AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS, AT91C_BASE_SMC + SMC_CTRL3);
+}
+
+#endif /* #ifdef CFG_NANDFLASH */
diff --git a/board/afeb9260-133/afeb9260-133.mk b/board/afeb9260-133/afeb9260-133.mk
new file mode 100644
index 0000000..84e45d3
--- /dev/null
+++ b/board/afeb9260-133/afeb9260-133.mk
@@ -0,0 +1,8 @@
+# Target name (case sensitive!!!)
+TARGET=AFEB9260_133
+# Board name (case sensitive!!!)
+BOARD=afeb9260-133
+# Link Address and Top_of_Memory
+LINK_ADDR=0x200000
+TOP_OF_MEMORY=0x301000
+
diff --git a/board/afeb9260-133/dataflash/afeb9260-133.h b/board/afeb9260-133/dataflash/afeb9260-133.h
new file mode 100644
index 0000000..2ebb020
--- /dev/null
+++ b/board/afeb9260-133/dataflash/afeb9260-133.h
@@ -0,0 +1,127 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support  -  ROUSSET  -
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2006, Atmel Corporation
+
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaiimer below.
+ *
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the disclaimer below in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ * File Name           : at91sam9260ek.h
+ * Object              :
+ * Creation            : NLe Jul 13th 2006
+ *-----------------------------------------------------------------------------
+ */
+#ifndef _AFEB9260_133_H
+#define _AFEB9260_133_H
+#include	"spi.h"
+#include	"pll.h"
+
+/* ******************************************************************* */
+/* DataFlash Settings                                                  */
+/*                                                                     */
+/* ******************************************************************* */
+#define AT91C_BASE_SPI	AT91C_BASE_SPI0
+#define AT91C_ID_SPI	AT91C_ID_SPI0
+
+/* SPI CLOCK */
+#define AT91C_SPI_CLK 		 5000000
+/* AC characteristics */
+/* DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns */
+#define DATAFLASH_TCSS		(0x1a << 16)	/* 250ns min (tCSS) <=> 12/48000000 = 250ns */
+#define DATAFLASH_TCHS		(0x1 << 24)	/* 250ns min (tCSH) <=> (64*1+SCBR)/(2*48000000) */
+
+#define DF_CS_SETTINGS 		((SPI_MODE) | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | ((MASTER_CLOCK / AT91C_SPI_CLK) << 8))
+
+
+/* ******************************************************************* */
+/* BootStrap Settings                                                  */
+/*                                                                     */
+/* ******************************************************************* */
+#define MACH_TYPE       	0x44B		/* AT91SAM9260-EK */
+
+#define IMG_ADDRESS 		0x8400		/* Image Address in DataFlash */
+
+#if	defined(IMG_SIZE)
+#warning			"IMG_SIZE redefined"
+#else
+#define	IMG_SIZE		0x39000	/* Image Size in DataFlash    */
+#endif
+
+#if	defined(JUMP_ADDR)
+#warning			"JUMP_ADDR redefined"
+#else
+#define JUMP_ADDR		0x21F00000	/* Final Jump Address 	      */
+#endif
+
+/* ******************************************************************* */
+/* NandFlash Settings                                                  */
+/*                                                                     */
+/* ******************************************************************* */
+#define AT91C_SMARTMEDIA_BASE	0x40000000
+
+#define AT91_SMART_MEDIA_ALE    (1 << 21)	/* our ALE is AD21 */
+#define AT91_SMART_MEDIA_CLE    (1 << 22)	/* our CLE is AD22 */
+
+#define NAND_DISABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_SODR = AT91C_PIO_PC14;} while(0)
+#define NAND_ENABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_CODR = AT91C_PIO_PC14;} while(0)
+
+#define NAND_WAIT_READY() while (!(*(volatile unsigned int *)AT91C_PIOC_PDSR & AT91C_PIO_PC13))
+
+
+/* ******************************************************************** */
+/* SMC Chip Select 3 Timings for NandFlash for MASTER_CLOCK = 100000000.*/
+/* Micron 16bits 256Mb for MASTER_CLOCK = 100000000.			*/
+/* Please refer to SMC section in AT91SAM9261 datasheet to learn how 	*/
+/* to generate these values. 						*/
+/* ******************************************************************** */
+
+#define AT91C_SM_NWE_SETUP	(2 << 0)
+#define AT91C_SM_NCS_WR_SETUP	(2 << 8)
+#define AT91C_SM_NRD_SETUP	(2 << 16)
+#define AT91C_SM_NCS_RD_SETUP	(2 << 24)
+  
+#define AT91C_SM_NWE_PULSE 	(4 << 0)
+#define AT91C_SM_NCS_WR_PULSE	(4 << 8)
+#define AT91C_SM_NRD_PULSE	(4 << 16)
+#define AT91C_SM_NCS_RD_PULSE	(4 << 24)
+  
+#define AT91C_SM_NWE_CYCLE 	(8 << 0)
+#define AT91C_SM_NRD_CYCLE	(8 << 16)
+
+#define AT91C_SM_TDF	        (2 << 16)
+
+
+
+/* ******************************************************************* */
+/* Application Settings                                                */
+/* ******************************************************************* */
+#define CFG_DEBUG
+#define CFG_DATAFLASH
+#define	CFG_SDRAM
+#define	CFG_HW_INIT
+
+
+#endif	/* _AT91SAM9260EK_H */
diff --git a/board/afeb9260-133/nandflash/afeb9260-133.h b/board/afeb9260-133/nandflash/afeb9260-133.h
new file mode 100644
index 0000000..414d30c
--- /dev/null
+++ b/board/afeb9260-133/nandflash/afeb9260-133.h
@@ -0,0 +1,151 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support  -  ROUSSET  -
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2006, Atmel Corporation
+
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the disclaimer below in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ * File Name           : at91sam9260ek.h
+ * Object              :
+ * Creation            : NLe Sep 28th 2006
+ *-----------------------------------------------------------------------------
+ */
+#ifndef _AFEB9260_133_H
+#define _AFEB9260_133_H
+#include	"spi.h"
+#include	"pll.h"
+
+/* ******************************************************************* */
+/* DataFlash Settings                                                  */
+/*                                                                     */
+/* ******************************************************************* */
+#define AT91C_BASE_SPI	AT91C_BASE_SPI0
+#define AT91C_ID_SPI	AT91C_ID_SPI0
+
+/* SPI CLOCK */
+#define AT91C_SPI_CLK 		 5000000
+/* AC characteristics */
+/* DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns */
+#define DATAFLASH_TCSS		(0x1a << 16)	/* 250ns min (tCSS) <=> 12/48000000 = 250ns */
+#define DATAFLASH_TCHS		(0x1 << 24)	/* 250ns min (tCSH) <=> (64*1+SCBR)/(2*48000000) */
+
+#define DF_CS_SETTINGS 		((SPI_MODE) | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) | ((MASTER_CLOCK / AT91C_SPI_CLK) << 8))
+
+
+/* ******************************************************************* */
+/* NandFlash Settings                                                  */
+/*                                                                     */
+/* ******************************************************************* */
+#define AT91C_SMARTMEDIA_BASE	0x40000000
+
+#define AT91_SMART_MEDIA_ALE    (1 << 21)	/* our ALE is AD21 */
+#define AT91_SMART_MEDIA_CLE    (1 << 22)	/* our CLE is AD22 */
+
+#define NAND_DISABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_SODR = AT91C_PIO_PC14;} while(0)
+#define NAND_ENABLE_CE() do { *(volatile unsigned int *)AT91C_PIOC_CODR = AT91C_PIO_PC14;} while(0)
+
+#define NAND_WAIT_READY() while (!(*(volatile unsigned int *)AT91C_PIOC_PDSR & AT91C_PIO_PC13))
+
+
+/* ******************************************************************** */
+/* SMC Chip Select 3 Timings for NandFlash for MASTER_CLOCK = 100000000.*/
+/* Micron 16bits 256Mb for MASTER_CLOCK = 100000000.			*/
+/* Please refer to SMC section in AT91SAM9261 datasheet to learn how 	*/
+/* to generate these values. 						*/
+/* ******************************************************************** */
+
+#define AT91C_SM_NWE_SETUP	(2 << 0)
+#define AT91C_SM_NCS_WR_SETUP	(2 << 8)
+#define AT91C_SM_NRD_SETUP	(2 << 16)
+#define AT91C_SM_NCS_RD_SETUP	(2 << 24)
+  
+#define AT91C_SM_NWE_PULSE 	(4 << 0)
+#define AT91C_SM_NCS_WR_PULSE	(4 << 8)
+#define AT91C_SM_NRD_PULSE	(4 << 16)
+#define AT91C_SM_NCS_RD_PULSE	(4 << 24)
+  
+#define AT91C_SM_NWE_CYCLE 	(8 << 0)
+#define AT91C_SM_NRD_CYCLE	(8 << 16)
+
+#define AT91C_SM_TDF	        (2 << 16)
+
+
+/* ******************************************************************** */
+/* SMC Chip Select 3 Timings for NandFlash for MASTER_CLOCK = 100000000.*/
+/* Micron 16bits 256Mb for MASTER_CLOCK = 100000000.			*/
+/* Please refer to SMC section in AT91SAM9261 datasheet to learn how 	*/
+/* to generate these values. 						*/
+/* ******************************************************************** */
+/*#define AT91C_SM_NWE_SETUP	(0 << 0)
+#define AT91C_SM_NCS_WR_SETUP	(0 << 8)
+#define AT91C_SM_NRD_SETUP	(0 << 16)
+#define AT91C_SM_NCS_RD_SETUP	(0 << 24)
+  
+#define AT91C_SM_NWE_PULSE 	(2 << 0)
+#define AT91C_SM_NCS_WR_PULSE	(3 << 8)
+#define AT91C_SM_NRD_PULSE	(2 << 16)
+#define AT91C_SM_NCS_RD_PULSE	(3 << 24)
+  
+#define AT91C_SM_NWE_CYCLE 	(3 << 0)
+#define AT91C_SM_NRD_CYCLE	(3 << 16)
+
+#define AT91C_SM_TDF	        (1 << 16)
+*/
+
+/* ******************************************************************* */
+/* BootStrap Settings                                                  */
+/*                                                                     */
+/* ******************************************************************* */
+#define MACH_TYPE      		0x44B       	/* AT91SAM9260-EK */
+
+#define IMG_ADDRESS 		0x20000		/* Image Address in NandFlash */
+
+#if	defined(IMG_SIZE)
+#warning			"IMG_SIZE redefined"
+#else
+#define	IMG_SIZE		0x30000		/* Image Size in NandFlash    */
+#endif
+
+#if	defined(JUMP_ADDR)
+#warning			"JUMP_ADDR redefined"
+#else
+#define JUMP_ADDR		0x23F00000	/* Final Jump Address 	      */
+#endif
+
+/* ******************************************************************* */
+/* Application Settings                                                */
+/* ******************************************************************* */
+#define CFG_DEBUG
+#undef CFG_DATAFLASH
+
+#define CFG_NANDFLASH
+#undef	NANDFLASH_SMALL_BLOCKS	/* NANDFLASH_LARGE_BLOCKS used instead */
+
+#define CFG_HW_INIT
+#define CFG_SDRAM
+
+#endif	/* _AT91SAM9260EK_H */
diff --git a/board/afeb9260-133/pll.h b/board/afeb9260-133/pll.h
new file mode 100644
index 0000000..907aaa0
--- /dev/null
+++ b/board/afeb9260-133/pll.h
@@ -0,0 +1,35 @@
+/* ******************************************************************* */
+/* PMC Settings                                                        */
+/*                                                                     */
+/* The main oscillator is enabled as soon as possible in the c_startup */
+/* and MCK is switched on the main oscillator.                         */
+/* PLL initialization is done later in the hw_init() function          */
+/* ******************************************************************* */
+#define PLL_LOCK_TIMEOUT	1000000
+
+#define PLLA_120MHz
+
+#ifdef PLLA_200MHz
+#define PLLA_SETTINGS	0x2060BF09
+#define MASTER_CLOCK		(198656000/2)
+#endif
+
+#ifdef PLLA_180MHz
+#define PLLA_SETTINGS	0x2125BF1E /* 180MHz */
+#define MASTER_CLOCK		(179999198/2) /* 180MHz MCK=90MHz */
+#endif
+
+#ifdef PLLA_120MHz
+//#define PLLA_SETTINGS	0x2125BF2d /* 120MHz */
+//#define MASTER_CLOCK		(119999322) /* 120MHz MCK=60MHz*/
+#define PLLA_SETTINGS	0x2125BF2d /* 120MHz */
+#define MASTER_CLOCK		(119999465/2) /* 120MHz MCK=60MHz*/
+#endif
+
+#if !defined(PLLA_180MHz) && !defined(PLLA_120MHz)
+#error Define PLLA frequency
+#endif
+#define PLLB_SETTINGS	0x10483F0E
+
+/* Switch MCK on PLLA output PCK = PLLA = 2 * MCK */
+#define MCKR_SETTINGS	(AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2)
-- 
1.5.6.5