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-rw-r--r--recipes/u-boot/files/bug20/bug-uboot.patch1173
-rw-r--r--recipes/u-boot/u-boot_git.bb2
2 files changed, 1175 insertions, 0 deletions
diff --git a/recipes/u-boot/files/bug20/bug-uboot.patch b/recipes/u-boot/files/bug20/bug-uboot.patch
new file mode 100644
index 0000000000..58c82a1274
--- /dev/null
+++ b/recipes/u-boot/files/bug20/bug-uboot.patch
@@ -0,0 +1,1173 @@
+diff --git a/Makefile b/Makefile
+index ed6156f..f0d42c5 100644
+--- a/Makefile
++++ b/Makefile
+@@ -3144,6 +3144,9 @@ omap3_zoom1_config : unconfig
+ omap3_zoom2_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3
+
++omap3_bug_config : unconfig
++ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 bug ti omap3
++
+ smdkc100_config: unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 smdkc100 samsung s5pc1xx
+
+diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
+index 7fe6275..a7e8593 100644
+--- a/board/ti/beagle/beagle.h
++++ b/board/ti/beagle/beagle.h
+@@ -255,8 +255,8 @@ const omap3_sysinfo sysinfo = {
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
+- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
++ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*GPIO_168*/\
++ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*GPIO_183*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+@@ -268,6 +268,7 @@ const omap3_sysinfo sysinfo = {
+ MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
+ MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
++>>>>>>> 6ca9da4d42aeb43df5ef29f7d0518009df583b2f
+ /* USB EHCI (port 2) */\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA2*/\
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) /*HSUSB2_DATA7*/\
+diff --git a/board/ti/bug/Makefile b/board/ti/bug/Makefile
+new file mode 100644
+index 0000000..0751e39
+--- /dev/null
++++ b/board/ti/bug/Makefile
+@@ -0,0 +1,47 @@
++#
++# (C) Copyright 2000, 2001, 2002
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = $(obj)lib$(BOARD).a
++
++COBJS := bug.o
++
++SRCS := $(COBJS:.o=.c)
++OBJS := $(addprefix $(obj),$(COBJS))
++
++$(LIB): $(obj).depend $(OBJS)
++ $(AR) $(ARFLAGS) $@ $(OBJS)
++
++clean:
++ rm -f $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak $(obj).depend
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
+diff --git a/board/ti/bug/bug.c b/board/ti/bug/bug.c
+new file mode 100644
+index 0000000..513a031
+--- /dev/null
++++ b/board/ti/bug/bug.c
+@@ -0,0 +1,133 @@
++/*
++ * (C) Copyright 2004-2008
++ * Texas Instruments, <www.ti.com>
++ *
++ * Author :
++ * Manikandan Pillai <mani.pillai@ti.com>
++ *
++ * Derived from Beagle Board and 3430 SDP code by
++ * Richard Woodruff <r-woodruff2@ti.com>
++ * Syed Mohammed Khasim <khasim@ti.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#include <common.h>
++#include <netdev.h>
++#include <asm/io.h>
++#include <asm/arch/mem.h>
++#include <asm/arch/mux.h>
++#include <asm/arch/sys_proto.h>
++#include <i2c.h>
++#include <asm/mach-types.h>
++#include "bug.h"
++
++/*
++ * Routine: board_init
++ * Description: Early hardware init.
++ */
++int board_init(void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
++ /* board id for Linux */
++ gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
++ /* boot param addr */
++ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
++
++ return 0;
++}
++
++/*
++ * Routine: misc_init_r
++ * Description: Init ethernet (done here so udelay works)
++ */
++int misc_init_r(void)
++{
++
++#ifdef CONFIG_DRIVER_OMAP34XX_I2C
++ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
++#endif
++
++#if defined(CONFIG_CMD_NET)
++ setup_net_chip();
++#endif
++
++ dieid_num_r();
++
++ return 0;
++}
++
++/*
++ * Routine: set_muxconf_regs
++ * Description: Setting up the configuration Mux registers specific to the
++ * hardware. Many pins need to be moved from protect to primary
++ * mode.
++ */
++void set_muxconf_regs(void)
++{
++ MUX_EVM();
++}
++
++/*
++ * Routine: setup_net_chip
++ * Description: Setting up the configuration GPMC registers specific to the
++ * Ethernet hardware.
++ */
++static void setup_net_chip(void)
++{
++ struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE;
++ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
++
++ /* Configure GPMC registers */
++ writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
++ writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
++ writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
++ writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
++ writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
++ writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
++ writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
++
++ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
++ writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
++ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
++ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
++ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
++ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
++ &ctrl_base->gpmc_nadv_ale);
++
++ /* Make GPIO 64 as output pin */
++ writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe);
++
++ /* Now send a pulse on the GPIO pin */
++ writel(GPIO0, &gpio3_base->setdataout);
++ udelay(1);
++ writel(GPIO0, &gpio3_base->cleardataout);
++ udelay(1);
++ writel(GPIO0, &gpio3_base->setdataout);
++}
++
++int board_eth_init(bd_t *bis)
++{
++ int rc = 0;
++#ifdef CONFIG_SMC911X
++ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
++#endif
++ return rc;
++}
+diff --git a/board/ti/bug/bug.h b/board/ti/bug/bug.h
+new file mode 100644
+index 0000000..9ec306e
+--- /dev/null
++++ b/board/ti/bug/bug.h
+@@ -0,0 +1,411 @@
++/*
++ * (C) Copyright 2008
++ * Nishanth Menon <menon.nishanth@gmail.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#ifndef _EVM_H_
++#define _EVM_H_
++
++const omap3_sysinfo sysinfo = {
++ DDR_DISCRETE,
++ "OMAP3 BUGBase 2.0 board",
++#if defined(CONFIG_ENV_IS_IN_ONENAND)
++ "OneNAND",
++#else
++ "NAND",
++#endif
++};
++
++static void setup_net_chip(void);
++
++/*
++ * IEN - Input Enable
++ * IDIS - Input Disable
++ * PTD - Pull type Down
++ * PTU - Pull type Up
++ * DIS - Pull type selection is inactive
++ * EN - Pull type selection is active
++ * M0 - Mode 0
++ * The commented string gives the final mux configuration for that pin
++ */
++#define MUX_EVM() \
++ /*SDRC*/\
++ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
++ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
++ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
++ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
++ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
++ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
++ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
++ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
++ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
++ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
++ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
++ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
++ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
++ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
++ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
++ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
++ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
++ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
++ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
++ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
++ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
++ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
++ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
++ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
++ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
++ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
++ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
++ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
++ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
++ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
++ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
++ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
++ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
++ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
++ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
++ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
++ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
++ /*GPMC*/\
++ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | EN | M4)) /*O_CAM_REN -- GPMC_A1*/ \
++ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | EN | M4)) /*O_SD2_EN -- GPMC_A2*/\
++ MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) /*SPI_UART_INT# -- GPMC_A3*/\
++ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | EN | M4)) /*O_CAM_PWRDN# -- GPMC_A4*/\
++ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | EN | M4)) /*O_CAM_RCLK_R/F# -- GPMC_A5*/\
++ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | EN | M4)) /*WIFI_RED -- GPMC_A6*/\
++ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | EN | M4)) /*WIFI_GREEN -- GPMC_A7*/\
++ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | EN | M4)) /*WIFI_BLUE -- GPMC_A8*/\
++ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | EN | M4)) /*SPI_UART_RST# -- GPMC_A9*/\
++ MUX_VAL(CP(GPMC_A10), (IEN | PTD | EN | M4)) /*WALL_PRESENT# -- GPMC_A10*/\
++ /**/\
++ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
++ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
++ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
++ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
++ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
++ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
++ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
++ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
++ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
++ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
++ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
++ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
++ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
++ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
++ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
++ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
++ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
++ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
++ /**/\
++ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | DIS | M4)) /*GPMC_nCS2*/\
++ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /*GPMC_nCS3*/\
++ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTD | DIS | M4)) /*GPMC_nCS4*/\
++ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4)) /*GPMC_nCS5*/\
++ MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | DIS | M4)) /*GPMC_nCS6*/\
++ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | DIS | M4)) /*GPMC_nCS7*/\
++ /**/\
++ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/ \
++ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
++ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
++ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
++ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) /*GPMC_nBE0_CLE*/\
++ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) /*GPMC_nBE1*/\
++ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
++ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
++ /**/\
++ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTD | EN | M4)) /*I2C_EXP_INT -- GPMC_WAIT1*/\
++ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTD | EN | M4)) /*BATT_LOW_GPIO -- GPIO_64*/\
++ MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTD | DIS | M4)) /*I2X_SW_RESET -- GPIO_65*/\
++ /*DSS*/\
++ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
++ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
++ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
++ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
++ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
++ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
++ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
++ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
++ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
++ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
++ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
++ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
++ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
++ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
++ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
++ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
++ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
++ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
++ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
++ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
++ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
++ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
++ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
++ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
++ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
++ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
++ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
++ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
++ /*CAMERA*/\
++ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
++ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
++ /**/\
++ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M4)) /*USB_SUSP -- CAM_XCLKA*/\
++ /**/\
++ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
++ /**/\
++ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_BUF_OE -- GPIO_98*/\
++ /* - CAM_RESET*/\
++ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
++ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
++ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
++ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
++ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
++ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
++ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
++ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
++ /**/\
++ MUX_VAL(CP(CAM_D8), (IDIS | PTD | DIS | M4)) /*DOCK_RESET -- CAM_D8*/\
++ MUX_VAL(CP(CAM_D9), (IDIS | PTD | DIS | M4)) /*MUTE -- CAM_D9*/\
++ MUX_VAL(CP(CAM_D10), (IDIS | PTD | DIS | M4)) /*DR_MSECURE -- CAM_D10*/\
++ MUX_VAL(CP(CAM_D11), (IEN | PTU | EN | M4)) /*SW_STATUS -- CAM_D11*/\
++ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M4)) /*USB_HPWR -- CAM_XCLKB*/\
++ MUX_VAL(CP(CAM_WEN), (IEN | PTU | EN | M4)) /*CAM_CK# -- GPIO_167*/\
++ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M4)) /*HOST_RESET -- CAM_STROBE*/\
++ /**/\
++ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
++ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
++ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
++ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
++ /*Audio Interface */\
++ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
++ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
++ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
++ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
++ /*Expansion card */\
++ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
++ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
++ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
++ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
++ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
++ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
++ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
++ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
++ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
++ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
++ /*Wireless LAN */\
++ MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) /*MMC2_CLK*/\
++ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
++ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
++ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
++ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
++ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
++ MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M1)) /*MMC2_DAT4*/\
++ MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M1)) /*MMC2_DAT5*/\
++ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M1)) /*MMC2_DAT6 */\
++ /**/\
++ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*DDR_TEMP_SENSE -- MMC2_DAT7*/\
++ /*Bluetooth*/\
++ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\
++ MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /*McBSP3_DR*/\
++ MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /*McBSP3_CLKX */\
++ MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /*McBSP3_FSX*/\
++ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
++ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
++ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
++ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /*UART2_RX*/\
++ /*Modem Interface */\
++ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
++ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
++ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
++ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
++ MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
++ /* - LCD_INI*/\
++ MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
++ /* - LCD_ENVDD */\
++ MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
++ /* - LCD_QVGA/nVGA */\
++ MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
++ /* - LCD_RESB */\
++ MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*BT_RESET -- MCBSP1_CLKR */\
++ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTD | DIS | M4)) /*WIFI_RESET -- MCBSP1_FSR*/\
++ /**/\
++ MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) /*MCBSP1_DX*/\
++ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /*MCBSP1_DR*/\
++ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*MCBSP_CLKS */\
++ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*MCBSP1_FSX*/\
++ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*MCBSP1_CLKX */\
++ /*Serial Interface*/\
++ MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) /*WLBT_IRQ_WAKE -- UART3_CTS_RCTX*/\
++ MUX_VAL(CP(UART3_RTS_SD), (IEN | PTU | EN | M4)) /*BAT_CHRG -- UART3_RTS_SD */\
++ /**/\
++ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
++ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
++ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
++ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
++ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
++ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
++ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
++ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
++ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
++ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
++ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
++ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
++ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
++ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
++ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
++ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
++ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
++ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
++ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
++ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
++ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
++ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
++ /**/\
++ MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4)) /*SD2_CD# -- HDQ_SIO*/\
++ /**/\
++ MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
++ MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
++ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
++ /**/\
++ MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTD | DIS | M0)) /*SPI_UART_CS# -- McSPI1_CS0*/\
++ /**/\
++ MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M3)) /*MMC3_CMD*/\
++ /* TS_PEN_IRQ */\
++ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M3)) /*MMC3_CLK*/\
++ /* - LAN_INTR*/\
++ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) /*HSUSB2_DAT2*/\
++ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) /*HSUSB2_DAT7*/\
++ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) /*HSUSB2_DAT4*/\
++ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) /*HSUSB2_DAT5*/\
++ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) /*HSUSB2_DAT6*/\
++ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) /*HSUSB2_DAT3*/\
++ /*Control and debug */\
++ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
++ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
++ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
++ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
++ /* - PEN_IRQ */\
++ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
++ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
++ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
++ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
++ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
++ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
++ /* - VIO_1V8*/\
++ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
++ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
++ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) /*SYS_CLKOUT2*/\
++ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
++ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
++ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
++ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
++ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
++ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
++ /**/\
++ MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M4)) /*M4_PRESENT -- ETK_CLK*/\
++ MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M4)) /*PIM4_INT -- ETK_CTL*/\
++ MUX_VAL(CP(ETK_D0_ES2 ), (IEN | PTU | EN | M4)) /*M2_PRESENT -- ETK_D0*/\
++ MUX_VAL(CP(ETK_D1_ES2 ), (IEN | PTU | EN | M4)) /*PIM2_INT -- ETK_D1*/\
++ MUX_VAL(CP(ETK_D2_ES2 ), (IEN | PTU | EN | M4)) /*M1_PRESENT -- ETK_D2*/\
++ /**/\
++ MUX_VAL(CP(ETK_D3_ES2 ), (IEN | PTU | EN | M2)) /*SD3_DAT3 -- ETK_D3*/\
++ MUX_VAL(CP(ETK_D4_ES2 ), (IEN | PTU | EN | M2)) /*SD3_DAT0 -- ETK_D4*/\
++ MUX_VAL(CP(ETK_D5_ES2 ), (IEN | PTU | EN | M2)) /*SD3_DAT1 -- ETK_D5*/\
++ MUX_VAL(CP(ETK_D6_ES2 ), (IEN | PTU | EN | M2)) /*SD3_DAT2 -- ETK_D6*/\
++ /**/\
++ MUX_VAL(CP(ETK_D7_ES2 ), (IEN | PTU | EN | M4)) /*PIM1-INT -- ETK_D7*/\
++ MUX_VAL(CP(ETK_D8_ES2 ), (IEN | PTU | EN | M4)) /*M3_PRESENT -- ETK_D8*/\
++ MUX_VAL(CP(ETK_D9_ES2 ), (IEN | PTU | EN | M4)) /*PIM3_INT -- ETK_D9*/\
++ /**/\
++ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\
++ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\
++ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/\
++ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_NXT*/\
++ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DAT0*/\
++ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DAT1*/\
++ /*Die to Die */\
++ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
++ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
++ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
++ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
++ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
++ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
++ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
++ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
++ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
++ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
++ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
++ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
++ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
++ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
++ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
++ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
++ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
++ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
++ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
++ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
++ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
++ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
++ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
++ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
++ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
++ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
++ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
++ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
++ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
++ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
++ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
++ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
++ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
++ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
++ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
++ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
++ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
++ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
++ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
++ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
++ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
++ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
++ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
++ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
++ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
++ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
++ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
++ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
++ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
++ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
++ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
++ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
++ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
++ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
++ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
++ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
++ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
++ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
++ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
++ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
++ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
++ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
++ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
++ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
++ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/\
++
++#endif
+diff --git a/board/ti/bug/config.mk b/board/ti/bug/config.mk
+new file mode 100644
+index 0000000..4d873eb
+--- /dev/null
++++ b/board/ti/bug/config.mk
+@@ -0,0 +1,33 @@
++#
++# (C) Copyright 2006 - 2008
++# Texas Instruments, <www.ti.com>
++#
++# EVM uses OMAP3 (ARM-CortexA8) cpu
++# see http://www.ti.com/ for more information on Texas Instruments
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++# Physical Address:
++# 8000'0000 (bank0)
++# A000/0000 (bank1)
++# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
++# (mem base + reserved)
++
++# For use with external or internal boots.
++TEXT_BASE = 0x80e80000
+diff --git a/drivers/mmc/omap3_mmc.c b/drivers/mmc/omap3_mmc.c
+index 96c0e65..d8643b8 100644
+--- a/drivers/mmc/omap3_mmc.c
++++ b/drivers/mmc/omap3_mmc.c
+@@ -507,9 +507,11 @@ unsigned char configure_mmc(mmc_card_data *mmc_card_cur)
+ unsigned long mmc_bread(int dev_num, unsigned long blknr, lbaint_t blkcnt,
+ void *dst)
+ {
++ //printf("mmc_bread...\n");
+ omap_mmc_read_sect(blknr, (blkcnt * MMCSD_SECTOR_SIZE), &cur_card_data,
+ (unsigned long *) dst);
+- return 1;
++ //return 1;
++ return blkcnt;
+ }
+
+ int mmc_legacy_init(int verbose)
+@@ -517,6 +519,7 @@ int mmc_legacy_init(int verbose)
+ if (configure_mmc(&cur_card_data) != 1)
+ return 1;
+
++ printf("mmc_legacy_init...\n");
+ mmc_blk_dev.if_type = IF_TYPE_MMC;
+ mmc_blk_dev.part_type = PART_TYPE_DOS;
+ mmc_blk_dev.dev = 0;
+diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
+index 4fe3bd8..1f3a633 100644
+--- a/include/configs/omap3_beagle.h
++++ b/include/configs/omap3_beagle.h
+@@ -232,6 +232,8 @@
+ */
+ #define V_PROMPT "OMAP3 beagleboard.org # "
+
++#define CONFIG_CMDLINE_EDITING
++
+ #define CONFIG_SYS_LONGHELP /* undef to save memory */
+ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+diff --git a/include/configs/omap3_bug.h b/include/configs/omap3_bug.h
+new file mode 100644
+index 0000000..30e1d26
+--- /dev/null
++++ b/include/configs/omap3_bug.h
+@@ -0,0 +1,432 @@
++/*
++ * (C) Copyright 2006
++ * Texas Instruments.
++ * Richard Woodruff <r-woodruff2@ti.com>
++ * Syed Mohammed Khasim <x0khasim@ti.com>
++ *
++ * Configuration settings for the 3530 TI EVM3530 board.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++#include <asm/sizes.h>
++
++/* ============================================================================
++ * High Level Configuration Options
++ * ============================================================================
++ */
++#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
++#define CONFIG_OMAP 1 /* in a TI OMAP core */
++#define CONFIG_OMAP34XX 1 /* which is a 34XX */
++#define CONFIG_OMAP3430 1 /* which is in a 3430 */ */
++#define CONFIG_OMAP3BB2 1 /* working with BUG BASE 2.0 */
++
++#define ES_2_0 1
++
++#include <asm/arch/cpu.h> /* Get chip and board defs */
++#include <asm/arch/omap3.h>
++
++/*
++ * Display CPU and Board information
++ */
++#define CONFIG_DISPLAY_CPUINFO 1
++#define CONFIG_DISPLAY_BOARDINFO 1
++
++/* Clock Defines */
++#define V_OSCK 26000000 /* Clock output from T2 */
++#define V_SCLK (V_OSCK >> 1)
++
++#undef CONFIG_USE_IRQ /* No support for IRQs */
++#define CONFIG_MISC_INIT_R
++
++#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
++#define CONFIG_SETUP_MEMORY_TAGS 1
++#define CONFIG_INITRD_TAG 1
++#define CONFIG_REVISION_TAG 1
++
++/* ----------------------------------------------------------------------------
++ * OFF Mode pad configuration
++ * ----------------------------------------------------------------------------
++ */
++#define CONFIG_OFF_PADCONF 1
++
++
++/* ============================================================================
++ * Commands
++ * ============================================================================
++ */
++
++#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
++
++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
++#include <config_cmd_default.h>
++
++#define CONFIG_CMD_EXT2 /* EXT2 Support */
++#define CONFIG_CMD_FAT /* FAT support */
++#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
++
++#define CONFIG_CMD_I2C /* I2C serial bus support */
++#define CONFIG_CMD_MMC /* MMC support */
++/*#define CONFIG_CMD_ONENAND /* ONENAND support */
++#define CONFIG_CMD_NAND
++#define CONFIG_CMD_DHCP
++#define CONFIG_CMD_PING
++
++#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
++#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
++#undef CONFIG_CMD_IMI /* iminfo */
++#undef CONFIG_CMD_IMLS /* List all found images */
++
++/* ============================================================================
++ * Hardware drivers
++ * ============================================================================
++ */
++
++/*
++ * TWL4030
++ */
++#define CONFIG_TWL4030_POWER 1
++
++/* ----------------------------------------------------------------------------
++ * NS16550
++ * ----------------------------------------------------------------------------
++ */
++#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
++
++#define CONFIG_SYS_NS16550
++#define CONFIG_SYS_NS16550_SERIAL
++#define CONFIG_SYS_NS16550_REG_SIZE (-4)
++#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
++
++#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
++#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
++
++
++/* ----------------------------------------------------------------------------
++ * Serial Console
++ * ----------------------------------------------------------------------------
++ */
++#define CONFIG_SERIAL1 3 /* UART1 */
++#define CONFIG_CONS_INDEX 3
++#define CONFIG_BAUDRATE 115200
++#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
++
++#define CONFIG_MMC 1
++#define CONFIG_OMAP3_MMC 1
++#define CONFIG_DOS_PARTITION 1
++/* ----------------------------------------------------------------------------
++ * SMSC9115 Ethernet from SMSC9118 family
++ * ----------------------------------------------------------------------------
++ */
++#undef CONFIG_CMD_NET
++#ifdef CONFIG_CMD_NET
++#define CONFIG_NET_MULTI
++#define CONFIG_SMC911X
++#define CONFIG_SMC911X_32_BIT
++#define CONFIG_SMC911X_BASE 0x2C000000
++
++#endif /* (CONFIG_COMMANDS & CONFIG_CMD_NET) */
++
++/* ----------------------------------------------------------------------------
++ * I2C
++ * ----------------------------------------------------------------------------
++ */
++#ifdef CONFIG_CMD_I2C
++
++#define CONFIG_DRIVER_OMAP34XX_I2C 1
++
++#define CONFIG_SYS_I2C_SPEED 100
++#define CONFIG_SYS_I2C_SLAVE 1
++#define CONFIG_SYS_I2C_BUS 0
++#define CONFIG_SYS_I2C_BUS_SELECT 1
++
++#endif /* (CONFIG_COMMANDS & CONFIG_CMD_I2C) */
++
++/* ----------------------------------------------------------------------------
++ * OneNAND & NAND
++ * ----------------------------------------------------------------------------
++ */
++#define NAND_MAX_CHIPS 1
++#define CONFIG_NAND_OMAP_GPMC
++#define GPMC_NAND_ECC_LP_x16_LAYOUT
++#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
++#define ONENAND_DEBUG
++
++#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address to access nand*/
++#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address to access nand at CS0*/
++
++
++#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
++#define SECTORSIZE 512
++
++#define NAND_ALLOW_ERASE_ALL
++#define ADDR_COLUMN 1
++#define ADDR_PAGE 2
++#define ADDR_COLUMN_PAGE 3
++
++#define NAND_ChipID_UNKNOWN 0x00
++#define NAND_MAX_FLOORS 1
++#define NAND_MAX_CHIPS 1
++#define NAND_NO_RB 1
++#define CONFIG_SYS_NAND_WP
++
++/* ----------------------------------------------------------------------------
++ * PISMO
++ * ----------------------------------------------------------------------------
++ */
++#define PISMO1_NAND_SIZE GPMC_SIZE_128M
++#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
++#define DBG_MPDB_SIZE GPMC_SIZE_16M
++
++#define CONFIG_SYS_MAX_FLASH_BANKS 2
++#define CONFIG_SYS_MAX_FLASH_SECT (520)
++
++#define CONFIG_SYS_FLASH_BASE boot_flash_base
++#define PHYS_FLASH_SECT_SIZE boot_flash_sec
++
++#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
++#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */
++
++
++/* ----------------------------------------------------------------------------
++ * Flash
++ * ----------------------------------------------------------------------------
++ */
++#define CONFIG_SYS_NO_FLASH 1 /* Disable Flash support */
++
++/* ============================================================================
++ * Miscellaneous configurable options
++ * ============================================================================
++ */
++/* ----------------------------------------------------------------------------
++ * SDRAM Bank Allocation method
++ * ----------------------------------------------------------------------------
++ */
++#define SDRC_R_B_C 1
++
++/* ----------------------------------------------------------------------------
++ * Physical Memory Map
++ * (CS1 may or may not be populated)
++ * ----------------------------------------------------------------------------
++ */
++#define CONFIG_NR_DRAM_BANKS 2
++
++#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
++#define PHYS_SDRAM_1_SIZE SZ_128M /* At least 128 megs */
++
++#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
++
++/* ----------------------------------------------------------------------------
++ * Range for memory test
++ * ----------------------------------------------------------------------------
++ */
++#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
++#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0+0x01F00000)
++
++
++#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
++
++
++/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
++ * 32KHz clk, or from external sig. This rate is divided by a local divisor.
++ */
++
++#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
++#define CONFIG_SYS_PTV 2 /* 2^(pvt+1) */
++#define CONFIG_SYS_HZ 1000
++
++/* ----------------------------------------------------------------------------
++ * JFFS2
++ * (OMAP3 EVM supports JFFS2 by default)
++ * ----------------------------------------------------------------------------
++ */
++#define CONFIG_SYS_JFFS2_MEM_NAND
++
++#if 0
++#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS /* use flash_info[2] */
++#define CONFIG_SYS_JFFS2_NUM_BANKS 1
++#endif
++
++#define JFFS2_BOOT_DEFAULTS TRUE
++
++
++/* ----------------------------------------------------------------------------
++ * Monitor
++ * ----------------------------------------------------------------------------
++ */
++#define CONFIG_SYS_MONITOR_BASE ONENAND_MAP /* At start of flash */
++
++#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
++
++
++/* ============================================================================
++ * Environment
++ * ============================================================================
++ */
++#define ENV_IS_VARIABLE 1
++
++#define CONFIG_ENV_IS_IN_NAND 1
++//#define CONFIG_ENV_IS_IN_ONENAND 1
++
++#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
++#define CONFIG_ENV_OFFSET boot_flash_off
++#define CONFIG_ENV_ADDR boot_flash_env_addr
++
++/* ----------------------------------------------------------------------------
++ * Allow environment overwrite
++ * ----------------------------------------------------------------------------
++ */
++#define CONFIG_ENV_OVERWRITE
++
++/* ----------------------------------------------------------------------------
++ * Size of environment
++ * ----------------------------------------------------------------------------
++ */
++#define CONFIG_ENV_SIZE SZ_128K
++
++/* ----------------------------------------------------------------------------
++ * Size of malloc() pool
++ * ----------------------------------------------------------------------------
++ */
++#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
++
++/* ----------------------------------------------------------------------------
++ * Size of global data arra
++ * ----------------------------------------------------------------------------
++ */
++#define CONFIG_SYS_GBL_DATA_SIZE 128
++
++/* ----------------------------------------------------------------------------
++ * Prompt
++ * ----------------------------------------------------------------------------
++ */
++#define V_PROMPT "BUGBASE2 # "
++#define CONFIG_SYS_PROMPT V_PROMPT
++#define CONFIG_CMDLINE_EDITING
++
++/* ----------------------------------------------------------------------------
++ * Help
++ * (Undef to save memory)
++ * ----------------------------------------------------------------------------
++ */
++#define CONFIG_SYS_LONGHELP
++
++/* ----------------------------------------------------------------------------
++ * Default load address
++ * ----------------------------------------------------------------------------
++ */
++#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
++
++/* ----------------------------------------------------------------------------
++ * Buffers
++ * ----------------------------------------------------------------------------
++ */
++#define CONFIG_SYS_CBSIZE 512 /* Console I/O */
++#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print */
++#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument */
++
++/* ----------------------------------------------------------------------------
++ * Stack sizes
++ * Used to set stack sizes in start.S
++ * ----------------------------------------------------------------------------
++ */
++#define CONFIG_STACKSIZE SZ_128K /* Regular stack */
++
++#ifdef CONFIG_USE_IRQ
++#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
++#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
++#endif
++
++/* ----------------------------------------------------------------------------
++ * Boot options
++ * ----------------------------------------------------------------------------
++ */
++
++#define CONFIG_PREBOOT /* enable preboot variable */
++
++#define CONFIG_BOOTDELAY 3
++
++#define CONFIG_BOOTCOMMAND "run mmcboot"
++
++#define CONFIG_AUTO_COMPLETE 1 /* TBD */
++
++#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ /* TBD */
++
++
++#ifdef NFS_BOOT_DEFAULTS
++
++#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/user/rootfs ip=dhcp"
++
++#elif defined(JFFS2_BOOT_DEFAULTS)
++
++#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/mtdblock4 rw rootfstype=jffs2"
++
++#else
++
++#define CONFIG_BOOTARGS "console=ttyS2,115200n8 root=/dev/mmcblk0p1 rw rootwait"
++
++#endif
++
++#define CONFIG_EXTRA_ENV_SETTINGS \
++ "console=ttyS2,115200n8\0" \
++ "mmcboot=mmc init;ext2load mmc 0:1 0x80000000 /boot/uImage;run mmcargs;bootm 0x80000000\0"\
++ "mmcargs=setenv bootargs console=${console} root=/dev/mmcblk0p1 rw rootwait rootdelay=1 kgdboc=${console} usbcore.autosuspend=-1\0" \
++
++#define CONFIG_ETHADDR aa:bb:cc:dd:ee:ff
++
++#define CONFIG_GATEWAYIP 192.168.1.1
++#define CONFIG_SERVERIP 192.168.1.20
++#define CONFIG_IPADDR 192.168.1.10
++
++#define CONFIG_NETMASK 255.255.255.0
++
++
++#ifndef __ASSEMBLY__
++extern struct gpmc *gpmc_cfg;
++extern volatile unsigned int boot_flash_env_addr;
++extern unsigned int nand_cs_base;
++extern unsigned int boot_flash_base;
++extern unsigned int boot_flash_off;
++extern unsigned int boot_flash_sec;
++extern unsigned int boot_flash_type;
++#endif /* __ASSEMBLY__ */
++
++#define READ_NAND(adr) __raw_readw((nand_cs_base + GPMC_NAND_DAT))
++
++#define WRITE_NAND_COMMAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_CMD))
++#define WRITE_NAND_ADDRESS(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_ADR))
++#define WRITE_NAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_DAT))
++
++#define NAND_WP_OFF() do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0)
++#define NAND_WP_ON() do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0)
++
++#ifdef CFG_NAND_LEGACY
++#define NAND_CTL_CLRALE(nandptr)
++#define NAND_CTL_SETALE(nandptr)
++#define NAND_CTL_CLRCLE(nandptr)
++#define NAND_CTL_SETCLE(nandptr)
++#endif /* CFG_NAND_LEGACY */
++
++#define NAND_DISABLE_CE(nand)
++#define NAND_ENABLE_CE(nand)
++#define NAND_WAIT_READY(nand) udelay(10)
++
++#endif /* __CONFIG_BUGBASE2_H */
+diff --git a/lib_arm/board.c b/lib_arm/board.c
+index e148739..f3c58ea 100644
+--- a/lib_arm/board.c
++++ b/lib_arm/board.c
+@@ -291,7 +291,6 @@ void start_armboot (void)
+ hang ();
+ }
+ }
+-
+ /* armboot_start is defined in the board-specific linker script */
+ mem_malloc_init (_armboot_start - CONFIG_SYS_MALLOC_LEN,
+ CONFIG_SYS_MALLOC_LEN);
diff --git a/recipes/u-boot/u-boot_git.bb b/recipes/u-boot/u-boot_git.bb
index 90ca78d386..cc0c5327ef 100644
--- a/recipes/u-boot/u-boot_git.bb
+++ b/recipes/u-boot/u-boot_git.bb
@@ -14,9 +14,11 @@ SRCREV_palmpre = "6b8edfde22acc574b5532e9f086e6a7287a9bc78"
SRCREV_cm-t35 = "3c014f1586d5bfe30dca7549396915c83f31cd30"
SRCREV_mpc8641-hpcn = "f20393c5e787b3776c179d20f82a86bda124d651"
SRCREV_p2020ds = "f20393c5e787b3776c179d20f82a86bda124d651"
+SRCREV_bug20 = "169a4c804dbaf11facb041b1333d394c6ceb8d68"
SRC_URI_append_afeb9260 = " file://AFEB9260-network-fix.patch"
SRC_URI_append_afeb9260-180 = " file://AFEB9260-network-fix.patch"
SRC_URI_append_cm-t35 = "file://cm-t35/cm-t35.patch"
+SRC_URI_append_bug20 = "file://bug-uboot.patch"
SRC_URI_beagleboard = "git://www.denx.de/git/u-boot.git;protocol=git \
file://0001-OMAP3-enable-i2c-bus-switching-for-Beagle-and-Overo.patch \
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 13:33:09 +0000