diff options
Diffstat (limited to 'recipes')
16 files changed, 0 insertions, 5748 deletions
diff --git a/recipes/u-boot/u-boot-git/omap3evm/0001-Changes-for-making-a-NAND-build.patch b/recipes/u-boot/u-boot-git/omap3evm/0001-Changes-for-making-a-NAND-build.patch deleted file mode 100644 index b762ac0f1e..0000000000 --- a/recipes/u-boot/u-boot-git/omap3evm/0001-Changes-for-making-a-NAND-build.patch +++ /dev/null @@ -1,50 +0,0 @@ -From d58014b0e26652eac04f9799e14640854f7885a8 Mon Sep 17 00:00:00 2001 -From: Manikandan Pillai <mani.pillai@ti.com> -Date: Tue, 7 Apr 2009 14:26:41 +0530 -Subject: [PATCH 01/16] Changes for making a NAND build. - ---- - include/configs/omap3_evm.h | 7 +++++-- - 1 files changed, 5 insertions(+), 2 deletions(-) - -diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h -index f4498a9..6283d59 100644 ---- a/include/configs/omap3_evm.h -+++ b/include/configs/omap3_evm.h -@@ -106,7 +106,7 @@ - - #define CONFIG_CMD_I2C /* I2C serial bus support */ - #define CONFIG_CMD_MMC /* MMC support */ --#define CONFIG_CMD_ONENAND /* ONENAND support */ -+#define CONFIG_CMD_NAND /* NAND support */ - #define CONFIG_CMD_DHCP - #define CONFIG_CMD_PING - -@@ -125,12 +125,15 @@ - /* - * Board NAND Info. - */ -+#define CONFIG_NAND_OMAP_GPMC - #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ - /* to access nand */ - #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access */ - /* nand at CS0 */ - -+#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 -+ - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ - /* NAND devices */ - #define SECTORSIZE 512 -@@ -271,7 +274,7 @@ - #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - --#define CONFIG_ENV_IS_IN_ONENAND 1 -+#define CONFIG_ENV_IS_IN_NAND 1 - #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ - #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ - --- -1.6.2.4 - diff --git a/recipes/u-boot/u-boot-git/omap3evm/0002-Fix-for-NFS-boot-for-OMAP3-EVM.patch b/recipes/u-boot/u-boot-git/omap3evm/0002-Fix-for-NFS-boot-for-OMAP3-EVM.patch deleted file mode 100644 index 243f175728..0000000000 --- a/recipes/u-boot/u-boot-git/omap3evm/0002-Fix-for-NFS-boot-for-OMAP3-EVM.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 57a0438b9f70bb3e98a20773134b17ef33e266b9 Mon Sep 17 00:00:00 2001 -From: Manikandan Pillai <mani.pillai@ti.com> -Date: Tue, 7 Apr 2009 14:27:31 +0530 -Subject: [PATCH 02/16] Fix for NFS boot for OMAP3 EVM - -The eth_halt() function has been modified to remove the -chip reset and instead stop the transmit/receive from the device. ---- - drivers/net/smc911x.c | 23 ++++++++++++++++++++++- - 1 files changed, 22 insertions(+), 1 deletions(-) - -diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c -index 1ded8f0..2f0852e 100644 ---- a/drivers/net/smc911x.c -+++ b/drivers/net/smc911x.c -@@ -116,6 +116,27 @@ static int smc911x_phy_reset(void) - return 0; - } - -+static void smc911x_shutdown(void) -+{ -+ unsigned cr; -+ -+ /* Turn of Rx and TX */ -+ cr = smc911x_get_mac_csr(MAC_CR); -+ cr &= ~(MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS); -+ smc911x_set_mac_csr(MAC_CR, cr); -+ -+ /* Stop Transmission */ -+ cr = smc911x_get_mac_csr(TX_CFG); -+ cr &= ~(TX_CFG_STOP_TX); -+ smc911x_set_mac_csr(TX_CFG, cr); -+ /* Stop receiving packets */ -+ cr = smc911x_get_mac_csr(RX_CFG); -+ cr &= ~(RX_CFG_RXDOFF); -+ smc911x_set_mac_csr(RX_CFG, cr); -+ -+} -+ -+ - static void smc911x_phy_configure(void) - { - int timeout; -@@ -224,7 +245,7 @@ int eth_send(volatile void *packet, int length) - - void eth_halt(void) - { -- smc911x_reset(); -+ smc911x_shutdown(); - } - - int eth_rx(void) --- -1.6.2.4 - diff --git a/recipes/u-boot/u-boot-git/omap3evm/0003-OMAP3-timer-handling-to-1ms-tick-and-CONFIG_SYS_HZ-t.patch b/recipes/u-boot/u-boot-git/omap3evm/0003-OMAP3-timer-handling-to-1ms-tick-and-CONFIG_SYS_HZ-t.patch deleted file mode 100644 index 75f7ef230a..0000000000 --- a/recipes/u-boot/u-boot-git/omap3evm/0003-OMAP3-timer-handling-to-1ms-tick-and-CONFIG_SYS_HZ-t.patch +++ /dev/null @@ -1,277 +0,0 @@ -From 13fc02c66aa4cc1c5653a4987fdddce63810a7e9 Mon Sep 17 00:00:00 2001 -From: Manikandan Pillai <mani.pillai@ti.com> -Date: Tue, 7 Apr 2009 14:28:05 +0530 -Subject: [PATCH 03/16] OMAP3 timer handling to 1ms tick and CONFIG_SYS_HZ to 1000. - -Clean up macros and comments. ---- - cpu/arm_cortexa8/omap3/interrupts.c | 81 ++++++++++------------------------ - examples/Makefile | 2 +- - include/configs/omap3_beagle.h | 11 +++-- - include/configs/omap3_evm.h | 13 +++--- - include/configs/omap3_overo.h | 10 ++-- - include/configs/omap3_pandora.h | 11 ++--- - include/configs/omap3_zoom1.h | 11 ++--- - 7 files changed, 52 insertions(+), 87 deletions(-) - -diff --git a/cpu/arm_cortexa8/omap3/interrupts.c b/cpu/arm_cortexa8/omap3/interrupts.c -index 9e9817d..b99e284 100644 ---- a/cpu/arm_cortexa8/omap3/interrupts.c -+++ b/cpu/arm_cortexa8/omap3/interrupts.c -@@ -169,7 +169,16 @@ static ulong timestamp; - static ulong lastinc; - static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE; - --/* nothing really to do with interrupts, just starts up a counter. */ -+/* -+ * Nothing really to do with interrupts, just starts up a counter. -+ * We run the counter with 13MHz, divided by 8, resulting in timer -+ * frequency of 1.625MHz. With 32bit counter register, counter -+ * overflows in ~44min -+ */ -+ -+/* 13MHz / 8 = 1.625MHz */ -+#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PVT)) -+ - int interrupt_init(void) - { - /* start the counter ticking up, reload value on overflow */ -@@ -204,78 +213,38 @@ void set_timer(ulong t) - /* delay x useconds AND perserve advance timstamp value */ - void udelay(unsigned long usec) - { -- ulong tmo, tmp; -- -- /* if "big" number, spread normalization to seconds */ -- if (usec >= 1000) { -- /* if "big" number, spread normalization to seconds */ -- tmo = usec / 1000; -- /* find number of "ticks" to wait to achieve target */ -- tmo *= CONFIG_SYS_HZ; -- tmo /= 1000; /* finish normalize. */ -- } else {/* else small number, don't kill it prior to HZ multiply */ -- tmo = usec * CONFIG_SYS_HZ; -- tmo /= (1000 * 1000); -- } -- -- tmp = get_timer(0); /* get current timestamp */ -- /* if setting this forward will roll time stamp */ -- if ((tmo + tmp + 1) < tmp) -- /* reset "advancing" timestamp to 0, set lastinc value */ -- reset_timer_masked(); -- else -- tmo += tmp; /* else, set advancing stamp wake up time */ -- while (get_timer_masked() < tmo) /* loop till event */ -- /*NOP*/; -+ ulong tmo, endtime; -+ -+ tmo = usec * (TIMER_CLOCK / CONFIG_SYS_HZ); -+ tmo /= 1000; -+ -+ endtime = readl(&timer_base->tcrr) + tmo; -+ -+ while (readl(&timer_base->tcrr) < endtime); - } - - void reset_timer_masked(void) - { - /* reset time, capture current incrementer value time */ -- lastinc = readl(&timer_base->tcrr); -+ lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); - timestamp = 0; /* start "advancing" time stamp from 0 */ - } - - ulong get_timer_masked(void) - { -- ulong now = readl(&timer_base->tcrr); /* current tick value */ -+ /* current tick value */ -+ ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); - - if (now >= lastinc) /* normal mode (non roll) */ - /* move stamp fordward with absoulte diff ticks */ - timestamp += (now - lastinc); - else /* we have rollover of incrementer */ -- timestamp += (0xFFFFFFFF - lastinc) + now; -+ timestamp += ((0xFFFFFFFF / (TIMER_CLOCK / CONFIG_SYS_HZ)) -+ - lastinc) + now; - lastinc = now; - return timestamp; - } - --/* waits specified delay value and resets timestamp */ --void udelay_masked(unsigned long usec) --{ -- ulong tmo; -- ulong endtime; -- signed long diff; -- -- /* if "big" number, spread normalization to seconds */ -- if (usec >= 1000) { -- /* start to normalize for usec to ticks per sec */ -- tmo = usec / 1000; -- /* find number of "ticks" to wait to achieve target */ -- tmo *= CONFIG_SYS_HZ; -- tmo /= 1000; /* finish normalize. */ -- } else { /* else small number, */ -- /* don't kill it prior to HZ multiply */ -- tmo = usec * CONFIG_SYS_HZ; -- tmo /= (1000 * 1000); -- } -- endtime = get_timer_masked() + tmo; -- -- do { -- ulong now = get_timer_masked(); -- diff = endtime - now; -- } while (diff >= 0); --} -- - /* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. -@@ -291,7 +260,5 @@ unsigned long long get_ticks(void) - */ - ulong get_tbclk(void) - { -- ulong tbclk; -- tbclk = CONFIG_SYS_HZ; -- return tbclk; -+ return CONFIG_SYS_HZ; - } -diff --git a/examples/Makefile b/examples/Makefile -index dbcfa92..d2e811a 100644 ---- a/examples/Makefile -+++ b/examples/Makefile -@@ -33,7 +33,7 @@ ifeq ($(ARCH),arm) - ifeq ($(BOARD),omap2420h4) - LOAD_ADDR = 0x80300000 - else --ifeq ($(CPU),omap3) -+ifeq ($(SOC),omap3) - LOAD_ADDR = 0x80300000 - else - LOAD_ADDR = 0xc100000 -diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h -index 9057606..2f30783 100644 ---- a/include/configs/omap3_beagle.h -+++ b/include/configs/omap3_beagle.h -@@ -220,14 +220,15 @@ - /* load address */ - - /* -- * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by -- * 32KHz clk, or from external sig. This rate is divided by a local divisor. -+ * OMAP3 has 12 GP timers, they can be driven by the system clock -+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). -+ * This rate is divided by a local divisor. - */ --#define V_PVT 7 - - #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) --#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ --#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) -+#define CONFIG_SYS_PVT 2 /* Divisor: 2^(PVT+1) => 8 */ -+#define CONFIG_SYS_HZ 1000 -+ - - /*----------------------------------------------------------------------- - * Stack sizes -diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h -index 6283d59..fb8a424 100644 ---- a/include/configs/omap3_evm.h -+++ b/include/configs/omap3_evm.h -@@ -222,14 +222,13 @@ - /* address */ - - /* -- * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by -- * 32KHz clk, or from external sig. This rate is divided by a local divisor. -+ * OMAP3 has 12 GP timers, they can be driven by the system clock -+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). -+ * This rate is divided by a local divisor. - */ --#define V_PVT 7 -- --#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 --#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ --#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) -+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -+#define CONFIG_SYS_PVT 2 /* Divisor: 2^(PVT+1) => 8 */ -+#define CONFIG_SYS_HZ 1000 - - /*----------------------------------------------------------------------- - * Stack sizes -diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h -index dee0417..45e5478 100644 ---- a/include/configs/omap3_overo.h -+++ b/include/configs/omap3_overo.h -@@ -213,14 +213,14 @@ - /* address */ - - /* -- * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by -- * 32KHz clk, or from external sig. This rate is divided by a local divisor. -+ * OMAP3 has 12 GP timers, they can be driven by the system clock -+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). -+ * This rate is divided by a local divisor. - */ --#define V_PVT 7 - - #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) --#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ --#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) -+#define CONFIG_SYS_PVT 2 /* Divisor: 2^(PVT+1) => 8 */ -+#define CONFIG_SYS_HZ 1000 - - /*----------------------------------------------------------------------- - * Stack sizes -diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h -index 00c0374..4ed8373 100644 ---- a/include/configs/omap3_pandora.h -+++ b/include/configs/omap3_pandora.h -@@ -215,14 +215,13 @@ - /* address */ - - /* -- * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by -- * 32KHz clk, or from external sig. This rate is divided by a local divisor. -+ * OMAP3 has 12 GP timers, they can be driven by the system clock -+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). -+ * This rate is divided by a local divisor. - */ --#define V_PVT 7 -- - #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) --#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ --#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) -+#define CONFIG_SYS_PVT 2 /* Divisor: 2^(PVT+1) => 8 */ -+#define CONFIG_SYS_HZ 1000 - - /*----------------------------------------------------------------------- - * Stack sizes -diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h -index f8ae163..0185fa6 100644 ---- a/include/configs/omap3_zoom1.h -+++ b/include/configs/omap3_zoom1.h -@@ -222,14 +222,13 @@ - /* load address */ - - /* -- * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by -- * 32KHz clk, or from external sig. This rate is divided by a local divisor. -+ * OMAP3 has 12 GP timers, they can be driven by the system clock -+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). -+ * This rate is divided by a local divisor. - */ --#define V_PVT 7 -- - #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) --#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ --#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) -+#define CONFIG_SYS_PVT 2 /* Divisor: 2^(PVT+1) => 8 */ -+#define CONFIG_SYS_HZ 1000 - - /*----------------------------------------------------------------------- - * Stack sizes --- -1.6.2.4 - diff --git a/recipes/u-boot/u-boot-git/omap3evm/0004-Reverse-patch-for-NFS-boot-to-fix-comments-provided.patch b/recipes/u-boot/u-boot-git/omap3evm/0004-Reverse-patch-for-NFS-boot-to-fix-comments-provided.patch deleted file mode 100644 index 8ce6ac9602..0000000000 --- a/recipes/u-boot/u-boot-git/omap3evm/0004-Reverse-patch-for-NFS-boot-to-fix-comments-provided.patch +++ /dev/null @@ -1,53 +0,0 @@ -From 515c1e71f21e6666d8f8da7a539d6edd122a0fc3 Mon Sep 17 00:00:00 2001 -From: Manikandan Pillai <mani.pillai@ti.com> -Date: Wed, 8 Apr 2009 09:03:10 +0530 -Subject: [PATCH 04/16] Reverse patch for NFS boot to fix comments provided by community - ---- - drivers/net/smc911x.c | 23 +---------------------- - 1 files changed, 1 insertions(+), 22 deletions(-) - -diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c -index 2f0852e..1ded8f0 100644 ---- a/drivers/net/smc911x.c -+++ b/drivers/net/smc911x.c -@@ -116,27 +116,6 @@ static int smc911x_phy_reset(void) - return 0; - } - --static void smc911x_shutdown(void) --{ -- unsigned cr; -- -- /* Turn of Rx and TX */ -- cr = smc911x_get_mac_csr(MAC_CR); -- cr &= ~(MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS); -- smc911x_set_mac_csr(MAC_CR, cr); -- -- /* Stop Transmission */ -- cr = smc911x_get_mac_csr(TX_CFG); -- cr &= ~(TX_CFG_STOP_TX); -- smc911x_set_mac_csr(TX_CFG, cr); -- /* Stop receiving packets */ -- cr = smc911x_get_mac_csr(RX_CFG); -- cr &= ~(RX_CFG_RXDOFF); -- smc911x_set_mac_csr(RX_CFG, cr); -- --} -- -- - static void smc911x_phy_configure(void) - { - int timeout; -@@ -245,7 +224,7 @@ int eth_send(volatile void *packet, int length) - - void eth_halt(void) - { -- smc911x_shutdown(); -+ smc911x_reset(); - } - - int eth_rx(void) --- -1.6.2.4 - diff --git a/recipes/u-boot/u-boot-git/omap3evm/0005-SMC911x-driver-fixed-for-NFS-boot.patch b/recipes/u-boot/u-boot-git/omap3evm/0005-SMC911x-driver-fixed-for-NFS-boot.patch deleted file mode 100644 index 8b3894bc3f..0000000000 --- a/recipes/u-boot/u-boot-git/omap3evm/0005-SMC911x-driver-fixed-for-NFS-boot.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 3ffa2549a4f61053f78c00b8716cda392cf97b93 Mon Sep 17 00:00:00 2001 -From: Manikandan Pillai <mani.pillai@ti.com> -Date: Wed, 8 Apr 2009 09:08:00 +0530 -Subject: [PATCH 05/16] SMC911x driver fixed for NFS boot - -eth_halt() function in the smc911x drivers used to call the -smc911x_reset() function. eth_halt() used to be called after -tftp transfers. This used to put the ethernet chip in reset -while the linux boots up resulting in the ethernet driver -not coming up. NFS boot used to fail as a result. - -This patch calls smc911x_shutdown() instead of smc911x_reset(). -Some comments received has also been fixed. ---- - drivers/net/smc911x.c | 23 ++++++++++++++++++++++- - 1 files changed, 22 insertions(+), 1 deletions(-) - -diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c -index 1ded8f0..5bc3914 100644 ---- a/drivers/net/smc911x.c -+++ b/drivers/net/smc911x.c -@@ -116,6 +116,27 @@ static int smc911x_phy_reset(void) - return 0; - } - -+static void smc911x_shutdown(void) -+{ -+ unsigned int cr; -+ -+ /* Turn of Rx and TX */ -+ cr = smc911x_get_mac_csr(MAC_CR); -+ cr &= ~(MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS); -+ smc911x_set_mac_csr(MAC_CR, cr); -+ -+ /* Stop Transmission */ -+ cr = smc911x_get_mac_csr(TX_CFG); -+ cr &= ~(TX_CFG_STOP_TX); -+ smc911x_set_mac_csr(TX_CFG, cr); -+ /* Stop receiving packets */ -+ cr = smc911x_get_mac_csr(RX_CFG); -+ cr &= ~(RX_CFG_RXDOFF); -+ smc911x_set_mac_csr(RX_CFG, cr); -+ -+} -+ -+ - static void smc911x_phy_configure(void) - { - int timeout; -@@ -224,7 +245,7 @@ int eth_send(volatile void *packet, int length) - - void eth_halt(void) - { -- smc911x_reset(); -+ smc911x_shutdown(); - } - - int eth_rx(void) --- -1.6.2.4 - diff --git a/recipes/u-boot/u-boot-git/omap3evm/0006-Added-OMAP3517-3505-support.patch b/recipes/u-boot/u-boot-git/omap3evm/0006-Added-OMAP3517-3505-support.patch deleted file mode 100644 index 326679af78..0000000000 --- a/recipes/u-boot/u-boot-git/omap3evm/0006-Added-OMAP3517-3505-support.patch +++ /dev/null @@ -1,2501 +0,0 @@ -From 4144e9f85d1b0e48732c80b05bc380ae6d2af6d8 Mon Sep 17 00:00:00 2001 -From: Vaibhav Hiremath <hvaibhav@ti.com> -Date: Sat, 13 Jun 2009 00:47:34 +0530 -Subject: [PATCH 06/16] Added OMAP3517/3505 support - -Added support for OMAP3517/3505 SoC, it includes all the changes -from Mani's commit for OMAP3517 and review comments fix. - -Major features/changes - - - New config file - - New board files - - New ethernet driver - -Major Review comments - - - Added macine ID for OMAP3517 - - Naming conventions used. ---- - Makefile | 3 + - board/omap3/omap3517evm/Makefile | 47 +++ - board/omap3/omap3517evm/config.mk | 33 ++ - board/omap3/omap3517evm/omap3517evm.c | 124 ++++++ - board/omap3/omap3517evm/omap3517evm.h | 392 ++++++++++++++++++ - board/omap3/omap3517evm/u-boot.lds | 63 +++ - cpu/arm_cortexa8/omap3/board.c | 8 + - cpu/arm_cortexa8/omap3/clock.c | 4 + - cpu/arm_cortexa8/omap3/mem.c | 110 +++++ - drivers/net/Makefile | 1 + - drivers/net/ticpgmac.c | 693 ++++++++++++++++++++++++++++++++ - include/asm-arm/arch-omap3/cpu.h | 26 ++ - include/asm-arm/arch-omap3/mux.h | 41 ++ - include/asm-arm/arch-omap3/sys_proto.h | 1 + - include/asm-arm/arch-omap3/ticpgmac.h | 340 ++++++++++++++++ - include/asm-arm/mach-types.h | 1 + - include/configs/omap3517evm.h | 349 ++++++++++++++++ - lib_arm/board.c | 4 +- - net/eth.c | 4 +- - 19 files changed, 2240 insertions(+), 4 deletions(-) - create mode 100644 board/omap3/omap3517evm/Makefile - create mode 100644 board/omap3/omap3517evm/config.mk - create mode 100644 board/omap3/omap3517evm/omap3517evm.c - create mode 100644 board/omap3/omap3517evm/omap3517evm.h - create mode 100644 board/omap3/omap3517evm/u-boot.lds - create mode 100644 drivers/net/ticpgmac.c - create mode 100644 include/asm-arm/arch-omap3/ticpgmac.h - create mode 100644 include/configs/omap3517evm.h - -diff --git a/Makefile b/Makefile -index 61bae6d..df25fb3 100644 ---- a/Makefile -+++ b/Makefile -@@ -2942,6 +2942,9 @@ omap3_pandora_config : unconfig - omap3_zoom1_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom1 omap3 omap3 - -+omap3517evm_config : unconfig -+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 omap3517evm omap3 omap3 -+ - ######################################################################### - ## XScale Systems - ######################################################################### -diff --git a/board/omap3/omap3517evm/Makefile b/board/omap3/omap3517evm/Makefile -new file mode 100644 -index 0000000..8f6d10e ---- /dev/null -+++ b/board/omap3/omap3517evm/Makefile -@@ -0,0 +1,47 @@ -+# -+# (C) Copyright 2000, 2001, 2002 -+# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -+# -+# See file CREDITS for list of people who contributed to this -+# project. -+# -+# This program is free software; you can redistribute it and/or -+# modify it under the terms of the GNU General Public License as -+# published by the Free Software Foundation; either version 2 of -+# the License, or (at your option) any later version. -+# -+# This program is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not, write to the Free Software -+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+# MA 02111-1307 USA -+# -+ -+include $(TOPDIR)/config.mk -+ -+LIB = $(obj)lib$(BOARD).a -+ -+COBJS := omap3517evm.o -+ -+SRCS := $(COBJS:.o=.c) -+OBJS := $(addprefix $(obj),$(COBJS)) -+ -+$(LIB): $(obj).depend $(OBJS) -+ $(AR) $(ARFLAGS) $@ $(OBJS) -+ -+clean: -+ rm -f $(OBJS) -+ -+distclean: clean -+ rm -f $(LIB) core *.bak $(obj).depend -+ -+######################################################################### -+ -+# defines $(obj).depend target -+include $(SRCTREE)/rules.mk -+ -+sinclude $(obj).depend -diff --git a/board/omap3/omap3517evm/config.mk b/board/omap3/omap3517evm/config.mk -new file mode 100644 -index 0000000..4d873eb ---- /dev/null -+++ b/board/omap3/omap3517evm/config.mk -@@ -0,0 +1,33 @@ -+# -+# (C) Copyright 2006 - 2008 -+# Texas Instruments, <www.ti.com> -+# -+# EVM uses OMAP3 (ARM-CortexA8) cpu -+# see http://www.ti.com/ for more information on Texas Instruments -+# -+# See file CREDITS for list of people who contributed to this -+# project. -+# -+# This program is free software; you can redistribute it and/or -+# modify it under the terms of the GNU General Public License as -+# published by the Free Software Foundation; either version 2 of -+# the License, or (at your option) any later version. -+# -+# This program is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not, write to the Free Software -+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+# MA 02111-1307 USA -+# -+# Physical Address: -+# 8000'0000 (bank0) -+# A000/0000 (bank1) -+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -+# (mem base + reserved) -+ -+# For use with external or internal boots. -+TEXT_BASE = 0x80e80000 -diff --git a/board/omap3/omap3517evm/omap3517evm.c b/board/omap3/omap3517evm/omap3517evm.c -new file mode 100644 -index 0000000..2330776 ---- /dev/null -+++ b/board/omap3/omap3517evm/omap3517evm.c -@@ -0,0 +1,124 @@ -+/* -+ * (C) Copyright 2004-2008 -+ * Texas Instruments, <www.ti.com> -+ * -+ * Author : -+ * Manikandan Pillai <mani.pillai@ti.com> -+ * -+ * Derived from Beagle Board and 3430 SDP code by -+ * Richard Woodruff <r-woodruff2@ti.com> -+ * Syed Mohammed Khasim <khasim@ti.com> -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+#include <common.h> -+#include <asm/io.h> -+#include <asm/arch/mem.h> -+#include <asm/arch/mux.h> -+#include <asm/arch/sys_proto.h> -+#include <i2c.h> -+#include <asm/mach-types.h> -+#include "omap3517evm.h" -+ -+/****************************************************************************** -+ * Routine: board_init -+ * Description: Early hardware init. -+ *****************************************************************************/ -+int board_init(void) -+{ -+ DECLARE_GLOBAL_DATA_PTR; -+ -+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ -+ /* board id for Linux */ -+ gd->bd->bi_arch_number = MACH_TYPE_OMAP3517EVM; -+ /* boot param addr */ -+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); -+ -+ return 0; -+} -+ -+/****************************************************************************** -+ * Routine: misc_init_r -+ * Description: Init ethernet (done here so udelay works) -+ *****************************************************************************/ -+int misc_init_r(void) -+{ -+ -+#ifdef CONFIG_DRIVER_OMAP34XX_I2C -+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -+#endif -+ -+#if defined(CONFIG_CMD_NET) -+ setup_net_chip(); -+#endif -+ -+ dieid_num_r(); -+ -+ return 0; -+} -+ -+/****************************************************************************** -+ * Routine: set_muxconf_regs -+ * Description: Setting up the configuration Mux registers specific to the -+ * hardware. Many pins need to be moved from protect to primary -+ * mode. -+ *****************************************************************************/ -+void set_muxconf_regs(void) -+{ -+ MUX_OMAP3517EVM(); -+} -+ -+/****************************************************************************** -+ * Routine: setup_net_chip -+ * Description: Setting up the configuration GPMC registers specific to the -+ * Ethernet hardware. -+ *****************************************************************************/ -+static void setup_net_chip(void) -+{ -+ gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE; -+ gpmc_csx_t *gpmc_cs6_base = (gpmc_csx_t *)GPMC_CONFIG_CS6_BASE; -+ ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE; -+ -+ /* Configure GPMC registers */ -+ writel(NET_GPMC_CONFIG1, &gpmc_cs6_base->config1); -+ writel(NET_GPMC_CONFIG2, &gpmc_cs6_base->config2); -+ writel(NET_GPMC_CONFIG3, &gpmc_cs6_base->config3); -+ writel(NET_GPMC_CONFIG4, &gpmc_cs6_base->config4); -+ writel(NET_GPMC_CONFIG5, &gpmc_cs6_base->config5); -+ writel(NET_GPMC_CONFIG6, &gpmc_cs6_base->config6); -+ writel(NET_GPMC_CONFIG7, &gpmc_cs6_base->config7); -+ -+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ -+ writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); -+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ -+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); -+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ -+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, -+ &ctrl_base->gpmc_nadv_ale); -+ -+ /* Make GPIO 64 as output pin */ -+ writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe); -+ -+ /* Now send a pulse on the GPIO pin */ -+ writel(GPIO0, &gpio3_base->setdataout); -+ udelay(1); -+ writel(GPIO0, &gpio3_base->cleardataout); -+ udelay(1); -+ writel(GPIO0, &gpio3_base->setdataout); -+} -diff --git a/board/omap3/omap3517evm/omap3517evm.h b/board/omap3/omap3517evm/omap3517evm.h -new file mode 100644 -index 0000000..aba53bf ---- /dev/null -+++ b/board/omap3/omap3517evm/omap3517evm.h -@@ -0,0 +1,392 @@ -+/* -+ * (C) Copyright 2008 -+ * Nishanth Menon <menon.nishanth@gmail.com> -+ * -+ * See file CREDITS for list of people who contributed to this -+ * project. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ */ -+#ifndef _OMAP3517EVM_H_ -+#define _OMAP3517EVM_H_ -+ -+const omap3_sysinfo sysinfo = { -+ OMAP3EVM_V1, -+ OMAP3EVM_V2, -+ DDR_DISCRETE, -+ "OMAP3 omap3517evm board", -+ "NAND", -+}; -+ -+static void setup_net_chip(void); -+ -+/* -+ * IEN - Input Enable -+ * IDIS - Input Disable -+ * PTD - Pull type Down -+ * PTU - Pull type Up -+ * DIS - Pull type selection is inactive -+ * EN - Pull type selection is active -+ * M0 - Mode 0 -+ * The commented string gives the final mux configuration for that pin -+ */ -+#define MUX_OMAP3517EVM() \ -+ /*SDRC*/\ -+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ -+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ -+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ -+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ -+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ -+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ -+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ -+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ -+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ -+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ -+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ -+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ -+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ -+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ -+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ -+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ -+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ -+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ -+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ -+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ -+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ -+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ -+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ -+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) |