diff options
Diffstat (limited to 'packages/linux')
95 files changed, 32855 insertions, 306 deletions
diff --git a/packages/linux/gumstix-linux.inc b/packages/linux/gumstix-linux.inc index 50111cb545..038089c965 100644 --- a/packages/linux/gumstix-linux.inc +++ b/packages/linux/gumstix-linux.inc @@ -35,16 +35,6 @@ do_configure_prepend() { yes '' | oe_runmake oldconfig } -do_sizecheck() { - if [ ! -z "${KERNEL_IMAGE_MAXSIZE}" ]; then - size=`ls -l arch/${ARCH}/boot/${KERNEL_IMAGETYPE} | awk '{ print $5}'` - if [ $size -ge ${KERNEL_IMAGE_MAXSIZE} ]; then - rm arch/${ARCH}/boot/${KERNEL_IMAGETYPE} - die "This kernel (size=$size) is too big for your device. Please reduce the size of the kernel by making more of it modular." - fi - fi -} - do_install_prepend() { if test -e arch/${ARCH}/boot/Image ; then ln -f arch/${ARCH}/boot/Image arch/${ARCH}/boot/uImage @@ -68,7 +58,4 @@ do_deploy() { fi } -addtask sizecheck before do_install after do_compile addtask deploy before do_package after do_install - - diff --git a/packages/linux/linux-openmoko-devel/.mtn2git_empty b/packages/linux/linux-2.6.24/at32stk1000/.mtn2git_empty index e69de29bb2..e69de29bb2 100644 --- a/packages/linux/linux-openmoko-devel/.mtn2git_empty +++ b/packages/linux/linux-2.6.24/at32stk1000/.mtn2git_empty diff --git a/packages/linux/linux-2.6.24/at32stk1000/defconfig b/packages/linux/linux-2.6.24/at32stk1000/defconfig new file mode 100644 index 0000000000..8a3e2ace8b --- /dev/null +++ b/packages/linux/linux-2.6.24/at32stk1000/defconfig @@ -0,0 +1,1186 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.24.3 +# Fri Mar 14 12:39:45 2008 +# +CONFIG_AVR32=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_FAIR_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +# CONFIG_BASE_FULL is not set +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=1 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" + +# +# System Type and features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_SUBARCH_AVR32B=y +CONFIG_MMU=y +CONFIG_PERFORMANCE_COUNTERS=y +CONFIG_PLATFORM_AT32AP=y +CONFIG_CPU_AT32AP700X=y +CONFIG_CPU_AT32AP7000=y +CONFIG_BOARD_ATSTK1000=y +# CONFIG_BOARD_ATNGW100 is not set +CONFIG_BOARD_ATSTK1002=y +# CONFIG_BOARD_ATSTK1003 is not set +# CONFIG_BOARD_ATSTK1004 is not set +# CONFIG_BOARD_ATSTK100X_CUSTOM is not set +# CONFIG_BOARD_ATSTK100X_SPI1 is not set +# CONFIG_BOARD_ATSTK1000_J2_LED is not set +# CONFIG_BOARD_ATSTK1000_J2_LED8 is not set +# CONFIG_BOARD_ATSTK1000_J2_RGB is not set +CONFIG_BOARD_ATSTK1000_EXTDAC=y +# CONFIG_BOARD_ATSTK100X_ENABLE_AC97 is not set +# CONFIG_BOARD_ATSTK1000_CF_HACKS is not set +# CONFIG_BOARD_ATSTK100X_ENABLE_PSIF is not set +CONFIG_LOADER_U_BOOT=y + +# +# Atmel AVR32 AP options +# +# CONFIG_AP700X_32_BIT_SMC is not set +CONFIG_AP700X_16_BIT_SMC=y +# CONFIG_AP700X_8_BIT_SMC is not set +CONFIG_GPIO_DEV=y +CONFIG_LOAD_ADDRESS=0x10000000 +CONFIG_ENTRY_ADDRESS=0x90000000 +CONFIG_PHYS_OFFSET=0x10000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set +# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set +# CONFIG_NEED_NODE_MEMMAP_SIZE is not set +CONFIG_ARCH_FLATMEM_ENABLE=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +# CONFIG_ARCH_SPARSEMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_OWNERSHIP_TRACE is not set +CONFIG_NMI_DEBUGGING=y +CONFIG_DW_DMAC=y +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +CONFIG_CMDLINE=" debug " + +# +# Power management options +# + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +# CONFIG_CPU_FREQ_STAT is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_AT32AP=y + +# +# Bus options +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE=m +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=m +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_TUNNEL=m +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_BRIDGE=m +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_TCPPROBE is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x8000000 +CONFIG_MTD_PHYSMAP_LEN=0x0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +CONFIG_MTD_DATAFLASH=m +CONFIG_MTD_M25P80=m +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +CONFIG_ATMEL_PWM=m +CONFIG_ATMEL_TCLIB=y +CONFIG_ATMEL_TCB_CLKSRC=y +CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0 +# CONFIG_EEPROM_93CX6 is not set +CONFIG_ATMEL_SSC=m +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=m +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_PATA_AT32=m +# CONFIG_PATA_PLATFORM is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +CONFIG_MACB=y +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_WAN is not set +CONFIG_PPP=m +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=m +# CONFIG_PPP_SYNC_TTY is not set +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +# CONFIG_PPP_MPPE is not set +# CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=m +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=m + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=m +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_INPUT_MOUSE=y +# CONFIG_MOUSE_PS2 is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +CONFIG_MOUSE_GPIO=m +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_SERIAL_ATMEL_PDC=y +# CONFIG_SERIAL_ATMEL_TTYAT is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=m +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=m + +# +# I2C Algorithms +# +CONFIG_I2C_ALGOBIT=m +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +CONFIG_I2C_ATMELTWI=m +CONFIG_I2C_GPIO=m +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_ATMEL=y +# CONFIG_SPI_BITBANG is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_AT25 is not set +CONFIG_SPI_SPIDEV=m +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_AT32AP700X_WDT=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_ATMEL=y +# CONFIG_FB_VIRTUAL is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_LTV350QV=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_ATMEL_LCDC=y +CONFIG_BACKLIGHT_CORGI=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=m +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_LOGO is not set + +# +# Sound +# +CONFIG_SOUND=m + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_VERBOSE_PROCFS is not set +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +CONFIG_SND_AC97_CODEC=m +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# AVR32 devices +# +CONFIG_SND_ATMEL_AC97=m + +# +# SPI devices +# +CONFIG_SND_AT73C213=m +CONFIG_SND_AT73C213_TARGET_BITRATE=48000 + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# SoC Audio support for SuperH +# + +# +# Open Sound System +# +CONFIG_SOUND_PRIME=m +# CONFIG_SOUND_MSNDCLAS is not set +# CONFIG_SOUND_MSNDPIN is not set +CONFIG_SOUND_AT32_ABDAC=m +CONFIG_AC97_BUS=m +# CONFIG_HID_SUPPORT is not set +CONFIG_USB_SUPPORT=y +# CONFIG_USB_ARCH_HAS_HCD is not set +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AMD5536UDC is not set +CONFIG_USB_GADGET_ATMEL_USBA=y +CONFIG_USB_ATMEL_USBA=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +# CONFIG_USB_FILE_STORAGE_TEST is not set +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +# CONFIG_SDIO_UART is not set + +# +# MMC/SD Host Controller Drivers +# +CONFIG_MMC_ATMELMCI=y +CONFIG_MMC_SPI=m +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=m + +# +# LED drivers +# +CONFIG_LEDS_ATMEL_PWM=m +CONFIG_LEDS_GPIO=m + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_AT32AP700X=y + +# +# Userspace I/O +# +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=m + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=m +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set +CONFIG_INSTRUMENTATION=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=m +CONFIG_KPROBES=y +# CONFIG_MARKERS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +CONFIG_FRAME_POINTER=y +CONFIG_FORCED_INLINING=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SAMPLES is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_HASH=m +CONFIG_CRYPTO_MANAGER=m +CONFIG_CRYPTO_HMAC=m +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_ECB is not set +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_HW is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +CONFIG_CRC7=m +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/packages/linux/linux-2.6.24/atngw100/.mtn2git_empty b/packages/linux/linux-2.6.24/atngw100/.mtn2git_empty new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/packages/linux/linux-2.6.24/atngw100/.mtn2git_empty diff --git a/packages/linux/linux-2.6.24/atngw100/defconfig b/packages/linux/linux-2.6.24/atngw100/defconfig new file mode 100644 index 0000000000..922bb32c44 --- /dev/null +++ b/packages/linux/linux-2.6.24/atngw100/defconfig @@ -0,0 +1,1223 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.24.3 +# Fri Mar 14 11:46:04 2008 +# +CONFIG_AVR32=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FAIR_USER_SCHED=y +# CONFIG_FAIR_CGROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +# CONFIG_BASE_FULL is not set +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=1 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" + +# +# System Type and features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_SUBARCH_AVR32B=y +CONFIG_MMU=y +CONFIG_PERFORMANCE_COUNTERS=y +CONFIG_PLATFORM_AT32AP=y +CONFIG_CPU_AT32AP700X=y +CONFIG_CPU_AT32AP7000=y +# CONFIG_BOARD_ATSTK1000 is not set +CONFIG_BOARD_ATNGW100=y +CONFIG_BOARD_ATNGW100_I2C_GPIO=y +CONFIG_LOADER_U_BOOT=y + +# +# Atmel AVR32 AP options +# +# CONFIG_AP700X_32_BIT_SMC is not set +CONFIG_AP700X_16_BIT_SMC=y +# CONFIG_AP700X_8_BIT_SMC is not set +CONFIG_GPIO_DEV=y +CONFIG_LOAD_ADDRESS=0x10000000 +CONFIG_ENTRY_ADDRESS=0x90000000 +CONFIG_PHYS_OFFSET=0x10000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set +# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set +# CONFIG_NEED_NODE_MEMMAP_SIZE is not set +CONFIG_ARCH_FLATMEM_ENABLE=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +# CONFIG_ARCH_SPARSEMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_OWNERSHIP_TRACE is not set +# CONFIG_NMI_DEBUGGING is not set +CONFIG_DW_DMAC=y +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +CONFIG_CMDLINE="" + +# +# Power management options +# + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +# CONFIG_CPU_FREQ_STAT is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_AT32AP=y + +# +# Bus options +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_MULTIPLE_TABLES is not set +# CONFIG_IP_ROUTE_MULTIPATH is not set +# CONFIG_IP_ROUTE_VERBOSE is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +# CONFIG_IP_PIMSM_V2 is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +CONFIG_INET_XFRM_TUNNEL=y +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IP_VS is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=y +CONFIG_INET6_TUNNEL=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK is not set +CONFIG_NF_CONNTRACK_ENABLED=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CT_ACCT=y +CONFIG_NF_CONNTRACK_MARK=y +# CONFIG_NF_CONNTRACK_EVENTS is not set +CONFIG_NF_CT_PROTO_GRE=m +# CONFIG_NF_CT_PROTO_SCTP is not set +# CONFIG_NF_CT_PROTO_UDPLITE is not set +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NETFILTER_XTABLES=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set +# CONFIG_NETFILTER_XT_TARGET_TRACE is not set +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m + +# +# IP: Netfilter Configuration +# +CONFIG_NF_CONNTRACK_IPV4=m +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_IPRANGE=m +CONFIG_IP_NF_MATCH_TOS=m +CONFIG_IP_NF_MATCH_RECENT=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_MATCH_OWNER=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=m +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_SAME=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_PROTO_GRE=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_NF_NAT_SIP=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_TOS=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# IPv6: Netfilter Configuration (EXPERIMENTAL) +# +CONFIG_NF_CONNTRACK_IPV6=m +CONFIG_IP6_NF_QUEUE=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_OWNER=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_RAW=m + +# +# Bridge: Netfilter Configuration +# +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=m +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +CONFIG_NET_CLS_ROUTE=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_TCPPROBE is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x80000000 +CONFIG_MTD_PHYSMAP_LEN=0x0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +CONFIG_MTD_DATAFLASH=y +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ATMEL_PWM is not set +CONFIG_ATMEL_TCLIB=y +CONFIG_ATMEL_TCB_CLKSRC=y +CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0 +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ATMEL_SSC is not set +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +# CONFIG_MII is not set +CONFIG_MACB=y +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_WAN is not set +CONFIG_PPP=m +# CONFIG_PPP_MULTILINK is not set +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +# CONFIG_PPP_SYNC_TTY is not set +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +# CONFIG_PPPOL2TP is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=m +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AT32PSIF is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_SERIAL_ATMEL_PDC=y +# CONFIG_SERIAL_ATMEL_TTYAT is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_RTC is not set +CONFIG_GEN_RTC=n +# CONFIG_GEN_RTC_X is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=m +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=m + +# +# I2C Algorithms +# +CONFIG_I2C_ALGOBIT=m +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +CONFIG_I2C_ATMELTWI=m +CONFIG_I2C_GPIO=m +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_ATMEL=y +# CONFIG_SPI_BITBANG is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_AT25 is not set +CONFIG_SPI_SPIDEV=m +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_AT32AP700X_WDT=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set +CONFIG_USB_SUPPORT=y +# CONFIG_USB_ARCH_HAS_HCD is not set +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AMD5536UDC is not set +CONFIG_USB_GADGET_ATMEL_USBA=y +CONFIG_USB_ATMEL_USBA=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +# CONFIG_USB_FILE_STORAGE_TEST is not set +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +# CONFIG_SDIO_UART is not set + +# +# MMC/SD Host Controller Drivers +# +CONFIG_MMC_ATMELMCI=y +CONFIG_MMC_SPI=m +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +CONFIG_LEDS_GPIO=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_AT32AP700X=y + +# +# Userspace I/O +# +# CONFIG_UIO is not set + +# +# File systems +# +CONFIG_EXT2_FS=m +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=m +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=m +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=m + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=850 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_NFSD_TCP=y +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS is not set +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_XATTR is not set +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_EXPERIMENTAL is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=m +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=m +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set +CONFIG_INSTRUMENTATION=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=m +CONFIG_KPROBES=y +# CONFIG_MARKERS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +CONFIG_FRAME_POINTER=y +# CONFIG_FORCED_INLINING is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SAMPLES is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +CONFIG_CRYPTO_ARC4=m +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +CONFIG_CRC7=m +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/packages/linux/linux-2.6.24/mpc8313e-rdb/defconfig b/packages/linux/linux-2.6.24/mpc8313e-rdb/defconfig index b87f62acbc..b7ca083ac1 100644 --- a/packages/linux/linux-2.6.24/mpc8313e-rdb/defconfig +++ b/packages/linux/linux-2.6.24/mpc8313e-rdb/defconfig @@ -758,7 +758,7 @@ CONFIG_NETDEVICES=y # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set +CONFIG_TUN=m # CONFIG_VETH is not set # CONFIG_ARCNET is not set CONFIG_PHYLIB=y diff --git a/packages/linux/linux-2.6.24/simpad/linux-2.6.24-SIMpad-rtc-sa1100.patch b/packages/linux/linux-2.6.24/simpad/linux-2.6.24-SIMpad-rtc-sa1100.patch new file mode 100644 index 0000000000..6e09bfd103 --- /dev/null +++ b/packages/linux/linux-2.6.24/simpad/linux-2.6.24-SIMpad-rtc-sa1100.patch @@ -0,0 +1,28 @@ +diff -Nur linux-2.6.24.vanilla/drivers/rtc/rtc-sa1100.c linux-2.6.24/drivers/rtc/rtc-sa1100.c +--- linux-2.6.24.vanilla/drivers/rtc/rtc-sa1100.c 2008-01-24 23:58:37.000000000 +0100 ++++ linux-2.6.24/drivers/rtc/rtc-sa1100.c 2008-03-17 20:52:41.000000000 +0100 +@@ -15,6 +15,10 @@ + * Converted to the RTC subsystem and Driver Model + * by Richard Purdie <rpurdie@rpsys.net> + * ++ * 2008/03/17 mrdata: ++ * disable IRQ RTC1Hz and RTCAlrm before request_irq ++ * in sa1100_rtc_open() ++ * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version +@@ -154,7 +158,12 @@ + static int sa1100_rtc_open(struct device *dev) + { + int ret; +- ++ ++ spin_lock_irq(&sa1100_rtc_lock); ++ RTSR &= ~RTSR_HZE; ++ RTSR &= ~RTSR_ALE; ++ spin_unlock_irq(&sa1100_rtc_lock); ++ + ret = request_irq(IRQ_RTC1Hz, sa1100_rtc_interrupt, IRQF_DISABLED, + "rtc 1Hz", dev); + if (ret) { diff --git a/packages/linux/linux-beagleboard/.mtn2git_empty b/packages/linux/linux-beagleboard/.mtn2git_empty new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/packages/linux/linux-beagleboard/.mtn2git_empty diff --git a/packages/linux/linux-beagleboard/defconfig b/packages/linux/linux-beagleboard/defconfig new file mode 100644 index 0000000000..7a994cc810 --- /dev/null +++ b/packages/linux/linux-beagleboard/defconfig @@ -0,0 +1,805 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.24-rc3-omap1 +# Mon Dec 3 16:12:50 2007 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FAIR_USER_SCHED=y +# CONFIG_FAIR_CGROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +CONFIG_ARCH_OMAP=y + +# +# TI OMAP Implementations +# +# CONFIG_ARCH_OMAP1 is not set +# CONFIG_ARCH_OMAP2 is not set +CONFIG_ARCH_OMAP3=y + +# +# OMAP Feature Selections +# +CONFIG_OMAP_DEBUG_SRAM_PATCH=y +# CONFIG_OMAP_RESET_CLOCKS is not set +CONFIG_OMAP_BOOT_TAG=y +CONFIG_OMAP_BOOT_REASON=y +# CONFIG_OMAP_COMPONENT_VERSION is not set +# CONFIG_OMAP_GPIO_SWITCH is not set +CONFIG_OMAP_MUX=y +CONFIG_OMAP_MUX_DEBUG=y +CONFIG_OMAP_MUX_WARNINGS=y +# CONFIG_OMAP_MCBSP is not set +# CONFIG_OMAP_MMU_FWK is not set +# CONFIG_OMAP_MBOX_FWK is not set +CONFIG_OMAP_MPU_TIMER=y +# CONFIG_OMAP_32K_TIMER is not set +CONFIG_OMAP_DM_TIMER=y +CONFIG_OMAP_LL_DEBUG_UART1=y +# CONFIG_OMAP_LL_DEBUG_UART2 is not set +# CONFIG_OMAP_LL_DEBUG_UART3 is not set +CONFIG_OMAP_SERIAL_WAKE=y +CONFIG_ARCH_OMAP34XX=y +CONFIG_ARCH_OMAP3430=y + +# +# OMAP Board Type +# +# CONFIG_MACH_OMAP_3430SDP is not set +CONFIG_MACH_OMAP3_BEAGLE=y + +# +# Boot options +# + +# +# Power management +# + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_IFAR=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_ARM_XENON is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_HAS_TLS_REG=y +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="root=/dev/nfs nfsroot=192.168.0.1:/home/user/buildroot ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:tgt:eth0:off rw console=ttyS2,115200n8" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y +CONFIG_VFPv3=y +# CONFIG_NEON is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_SUSPEND_UP_POSSIBLE=y + +# +# Networking +# +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_CDROM_PKTCDVD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_UCB1400 is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_OMAP=y +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_TPS65010 is not set +# CONFIG_SENSORS_TLV320AIC23 is not set +CONFIG_TWL4030_CORE=y +CONFIG_TWL4030_GPIO=y +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_OMAP_WATCHDOG=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +CONFIG_DAB=y + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y + +# +# Sound +# +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB is not set + +# +# Enable Host or Gadget support to see Inventra options +# + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set + +# +# MMC/SD Host Controller Drivers +# +CONFIG_MMC_OMAP=y +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set + +# +# CBUS support +# +# CONFIG_CBUS is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_QUOTA=y +CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +CONFIG_INSTRUMENTATION=y +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +CONFIG_FRAME_POINTER=y +CONFIG_FORCED_INLINING=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SAMPLES is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_MANAGER=y +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/packages/linux/linux-beagleboard_git.bb b/packages/linux/linux-beagleboard_git.bb new file mode 100644 index 0000000000..610b9ea361 --- /dev/null +++ b/packages/linux/linux-beagleboard_git.bb @@ -0,0 +1,12 @@ +require linux.inc + +SRCREV = "1a77f70604e00b94bb3c841665a44b34430e9eda" +PV = "2.6.23+2.6.24rc3-git${SRCREV}" +PR = "r1" + +COMPATIBLE_MACHINE = "beagleboard" + +SRC_URI = "git://www.beagleboard.org/linux.git;protocol=http \ + file://defconfig" + +S = "${WORKDIR}/linux" diff --git a/packages/linux/linux-handhelds-2.6.inc b/packages/linux/linux-handhelds-2.6.inc index 3bd9f78ea2..48e49115f0 100644 --- a/packages/linux/linux-handhelds-2.6.inc +++ b/packages/linux/linux-handhelds-2.6.inc @@ -37,6 +37,16 @@ do_configure() { die "No default configuration for ${MACHINE} available." fi + if [ -n "${KERNEL_INITRAMFS_PATH}" -a "${ANGSTROM_MODE}" = "glibc" ]; then + if [ ! -f ${KERNEL_INITRAMFS_PATH} ]; then + echo "${KERNEL_INITRAMFS_PATH} does not exist, you may need to bitbake it separately" + exit 1 + fi + + # Kernel expects non-compressed cpio + gzip -d -c ${KERNEL_INITRAMFS_PATH} >${WORKDIR}/initramfs.cpio + echo "CONFIG_INITRAMFS_SOURCE=\"${WORKDIR}/initramfs.cpio\"" >> ${S}/.config + fi if [ "${TARGET_OS}" == "linux-gnueabi" -o "${TARGET_OS}" == "linux-uclibcgnueabi" ]; then echo "CONFIG_AEABI=y" >> ${S}/.config @@ -48,22 +58,13 @@ do_configure() { sed -e '/CONFIG_AEABI/d' \ -e '/CONFIG_OABI_COMPAT=/d' \ + -e '/CONFIG_INITRAMFS_SOURCE=/d' \ '${WORKDIR}/defconfig' >>'${S}/.config' yes '' | oe_runmake oldconfig } -do_compile_prepend() { - if [ -n "${KERNEL_INITRAMFS_PATH}" -a "${ANGSTROM_MODE}" == "glibc" ]; then - if [ ! -f ${KERNEL_INITRAMFS_PATH} ]; then - echo "${KERNEL_INITRAMFS_PATH} does not exist, you may need to bitbake it separately" - exit 1 - fi - cp ${KERNEL_INITRAMFS_PATH} usr/initramfs_data.cpio.gz - fi -} - do_deploy() { install -d ${DEPLOY_DIR_IMAGE} install -m 0644 arch/${ARCH}/boot/${KERNEL_IMAGETYPE} ${DEPLOY_DIR_IMAGE}/${KERNEL_FILENAME} diff --git a/packages/linux/linux-handhelds-2.6_2.6.21-hh20.bb b/packages/linux/linux-handhelds-2.6_2.6.21-hh20.bb index 066c17faed..3df1102761 100644 --- a/packages/linux/linux-handhelds-2.6_2.6.21-hh20.bb +++ b/packages/linux/linux-handhelds-2.6_2.6.21-hh20.bb @@ -1,7 +1,7 @@ SECTION = "kernel" DESCRIPTION = "handhelds.org Linux kernel 2.6 for PocketPCs and other consumer handheld devices." LICENSE = "GPL" -PR = "r14" +PR = "r20" DEFAULT_PREFERENCE = "-1" @@ -12,6 +12,6 @@ FILESPATH = "${FILE_DIRNAME}/linux-handhelds-2.6-2.6.21/${MACHINE}:${FILE_DIRNAM SRC_URI = "${HANDHELDS_CVS};module=linux/kernel26;tag=${@'K' + bb.data.getVar('PV',d,1).replace('.', '-')} \ file://linux-2.6.git-9d20fdd58e74d4d26dc5216efaaa0f800c23dd3a.patch;patch=1 \ http://www.rpsys.net/openzaurus/patches/archive/export_atags-r0a.patch;patch=1 \ - file://defconfig" + file://defconfig" require linux-handhelds-2.6.inc diff --git a/packages/linux/linux-mainstone/.mtn2git_empty b/packages/linux/linux-mainstone/.mtn2git_empty new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/packages/linux/linux-mainstone/.mtn2git_empty diff --git a/packages/linux/linux-mainstone/mainstone-keypad.patch b/packages/linux/linux-mainstone/mainstone-keypad.patch new file mode 100644 index 0000000000..cad6289260 --- /dev/null +++ b/packages/linux/linux-mainstone/mainstone-keypad.patch @@ -0,0 +1,7631 @@ +diff -NbBur linux-2.6.25-rc4-orig/arch/arm/mach-pxa/devices.c linux-2.6.25-rc4/arch/arm/mach-pxa/devices.c +--- linux-2.6.25-rc4-orig/arch/arm/mach-pxa/devices.c 2008-03-08 18:25:54.000000000 +0100 ++++ linux-2.6.25-rc4/arch/arm/mach-pxa/devices.c 2008-03-08 16:22:35.000000000 +0100 +@@ -396,6 +396,31 @@ + + #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) + ++static struct resource pxa27x_resource_keypad[] = { ++ [0] = { ++ .start = 0x41500000, ++ .end = 0x4150004c, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_KEYPAD, ++ .end = IRQ_KEYPAD, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++struct platform_device pxa27x_device_keypad = { ++ .name = "pxa27x-keypad", ++ .id = -1, ++ .resource = pxa27x_resource_keypad, ++ .num_resources = ARRAY_SIZE(pxa27x_resource_keypad), ++}; ++ ++void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info) ++{ ++ pxa_register_device(&pxa27x_device_keypad, info); ++} ++ + static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32); + + static struct resource pxa27x_resource_ohci[] = { +diff -NbBur linux-2.6.25-rc4-orig/arch/arm/mach-pxa/devices.h linux-2.6.25-rc4/arch/arm/mach-pxa/devices.h +--- linux-2.6.25-rc4-orig/arch/arm/mach-pxa/devices.h 2008-03-08 18:25:54.000000000 +0100 ++++ linux-2.6.25-rc4/arch/arm/mach-pxa/devices.h 2008-03-08 16:22:35.000000000 +0100 +@@ -14,6 +14,7 @@ + + extern struct platform_device pxa27x_device_i2c_power; + extern struct platform_device pxa27x_device_ohci; ++extern struct platform_device pxa27x_device_keypad; + + extern struct platform_device pxa25x_device_ssp; + extern struct platform_device pxa25x_device_nssp; +diff -NbBur linux-2.6.25-rc4-orig/arch/arm/mach-pxa/mainstone.c linux-2.6.25-rc4/arch/arm/mach-pxa/mainstone.c +--- linux-2.6.25-rc4-orig/arch/arm/mach-pxa/mainstone.c 2008-03-08 18:25:54.000000000 +0100 ++++ linux-2.6.25-rc4/arch/arm/mach-pxa/mainstone.c 2008-03-08 16:11:42.000000000 +0100 +@@ -46,6 +46,7 @@ + #include <asm/arch/mmc.h> + #include <asm/arch/irda.h> + #include <asm/arch/ohci.h> ++#include <asm/arch/pxa27x_keypad.h> + + #include "generic.h" + #include "devices.h" +@@ -460,6 +461,72 @@ + .init = mainstone_ohci_init, + }; + ++#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULES) ++static unsigned int mainstone_matrix_keys[] = { ++ KEY(0, 0, KEY_A), KEY(1, 0, KEY_B), KEY(2, 0, KEY_C), ++ KEY(3, 0, KEY_D), KEY(4, 0, KEY_E), KEY(5, 0, KEY_F), ++ KEY(0, 1, KEY_G), KEY(1, 1, KEY_H), KEY(2, 1, KEY_I), ++ KEY(3, 1, KEY_J), KEY(4, 1, KEY_K), KEY(5, 1, KEY_L), ++ KEY(0, 2, KEY_M), KEY(1, 2, KEY_N), KEY(2, 2, KEY_O), ++ KEY(3, 2, KEY_P), KEY(4, 2, KEY_Q), KEY(5, 2, KEY_R), ++ KEY(0, 3, KEY_S), KEY(1, 3, KEY_T), KEY(2, 3, KEY_U), ++ KEY(3, 3, KEY_V), KEY(4, 3, KEY_W), KEY(5, 3, KEY_X), ++ KEY(2, 4, KEY_Y), KEY(3, 4, KEY_Z), ++ ++ KEY(0, 4, KEY_DOT), /* . */ ++ KEY(1, 4, KEY_CLOSE), /* @ */ ++ KEY(4, 4, KEY_SLASH), ++ KEY(5, 4, KEY_BACKSLASH), ++ KEY(0, 5, KEY_HOME), ++ KEY(1, 5, KEY_LEFTSHIFT), ++ KEY(2, 5, KEY_SPACE), ++ KEY(3, 5, KEY_SPACE), ++ KEY(4, 5, KEY_ENTER), ++ KEY(5, 5, KEY_BACKSPACE), ++ ++ KEY(0, 6, KEY_UP), ++ KEY(1, 6, KEY_DOWN), ++ KEY(2, 6, KEY_LEFT), ++ KEY(3, 6, KEY_RIGHT), ++ KEY(4, 6, KEY_SELECT), ++}; ++ ++struct pxa27x_keypad_platform_data mainstone_keypad_info = { ++ .matrix_key_rows = 6, ++ .matrix_key_cols = 7, ++ .matrix_key_map = mainstone_matrix_keys, ++ .matrix_key_map_size = ARRAY_SIZE(mainstone_matrix_keys), ++ ++ .enable_rotary0 = 1, ++ .rotary0_up_key = KEY_UP, ++ .rotary0_down_key = KEY_DOWN, ++ ++ .debounce_interval = 30, ++}; ++ ++static void __init mainstone_init_keypad(void) ++{ ++ pxa_gpio_mode(100 | GPIO_ALT_FN_1_IN); /* MKIN0 */ ++ pxa_gpio_mode(101 | GPIO_ALT_FN_1_IN); /* MKIN1 */ ++ pxa_gpio_mode(102 | GPIO_ALT_FN_1_IN); /* MKIN2 */ ++ pxa_gpio_mode( 97 | GPIO_ALT_FN_3_IN); /* MKIN3 */ ++ pxa_gpio_mode( 98 | GPIO_ALT_FN_3_IN); /* MKIN4 */ ++ pxa_gpio_mode( 99 | GPIO_ALT_FN_3_IN); /* MKIN5 */ ++ pxa_gpio_mode(103 | GPIO_ALT_FN_2_OUT); /* MKOUT0 */ ++ pxa_gpio_mode(104 | GPIO_ALT_FN_2_OUT); /* MKOUT1 */ ++ pxa_gpio_mode(105 | GPIO_ALT_FN_2_OUT); /* MKOUT2 */ ++ pxa_gpio_mode(106 | GPIO_ALT_FN_2_OUT); /* MKOUT3 */ ++ pxa_gpio_mode(107 | GPIO_ALT_FN_2_OUT); /* MKOUT4 */ ++ pxa_gpio_mode(108 | GPIO_ALT_FN_2_OUT); /* MKOUT5 */ ++ pxa_gpio_mode( 93 | GPIO_ALT_FN_1_IN); /* DKIN0 */ ++ pxa_gpio_mode( 94 | GPIO_ALT_FN_1_IN); /* DKIN1 */ ++ ++ pxa_set_keypad_info(&mainstone_keypad_info); ++} ++#else ++static inline void mainstone_init_keypad(void) { } ++#endif ++ + static void __init mainstone_init(void) + { + int SW7 = 0; /* FIXME: get from SCR (Mst doc section 3.2.1.1) */ +@@ -520,6 +587,8 @@ + pxa_set_mci_info(&mainstone_mci_platform_data); + pxa_set_ficp_info(&mainstone_ficp_platform_data); + pxa_set_ohci_info(&mainstone_ohci_platform_data); ++ ++ mainstone_init_keypad(); + } + + +diff -NbBur linux-2.6.25-rc4-orig/arch/arm/mach-pxa/pxa27x.c linux-2.6.25-rc4/arch/arm/mach-pxa/pxa27x.c +--- linux-2.6.25-rc4-orig/arch/arm/mach-pxa/pxa27x.c 2008-03-08 18:25:54.000000000 +0100 ++++ linux-2.6.25-rc4/arch/arm/mach-pxa/pxa27x.c 2008-03-08 16:22:35.000000000 +0100 +@@ -151,7 +151,7 @@ + + INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev), + INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev), +- INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL), ++ INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev), + + INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), + INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), +diff -NbBur linux-2.6.25-rc4-orig/arch/arm/mach-pxa/pxa3xx.c linux-2.6.25-rc4/arch/arm/mach-pxa/pxa3xx.c +--- linux-2.6.25-rc4-orig/arch/arm/mach-pxa/pxa3xx.c 2008-03-08 18:25:54.000000000 +0100 ++++ linux-2.6.25-rc4/arch/arm/mach-pxa/pxa3xx.c 2008-03-08 16:22:35.000000000 +0100 +@@ -185,6 +185,7 @@ + PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), + PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev), + PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev), ++ PXA3xx_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev), + + PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), + PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/akita.h linux-2.6.25-rc4/include/asm-arm/arch/akita.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/akita.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/akita.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,32 @@ ++/* ++ * Hardware specific definitions for SL-C1000 (Akita) ++ * ++ * Copyright (c) 2005 Richard Purdie ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++/* Akita IO Expander GPIOs */ ++ ++#define AKITA_IOEXP_RESERVED_7 (1 << 7) ++#define AKITA_IOEXP_IR_ON (1 << 6) ++#define AKITA_IOEXP_AKIN_PULLUP (1 << 5) ++#define AKITA_IOEXP_BACKLIGHT_CONT (1 << 4) ++#define AKITA_IOEXP_BACKLIGHT_ON (1 << 3) ++#define AKITA_IOEXP_MIC_BIAS (1 << 2) ++#define AKITA_IOEXP_RESERVED_1 (1 << 1) ++#define AKITA_IOEXP_RESERVED_0 (1 << 0) ++ ++/* Direction Bitfield 0=output 1=input */ ++#define AKITA_IOEXP_IO_DIR 0 ++/* Default Values */ ++#define AKITA_IOEXP_IO_OUT (AKITA_IOEXP_IR_ON | AKITA_IOEXP_AKIN_PULLUP) ++ ++extern struct platform_device akitaioexp_device; ++ ++void akita_set_ioexp(struct device *dev, unsigned char bitmask); ++void akita_reset_ioexp(struct device *dev, unsigned char bitmask); ++ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/audio.h linux-2.6.25-rc4/include/asm-arm/arch/audio.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/audio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/audio.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,15 @@ ++#ifndef __ASM_ARCH_AUDIO_H__ ++#define __ASM_ARCH_AUDIO_H__ ++ ++#include <sound/core.h> ++#include <sound/pcm.h> ++ ++typedef struct { ++ int (*startup)(struct snd_pcm_substream *, void *); ++ void (*shutdown)(struct snd_pcm_substream *, void *); ++ void (*suspend)(void *); ++ void (*resume)(void *); ++ void *priv; ++} pxa2xx_audio_ops_t; ++ ++#endif +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/bitfield.h linux-2.6.25-rc4/include/asm-arm/arch/bitfield.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/bitfield.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/bitfield.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,113 @@ ++/* ++ * FILE bitfield.h ++ * ++ * Version 1.1 ++ * Author Copyright (c) Marc A. Viredaz, 1998 ++ * DEC Western Research Laboratory, Palo Alto, CA ++ * Date April 1998 (April 1997) ++ * System Advanced RISC Machine (ARM) ++ * Language C or ARM Assembly ++ * Purpose Definition of macros to operate on bit fields. ++ */ ++ ++ ++ ++#ifndef __BITFIELD_H ++#define __BITFIELD_H ++ ++#ifndef __ASSEMBLY__ ++#define UData(Data) ((unsigned long) (Data)) ++#else ++#define UData(Data) (Data) ++#endif ++ ++ ++/* ++ * MACRO: Fld ++ * ++ * Purpose ++ * The macro "Fld" encodes a bit field, given its size and its shift value ++ * with respect to bit 0. ++ * ++ * Note ++ * A more intuitive way to encode bit fields would have been to use their ++ * mask. However, extracting size and shift value information from a bit ++ * field's mask is cumbersome and might break the assembler (255-character ++ * line-size limit). ++ * ++ * Input ++ * Size Size of the bit field, in number of bits. ++ * Shft Shift value of the bit field with respect to bit 0. ++ * ++ * Output ++ * Fld Encoded bit field. ++ */ ++ ++#define Fld(Size, Shft) (((Size) << 16) + (Shft)) ++ ++ ++/* ++ * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit ++ * ++ * Purpose ++ * The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return ++ * the size, shift value, mask, aligned mask, and first bit of a ++ * bit field. ++ * ++ * Input ++ * Field Encoded bit field (using the macro "Fld"). ++ * ++ * Output ++ * FSize Size of the bit field, in number of bits. ++ * FShft Shift value of the bit field with respect to bit 0. ++ * FMsk Mask for the bit field. ++ * FAlnMsk Mask for the bit field, aligned on bit 0. ++ * F1stBit First bit of the bit field. ++ */ ++ ++#define FSize(Field) ((Field) >> 16) ++#define FShft(Field) ((Field) & 0x0000FFFF) ++#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) ++#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) ++#define F1stBit(Field) (UData (1) << FShft (Field)) ++ ++ ++/* ++ * MACRO: FInsrt ++ * ++ * Purpose ++ * The macro "FInsrt" inserts a value into a bit field by shifting the ++ * former appropriately. ++ * ++ * Input ++ * Value Bit-field value. ++ * Field Encoded bit field (using the macro "Fld"). ++ * ++ * Output ++ * FInsrt Bit-field value positioned appropriately. ++ */ ++ ++#define FInsrt(Value, Field) \ ++ (UData (Value) << FShft (Field)) ++ ++ ++/* ++ * MACRO: FExtr ++ * ++ * Purpose ++ * The macro "FExtr" extracts the value of a bit field by masking and ++ * shifting it appropriately. ++ * ++ * Input ++ * Data Data containing the bit-field to be extracted. ++ * Field Encoded bit field (using the macro "Fld"). ++ * ++ * Output ++ * FExtr Bit-field value. ++ */ ++ ++#define FExtr(Data, Field) \ ++ ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) ++ ++ ++#endif /* __BITFIELD_H */ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/cm-x270.h linux-2.6.25-rc4/include/asm-arm/arch/cm-x270.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/cm-x270.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/cm-x270.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,50 @@ ++/* ++ * linux/include/asm/arch-pxa/cm-x270.h ++ * ++ * Copyright Compulab Ltd., 2003, 2007 ++ * Mike Rapoport <mike@compulab.co.il> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++ ++/* CM-x270 device physical addresses */ ++#define CMX270_CS1_PHYS (PXA_CS1_PHYS) ++#define MARATHON_PHYS (PXA_CS2_PHYS) ++#define CMX270_IDE104_PHYS (PXA_CS3_PHYS) ++#define CMX270_IT8152_PHYS (PXA_CS4_PHYS) ++ ++/* Statically mapped regions */ ++#define CMX270_VIRT_BASE (0xe8000000) ++#define CMX270_IT8152_VIRT (CMX270_VIRT_BASE) ++#define CMX270_IDE104_VIRT (CMX270_IT8152_VIRT + SZ_64M) ++ ++/* GPIO related definitions */ ++#define GPIO_IT8152_IRQ (22) ++ ++#define IRQ_GPIO_IT8152_IRQ IRQ_GPIO(GPIO_IT8152_IRQ) ++#define PME_IRQ IRQ_GPIO(0) ++#define CMX270_IDE_IRQ IRQ_GPIO(100) ++#define CMX270_GPIRQ1 IRQ_GPIO(101) ++#define CMX270_TOUCHIRQ IRQ_GPIO(96) ++#define CMX270_ETHIRQ IRQ_GPIO(10) ++#define CMX270_GFXIRQ IRQ_GPIO(95) ++#define CMX270_NANDIRQ IRQ_GPIO(89) ++#define CMX270_MMC_IRQ IRQ_GPIO(83) ++ ++/* PCMCIA related definitions */ ++#define PCC_DETECT(x) (GPLR(84 - (x)) & GPIO_bit(84 - (x))) ++#define PCC_READY(x) (GPLR(82 - (x)) & GPIO_bit(82 - (x))) ++ ++#define PCMCIA_S0_CD_VALID IRQ_GPIO(84) ++#define PCMCIA_S0_CD_VALID_EDGE GPIO_BOTH_EDGES ++ ++#define PCMCIA_S1_CD_VALID IRQ_GPIO(83) ++#define PCMCIA_S1_CD_VALID_EDGE GPIO_BOTH_EDGES ++ ++#define PCMCIA_S0_RDYINT IRQ_GPIO(82) ++#define PCMCIA_S1_RDYINT IRQ_GPIO(81) ++ ++#define PCMCIA_RESET_GPIO 53 +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/colibri.h linux-2.6.25-rc4/include/asm-arm/arch/colibri.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/colibri.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/colibri.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,19 @@ ++#ifndef _COLIBRI_H_ ++#define _COLIBRI_H_ ++ ++/* physical memory regions */ ++#define COLIBRI_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */ ++#define COLIBRI_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */ ++#define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */ ++ ++/* virtual memory regions */ ++#define COLIBRI_DISK_VIRT 0xF0000000 /* Disk On Chip region */ ++ ++/* size of flash */ ++#define COLIBRI_FLASH_SIZE 0x02000000 /* Flash size 32 MB */ ++ ++/* Ethernet Controller Davicom DM9000 */ ++#define GPIO_DM9000 114 ++#define COLIBRI_ETH_IRQ IRQ_GPIO(GPIO_DM9000) ++ ++#endif /* _COLIBRI_H_ */ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/corgi.h linux-2.6.25-rc4/include/asm-arm/arch/corgi.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/corgi.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/corgi.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,109 @@ ++/* ++ * Hardware specific definitions for SL-C7xx series of PDAs ++ * ++ * Copyright (c) 2004-2005 Richard Purdie ++ * ++ * Based on Sharp's 2.4 kernel patches ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++#ifndef __ASM_ARCH_CORGI_H ++#define __ASM_ARCH_CORGI_H 1 ++ ++ ++/* ++ * Corgi (Non Standard) GPIO Definitions ++ */ ++#define CORGI_GPIO_KEY_INT (0) /* Keyboard Interrupt */ ++#define CORGI_GPIO_AC_IN (1) /* Charger Detection */ ++#define CORGI_GPIO_WAKEUP (3) /* System wakeup notification? */ ++#define CORGI_GPIO_AK_INT (4) /* Headphone Jack Control Interrupt */ ++#define CORGI_GPIO_TP_INT (5) /* Touch Panel Interrupt */ ++#define CORGI_GPIO_nSD_WP (7) /* SD Write Protect? */ ++#define CORGI_GPIO_nSD_DETECT (9) /* MMC/SD Card Detect */ ++#define CORGI_GPIO_nSD_INT (10) /* SD Interrupt for SDIO? */ ++#define CORGI_GPIO_MAIN_BAT_LOW (11) /* Main Battery Low Notification */ ++#define CORGI_GPIO_BAT_COVER (11) /* Battery Cover Detect */ ++#define CORGI_GPIO_LED_ORANGE (13) /* Orange LED Control */ ++#define CORGI_GPIO_CF_CD (14) /* Compact Flash Card Detect */ ++#define CORGI_GPIO_CHRG_FULL (16) /* Charging Complete Notification */ ++#define CORGI_GPIO_CF_IRQ (17) /* Compact Flash Interrupt */ ++#define CORGI_GPIO_LCDCON_CS (19) /* LCD Control Chip Select */ ++#define CORGI_GPIO_MAX1111_CS (20) /* MAX1111 Chip Select */ ++#define CORGI_GPIO_ADC_TEMP_ON (21) /* Select battery voltage or temperature */ ++#define CORGI_GPIO_IR_ON (22) /* Enable IR Transciever */ ++#define CORGI_GPIO_ADS7846_CS (24) /* ADS7846 Chip Select */ ++#define CORGI_GPIO_SD_PWR (33) /* MMC/SD Power */ ++#define CORGI_GPIO_CHRG_ON (38) /* Enable battery Charging */ ++#define CORGI_GPIO_DISCHARGE_ON (42) /* Enable battery Discharge */ ++#define CORGI_GPIO_CHRG_UKN (43) /* Unknown Charging (Bypass Control?) */ ++#define CORGI_GPIO_HSYNC (44) /* LCD HSync Pulse */ ++#define CORGI_GPIO_USB_PULLUP (45) /* USB show presence to host */ ++ ++ ++/* ++ * Corgi Keyboard Definitions ++ */ ++#define CORGI_KEY_STROBE_NUM (12) ++#define CORGI_KEY_SENSE_NUM (8) ++#define CORGI_GPIO_ALL_STROBE_BIT (0x00003ffc) ++#define CORGI_GPIO_HIGH_SENSE_BIT (0xfc000000) ++#define CORGI_GPIO_HIGH_SENSE_RSHIFT (26) ++#define CORGI_GPIO_LOW_SENSE_BIT (0x00000003) ++#define CORGI_GPIO_LOW_SENSE_LSHIFT (6) ++#define CORGI_GPIO_STROBE_BIT(a) GPIO_bit(66+(a)) ++#define CORGI_GPIO_SENSE_BIT(a) GPIO_bit(58+(a)) ++#define CORGI_GAFR_ALL_STROBE_BIT (0x0ffffff0) ++#define CORGI_GAFR_HIGH_SENSE_BIT (0xfff00000) ++#define CORGI_GAFR_LOW_SENSE_BIT (0x0000000f) ++#define CORGI_GPIO_KEY_SENSE(a) (58+(a)) ++#define CORGI_GPIO_KEY_STROBE(a) (66+(a)) ++ ++ ++/* ++ * Corgi Interrupts ++ */ ++#define CORGI_IRQ_GPIO_KEY_INT IRQ_GPIO(0) ++#define CORGI_IRQ_GPIO_AC_IN IRQ_GPIO(1) ++#define CORGI_IRQ_GPIO_WAKEUP IRQ_GPIO(3) ++#define CORGI_IRQ_GPIO_AK_INT IRQ_GPIO(4) ++#define CORGI_IRQ_GPIO_TP_INT IRQ_GPIO(5) ++#define CORGI_IRQ_GPIO_nSD_DETECT IRQ_GPIO(9) ++#define CORGI_IRQ_GPIO_nSD_INT IRQ_GPIO(10) ++#define CORGI_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(11) ++#define CORGI_IRQ_GPIO_CF_CD IRQ_GPIO(14) ++#define CORGI_IRQ_GPIO_CHRG_FULL IRQ_GPIO(16) /* Battery fully charged */ ++#define CORGI_IRQ_GPIO_CF_IRQ IRQ_GPIO(17) ++#define CORGI_IRQ_GPIO_KEY_SENSE(a) IRQ_GPIO(58+(a)) /* Keyboard Sense lines */ ++ ++ ++/* ++ * Corgi SCOOP GPIOs and Config ++ */ ++#define CORGI_SCP_LED_GREEN SCOOP_GPCR_PA11 ++#define CORGI_SCP_SWA SCOOP_GPCR_PA12 /* Hinge Switch A */ ++#define CORGI_SCP_SWB SCOOP_GPCR_PA13 /* Hinge Switch B */ ++#define CORGI_SCP_MUTE_L SCOOP_GPCR_PA14 ++#define CORGI_SCP_MUTE_R SCOOP_GPCR_PA15 ++#define CORGI_SCP_AKIN_PULLUP SCOOP_GPCR_PA16 ++#define CORGI_SCP_APM_ON SCOOP_GPCR_PA17 ++#define CORGI_SCP_BACKLIGHT_CONT SCOOP_GPCR_PA18 ++#define CORGI_SCP_MIC_BIAS SCOOP_GPCR_PA19 ++ ++#define CORGI_SCOOP_IO_DIR ( CORGI_SCP_LED_GREEN | CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R | \ ++ CORGI_SCP_AKIN_PULLUP | CORGI_SCP_APM_ON | CORGI_SCP_BACKLIGHT_CONT | \ ++ CORGI_SCP_MIC_BIAS ) ++#define CORGI_SCOOP_IO_OUT ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R ) ++ ++ ++/* ++ * Shared data structures ++ */ ++extern struct platform_device corgiscoop_device; ++extern struct platform_device corgissp_device; ++ ++#endif /* __ASM_ARCH_CORGI_H */ ++ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/debug-macro.S linux-2.6.25-rc4/include/asm-arm/arch/debug-macro.S +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/debug-macro.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/debug-macro.S 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,25 @@ ++/* linux/include/asm-arm/arch-pxa/debug-macro.S ++ * ++ * Debugging macro include header ++ * ++ * Copyright (C) 1994-1999 Russell King ++ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++*/ ++ ++#include "hardware.h" ++ ++ .macro addruart,rx ++ mrc p15, 0, \rx, c1, c0 ++ tst \rx, #1 @ MMU enabled? ++ moveq \rx, #0x40000000 @ physical ++ movne \rx, #io_p2v(0x40000000) @ virtual ++ orr \rx, \rx, #0x00100000 ++ .endm ++ ++#define UART_SHIFT 2 ++#include <asm/hardware/debug-8250.S> +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/dma.h linux-2.6.25-rc4/include/asm-arm/arch/dma.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/dma.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/dma.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,50 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/dma.h ++ * ++ * Author: Nicolas Pitre ++ * Created: Jun 15, 2001 ++ * Copyright: MontaVista Software, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#ifndef __ASM_ARCH_DMA_H ++#define __ASM_ARCH_DMA_H ++ ++/* ++ * Descriptor structure for PXA's DMA engine ++ * Note: this structure must always be aligned to a 16-byte boundary. ++ */ ++ ++typedef struct pxa_dma_desc { ++ volatile u32 ddadr; /* Points to the next descriptor + flags */ ++ volatile u32 dsadr; /* DSADR value for the current transfer */ ++ volatile u32 dtadr; /* DTADR value for the current transfer */ ++ volatile u32 dcmd; /* DCMD value for the current transfer */ ++} pxa_dma_desc; ++ ++typedef enum { ++ DMA_PRIO_HIGH = 0, ++ DMA_PRIO_MEDIUM = 1, ++ DMA_PRIO_LOW = 2 ++} pxa_dma_prio; ++ ++#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) ++#define HAVE_ARCH_PCI_SET_DMA_MASK 1 ++#endif ++ ++/* ++ * DMA registration ++ */ ++ ++int __init pxa_init_dma(int num_ch); ++ ++int pxa_request_dma (char *name, ++ pxa_dma_prio prio, ++ void (*irq_handler)(int, void *), ++ void *data); ++ ++void pxa_free_dma (int dma_ch); ++ ++#endif /* _ASM_ARCH_DMA_H */ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/entry-macro.S linux-2.6.25-rc4/include/asm-arm/arch/entry-macro.S +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/entry-macro.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/entry-macro.S 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,57 @@ ++/* ++ * include/asm-arm/arch-pxa/entry-macro.S ++ * ++ * Low-level IRQ helper macros for PXA-based platforms ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++#include <asm/hardware.h> ++#include <asm/arch/irqs.h> ++ ++ .macro disable_fiq ++ .endm ++ ++ .macro get_irqnr_preamble, base, tmp ++ .endm ++ ++ .macro arch_ret_to_user, tmp1, tmp2 ++ .endm ++ ++ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ++ mrc p15, 0, \tmp, c0, c0, 0 @ CPUID ++ mov \tmp, \tmp, lsr #13 ++ and \tmp, \tmp, #0x7 @ Core G ++ cmp \tmp, #1 ++ bhi 1004f ++ ++ mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000 ++ add \base, \base, #0x00d00000 ++ ldr \irqstat, [\base, #0] @ ICIP ++ ldr \irqnr, [\base, #4] @ ICMR ++ b 1002f ++ ++1004: ++ mrc p6, 0, \irqstat, c6, c0, 0 @ ICIP2 ++ mrc p6, 0, \irqnr, c7, c0, 0 @ ICMR2 ++ ands \irqnr, \irqstat, \irqnr ++ beq 1003f ++ rsb \irqstat, \irqnr, #0 ++ and \irqstat, \irqstat, \irqnr ++ clz \irqnr, \irqstat ++ rsb \irqnr, \irqnr, #31 ++ add \irqnr, \irqnr, #32 ++ b 1001f ++1003: ++ mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP ++ mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR ++1002: ++ ands \irqnr, \irqstat, \irqnr ++ beq 1001f ++ rsb \irqstat, \irqnr, #0 ++ and \irqstat, \irqstat, \irqnr ++ clz \irqnr, \irqstat ++ rsb \irqnr, \irqnr, #31 ++1001: ++ .endm +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/gpio.h linux-2.6.25-rc4/include/asm-arm/arch/gpio.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/gpio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/gpio.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,65 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/gpio.h ++ * ++ * PXA GPIO wrappers for arch-neutral GPIO calls ++ * ++ * Written by Philipp Zabel <philipp.zabel@gmail.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#ifndef __ASM_ARCH_PXA_GPIO_H ++#define __ASM_ARCH_PXA_GPIO_H ++ ++#include <asm/arch/pxa-regs.h> ++#include <asm/irq.h> ++#include <asm/hardware.h> ++ ++#include <asm-generic/gpio.h> ++ ++ ++/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85). ++ * Those cases currently cause holes in the GPIO number space. ++ */ ++#define NR_BUILTIN_GPIO 128 ++ ++static inline int gpio_get_value(unsigned gpio) ++{ ++ if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) ++ return GPLR(gpio) & GPIO_bit(gpio); ++ else ++ return __gpio_get_value(gpio); ++} ++ ++static inline void gpio_set_value(unsigned gpio, int value) ++{ ++ if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) { ++ if (value) ++ GPSR(gpio) = GPIO_bit(gpio); ++ else ++ GPCR(gpio) = GPIO_bit(gpio); ++ } else { ++ __gpio_set_value(gpio, value); ++ } ++} ++ ++#define gpio_cansleep __gpio_cansleep ++ ++#define gpio_to_irq(gpio) IRQ_GPIO(gpio) ++#define irq_to_gpio(irq) IRQ_TO_GPIO(irq) ++ ++ ++#endif +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/hardware.h linux-2.6.25-rc4/include/asm-arm/arch/hardware.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/hardware.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/hardware.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,216 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/hardware.h ++ * ++ * Author: Nicolas Pitre ++ * Created: Jun 15, 2001 ++ * Copyright: MontaVista Software Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __ASM_ARCH_HARDWARE_H ++#define __ASM_ARCH_HARDWARE_H ++ ++/* ++ * We requires absolute addresses. ++ */ ++#define PCIO_BASE 0 ++ ++/* ++ * Workarounds for at least 2 errata so far require this. ++ * The mapping is set in mach-pxa/generic.c. ++ */ ++#define UNCACHED_PHYS_0 0xff000000 ++#define UNCACHED_ADDR UNCACHED_PHYS_0 ++ ++/* ++ * Intel PXA2xx internal register mapping: ++ * ++ * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff ++ * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff ++ * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff ++ * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff ++ * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff ++ * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff ++ * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff ++ * ++ * Note that not all PXA2xx chips implement all those addresses, and the ++ * kernel only maps the minimum needed range of this mapping. ++ */ ++#define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) ++#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1)) ++ ++#ifndef __ASSEMBLY__ ++ ++# define __REG(x) (*((volatile u32 *)io_p2v(x))) ++ ++/* With indexed regs we don't want to feed the index through io_p2v() ++ especially if it is a variable, otherwise horrible code will result. */ ++# define __REG2(x,y) \ ++ (*(volatile u32 *)((u32)&__REG(x) + (y))) ++ ++# define __PREG(x) (io_v2p((u32)&(x))) ++ ++#else ++ ++# define __REG(x) io_p2v(x) ++# define __PREG(x) io_v2p(x) ++ ++#endif ++ ++#ifndef __ASSEMBLY__ ++ ++#ifdef CONFIG_PXA25x ++#define __cpu_is_pxa21x(id) \ ++ ({ \ ++ unsigned int _id = (id) >> 4 & 0xf3f; \ ++ _id == 0x212; \ ++ }) ++ ++#define __cpu_is_pxa25x(id) \ ++ ({ \ ++ unsigned int _id = (id) >> 4 & 0xfff; \ ++ _id == 0x2d0 || _id == 0x290; \ ++ }) ++#else ++#define __cpu_is_pxa21x(id) (0) ++#define __cpu_is_pxa25x(id) (0) ++#endif ++ ++#ifdef CONFIG_PXA27x ++#define __cpu_is_pxa27x(id) \ ++ ({ \ ++ unsigned int _id = (id) >> 4 & 0xfff; \ ++ _id == 0x411; \ ++ }) ++#else ++#define __cpu_is_pxa27x(id) (0) ++#endif ++ ++#ifdef CONFIG_CPU_PXA300 ++#define __cpu_is_pxa300(id) \ ++ ({ \ ++ unsigned int _id = (id) >> 4 & 0xfff; \ ++ _id == 0x688; \ ++ }) ++#else ++#define __cpu_is_pxa300(id) (0) ++#endif ++ ++#ifdef CONFIG_CPU_PXA310 ++#define __cpu_is_pxa310(id) \ ++ ({ \ ++ unsigned int _id = (id) >> 4 & 0xfff; \ ++ _id == 0x689; \ ++ }) ++#else ++#define __cpu_is_pxa310(id) (0) ++#endif ++ ++#ifdef CONFIG_CPU_PXA320 ++#define __cpu_is_pxa320(id) \ ++ ({ \ ++ unsigned int _id = (id) >> 4 & 0xfff; \ ++ _id == 0x603 || _id == 0x682; \ ++ }) ++#else ++#define __cpu_is_pxa320(id) (0) ++#endif ++ ++#define cpu_is_pxa21x() \ ++ ({ \ ++ __cpu_is_pxa21x(read_cpuid_id()); \ ++ }) ++ ++#define cpu_is_pxa25x() \ ++ ({ \ ++ __cpu_is_pxa25x(read_cpuid_id()); \ ++ }) ++ ++#define cpu_is_pxa27x() \ ++ ({ \ ++ __cpu_is_pxa27x(read_cpuid_id()); \ ++ }) ++ ++#define cpu_is_pxa300() \ ++ ({ \ ++ __cpu_is_pxa300(read_cpuid_id()); \ ++ }) ++ ++#define cpu_is_pxa310() \ ++ ({ \ ++ __cpu_is_pxa310(read_cpuid_id()); \ ++ }) ++ ++#define cpu_is_pxa320() \ ++ ({ \ ++ __cpu_is_pxa320(read_cpuid_id()); \ ++ }) ++ ++/* ++ * CPUID Core Generation Bit ++ * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x ++ * == 0x3 for pxa300/pxa310/pxa320 ++ */ ++#define __cpu_is_pxa2xx(id) \ ++ ({ \ ++ unsigned int _id = (id) >> 13 & 0x7; \ ++ _id <= 0x2; \ ++ }) ++ ++#define __cpu_is_pxa3xx(id) \ ++ ({ \ ++ unsigned int _id = (id) >> 13 & 0x7; \ ++ _id == 0x3; \ ++ }) ++ ++#define cpu_is_pxa2xx() \ ++ ({ \ ++ __cpu_is_pxa2xx(read_cpuid_id()); \ ++ }) ++ ++#define cpu_is_pxa3xx() \ ++ ({ \ ++ __cpu_is_pxa3xx(read_cpuid_id()); \ ++ }) ++ ++/* ++ * Handy routine to set GPIO alternate functions ++ */ ++extern int pxa_gpio_mode( int gpio_mode ); ++ ++/* ++ * Return GPIO level, nonzero means high, zero is low ++ */ ++extern int pxa_gpio_get_value(unsigned gpio); ++ ++/* ++ * Set output GPIO level ++ */ ++extern void pxa_gpio_set_value(unsigned gpio, int value); ++ ++/* ++ * Routine to enable or disable CKEN ++ */ ++static inline void __deprecated pxa_set_cken(int clock, int enable) ++{ ++ extern void __pxa_set_cken(int clock, int enable); ++ __pxa_set_cken(clock, enable); ++} ++ ++/* ++ * return current memory and LCD clock frequency in units of 10kHz ++ */ ++extern unsigned int get_memclk_frequency_10khz(void); ++ ++#endif ++ ++#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) ++#define PCIBIOS_MIN_IO 0 ++#define PCIBIOS_MIN_MEM 0 ++#define pcibios_assign_all_busses() 1 ++#endif ++ ++#endif /* _ASM_ARCH_HARDWARE_H */ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/i2c.h linux-2.6.25-rc4/include/asm-arm/arch/i2c.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/i2c.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/i2c.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,77 @@ ++/* ++ * i2c_pxa.h ++ * ++ * Copyright (C) 2002 Intrinsyc Software Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++#ifndef _I2C_PXA_H_ ++#define _I2C_PXA_H_ ++ ++#if 0 ++#define DEF_TIMEOUT 3 ++#else ++/* need a longer timeout if we're dealing with the fact we may well be ++ * looking at a multi-master environment ++*/ ++#define DEF_TIMEOUT 32 ++#endif ++ ++#define BUS_ERROR (-EREMOTEIO) ++#define XFER_NAKED (-ECONNREFUSED) ++#define I2C_RETRY (-2000) /* an error has occurred retry transmit */ ++ ++/* ICR initialize bit values ++* ++* 15. FM 0 (100 Khz operation) ++* 14. UR 0 (No unit reset) ++* 13. SADIE 0 (Disables the unit from interrupting on slave addresses ++* matching its slave address) ++* 12. ALDIE 0 (Disables the unit from interrupt when it loses arbitration ++* in master mode) ++* 11. SSDIE 0 (Disables interrupts from a slave stop detected, in slave mode) ++* 10. BEIE 1 (Enable interrupts from detected bus errors, no ACK sent) ++* 9. IRFIE 1 (Enable interrupts from full buffer received) ++* 8. ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty) ++* 7. GCD 1 (Disables i2c unit response to general call messages as a slave) ++* 6. IUE 0 (Disable unit until we change settings) ++* 5. SCLE 1 (Enables the i2c clock output for master mode (drives SCL) ++* 4. MA 0 (Only send stop with the ICR stop bit) ++* 3. TB 0 (We are not transmitting a byte initially) ++* 2. ACKNAK 0 (Send an ACK after the unit receives a byte) ++* 1. STOP 0 (Do not send a STOP) ++* 0. START 0 (Do not send a START) ++* ++*/ ++#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) ++ ++/* I2C status register init values ++ * ++ * 10. BED 1 (Clear bus error detected) ++ * 9. SAD 1 (Clear slave address detected) ++ * 7. IRF 1 (Clear IDBR Receive Full) ++ * 6. ITE 1 (Clear IDBR Transmit Empty) ++ * 5. ALD 1 (Clear Arbitration Loss Detected) ++ * 4. SSD 1 (Clear Slave Stop Detected) ++ */ ++#define I2C_ISR_INIT 0x7FF /* status register init */ ++ ++struct i2c_slave_client; ++ ++struct i2c_pxa_platform_data { ++ unsigned int slave_addr; ++ struct i2c_slave_client *slave; ++ unsigned int class; ++ int use_pio; ++}; ++ ++extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info); ++ ++#ifdef CONFIG_PXA27x ++extern void pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info); ++#endif ++ ++#endif +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/idp.h linux-2.6.25-rc4/include/asm-arm/arch/idp.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/idp.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/idp.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,199 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/idp.h ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc. ++ * ++ * 2001-09-13: Cliff Brake <cbrake@accelent.com> ++ * Initial code ++ * ++ * 2005-02-15: Cliff Brake <cliff.brake@gmail.com> ++ * <http://www.vibren.com> <http://bec-systems.com> ++ * Changes for 2.6 kernel. ++ */ ++ ++ ++/* ++ * Note: this file must be safe to include in assembly files ++ * ++ * Support for the Vibren PXA255 IDP requires rev04 or later ++ * IDP hardware. ++ */ ++ ++ ++#define IDP_FLASH_PHYS (PXA_CS0_PHYS) ++#define IDP_ALT_FLASH_PHYS (PXA_CS1_PHYS) ++#define IDP_MEDIAQ_PHYS (PXA_CS3_PHYS) ++#define IDP_IDE_PHYS (PXA_CS5_PHYS + 0x03000000) ++#define IDP_ETH_PHYS (PXA_CS5_PHYS + 0x03400000) ++#define IDP_COREVOLT_PHYS (PXA_CS5_PHYS + 0x03800000) ++#define IDP_CPLD_PHYS (PXA_CS5_PHYS + 0x03C00000) ++ ++ ++/* ++ * virtual memory map ++ */ ++ ++#define IDP_COREVOLT_VIRT (0xf0000000) ++#define IDP_COREVOLT_SIZE (1*1024*1024) ++ ++#define IDP_CPLD_VIRT (IDP_COREVOLT_VIRT + IDP_COREVOLT_SIZE) ++#define IDP_CPLD_SIZE (1*1024*1024) ++ ++#if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000 ++#error Your custom IO space is getting a bit large !! ++#endif ++ ++#define CPLD_P2V(x) ((x) - IDP_CPLD_PHYS + IDP_CPLD_VIRT) ++#define CPLD_V2P(x) ((x) - IDP_CPLD_VIRT + IDP_CPLD_PHYS) ++ ++#ifndef __ASSEMBLY__ ++# define __CPLD_REG(x) (*((volatile unsigned long *)CPLD_P2V(x))) ++#else ++# define __CPLD_REG(x) CPLD_P2V(x) ++#endif ++ ++/* board level registers in the CPLD: (offsets from CPLD_VIRT) */ ++ ++#define _IDP_CPLD_REV (IDP_CPLD_PHYS + 0x00) ++#define _IDP_CPLD_PERIPH_PWR (IDP_CPLD_PHYS + 0x04) ++#define _IDP_CPLD_LED_CONTROL (IDP_CPLD_PHYS + 0x08) ++#define _IDP_CPLD_KB_COL_HIGH (IDP_CPLD_PHYS + 0x0C) ++#define _IDP_CPLD_KB_COL_LOW (IDP_CPLD_PHYS + 0x10) ++#define _IDP_CPLD_PCCARD_EN (IDP_CPLD_PHYS + 0x14) ++#define _IDP_CPLD_GPIOH_DIR (IDP_CPLD_PHYS + 0x18) ++#define _IDP_CPLD_GPIOH_VALUE (IDP_CPLD_PHYS + 0x1C) ++#define _IDP_CPLD_GPIOL_DIR (IDP_CPLD_PHYS + 0x20) ++#define _IDP_CPLD_GPIOL_VALUE (IDP_CPLD_PHYS + 0x24) ++#define _IDP_CPLD_PCCARD_PWR (IDP_CPLD_PHYS + 0x28) ++#define _IDP_CPLD_MISC_CTRL (IDP_CPLD_PHYS + 0x2C) ++#define _IDP_CPLD_LCD (IDP_CPLD_PHYS + 0x30) ++#define _IDP_CPLD_FLASH_WE (IDP_CPLD_PHYS + 0x34) ++ ++#define _IDP_CPLD_KB_ROW (IDP_CPLD_PHYS + 0x50) ++#define _IDP_CPLD_PCCARD0_STATUS (IDP_CPLD_PHYS + 0x54) ++#define _IDP_CPLD_PCCARD1_STATUS (IDP_CPLD_PHYS + 0x58) ++#define _IDP_CPLD_MISC_STATUS (IDP_CPLD_PHYS + 0x5C) ++ ++/* FPGA register virtual addresses */ ++ ++#define IDP_CPLD_REV __CPLD_REG(_IDP_CPLD_REV) ++#define IDP_CPLD_PERIPH_PWR __CPLD_REG(_IDP_CPLD_PERIPH_PWR) ++#define IDP_CPLD_LED_CONTROL __CPLD_REG(_IDP_CPLD_LED_CONTROL) ++#define IDP_CPLD_KB_COL_HIGH __CPLD_REG(_IDP_CPLD_KB_COL_HIGH) ++#define IDP_CPLD_KB_COL_LOW __CPLD_REG(_IDP_CPLD_KB_COL_LOW) ++#define IDP_CPLD_PCCARD_EN __CPLD_REG(_IDP_CPLD_PCCARD_EN) ++#define IDP_CPLD_GPIOH_DIR __CPLD_REG(_IDP_CPLD_GPIOH_DIR) ++#define IDP_CPLD_GPIOH_VALUE __CPLD_REG(_IDP_CPLD_GPIOH_VALUE) ++#define IDP_CPLD_GPIOL_DIR __CPLD_REG(_IDP_CPLD_GPIOL_DIR) ++#define IDP_CPLD_GPIOL_VALUE __CPLD_REG(_IDP_CPLD_GPIOL_VALUE) ++#define IDP_CPLD_PCCARD_PWR __CPLD_REG(_IDP_CPLD_PCCARD_PWR) ++#define IDP_CPLD_MISC_CTRL __CPLD_REG(_IDP_CPLD_MISC_CTRL) ++#define IDP_CPLD_LCD __CPLD_REG(_IDP_CPLD_LCD) ++#define IDP_CPLD_FLASH_WE __CPLD_REG(_IDP_CPLD_FLASH_WE) ++ ++#define IDP_CPLD_KB_ROW __CPLD_REG(_IDP_CPLD_KB_ROW) ++#define IDP_CPLD_PCCARD0_STATUS __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS) ++#define IDP_CPLD_PCCARD1_STATUS __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS) ++#define IDP_CPLD_MISC_STATUS __CPLD_REG(_IDP_CPLD_MISC_STATUS) ++ ++ ++/* ++ * Bit masks for various registers ++ */ ++ ++// IDP_CPLD_PCCARD_PWR ++#define PCC0_PWR0 (1 << 0) ++#define PCC0_PWR1 (1 << 1) ++#define PCC0_PWR2 (1 << 2) ++#define PCC0_PWR3 (1 << 3) ++#define PCC1_PWR0 (1 << 4) ++#define PCC1_PWR1 (1 << 5) ++#define PCC1_PWR2 (1 << 6) ++#define PCC1_PWR3 (1 << 7) ++ ++// IDP_CPLD_PCCARD_EN ++#define PCC0_RESET (1 << 6) ++#define PCC1_RESET (1 << 7) ++#define PCC0_ENABLE (1 << 0) ++#define PCC1_ENABLE (1 << 1) ++ ++// IDP_CPLD_PCCARDx_STATUS ++#define _PCC_WRPROT (1 << 7) // 7-4 read as low true ++#define _PCC_RESET (1 << 6) ++#define _PCC_IRQ (1 << 5) ++#define _PCC_INPACK (1 << 4) ++#define PCC_BVD2 (1 << 3) ++#define PCC_BVD1 (1 << 2) ++#define PCC_VS2 (1 << 1) ++#define PCC_VS1 (1 << 0) ++ ++#define PCC_DETECT(x) (GPLR(7 + (x)) & GPIO_bit(7 + (x))) ++ ++/* A listing of interrupts used by external hardware devices */ ++ ++#define TOUCH_PANEL_IRQ IRQ_GPIO(5) ++#define IDE_IRQ IRQ_GPIO(21) ++ ++#define TOUCH_PANEL_IRQ_EDGE IRQT_FALLING ++ ++#define ETHERNET_IRQ IRQ_GPIO(4) ++#define ETHERNET_IRQ_EDGE IRQT_RISING ++ ++#define IDE_IRQ_EDGE IRQT_RISING ++ ++#define PCMCIA_S0_CD_VALID IRQ_GPIO(7) ++#define PCMCIA_S0_CD_VALID_EDGE IRQT_BOTHEDGE ++ ++#define PCMCIA_S1_CD_VALID IRQ_GPIO(8) ++#define PCMCIA_S1_CD_VALID_EDGE IRQT_BOTHEDGE ++ ++#define PCMCIA_S0_RDYINT IRQ_GPIO(19) ++#define PCMCIA_S1_RDYINT IRQ_GPIO(22) ++ ++ ++/* ++ * Macros for LED Driver ++ */ ++ ++/* leds 0 = ON */ ++#define IDP_HB_LED (1<<5) ++#define IDP_BUSY_LED (1<<6) ++ ++#define IDP_LEDS_MASK (IDP_HB_LED | IDP_BUSY_LED) ++ ++/* ++ * macros for MTD driver ++ */ ++ ++#define FLASH_WRITE_PROTECT_DISABLE() ((IDP_CPLD_FLASH_WE) &= ~(0x1)) ++#define FLASH_WRITE_PROTECT_ENABLE() ((IDP_CPLD_FLASH_WE) |= (0x1)) ++ ++/* ++ * macros for matrix keyboard driver ++ */ ++ ++#define KEYBD_MATRIX_NUMBER_INPUTS 7 ++#define KEYBD_MATRIX_NUMBER_OUTPUTS 14 ++ ++#define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC FALSE ++#define KEYBD_MATRIX_INVERT_INPUT_LOGIC FALSE ++ ++#define KEYBD_MATRIX_SETTLING_TIME_US 100 ++#define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT 2 ++ ++#define KEYBD_MATRIX_SET_OUTPUTS(outputs) \ ++{\ ++ IDP_CPLD_KB_COL_LOW = outputs;\ ++ IDP_CPLD_KB_COL_HIGH = outputs >> 7;\ ++} ++ ++#define KEYBD_MATRIX_GET_INPUTS(inputs) \ ++{\ ++ inputs = (IDP_CPLD_KB_ROW & 0x7f);\ ++} ++ ++ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/io.h linux-2.6.25-rc4/include/asm-arm/arch/io.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/io.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/io.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,20 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/io.h ++ * ++ * Copied from asm/arch/sa1100/io.h ++ */ ++#ifndef __ASM_ARM_ARCH_IO_H ++#define __ASM_ARM_ARCH_IO_H ++ ++#include <asm/hardware.h> ++ ++#define IO_SPACE_LIMIT 0xffffffff ++ ++/* ++ * We don't actually have real ISA nor PCI buses, but there is so many ++ * drivers out there that might just work if we fake them... ++ */ ++#define __io(a) ((void __iomem *)(a)) ++#define __mem_pci(a) (a) ++ ++#endif +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/irda.h linux-2.6.25-rc4/include/asm-arm/arch/irda.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/irda.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/irda.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,17 @@ ++#ifndef ASMARM_ARCH_IRDA_H ++#define ASMARM_ARCH_IRDA_H ++ ++/* board specific transceiver capabilities */ ++ ++#define IR_OFF 1 ++#define IR_SIRMODE 2 ++#define IR_FIRMODE 4 ++ ++struct pxaficp_platform_data { ++ int transceiver_cap; ++ void (*transceiver_mode)(struct device *dev, int mode); ++}; ++ ++extern void pxa_set_ficp_info(struct pxaficp_platform_data *info); ++ ++#endif +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/irqs.h linux-2.6.25-rc4/include/asm-arm/arch/irqs.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/irqs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/irqs.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,257 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/irqs.h ++ * ++ * Author: Nicolas Pitre ++ * Created: Jun 15, 2001 ++ * Copyright: MontaVista Software Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++ ++#define PXA_IRQ(x) (x) ++ ++#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) ++#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ ++#define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */ ++#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */ ++#define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI) */ ++#define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */ ++#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */ ++#define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */ ++#endif ++ ++#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */ ++#define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */ ++#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */ ++#define IRQ_GPIO1 PXA_IRQ(9) /* GPIO1 Edge Detect */ ++#define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */ ++#define IRQ_USB PXA_IRQ(11) /* USB Service */ ++#define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */ ++#define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt */ ++#define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */ ++#define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */ ++#define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */ ++#define IRQ_NSSP PXA_IRQ(16) /* Network SSP Service Request (PXA25x) */ ++#define IRQ_SSP2 PXA_IRQ(16) /* SSP2 interrupt (PXA27x) */ ++#define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */ ++#define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */ ++#define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */ ++#define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */ ++#define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */ ++#define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/ ++#define IRQ_MMC PXA_IRQ(23) /* MMC Status/Error Detection */ ++#define IRQ_SSP PXA_IRQ(24) /* SSP Service Request */ ++#define IRQ_DMA PXA_IRQ(25) /* DMA Channel Service Request */ ++#define IRQ_OST0 PXA_IRQ(26) /* OS Timer match 0 */ ++#define IRQ_OST1 PXA_IRQ(27) /* OS Timer match 1 */ ++#define IRQ_OST2 PXA_IRQ(28) /* OS Timer match 2 */ ++#define IRQ_OST3 PXA_IRQ(29) /* OS Timer match 3 */ ++#define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */ ++#define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */ ++ ++#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) ++#define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */ ++#define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */ ++#endif ++ ++#ifdef CONFIG_PXA3xx ++#define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request */ ++#define IRQ_CIR PXA_IRQ(34) /* Consumer IR */ ++#define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */ ++#define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */ ++#define IRQ_GRPHICS PXA_IRQ(39) /* Graphics Controller */ ++#define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */ ++#define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */ ++#define IRQ_NAND PXA_IRQ(45) /* NAND Controller */ ++#define IRQ_USB2 PXA_IRQ(46) /* USB 2.0 Device Controller */ ++#define IRQ_WAKEUP0 PXA_IRQ(49) /* EXT_WAKEUP0 */ ++#define IRQ_WAKEUP1 PXA_IRQ(50) /* EXT_WAKEUP1 */ ++#define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */ ++#define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */ ++#endif ++ ++#define PXA_GPIO_IRQ_BASE (64) ++#define PXA_GPIO_IRQ_NUM (128) ++ ++#define GPIO_2_x_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x)) ++#define IRQ_GPIO(x) (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x)) ++ ++#define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE) ++#define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i)) ++ ++/* ++ * The next 16 interrupts are for board specific purposes. Since ++ * the kernel can only run on one machine at a time, we can re-use ++ * these. If you need more, increase IRQ_BOARD_END, but keep it ++ * within sensible limits. ++ */ ++#define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM) ++#define IRQ_BOARD_END (IRQ_BOARD_START + 16) ++ ++#define IRQ_SA1111_START (IRQ_BOARD_END) ++#define IRQ_GPAIN0 (IRQ_BOARD_END + 0) ++#define IRQ_GPAIN1 (IRQ_BOARD_END + 1) ++#define IRQ_GPAIN2 (IRQ_BOARD_END + 2) ++#define IRQ_GPAIN3 (IRQ_BOARD_END + 3) ++#define IRQ_GPBIN0 (IRQ_BOARD_END + 4) ++#define IRQ_GPBIN1 (IRQ_BOARD_END + 5) ++#define IRQ_GPBIN2 (IRQ_BOARD_END + 6) ++#define IRQ_GPBIN3 (IRQ_BOARD_END + 7) ++#define IRQ_GPBIN4 (IRQ_BOARD_END + 8) ++#define IRQ_GPBIN5 (IRQ_BOARD_END + 9) ++#define IRQ_GPCIN0 (IRQ_BOARD_END + 10) ++#define IRQ_GPCIN1 (IRQ_BOARD_END + 11) ++#define IRQ_GPCIN2 (IRQ_BOARD_END + 12) ++#define IRQ_GPCIN3 (IRQ_BOARD_END + 13) ++#define IRQ_GPCIN4 (IRQ_BOARD_END + 14) ++#define IRQ_GPCIN5 (IRQ_BOARD_END + 15) ++#define IRQ_GPCIN6 (IRQ_BOARD_END + 16) ++#define IRQ_GPCIN7 (IRQ_BOARD_END + 17) ++#define IRQ_MSTXINT (IRQ_BOARD_END + 18) ++#define IRQ_MSRXINT (IRQ_BOARD_END + 19) ++#define IRQ_MSSTOPERRINT (IRQ_BOARD_END + 20) ++#define IRQ_TPTXINT (IRQ_BOARD_END + 21) ++#define IRQ_TPRXINT (IRQ_BOARD_END + 22) ++#define IRQ_TPSTOPERRINT (IRQ_BOARD_END + 23) ++#define SSPXMTINT (IRQ_BOARD_END + 24) ++#define SSPRCVINT (IRQ_BOARD_END + 25) ++#define SSPROR (IRQ_BOARD_END + 26) ++#define AUDXMTDMADONEA (IRQ_BOARD_END + 32) ++#define AUDRCVDMADONEA (IRQ_BOARD_END + 33) ++#define AUDXMTDMADONEB (IRQ_BOARD_END + 34) ++#define AUDRCVDMADONEB (IRQ_BOARD_END + 35) ++#define AUDTFSR (IRQ_BOARD_END + 36) ++#define AUDRFSR (IRQ_BOARD_END + 37) ++#define AUDTUR (IRQ_BOARD_END + 38) ++#define AUDROR (IRQ_BOARD_END + 39) ++#define AUDDTS (IRQ_BOARD_END + 40) ++#define AUDRDD (IRQ_BOARD_END + 41) ++#define AUDSTO (IRQ_BOARD_END + 42) ++#define IRQ_USBPWR (IRQ_BOARD_END + 43) ++#define IRQ_HCIM (IRQ_BOARD_END + 44) ++#define IRQ_HCIBUFFACC (IRQ_BOARD_END + 45) ++#define IRQ_HCIRMTWKP (IRQ_BOARD_END + 46) ++#define IRQ_NHCIMFCIR (IRQ_BOARD_END + 47) ++#define IRQ_USB_PORT_RESUME (IRQ_BOARD_END + 48) ++#define IRQ_S0_READY_NINT (IRQ_BOARD_END + 49) ++#define IRQ_S1_READY_NINT (IRQ_BOARD_END + 50) ++#define IRQ_S0_CD_VALID (IRQ_BOARD_END + 51) ++#define IRQ_S1_CD_VALID (IRQ_BOARD_END + 52) ++#define IRQ_S0_BVD1_STSCHG (IRQ_BOARD_END + 53) ++#define IRQ_S1_BVD1_STSCHG (IRQ_BOARD_END + 54) ++ ++#define IRQ_LOCOMO_START (IRQ_BOARD_END) ++#define IRQ_LOCOMO_KEY (IRQ_BOARD_END + 0) ++#define IRQ_LOCOMO_GPIO0 (IRQ_BOARD_END + 1) ++#define IRQ_LOCOMO_GPIO1 (IRQ_BOARD_END + 2) ++#define IRQ_LOCOMO_GPIO2 (IRQ_BOARD_END + 3) ++#define IRQ_LOCOMO_GPIO3 (IRQ_BOARD_END + 4) ++#define IRQ_LOCOMO_GPIO4 (IRQ_BOARD_END + 5) ++#define IRQ_LOCOMO_GPIO5 (IRQ_BOARD_END + 6) ++#define IRQ_LOCOMO_GPIO6 (IRQ_BOARD_END + 7) ++#define IRQ_LOCOMO_GPIO7 (IRQ_BOARD_END + 8) ++#define IRQ_LOCOMO_GPIO8 (IRQ_BOARD_END + 9) ++#define IRQ_LOCOMO_GPIO9 (IRQ_BOARD_END + 10) ++#define IRQ_LOCOMO_GPIO10 (IRQ_BOARD_END + 11) ++#define IRQ_LOCOMO_GPIO11 (IRQ_BOARD_END + 12) ++#define IRQ_LOCOMO_GPIO12 (IRQ_BOARD_END + 13) ++#define IRQ_LOCOMO_GPIO13 (IRQ_BOARD_END + 14) ++#define IRQ_LOCOMO_GPIO14 (IRQ_BOARD_END + 15) ++#define IRQ_LOCOMO_GPIO15 (IRQ_BOARD_END + 16) ++#define IRQ_LOCOMO_LT (IRQ_BOARD_END + 17) ++#define IRQ_LOCOMO_SPI_RFR (IRQ_BOARD_END + 18) ++#define IRQ_LOCOMO_SPI_RFW (IRQ_BOARD_END + 19) ++#define IRQ_LOCOMO_SPI_OVRN (IRQ_BOARD_END + 20) ++#define IRQ_LOCOMO_SPI_TEND (IRQ_BOARD_END + 21) ++ ++/* ++ * Figure out the MAX IRQ number. ++ * ++ * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1. ++ * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1 ++ * Otherwise, we have the standard IRQs only. ++ */ ++#ifdef CONFIG_SA1111 ++#define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1) ++#elif defined(CONFIG_SHARP_LOCOMO) ++#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) ++#elif defined(CONFIG_ARCH_LUBBOCK) || \ ++ defined(CONFIG_MACH_LOGICPD_PXA270) || \ ++ defined(CONFIG_MACH_MAINSTONE) || \ ++ defined(CONFIG_MACH_PCM027) ++#define NR_IRQS (IRQ_BOARD_END) ++#else ++#define NR_IRQS (IRQ_BOARD_START) ++#endif ++ ++/* ++ * Board specific IRQs. Define them here. ++ * Do not surround them with ifdefs. ++ */ ++#define LUBBOCK_IRQ(x) (IRQ_BOARD_START + (x)) ++#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0) ++#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1) ++#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */ ++#define LUBBOCK_ETH_IRQ LUBBOCK_IRQ(3) ++#define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4) ++#define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5) ++#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */ ++#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) ++ ++#define LPD270_IRQ(x) (IRQ_BOARD_START + (x)) ++#define LPD270_USBC_IRQ LPD270_IRQ(2) ++#define LPD270_ETHERNET_IRQ LPD270_IRQ(3) ++#define LPD270_AC97_IRQ LPD270_IRQ(4) ++ ++#define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x)) ++#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0) ++#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1) ++#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2) ++#define MAINSTONE_ETHERNET_IRQ MAINSTONE_IRQ(3) ++#define MAINSTONE_AC97_IRQ MAINSTONE_IRQ(4) ++#define MAINSTONE_PEN_IRQ MAINSTONE_IRQ(5) ++#define MAINSTONE_MSINS_IRQ MAINSTONE_IRQ(6) ++#define MAINSTONE_EXBRD_IRQ MAINSTONE_IRQ(7) ++#define MAINSTONE_S0_CD_IRQ MAINSTONE_IRQ(9) ++#define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10) ++#define MAINSTONE_S0_IRQ MAINSTONE_IRQ(11) ++#define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13) ++#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14) ++#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15) ++ ++/* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */ ++#define IRQ_LOCOMO_KEY_BASE (IRQ_BOARD_START + 0) ++#define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1) ++#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) ++#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) ++ ++/* phyCORE-PXA270 (PCM027) Interrupts */ ++#define PCM027_IRQ(x) (IRQ_BOARD_START + (x)) ++#define PCM027_BTDET_IRQ PCM027_IRQ(0) ++#define PCM027_FF_RI_IRQ PCM027_IRQ(1) ++#define PCM027_MMCDET_IRQ PCM027_IRQ(2) ++#define PCM027_PM_5V_IRQ PCM027_IRQ(3) ++ ++/* ITE8152 irqs */ ++/* add IT8152 IRQs beyond BOARD_END */ ++#ifdef CONFIG_PCI_HOST_ITE8152 ++#define IT8152_IRQ(x) (IRQ_GPIO(IRQ_BOARD_END) + 1 + (x)) ++ ++/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */ ++#define IT8152_LD_IRQ_COUNT 9 ++#define IT8152_LP_IRQ_COUNT 16 ++#define IT8152_PD_IRQ_COUNT 15 ++ ++/* Priorities: */ ++#define IT8152_PD_IRQ(i) IT8152_IRQ(i) ++#define IT8152_LP_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT) ++#define IT8152_LD_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT + IT8152_LP_IRQ_COUNT) ++ ++#define IT8152_LAST_IRQ IT8152_LD_IRQ(IT8152_LD_IRQ_COUNT - 1) ++ ++#undef NR_IRQS ++#define NR_IRQS (IT8152_LAST_IRQ+1) ++#endif +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/littleton.h linux-2.6.25-rc4/include/asm-arm/arch/littleton.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/littleton.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/littleton.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,6 @@ ++#ifndef __ASM_ARCH_ZYLONITE_H ++#define __ASM_ARCH_ZYLONITE_H ++ ++#define LITTLETON_ETH_PHYS 0x30000000 ++ ++#endif /* __ASM_ARCH_ZYLONITE_H */ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/lpd270.h linux-2.6.25-rc4/include/asm-arm/arch/lpd270.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/lpd270.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/lpd270.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,38 @@ ++/* ++ * include/asm-arm/arch-pxa/lpd270.h ++ * ++ * Author: Lennert Buytenhek ++ * Created: Feb 10, 2006 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __ASM_ARCH_LPD270_H ++#define __ASM_ARCH_LPD270_H ++ ++#define LPD270_CPLD_PHYS PXA_CS2_PHYS ++#define LPD270_CPLD_VIRT 0xf0000000 ++#define LPD270_CPLD_SIZE 0x00100000 ++ ++#define LPD270_ETH_PHYS (PXA_CS2_PHYS + 0x01000000) ++ ++/* CPLD registers */ ++#define LPD270_CPLD_REG(x) ((unsigned long)(LPD270_CPLD_VIRT + (x))) ++#define LPD270_CONTROL LPD270_CPLD_REG(0x00) ++#define LPD270_PERIPHERAL0 LPD270_CPLD_REG(0x04) ++#define LPD270_PERIPHERAL1 LPD270_CPLD_REG(0x08) ++#define LPD270_CPLD_REVISION LPD270_CPLD_REG(0x14) ++#define LPD270_EEPROM_SPI_ITF LPD270_CPLD_REG(0x20) ++#define LPD270_MODE_PINS LPD270_CPLD_REG(0x24) ++#define LPD270_EGPIO LPD270_CPLD_REG(0x30) ++#define LPD270_INT_MASK LPD270_CPLD_REG(0x40) ++#define LPD270_INT_STATUS LPD270_CPLD_REG(0x50) ++ ++#define LPD270_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */ ++#define LPD270_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */ ++#define LPD270_INT_USBC (1 << 2) /* USB client cable detection IRQ */ ++ ++ ++#endif +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/lubbock.h linux-2.6.25-rc4/include/asm-arm/arch/lubbock.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/lubbock.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/lubbock.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,40 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/lubbock.h ++ * ++ * Author: Nicolas Pitre ++ * Created: Jun 15, 2001 ++ * Copyright: MontaVista Software Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#define LUBBOCK_ETH_PHYS PXA_CS3_PHYS ++ ++#define LUBBOCK_FPGA_PHYS PXA_CS2_PHYS ++#define LUBBOCK_FPGA_VIRT (0xf0000000) ++#define LUB_P2V(x) ((x) - LUBBOCK_FPGA_PHYS + LUBBOCK_FPGA_VIRT) ++#define LUB_V2P(x) ((x) - LUBBOCK_FPGA_VIRT + LUBBOCK_FPGA_PHYS) ++ ++#ifndef __ASSEMBLY__ ++# define __LUB_REG(x) (*((volatile unsigned long *)LUB_P2V(x))) ++#else ++# define __LUB_REG(x) LUB_P2V(x) ++#endif ++ ++/* FPGA register virtual addresses */ ++#define LUB_WHOAMI __LUB_REG(LUBBOCK_FPGA_PHYS + 0x000) ++#define LUB_HEXLED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x010) ++#define LUB_DISC_BLNK_LED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x040) ++#define LUB_CONF_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x050) ++#define LUB_USER_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x060) ++#define LUB_MISC_WR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080) ++#define LUB_MISC_RD __LUB_REG(LUBBOCK_FPGA_PHYS + 0x090) ++#define LUB_IRQ_MASK_EN __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0c0) ++#define LUB_IRQ_SET_CLR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0d0) ++#define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100) ++ ++#ifndef __ASSEMBLY__ ++extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set); ++#endif +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/magician.h linux-2.6.25-rc4/include/asm-arm/arch/magician.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/magician.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/magician.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,111 @@ ++/* ++ * GPIO and IRQ definitions for HTC Magician PDA phones ++ * ++ * Copyright (c) 2007 Philipp Zabel ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#ifndef _MAGICIAN_H_ ++#define _MAGICIAN_H_ ++ ++#include <asm/arch/pxa-regs.h> ++ ++/* ++ * PXA GPIOs ++ */ ++ ++#define GPIO0_MAGICIAN_KEY_POWER 0 ++#define GPIO9_MAGICIAN_UNKNOWN 9 ++#define GPIO10_MAGICIAN_GSM_IRQ 10 ++#define GPIO11_MAGICIAN_GSM_OUT1 11 ++#define GPIO13_MAGICIAN_CPLD_IRQ 13 ++#define GPIO18_MAGICIAN_UNKNOWN 18 ++#define GPIO22_MAGICIAN_VIBRA_EN 22 ++#define GPIO26_MAGICIAN_GSM_POWER 26 ++#define GPIO27_MAGICIAN_USBC_PUEN 27 ++#define GPIO30_MAGICIAN_nCHARGE_EN 30 ++#define GPIO37_MAGICIAN_KEY_HANGUP 37 ++#define GPIO38_MAGICIAN_KEY_CONTACTS 38 ++#define GPIO40_MAGICIAN_GSM_OUT2 40 ++#define GPIO48_MAGICIAN_UNKNOWN 48 ++#define GPIO56_MAGICIAN_UNKNOWN 56 ++#define GPIO57_MAGICIAN_CAM_RESET 57 ++#define GPIO83_MAGICIAN_nIR_EN 83 ++#define GPIO86_MAGICIAN_GSM_RESET 86 ++#define GPIO87_MAGICIAN_GSM_SELECT 87 ++#define GPIO90_MAGICIAN_KEY_CALENDAR 90 ++#define GPIO91_MAGICIAN_KEY_CAMERA 91 ++#define GPIO93_MAGICIAN_KEY_UP 93 ++#define GPIO94_MAGICIAN_KEY_DOWN 94 ++#define GPIO95_MAGICIAN_KEY_LEFT 95 ++#define GPIO96_MAGICIAN_KEY_RIGHT 96 ++#define GPIO97_MAGICIAN_KEY_ENTER 97 ++#define GPIO98_MAGICIAN_KEY_RECORD 98 ++#define GPIO99_MAGICIAN_HEADPHONE_IN 99 ++#define GPIO100_MAGICIAN_KEY_VOL_UP 100 ++#define GPIO101_MAGICIAN_KEY_VOL_DOWN 101 ++#define GPIO102_MAGICIAN_KEY_PHONE 102 ++#define GPIO103_MAGICIAN_LED_KP 103 ++#define GPIO104_MAGICIAN_LCD_POWER_1 104 ++#define GPIO105_MAGICIAN_LCD_POWER_2 105 ++#define GPIO106_MAGICIAN_LCD_POWER_3 106 ++#define GPIO107_MAGICIAN_DS1WM_IRQ 107 ++#define GPIO108_MAGICIAN_GSM_READY 108 ++#define GPIO114_MAGICIAN_UNKNOWN 114 ++#define GPIO115_MAGICIAN_nPEN_IRQ 115 ++#define GPIO116_MAGICIAN_nCAM_EN 116 ++#define GPIO119_MAGICIAN_UNKNOWN 119 ++#define GPIO120_MAGICIAN_UNKNOWN 120 ++ ++/* ++ * PXA GPIO alternate function mode & direction ++ */ ++ ++#define GPIO0_MAGICIAN_KEY_POWER_MD (0 | GPIO_IN) ++#define GPIO9_MAGICIAN_UNKNOWN_MD (9 | GPIO_IN) ++#define GPIO10_MAGICIAN_GSM_IRQ_MD (10 | GPIO_IN) ++#define GPIO11_MAGICIAN_GSM_OUT1_MD (11 | GPIO_OUT) ++#define GPIO13_MAGICIAN_CPLD_IRQ_MD (13 | GPIO_IN) ++#define GPIO18_MAGICIAN_UNKNOWN_MD (18 | GPIO_OUT) ++#define GPIO22_MAGICIAN_VIBRA_EN_MD (22 | GPIO_OUT) ++#define GPIO26_MAGICIAN_GSM_POWER_MD (26 | GPIO_OUT) ++#define GPIO27_MAGICIAN_USBC_PUEN_MD (27 | GPIO_OUT) ++#define GPIO30_MAGICIAN_nCHARGE_EN_MD (30 | GPIO_OUT) ++#define GPIO37_MAGICIAN_KEY_HANGUP_MD (37 | GPIO_OUT) ++#define GPIO38_MAGICIAN_KEY_CONTACTS_MD (38 | GPIO_OUT) ++#define GPIO40_MAGICIAN_GSM_OUT2_MD (40 | GPIO_OUT) ++#define GPIO48_MAGICIAN_UNKNOWN_MD (48 | GPIO_OUT) ++#define GPIO56_MAGICIAN_UNKNOWN_MD (56 | GPIO_OUT) ++#define GPIO57_MAGICIAN_CAM_RESET_MD (57 | GPIO_OUT) ++#define GPIO83_MAGICIAN_nIR_EN_MD (83 | GPIO_OUT) ++#define GPIO86_MAGICIAN_GSM_RESET_MD (86 | GPIO_OUT) ++#define GPIO87_MAGICIAN_GSM_SELECT_MD (87 | GPIO_OUT) ++#define GPIO90_MAGICIAN_KEY_CALENDAR_MD (90 | GPIO_OUT) ++#define GPIO91_MAGICIAN_KEY_CAMERA_MD (91 | GPIO_OUT) ++#define GPIO93_MAGICIAN_KEY_UP_MD (93 | GPIO_IN) ++#define GPIO94_MAGICIAN_KEY_DOWN_MD (94 | GPIO_IN) ++#define GPIO95_MAGICIAN_KEY_LEFT_MD (95 | GPIO_IN) ++#define GPIO96_MAGICIAN_KEY_RIGHT_MD (96 | GPIO_IN) ++#define GPIO97_MAGICIAN_KEY_ENTER_MD (97 | GPIO_IN) ++#define GPIO98_MAGICIAN_KEY_RECORD_MD (98 | GPIO_IN) ++#define GPIO99_MAGICIAN_HEADPHONE_IN_MD (99 | GPIO_IN) ++#define GPIO100_MAGICIAN_KEY_VOL_UP_MD (100 | GPIO_IN) ++#define GPIO101_MAGICIAN_KEY_VOL_DOWN_MD (101 | GPIO_IN) ++#define GPIO102_MAGICIAN_KEY_PHONE_MD (102 | GPIO_IN) ++#define GPIO103_MAGICIAN_LED_KP_MD (103 | GPIO_OUT) ++#define GPIO104_MAGICIAN_LCD_POWER_1_MD (104 | GPIO_OUT) ++#define GPIO105_MAGICIAN_LCD_POWER_2_MD (105 | GPIO_OUT) ++#define GPIO106_MAGICIAN_LCD_POWER_3_MD (106 | GPIO_OUT) ++#define GPIO107_MAGICIAN_DS1WM_IRQ_MD (107 | GPIO_IN) ++#define GPIO108_MAGICIAN_GSM_READY_MD (108 | GPIO_IN) ++#define GPIO114_MAGICIAN_UNKNOWN_MD (114 | GPIO_OUT) ++#define GPIO115_MAGICIAN_nPEN_IRQ_MD (115 | GPIO_IN) ++#define GPIO116_MAGICIAN_nCAM_EN_MD (116 | GPIO_OUT) ++#define GPIO119_MAGICIAN_UNKNOWN_MD (119 | GPIO_OUT) ++#define GPIO120_MAGICIAN_UNKNOWN_MD (120 | GPIO_OUT) ++ ++#endif /* _MAGICIAN_H_ */ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/mainstone.h linux-2.6.25-rc4/include/asm-arm/arch/mainstone.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/mainstone.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/mainstone.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,120 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/mainstone.h ++ * ++ * Author: Nicolas Pitre ++ * Created: Nov 14, 2002 ++ * Copyright: MontaVista Software Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef ASM_ARCH_MAINSTONE_H ++#define ASM_ARCH_MAINSTONE_H ++ ++#define MST_ETH_PHYS PXA_CS4_PHYS ++ ++#define MST_FPGA_PHYS PXA_CS2_PHYS ++#define MST_FPGA_VIRT (0xf0000000) ++#define MST_P2V(x) ((x) - MST_FPGA_PHYS + MST_FPGA_VIRT) ++#define MST_V2P(x) ((x) - MST_FPGA_VIRT + MST_FPGA_PHYS) ++ ++#ifndef __ASSEMBLY__ ++# define __MST_REG(x) (*((volatile unsigned long *)MST_P2V(x))) ++#else ++# define __MST_REG(x) MST_P2V(x) ++#endif ++ ++/* board level registers in the FPGA */ ++ ++#define MST_LEDDAT1 __MST_REG(0x08000010) ++#define MST_LEDDAT2 __MST_REG(0x08000014) ++#define MST_LEDCTRL __MST_REG(0x08000040) ++#define MST_GPSWR __MST_REG(0x08000060) ++#define MST_MSCWR1 __MST_REG(0x08000080) ++#define MST_MSCWR2 __MST_REG(0x08000084) ++#define MST_MSCWR3 __MST_REG(0x08000088) ++#define MST_MSCRD __MST_REG(0x08000090) ++#define MST_INTMSKENA __MST_REG(0x080000c0) ++#define MST_INTSETCLR __MST_REG(0x080000d0) ++#define MST_PCMCIA0 __MST_REG(0x080000e0) ++#define MST_PCMCIA1 __MST_REG(0x080000e4) ++ ++#define MST_MSCWR1_CAMERA_ON (1 << 15) /* Camera interface power control */ ++#define MST_MSCWR1_CAMERA_SEL (1 << 14) /* Camera interface mux control */ ++#define MST_MSCWR1_LCD_CTL (1 << 13) /* General-purpose LCD control */ ++#define MST_MSCWR1_MS_ON (1 << 12) /* Memory Stick power control */ ++#define MST_MSCWR1_MMC_ON (1 << 11) /* MultiMediaCard* power control */ ++#define MST_MSCWR1_MS_SEL (1 << 10) /* SD/MS multiplexer control */ ++#define MST_MSCWR1_BB_SEL (1 << 9) /* PCMCIA/Baseband multiplexer */ ++#define MST_MSCWR1_BT_ON (1 << 8) /* Bluetooth UART transceiver */ ++#define MST_MSCWR1_BTDTR (1 << 7) /* Bluetooth UART DTR */ ++ ++#define MST_MSCWR1_IRDA_MASK (3 << 5) /* IrDA transceiver mode */ ++#define MST_MSCWR1_IRDA_FULL (0 << 5) /* full distance power */ ++#define MST_MSCWR1_IRDA_OFF (1 << 5) /* shutdown */ ++#define MST_MSCWR1_IRDA_MED (2 << 5) /* 2/3 distance power */ ++#define MST_MSCWR1_IRDA_LOW (3 << 5) /* 1/3 distance power */ ++ ++#define MST_MSCWR1_IRDA_FIR (1 << 4) /* IrDA transceiver SIR/FIR */ ++#define MST_MSCWR1_GREENLED (1 << 3) /* LED D1 control */ ++#define MST_MSCWR1_PDC_CTL (1 << 2) /* reserved */ ++#define MST_MSCWR1_MTR_ON (1 << 1) /* Silent alert motor */ ++#define MST_MSCWR1_SYSRESET (1 << 0) /* System reset */ ++ ++#define MST_MSCWR2_USB_OTG_RST (1 << 6) /* USB On The Go reset */ ++#define MST_MSCWR2_USB_OTG_SEL (1 << 5) /* USB On The Go control */ ++#define MST_MSCWR2_nUSBC_SC (1 << 4) /* USB client soft connect control */ ++#define MST_MSCWR2_I2S_SPKROFF (1 << 3) /* I2S CODEC amplifier control */ ++#define MST_MSCWR2_AC97_SPKROFF (1 << 2) /* AC97 CODEC amplifier control */ ++#define MST_MSCWR2_RADIO_PWR (1 << 1) /* Radio module power control */ ++#define MST_MSCWR2_RADIO_WAKE (1 << 0) /* Radio module wake-up signal */ ++ ++#define MST_MSCWR3_GPIO_RESET_EN (1 << 2) /* Enable GPIO Reset */ ++#define MST_MSCWR3_GPIO_RESET (1 << 1) /* Initiate a GPIO Reset */ ++#define MST_MSCWR3_COMMS_SW_RESET (1 << 0) /* Communications Processor Reset Control */ ++ ++#define MST_MSCRD_nPENIRQ (1 << 9) /* ADI7873* nPENIRQ signal */ ++#define MST_MSCRD_nMEMSTK_CD (1 << 8) /* Memory Stick detection signal */ ++#define MST_MSCRD_nMMC_CD (1 << 7) /* SD/MMC card detection signal */ ++#define MST_MSCRD_nUSIM_CD (1 << 6) /* USIM card detection signal */ ++#define MST_MSCRD_USB_CBL (1 << 5) /* USB client cable status */ ++#define MST_MSCRD_TS_BUSY (1 << 4) /* ADI7873 busy */ ++#define MST_MSCRD_BTDSR (1 << 3) /* Bluetooth UART DSR */ ++#define MST_MSCRD_BTRI (1 << 2) /* Bluetooth UART Ring Indicator */ ++#define MST_MSCRD_BTDCD (1 << 1) /* Bluetooth UART DCD */ ++#define MST_MSCRD_nMMC_WP (1 << 0) /* SD/MMC write-protect status */ ++ ++#define MST_INT_S1_IRQ (1 << 15) /* PCMCIA socket 1 IRQ */ ++#define MST_INT_S1_STSCHG (1 << 14) /* PCMCIA socket 1 status changed */ ++#define MST_INT_S1_CD (1 << 13) /* PCMCIA socket 1 card detection */ ++#define MST_INT_S0_IRQ (1 << 11) /* PCMCIA socket 0 IRQ */ ++#define MST_INT_S0_STSCHG (1 << 10) /* PCMCIA socket 0 status changed */ ++#define MST_INT_S0_CD (1 << 9) /* PCMCIA socket 0 card detection */ ++#define MST_INT_nEXBRD_INT (1 << 7) /* Expansion board IRQ */ ++#define MST_INT_MSINS (1 << 6) /* Memory Stick* detection */ ++#define MST_INT_PENIRQ (1 << 5) /* ADI7873* touch-screen IRQ */ ++#define MST_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */ ++#define MST_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */ ++#define MST_INT_USBC (1 << 2) /* USB client cable detection IRQ */ ++#define MST_INT_USIM (1 << 1) /* USIM card detection IRQ */ ++#define MST_INT_MMC (1 << 0) /* MMC/SD card detection IRQ */ ++ ++#define MST_PCMCIA_nIRQ (1 << 10) /* IRQ / ready signal */ ++#define MST_PCMCIA_nSPKR_BVD2 (1 << 9) /* VDD sense / digital speaker */ ++#define MST_PCMCIA_nSTSCHG_BVD1 (1 << 8) /* VDD sense / card status changed */ ++#define MST_PCMCIA_nVS2 (1 << 7) /* VSS voltage sense */ ++#define MST_PCMCIA_nVS1 (1 << 6) /* VSS voltage sense */ ++#define MST_PCMCIA_nCD (1 << 5) /* Card detection signal */ ++#define MST_PCMCIA_RESET (1 << 4) /* Card reset signal */ ++#define MST_PCMCIA_PWR_MASK (0x000f) /* MAX1602 power-supply controls */ ++ ++#define MST_PCMCIA_PWR_VPP_0 0x0 /* voltage VPP = 0V */ ++#define MST_PCMCIA_PWR_VPP_120 0x2 /* voltage VPP = 12V*/ ++#define MST_PCMCIA_PWR_VPP_VCC 0x1 /* voltage VPP = VCC */ ++#define MST_PCMCIA_PWR_VCC_0 0x0 /* voltage VCC = 0V */ ++#define MST_PCMCIA_PWR_VCC_33 0x8 /* voltage VCC = 3.3V */ ++#define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */ ++ ++#endif +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/memory.h linux-2.6.25-rc4/include/asm-arm/arch/memory.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/memory.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/memory.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,52 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/memory.h ++ * ++ * Author: Nicolas Pitre ++ * Copyright: (C) 2001 MontaVista Software Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __ASM_ARCH_MEMORY_H ++#define __ASM_ARCH_MEMORY_H ++ ++/* ++ * Physical DRAM offset. ++ */ ++#define PHYS_OFFSET UL(0xa0000000) ++ ++/* ++ * Virtual view <-> DMA view memory address translations ++ * virt_to_bus: Used to translate the virtual address to an ++ * address suitable to be passed to set_dma_addr ++ * bus_to_virt: Used to convert an address for DMA operations ++ * to an address that the kernel can use. ++ */ ++#define __virt_to_bus(x) __virt_to_phys(x) ++#define __bus_to_virt(x) __phys_to_virt(x) ++ ++/* ++ * The nodes are matched with the physical SDRAM banks as follows: ++ * ++ * node 0: 0xa0000000-0xa3ffffff --> 0xc0000000-0xc3ffffff ++ * node 1: 0xa4000000-0xa7ffffff --> 0xc4000000-0xc7ffffff ++ * node 2: 0xa8000000-0xabffffff --> 0xc8000000-0xcbffffff ++ * node 3: 0xac000000-0xafffffff --> 0xcc000000-0xcfffffff ++ * ++ * This needs a node mem size of 26 bits. ++ */ ++#define NODE_MEM_SIZE_BITS 26 ++ ++#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) ++void cmx270_pci_adjust_zones(int node, unsigned long *size, ++ unsigned long *holes); ++ ++#define arch_adjust_zones(node, size, holes) \ ++ cmx270_pci_adjust_zones(node, size, holes) ++ ++#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1) ++#endif ++ ++#endif +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/mfp.h linux-2.6.25-rc4/include/asm-arm/arch/mfp.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/mfp.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/mfp.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,311 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/mfp.h ++ * ++ * Multi-Function Pin Definitions ++ * ++ * Copyright (C) 2007 Marvell International Ltd. ++ * ++ * 2007-8-21: eric miao <eric.miao@marvell.com> ++ * initial version ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __ASM_ARCH_MFP_H ++#define __ASM_ARCH_MFP_H ++ ++#define mfp_to_gpio(m) ((m) % 128) ++ ++/* list of all the configurable MFP pins */ ++enum { ++ MFP_PIN_INVALID = -1, ++ ++ MFP_PIN_GPIO0 = 0, ++ MFP_PIN_GPIO1, ++ MFP_PIN_GPIO2, ++ MFP_PIN_GPIO3, ++ MFP_PIN_GPIO4, ++ MFP_PIN_GPIO5, ++ MFP_PIN_GPIO6, ++ MFP_PIN_GPIO7, ++ MFP_PIN_GPIO8, ++ MFP_PIN_GPIO9, ++ MFP_PIN_GPIO10, ++ MFP_PIN_GPIO11, ++ MFP_PIN_GPIO12, ++ MFP_PIN_GPIO13, ++ MFP_PIN_GPIO14, ++ MFP_PIN_GPIO15, ++ MFP_PIN_GPIO16, ++ MFP_PIN_GPIO17, ++ MFP_PIN_GPIO18, ++ MFP_PIN_GPIO19, ++ MFP_PIN_GPIO20, ++ MFP_PIN_GPIO21, ++ MFP_PIN_GPIO22, ++ MFP_PIN_GPIO23, ++ MFP_PIN_GPIO24, ++ MFP_PIN_GPIO25, ++ MFP_PIN_GPIO26, ++ MFP_PIN_GPIO27, ++ MFP_PIN_GPIO28, ++ MFP_PIN_GPIO29, ++ MFP_PIN_GPIO30, ++ MFP_PIN_GPIO31, ++ MFP_PIN_GPIO32, ++ MFP_PIN_GPIO33, ++ MFP_PIN_GPIO34, ++ MFP_PIN_GPIO35, ++ MFP_PIN_GPIO36, ++ MFP_PIN_GPIO37, ++ MFP_PIN_GPIO38, ++ MFP_PIN_GPIO39, ++ MFP_PIN_GPIO40, ++ MFP_PIN_GPIO41, ++ MFP_PIN_GPIO42, ++ MFP_PIN_GPIO43, ++ MFP_PIN_GPIO44, ++ MFP_PIN_GPIO45, ++ MFP_PIN_GPIO46, ++ MFP_PIN_GPIO47, ++ MFP_PIN_GPIO48, ++ MFP_PIN_GPIO49, ++ MFP_PIN_GPIO50, ++ MFP_PIN_GPIO51, ++ MFP_PIN_GPIO52, ++ MFP_PIN_GPIO53, ++ MFP_PIN_GPIO54, ++ MFP_PIN_GPIO55, ++ MFP_PIN_GPIO56, ++ MFP_PIN_GPIO57, ++ MFP_PIN_GPIO58, ++ MFP_PIN_GPIO59, ++ MFP_PIN_GPIO60, ++ MFP_PIN_GPIO61, ++ MFP_PIN_GPIO62, ++ MFP_PIN_GPIO63, ++ MFP_PIN_GPIO64, ++ MFP_PIN_GPIO65, ++ MFP_PIN_GPIO66, ++ MFP_PIN_GPIO67, ++ MFP_PIN_GPIO68, ++ MFP_PIN_GPIO69, ++ MFP_PIN_GPIO70, ++ MFP_PIN_GPIO71, ++ MFP_PIN_GPIO72, ++ MFP_PIN_GPIO73, ++ MFP_PIN_GPIO74, ++ MFP_PIN_GPIO75, ++ MFP_PIN_GPIO76, ++ MFP_PIN_GPIO77, ++ MFP_PIN_GPIO78, ++ MFP_PIN_GPIO79, ++ MFP_PIN_GPIO80, ++ MFP_PIN_GPIO81, ++ MFP_PIN_GPIO82, ++ MFP_PIN_GPIO83, ++ MFP_PIN_GPIO84, ++ MFP_PIN_GPIO85, ++ MFP_PIN_GPIO86, ++ MFP_PIN_GPIO87, ++ MFP_PIN_GPIO88, ++ MFP_PIN_GPIO89, ++ MFP_PIN_GPIO90, ++ MFP_PIN_GPIO91, ++ MFP_PIN_GPIO92, ++ MFP_PIN_GPIO93, ++ MFP_PIN_GPIO94, ++ MFP_PIN_GPIO95, ++ MFP_PIN_GPIO96, ++ MFP_PIN_GPIO97, ++ MFP_PIN_GPIO98, ++ MFP_PIN_GPIO99, ++ MFP_PIN_GPIO100, ++ MFP_PIN_GPIO101, ++ MFP_PIN_GPIO102, ++ MFP_PIN_GPIO103, ++ MFP_PIN_GPIO104, ++ MFP_PIN_GPIO105, ++ MFP_PIN_GPIO106, ++ MFP_PIN_GPIO107, ++ MFP_PIN_GPIO108, ++ MFP_PIN_GPIO109, ++ MFP_PIN_GPIO110, ++ MFP_PIN_GPIO111, ++ MFP_PIN_GPIO112, ++ MFP_PIN_GPIO113, ++ MFP_PIN_GPIO114, ++ MFP_PIN_GPIO115, ++ MFP_PIN_GPIO116, ++ MFP_PIN_GPIO117, ++ MFP_PIN_GPIO118, ++ MFP_PIN_GPIO119, ++ MFP_PIN_GPIO120, ++ MFP_PIN_GPIO121, ++ MFP_PIN_GPIO122, ++ MFP_PIN_GPIO123, ++ MFP_PIN_GPIO124, ++ MFP_PIN_GPIO125, ++ MFP_PIN_GPIO126, ++ MFP_PIN_GPIO127, ++ MFP_PIN_GPIO0_2, ++ MFP_PIN_GPIO1_2, ++ MFP_PIN_GPIO2_2, ++ MFP_PIN_GPIO3_2, ++ MFP_PIN_GPIO4_2, ++ MFP_PIN_GPIO5_2, ++ MFP_PIN_GPIO6_2, ++ MFP_PIN_GPIO7_2, ++ MFP_PIN_GPIO8_2, ++ MFP_PIN_GPIO9_2, ++ MFP_PIN_GPIO10_2, ++ MFP_PIN_GPIO11_2, ++ MFP_PIN_GPIO12_2, ++ MFP_PIN_GPIO13_2, ++ MFP_PIN_GPIO14_2, ++ MFP_PIN_GPIO15_2, ++ MFP_PIN_GPIO16_2, ++ MFP_PIN_GPIO17_2, ++ ++ MFP_PIN_ULPI_STP, ++ MFP_PIN_ULPI_NXT, ++ MFP_PIN_ULPI_DIR, ++ ++ MFP_PIN_nXCVREN, ++ MFP_PIN_DF_CLE_nOE, ++ MFP_PIN_DF_nADV1_ALE, ++ MFP_PIN_DF_SCLK_E, ++ MFP_PIN_DF_SCLK_S, ++ MFP_PIN_nBE0, ++ MFP_PIN_nBE1, ++ MFP_PIN_DF_nADV2_ALE, ++ MFP_PIN_DF_INT_RnB, ++ MFP_PIN_DF_nCS0, ++ MFP_PIN_DF_nCS1, ++ MFP_PIN_nLUA, ++ MFP_PIN_nLLA, ++ MFP_PIN_DF_nWE, ++ MFP_PIN_DF_ALE_nWE, ++ MFP_PIN_DF_nRE_nOE, ++ MFP_PIN_DF_ADDR0, ++ MFP_PIN_DF_ADDR1, ++ MFP_PIN_DF_ADDR2, ++ MFP_PIN_DF_ADDR3, ++ MFP_PIN_DF_IO0, ++ MFP_PIN_DF_IO1, ++ MFP_PIN_DF_IO2, ++ MFP_PIN_DF_IO3, ++ MFP_PIN_DF_IO4, ++ MFP_PIN_DF_IO5, ++ MFP_PIN_DF_IO6, ++ MFP_PIN_DF_IO7, ++ MFP_PIN_DF_IO8, ++ MFP_PIN_DF_IO9, ++ MFP_PIN_DF_IO10, ++ MFP_PIN_DF_IO11, ++ MFP_PIN_DF_IO12, ++ MFP_PIN_DF_IO13, ++ MFP_PIN_DF_IO14, ++ MFP_PIN_DF_IO15, ++ ++ MFP_PIN_MAX, ++}; ++ ++/* ++ * a possible MFP configuration is represented by a 32-bit integer ++ * ++ * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum) ++ * bit 10..12 - Alternate Function Selection ++ * bit 13..15 - Drive Strength ++ * bit 16..18 - Low Power Mode State ++ * bit 19..20 - Low Power Mode Edge Detection ++ * bit 21..22 - Run Mode Pull State ++ * ++ * to facilitate the definition, the following macros are provided ++ * ++ * MFP_CFG_DEFAULT - default MFP configuration value, with ++ * alternate function = 0, ++ * drive strength = fast 3mA (MFP_DS03X) ++ * low power mode = default ++ * edge detection = none ++ * ++ * MFP_CFG - default MFPR value with alternate function ++ * MFP_CFG_DRV - default MFPR value with alternate function and ++ * pin drive strength ++ * MFP_CFG_LPM - default MFPR value with alternate function and ++ * low power mode ++ * MFP_CFG_X - default MFPR value with alternate function, ++ * pin drive strength and low power mode ++ */ ++ ++typedef unsigned long mfp_cfg_t; ++ ++#define MFP_PIN(x) ((x) & 0x3ff) ++ ++#define MFP_AF0 (0x0 << 10) ++#define MFP_AF1 (0x1 << 10) ++#define MFP_AF2 (0x2 << 10) ++#define MFP_AF3 (0x3 << 10) ++#define MFP_AF4 (0x4 << 10) ++#define MFP_AF5 (0x5 << 10) ++#define MFP_AF6 (0x6 << 10) ++#define MFP_AF7 (0x7 << 10) ++#define MFP_AF_MASK (0x7 << 10) ++#define MFP_AF(x) (((x) >> 10) & 0x7) ++ ++#define MFP_DS01X (0x0 << 13) ++#define MFP_DS02X (0x1 << 13) ++#define MFP_DS03X (0x2 << 13) ++#define MFP_DS04X (0x3 << 13) ++#define MFP_DS06X (0x4 << 13) ++#define MFP_DS08X (0x5 << 13) ++#define MFP_DS10X (0x6 << 13) ++#define MFP_DS13X (0x7 << 13) ++#define MFP_DS_MASK (0x7 << 13) ++#define MFP_DS(x) (((x) >> 13) & 0x7) ++ ++#define MFP_LPM_INPUT (0x0 << 16) ++#define MFP_LPM_DRIVE_LOW (0x1 << 16) ++#define MFP_LPM_DRIVE_HIGH (0x2 << 16) ++#define MFP_LPM_PULL_LOW (0x3 << 16) ++#define MFP_LPM_PULL_HIGH (0x4 << 16) ++#define MFP_LPM_FLOAT (0x5 << 16) ++#define MFP_LPM_STATE_MASK (0x7 << 16) ++#define MFP_LPM_STATE(x) (((x) >> 16) & 0x7) ++ ++#define MFP_LPM_EDGE_NONE (0x0 << 19) ++#define MFP_LPM_EDGE_RISE (0x1 << 19) ++#define MFP_LPM_EDGE_FALL (0x2 << 19) ++#define MFP_LPM_EDGE_BOTH (0x3 << 19) ++#define MFP_LPM_EDGE_MASK (0x3 << 19) ++#define MFP_LPM_EDGE(x) (((x) >> 19) & 0x3) ++ ++#define MFP_PULL_NONE (0x0 << 21) ++#define MFP_PULL_LOW (0x1 << 21) ++#define MFP_PULL_HIGH (0x2 << 21) ++#define MFP_PULL_BOTH (0x3 << 21) ++#define MFP_PULL_MASK (0x3 << 21) ++#define MFP_PULL(x) (((x) >> 21) & 0x3) ++ ++#define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_INPUT |\ ++ MFP_LPM_EDGE_NONE | MFP_PULL_NONE) ++ ++#define MFP_CFG(pin, af) \ ++ ((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\ ++ (MFP_PIN(MFP_PIN_##pin) | MFP_##af)) ++ ++#define MFP_CFG_DRV(pin, af, drv) \ ++ ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\ ++ (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv)) ++ ++#define MFP_CFG_LPM(pin, af, lpm) \ ++ ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\ ++ (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm)) ++ ++#define MFP_CFG_X(pin, af, drv, lpm) \ ++ ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\ ++ (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm)) ++ ++#endif /* __ASM_ARCH_MFP_H */ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/mfp-pxa300.h linux-2.6.25-rc4/include/asm-arm/arch/mfp-pxa300.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/mfp-pxa300.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/mfp-pxa300.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,575 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/mfp-pxa300.h ++ * ++ * PXA300/PXA310 specific MFP configuration definitions ++ * ++ * Copyright (C) 2007 Marvell International Ltd. ++ * 2007-08-21: eric miao <eric.miao@marvell.com> ++ * initial version ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __ASM_ARCH_MFP_PXA300_H ++#define __ASM_ARCH_MFP_PXA300_H ++ ++#include <asm/arch/mfp.h> ++#include <asm/arch/mfp-pxa3xx.h> ++ ++/* GPIO */ ++#define GPIO46_GPIO MFP_CFG(GPIO46, AF1) ++#define GPIO49_GPIO MFP_CFG(GPIO49, AF3) ++#define GPIO50_GPIO MFP_CFG(GPIO50, AF2) ++#define GPIO51_GPIO MFP_CFG(GPIO51, AF3) ++#define GPIO52_GPIO MFP_CFG(GPIO52, AF3) ++#define GPIO56_GPIO MFP_CFG(GPIO56, AF0) ++#define GPIO58_GPIO MFP_CFG(GPIO58, AF0) ++#define GPIO59_GPIO MFP_CFG(GPIO59, AF0) ++#define GPIO60_GPIO MFP_CFG(GPIO60, AF0) ++#define GPIO61_GPIO MFP_CFG(GPIO61, AF0) ++#define GPIO62_GPIO MFP_CFG(GPIO62, AF0) ++ ++#ifdef CONFIG_CPU_PXA310 ++#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0) ++#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0) ++#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0) ++#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0) ++#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0) ++#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0) ++#endif ++ ++/* Chip Select */ ++#define GPIO2_nCS3 MFP_CFG(GPIO2, AF1) ++ ++/* AC97 */ ++#define GPIO23_AC97_nACRESET MFP_CFG(GPIO23, AF1) ++#define GPIO24_AC97_SYSCLK MFP_CFG(GPIO24, AF1) ++#define GPIO29_AC97_BITCLK MFP_CFG(GPIO29, AF1) ++#define GPIO25_AC97_SDATA_IN_0 MFP_CFG(GPIO25, AF1) ++#define GPIO26_AC97_SDATA_IN_1 MFP_CFG(GPIO26, AF1) ++#define GPIO17_AC97_SDATA_IN_2 MFP_CFG(GPIO17, AF3) ++#define GPIO21_AC97_SDATA_IN_2 MFP_CFG(GPIO21, AF2) ++#define GPIO18_AC97_SDATA_IN_3 MFP_CFG(GPIO18, AF3) ++#define GPIO22_AC97_SDATA_IN_3 MFP_CFG(GPIO22, AF2) ++#define GPIO27_AC97_SDATA_OUT MFP_CFG(GPIO27, AF1) ++#define GPIO28_AC97_SYNC MFP_CFG(GPIO28, AF1) ++ ++/* I2C */ ++#define GPIO21_I2C_SCL MFP_CFG_LPM(GPIO21, AF1, PULL_HIGH) ++#define GPIO22_I2C_SDA MFP_CFG_LPM(GPIO22, AF1, PULL_HIGH) ++ ++/* QCI */ ++#define GPIO39_CI_DD_0 MFP_CFG_DRV(GPIO39, AF1, DS04X) ++#define GPIO40_CI_DD_1 MFP_CFG_DRV(GPIO40, AF1, DS04X) ++#define GPIO41_CI_DD_2 MFP_CFG_DRV(GPIO41, AF1, DS04X) ++#define GPIO42_CI_DD_3 MFP_CFG_DRV(GPIO42, AF1, DS04X) ++#define GPIO43_CI_DD_4 MFP_CFG_DRV(GPIO43, AF1, DS04X) ++#define GPIO44_CI_DD_5 MFP_CFG_DRV(GPIO44, AF1, DS04X) ++#define GPIO45_CI_DD_6 MFP_CFG_DRV(GPIO45, AF1, DS04X) ++#define GPIO46_CI_DD_7 MFP_CFG_DRV(GPIO46, AF0, DS04X) ++#define GPIO47_CI_DD_8 MFP_CFG_DRV(GPIO47, AF1, DS04X) ++#define GPIO48_CI_DD_9 MFP_CFG_DRV(GPIO48, AF1, DS04X) ++#define GPIO52_CI_HSYNC MFP_CFG_DRV(GPIO52, AF0, DS04X) ++#define GPIO51_CI_VSYNC MFP_CFG_DRV(GPIO51, AF0, DS04X) ++#define GPIO49_CI_MCLK MFP_CFG_DRV(GPIO49, AF0, DS04X) ++#define GPIO50_CI_PCLK MFP_CFG_DRV(GPIO50, AF0, DS04X) ++ ++/* KEYPAD */ ++#define GPIO3_KP_DKIN_6 MFP_CFG_LPM(GPIO3, AF2, FLOAT) ++#define GPIO4_KP_DKIN_7 MFP_CFG_LPM(GPIO4, AF2, FLOAT) ++#define GPIO16_KP_DKIN_6 MFP_CFG_LPM(GPIO16, AF6, FLOAT) ++#define GPIO83_KP_DKIN_2 MFP_CFG_LPM(GPIO83, AF5, FLOAT) ++#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF5, FLOAT) ++#define GPIO85_KP_DKIN_0 MFP_CFG_LPM(GPIO85, AF3, FLOAT) ++#define GPIO86_KP_DKIN_1 MFP_CFG_LPM(GPIO86, AF3, FLOAT) ++#define GPIO87_KP_DKIN_2 MFP_CFG_LPM(GPIO87, AF3, FLOAT) ++#define GPIO88_KP_DKIN_3 MFP_CFG_LPM(GPIO88, AF3, FLOAT) ++#define GPIO89_KP_DKIN_3 MFP_CFG_LPM(GPIO89, AF3, FLOAT) ++#define GPIO107_KP_DKIN_0 MFP_CFG_LPM(GPIO107, AF2, FLOAT) ++#define GPIO108_KP_DKIN_1 MFP_CFG_LPM(GPIO108, AF2, FLOAT) ++#define GPIO109_KP_DKIN_2 MFP_CFG_LPM(GPIO109, AF2, FLOAT) ++#define GPIO110_KP_DKIN_3 MFP_CFG_LPM(GPIO110, AF2, FLOAT) ++#define GPIO111_KP_DKIN_4 MFP_CFG_LPM(GPIO111, AF2, FLOAT) ++#define GPIO112_KP_DKIN_5 MFP_CFG_LPM(GPIO112, AF2, FLOAT) ++#define GPIO113_KP_DKIN_6 MFP_CFG_LPM(GPIO113, AF2, FLOAT) ++#define GPIO114_KP_DKIN_7 MFP_CFG_LPM(GPIO114, AF2, FLOAT) ++#define GPIO115_KP_DKIN_0 MFP_CFG_LPM(GPIO115, AF2, FLOAT) ++#define GPIO116_KP_DKIN_1 MFP_CFG_LPM(GPIO116, AF2, FLOAT) ++#define GPIO117_KP_DKIN_2 MFP_CFG_LPM(GPIO117, AF2, FLOAT) ++#define GPIO118_KP_DKIN_3 MFP_CFG_LPM(GPIO118, AF2, FLOAT) ++#define GPIO119_KP_DKIN_4 MFP_CFG_LPM(GPIO119, AF2, FLOAT) ++#define GPIO120_KP_DKIN_5 MFP_CFG_LPM(GPIO120, AF2, FLOAT) ++#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT) ++#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT) ++#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT) ++#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT) ++#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF5, FLOAT) ++#define GPIO0_2_KP_DKIN_0 MFP_CFG_LPM(GPIO0_2, AF2, FLOAT) ++#define GPIO1_2_KP_DKIN_1 MFP_CFG_LPM(GPIO1_2, AF2, FLOAT) ++#define GPIO2_2_KP_DKIN_6 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT) ++#define GPIO3_2_KP_DKIN_7 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT) ++#define GPIO4_2_KP_DKIN_1 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT) ++#define GPIO5_2_KP_DKIN_0 MFP_CFG_LPM(GPIO5_2, AF2, FLOAT) ++ ++#define GPIO5_KP_MKIN_0 MFP_CFG_LPM(GPIO5, AF2, FLOAT) ++#define GPIO6_KP_MKIN_1 MFP_CFG_LPM(GPIO6, AF2, FLOAT) ++#define GPIO9_KP_MKIN_6 MFP_CFG_LPM(GPIO9, AF3, FLOAT) ++#define GPIO10_KP_MKIN_7 MFP_CFG_LPM(GPIO10, AF3, FLOAT) ++#define GPIO70_KP_MKIN_6 MFP_CFG_LPM(GPIO70, AF3, FLOAT) ++#define GPIO71_KP_MKIN_7 MFP_CFG_LPM(GPIO71, AF3, FLOAT) ++#define GPIO100_KP_MKIN_6 MFP_CFG_LPM(GPIO100, AF7, FLOAT) ++#define GPIO101_KP_MKIN_7 MFP_CFG_LPM(GPIO101, AF7, FLOAT) ++#define GPIO112_KP_MKIN_6 MFP_CFG_LPM(GPIO112, AF4, FLOAT) ++#define GPIO113_KP_MKIN_7 MFP_CFG_LPM(GPIO113, AF4, FLOAT) ++#define GPIO115_KP_MKIN_0 MFP_CFG_LPM(GPIO115, AF1, FLOAT) ++#define GPIO116_KP_MKIN_1 MFP_CFG_LPM(GPIO116, AF1, FLOAT) ++#define GPIO117_KP_MKIN_2 MFP_CFG_LPM(GPIO117, AF1, FLOAT) ++#define GPIO118_KP_MKIN_3 MFP_CFG_LPM(GPIO118, AF1, FLOAT) ++#define GPIO119_KP_MKIN_4 MFP_CFG_LPM(GPIO119, AF1, FLOAT) ++#define GPIO120_KP_MKIN_5 MFP_CFG_LPM(GPIO120, AF1, FLOAT) ++#define GPIO125_KP_MKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT) ++#define GPIO2_2_KP_MKIN_6 MFP_CFG_LPM(GPIO2_2, AF1, FLOAT) ++#define GPIO3_2_KP_MKIN_7 MFP_CFG_LPM(GPIO3_2, AF1, FLOAT) ++ ++#define GPIO7_KP_MKOUT_5 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH) ++#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF3, DRIVE_HIGH) ++#define GPIO12_KP_MKOUT_6 MFP_CFG_LPM(GPIO12, AF3, DRIVE_HIGH) ++#define GPIO13_KP_MKOUT_7 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH) ++#define GPIO19_KP_MKOUT_4 MFP_CFG_LPM(GPIO19, AF3, DRIVE_HIGH) ++#define GPIO20_KP_MKOUT_5 MFP_CFG_LPM(GPIO20, AF3, DRIVE_HIGH) ++#define GPIO38_KP_MKOUT_5 MFP_CFG_LPM(GPIO38, AF5, DRIVE_HIGH) ++#define GPIO53_KP_MKOUT_6 MFP_CFG_LPM(GPIO53, AF5, DRIVE_HIGH) ++#define GPIO78_KP_MKOUT_7 MFP_CFG_LPM(GPIO78, AF5, DRIVE_HIGH) ++#define GPIO85_KP_MKOUT_0 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH) ++#define GPIO86_KP_MKOUT_1 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH) ++#define GPIO87_KP_MKOUT_2 MFP_CFG_LPM(GPIO87, AF2, DRIVE_HIGH) ++#define GPIO88_KP_MKOUT_3 MFP_CFG_LPM(GPIO88, AF2, DRIVE_HIGH) ++#define GPIO104_KP_MKOUT_6 MFP_CFG_LPM(GPIO104, AF5, DRIVE_HIGH) ++#define GPIO105_KP_MKOUT_7 MFP_CFG_LPM(GPIO105, AF5, DRIVE_HIGH) ++#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH) ++#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH) ++#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH) ++#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH) ++#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH) ++#define GPIO126_KP_MKOUT_7 MFP_CFG_LPM(GPIO126, AF4, DRIVE_HIGH) ++#define GPIO5_2_KP_MKOUT_6 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH) ++#define GPIO4_2_KP_MKOUT_5 MFP_CFG_LPM(GPIO4_2, AF1, DRIVE_HIGH) ++#define GPIO6_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO6_2, AF1, DRIVE_HIGH) ++ ++/* LCD */ ++#define GPIO54_LCD_LDD_0 MFP_CFG_DRV(GPIO54, AF1, DS01X) ++#define GPIO55_LCD_LDD_1 MFP_CFG_DRV(GPIO55, AF1, DS01X) ++#define GPIO56_LCD_LDD_2 MFP_CFG_DRV(GPIO56, AF1, DS01X) ++#define GPIO57_LCD_LDD_3 MFP_CFG_DRV(GPIO57, AF1, DS01X) ++#define GPIO58_LCD_LDD_4 MFP_CFG_DRV(GPIO58, AF1, DS01X) ++#define GPIO59_LCD_LDD_5 MFP_CFG_DRV(GPIO59, AF1, DS01X) ++#define GPIO60_LCD_LDD_6 MFP_CFG_DRV(GPIO60, AF1, DS01X) ++#define GPIO61_LCD_LDD_7 MFP_CFG_DRV(GPIO61, AF1, DS01X) ++#define GPIO62_LCD_LDD_8 MFP_CFG_DRV(GPIO62, AF1, DS01X) ++#define GPIO63_LCD_LDD_9 MFP_CFG_DRV(GPIO63, AF1, DS01X) ++#define GPIO64_LCD_LDD_10 MFP_CFG_DRV(GPIO64, AF1, DS01X) ++#define GPIO65_LCD_LDD_11 MFP_CFG_DRV(GPIO65, AF1, DS01X) ++#define GPIO66_LCD_LDD_12 MFP_CFG_DRV(GPIO66, AF1, DS01X) ++#define GPIO67_LCD_LDD_13 MFP_CFG_DRV(GPIO67, AF1, DS01X) ++#define GPIO68_LCD_LDD_14 MFP_CFG_DRV(GPIO68, AF1, DS01X) ++#define GPIO69_LCD_LDD_15 MFP_CFG_DRV(GPIO69, AF1, DS01X) ++#define GPIO70_LCD_LDD_16 MFP_CFG_DRV(GPIO70, AF1, DS01X) ++#define GPIO71_LCD_LDD_17 MFP_CFG_DRV(GPIO71, AF1, DS01X) ++#define GPIO62_LCD_CS_N MFP_CFG_DRV(GPIO62, AF2, DS01X) ++#define GPIO72_LCD_FCLK MFP_CFG_DRV(GPIO72, AF1, DS01X) ++#define GPIO73_LCD_LCLK MFP_CFG_DRV(GPIO73, AF1, DS01X) ++#define GPIO74_LCD_PCLK MFP_CFG_DRV(GPIO74, AF1, DS02X) ++#define GPIO75_LCD_BIAS MFP_CFG_DRV(GPIO75, AF1, DS01X) ++#define GPIO76_LCD_VSYNC MFP_CFG_DRV(GPIO76, AF2, DS01X) ++ ++#define GPIO15_LCD_CS_N MFP_CFG_DRV(GPIO15, AF2, DS01X) ++#define GPIO127_LCD_CS_N MFP_CFG_DRV(GPIO127, AF1, DS01X) ++#define GPIO63_LCD_VSYNC MFP_CFG_DRV(GPIO63, AF2, DS01X) ++ ++/* Mini-LCD */ ++#define GPIO72_MLCD_FCLK MFP_CFG_DRV(GPIO72, AF7, DS08X) ++#define GPIO73_MLCD_LCLK MFP_CFG_DRV(GPIO73, AF7, DS08X) ++#define GPIO54_MLCD_LDD_0 MFP_CFG_DRV(GPIO54, AF7, DS08X) ++#define GPIO55_MLCD_LDD_1 MFP_CFG_DRV(GPIO55, AF7, DS08X) ++#define GPIO56_MLCD_LDD_2 MFP_CFG_DRV(GPIO56, AF7, DS08X) ++#define GPIO57_MLCD_LDD_3 MFP_CFG_DRV(GPIO57, AF7, DS08X) ++#define GPIO58_MLCD_LDD_4 MFP_CFG_DRV(GPIO58, AF7, DS08X) ++#define GPIO59_MLCD_LDD_5 MFP_CFG_DRV(GPIO59, AF7, DS08X) ++#define GPIO60_MLCD_LDD_6 MFP_CFG_DRV(GPIO60, AF7, DS08X) ++#define GPIO61_MLCD_LDD_7 MFP_CFG_DRV(GPIO61, AF7, DS08X) ++#define GPIO62_MLCD_LDD_8 MFP_CFG_DRV(GPIO62, AF7, DS08X) ++#define GPIO63_MLCD_LDD_9 MFP_CFG_DRV(GPIO63, AF7, DS08X) ++#define GPIO64_MLCD_LDD_10 MFP_CFG_DRV(GPIO64, AF7, DS08X) ++#define GPIO65_MLCD_LDD_11 MFP_CFG_DRV(GPIO65, AF7, DS08X) ++#define GPIO66_MLCD_LDD_12 MFP_CFG_DRV(GPIO66, AF7, DS08X) ++#define GPIO67_MLCD_LDD_13 MFP_CFG_DRV(GPIO67, AF7, DS08X) ++#define GPIO68_MLCD_LDD_14 MFP_CFG_DRV(GPIO68, AF7, DS08X) ++#define GPIO69_MLCD_LDD_15 MFP_CFG_DRV(GPIO69, AF7, DS08X) ++#define GPIO74_MLCD_PCLK MFP_CFG_DRV(GPIO74, AF7, DS08X) ++#define GPIO75_MLCD_BIAS MFP_CFG_DRV(GPIO75, AF2, DS08X) ++ ++/* MMC1 */ ++#define GPIO7_MMC1_CLK MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH) ++#define GPIO8_MMC1_CMD MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH) ++#define GPIO14_MMC1_CMD MFP_CFG_LPM(GPIO14, AF5, DRIVE_HIGH) ++#define GPIO15_MMC1_CMD MFP_CFG_LPM(GPIO15, AF5, DRIVE_HIGH) ++#define GPIO3_MMC1_DAT0 MFP_CFG_LPM(GPIO3, AF4, DRIVE_HIGH) ++#define GPIO4_MMC1_DAT1 MFP_CFG_LPM(GPIO4, AF4, DRIVE_HIGH) ++#define GPIO5_MMC1_DAT2 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH) ++#define GPIO6_MMC1_DAT3 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH) ++ ++/* MMC2 */ ++#define GPIO9_MMC2_DAT0 MFP_CFG_LPM(GPIO9, AF4, PULL_HIGH) ++#define GPIO10_MMC2_DAT1 MFP_CFG_LPM(GPIO10, AF4, PULL_HIGH) ++#define GPIO11_MMC2_DAT2 MFP_CFG_LPM(GPIO11, AF4, PULL_HIGH) ++#define GPIO12_MMC2_DAT3 MFP_CFG_LPM(GPIO12, AF4, PULL_HIGH) ++#define GPIO13_MMC2_CLK MFP_CFG_LPM(GPIO13, AF4, PULL_HIGH) ++#define GPIO14_MMC2_CMD MFP_CFG_LPM(GPIO14, AF4, PULL_HIGH) ++#define GPIO77_MMC2_DAT0 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH) ++#define GPIO78_MMC2_DAT1 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH) ++#define GPIO79_MMC2_DAT2 MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH) ++#define GPIO80_MMC2_DAT3 MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH) ++#define GPIO81_MMC2_CLK MFP_CFG_LPM(GPIO81, AF4, PULL_HIGH) ++#define GPIO82_MMC2_CMD MFP_CFG_LPM(GPIO82, AF4, PULL_HIGH) ++ ++/* SSP1 */ ++#define GPIO89_SSP1_EXTCLK MFP_CFG(GPIO89, AF1) ++#define GPIO90_SSP1_SYSCLK MFP_CFG(GPIO90, AF1) ++#define GPIO15_SSP1_SCLK MFP_CFG(GPIO15, AF6) ++#define GPIO16_SSP1_FRM MFP_CFG(GPIO16, AF2) ++#define GPIO33_SSP1_SCLK MFP_CFG(GPIO33, AF5) ++#define GPIO34_SSP1_FRM MFP_CFG(GPIO34, AF5) ++#define GPIO85_SSP1_SCLK MFP_CFG(GPIO85, AF1) ++#define GPIO86_SSP1_FRM MFP_CFG(GPIO86, AF1) ++#define GPIO18_SSP1_TXD MFP_CFG(GPIO18, AF7) ++#define GPIO18_SSP1_RXD MFP_CFG(GPIO18, AF2) ++#define GPIO20_SSP1_TXD MFP_CFG(GPIO20, AF2) ++#define GPIO20_SSP1_RXD MFP_CFG(GPIO20, AF7) ++#define GPIO35_SSP1_TXD MFP_CFG(GPIO35, AF5) ++#define GPIO35_SSP1_RXD MFP_CFG(GPIO35, AF4) ++#define GPIO36_SSP1_TXD MFP_CFG(GPIO36, AF5) ++#define GPIO36_SSP1_RXD MFP_CFG(GPIO36, AF6) ++#define GPIO87_SSP1_TXD MFP_CFG(GPIO87, AF1) ++#define GPIO87_SSP1_RXD MFP_CFG(GPIO87, AF6) ++#define GPIO88_SSP1_TXD MFP_CFG(GPIO88, AF6) ++#define GPIO88_SSP1_RXD MFP_CFG(GPIO88, AF1) ++ ++/* SSP2 */ ++#define GPIO29_SSP2_EXTCLK MFP_CFG(GPIO29, AF2) ++#define GPIO23_SSP2_SCLK MFP_CFG(GPIO23, AF2) ++#define GPIO17_SSP2_FRM MFP_CFG(GPIO17, AF2) ++#define GPIO25_SSP2_SCLK MFP_CFG(GPIO25, AF2) ++#define GPIO26_SSP2_FRM MFP_CFG(GPIO26, AF2) ++#define GPIO33_SSP2_SCLK MFP_CFG(GPIO33, AF6) ++#define GPIO34_SSP2_FRM MFP_CFG(GPIO34, AF6) ++#define GPIO64_SSP2_SCLK MFP_CFG(GPIO64, AF2) ++#define GPIO65_SSP2_FRM MFP_CFG(GPIO65, AF2) ++#define GPIO19_SSP2_TXD MFP_CFG(GPIO19, AF2) ++#define GPIO19_SSP2_RXD MFP_CFG(GPIO19, AF7) ++#define GPIO24_SSP2_TXD MFP_CFG(GPIO24, AF5) ++#define GPIO24_SSP2_RXD MFP_CFG(GPIO24, AF4) ++#define GPIO27_SSP2_TXD MFP_CFG(GPIO27, AF2) ++#define GPIO27_SSP2_RXD MFP_CFG(GPIO27, AF5) ++#define GPIO28_SSP2_TXD MFP_CFG(GPIO28, AF5) ++#define GPIO28_SSP2_RXD MFP_CFG(GPIO28, AF2) ++#define GPIO35_SSP2_TXD MFP_CFG(GPIO35, AF7) ++#define GPIO35_SSP2_RXD MFP_CFG(GPIO35, AF6) ++#define GPIO66_SSP2_TXD MFP_CFG(GPIO66, AF4) ++#define GPIO66_SSP2_RXD MFP_CFG(GPIO66, AF2) ++#define GPIO67_SSP2_TXD MFP_CFG(GPIO67, AF2) ++#define GPIO67_SSP2_RXD MFP_CFG(GPIO67, AF4) ++#define GPIO36_SSP2_TXD MFP_CFG(GPIO36, AF7) ++ ++/* SSP3 */ ++#define GPIO69_SSP3_FRM MFP_CFG_X(GPIO69, AF2, DS08X, DRIVE_LOW) ++#define GPIO68_SSP3_SCLK MFP_CFG_X(GPIO68, AF2, DS08X, FLOAT) ++#define GPIO92_SSP3_FRM MFP_CFG_X(GPIO92, AF1, DS08X, DRIVE_LOW) ++#define GPIO91_SSP3_SCLK MFP_CFG_X(GPIO91, AF1, DS08X, FLOAT) ++#define GPIO70_SSP3_TXD MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW) ++#define GPIO70_SSP3_RXD MFP_CFG_X(GPIO70, AF5, DS08X, FLOAT) ++#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF5, DS08X, DRIVE_LOW) ++#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF2, DS08X, FLOAT) ++#define GPIO93_SSP3_TXD MFP_CFG_X(GPIO93, AF1, DS08X, DRIVE_LOW) ++#define GPIO93_SSP3_RXD MFP_CFG_X(GPIO93, AF5, DS08X, FLOAT) ++#define GPIO94_SSP3_TXD MFP_CFG_X(GPIO94, AF5, DS08X, DRIVE_LOW) ++#define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT) ++ ++/* SSP4 */ ++#define GPIO95_SSP4_SCLK MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) ++#define GPIO96_SSP4_FRM MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) ++#define GPIO97_SSP4_TXD MFP_CFG_LPM(GPIO97, AF1, PULL_HIGH) ++#define GPIO97_SSP4_RXD MFP_CFG_LPM(GPIO97, AF5, PULL_HIGH) ++#define GPIO98_SSP4_TXD MFP_CFG_LPM(GPIO98, AF5, PULL_HIGH) ++#define GPIO98_SSP4_RXD MFP_CFG_LPM(GPIO98, AF1, PULL_HIGH) ++ ++/* UART1 */ ++#define GPIO32_UART1_CTS MFP_CFG_LPM(GPIO32, AF2, FLOAT) ++#define GPIO37_UART1_CTS MFP_CFG_LPM(GPIO37, AF4, FLOAT) ++#define GPIO79_UART1_CTS MFP_CFG_LPM(GPIO79, AF1, FLOAT) ++#define GPIO84_UART1_CTS MFP_CFG_LPM(GPIO84, AF3, FLOAT) ++#define GPIO101_UART1_CTS MFP_CFG_LPM(GPIO101, AF1, FLOAT) ++#define GPIO106_UART1_CTS MFP_CFG_LPM(GPIO106, AF6, FLOAT) ++ ++#define GPIO32_UART1_RTS MFP_CFG_LPM(GPIO32, AF4, FLOAT) ++#define GPIO37_UART1_RTS MFP_CFG_LPM(GPIO37, AF2, FLOAT) ++#define GPIO79_UART1_RTS MFP_CFG_LPM(GPIO79, AF3, FLOAT) ++#define GPIO84_UART1_RTS MFP_CFG_LPM(GPIO84, AF1, FLOAT) ++#define GPIO101_UART1_RTS MFP_CFG_LPM(GPIO101, AF6, FLOAT) ++#define GPIO106_UART1_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT) ++ ++#define GPIO34_UART1_DSR MFP_CFG_LPM(GPIO34, AF2, FLOAT) ++#define GPIO36_UART1_DSR MFP_CFG_LPM(GPIO36, AF4, FLOAT) ++#define GPIO81_UART1_DSR MFP_CFG_LPM(GPIO81, AF1, FLOAT) ++#define GPIO83_UART1_DSR MFP_CFG_LPM(GPIO83, AF3, FLOAT) ++#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF1, FLOAT) ++#define GPIO105_UART1_DSR MFP_CFG_LPM(GPIO105, AF6, FLOAT) ++ ++#define GPIO34_UART1_DTR MFP_CFG_LPM(GPIO34, AF4, FLOAT) ++#define GPIO36_UART1_DTR MFP_CFG_LPM(GPIO36, AF2, FLOAT) ++#define GPIO81_UART1_DTR MFP_CFG_LPM(GPIO81, AF3, FLOAT) ++#define GPIO83_UART1_DTR MFP_CFG_LPM(GPIO83, AF1, FLOAT) ++#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF6, FLOAT) ++#define GPIO105_UART1_DTR MFP_CFG_LPM(GPIO105, AF1, FLOAT) ++ ++#define GPIO35_UART1_RI MFP_CFG_LPM(GPIO35, AF2, FLOAT) ++#define GPIO82_UART1_RI MFP_CFG_LPM(GPIO82, AF1, FLOAT) ++#define GPIO104_UART1_RI MFP_CFG_LPM(GPIO104, AF1, FLOAT) ++ ++#define GPIO33_UART1_DCD MFP_CFG_LPM(GPIO33, AF2, FLOAT) ++#define GPIO80_UART1_DCD MFP_CFG_LPM(GPIO80, AF1, FLOAT) ++#define GPIO102_UART1_DCD MFP_CFG_LPM(GPIO102, AF1, FLOAT) ++ ++#define GPIO30_UART1_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT) ++#define GPIO31_UART1_RXD MFP_CFG_LPM(GPIO31, AF4, FLOAT) ++#define GPIO77_UART1_RXD MFP_CFG_LPM(GPIO77, AF1, FLOAT) ++#define GPIO78_UART1_RXD MFP_CFG_LPM(GPIO78, AF3, FLOAT) ++#define GPIO99_UART1_RXD MFP_CFG_LPM(GPIO99, AF1, FLOAT) ++#define GPIO100_UART1_RXD MFP_CFG_LPM(GPIO100, AF6, FLOAT) ++#define GPIO102_UART1_RXD MFP_CFG_LPM(GPIO102, AF6, FLOAT) ++#define GPIO104_UART1_RXD MFP_CFG_LPM(GPIO104, AF4, FLOAT) ++ ++#define GPIO30_UART1_TXD MFP_CFG_LPM(GPIO30, AF4, FLOAT) ++#define GPIO31_UART1_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT) ++#define GPIO77_UART1_TXD MFP_CFG_LPM(GPIO77, AF3, FLOAT) ++#define GPIO78_UART1_TXD MFP_CFG_LPM(GPIO78, AF1, FLOAT) ++#define GPIO99_UART1_TXD MFP_CFG_LPM(GPIO99, AF6, FLOAT) ++#define GPIO100_UART1_TXD MFP_CFG_LPM(GPIO100, AF1, FLOAT) ++#define GPIO102_UART1_TXD MFP_CFG_LPM(GPIO102, AF4, FLOAT) ++ ++/* UART2 */ ++#define GPIO15_UART2_CTS MFP_CFG_LPM(GPIO15, AF3, FLOAT) ++#define GPIO16_UART2_CTS MFP_CFG_LPM(GPIO16, AF5, FLOAT) ++#define GPIO111_UART2_CTS MFP_CFG_LPM(GPIO111, AF3, FLOAT) ++#define GPIO114_UART2_CTS MFP_CFG_LPM(GPIO114, AF1, FLOAT) ++ ++#define GPIO15_UART2_RTS MFP_CFG_LPM(GPIO15, AF4, FLOAT) ++#define GPIO16_UART2_RTS MFP_CFG_LPM(GPIO16, AF4, FLOAT) ++#define GPIO114_UART2_RTS MFP_CFG_LPM(GPIO114, AF3, FLOAT) ++#define GPIO111_UART2_RTS MFP_CFG_LPM(GPIO111, AF1, FLOAT) ++ ++#define GPIO18_UART2_RXD MFP_CFG_LPM(GPIO18, AF5, FLOAT) ++#define GPIO19_UART2_RXD MFP_CFG_LPM(GPIO19, AF4, FLOAT) ++#define GPIO112_UART2_RXD MFP_CFG_LPM(GPIO112, AF1, FLOAT) ++#define GPIO113_UART2_RXD MFP_CFG_LPM(GPIO113, AF3, FLOAT) ++ ++#define GPIO18_UART2_TXD MFP_CFG_LPM(GPIO18, AF4, FLOAT) ++#define GPIO19_UART2_TXD MFP_CFG_LPM(GPIO19, AF5, FLOAT) ++#define GPIO112_UART2_TXD MFP_CFG_LPM(GPIO112, AF3, FLOAT) ++#define GPIO113_UART2_TXD MFP_CFG_LPM(GPIO113, AF1, FLOAT) ++ ++/* UART3 */ ++#define GPIO91_UART3_CTS MFP_CFG_LPM(GPIO91, AF2, FLOAT) ++#define GPIO92_UART3_CTS MFP_CFG_LPM(GPIO92, AF4, FLOAT) ++#define GPIO107_UART3_CTS MFP_CFG_LPM(GPIO107, AF1, FLOAT) ++#define GPIO108_UART3_CTS MFP_CFG_LPM(GPIO108, AF3, FLOAT) ++ ++#define GPIO91_UART3_RTS MFP_CFG_LPM(GPIO91, AF4, FLOAT) ++#define GPIO92_UART3_RTS MFP_CFG_LPM(GPIO92, AF2, FLOAT) ++#define GPIO107_UART3_RTS MFP_CFG_LPM(GPIO107, AF3, FLOAT) ++#define GPIO108_UART3_RTS MFP_CFG_LPM(GPIO108, AF1, FLOAT) ++ ++#define GPIO7_UART3_RXD MFP_CFG_LPM(GPIO7, AF2, FLOAT) ++#define GPIO8_UART3_RXD MFP_CFG_LPM(GPIO8, AF6, FLOAT) ++#define GPIO93_UART3_RXD MFP_CFG_LPM(GPIO93, AF4, FLOAT) ++#define GPIO94_UART3_RXD MFP_CFG_LPM(GPIO94, AF2, FLOAT) ++#define GPIO109_UART3_RXD MFP_CFG_LPM(GPIO109, AF3, FLOAT) ++#define GPIO110_UART3_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT) ++ ++#define GPIO7_UART3_TXD MFP_CFG_LPM(GPIO7, AF6, FLOAT) ++#define GPIO8_UART3_TXD MFP_CFG_LPM(GPIO8, AF2, FLOAT) ++#define GPIO93_UART3_TXD MFP_CFG_LPM(GPIO93, AF2, FLOAT) ++#define GPIO94_UART3_TXD MFP_CFG_LPM(GPIO94, AF4, FLOAT) ++#define GPIO109_UART3_TXD MFP_CFG_LPM(GPIO109, AF1, FLOAT) ++#define GPIO110_UART3_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT) ++ ++/* USB Host */ ++#define GPIO0_2_USBH_PEN MFP_CFG(GPIO0_2, AF1) ++#define GPIO1_2_USBH_PWR MFP_CFG(GPIO1_2, AF1) ++ ++/* USB P3 */ ++#define GPIO77_USB_P3_1 MFP_CFG(GPIO77, AF2) ++#define GPIO78_USB_P3_2 MFP_CFG(GPIO78, AF2) ++#define GPIO79_USB_P3_3 MFP_CFG(GPIO79, AF2) ++#define GPIO80_USB_P3_4 MFP_CFG(GPIO80, AF2) ++#define GPIO81_USB_P3_5 MFP_CFG(GPIO81, AF2) ++#define GPIO82_USB_P3_6 MFP_CFG(GPIO82, AF2) ++ ++/* PWM */ ++#define GPIO17_PWM0_OUT MFP_CFG(GPIO17, AF1) ++#define GPIO18_PWM1_OUT MFP_CFG(GPIO18, AF1) ++#define GPIO19_PWM2_OUT MFP_CFG(GPIO19, AF1) ++#define GPIO20_PWM3_OUT MFP_CFG(GPIO20, AF1) ++ ++/* CIR */ ++#define GPIO8_CIR_OUT MFP_CFG(GPIO8, AF5) ++#define GPIO16_CIR_OUT MFP_CFG(GPIO16, AF3) ++ ++#define GPIO20_OW_DQ_IN MFP_CFG(GPIO20, AF5) ++#define GPIO126_OW_DQ MFP_CFG(GPIO126, AF2) ++ ++#define GPIO0_DF_RDY MFP_CFG(GPIO0, AF1) ++#define GPIO7_CLK_BYPASS_XSC MFP_CFG(GPIO7, AF7) ++#define GPIO17_EXT_SYNC_MVT_0 MFP_CFG(GPIO17, AF6) ++#define GPIO18_EXT_SYNC_MVT_1 MFP_CFG(GPIO18, AF6) ++#define GPIO19_OST_CHOUT_MVT_0 MFP_CFG(GPIO19, AF6) ++#define GPIO20_OST_CHOUT_MVT_1 MFP_CFG(GPIO20, AF6) ++#define GPIO49_48M_CLK MFP_CFG(GPIO49, AF2) ++#define GPIO126_EXT_CLK MFP_CFG(GPIO126, AF3) ++#define GPIO127_CLK_BYPASS_GB MFP_CFG(GPIO127, AF7) ++#define GPIO71_EXT_MATCH_MVT MFP_CFG(GPIO71, AF6) ++ ++#define GPIO3_uIO_IN MFP_CFG(GPIO3, AF1) ++ ++#define GPIO4_uSIM_CARD_STATE MFP_CFG(GPIO4, AF1) ++#define GPIO5_uSIM_uCLK MFP_CFG(GPIO5, AF1) ++#define GPIO6_uSIM_uRST MFP_CFG(GPIO6, AF1) ++#define GPIO16_uSIM_UVS_0 MFP_CFG(GPIO16, AF1) ++ ++#define GPIO9_SCIO MFP_CFG(GPIO9, AF1) ++#define GPIO20_RTC_MVT MFP_CFG(GPIO20, AF4) ++#define GPIO126_RTC_MVT MFP_CFG(GPIO126, AF1) ++ ++/* ++ * PXA300 specific MFP configurations ++ */ ++#ifdef CONFIG_CPU_PXA300 ++#define GPIO99_USB_P2_2 MFP_CFG(GPIO99, AF2) ++#define GPIO99_USB_P2_5 MFP_CFG(GPIO99, AF3) ++#define GPIO99_USB_P2_6 MFP_CFG(GPIO99, AF4) ++#define GPIO100_USB_P2_2 MFP_CFG(GPIO100, AF4) ++#define GPIO100_USB_P2_5 MFP_CFG(GPIO100, AF5) ++#define GPIO101_USB_P2_1 MFP_CFG(GPIO101, AF2) ++#define GPIO102_USB_P2_4 MFP_CFG(GPIO102, AF2) ++#define GPIO104_USB_P2_3 MFP_CFG(GPIO104, AF2) ++#define GPIO105_USB_P2_5 MFP_CFG(GPIO105, AF2) ++#define GPIO100_USB_P2_6 MFP_CFG(GPIO100, AF2) ++#define GPIO106_USB_P2_7 MFP_CFG(GPIO106, AF2) ++#define GPIO103_USB_P2_8 MFP_CFG(GPIO103, AF2) ++ ++/* U2D UTMI */ ++#define GPIO38_UTM_CLK MFP_CFG(GPIO38, AF1) ++#define GPIO26_U2D_RXERROR MFP_CFG(GPIO26, AF3) ++#define GPIO50_U2D_RXERROR MFP_CFG(GPIO50, AF1) ++#define GPIO89_U2D_RXERROR MFP_CFG(GPIO89, AF5) ++#define GPIO24_UTM_RXVALID MFP_CFG(GPIO24, AF3) ++#define GPIO48_UTM_RXVALID MFP_CFG(GPIO48, AF2) ++#define GPIO87_UTM_RXVALID MFP_CFG(GPIO87, AF5) ++#define GPIO25_UTM_RXACTIVE MFP_CFG(GPIO25, AF3) ++#define GPIO47_UTM_RXACTIVE MFP_CFG(GPIO47, AF2) ++#define GPIO49_UTM_RXACTIVE MFP_CFG(GPIO49, AF1) ++#define GPIO88_UTM_RXACTIVE MFP_CFG(GPIO88, AF5) ++#define GPIO53_UTM_TXREADY MFP_CFG(GPIO53, AF1) ++#define GPIO67_UTM_LINESTATE_0 MFP_CFG(GPIO67, AF3) ++#define GPIO92_UTM_LINESTATE_0 MFP_CFG(GPIO92, AF3) ++#define GPIO104_UTM_LINESTATE_0 MFP_CFG(GPIO104, AF3) ++#define GPIO109_UTM_LINESTATE_0 MFP_CFG(GPIO109, AF4) ++#define GPIO68_UTM_LINESTATE_1 MFP_CFG(GPIO68, AF3) ++#define GPIO93_UTM_LINESTATE_1 MFP_CFG(GPIO93, AF3) ++#define GPIO105_UTM_LINESTATE_1 MFP_CFG(GPIO105, AF3) ++#define GPIO27_U2D_OPMODE_0 MFP_CFG(GPIO27, AF4) ++#define GPIO51_U2D_OPMODE_0 MFP_CFG(GPIO51, AF2) ++#define GPIO90_U2D_OPMODE_0 MFP_CFG(GPIO90, AF7) ++#define GPIO28_U2D_OPMODE_1 MFP_CFG(GPIO28, AF4) ++#define GPIO52_U2D_OPMODE_1 MFP_CFG(GPIO52, AF2) ++#define GPIO106_U2D_OPMODE_1 MFP_CFG(GPIO106, AF3) ++#define GPIO110_U2D_OPMODE_1 MFP_CFG(GPIO110, AF5) ++#define GPIO76_U2D_RESET MFP_CFG(GPIO76, AF1) ++#define GPIO95_U2D_RESET MFP_CFG(GPIO95, AF2) ++#define GPIO100_U2D_RESET MFP_CFG(GPIO100, AF3) ++#define GPIO66_U2D_SUSPEND MFP_CFG(GPIO66, AF3) ++#define GPIO98_U2D_SUSPEND MFP_CFG(GPIO98, AF2) ++#define GPIO103_U2D_SUSPEND MFP_CFG(GPIO103, AF3) ++#define GPIO65_U2D_TERM_SEL MFP_CFG(GPIO65, AF5) ++#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF3) ++#define GPIO102_U2D_TERM_SEL MFP_CFG(GPIO102, AF5) ++#define GPIO29_U2D_TXVALID MFP_CFG(GPIO29, AF3) ++#define GPIO52_U2D_TXVALID MFP_CFG(GPIO52, AF4) ++#define GPIO69_U2D_TXVALID MFP_CFG(GPIO69, AF3) ++#define GPIO85_U2D_TXVALID MFP_CFG(GPIO85, AF7) ++#define GPIO64_U2D_XCVR_SEL MFP_CFG(GPIO64, AF5) ++#define GPIO96_U2D_XCVR_SEL MFP_CFG(GPIO96, AF3) ++#define GPIO101_U2D_XCVR_SEL MFP_CFG(GPIO101, AF5) ++#define GPIO30_UTM_PHYDATA_0 MFP_CFG(GPIO30, AF3) ++#define GPIO31_UTM_PHYDATA_1 MFP_CFG(GPIO31, AF3) ++#define GPIO32_UTM_PHYDATA_2 MFP_CFG(GPIO32, AF3) ++#define GPIO33_UTM_PHYDATA_3 MFP_CFG(GPIO33, AF3) ++#define GPIO34_UTM_PHYDATA_4 MFP_CFG(GPIO34, AF3) ++#define GPIO35_UTM_PHYDATA_5 MFP_CFG(GPIO35, AF3) ++#define GPIO36_UTM_PHYDATA_6 MFP_CFG(GPIO36, AF3) ++#define GPIO37_UTM_PHYDATA_7 MFP_CFG(GPIO37, AF3) ++#define GPIO39_UTM_PHYDATA_0 MFP_CFG(GPIO39, AF3) ++#define GPIO40_UTM_PHYDATA_1 MFP_CFG(GPIO40, AF3) ++#define GPIO41_UTM_PHYDATA_2 MFP_CFG(GPIO41, AF3) ++#define GPIO42_UTM_PHYDATA_3 MFP_CFG(GPIO42, AF3) ++#define GPIO43_UTM_PHYDATA_4 MFP_CFG(GPIO43, AF3) ++#define GPIO44_UTM_PHYDATA_5 MFP_CFG(GPIO44, AF3) ++#define GPIO45_UTM_PHYDATA_6 MFP_CFG(GPIO45, AF3) ++#define GPIO46_UTM_PHYDATA_7 MFP_CFG(GPIO46, AF3) ++#endif /* CONFIG_CPU_PXA300 */ ++ ++/* ++ * PXA310 specific MFP configurations ++ */ ++#ifdef CONFIG_CPU_PXA310 ++/* USB P2 */ ++#define GPIO36_USB_P2_1 MFP_CFG(GPIO36, AF1) ++#define GPIO30_USB_P2_2 MFP_CFG(GPIO30, AF1) ++#define GPIO35_USB_P2_3 MFP_CFG(GPIO35, AF1) ++#define GPIO32_USB_P2_4 MFP_CFG(GPIO32, AF1) ++#define GPIO34_USB_P2_5 MFP_CFG(GPIO34, AF1) ++#define GPIO31_USB_P2_6 MFP_CFG(GPIO31, AF1) ++ ++/* MMC1 */ ++#define GPIO24_MMC1_CMD MFP_CFG(GPIO24, AF3) ++#define GPIO29_MMC1_DAT0 MFP_CFG(GPIO29, AF3) ++ ++/* MMC3 */ ++#define GPIO103_MMC3_CLK MFP_CFG(GPIO103, AF2) ++#define GPIO105_MMC3_CMD MFP_CFG(GPIO105, AF2) ++#define GPIO11_2_MMC3_CLK MFP_CFG(GPIO11_2, AF1) ++#define GPIO12_2_MMC3_CMD MFP_CFG(GPIO12_2, AF1) ++#define GPIO7_2_MMC3_DAT0 MFP_CFG(GPIO7_2, AF1) ++#define GPIO8_2_MMC3_DAT1 MFP_CFG(GPIO8_2, AF1) ++#define GPIO9_2_MMC3_DAT2 MFP_CFG(GPIO9_2, AF1) ++#define GPIO10_2_MMC3_DAT3 MFP_CFG(GPIO10_2, AF1) ++ ++/* ULPI */ ++#define GPIO38_ULPI_CLK MFP_CFG(GPIO38, AF1) ++#define GPIO30_ULPI_DATA_OUT_0 MFP_CFG(GPIO30, AF3) ++#define GPIO31_ULPI_DATA_OUT_1 MFP_CFG(GPIO31, AF3) ++#define GPIO32_ULPI_DATA_OUT_2 MFP_CFG(GPIO32, AF3) ++#define GPIO33_ULPI_DATA_OUT_3 MFP_CFG(GPIO33, AF3) ++#define GPIO34_ULPI_DATA_OUT_4 MFP_CFG(GPIO34, AF3) ++#define GPIO35_ULPI_DATA_OUT_5 MFP_CFG(GPIO35, AF3) ++#define GPIO36_ULPI_DATA_OUT_6 MFP_CFG(GPIO36, AF3) ++#define GPIO37_ULPI_DATA_OUT_7 MFP_CFG(GPIO37, AF3) ++#define GPIO33_ULPI_OTG_INTR MFP_CFG(GPIO33, AF1) ++ ++#define ULPI_DIR MFP_CFG_DRV(ULPI_DIR, MFP_AF0, MFP_DS01X) ++#define ULPI_NXT MFP_CFG_DRV(ULPI_NXT, MFP_AF0, MFP_DS01X) ++#define ULPI_STP MFP_CFG_DRV(ULPI_STP, MFP_AF0, MFP_DS01X) ++#endif /* CONFIG_CPU_PXA310 */ ++ ++#endif /* __ASM_ARCH_MFP_PXA300_H */ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/mfp-pxa320.h linux-2.6.25-rc4/include/asm-arm/arch/mfp-pxa320.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/mfp-pxa320.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/mfp-pxa320.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,447 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/mfp-pxa320.h ++ * ++ * PXA320 specific MFP configuration definitions ++ * ++ * Copyright (C) 2007 Marvell International Ltd. ++ * 2007-08-21: eric miao <eric.miao@marvell.com> ++ * initial version ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __ASM_ARCH_MFP_PXA320_H ++#define __ASM_ARCH_MFP_PXA320_H ++ ++#include <asm/arch/mfp.h> ++#include <asm/arch/mfp-pxa3xx.h> ++ ++/* GPIO */ ++#define GPIO46_GPIO MFP_CFG(GPIO46, AF0) ++#define GPIO49_GPIO MFP_CFG(GPIO49, AF0) ++#define GPIO50_GPIO MFP_CFG(GPIO50, AF0) ++#define GPIO51_GPIO MFP_CFG(GPIO51, AF0) ++#define GPIO52_GPIO MFP_CFG(GPIO52, AF0) ++ ++#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0) ++#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0) ++#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0) ++#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0) ++#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0) ++#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0) ++#define GPIO13_2_GPIO MFP_CFG(GPIO13_2, AF0) ++#define GPIO14_2_GPIO MFP_CFG(GPIO14_2, AF0) ++#define GPIO15_2_GPIO MFP_CFG(GPIO15_2, AF0) ++#define GPIO16_2_GPIO MFP_CFG(GPIO16_2, AF0) ++#define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0) ++ ++/* Chip Select */ ++#define GPIO4_nCS3 MFP_CFG(GPIO4, AF1) ++ ++/* AC97 */ ++#define GPIO34_AC97_SYSCLK MFP_CFG(GPIO34, AF1) ++#define GPIO39_AC97_BITCLK MFP_CFG(GPIO39, AF1) ++#define GPIO40_AC97_nACRESET MFP_CFG(GPIO40, AF1) ++#define GPIO35_AC97_SDATA_IN_0 MFP_CFG(GPIO35, AF1) ++#define GPIO36_AC97_SDATA_IN_1 MFP_CFG(GPIO36, AF1) ++#define GPIO32_AC97_SDATA_IN_2 MFP_CFG(GPIO32, AF2) ++#define GPIO33_AC97_SDATA_IN_3 MFP_CFG(GPIO33, AF2) ++#define GPIO11_AC97_SDATA_IN_2 MFP_CFG(GPIO11, AF3) ++#define GPIO12_AC97_SDATA_IN_3 MFP_CFG(GPIO12, AF3) ++#define GPIO37_AC97_SDATA_OUT MFP_CFG(GPIO37, AF1) ++#define GPIO38_AC97_SYNC MFP_CFG(GPIO38, AF1) ++ ++/* I2C */ ++#define GPIO32_I2C_SCL MFP_CFG_LPM(GPIO32, AF1, PULL_HIGH) ++#define GPIO33_I2C_SDA MFP_CFG_LPM(GPIO33, AF1, PULL_HIGH) ++ ++/* QCI */ ++#define GPIO49_CI_DD_0 MFP_CFG_DRV(GPIO49, AF1, DS04X) ++#define GPIO50_CI_DD_1 MFP_CFG_DRV(GPIO50, AF1, DS04X) ++#define GPIO51_CI_DD_2 MFP_CFG_DRV(GPIO51, AF1, DS04X) ++#define GPIO52_CI_DD_3 MFP_CFG_DRV(GPIO52, AF1, DS04X) ++#define GPIO53_CI_DD_4 MFP_CFG_DRV(GPIO53, AF1, DS04X) ++#define GPIO54_CI_DD_5 MFP_CFG_DRV(GPIO54, AF1, DS04X) ++#define GPIO55_CI_DD_6 MFP_CFG_DRV(GPIO55, AF1, DS04X) ++#define GPIO56_CI_DD_7 MFP_CFG_DRV(GPIO56, AF0, DS04X) ++#define GPIO57_CI_DD_8 MFP_CFG_DRV(GPIO57, AF1, DS04X) ++#define GPIO58_CI_DD_9 MFP_CFG_DRV(GPIO58, AF1, DS04X) ++#define GPIO59_CI_MCLK MFP_CFG_DRV(GPIO59, AF0, DS04X) ++#define GPIO60_CI_PCLK MFP_CFG_DRV(GPIO60, AF0, DS04X) ++#define GPIO61_CI_HSYNC MFP_CFG_DRV(GPIO61, AF0, DS04X) ++#define GPIO62_CI_VSYNC MFP_CFG_DRV(GPIO62, AF0, DS04X) ++ ++#define GPIO31_CIR_OUT MFP_CFG(GPIO31, AF5) ++ ++#define GPIO0_2_CLK_EXT MFP_CFG(GPIO0_2, AF3) ++#define GPIO0_DRQ MFP_CFG(GPIO0, AF2) ++#define GPIO11_EXT_SYNC0 MFP_CFG(GPIO11, AF5) ++#define GPIO12_EXT_SYNC1 MFP_CFG(GPIO12, AF6) ++#define GPIO0_2_HZ_CLK MFP_CFG(GPIO0_2, AF1) ++#define GPIO14_HZ_CLK MFP_CFG(GPIO14, AF4) ++#define GPIO30_ICP_RXD MFP_CFG(GPIO30, AF1) ++#define GPIO31_ICP_TXD MFP_CFG(GPIO31, AF1) ++ ++#define GPIO83_KP_DKIN_0 MFP_CFG_LPM(GPIO83, AF3, FLOAT) ++#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF3, FLOAT) ++#define GPIO85_KP_DKIN_2 MFP_CFG_LPM(GPIO85, AF3, FLOAT) ++#define GPIO86_KP_DKIN_3 MFP_CFG_LPM(GPIO86, AF3, FLOAT) ++ ++#define GPIO105_KP_DKIN_0 MFP_CFG_LPM(GPIO105, AF2, FLOAT) ++#define GPIO106_KP_DKIN_1 MFP_CFG_LPM(GPIO106, AF2, FLOAT) ++#define GPIO107_KP_DKIN_2 MFP_CFG_LPM(GPIO107, AF2, FLOAT) ++#define GPIO108_KP_DKIN_3 MFP_CFG_LPM(GPIO108, AF2, FLOAT) ++#define GPIO109_KP_DKIN_4 MFP_CFG_LPM(GPIO109, AF2, FLOAT) ++#define GPIO110_KP_DKIN_5 MFP_CFG_LPM(GPIO110, AF2, FLOAT) ++#define GPIO111_KP_DKIN_6 MFP_CFG_LPM(GPIO111, AF2, FLOAT) ++#define GPIO112_KP_DKIN_7 MFP_CFG_LPM(GPIO112, AF2, FLOAT) ++ ++#define GPIO113_KP_DKIN_0 MFP_CFG_LPM(GPIO113, AF2, FLOAT) ++#define GPIO114_KP_DKIN_1 MFP_CFG_LPM(GPIO114, AF2, FLOAT) ++#define GPIO115_KP_DKIN_2 MFP_CFG_LPM(GPIO115, AF2, FLOAT) ++#define GPIO116_KP_DKIN_3 MFP_CFG_LPM(GPIO116, AF2, FLOAT) ++#define GPIO117_KP_DKIN_4 MFP_CFG_LPM(GPIO117, AF2, FLOAT) ++#define GPIO118_KP_DKIN_5 MFP_CFG_LPM(GPIO118, AF2, FLOAT) ++#define GPIO119_KP_DKIN_6 MFP_CFG_LPM(GPIO119, AF2, FLOAT) ++#define GPIO120_KP_DKIN_7 MFP_CFG_LPM(GPIO120, AF2, FLOAT) ++ ++#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF2, FLOAT) ++#define GPIO126_KP_DKIN_1 MFP_CFG_LPM(GPIO126, AF2, FLOAT) ++ ++#define GPIO2_2_KP_DKIN_0 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT) ++#define GPIO3_2_KP_DKIN_1 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT) ++#define GPIO125_KP_DKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT) ++#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT) ++#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT) ++#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT) ++#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT) ++#define GPIO4_2_KP_DKIN_7 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT) ++ ++#define GPIO113_KP_MKIN_0 MFP_CFG_LPM(GPIO113, AF1, FLOAT) ++#define GPIO114_KP_MKIN_1 MFP_CFG_LPM(GPIO114, AF1, FLOAT) ++#define GPIO115_KP_MKIN_2 MFP_CFG_LPM(GPIO115, AF1, FLOAT) ++#define GPIO116_KP_MKIN_3 MFP_CFG_LPM(GPIO116, AF1, FLOAT) ++#define GPIO117_KP_MKIN_4 MFP_CFG_LPM(GPIO117, AF1, FLOAT) ++#define GPIO118_KP_MKIN_5 MFP_CFG_LPM(GPIO118, AF1, FLOAT) ++#define GPIO119_KP_MKIN_6 MFP_CFG_LPM(GPIO119, AF1, FLOAT) ++#define GPIO120_KP_MKIN_7 MFP_CFG_LPM(GPIO120, AF1, FLOAT) ++ ++#define GPIO83_KP_MKOUT_0 MFP_CFG_LPM(GPIO83, AF2, DRIVE_HIGH) ++#define GPIO84_KP_MKOUT_1 MFP_CFG_LPM(GPIO84, AF2, DRIVE_HIGH) ++#define GPIO85_KP_MKOUT_2 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH) ++#define GPIO86_KP_MKOUT_3 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH) ++#define GPIO13_KP_MKOUT_4 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH) ++#define GPIO14_KP_MKOUT_5 MFP_CFG_LPM(GPIO14, AF3, DRIVE_HIGH) ++ ++#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH) ++#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH) ++#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH) ++#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH) ++#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH) ++#define GPIO126_KP_MKOUT_5 MFP_CFG_LPM(GPIO126, AF1, DRIVE_HIGH) ++#define GPIO127_KP_MKOUT_6 MFP_CFG_LPM(GPIO127, AF1, DRIVE_HIGH) ++#define GPIO5_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH) ++ ++/* LCD */ ++#define GPIO6_2_LCD_LDD_0 MFP_CFG_DRV(GPIO6_2, AF1, DS01X) ++#define GPIO7_2_LCD_LDD_1 MFP_CFG_DRV(GPIO7_2, AF1, DS01X) ++#define GPIO8_2_LCD_LDD_2 MFP_CFG_DRV(GPIO8_2, AF1, DS01X) ++#define GPIO9_2_LCD_LDD_3 MFP_CFG_DRV(GPIO9_2, AF1, DS01X) ++#define GPIO10_2_LCD_LDD_4 MFP_CFG_DRV(GPIO10_2, AF1, DS01X) ++#define GPIO11_2_LCD_LDD_5 MFP_CFG_DRV(GPIO11_2, AF1, DS01X) ++#define GPIO12_2_LCD_LDD_6 MFP_CFG_DRV(GPIO12_2, AF1, DS01X) ++#define GPIO13_2_LCD_LDD_7 MFP_CFG_DRV(GPIO13_2, AF1, DS01X) ++#define GPIO63_LCD_LDD_8 MFP_CFG_DRV(GPIO63, AF1, DS01X) ++#define GPIO64_LCD_LDD_9 MFP_CFG_DRV(GPIO64, AF1, DS01X) ++#define GPIO65_LCD_LDD_10 MFP_CFG_DRV(GPIO65, AF1, DS01X) ++#define GPIO66_LCD_LDD_11 MFP_CFG_DRV(GPIO66, AF1, DS01X) ++#define GPIO67_LCD_LDD_12 MFP_CFG_DRV(GPIO67, AF1, DS01X) ++#define GPIO68_LCD_LDD_13 MFP_CFG_DRV(GPIO68, AF1, DS01X) ++#define GPIO69_LCD_LDD_14 MFP_CFG_DRV(GPIO69, AF1, DS01X) ++#define GPIO70_LCD_LDD_15 MFP_CFG_DRV(GPIO70, AF1, DS01X) ++#define GPIO71_LCD_LDD_16 MFP_CFG_DRV(GPIO71, AF1, DS01X) ++#define GPIO72_LCD_LDD_17 MFP_CFG_DRV(GPIO72, AF1, DS01X) ++#define GPIO73_LCD_CS_N MFP_CFG_DRV(GPIO73, AF2, DS01X) ++#define GPIO74_LCD_VSYNC MFP_CFG_DRV(GPIO74, AF2, DS01X) ++#define GPIO14_2_LCD_FCLK MFP_CFG_DRV(GPIO14_2, AF1, DS01X) ++#define GPIO15_2_LCD_LCLK MFP_CFG_DRV(GPIO15_2, AF1, DS01X) ++#define GPIO16_2_LCD_PCLK MFP_CFG_DRV(GPIO16_2, AF1, DS01X) ++#define GPIO17_2_LCD_BIAS MFP_CFG_DRV(GPIO17_2, AF1, DS01X) ++#define GPIO64_LCD_VSYNC MFP_CFG_DRV(GPIO64, AF2, DS01X) ++#define GPIO63_LCD_CS_N MFP_CFG_DRV(GPIO63, AF2, DS01X) ++ ++#define GPIO6_2_MLCD_DD_0 MFP_CFG_DRV(GPIO6_2, AF7, DS08X) ++#define GPIO7_2_MLCD_DD_1 MFP_CFG_DRV(GPIO7_2, AF7, DS08X) ++#define GPIO8_2_MLCD_DD_2 MFP_CFG_DRV(GPIO8_2, AF7, DS08X) ++#define GPIO9_2_MLCD_DD_3 MFP_CFG_DRV(GPIO9_2, AF7, DS08X) ++#define GPIO10_2_MLCD_DD_4 MFP_CFG_DRV(GPIO10_2, AF7, DS08X) ++#define GPIO11_2_MLCD_DD_5 MFP_CFG_DRV(GPIO11_2, AF7, DS08X) ++#define GPIO12_2_MLCD_DD_6 MFP_CFG_DRV(GPIO12_2, AF7, DS08X) ++#define GPIO13_2_MLCD_DD_7 MFP_CFG_DRV(GPIO13_2, AF7, DS08X) ++#define GPIO63_MLCD_DD_8 MFP_CFG_DRV(GPIO63, AF7, DS08X) ++#define GPIO64_MLCD_DD_9 MFP_CFG_DRV(GPIO64, AF7, DS08X) ++#define GPIO65_MLCD_DD_10 MFP_CFG_DRV(GPIO65, AF7, DS08X) ++#define GPIO66_MLCD_DD_11 MFP_CFG_DRV(GPIO66, AF7, DS08X) ++#define GPIO67_MLCD_DD_12 MFP_CFG_DRV(GPIO67, AF7, DS08X) ++#define GPIO68_MLCD_DD_13 MFP_CFG_DRV(GPIO68, AF7, DS08X) ++#define GPIO69_MLCD_DD_14 MFP_CFG_DRV(GPIO69, AF7, DS08X) ++#define GPIO70_MLCD_DD_15 MFP_CFG_DRV(GPIO70, AF7, DS08X) ++#define GPIO71_MLCD_DD_16 MFP_CFG_DRV(GPIO71, AF7, DS08X) ++#define GPIO72_MLCD_DD_17 MFP_CFG_DRV(GPIO72, AF7, DS08X) ++#define GPIO73_MLCD_CS MFP_CFG_DRV(GPIO73, AF7, DS08X) ++#define GPIO74_MLCD_VSYNC MFP_CFG_DRV(GPIO74, AF7, DS08X) ++#define GPIO14_2_MLCD_FCLK MFP_CFG_DRV(GPIO14_2, AF7, DS08X) ++#define GPIO15_2_MLCD_LCLK MFP_CFG_DRV(GPIO15_2, AF7, DS08X) ++#define GPIO16_2_MLCD_PCLK MFP_CFG_DRV(GPIO16_2, AF7, DS08X) ++#define GPIO17_2_MLCD_BIAS MFP_CFG_DRV(GPIO17_2, AF7, DS08X) ++ ++/* MMC1 */ ++#define GPIO9_MMC1_CMD MFP_CFG_LPM(GPIO9, AF4, DRIVE_HIGH) ++#define GPIO22_MMC1_CLK MFP_CFG_LPM(GPIO22, AF4, DRIVE_HIGH) ++#define GPIO23_MMC1_CMD MFP_CFG_LPM(GPIO23, AF4, DRIVE_HIGH) ++#define GPIO30_MMC1_CLK MFP_CFG_LPM(GPIO30, AF4, DRIVE_HIGH) ++#define GPIO31_MMC1_CMD MFP_CFG_LPM(GPIO31, AF4, DRIVE_HIGH) ++#define GPIO5_MMC1_DAT0 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH) ++#define GPIO6_MMC1_DAT1 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH) ++#define GPIO7_MMC1_DAT2 MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH) ++#define GPIO8_MMC1_DAT3 MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH) ++#define GPIO18_MMC1_DAT0 MFP_CFG_LPM(GPIO18, AF4, DRIVE_HIGH) ++#define GPIO19_MMC1_DAT1 MFP_CFG_LPM(GPIO19, AF4, DRIVE_HIGH) ++#define GPIO20_MMC1_DAT2 MFP_CFG_LPM(GPIO20, AF4, DRIVE_HIGH) ++#define GPIO21_MMC1_DAT3 MFP_CFG_LPM(GPIO21, AF4, DRIVE_HIGH) ++ ++#define GPIO28_MMC2_CLK MFP_CFG_LPM(GPIO28, AF4, PULL_HIGH) ++#define GPIO29_MMC2_CMD MFP_CFG_LPM(GPIO29, AF4, PULL_HIGH) ++#define GPIO30_MMC2_CLK MFP_CFG_LPM(GPIO30, AF3, PULL_HIGH) ++#define GPIO31_MMC2_CMD MFP_CFG_LPM(GPIO31, AF3, PULL_HIGH) ++#define GPIO79_MMC2_CLK MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH) ++#define GPIO80_MMC2_CMD MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH) ++ ++#define GPIO5_MMC2_DAT0 MFP_CFG_LPM(GPIO5, AF2, PULL_HIGH) ++#define GPIO6_MMC2_DAT1 MFP_CFG_LPM(GPIO6, AF2, PULL_HIGH) ++#define GPIO7_MMC2_DAT2 MFP_CFG_LPM(GPIO7, AF2, PULL_HIGH) ++#define GPIO8_MMC2_DAT3 MFP_CFG_LPM(GPIO8, AF2, PULL_HIGH) ++#define GPIO24_MMC2_DAT0 MFP_CFG_LPM(GPIO24, AF4, PULL_HIGH) ++#define GPIO75_MMC2_DAT0 MFP_CFG_LPM(GPIO75, AF4, PULL_HIGH) ++#define GPIO25_MMC2_DAT1 MFP_CFG_LPM(GPIO25, AF4, PULL_HIGH) ++#define GPIO76_MMC2_DAT1 MFP_CFG_LPM(GPIO76, AF4, PULL_HIGH) ++#define GPIO26_MMC2_DAT2 MFP_CFG_LPM(GPIO26, AF4, PULL_HIGH) ++#define GPIO77_MMC2_DAT2 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH) ++#define GPIO27_MMC2_DAT3 MFP_CFG_LPM(GPIO27, AF4, PULL_HIGH) ++#define GPIO78_MMC2_DAT3 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH) ++ ++/* 1-Wire */ ++#define GPIO14_ONE_WIRE MFP_CFG_LPM(GPIO14, AF5, FLOAT) ++#define GPIO0_2_ONE_WIRE MFP_CFG_LPM(GPIO0_2, AF2, FLOAT) ++ ++/* SSP1 */ ++#define GPIO87_SSP1_EXTCLK MFP_CFG(GPIO87, AF1) ++#define GPIO88_SSP1_SYSCLK MFP_CFG(GPIO88, AF1) ++#define GPIO83_SSP1_SCLK MFP_CFG(GPIO83, AF1) ++#define GPIO84_SSP1_SFRM MFP_CFG(GPIO84, AF1) ++#define GPIO85_SSP1_RXD MFP_CFG(GPIO85, AF6) ++#define GPIO85_SSP1_TXD MFP_CFG(GPIO85, AF1) ++#define GPIO86_SSP1_RXD MFP_CFG(GPIO86, AF1) ++#define GPIO86_SSP1_TXD MFP_CFG(GPIO86, AF6) ++ ++/* SSP2 */ ++#define GPIO39_SSP2_EXTCLK MFP_CFG(GPIO39, AF2) ++#define GPIO40_SSP2_SYSCLK MFP_CFG(GPIO40, AF2) ++#define GPIO12_SSP2_SCLK MFP_CFG(GPIO12, AF2) ++#define GPIO35_SSP2_SCLK MFP_CFG(GPIO35, AF2) ++#define GPIO36_SSP2_SFRM MFP_CFG(GPIO36, AF2) ++#define GPIO37_SSP2_RXD MFP_CFG(GPIO37, AF5) ++#define GPIO37_SSP2_TXD MFP_CFG(GPIO37, AF2) ++#define GPIO38_SSP2_RXD MFP_CFG(GPIO38, AF2) ++#define GPIO38_SSP2_TXD MFP_CFG(GPIO38, AF5) ++ ++#define GPIO69_SSP3_SCLK MFP_CFG(GPIO69, AF2, DS08X, FLOAT) ++#define GPIO70_SSP3_FRM MFP_CFG(GPIO70, AF2, DS08X, DRIVE_LOW) ++#define GPIO89_SSP3_SCLK MFP_CFG(GPIO89, AF1, DS08X, FLOAT) ++#define GPIO90_SSP3_FRM MFP_CFG(GPIO90, AF1, DS08X, DRIVE_LOW) ++#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT) ++#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW) ++#define GPIO72_SSP3_RXD MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT) ++#define GPIO72_SSP3_TXD MFP_CFG_X(GPIO72, AF5, DS08X, DRIVE_LOW) ++#define GPIO91_SSP3_RXD MFP_CFG_X(GPIO91, AF5, DS08X, FLOAT) ++#define GPIO91_SSP3_TXD MFP_CFG_X(GPIO91, AF1, DS08X, DRIVE_LOW) ++#define GPIO92_SSP3_RXD MFP_CFG_X(GPIO92, AF1, DS08X, FLOAT) ++#define GPIO92_SSP3_TXD MFP_CFG_X(GPIO92, AF5, DS08X, DRIVE_LOW) ++ ++#define GPIO93_SSP4_SCLK MFP_CFG_LPM(GPIO93, AF1, PULL_HIGH) ++#define GPIO94_SSP4_FRM MFP_CFG_LPM(GPIO94, AF1, PULL_HIGH) ++#define GPIO94_SSP4_RXD MFP_CFG_LPM(GPIO94, AF5, PULL_HIGH) ++#define GPIO95_SSP4_RXD MFP_CFG_LPM(GPIO95, AF5, PULL_HIGH) ++#define GPIO95_SSP4_TXD MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) ++#define GPIO96_SSP4_RXD MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) ++#define GPIO96_SSP4_TXD MFP_CFG_LPM(GPIO96, AF5, PULL_HIGH) ++ ++/* UART1 */ ++#define GPIO41_UART1_RXD MFP_CFG_LPM(GPIO41, AF2, FLOAT) ++#define GPIO41_UART1_TXD MFP_CFG_LPM(GPIO41, AF4, FLOAT) ++#define GPIO42_UART1_RXD MFP_CFG_LPM(GPIO42, AF4, FLOAT) ++#define GPIO42_UART1_TXD MFP_CFG_LPM(GPIO42, AF2, FLOAT) ++#define GPIO97_UART1_RXD MFP_CFG_LPM(GPIO97, AF1, FLOAT) ++#define GPIO97_UART1_TXD MFP_CFG_LPM(GPIO97, AF6, FLOAT) ++#define GPIO98_UART1_RXD MFP_CFG_LPM(GPIO98, AF6, FLOAT) ++#define GPIO98_UART1_TXD MFP_CFG_LPM(GPIO98, AF1, FLOAT) ++#define GPIO43_UART1_CTS MFP_CFG_LPM(GPIO43, AF2, FLOAT) ++#define GPIO43_UART1_RTS MFP_CFG_LPM(GPIO43, AF4, FLOAT) ++#define GPIO48_UART1_CTS MFP_CFG_LPM(GPIO48, AF4, FLOAT) ++#define GPIO48_UART1_RTS MFP_CFG_LPM(GPIO48, AF2, FLOAT) ++#define GPIO99_UART1_CTS MFP_CFG_LPM(GPIO99, AF1, FLOAT) ++#define GPIO99_UART1_RTS MFP_CFG_LPM(GPIO99, AF6, FLOAT) ++#define GPIO104_UART1_CTS MFP_CFG_LPM(GPIO104, AF6, FLOAT) ++#define GPIO104_UART1_RTS MFP_CFG_LPM(GPIO104, AF1, FLOAT) ++#define GPIO45_UART1_DTR MFP_CFG_LPM(GPIO45, AF4, FLOAT) ++#define GPIO45_UART1_DSR MFP_CFG_LPM(GPIO45, AF2, FLOAT) ++#define GPIO47_UART1_DTR MFP_CFG_LPM(GPIO47, AF2, FLOAT) ++#define GPIO47_UART1_DSR MFP_CFG_LPM(GPIO47, AF4, FLOAT) ++#define GPIO101_UART1_DTR MFP_CFG_LPM(GPIO101, AF6, FLOAT) ++#define GPIO101_UART1_DSR MFP_CFG_LPM(GPIO101, AF1, FLOAT) ++#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF1, FLOAT) ++#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF6, FLOAT) ++#define GPIO44_UART1_DCD MFP_CFG_LPM(GPIO44, AF2, FLOAT) ++#define GPIO100_UART1_DCD MFP_CFG_LPM(GPIO100, AF1, FLOAT) ++#define GPIO46_UART1_RI MFP_CFG_LPM(GPIO46, AF2, FLOAT) ++#define GPIO102_UART1_RI MFP_CFG_LPM(GPIO102, AF1, FLOAT) ++ ++/* UART2 */ ++#define GPIO109_UART2_CTS MFP_CFG_LPM(GPIO109, AF3, FLOAT) ++#define GPIO109_UART2_RTS MFP_CFG_LPM(GPIO109, AF1, FLOAT) ++#define GPIO112_UART2_CTS MFP_CFG_LPM(GPIO112, AF1, FLOAT) ++#define GPIO112_UART2_RTS MFP_CFG_LPM(GPIO112, AF3, FLOAT) ++#define GPIO110_UART2_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT) ++#define GPIO110_UART2_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT) ++#define GPIO111_UART2_RXD MFP_CFG_LPM(GPIO111, AF3, FLOAT) ++#define GPIO111_UART2_TXD MFP_CFG_LPM(GPIO111, AF1, FLOAT) ++ ++/* UART3 */ ++#define GPIO89_UART3_CTS MFP_CFG_LPM(GPIO89, AF2, FLOAT) ++#define GPIO89_UART3_RTS MFP_CFG_LPM(GPIO89, AF4, FLOAT) ++#define GPIO90_UART3_CTS MFP_CFG_LPM(GPIO90, AF4, FLOAT) ++#define GPIO90_UART3_RTS MFP_CFG_LPM(GPIO90, AF2, FLOAT) ++#define GPIO105_UART3_CTS MFP_CFG_LPM(GPIO105, AF1, FLOAT) ++#define GPIO105_UART3_RTS MFP_CFG_LPM(GPIO105, AF3, FLOAT) ++#define GPIO106_UART3_CTS MFP_CFG_LPM(GPIO106, AF3, FLOAT) ++#define GPIO106_UART3_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT) ++#define GPIO30_UART3_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT) ++#define GPIO30_UART3_TXD MFP_CFG_LPM(GPIO30, AF6, FLOAT) ++#define GPIO31_UART3_RXD MFP_CFG_LPM(GPIO31, AF6, FLOAT) ++#define GPIO31_UART3_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT) ++#define GPIO91_UART3_RXD MFP_CFG_LPM(GPIO91, AF4, FLOAT) ++#define GPIO91_UART3_TXD MFP_CFG_LPM(GPIO91, AF2, FLOAT) ++#define GPIO92_UART3_RXD MFP_CFG_LPM(GPIO92, AF2, FLOAT) ++#define GPIO92_UART3_TXD MFP_CFG_LPM(GPIO92, AF4, FLOAT) ++#define GPIO107_UART3_RXD MFP_CFG_LPM(GPIO107, AF3, FLOAT) ++#define GPIO107_UART3_TXD MFP_CFG_LPM(GPIO107, AF1, FLOAT) ++#define GPIO108_UART3_RXD MFP_CFG_LPM(GPIO108, AF1, FLOAT) ++#define GPIO108_UART3_TXD MFP_CFG_LPM(GPIO108, AF3, FLOAT) ++ ++ ++/* USB 2.0 UTMI */ ++#define GPIO10_UTM_CLK MFP_CFG(GPIO10, AF1) ++#define GPIO36_U2D_RXERROR MFP_CFG(GPIO36, AF3) ++#define GPIO60_U2D_RXERROR MFP_CFG(GPIO60, AF1) ++#define GPIO87_U2D_RXERROR MFP_CFG(GPIO87, AF5) ++#define GPIO34_UTM_RXVALID MFP_CFG(GPIO34, AF3) ++#define GPIO58_UTM_RXVALID MFP_CFG(GPIO58, AF2) ++#define GPIO85_UTM_RXVALID MFP_CFG(GPIO85, AF5) ++#define GPIO35_UTM_RXACTIVE MFP_CFG(GPIO35, AF3) ++#define GPIO59_UTM_RXACTIVE MFP_CFG(GPIO59, AF1) ++#define GPIO86_UTM_RXACTIVE MFP_CFG(GPIO86, AF5) ++#define GPIO73_UTM_TXREADY MFP_CFG(GPIO73, AF1) ++#define GPIO68_UTM_LINESTATE_0 MFP_CFG(GPIO68, AF3) ++#define GPIO90_UTM_LINESTATE_0 MFP_CFG(GPIO90, AF3) ++#define GPIO102_UTM_LINESTATE_0 MFP_CFG(GPIO102, AF3) ++#define GPIO107_UTM_LINESTATE_0 MFP_CFG(GPIO107, AF4) ++#define GPIO69_UTM_LINESTATE_1 MFP_CFG(GPIO69, AF3) ++#define GPIO91_UTM_LINESTATE_1 MFP_CFG(GPIO91, AF3) ++#define GPIO103_UTM_LINESTATE_1 MFP_CFG(GPIO103, AF3) ++ ++#define GPIO41_U2D_PHYDATA_0 MFP_CFG(GPIO41, AF3) ++#define GPIO42_U2D_PHYDATA_1 MFP_CFG(GPIO42, AF3) ++#define GPIO43_U2D_PHYDATA_2 MFP_CFG(GPIO43, AF3) ++#define GPIO44_U2D_PHYDATA_3 MFP_CFG(GPIO44, AF3) ++#define GPIO45_U2D_PHYDATA_4 MFP_CFG(GPIO45, AF3) ++#define GPIO46_U2D_PHYDATA_5 MFP_CFG(GPIO46, AF3) ++#define GPIO47_U2D_PHYDATA_6 MFP_CFG(GPIO47, AF3) ++#define GPIO48_U2D_PHYDATA_7 MFP_CFG(GPIO48, AF3) ++ ++#define GPIO49_U2D_PHYDATA_0 MFP_CFG(GPIO49, AF3) ++#define GPIO50_U2D_PHYDATA_1 MFP_CFG(GPIO50, AF3) ++#define GPIO51_U2D_PHYDATA_2 MFP_CFG(GPIO51, AF3) ++#define GPIO52_U2D_PHYDATA_3 MFP_CFG(GPIO52, AF3) ++#define GPIO53_U2D_PHYDATA_4 MFP_CFG(GPIO53, AF3) ++#define GPIO54_U2D_PHYDATA_5 MFP_CFG(GPIO54, AF3) ++#define GPIO55_U2D_PHYDATA_6 MFP_CFG(GPIO55, AF3) ++#define GPIO56_U2D_PHYDATA_7 MFP_CFG(GPIO56, AF3) ++ ++#define GPIO37_U2D_OPMODE0 MFP_CFG(GPIO37, AF4) ++#define GPIO61_U2D_OPMODE0 MFP_CFG(GPIO61, AF2) ++#define GPIO88_U2D_OPMODE0 MFP_CFG(GPIO88, AF7) ++ ++#define GPIO38_U2D_OPMODE1 MFP_CFG(GPIO38, AF4) ++#define GPIO62_U2D_OPMODE1 MFP_CFG(GPIO62, AF2) ++#define GPIO104_U2D_OPMODE1 MFP_CFG(GPIO104, AF4) ++#define GPIO108_U2D_OPMODE1 MFP_CFG(GPIO108, AF5) ++ ++#define GPIO74_U2D_RESET MFP_CFG(GPIO74, AF1) ++#define GPIO93_U2D_RESET MFP_CFG(GPIO93, AF2) ++#define GPIO98_U2D_RESET MFP_CFG(GPIO98, AF3) ++ ++#define GPIO67_U2D_SUSPEND MFP_CFG(GPIO67, AF3) ++#define GPIO96_U2D_SUSPEND MFP_CFG(GPIO96, AF2) ++#define GPIO101_U2D_SUSPEND MFP_CFG(GPIO101, AF3) ++ ++#define GPIO66_U2D_TERM_SEL MFP_CFG(GPIO66, AF5) ++#define GPIO95_U2D_TERM_SEL MFP_CFG(GPIO95, AF3) ++#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF7) ++#define GPIO100_U2D_TERM_SEL MFP_CFG(GPIO100, AF5) ++ ++#define GPIO39_U2D_TXVALID MFP_CFG(GPIO39, AF4) ++#define GPIO70_U2D_TXVALID MFP_CFG(GPIO70, AF5) ++#define GPIO83_U2D_TXVALID MFP_CFG(GPIO83, AF7) ++ ++#define GPIO65_U2D_XCVR_SEL MFP_CFG(GPIO65, AF5) ++#define GPIO94_U2D_XCVR_SEL MFP_CFG(GPIO94, AF3) ++#define GPIO99_U2D_XCVR_SEL MFP_CFG(GPIO99, AF5) ++ ++/* USB Host 1.1 */ ++#define GPIO2_2_USBH_PEN MFP_CFG(GPIO2_2, AF1) ++#define GPIO3_2_USBH_PWR MFP_CFG(GPIO3_2, AF1) ++ ++/* USB P2 */ ++#define GPIO97_USB_P2_2 MFP_CFG(GPIO97, AF2) ++#define GPIO97_USB_P2_6 MFP_CFG(GPIO97, AF4) ++#define GPIO98_USB_P2_2 MFP_CFG(GPIO98, AF4) ++#define GPIO98_USB_P2_6 MFP_CFG(GPIO98, AF2) ++#define GPIO99_USB_P2_1 MFP_CFG(GPIO99, AF2) ++#define GPIO100_USB_P2_4 MFP_CFG(GPIO100, AF2) ++#define GPIO101_USB_P2_8 MFP_CFG(GPIO101, AF2) ++#define GPIO102_USB_P2_3 MFP_CFG(GPIO102, AF2) ++#define GPIO103_USB_P2_5 MFP_CFG(GPIO103, AF2) ++#define GPIO104_USB_P2_7 MFP_CFG(GPIO104, AF2) ++ ++/* USB P3 */ ++#define GPIO75_USB_P3_1 MFP_CFG(GPIO75, AF2) ++#define GPIO76_USB_P3_2 MFP_CFG(GPIO76, AF2) ++#define GPIO77_USB_P3_3 MFP_CFG(GPIO77, AF2) ++#define GPIO78_USB_P3_4 MFP_CFG(GPIO78, AF2) ++#define GPIO79_USB_P3_5 MFP_CFG(GPIO79, AF2) ++#define GPIO80_USB_P3_6 MFP_CFG(GPIO80, AF2) ++ ++#define GPIO13_CHOUT0 MFP_CFG(GPIO13, AF6) ++#define GPIO14_CHOUT1 MFP_CFG(GPIO14, AF6) ++ ++#define GPIO2_RDY MFP_CFG(GPIO2, AF1) ++#define GPIO5_NPIOR MFP_CFG(GPIO5, AF3) ++ ++#define GPIO11_PWM0_OUT MFP_CFG(GPIO11, AF1) ++#define GPIO12_PWM1_OUT MFP_CFG(GPIO12, AF1) ++#define GPIO13_PWM2_OUT MFP_CFG(GPIO13, AF1) ++#define GPIO14_PWM3_OUT MFP_CFG(GPIO14, AF1) ++ ++#endif /* __ASM_ARCH_MFP_PXA320_H */ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/mfp-pxa3xx.h linux-2.6.25-rc4/include/asm-arm/arch/mfp-pxa3xx.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/mfp-pxa3xx.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/mfp-pxa3xx.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,252 @@ ++#ifndef __ASM_ARCH_MFP_PXA3XX_H ++#define __ASM_ARCH_MFP_PXA3XX_H ++ ++#define MFPR_BASE (0x40e10000) ++#define MFPR_SIZE (PAGE_SIZE) ++ ++/* MFPR register bit definitions */ ++#define MFPR_PULL_SEL (0x1 << 15) ++#define MFPR_PULLUP_EN (0x1 << 14) ++#define MFPR_PULLDOWN_EN (0x1 << 13) ++#define MFPR_SLEEP_SEL (0x1 << 9) ++#define MFPR_SLEEP_OE_N (0x1 << 7) ++#define MFPR_EDGE_CLEAR (0x1 << 6) ++#define MFPR_EDGE_FALL_EN (0x1 << 5) ++#define MFPR_EDGE_RISE_EN (0x1 << 4) ++ ++#define MFPR_SLEEP_DATA(x) ((x) << 8) ++#define MFPR_DRIVE(x) (((x) & 0x7) << 10) ++#define MFPR_AF_SEL(x) (((x) & 0x7) << 0) ++ ++#define MFPR_EDGE_NONE (0) ++#define MFPR_EDGE_RISE (MFPR_EDGE_RISE_EN) ++#define MFPR_EDGE_FALL (MFPR_EDGE_FALL_EN) ++#define MFPR_EDGE_BOTH (MFPR_EDGE_RISE | MFPR_EDGE_FALL) ++ ++/* ++ * Table that determines the low power modes outputs, with actual settings ++ * used in parentheses for don't-care values. Except for the float output, ++ * the configured driven and pulled levels match, so if there is a need for ++ * non-LPM pulled output, the same configuration could probably be used. ++ * ++ * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel ++ * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15) ++ * ++ * Input 0 X(0) X(0) X(0) 0 ++ * Drive 0 0 0 0 X(1) 0 ++ * Drive 1 0 1 X(1) 0 0 ++ * Pull hi (1) 1 X(1) 1 0 0 ++ * Pull lo (0) 1 X(0) 0 1 0 ++ * Z (float) 1 X(0) 0 0 0 ++ */ ++#define MFPR_LPM_INPUT (0) ++#define MFPR_LPM_DRIVE_LOW (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN) ++#define MFPR_LPM_DRIVE_HIGH (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN) ++#define MFPR_LPM_PULL_LOW (MFPR_LPM_DRIVE_LOW | MFPR_SLEEP_OE_N) ++#define MFPR_LPM_PULL_HIGH (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N) ++#define MFPR_LPM_FLOAT (MFPR_SLEEP_OE_N) ++#define MFPR_LPM_MASK (0xe080) ++ ++/* ++ * The pullup and pulldown state of the MFP pin at run mode is by default ++ * determined by the selected alternate function. In case that some buggy ++ * devices need to override this default behavior, the definitions below ++ * indicates the setting of corresponding MFPR bits ++ * ++ * Definition pull_sel pullup_en pulldown_en ++ * MFPR_PULL_NONE 0 0 0 ++ * MFPR_PULL_LOW 1 0 1 ++ * MFPR_PULL_HIGH 1 1 0 ++ * MFPR_PULL_BOTH 1 1 1 ++ */ ++#define MFPR_PULL_NONE (0) ++#define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN) ++#define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN) ++#define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN) ++ ++/* PXA3xx common MFP configurations - processor specific ones defined ++ * in mfp-pxa300.h and mfp-pxa320.h ++ */ ++#define GPIO0_GPIO MFP_CFG(GPIO0, AF0) ++#define GPIO1_GPIO MFP_CFG(GPIO1, AF0) ++#define GPIO2_GPIO MFP_CFG(GPIO2, AF0) ++#define GPIO3_GPIO MFP_CFG(GPIO3, AF0) ++#define GPIO4_GPIO MFP_CFG(GPIO4, AF0) ++#define GPIO5_GPIO MFP_CFG(GPIO5, AF0) ++#define GPIO6_GPIO MFP_CFG(GPIO6, AF0) ++#define GPIO7_GPIO MFP_CFG(GPIO7, AF0) ++#define GPIO8_GPIO MFP_CFG(GPIO8, AF0) ++#define GPIO9_GPIO MFP_CFG(GPIO9, AF0) ++#define GPIO10_GPIO MFP_CFG(GPIO10, AF0) ++#define GPIO11_GPIO MFP_CFG(GPIO11, AF0) ++#define GPIO12_GPIO MFP_CFG(GPIO12, AF0) ++#define GPIO13_GPIO MFP_CFG(GPIO13, AF0) ++#define GPIO14_GPIO MFP_CFG(GPIO14, AF0) ++#define GPIO15_GPIO MFP_CFG(GPIO15, AF0) ++#define GPIO16_GPIO MFP_CFG(GPIO16, AF0) ++#define GPIO17_GPIO MFP_CFG(GPIO17, AF0) ++#define GPIO18_GPIO MFP_CFG(GPIO18, AF0) ++#define GPIO19_GPIO MFP_CFG(GPIO19, AF0) ++#define GPIO20_GPIO MFP_CFG(GPIO20, AF0) ++#define GPIO21_GPIO MFP_CFG(GPIO21, AF0) ++#define GPIO22_GPIO MFP_CFG(GPIO22, AF0) ++#define GPIO23_GPIO MFP_CFG(GPIO23, AF0) ++#define GPIO24_GPIO MFP_CFG(GPIO24, AF0) ++#define GPIO25_GPIO MFP_CFG(GPIO25, AF0) ++#define GPIO26_GPIO MFP_CFG(GPIO26, AF0) ++#define GPIO27_GPIO MFP_CFG(GPIO27, AF0) ++#define GPIO28_GPIO MFP_CFG(GPIO28, AF0) ++#define GPIO29_GPIO MFP_CFG(GPIO29, AF0) ++#define GPIO30_GPIO MFP_CFG(GPIO30, AF0) ++#define GPIO31_GPIO MFP_CFG(GPIO31, AF0) ++#define GPIO32_GPIO MFP_CFG(GPIO32, AF0) ++#define GPIO33_GPIO MFP_CFG(GPIO33, AF0) ++#define GPIO34_GPIO MFP_CFG(GPIO34, AF0) ++#define GPIO35_GPIO MFP_CFG(GPIO35, AF0) ++#define GPIO36_GPIO MFP_CFG(GPIO36, AF0) ++#define GPIO37_GPIO MFP_CFG(GPIO37, AF0) ++#define GPIO38_GPIO MFP_CFG(GPIO38, AF0) ++#define GPIO39_GPIO MFP_CFG(GPIO39, AF0) ++#define GPIO40_GPIO MFP_CFG(GPIO40, AF0) ++#define GPIO41_GPIO MFP_CFG(GPIO41, AF0) ++#define GPIO42_GPIO MFP_CFG(GPIO42, AF0) ++#define GPIO43_GPIO MFP_CFG(GPIO43, AF0) ++#define GPIO44_GPIO MFP_CFG(GPIO44, AF0) ++#define GPIO45_GPIO MFP_CFG(GPIO45, AF0) ++ ++#define GPIO47_GPIO MFP_CFG(GPIO47, AF0) ++#define GPIO48_GPIO MFP_CFG(GPIO48, AF0) ++ ++#define GPIO53_GPIO MFP_CFG(GPIO53, AF0) ++#define GPIO54_GPIO MFP_CFG(GPIO54, AF0) ++#define GPIO55_GPIO MFP_CFG(GPIO55, AF0) ++ ++#define GPIO57_GPIO MFP_CFG(GPIO57, AF0) ++ ++#define GPIO63_GPIO MFP_CFG(GPIO63, AF0) ++#define GPIO64_GPIO MFP_CFG(GPIO64, AF0) ++#define GPIO65_GPIO MFP_CFG(GPIO65, AF0) ++#define GPIO66_GPIO MFP_CFG(GPIO66, AF0) ++#define GPIO67_GPIO MFP_CFG(GPIO67, AF0) ++#define GPIO68_GPIO MFP_CFG(GPIO68, AF0) ++#define GPIO69_GPIO MFP_CFG(GPIO69, AF0) ++#define GPIO70_GPIO MFP_CFG(GPIO70, AF0) ++#define GPIO71_GPIO MFP_CFG(GPIO71, AF0) ++#define GPIO72_GPIO MFP_CFG(GPIO72, AF0) ++#define GPIO73_GPIO MFP_CFG(GPIO73, AF0) ++#define GPIO74_GPIO MFP_CFG(GPIO74, AF0) ++#define GPIO75_GPIO MFP_CFG(GPIO75, AF0) ++#define GPIO76_GPIO MFP_CFG(GPIO76, AF0) ++#define GPIO77_GPIO MFP_CFG(GPIO77, AF0) ++#define GPIO78_GPIO MFP_CFG(GPIO78, AF0) ++#define GPIO79_GPIO MFP_CFG(GPIO79, AF0) ++#define GPIO80_GPIO MFP_CFG(GPIO80, AF0) ++#define GPIO81_GPIO MFP_CFG(GPIO81, AF0) ++#define GPIO82_GPIO MFP_CFG(GPIO82, AF0) ++#define GPIO83_GPIO MFP_CFG(GPIO83, AF0) ++#define GPIO84_GPIO MFP_CFG(GPIO84, AF0) ++#define GPIO85_GPIO MFP_CFG(GPIO85, AF0) ++#define GPIO86_GPIO MFP_CFG(GPIO86, AF0) ++#define GPIO87_GPIO MFP_CFG(GPIO87, AF0) ++#define GPIO88_GPIO MFP_CFG(GPIO88, AF0) ++#define GPIO89_GPIO MFP_CFG(GPIO89, AF0) ++#define GPIO90_GPIO MFP_CFG(GPIO90, AF0) ++#define GPIO91_GPIO MFP_CFG(GPIO91, AF0) ++#define GPIO92_GPIO MFP_CFG(GPIO92, AF0) ++#define GPIO93_GPIO MFP_CFG(GPIO93, AF0) ++#define GPIO94_GPIO MFP_CFG(GPIO94, AF0) ++#define GPIO95_GPIO MFP_CFG(GPIO95, AF0) ++#define GPIO96_GPIO MFP_CFG(GPIO96, AF0) ++#define GPIO97_GPIO MFP_CFG(GPIO97, AF0) ++#define GPIO98_GPIO MFP_CFG(GPIO98, AF0) ++#define GPIO99_GPIO MFP_CFG(GPIO99, AF0) ++#define GPIO100_GPIO MFP_CFG(GPIO100, AF0) ++#define GPIO101_GPIO MFP_CFG(GPIO101, AF0) ++#define GPIO102_GPIO MFP_CFG(GPIO102, AF0) ++#define GPIO103_GPIO MFP_CFG(GPIO103, AF0) ++#define GPIO104_GPIO MFP_CFG(GPIO104, AF0) ++#define GPIO105_GPIO MFP_CFG(GPIO105, AF0) ++#define GPIO106_GPIO MFP_CFG(GPIO106, AF0) ++#define GPIO107_GPIO MFP_CFG(GPIO107, AF0) ++#define GPIO108_GPIO MFP_CFG(GPIO108, AF0) ++#define GPIO109_GPIO MFP_CFG(GPIO109, AF0) ++#define GPIO110_GPIO MFP_CFG(GPIO110, AF0) ++#define GPIO111_GPIO MFP_CFG(GPIO111, AF0) ++#define GPIO112_GPIO MFP_CFG(GPIO112, AF0) ++#define GPIO113_GPIO MFP_CFG(GPIO113, AF0) ++#define GPIO114_GPIO MFP_CFG(GPIO114, AF0) ++#define GPIO115_GPIO MFP_CFG(GPIO115, AF0) ++#define GPIO116_GPIO MFP_CFG(GPIO116, AF0) ++#define GPIO117_GPIO MFP_CFG(GPIO117, AF0) ++#define GPIO118_GPIO MFP_CFG(GPIO118, AF0) ++#define GPIO119_GPIO MFP_CFG(GPIO119, AF0) ++#define GPIO120_GPIO MFP_CFG(GPIO120, AF0) ++#define GPIO121_GPIO MFP_CFG(GPIO121, AF0) ++#define GPIO122_GPIO MFP_CFG(GPIO122, AF0) ++#define GPIO123_GPIO MFP_CFG(GPIO123, AF0) ++#define GPIO124_GPIO MFP_CFG(GPIO124, AF0) ++#define GPIO125_GPIO MFP_CFG(GPIO125, AF0) ++#define GPIO126_GPIO MFP_CFG(GPIO126, AF0) ++#define GPIO127_GPIO MFP_CFG(GPIO127, AF0) ++ ++#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0) ++#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0) ++#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0) ++#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0) ++#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0) ++#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0) ++#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0) ++ ++/* ++ * each MFP pin will have a MFPR register, since the offset of the ++ * register varies between processors, the processor specific code ++ * should initialize the pin offsets by pxa3xx_mfp_init_addr() ++ * ++ * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map" ++ * structure, which represents a range of MFP pins from "start" to ++ * "end", with the offset begining at "offset", to define a single ++ * pin, let "end" = -1 ++ * ++ * use ++ * ++ * MFP_ADDR_X() to define a range of pins ++ * MFP_ADDR() to define a single pin ++ * MFP_ADDR_END to signal the end of pin offset definitions ++ */ ++struct pxa3xx_mfp_addr_map { ++ unsigned int start; ++ unsigned int end; ++ unsigned long offset; ++}; ++ ++#define MFP_ADDR_X(start, end, offset) \ ++ { MFP_PIN_##start, MFP_PIN_##end, offset } ++ ++#define MFP_ADDR(pin, offset) \ ++ { MFP_PIN_##pin, -1, offset } ++ ++#define MFP_ADDR_END { MFP_PIN_INVALID, 0 } ++ ++/* ++ * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access ++ * to the MFPR register ++ */ ++unsigned long pxa3xx_mfp_read(int mfp); ++void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val); ++ ++/* ++ * pxa3xx_mfp_config - configure the MFPR registers ++ * ++ * used by board specific initialization code ++ */ ++void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num); ++ ++/* ++ * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin ++ * index and MFPR register offset ++ * ++ * used by processor specific code ++ */ ++void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *); ++void __init pxa3xx_init_mfp(void); ++#endif /* __ASM_ARCH_MFP_PXA3XX_H */ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/mmc.h linux-2.6.25-rc4/include/asm-arm/arch/mmc.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/mmc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/mmc.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,23 @@ ++#ifndef ASMARM_ARCH_MMC_H ++#define ASMARM_ARCH_MMC_H ++ ++#include <linux/mmc/host.h> ++#include <linux/interrupt.h> ++ ++struct device; ++struct mmc_host; ++ ++struct pxamci_platform_data { ++ unsigned int ocr_mask; /* available voltages */ ++ unsigned long detect_delay; /* delay in jiffies before detecting cards after interrupt */ ++ int (*init)(struct device *, irq_handler_t , void *); ++ int (*get_ro)(struct device *); ++ void (*setpower)(struct device *, unsigned int); ++ void (*exit)(struct device *, void *); ++}; ++ ++extern void pxa_set_mci_info(struct pxamci_platform_data *info); ++extern void pxa3xx_set_mci2_info(struct pxamci_platform_data *info); ++extern void pxa3xx_set_mci3_info(struct pxamci_platform_data *info); ++ ++#endif +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/mtd-xip.h linux-2.6.25-rc4/include/asm-arm/arch/mtd-xip.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/mtd-xip.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/mtd-xip.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,37 @@ ++/* ++ * MTD primitives for XIP support. Architecture specific functions ++ * ++ * Do not include this file directly. It's included from linux/mtd/xip.h ++ * ++ * Author: Nicolas Pitre ++ * Created: Nov 2, 2004 ++ * Copyright: (C) 2004 MontaVista Software, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $ ++ */ ++ ++#ifndef __ARCH_PXA_MTD_XIP_H__ ++#define __ARCH_PXA_MTD_XIP_H__ ++ ++#include <asm/arch/pxa-regs.h> ++ ++#define xip_irqpending() (ICIP & ICMR) ++ ++/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */ ++#define xip_currtime() (OSCR) ++#define xip_elapsed_since(x) (signed)((OSCR - (x)) / 4) ++ ++/* ++ * xip_cpu_idle() is used when waiting for a delay equal or larger than ++ * the system timer tick period. This should put the CPU into idle mode ++ * to save power and to be woken up only when some interrupts are pending. ++ * As above, this should not rely upon standard kernel code. ++ */ ++ ++#define xip_cpu_idle() asm volatile ("mcr p14, 0, %0, c7, c0, 0" :: "r" (1)) ++ ++#endif /* __ARCH_PXA_MTD_XIP_H__ */ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/ohci.h linux-2.6.25-rc4/include/asm-arm/arch/ohci.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/ohci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/ohci.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,20 @@ ++#ifndef ASMARM_ARCH_OHCI_H ++#define ASMARM_ARCH_OHCI_H ++ ++struct device; ++ ++struct pxaohci_platform_data { ++ int (*init)(struct device *); ++ void (*exit)(struct device *); ++ ++ int port_mode; ++#define PMM_NPS_MODE 1 ++#define PMM_GLOBAL_MODE 2 ++#define PMM_PERPORT_MODE 3 ++ ++ int power_budget; ++}; ++ ++extern void pxa_set_ohci_info(struct pxaohci_platform_data *info); ++ ++#endif +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/pcm027.h linux-2.6.25-rc4/include/asm-arm/arch/pcm027.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/pcm027.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/pcm027.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,75 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/pcm027.h ++ * ++ * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de> ++ * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/* ++ * Definitions of CPU card resources only ++ */ ++ ++/* I2C RTC */ ++#define PCM027_RTC_IRQ_GPIO 0 ++#define PCM027_RTC_IRQ IRQ_GPIO(PCM027_RTC_IRQ_GPIO) ++#define PCM027_RTC_IRQ_EDGE IRQ_TYPE_EDGE_FALLING ++#define ADR_PCM027_RTC 0x51 /* I2C address */ ++ ++/* I2C EEPROM */ ++#define ADR_PCM027_EEPROM 0x54 /* I2C address */ ++ ++/* Ethernet chip (SMSC91C111) */ ++#define PCM027_ETH_IRQ_GPIO 52 ++#define PCM027_ETH_IRQ IRQ_GPIO(PCM027_ETH_IRQ_GPIO) ++#define PCM027_ETH_IRQ_EDGE IRQ_TYPE_EDGE_RISING ++#define PCM027_ETH_PHYS PXA_CS5_PHYS ++#define PCM027_ETH_SIZE (1*1024*1024) ++ ++/* CAN controller SJA1000 (unsupported yet) */ ++#define PCM027_CAN_IRQ_GPIO 114 ++#define PCM027_CAN_IRQ IRQ_GPIO(PCM027_CAN_IRQ_GPIO) ++#define PCM027_CAN_IRQ_EDGE IRQ_TYPE_EDGE_FALLING ++#define PCM027_CAN_PHYS 0x22000000 ++#define PCM027_CAN_SIZE 0x100 ++ ++/* SPI GPIO expander (unsupported yet) */ ++#define PCM027_EGPIO_IRQ_GPIO 27 ++#define PCM027_EGPIO_IRQ IRQ_GPIO(PCM027_EGPIO_IRQ_GPIO) ++#define PCM027_EGPIO_IRQ_EDGE IRQ_TYPE_EDGE_FALLING ++#define PCM027_EGPIO_CS 24 ++/* ++ * TODO: Switch this pin from dedicated usage to GPIO if ++ * more than the MAX7301 device is connected to this SPI bus ++ */ ++#define PCM027_EGPIO_CS_MODE GPIO24_SFRM_MD ++ ++/* Flash memory */ ++#define PCM027_FLASH_PHYS 0x00000000 ++#define PCM027_FLASH_SIZE 0x02000000 ++ ++/* onboard LEDs connected to GPIO */ ++#define PCM027_LED_CPU 90 ++#define PCM027_LED_HEARD_BEAT 91 ++ ++/* ++ * This CPU module needs a baseboard to work. After basic initializing ++ * its own devices, it calls baseboard's init function. ++ * TODO: Add your own basebaord init function and call it from ++ * inside pcm027_init(). This example here is for the developmen board. ++ * Refer pcm990-baseboard.c ++ */ ++extern void pcm990_baseboard_init(void); +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/pcm990_baseboard.h linux-2.6.25-rc4/include/asm-arm/arch/pcm990_baseboard.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/pcm990_baseboard.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/pcm990_baseboard.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,275 @@ ++/* ++ * include/asm-arm/arch-pxa/pcm990_baseboard.h ++ * ++ * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de> ++ * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include <asm/arch/pcm027.h> ++ ++/* ++ * definitions relevant only when the PCM-990 ++ * development base board is in use ++ */ ++ ++/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */ ++#define PCM990_CTRL_INT_IRQ_GPIO 9 ++#define PCM990_CTRL_INT_IRQ IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO) ++#define PCM990_CTRL_INT_IRQ_EDGE IRQT_RISING ++#define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */ ++#define PCM990_CTRL_BASE 0xea000000 ++#define PCM990_CTRL_SIZE (1*1024*1024) ++ ++#define PCM990_CTRL_PWR_IRQ_GPIO 14 ++#define PCM990_CTRL_PWR_IRQ IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO) ++#define PCM990_CTRL_PWR_IRQ_EDGE IRQT_RISING ++ ++/* visible CPLD (U7) registers */ ++#define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */ ++#define PCM990_CTRL_SYSRES 0x0001 /* System RESET REGISTER */ ++#define PCM990_CTRL_RESOUT 0x0002 /* RESETOUT Enable REGISTER */ ++#define PCM990_CTRL_RESGPIO 0x0004 /* RESETGPIO Enable REGISTER */ ++ ++#define PCM990_CTRL_REG1 0x0002 /* Power REGISTER */ ++#define PCM990_CTRL_5VOFF 0x0001 /* Disable 5V Regulators */ ++#define PCM990_CTRL_CANPWR 0x0004 /* Enable CANPWR ADUM */ ++#define PCM990_CTRL_PM_5V 0x0008 /* Read 5V OK */ ++ ++#define PCM990_CTRL_REG2 0x0004 /* LED REGISTER */ ++#define PCM990_CTRL_LEDPWR 0x0001 /* POWER LED enable */ ++#define PCM990_CTRL_LEDBAS 0x0002 /* BASIS LED enable */ ++#define PCM990_CTRL_LEDUSR 0x0004 /* USER LED enable */ ++ ++#define PCM990_CTRL_REG3 0x0006 /* LCD CTRL REGISTER 3 */ ++#define PCM990_CTRL_LCDPWR 0x0001 /* RW LCD Power on */ ++#define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */ ++#define PCM990_CTRL_LCDPOS1 0x0004 /* RW POS 1 */ ++#define PCM990_CTRL_LCDPOS2 0x0008 /* RW POS 2 */ ++ ++#define PCM990_CTRL_REG4 0x0008 /* MMC1 CTRL REGISTER 4 */ ++#define PCM990_CTRL_MMC1PWR 0x0001 /* RW MMC1 Power on */ ++ ++#define PCM990_CTRL_REG5 0x000A /* MMC2 CTRL REGISTER 5 */ ++#define PCM990_CTRL_MMC2PWR 0x0001 /* RW MMC2 Power on */ ++#define PCM990_CTRL_MMC2LED 0x0002 /* RW MMC2 LED */ ++#define PCM990_CTRL_MMC2DE 0x0004 /* R MMC2 Card detect */ ++#define PCM990_CTRL_MMC2WP 0x0008 /* R MMC2 Card write protect */ ++ ++#define PCM990_CTRL_REG6 0x000C /* Interrupt Clear REGISTER */ ++#define PCM990_CTRL_INTC0 0x0001 /* Clear Reg BT Detect */ ++#define PCM990_CTRL_INTC1 0x0002 /* Clear Reg FR RI */ ++#define PCM990_CTRL_INTC2 0x0004 /* Clear Reg MMC1 Detect */ ++#define PCM990_CTRL_INTC3 0x0008 /* Clear Reg PM_5V off */ ++ ++#define PCM990_CTRL_REG7 0x000E /* Interrupt Enable REGISTER */ ++#define PCM990_CTRL_ENAINT0 0x0001 /* Enable Int BT Detect */ ++#define PCM990_CTRL_ENAINT1 0x0002 /* Enable Int FR RI */ ++#define PCM990_CTRL_ENAINT2 0x0004 /* Enable Int MMC1 Detect */ ++#define PCM990_CTRL_ENAINT3 0x0008 /* Enable Int PM_5V off */ ++ ++#define PCM990_CTRL_REG8 0x0014 /* Uart REGISTER */ ++#define PCM990_CTRL_FFSD 0x0001 /* BT Uart Enable */ ++#define PCM990_CTRL_BTSD 0x0002 /* FF Uart Enable */ ++#define PCM990_CTRL_FFRI 0x0004 /* FF Uart RI detect */ ++#define PCM990_CTRL_BTRX 0x0008 /* BT Uart Rx detect */ ++ ++#define PCM990_CTRL_REG9 0x0010 /* AC97 Flash REGISTER */ ++#define PCM990_CTRL_FLWP 0x0001 /* pC Flash Write Protect */ ++#define PCM990_CTRL_FLDIS 0x0002 /* pC Flash Disable */ ++#define PCM990_CTRL_AC97ENA 0x0004 /* Enable AC97 Expansion */ ++ ++#define PCM990_CTRL_REG10 0x0012 /* GPS-REGISTER */ ++#define PCM990_CTRL_GPSPWR 0x0004 /* GPS-Modul Power on */ ++#define PCM990_CTRL_GPSENA 0x0008 /* GPS-Modul Enable */ ++ ++#define PCM990_CTRL_REG11 0x0014 /* Accu REGISTER */ ++#define PCM990_CTRL_ACENA 0x0001 /* Charge Enable */ ++#define PCM990_CTRL_ACSEL 0x0002 /* Charge Akku -> DC Enable */ ++#define PCM990_CTRL_ACPRES 0x0004 /* DC Present */ ++#define PCM990_CTRL_ACALARM 0x0008 /* Error Akku */ ++ ++#define PCM990_CTRL_P2V(x) ((x) - PCM990_CTRL_PHYS + PCM990_CTRL_BASE) ++#define PCM990_CTRL_V2P(x) ((x) - PCM990_CTRL_BASE + PCM990_CTRL_PHYS) ++ ++#ifndef __ASSEMBLY__ ++# define __PCM990_CTRL_REG(x) \ ++ (*((volatile unsigned char *)PCM990_CTRL_P2V(x))) ++#else ++# define __PCM990_CTRL_REG(x) PCM990_CTRL_P2V(x) ++#endif ++ ++#define PCM990_INTMSKENA __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7) ++#define PCM990_INTSETCLR __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6) ++#define PCM990_CTRL0 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG0) ++#define PCM990_CTRL1 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG1) ++#define PCM990_CTRL2 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG2) ++#define PCM990_CTRL3 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3) ++#define PCM990_CTRL4 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG4) ++#define PCM990_CTRL5 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5) ++#define PCM990_CTRL6 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6) ++#define PCM990_CTRL7 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7) ++#define PCM990_CTRL8 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG8) ++#define PCM990_CTRL9 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG9) ++#define PCM990_CTRL10 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG10) ++#define PCM990_CTRL11 __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG11) ++ ++ ++/* ++ * IDE ++ */ ++#define PCM990_IDE_IRQ_GPIO 13 ++#define PCM990_IDE_IRQ IRQ_GPIO(PCM990_IDE_IRQ_GPIO) ++#define PCM990_IDE_IRQ_EDGE IRQT_RISING ++#define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */ ++#define PCM990_IDE_PLD_BASE 0xee000000 ++#define PCM990_IDE_PLD_SIZE (1*1024*1024) ++ ++/* visible CPLD (U6) registers */ ++#define PCM990_IDE_PLD_REG0 0x1000 /* OFFSET IDE REGISTER 0 */ ++#define PCM990_IDE_PM5V 0x0004 /* R System VCC_5V */ ++#define PCM990_IDE_STBY 0x0008 /* R System StandBy */ ++ ++#define PCM990_IDE_PLD_REG1 0x1002 /* OFFSET IDE REGISTER 1 */ ++#define PCM990_IDE_IDEMODE 0x0001 /* R TrueIDE Mode */ ++#define PCM990_IDE_DMAENA 0x0004 /* RW DMA Enable */ ++#define PCM990_IDE_DMA1_0 0x0008 /* RW 1=DREQ1 0=DREQ0 */ ++ ++#define PCM990_IDE_PLD_REG2 0x1004 /* OFFSET IDE REGISTER 2 */ ++#define PCM990_IDE_RESENA 0x0001 /* RW IDE Reset Bit enable */ ++#define PCM990_IDE_RES 0x0002 /* RW IDE Reset Bit */ ++#define PCM990_IDE_RDY 0x0008 /* RDY */ ++ ++#define PCM990_IDE_PLD_REG3 0x1006 /* OFFSET IDE REGISTER 3 */ ++#define PCM990_IDE_IDEOE 0x0001 /* RW Latch on Databus */ ++#define PCM990_IDE_IDEON 0x0002 /* RW Latch on Control Address */ ++#define PCM990_IDE_IDEIN 0x0004 /* RW Latch on Interrupt usw. */ ++ ++#define PCM990_IDE_PLD_REG4 0x1008 /* OFFSET IDE REGISTER 4 */ ++#define PCM990_IDE_PWRENA 0x0001 /* RW IDE Power enable */ ++#define PCM990_IDE_5V 0x0002 /* R IDE Power 5V */ ++#define PCM990_IDE_PWG 0x0008 /* R IDE Power is on */ ++ ++#define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE) ++#define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS) ++ ++#ifndef __ASSEMBLY__ ++# define __PCM990_IDE_PLD_REG(x) \ ++ (*((volatile unsigned char *)PCM990_IDE_PLD_P2V(x))) ++#else ++# define __PCM990_IDE_PLD_REG(x) PCM990_IDE_PLD_P2V(x) ++#endif ++ ++#define PCM990_IDE0 \ ++ __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG0) ++#define PCM990_IDE1 \ ++ __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG1) ++#define PCM990_IDE2 \ ++ __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG2) ++#define PCM990_IDE3 \ ++ __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG3) ++#define PCM990_IDE4 \ ++ __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG4) ++ ++/* ++ * Compact Flash ++ */ ++#define PCM990_CF_IRQ_GPIO 11 ++#define PCM990_CF_IRQ IRQ_GPIO(PCM990_CF_IRQ_GPIO) ++#define PCM990_CF_IRQ_EDGE IRQT_RISING ++ ++#define PCM990_CF_CD_GPIO 12 ++#define PCM990_CF_CD IRQ_GPIO(PCM990_CF_CD_GPIO) ++#define PCM990_CF_CD_EDGE IRQT_RISING ++ ++#define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */ ++#define PCM990_CF_PLD_BASE 0xef000000 ++#define PCM990_CF_PLD_SIZE (1*1024*1024) ++#define PCM990_CF_PLD_P2V(x) ((x) - PCM990_CF_PLD_PHYS + PCM990_CF_PLD_BASE) ++#define PCM990_CF_PLD_V2P(x) ((x) - PCM990_CF_PLD_BASE + PCM990_CF_PLD_PHYS) ++ ++/* visible CPLD (U6) registers */ ++#define PCM990_CF_PLD_REG0 0x1000 /* OFFSET CF REGISTER 0 */ ++#define PCM990_CF_REG0_LED 0x0001 /* RW LED on */ ++#define PCM990_CF_REG0_BLK 0x0002 /* RW LED flash when access */ ++#define PCM990_CF_REG0_PM5V 0x0004 /* R System VCC_5V enable */ ++#define PCM990_CF_REG0_STBY 0x0008 /* R System StandBy */ ++ ++#define PCM990_CF_PLD_REG1 0x1002 /* OFFSET CF REGISTER 1 */ ++#define PCM990_CF_REG1_IDEMODE 0x0001 /* RW CF card run as TrueIDE */ ++#define PCM990_CF_REG1_CF0 0x0002 /* RW CF card at ADDR 0x28000000 */ ++ ++#define PCM990_CF_PLD_REG2 0x1004 /* OFFSET CF REGISTER 2 */ ++#define PCM990_CF_REG2_RES 0x0002 /* RW CF RESET BIT */ ++#define PCM990_CF_REG2_RDYENA 0x0004 /* RW Enable CF_RDY */ ++#define PCM990_CF_REG2_RDY 0x0008 /* R CF_RDY auf PWAIT */ ++ ++#define PCM990_CF_PLD_REG3 0x1006 /* OFFSET CF REGISTER 3 */ ++#define PCM990_CF_REG3_CFOE 0x0001 /* RW Latch on Databus */ ++#define PCM990_CF_REG3_CFON 0x0002 /* RW Latch on Control Address */ ++#define PCM990_CF_REG3_CFIN 0x0004 /* RW Latch on Interrupt usw. */ ++#define PCM990_CF_REG3_CFCD 0x0008 /* RW Latch on CD1/2 VS1/2 usw */ ++ ++#define PCM990_CF_PLD_REG4 0x1008 /* OFFSET CF REGISTER 4 */ ++#define PCM990_CF_REG4_PWRENA 0x0001 /* RW CF Power on (CD1/2 = "00") */ ++#define PCM990_CF_REG4_5_3V 0x0002 /* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */ ++#define PCM990_CF_REG4_3B 0x0004 /* RW 3.0V Backup from VCC (5_3V=0) */ ++#define PCM990_CF_REG4_PWG 0x0008 /* R CF-Power is on */ ++ ++#define PCM990_CF_PLD_REG5 0x100A /* OFFSET CF REGISTER 5 */ ++#define PCM990_CF_REG5_BVD1 0x0001 /* R CF /BVD1 */ ++#define PCM990_CF_REG5_BVD2 0x0002 /* R CF /BVD2 */ ++#define PCM990_CF_REG5_VS1 0x0004 /* R CF /VS1 */ ++#define PCM990_CF_REG5_VS2 0x0008 /* R CF /VS2 */ ++ ++#define PCM990_CF_PLD_REG6 0x100C /* OFFSET CF REGISTER 6 */ ++#define PCM990_CF_REG6_CD1 0x0001 /* R CF Card_Detect1 */ ++#define PCM990_CF_REG6_CD2 0x0002 /* R CF Card_Detect2 */ ++ ++#ifndef __ASSEMBLY__ ++# define __PCM990_CF_PLD_REG(x) \ ++ (*((volatile unsigned char *)PCM990_CF_PLD_P2V(x))) ++#else ++# define __PCM990_CF_PLD_REG(x) PCM990_CF_PLD_P2V(x) ++#endif ++ ++#define PCM990_CF0 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG0) ++#define PCM990_CF1 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG1) ++#define PCM990_CF2 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG2) ++#define PCM990_CF3 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG3) ++#define PCM990_CF4 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG4) ++#define PCM990_CF5 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG5) ++#define PCM990_CF6 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG6) ++ ++/* ++ * Wolfson AC97 Touch ++ */ ++#define PCM990_AC97_IRQ_GPIO 10 ++#define PCM990_AC97_IRQ IRQ_GPIO(PCM990_AC97_IRQ_GPIO) ++#define PCM990_AC97_IRQ_EDGE IRQT_RISING ++ ++/* ++ * MMC phyCORE ++ */ ++#define PCM990_MMC0_IRQ_GPIO 9 ++#define PCM990_MMC0_IRQ IRQ_GPIO(PCM990_MMC0_IRQ_GPIO) ++#define PCM990_MMC0_IRQ_EDGE IRQT_FALLING ++ ++/* ++ * USB phyCore ++ */ ++#define PCM990_USB_OVERCURRENT (88 | GPIO_ALT_FN_1_IN) ++#define PCM990_USB_PWR_EN (89 | GPIO_ALT_FN_2_OUT) +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/pm.h linux-2.6.25-rc4/include/asm-arm/arch/pm.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/pm.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/pm.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,27 @@ ++/* ++ * Copyright (c) 2005 Richard Purdie ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include <linux/suspend.h> ++ ++struct pxa_cpu_pm_fns { ++ int save_size; ++ void (*save)(unsigned long *); ++ void (*restore)(unsigned long *); ++ int (*valid)(suspend_state_t state); ++ void (*enter)(suspend_state_t state); ++}; ++ ++extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns; ++ ++/* sleep.S */ ++extern void pxa25x_cpu_suspend(unsigned int); ++extern void pxa27x_cpu_suspend(unsigned int); ++extern void pxa_cpu_resume(void); ++ ++extern int pxa_pm_enter(suspend_state_t state); +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/poodle.h linux-2.6.25-rc4/include/asm-arm/arch/poodle.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/poodle.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/poodle.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,75 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/poodle.h ++ * ++ * May be copied or modified under the terms of the GNU General Public ++ * License. See linux/COPYING for more information. ++ * ++ * Based on: ++ * linux/include/asm-arm/arch-sa1100/collie.h ++ * ++ * ChangeLog: ++ * 04-06-2001 Lineo Japan, Inc. ++ * 04-16-2001 SHARP Corporation ++ * Update to 2.6 John Lenz ++ */ ++#ifndef __ASM_ARCH_POODLE_H ++#define __ASM_ARCH_POODLE_H 1 ++ ++/* ++ * GPIOs ++ */ ++/* PXA GPIOs */ ++#define POODLE_GPIO_ON_KEY (0) ++#define POODLE_GPIO_AC_IN (1) ++#define POODLE_GPIO_CO 16 ++#define POODLE_GPIO_TP_INT (5) ++#define POODLE_GPIO_WAKEUP (11) /* change battery */ ++#define POODLE_GPIO_GA_INT (10) ++#define POODLE_GPIO_IR_ON (22) ++#define POODLE_GPIO_HP_IN (4) ++#define POODLE_GPIO_CF_IRQ (17) ++#define POODLE_GPIO_CF_CD (14) ++#define POODLE_GPIO_CF_STSCHG (14) ++#define POODLE_GPIO_SD_PWR (33) ++#define POODLE_GPIO_SD_PWR1 (3) ++#define POODLE_GPIO_nSD_CLK (6) ++#define POODLE_GPIO_nSD_WP (7) ++#define POODLE_GPIO_nSD_INT (8) ++#define POODLE_GPIO_nSD_DETECT (9) ++#define POODLE_GPIO_MAIN_BAT_LOW (13) ++#define POODLE_GPIO_BAT_COVER (13) ++#define POODLE_GPIO_USB_PULLUP (20) ++#define POODLE_GPIO_ADC_TEMP_ON (21) ++#define POODLE_GPIO_BYPASS_ON (36) ++#define POODLE_GPIO_CHRG_ON (38) ++#define POODLE_GPIO_CHRG_FULL (16) ++#define POODLE_GPIO_DISCHARGE_ON (42) /* Enable battery discharge */ ++ ++/* PXA GPIOs */ ++#define POODLE_IRQ_GPIO_ON_KEY IRQ_GPIO(0) ++#define POODLE_IRQ_GPIO_AC_IN IRQ_GPIO(1) ++#define POODLE_IRQ_GPIO_HP_IN IRQ_GPIO(4) ++#define POODLE_IRQ_GPIO_CO IRQ_GPIO(16) ++#define POODLE_IRQ_GPIO_TP_INT IRQ_GPIO(5) ++#define POODLE_IRQ_GPIO_WAKEUP IRQ_GPIO(11) ++#define POODLE_IRQ_GPIO_GA_INT IRQ_GPIO(10) ++#define POODLE_IRQ_GPIO_CF_IRQ IRQ_GPIO(17) ++#define POODLE_IRQ_GPIO_CF_CD IRQ_GPIO(14) ++#define POODLE_IRQ_GPIO_nSD_INT IRQ_GPIO(8) ++#define POODLE_IRQ_GPIO_nSD_DETECT IRQ_GPIO(9) ++#define POODLE_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(13) ++ ++/* SCOOP GPIOs */ ++#define POODLE_SCOOP_CHARGE_ON SCOOP_GPCR_PA11 ++#define POODLE_SCOOP_CP401 SCOOP_GPCR_PA13 ++#define POODLE_SCOOP_VPEN SCOOP_GPCR_PA18 ++#define POODLE_SCOOP_L_PCLK SCOOP_GPCR_PA20 ++#define POODLE_SCOOP_L_LCLK SCOOP_GPCR_PA21 ++#define POODLE_SCOOP_HS_OUT SCOOP_GPCR_PA22 ++ ++#define POODLE_SCOOP_IO_DIR ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT ) ++#define POODLE_SCOOP_IO_OUT ( 0 ) ++ ++extern struct platform_device poodle_locomo_device; ++ ++#endif /* __ASM_ARCH_POODLE_H */ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/pxa27x_keypad.h linux-2.6.25-rc4/include/asm-arm/arch/pxa27x_keypad.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/pxa27x_keypad.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/pxa27x_keypad.h 2008-03-08 16:22:35.000000000 +0100 +@@ -0,0 +1,58 @@ ++#ifndef __ASM_ARCH_PXA27x_KEYPAD_H ++#define __ASM_ARCH_PXA27x_KEYPAD_H ++ ++#include <linux/input.h> ++ ++#define MAX_MATRIX_KEY_ROWS (8) ++#define MAX_MATRIX_KEY_COLS (8) ++ ++/* pxa3xx keypad platform specific parameters ++ * ++ * NOTE: ++ * 1. direct_key_num indicates the number of keys in the direct keypad ++ * _plus_ the number of rotary-encoder sensor inputs, this can be ++ * left as 0 if only rotary encoders are enabled, the driver will ++ * automatically calculate this ++ * ++ * 2. direct_key_map is the key code map for the direct keys, if rotary ++ * encoder(s) are enabled, direct key 0/1(2/3) will be ignored ++ * ++ * 3. rotary can be either interpreted as a relative input event (e.g. ++ * REL_WHEEL/REL_HWHEEL) or specific keys (e.g. UP/DOWN/LEFT/RIGHT) ++ * ++ * 4. matrix key and direct key will use the same debounce_interval by ++ * default, which should be sufficient in most cases ++ */ ++struct pxa27x_keypad_platform_data { ++ ++ /* code map for the matrix keys */ ++ unsigned int matrix_key_rows; ++ unsigned int matrix_key_cols; ++ unsigned int *matrix_key_map; ++ int matrix_key_map_size; ++ ++ /* direct keys */ ++ int direct_key_num; ++ unsigned int direct_key_map[8]; ++ ++ /* rotary encoders 0 */ ++ int enable_rotary0; ++ int rotary0_rel_code; ++ int rotary0_up_key; ++ int rotary0_down_key; ++ ++ /* rotary encoders 1 */ ++ int enable_rotary1; ++ int rotary1_rel_code; ++ int rotary1_up_key; ++ int rotary1_down_key; ++ ++ /* key debounce interval */ ++ unsigned int debounce_interval; ++}; ++ ++#define KEY(row, col, val) (((row) << 28) | ((col) << 24) | (val)) ++ ++extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info); ++ ++#endif /* __ASM_ARCH_PXA27x_KEYPAD_H */ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/pxa2xx-regs.h linux-2.6.25-rc4/include/asm-arm/arch/pxa2xx-regs.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/pxa2xx-regs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/pxa2xx-regs.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,84 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/pxa2xx-regs.h ++ * ++ * Taken from pxa-regs.h by Russell King ++ * ++ * Author: Nicolas Pitre ++ * Copyright: MontaVista Software Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __PXA2XX_REGS_H ++#define __PXA2XX_REGS_H ++ ++/* ++ * Memory controller ++ */ ++ ++#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */ ++#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ ++#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */ ++#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */ ++#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */ ++#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ ++#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ ++#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */ ++#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */ ++#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */ ++#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */ ++#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ ++#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */ ++#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */ ++#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */ ++#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ ++#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ ++ ++/* ++ * More handy macros for PCMCIA ++ * ++ * Arg is socket number ++ */ ++#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */ ++#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */ ++#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */ ++ ++/* MECR register defines */ ++#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ ++#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ ++ ++#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ ++#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ ++#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ ++#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ ++#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ ++#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ ++#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ ++#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ ++#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ ++#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ ++#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ ++#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ ++#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ ++#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ ++ ++ ++#ifdef CONFIG_PXA27x ++ ++#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ ++ ++#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ ++#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ ++#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ ++#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ ++#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ ++#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ ++#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ ++#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ ++#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ ++ ++#endif ++ ++#endif +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/pxa2xx_spi.h linux-2.6.25-rc4/include/asm-arm/arch/pxa2xx_spi.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/pxa2xx_spi.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/pxa2xx_spi.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,44 @@ ++/* ++ * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#ifndef PXA2XX_SPI_H_ ++#define PXA2XX_SPI_H_ ++ ++#define PXA2XX_CS_ASSERT (0x01) ++#define PXA2XX_CS_DEASSERT (0x02) ++ ++/* device.platform_data for SSP controller devices */ ++struct pxa2xx_spi_master { ++ u32 clock_enable; ++ u16 num_chipselect; ++ u8 enable_dma; ++}; ++ ++/* spi_board_info.controller_data for SPI slave devices, ++ * copied to spi_device.platform_data ... mostly for dma tuning ++ */ ++struct pxa2xx_spi_chip { ++ u8 tx_threshold; ++ u8 rx_threshold; ++ u8 dma_burst_size; ++ u32 timeout; ++ u8 enable_loopback; ++ void (*cs_control)(u32 command); ++}; ++ ++#endif /*PXA2XX_SPI_H_*/ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/pxa3xx-regs.h linux-2.6.25-rc4/include/asm-arm/arch/pxa3xx-regs.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/pxa3xx-regs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/pxa3xx-regs.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,174 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/pxa3xx-regs.h ++ * ++ * PXA3xx specific register definitions ++ * ++ * Copyright (C) 2007 Marvell International Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __ASM_ARCH_PXA3XX_REGS_H ++#define __ASM_ARCH_PXA3XX_REGS_H ++/* ++ * Service Power Management Unit (MPMU) ++ */ ++#define PMCR __REG(0x40F50000) /* Power Manager Control Register */ ++#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */ ++#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */ ++#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */ ++#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */ ++#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */ ++#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */ ++#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */ ++#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */ ++#define PCMD(x) __REG(0x40F50110 + ((x) << 2)) ++ ++/* ++ * Slave Power Managment Unit ++ */ ++#define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */ ++#define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */ ++#define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */ ++#define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */ ++#define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */ ++#define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */ ++#define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */ ++#define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */ ++#define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */ ++#define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */ ++#define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */ ++#define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */ ++#define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */ ++#define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */ ++ ++/* ++ * Application Subsystem Configuration bits. ++ */ ++#define ASCR_RDH (1 << 31) ++#define ASCR_D1S (1 << 2) ++#define ASCR_D2S (1 << 1) ++#define ASCR_D3S (1 << 0) ++ ++/* ++ * Application Reset Status bits. ++ */ ++#define ARSR_GPR (1 << 3) ++#define ARSR_LPMR (1 << 2) ++#define ARSR_WDT (1 << 1) ++#define ARSR_HWR (1 << 0) ++ ++/* ++ * Application Subsystem Wake-Up bits. ++ */ ++#define ADXER_WRTC (1 << 31) /* RTC */ ++#define ADXER_WOST (1 << 30) /* OS Timer */ ++#define ADXER_WTSI (1 << 29) /* Touchscreen */ ++#define ADXER_WUSBH (1 << 28) /* USB host */ ++#define ADXER_WUSB2 (1 << 26) /* USB client 2.0 */ ++#define ADXER_WMSL0 (1 << 24) /* MSL port 0*/ ++#define ADXER_WDMUX3 (1 << 23) /* USB EDMUX3 */ ++#define ADXER_WDMUX2 (1 << 22) /* USB EDMUX2 */ ++#define ADXER_WKP (1 << 21) /* Keypad */ ++#define ADXER_WUSIM1 (1 << 20) /* USIM Port 1 */ ++#define ADXER_WUSIM0 (1 << 19) /* USIM Port 0 */ ++#define ADXER_WOTG (1 << 16) /* USBOTG input */ ++#define ADXER_MFP_WFLASH (1 << 15) /* MFP: Data flash busy */ ++#define ADXER_MFP_GEN12 (1 << 14) /* MFP: MMC3/GPIO/OST inputs */ ++#define ADXER_MFP_WMMC2 (1 << 13) /* MFP: MMC2 */ ++#define ADXER_MFP_WMMC1 (1 << 12) /* MFP: MMC1 */ ++#define ADXER_MFP_WI2C (1 << 11) /* MFP: I2C */ ++#define ADXER_MFP_WSSP4 (1 << 10) /* MFP: SSP4 */ ++#define ADXER_MFP_WSSP3 (1 << 9) /* MFP: SSP3 */ ++#define ADXER_MFP_WMAXTRIX (1 << 8) /* MFP: matrix keypad */ ++#define ADXER_MFP_WUART3 (1 << 7) /* MFP: UART3 */ ++#define ADXER_MFP_WUART2 (1 << 6) /* MFP: UART2 */ ++#define ADXER_MFP_WUART1 (1 << 5) /* MFP: UART1 */ ++#define ADXER_MFP_WSSP2 (1 << 4) /* MFP: SSP2 */ ++#define ADXER_MFP_WSSP1 (1 << 3) /* MFP: SSP1 */ ++#define ADXER_MFP_WAC97 (1 << 2) /* MFP: AC97 */ ++#define ADXER_WEXTWAKE1 (1 << 1) /* External Wake 1 */ ++#define ADXER_WEXTWAKE0 (1 << 0) /* External Wake 0 */ ++ ++/* ++ * AD3R/AD2R/AD1R bits. R2-R5 are only defined for PXA320. ++ */ ++#define ADXR_L2 (1 << 8) ++#define ADXR_R5 (1 << 5) ++#define ADXR_R4 (1 << 4) ++#define ADXR_R3 (1 << 3) ++#define ADXR_R2 (1 << 2) ++#define ADXR_R1 (1 << 1) ++#define ADXR_R0 (1 << 0) ++ ++/* ++ * Values for PWRMODE CP15 register ++ */ ++#define PXA3xx_PM_S3D4C4 0x07 /* aka deep sleep */ ++#define PXA3xx_PM_S2D3C4 0x06 /* aka sleep */ ++#define PXA3xx_PM_S0D2C2 0x03 /* aka standby */ ++#define PXA3xx_PM_S0D1C2 0x02 /* aka LCD refresh */ ++#define PXA3xx_PM_S0D0C1 0x01 ++ ++/* ++ * Application Subsystem Clock ++ */ ++#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ ++#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */ ++#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ ++#define CKENA __REG(0x4134000C) /* A Clock Enable Register */ ++#define CKENB __REG(0x41340010) /* B Clock Enable Register */ ++#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ ++ ++/* ++ * Clock Enable Bit ++ */ ++#define CKEN_LCD 1 /* < LCD Clock Enable */ ++#define CKEN_USBH 2 /* < USB host clock enable */ ++#define CKEN_CAMERA 3 /* < Camera interface clock enable */ ++#define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */ ++#define CKEN_USB2 6 /* < USB 2.0 client clock enable. */ ++#define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */ ++#define CKEN_SMC 9 /* < Static Memory Controller clock enable */ ++#define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */ ++#define CKEN_BOOT 11 /* < Boot rom clock enable */ ++#define CKEN_MMC1 12 /* < MMC1 Clock enable */ ++#define CKEN_MMC2 13 /* < MMC2 clock enable */ ++#define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */ ++#define CKEN_CIR 15 /* < Consumer IR Clock Enable */ ++#define CKEN_USIM0 17 /* < USIM[0] Clock Enable */ ++#define CKEN_USIM1 18 /* < USIM[1] Clock Enable */ ++#define CKEN_TPM 19 /* < TPM clock enable */ ++#define CKEN_UDC 20 /* < UDC clock enable */ ++#define CKEN_BTUART 21 /* < BTUART clock enable */ ++#define CKEN_FFUART 22 /* < FFUART clock enable */ ++#define CKEN_STUART 23 /* < STUART clock enable */ ++#define CKEN_AC97 24 /* < AC97 clock enable */ ++#define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */ ++#define CKEN_SSP1 26 /* < SSP1 clock enable */ ++#define CKEN_SSP2 27 /* < SSP2 clock enable */ ++#define CKEN_SSP3 28 /* < SSP3 clock enable */ ++#define CKEN_SSP4 29 /* < SSP4 clock enable */ ++#define CKEN_MSL0 30 /* < MSL0 clock enable */ ++#define CKEN_PWM0 32 /* < PWM[0] clock enable */ ++#define CKEN_PWM1 33 /* < PWM[1] clock enable */ ++#define CKEN_I2C 36 /* < I2C clock enable */ ++#define CKEN_INTC 38 /* < Interrupt controller clock enable */ ++#define CKEN_GPIO 39 /* < GPIO clock enable */ ++#define CKEN_1WIRE 40 /* < 1-wire clock enable */ ++#define CKEN_HSIO2 41 /* < HSIO2 clock enable */ ++#define CKEN_MINI_IM 48 /* < Mini-IM */ ++#define CKEN_MINI_LCD 49 /* < Mini LCD */ ++ ++#if defined(CONFIG_CPU_PXA310) ++#define CKEN_MMC3 5 /* < MMC3 Clock Enable */ ++#define CKEN_MVED 43 /* < MVED clock enable */ ++#endif ++ ++/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */ ++#define PXA300_CKEN_GRAPHICS 42 /* Graphics controller clock enable */ ++#define PXA320_CKEN_GRAPHICS 7 /* Graphics controller clock enable */ ++ ++#endif /* __ASM_ARCH_PXA3XX_REGS_H */ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/pxafb.h linux-2.6.25-rc4/include/asm-arm/arch/pxafb.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/pxafb.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/pxafb.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,85 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/pxafb.h ++ * ++ * Support for the xscale frame buffer. ++ * ++ * Author: Jean-Frederic Clere ++ * Created: Sep 22, 2003 ++ * Copyright: jfclere@sinix.net ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include <linux/fb.h> ++ ++/* ++ * This structure describes the machine which we are running on. ++ * It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine ++ * of linux/drivers/video/pxafb.c ++ */ ++struct pxafb_mode_info { ++ u_long pixclock; ++ ++ u_short xres; ++ u_short yres; ++ ++ u_char bpp; ++ u_char hsync_len; ++ u_char left_margin; ++ u_char right_margin; ++ ++ u_char vsync_len; ++ u_char upper_margin; ++ u_char lower_margin; ++ u_char sync; ++ ++ u_int cmap_greyscale:1, ++ unused:31; ++}; ++ ++struct pxafb_mach_info { ++ struct pxafb_mode_info *modes; ++ unsigned int num_modes; ++ ++ u_int fixed_modes:1, ++ cmap_inverse:1, ++ cmap_static:1, ++ unused:29; ++ ++ /* The following should be defined in LCCR0 ++ * LCCR0_Act or LCCR0_Pas Active or Passive ++ * LCCR0_Sngl or LCCR0_Dual Single/Dual panel ++ * LCCR0_Mono or LCCR0_Color Mono/Color ++ * LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode) ++ * LCCR0_DMADel(Tcpu) (optional) DMA request delay ++ * ++ * The following should not be defined in LCCR0: ++ * LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM ++ * LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB ++ */ ++ u_int lccr0; ++ /* The following should be defined in LCCR3 ++ * LCCR3_OutEnH or LCCR3_OutEnL Output enable polarity ++ * LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type ++ * LCCR3_Acb(X) AB Bias pin frequency ++ * LCCR3_DPC (optional) Double Pixel Clock mode (untested) ++ * ++ * The following should not be defined in LCCR3 ++ * LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp ++ */ ++ u_int lccr3; ++ /* The following should be defined in LCCR4 ++ * LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2 ++ * ++ * All other bits in LCCR4 should be left alone. ++ */ ++ u_int lccr4; ++ void (*pxafb_backlight_power)(int); ++ void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *); ++ ++}; ++void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info); ++void set_pxa_fb_parent(struct device *parent_dev); ++unsigned long pxafb_get_hsync_time(struct device *dev); +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/pxa-regs.h linux-2.6.25-rc4/include/asm-arm/arch/pxa-regs.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/pxa-regs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/pxa-regs.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,2150 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/pxa-regs.h ++ * ++ * Author: Nicolas Pitre ++ * Created: Jun 15, 2001 ++ * Copyright: MontaVista Software Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __PXA_REGS_H ++#define __PXA_REGS_H ++ ++ ++/* ++ * PXA Chip selects ++ */ ++ ++#define PXA_CS0_PHYS 0x00000000 ++#define PXA_CS1_PHYS 0x04000000 ++#define PXA_CS2_PHYS 0x08000000 ++#define PXA_CS3_PHYS 0x0C000000 ++#define PXA_CS4_PHYS 0x10000000 ++#define PXA_CS5_PHYS 0x14000000 ++ ++ ++/* ++ * Personal Computer Memory Card International Association (PCMCIA) sockets ++ */ ++ ++#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ ++#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ ++#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ ++#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ ++#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ ++ ++#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ ++#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ ++#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ ++#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ ++ ++#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ ++#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ ++#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ ++#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ ++ ++#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ ++ (0x20000000 + (Nb)*PCMCIASp) ++#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ ++#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ ++ (_PCMCIA (Nb) + 2*PCMCIAPrtSp) ++#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ ++ (_PCMCIA (Nb) + 3*PCMCIAPrtSp) ++ ++#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ ++#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ ++#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ ++#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ ++ ++#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ ++#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ ++#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ ++#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ ++ ++ ++ ++/* ++ * DMA Controller ++ */ ++ ++#define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */ ++#define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */ ++#define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */ ++#define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */ ++#define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */ ++#define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */ ++#define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */ ++#define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */ ++#define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */ ++#define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */ ++#define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */ ++#define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */ ++#define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */ ++#define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */ ++#define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */ ++#define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */ ++ ++#define DCSR(x) __REG2(0x40000000, (x) << 2) ++ ++#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ ++#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ ++#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ ++#ifdef CONFIG_PXA27x ++#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ ++#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ ++#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ ++#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ ++#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ ++#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ ++#define DCSR_EORINTR (1 << 9) /* The end of Receive */ ++#endif ++#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ ++#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ ++#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */ ++#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ ++#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ ++ ++#define DALGN __REG(0x400000a0) /* DMA Alignment Register */ ++#define DINT __REG(0x400000f0) /* DMA Interrupt Register */ ++ ++#define DRCMR(n) (*(((n) < 64) ? \ ++ &__REG2(0x40000100, ((n) & 0x3f) << 2) : \ ++ &__REG2(0x40001100, ((n) & 0x3f) << 2))) ++ ++#define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */ ++#define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */ ++#define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */ ++#define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */ ++#define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */ ++#define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */ ++#define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */ ++#define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */ ++#define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */ ++#define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */ ++#define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */ ++#define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */ ++#define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */ ++#define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */ ++#define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */ ++#define DRCMR15 __REG(0x4000013c) /* Request to Channel Map Register for SSP2 receive Request */ ++#define DRCMR16 __REG(0x40000140) /* Request to Channel Map Register for SSP2 transmit Request */ ++#define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */ ++#define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */ ++#define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */ ++#define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */ ++#define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */ ++#define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */ ++#define DRCMR23 __REG(0x4000015c) /* Reserved */ ++#define DRCMR24 __REG(0x40000160) /* Reserved */ ++#define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */ ++#define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */ ++#define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */ ++#define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */ ++#define DRCMR29 __REG(0x40000174) /* Reserved */ ++#define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */ ++#define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */ ++#define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */ ++#define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */ ++#define DRCMR34 __REG(0x40000188) /* Reserved */ ++#define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */ ++#define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */ ++#define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */ ++#define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */ ++#define DRCMR39 __REG(0x4000019C) /* Reserved */ ++#define DRCMR66 __REG(0x40001108) /* Request to Channel Map Register for SSP3 receive Request */ ++#define DRCMR67 __REG(0x4000110C) /* Request to Channel Map Register for SSP3 transmit Request */ ++#define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */ ++#define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */ ++#define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */ ++ ++#define DRCMRRXSADR DRCMR2 ++#define DRCMRTXSADR DRCMR3 ++#define DRCMRRXBTRBR DRCMR4 ++#define DRCMRTXBTTHR DRCMR5 ++#define DRCMRRXFFRBR DRCMR6 ++#define DRCMRTXFFTHR DRCMR7 ++#define DRCMRRXMCDR DRCMR8 ++#define DRCMRRXMODR DRCMR9 ++#define DRCMRTXMODR DRCMR10 ++#define DRCMRRXPCDR DRCMR11 ++#define DRCMRTXPCDR DRCMR12 ++#define DRCMRRXSSDR DRCMR13 ++#define DRCMRTXSSDR DRCMR14 ++#define DRCMRRXSS2DR DRCMR15 ++#define DRCMRTXSS2DR DRCMR16 ++#define DRCMRRXICDR DRCMR17 ++#define DRCMRTXICDR DRCMR18 ++#define DRCMRRXSTRBR DRCMR19 ++#define DRCMRTXSTTHR DRCMR20 ++#define DRCMRRXMMC DRCMR21 ++#define DRCMRTXMMC DRCMR22 ++#define DRCMRRXSS3DR DRCMR66 ++#define DRCMRTXSS3DR DRCMR67 ++#define DRCMRUDC(x) DRCMR((x) + 24) ++ ++#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ ++#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ ++ ++#define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */ ++#define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */ ++#define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */ ++#define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */ ++#define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */ ++#define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */ ++#define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */ ++#define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */ ++#define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */ ++#define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */ ++#define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */ ++#define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */ ++#define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */ ++#define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */ ++#define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */ ++#define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */ ++#define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */ ++#define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */ ++#define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */ ++#define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */ ++#define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */ ++#define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */ ++#define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */ ++#define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */ ++#define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */ ++#define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */ ++#define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */ ++#define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */ ++#define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */ ++#define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */ ++#define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */ ++#define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */ ++#define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */ ++#define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */ ++#define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */ ++#define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */ ++#define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */ ++#define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */ ++#define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */ ++#define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */ ++#define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */ ++#define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */ ++#define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */ ++#define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */ ++#define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */ ++#define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */ ++#define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */ ++#define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */ ++#define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */ ++#define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */ ++#define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */ ++#define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */ ++#define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */ ++#define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */ ++#define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */ ++#define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */ ++#define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */ ++#define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */ ++#define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */ ++#define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */ ++#define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */ ++#define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */ ++#define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */ ++#define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */ ++ ++#define DDADR(x) __REG2(0x40000200, (x) << 4) ++#define DSADR(x) __REG2(0x40000204, (x) << 4) ++#define DTADR(x) __REG2(0x40000208, (x) << 4) ++#define DCMD(x) __REG2(0x4000020c, (x) << 4) ++ ++#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ ++#define DDADR_STOP (1 << 0) /* Stop (read / write) */ ++ ++#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */ ++#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */ ++#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ ++#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */ ++#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ ++#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ ++#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */ ++#define DCMD_BURST8 (1 << 16) /* 8 byte burst */ ++#define DCMD_BURST16 (2 << 16) /* 16 byte burst */ ++#define DCMD_BURST32 (3 << 16) /* 32 byte burst */ ++#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */ ++#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ ++#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ ++#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ ++ ++ ++/* ++ * UARTs ++ */ ++ ++/* Full Function UART (FFUART) */ ++#define FFUART FFRBR ++#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ ++#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ ++#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ ++#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ ++#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ ++#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ ++#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ ++#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ ++#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ ++#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ ++#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ ++#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ ++#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ ++ ++/* Bluetooth UART (BTUART) */ ++#define BTUART BTRBR ++#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ ++#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ ++#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ ++#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ ++#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ ++#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ ++#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ ++#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ ++#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ ++#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ ++#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ ++#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ ++#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ ++ ++/* Standard UART (STUART) */ ++#define STUART STRBR ++#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ ++#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ ++#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ ++#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ ++#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ ++#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ ++#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ ++#define STLSR __REG(0x40700014) /* Line Status Register (read only) */ ++#define STMSR __REG(0x40700018) /* Reserved */ ++#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ ++#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ ++#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ ++#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ ++ ++/* Hardware UART (HWUART) */ ++#define HWUART HWRBR ++#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */ ++#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */ ++#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */ ++#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */ ++#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */ ++#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */ ++#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */ ++#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */ ++#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */ ++#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */ ++#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */ ++#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */ ++#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */ ++#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */ ++#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ ++#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ ++ ++#define IER_DMAE (1 << 7) /* DMA Requests Enable */ ++#define IER_UUE (1 << 6) /* UART Unit Enable */ ++#define IER_NRZE (1 << 5) /* NRZ coding Enable */ ++#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ ++#define IER_MIE (1 << 3) /* Modem Interrupt Enable */ ++#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ ++#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ ++#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ ++ ++#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ ++#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ ++#define IIR_TOD (1 << 3) /* Time Out Detected */ ++#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ ++#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ ++#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ ++ ++#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ ++#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ ++#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ ++#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ ++#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ ++#define FCR_ITL_1 (0) ++#define FCR_ITL_8 (FCR_ITL1) ++#define FCR_ITL_16 (FCR_ITL2) ++#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) ++ ++#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ ++#define LCR_SB (1 << 6) /* Set Break */ ++#define LCR_STKYP (1 << 5) /* Sticky Parity */ ++#define LCR_EPS (1 << 4) /* Even Parity Select */ ++#define LCR_PEN (1 << 3) /* Parity Enable */ ++#define LCR_STB (1 << 2) /* Stop Bit */ ++#define LCR_WLS1 (1 << 1) /* Word Length Select */ ++#define LCR_WLS0 (1 << 0) /* Word Length Select */ ++ ++#define LSR_FIFOE (1 << 7) /* FIFO Error Status */ ++#define LSR_TEMT (1 << 6) /* Transmitter Empty */ ++#define LSR_TDRQ (1 << 5) /* Transmit Data Request */ ++#define LSR_BI (1 << 4) /* Break Interrupt */ ++#define LSR_FE (1 << 3) /* Framing Error */ ++#define LSR_PE (1 << 2) /* Parity Error */ ++#define LSR_OE (1 << 1) /* Overrun Error */ ++#define LSR_DR (1 << 0) /* Data Ready */ ++ ++#define MCR_LOOP (1 << 4) ++#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ ++#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ ++#define MCR_RTS (1 << 1) /* Request to Send */ ++#define MCR_DTR (1 << 0) /* Data Terminal Ready */ ++ ++#define MSR_DCD (1 << 7) /* Data Carrier Detect */ ++#define MSR_RI (1 << 6) /* Ring Indicator */ ++#define MSR_DSR (1 << 5) /* Data Set Ready */ ++#define MSR_CTS (1 << 4) /* Clear To Send */ ++#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ ++#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ ++#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ ++#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ ++ ++/* ++ * IrSR (Infrared Selection Register) ++ */ ++#define STISR_RXPL (1 << 4) /* Receive Data Polarity */ ++#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */ ++#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */ ++#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */ ++#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */ ++ ++ ++/* ++ * I2C registers ++ */ ++ ++#define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */ ++#define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */ ++#define ICR __REG(0x40301690) /* I2C Control Register - ICR */ ++#define ISR __REG(0x40301698) /* I2C Status Register - ISR */ ++#define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */ ++ ++#define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */ ++#define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */ ++#define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */ ++#define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */ ++#define PWRISAR __REG(0x40f001A0) /*Power I2C Slave Address Register-ISAR */ ++ ++#define ICR_START (1 << 0) /* start bit */ ++#define ICR_STOP (1 << 1) /* stop bit */ ++#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */ ++#define ICR_TB (1 << 3) /* transfer byte bit */ ++#define ICR_MA (1 << 4) /* master abort */ ++#define ICR_SCLE (1 << 5) /* master clock enable */ ++#define ICR_IUE (1 << 6) /* unit enable */ ++#define ICR_GCD (1 << 7) /* general call disable */ ++#define ICR_ITEIE (1 << 8) /* enable tx interrupts */ ++#define ICR_IRFIE (1 << 9) /* enable rx interrupts */ ++#define ICR_BEIE (1 << 10) /* enable bus error ints */ ++#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */ ++#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */ ++#define ICR_SADIE (1 << 13) /* slave address detected int enable */ ++#define ICR_UR (1 << 14) /* unit reset */ ++ ++#define ISR_RWM (1 << 0) /* read/write mode */ ++#define ISR_ACKNAK (1 << 1) /* ack/nak status */ ++#define ISR_UB (1 << 2) /* unit busy */ ++#define ISR_IBB (1 << 3) /* bus busy */ ++#define ISR_SSD (1 << 4) /* slave stop detected */ ++#define ISR_ALD (1 << 5) /* arbitration loss detected */ ++#define ISR_ITE (1 << 6) /* tx buffer empty */ ++#define ISR_IRF (1 << 7) /* rx buffer full */ ++#define ISR_GCAD (1 << 8) /* general call address detected */ ++#define ISR_SAD (1 << 9) /* slave address detected */ ++#define ISR_BED (1 << 10) /* bus error no ACK/NAK */ ++ ++ ++/* ++ * Serial Audio Controller ++ */ ++ ++#define SACR0 __REG(0x40400000) /* Global Control Register */ ++#define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */ ++#define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ ++#define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */ ++#define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */ ++#define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */ ++#define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */ ++ ++#define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */ ++#define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */ ++#define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */ ++#define SACR0_EFWR (1 << 4) /* Enable EFWR Function */ ++#define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */ ++#define SACR0_BCKD (1 << 2) /* Bit Clock Direction */ ++#define SACR0_ENB (1 << 0) /* Enable I2S Link */ ++#define SACR1_ENLBF (1 << 5) /* Enable Loopback */ ++#define SACR1_DRPL (1 << 4) /* Disable Replaying Function */ ++#define SACR1_DREC (1 << 3) /* Disable Recording Function */ ++#define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */ ++ ++#define SASR0_I2SOFF (1 << 7) /* Controller Status */ ++#define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */ ++#define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */ ++#define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */ ++#define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */ ++#define SASR0_BSY (1 << 2) /* I2S Busy */ ++#define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */ ++#define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */ ++ ++#define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */ ++#define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */ ++ ++#define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */ ++#define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */ ++#define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */ ++#define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */ ++ ++/* ++ * AC97 Controller registers ++ */ ++ ++#define POCR __REG(0x40500000) /* PCM Out Control Register */ ++#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ ++#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ ++ ++#define PICR __REG(0x40500004) /* PCM In Control Register */ ++#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ ++#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ ++ ++#define MCCR __REG(0x40500008) /* Mic In Control Register */ ++#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ ++#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ ++ ++#define GCR __REG(0x4050000C) /* Global Control Register */ ++#ifdef CONFIG_PXA3xx ++#define GCR_CLKBPB (1 << 31) /* Internal clock enable */ ++#endif ++#define GCR_nDMAEN (1 << 24) /* non DMA Enable */ ++#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ ++#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ ++#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ ++#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ ++#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ ++#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ ++#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ ++#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ ++#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ ++#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ ++ ++#define POSR __REG(0x40500010) /* PCM Out Status Register */ ++#define POSR_FIFOE (1 << 4) /* FIFO error */ ++#define POSR_FSR (1 << 2) /* FIFO Service Request */ ++ ++#define PISR __REG(0x40500014) /* PCM In Status Register */ ++#define PISR_FIFOE (1 << 4) /* FIFO error */ ++#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ ++#define PISR_FSR (1 << 2) /* FIFO Service Request */ ++ ++#define MCSR __REG(0x40500018) /* Mic In Status Register */ ++#define MCSR_FIFOE (1 << 4) /* FIFO error */ ++#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ ++#define MCSR_FSR (1 << 2) /* FIFO Service Request */ ++ ++#define GSR __REG(0x4050001C) /* Global Status Register */ ++#define GSR_CDONE (1 << 19) /* Command Done */ ++#define GSR_SDONE (1 << 18) /* Status Done */ ++#define GSR_RDCS (1 << 15) /* Read Completion Status */ ++#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ ++#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ ++#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ ++#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ ++#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ ++#define GSR_SCR (1 << 9) /* Secondary Codec Ready */ ++#define GSR_PCR (1 << 8) /* Primary Codec Ready */ ++#define GSR_MCINT (1 << 7) /* Mic In Interrupt */ ++#define GSR_POINT (1 << 6) /* PCM Out Interrupt */ ++#define GSR_PIINT (1 << 5) /* PCM In Interrupt */ ++#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ ++#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ ++#define GSR_MIINT (1 << 1) /* Modem In Interrupt */ ++#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ ++ ++#define CAR __REG(0x40500020) /* CODEC Access Register */ ++#define CAR_CAIP (1 << 0) /* Codec Access In Progress */ ++ ++#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ ++#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ ++ ++#define MOCR __REG(0x40500100) /* Modem Out Control Register */ ++#define MOCR_FEIE (1 << 3) /* FIFO Error */ ++#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ ++ ++#define MICR __REG(0x40500108) /* Modem In Control Register */ ++#define MICR_FEIE (1 << 3) /* FIFO Error */ ++#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ ++ ++#define MOSR __REG(0x40500110) /* Modem Out Status Register */ ++#define MOSR_FIFOE (1 << 4) /* FIFO error */ ++#define MOSR_FSR (1 << 2) /* FIFO Service Request */ ++ ++#define MISR __REG(0x40500118) /* Modem In Status Register */ ++#define MISR_FIFOE (1 << 4) /* FIFO error */ ++#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ ++#define MISR_FSR (1 << 2) /* FIFO Service Request */ ++ ++#define MODR __REG(0x40500140) /* Modem FIFO Data Register */ ++ ++#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ ++#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ ++#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ ++#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ ++ ++ ++/* ++ * USB Device Controller ++ * PXA25x and PXA27x USB device controller registers are different. ++ */ ++#if defined(CONFIG_PXA25x) ++ ++#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */ ++#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */ ++#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */ ++ ++#define UDCCR __REG(0x40600000) /* UDC Control Register */ ++#define UDCCR_UDE (1 << 0) /* UDC enable */ ++#define UDCCR_UDA (1 << 1) /* UDC active */ ++#define UDCCR_RSM (1 << 2) /* Device resume */ ++#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */ ++#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */ ++#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */ ++#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */ ++#define UDCCR_REM (1 << 7) /* Reset interrupt mask */ ++ ++#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */ ++#define UDCCS0_OPR (1 << 0) /* OUT packet ready */ ++#define UDCCS0_IPR (1 << 1) /* IN packet ready */ ++#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ ++#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */ ++#define UDCCS0_SST (1 << 4) /* Sent stall */ ++#define UDCCS0_FST (1 << 5) /* Force stall */ ++#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */ ++#define UDCCS0_SA (1 << 7) /* Setup active */ ++ ++/* Bulk IN - Endpoint 1,6,11 */ ++#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */ ++#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */ ++#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */ ++ ++#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ ++#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ ++#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */ ++#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */ ++#define UDCCS_BI_SST (1 << 4) /* Sent stall */ ++#define UDCCS_BI_FST (1 << 5) /* Force stall */ ++#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ ++ ++/* Bulk OUT - Endpoint 2,7,12 */ ++#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */ ++#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */ ++#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */ ++ ++#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ ++#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ ++#define UDCCS_BO_DME (1 << 3) /* DMA enable */ ++#define UDCCS_BO_SST (1 << 4) /* Sent stall */ ++#define UDCCS_BO_FST (1 << 5) /* Force stall */ ++#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */ ++#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ ++ ++/* Isochronous IN - Endpoint 3,8,13 */ ++#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */ ++#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */ ++#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */ ++ ++#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ ++#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ ++#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */ ++#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */ ++#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ ++ ++/* Isochronous OUT - Endpoint 4,9,14 */ ++#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */ ++#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */ ++#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */ ++ ++#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ ++#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ ++#define UDCCS_IO_ROF (1 << 2) /* Receive overflow */ ++#define UDCCS_IO_DME (1 << 3) /* DMA enable */ ++#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ ++#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ ++ ++/* Interrupt IN - Endpoint 5,10,15 */ ++#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */ ++#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */ ++#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */ ++ ++#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ ++#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ ++#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */ ++#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */ ++#define UDCCS_INT_SST (1 << 4) /* Sent stall */ ++#define UDCCS_INT_FST (1 << 5) /* Force stall */ ++#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ ++ ++#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */ ++#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */ ++#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */ ++#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */ ++#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */ ++#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */ ++#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */ ++#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */ ++#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */ ++#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */ ++#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */ ++#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */ ++#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */ ++#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */ ++#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */ ++#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */ ++#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */ ++#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */ ++#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */ ++#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */ ++#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */ ++#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */ ++#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */ ++#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */ ++ ++#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */ ++ ++#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ ++#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ ++#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */ ++#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */ ++#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */ ++#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */ ++#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ ++#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ ++ ++#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */ ++ ++#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ ++#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ ++#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */ ++#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */ ++#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */ ++#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */ ++#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ ++#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ ++ ++#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */ ++ ++#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */ ++#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */ ++#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */ ++#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */ ++#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */ ++#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */ ++#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */ ++#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */ ++ ++#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */ ++ ++#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */ ++#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */ ++#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */ ++#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */ ++#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */ ++#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */ ++#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */ ++#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */ ++ ++#elif defined(CONFIG_PXA27x) ++ ++#define UDCCR __REG(0x40600000) /* UDC Control Register */ ++#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ ++#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation ++ Protocol Port Support */ ++#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol ++ Support */ ++#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol ++ Enable */ ++#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */ ++#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */ ++#define UDCCR_ACN_S 11 ++#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */ ++#define UDCCR_AIN_S 8 ++#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface ++ Setting Number */ ++#define UDCCR_AAISN_S 5 ++#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active ++ Configuration */ ++#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration ++ Error */ ++#define UDCCR_UDR (1 << 2) /* UDC Resume */ ++#define UDCCR_UDA (1 << 1) /* UDC Active */ ++#define UDCCR_UDE (1 << 0) /* UDC Enable */ ++ ++#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */ ++#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */ ++#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */ ++#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ ++ ++#define UDC_INT_FIFOERROR (0x2) ++#define UDC_INT_PACKETCMP (0x1) ++ ++#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) ++#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */ ++#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */ ++#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */ ++#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */ ++#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */ ++ ++#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */ ++#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */ ++#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) ++#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */ ++#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */ ++#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */ ++#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */ ++#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */ ++ ++#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */ ++#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */ ++#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ ++#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt ++ Rising Edge Interrupt Enable */ ++#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt ++ Falling Edge Interrupt Enable */ ++#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge ++ Interrupt Enable */ ++#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge ++ Interrupt Enable */ ++#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge ++ Interrupt Enable */ ++#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge ++ Interrupt Enable */ ++#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge ++ Interrupt Enable */ ++#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge ++ Interrupt Enable */ ++#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising ++ Edge Interrupt Enable */ ++#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling ++ Edge Interrupt Enable */ ++#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge ++ Interrupt Enable */ ++#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge ++ Interrupt Enable */ ++ ++#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */ ++ ++#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */ ++#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */ ++#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */ ++#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */ ++#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */ ++#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */ ++#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */ ++#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */ ++#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */ ++#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */ ++#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */ ++#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */ ++#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */ ++#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */ ++ ++#define UDCCSN(x) __REG2(0x40600100, (x) << 2) ++#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */ ++#define UDCCSR0_SA (1 << 7) /* Setup Active */ ++#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ ++#define UDCCSR0_FST (1 << 5) /* Force Stall */ ++#define UDCCSR0_SST (1 << 4) /* Sent Stall */ ++#define UDCCSR0_DME (1 << 3) /* DMA Enable */ ++#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ ++#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */ ++#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */ ++ ++#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */ ++#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */ ++#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */ ++#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */ ++#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */ ++#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */ ++#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */ ++#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */ ++#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */ ++#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */ ++#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */ ++#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */ ++#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */ ++#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */ ++#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */ ++#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */ ++#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */ ++#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */ ++#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */ ++#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */ ++#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */ ++#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */ ++#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */ ++ ++#define UDCCSR_DPE (1 << 9) /* Data Packet Error */ ++#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ ++#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */ ++#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */ ++#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */ ++#define UDCCSR_FST (1 << 5) /* Force STALL */ ++#define UDCCSR_SST (1 << 4) /* Sent STALL */ ++#define UDCCSR_DME (1 << 3) /* DMA Enable */ ++#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */ ++#define UDCCSR_PC (1 << 1) /* Packet Complete */ ++#define UDCCSR_FS (1 << 0) /* FIFO needs service */ ++ ++#define UDCBCN(x) __REG2(0x40600200, (x)<<2) ++#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */ ++#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */ ++#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */ ++#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */ ++#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */ ++#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */ ++#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */ ++#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */ ++#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */ ++#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */ ++#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */ ++#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */ ++#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */ ++#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */ ++#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */ ++#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */ ++#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */ ++#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */ ++#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */ ++#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */ ++#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */ ++#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */ ++#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */ ++#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */ ++ ++#define UDCDN(x) __REG2(0x40600300, (x)<<2) ++#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2)) ++#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x)))) ++#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */ ++#define UDCDRA __REG(0x40600304) /* Data Register - EPA */ ++#define UDCDRB __REG(0x40600308) /* Data Register - EPB */ ++#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */ ++#define UDCDRD __REG(0x40600310) /* Data Register - EPD */ ++#define UDCDRE __REG(0x40600314) /* Data Register - EPE */ ++#define UDCDRF __REG(0x40600318) /* Data Register - EPF */ ++#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */ ++#define UDCDRH __REG(0x40600320) /* Data Register - EPH */ ++#define UDCDRI __REG(0x40600324) /* Data Register - EPI */ ++#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */ ++#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */ ++#define UDCDRL __REG(0x40600330) /* Data Register - EPL */ ++#define UDCDRM __REG(0x40600334) /* Data Register - EPM */ ++#define UDCDRN __REG(0x40600338) /* Data Register - EPN */ ++#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */ ++#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */ ++#define UDCDRR __REG(0x40600344) /* Data Register - EPR */ ++#define UDCDRS __REG(0x40600348) /* Data Register - EPS */ ++#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */ ++#define UDCDRU __REG(0x40600350) /* Data Register - EPU */ ++#define UDCDRV __REG(0x40600354) /* Data Register - EPV */ ++#define UDCDRW __REG(0x40600358) /* Data Register - EPW */ ++#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */ ++ ++#define UDCCN(x) __REG2(0x40600400, (x)<<2) ++#define UDCCRA __REG(0x40600404) /* Configuration register EPA */ ++#define UDCCRB __REG(0x40600408) /* Configuration register EPB */ ++#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */ ++#define UDCCRD __REG(0x40600410) /* Configuration register EPD */ ++#define UDCCRE __REG(0x40600414) /* Configuration register EPE */ ++#define UDCCRF __REG(0x40600418) /* Configuration register EPF */ ++#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */ ++#define UDCCRH __REG(0x40600420) /* Configuration register EPH */ ++#define UDCCRI __REG(0x40600424) /* Configuration register EPI */ ++#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */ ++#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */ ++#define UDCCRL __REG(0x40600430) /* Configuration register EPL */ ++#define UDCCRM __REG(0x40600434) /* Configuration register EPM */ ++#define UDCCRN __REG(0x40600438) /* Configuration register EPN */ ++#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */ ++#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */ ++#define UDCCRR __REG(0x40600444) /* Configuration register EPR */ ++#define UDCCRS __REG(0x40600448) /* Configuration register EPS */ ++#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */ ++#define UDCCRU __REG(0x40600450) /* Configuration register EPU */ ++#define UDCCRV __REG(0x40600454) /* Configuration register EPV */ ++#define UDCCRW __REG(0x40600458) /* Configuration register EPW */ ++#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */ ++ ++#define UDCCONR_CN (0x03 << 25) /* Configuration Number */ ++#define UDCCONR_CN_S (25) ++#define UDCCONR_IN (0x07 << 22) /* Interface Number */ ++#define UDCCONR_IN_S (22) ++#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */ ++#define UDCCONR_AISN_S (19) ++#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */ ++#define UDCCONR_EN_S (15) ++#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */ ++#define UDCCONR_ET_S (13) ++#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */ ++#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */ ++#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */ ++#define UDCCONR_ET_NU (0x00 << 13) /* Not used */ ++#define UDCCONR_ED (1 << 12) /* Endpoint Direction */ ++#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */ ++#define UDCCONR_MPS_S (2) ++#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */ ++#define UDCCONR_EE (1 << 0) /* Endpoint Enable */ ++ ++ ++#define UDC_INT_FIFOERROR (0x2) ++#define UDC_INT_PACKETCMP (0x1) ++ ++#define UDC_FNR_MASK (0x7ff) ++ ++#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST) ++#define UDC_BCR_MASK (0x3ff) ++#endif ++ ++/* ++ * Fast Infrared Communication Port ++ */ ++ ++#define FICP __REG(0x40800000) /* Start of FICP area */ ++#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ ++#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */ ++#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */ ++#define ICDR __REG(0x4080000c) /* ICP Data Register */ ++#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ ++#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ ++ ++#define ICCR0_AME (1 << 7) /* Address match enable */ ++#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */ ++#define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */ ++#define ICCR0_RXE (1 << 4) /* Receive enable */ ++#define ICCR0_TXE (1 << 3) /* Transmit enable */ ++#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */ ++#define ICCR0_LBM (1 << 1) /* Loopback mode */ ++#define ICCR0_ITR (1 << 0) /* IrDA transmission */ ++ ++#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */ ++#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */ ++#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */ ++#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */ ++#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */ ++#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */ ++ ++#ifdef CONFIG_PXA27x ++#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */ ++#endif ++#define ICSR0_FRE (1 << 5) /* Framing error */ ++#define ICSR0_RFS (1 << 4) /* Receive FIFO service request */ ++#define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */ ++#define ICSR0_RAB (1 << 2) /* Receiver abort */ ++#define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */ ++#define ICSR0_EIF (1 << 0) /* End/Error in FIFO */ ++ ++#define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */ ++#define ICSR1_CRE (1 << 5) /* CRC error */ ++#define ICSR1_EOF (1 << 4) /* End of frame */ ++#define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */ ++#define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */ ++#define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */ ++#define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */ ++ ++ ++/* ++ * Real Time Clock ++ */ ++ ++#define RCNR __REG(0x40900000) /* RTC Count Register */ ++#define RTAR __REG(0x40900004) /* RTC Alarm Register */ ++#define RTSR __REG(0x40900008) /* RTC Status Register */ ++#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ ++#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ ++ ++#define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */ ++#define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */ ++#define RTSR_HZE (1 << 3) /* HZ interrupt enable */ ++#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ ++#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ ++#define RTSR_AL (1 << 0) /* RTC alarm detected */ ++ ++ ++/* ++ * OS Timer & Match Registers ++ */ ++ ++#define OSMR0 __REG(0x40A00000) /* */ ++#define OSMR1 __REG(0x40A00004) /* */ ++#define OSMR2 __REG(0x40A00008) /* */ ++#define OSMR3 __REG(0x40A0000C) /* */ ++#define OSMR4 __REG(0x40A00080) /* */ ++#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ ++#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ ++#define OMCR4 __REG(0x40A000C0) /* */ ++#define OSSR __REG(0x40A00014) /* OS Timer Status Register */ ++#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ ++#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ ++ ++#define OSSR_M3 (1 << 3) /* Match status channel 3 */ ++#define OSSR_M2 (1 << 2) /* Match status channel 2 */ ++#define OSSR_M1 (1 << 1) /* Match status channel 1 */ ++#define OSSR_M0 (1 << 0) /* Match status channel 0 */ ++ ++#define OWER_WME (1 << 0) /* Watchdog Match Enable */ ++ ++#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ ++#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ ++#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ ++#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ ++ ++ ++/* ++ * Pulse Width Modulator ++ */ ++ ++#define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */ ++#define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */ ++#define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */ ++ ++#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */ ++#define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */ ++#define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */ ++ ++ ++/* ++ * Interrupt Controller ++ */ ++ ++#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */ ++#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */ ++#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */ ++#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ ++#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ ++#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ ++ ++ ++/* ++ * General Purpose I/O ++ */ ++ ++#define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000)) ++#define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004)) ++#define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008)) ++#define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100)) ++ ++#define GPLR_OFFSET 0x00 ++#define GPDR_OFFSET 0x0C ++#define GPSR_OFFSET 0x18 ++#define GPCR_OFFSET 0x24 ++#define GRER_OFFSET 0x30 ++#define GFER_OFFSET 0x3C ++#define GEDR_OFFSET 0x48 ++ ++#define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ ++#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ ++#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ ++ ++#define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */ ++#define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */ ++#define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */ ++ ++#define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */ ++#define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */ ++#define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */ ++ ++#define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */ ++#define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */ ++#define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */ ++ ++#define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */ ++#define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */ ++#define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */ ++ ++#define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */ ++#define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */ ++#define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */ ++ ++#define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */ ++#define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */ ++#define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */ ++ ++#define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */ ++#define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */ ++#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */ ++#define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */ ++#define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */ ++#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO<95-80> */ ++#define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */ ++#define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */ ++ ++#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */ ++#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */ ++#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */ ++#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */ ++#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */ ++#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */ ++#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */ ++ ++/* More handy macros. The argument is a literal GPIO number. */ ++ ++#define GPIO_bit(x) (1 << ((x) & 0x1f)) ++ ++#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) ++ ++/* Interrupt Controller */ ++ ++#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ ++#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ ++#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ ++#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ ++#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ ++ ++#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) ++#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) ++#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) ++#define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) ++#define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) ++#define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) ++#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) ++#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) ++ ++#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3)) ++#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3)) ++#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3)) ++#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3)) ++#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3)) ++#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3)) ++#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) ++#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ ++ ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) ++#else ++ ++#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) ++#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) ++#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) ++#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) ++#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) ++#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) ++#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) ++#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) ++ ++#endif ++ ++ ++/* GPIO alternate function assignments */ ++ ++#define GPIO1_RST 1 /* reset */ ++#define GPIO6_MMCCLK 6 /* MMC Clock */ ++#define GPIO7_48MHz 7 /* 48 MHz clock output */ ++#define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */ ++#define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */ ++#define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */ ++#define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */ ++#define GPIO12_32KHz 12 /* 32 kHz out */ ++#define GPIO13_MBGNT 13 /* memory controller grant */ ++#define GPIO14_MBREQ 14 /* alternate bus master request */ ++#define GPIO15_nCS_1 15 /* chip select 1 */ ++#define GPIO16_PWM0 16 /* PWM0 output */ ++#define GPIO17_PWM1 17 /* PWM1 output */ ++#define GPIO18_RDY 18 /* Ext. Bus Ready */ ++#define GPIO19_DREQ1 19 /* External DMA Request */ ++#define GPIO20_DREQ0 20 /* External DMA Request */ ++#define GPIO23_SCLK 23 /* SSP clock */ ++#define GPIO24_SFRM 24 /* SSP Frame */ ++#define GPIO25_STXD 25 /* SSP transmit */ ++#define GPIO26_SRXD 26 /* SSP receive */ ++#define GPIO27_SEXTCLK 27 /* SSP ext_clk */ ++#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ ++#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ ++#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ ++#define GPIO31_SYNC 31 /* AC97/I2S sync */ ++#define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */ ++#define GPIO32_SYSCLK 32 /* I2S System Clock */ ++#define GPIO32_MMCCLK 32 /* MMC Clock (PXA270) */ ++#define GPIO33_nCS_5 33 /* chip select 5 */ ++#define GPIO34_FFRXD 34 /* FFUART receive */ ++#define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */ ++#define GPIO35_FFCTS 35 /* FFUART Clear to send */ ++#define GPIO36_FFDCD 36 /* FFUART Data carrier detect */ ++#define GPIO37_FFDSR 37 /* FFUART data set ready */ ++#define GPIO38_FFRI 38 /* FFUART Ring Indicator */ ++#define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */ ++#define GPIO39_FFTXD 39 /* FFUART transmit data */ ++#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ ++#define GPIO41_FFRTS 41 /* FFUART request to send */ ++#define GPIO42_BTRXD 42 /* BTUART receive data */ ++#define GPIO42_HWRXD 42 /* HWUART receive data */ ++#define GPIO43_BTTXD 43 /* BTUART transmit data */ ++#define GPIO43_HWTXD 43 /* HWUART transmit data */ ++#define GPIO44_BTCTS 44 /* BTUART clear to send */ ++#define GPIO44_HWCTS 44 /* HWUART clear to send */ ++#define GPIO45_BTRTS 45 /* BTUART request to send */ ++#define GPIO45_HWRTS 45 /* HWUART request to send */ ++#define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */ ++#define GPIO46_ICPRXD 46 /* ICP receive data */ ++#define GPIO46_STRXD 46 /* STD_UART receive data */ ++#define GPIO47_ICPTXD 47 /* ICP transmit data */ ++#define GPIO47_STTXD 47 /* STD_UART transmit data */ ++#define GPIO48_nPOE 48 /* Output Enable for Card Space */ ++#define GPIO49_nPWE 49 /* Write Enable for Card Space */ ++#define GPIO50_nPIOR 50 /* I/O Read for Card Space */ ++#define GPIO51_nPIOW 51 /* I/O Write for Card Space */ ++#define GPIO52_nPCE_1 52 /* Card Enable for Card Space */ ++#define GPIO53_nPCE_2 53 /* Card Enable for Card Space */ ++#define GPIO53_MMCCLK 53 /* MMC Clock */ ++#define GPIO54_MMCCLK 54 /* MMC Clock */ ++#define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */ ++#define GPIO54_nPCE_2 54 /* Card Enable for Card Space (PXA27x) */ ++#define GPIO55_nPREG 55 /* Card Address bit 26 */ ++#define GPIO56_nPWAIT 56 /* Wait signal for Card Space */ ++#define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */ ++#define GPIO58_LDD_0 58 /* LCD data pin 0 */ ++#define GPIO59_LDD_1 59 /* LCD data pin 1 */ ++#define GPIO60_LDD_2 60 /* LCD data pin 2 */ ++#define GPIO61_LDD_3 61 /* LCD data pin 3 */ ++#define GPIO62_LDD_4 62 /* LCD data pin 4 */ ++#define GPIO63_LDD_5 63 /* LCD data pin 5 */ ++#define GPIO64_LDD_6 64 /* LCD data pin 6 */ ++#define GPIO65_LDD_7 65 /* LCD data pin 7 */ ++#define GPIO66_LDD_8 66 /* LCD data pin 8 */ ++#define GPIO66_MBREQ 66 /* alternate bus master req */ ++#define GPIO67_LDD_9 67 /* LCD data pin 9 */ ++#define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */ ++#define GPIO68_LDD_10 68 /* LCD data pin 10 */ ++#define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */ ++#define GPIO69_LDD_11 69 /* LCD data pin 11 */ ++#define GPIO69_MMCCLK 69 /* MMC_CLK */ ++#define GPIO70_LDD_12 70 /* LCD data pin 12 */ ++#define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */ ++#define GPIO71_LDD_13 71 /* LCD data pin 13 */ ++#define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */ ++#define GPIO72_LDD_14 72 /* LCD data pin 14 */ ++#define GPIO72_32kHz 72 /* 32 kHz clock */ ++#define GPIO73_LDD_15 73 /* LCD data pin 15 */ ++#define GPIO73_MBGNT 73 /* Memory controller grant */ ++#define GPIO74_LCD_FCLK 74 /* LCD Frame clock */ ++#define GPIO75_LCD_LCLK 75 /* LCD line clock */ ++#define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */ ++#define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */ ++#define GPIO78_nCS_2 78 /* chip select 2 */ ++#define GPIO79_nCS_3 79 /* chip select 3 */ ++#define GPIO80_nCS_4 80 /* chip select 4 */ ++#define GPIO81_NSCLK 81 /* NSSP clock */ ++#define GPIO82_NSFRM 82 /* NSSP Frame */ ++#define GPIO83_NSTXD 83 /* NSSP transmit */ ++#define GPIO84_NSRXD 84 /* NSSP receive */ ++#define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */ ++#define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */ ++#define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */ ++#define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */ ++#define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */ ++#define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */ ++#define GPIO111_MMCDAT3 111 /* MMC DAT3 (PXA27x) */ ++#define GPIO111_MMCCS1 111 /* MMC Chip Select 1 (PXA27x) */ ++#define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */ ++#define GPIO113_I2S_SYSCLK 113 /* I2S System Clock (PXA27x) */ ++#define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */ ++ ++/* GPIO alternate function mode & direction */ ++ ++#define GPIO_IN 0x000 ++#define GPIO_OUT 0x080 ++#define GPIO_ALT_FN_1_IN 0x100 ++#define GPIO_ALT_FN_1_OUT 0x180 ++#define GPIO_ALT_FN_2_IN 0x200 ++#define GPIO_ALT_FN_2_OUT 0x280 ++#define GPIO_ALT_FN_3_IN 0x300 ++#define GPIO_ALT_FN_3_OUT 0x380 ++#define GPIO_MD_MASK_NR 0x07f ++#define GPIO_MD_MASK_DIR 0x080 ++#define GPIO_MD_MASK_FN 0x300 ++#define GPIO_DFLT_LOW 0x400 ++#define GPIO_DFLT_HIGH 0x800 ++ ++#define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN) ++#define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT) ++#define GPIO7_48MHz_MD ( 7 | GPIO_ALT_FN_1_OUT) ++#define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT) ++#define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT) ++#define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT) ++#define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT) ++#define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT) ++#define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT) ++#define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN) ++#define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT) ++#define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT) ++#define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT) ++#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN) ++#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN) ++#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN) ++#define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT) ++#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT) ++#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT) ++#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN) ++#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN) ++#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN) ++#define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN) ++#define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT) ++#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN) ++#define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN) ++#define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT) ++#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT) ++#define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT) ++#define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT) ++#define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN) ++#define GPIO32_SYSCLK_I2S_MD (32 | GPIO_ALT_FN_1_OUT) ++#define GPIO32_MMCCLK_MD ( 32 | GPIO_ALT_FN_2_OUT) ++#define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT) ++#define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN) ++#define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT) ++#define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN) ++#define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN) ++#define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN) ++#define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN) ++#define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT) ++#define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT) ++#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) ++#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) ++#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) ++#define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN) ++#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) ++#define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT) ++#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) ++#define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN) ++#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) ++#define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT) ++#define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT) ++#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) ++#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) ++#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) ++#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) ++#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) ++#define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT) ++#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) ++#define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN) ++#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) ++#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) ++#define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN) ++#define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT) ++#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) ++#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) ++#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) ++#define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT) ++#define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT) ++#define GPIO54_nPCE_2_MD (54 | GPIO_ALT_FN_2_OUT) ++#define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT) ++#define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT) ++#define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN) ++#define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN) ++#define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT) ++#define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT) ++#define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT) ++#define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT) ++#define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT) ++#define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT) ++#define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT) ++#define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT) ++#define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT) ++#define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN) ++#define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT) ++#define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT) ++#define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT) ++#define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT) ++#define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT) ++#define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT) ++#define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT) ++#define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT) ++#define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT) ++#define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT) ++#define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT) ++#define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT) ++#define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT) ++#define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT) ++#define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT) ++#define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT) ++#define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT) ++#define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT) ++#define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT) ++#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT) ++#define GPIO79_pSKTSEL_MD (79 | GPIO_ALT_FN_1_OUT) ++#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT) ++#define GPIO81_NSSP_CLK_OUT (81 | GPIO_ALT_FN_1_OUT) ++#define GPIO81_NSSP_CLK_IN (81 | GPIO_ALT_FN_1_IN) ++#define GPIO82_NSSP_FRM_OUT (82 | GPIO_ALT_FN_1_OUT) ++#define GPIO82_NSSP_FRM_IN (82 | GPIO_ALT_FN_1_IN) ++#define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT) ++#define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN) ++#define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT) ++#define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN) ++#define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT) ++#define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT) ++#define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT) ++#define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT) ++#define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT) ++#define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT) ++#define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT) ++#define GPIO111_MMCDAT3_MD (111 | GPIO_ALT_FN_1_OUT) ++#define GPIO110_MMCCS1_MD (111 | GPIO_ALT_FN_1_OUT) ++#define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT) ++#define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT) ++#define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT) ++#define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN) ++#define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN) ++ ++/* ++ * Power Manager ++ */ ++ ++#define PMCR __REG(0x40F00000) /* Power Manager Control Register */ ++#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ ++#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ ++#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */ ++#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */ ++#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */ ++#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */ ++#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */ ++#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ ++#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ ++#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ ++#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */ ++#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ ++ ++#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */ ++#define PSTR __REG(0x40F00038) /*Power Manager Standby Config Register */ ++#define PSNR __REG(0x40F0003C) /*Power Manager Sense Config Register */ ++#define PVCR __REG(0x40F00040) /*Power Manager VoltageControl Register */ ++#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */ ++#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */ ++#define PCMD(x) __REG2(0x40F00080, (x)<<2) ++#define PCMD0 __REG(0x40F00080 + 0 * 4) ++#define PCMD1 __REG(0x40F00080 + 1 * 4) ++#define PCMD2 __REG(0x40F00080 + 2 * 4) ++#define PCMD3 __REG(0x40F00080 + 3 * 4) ++#define PCMD4 __REG(0x40F00080 + 4 * 4) ++#define PCMD5 __REG(0x40F00080 + 5 * 4) ++#define PCMD6 __REG(0x40F00080 + 6 * 4) ++#define PCMD7 __REG(0x40F00080 + 7 * 4) ++#define PCMD8 __REG(0x40F00080 + 8 * 4) ++#define PCMD9 __REG(0x40F00080 + 9 * 4) ++#define PCMD10 __REG(0x40F00080 + 10 * 4) ++#define PCMD11 __REG(0x40F00080 + 11 * 4) ++#define PCMD12 __REG(0x40F00080 + 12 * 4) ++#define PCMD13 __REG(0x40F00080 + 13 * 4) ++#define PCMD14 __REG(0x40F00080 + 14 * 4) ++#define PCMD15 __REG(0x40F00080 + 15 * 4) ++#define PCMD16 __REG(0x40F00080 + 16 * 4) ++#define PCMD17 __REG(0x40F00080 + 17 * 4) ++#define PCMD18 __REG(0x40F00080 + 18 * 4) ++#define PCMD19 __REG(0x40F00080 + 19 * 4) ++#define PCMD20 __REG(0x40F00080 + 20 * 4) ++#define PCMD21 __REG(0x40F00080 + 21 * 4) ++#define PCMD22 __REG(0x40F00080 + 22 * 4) ++#define PCMD23 __REG(0x40F00080 + 23 * 4) ++#define PCMD24 __REG(0x40F00080 + 24 * 4) ++#define PCMD25 __REG(0x40F00080 + 25 * 4) ++#define PCMD26 __REG(0x40F00080 + 26 * 4) ++#define PCMD27 __REG(0x40F00080 + 27 * 4) ++#define PCMD28 __REG(0x40F00080 + 28 * 4) ++#define PCMD29 __REG(0x40F00080 + 29 * 4) ++#define PCMD30 __REG(0x40F00080 + 30 * 4) ++#define PCMD31 __REG(0x40F00080 + 31 * 4) ++ ++#define PCMD_MBC (1<<12) ++#define PCMD_DCE (1<<11) ++#define PCMD_LC (1<<10) ++/* FIXME: PCMD_SQC need be checked. */ ++#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable, ++ bit 9 should be 0 all day. */ ++#define PVCR_VCSA (0x1<<14) ++#define PVCR_CommandDelay (0xf80) ++#define PCFR_PI2C_EN (0x1 << 6) ++ ++#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ ++#define PSSR_RDH (1 << 5) /* Read Disable Hold */ ++#define PSSR_PH (1 << 4) /* Peripheral Control Hold */ ++#define PSSR_STS (1 << 3) /* Standby Mode Status */ ++#define PSSR_VFS (1 << 2) /* VDD Fault Status */ ++#define PSSR_BFS (1 << 1) /* Battery Fault Status */ ++#define PSSR_SSS (1 << 0) /* Software Sleep Status */ ++ ++#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */ ++ ++#define PCFR_RO (1 << 15) /* RDH Override */ ++#define PCFR_PO (1 << 14) /* PH Override */ ++#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */ ++#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */ ++#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */ ++#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */ ++#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */ ++#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */ ++#define PCFR_DS (1 << 3) /* Deep Sleep Mode */ ++#define PCFR_FS (1 << 2) /* Float Static Chip Selects */ ++#define PCFR_FP (1 << 1) /* Float PCMCIA controls */ ++#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ ++ ++#define RCSR_GPR (1 << 3) /* GPIO Reset */ ++#define RCSR_SMR (1 << 2) /* Sleep Mode */ ++#define RCSR_WDR (1 << 1) /* Watchdog Reset */ ++#define RCSR_HWR (1 << 0) /* Hardware Reset */ ++ ++#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */ ++#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ ++#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ ++#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ ++#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ ++#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ ++#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ ++#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ ++#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ ++#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ ++#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ ++#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ ++#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ ++#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ ++#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ ++#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ ++#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ ++#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ ++ ++/* ++ * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h ++ */ ++ ++/* ++ * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h ++ */ ++ ++/* ++ * Core Clock ++ */ ++ ++#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */ ++#define CKEN __REG(0x41300004) /* Clock Enable Register */ ++#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ ++#define CCSR __REG(0x4130000C) /* Core Clock Status Register */ ++ ++#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ ++#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ ++#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ ++ ++#define CKEN_AC97CONF (31) /* AC97 Controller Configuration */ ++#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */ ++#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */ ++#define CKEN_MEMC (22) /* Memory Controller Clock Enable */ ++#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */ ++#define CKEN_IM (20) /* Internal Memory Clock Enable */ ++#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */ ++#define CKEN_USIM (18) /* USIM Unit Clock Enable */ ++#define CKEN_MSL (17) /* MSL Unit Clock Enable */ ++#define CKEN_LCD (16) /* LCD Unit Clock Enable */ ++#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */ ++#define CKEN_I2C (14) /* I2C Unit Clock Enable */ ++#define CKEN_FICP (13) /* FICP Unit Clock Enable */ ++#define CKEN_MMC (12) /* MMC Unit Clock Enable */ ++#define CKEN_USB (11) /* USB Unit Clock Enable */ ++#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */ ++#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */ ++#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */ ++#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */ ++#define CKEN_I2S (8) /* I2S Unit Clock Enable */ ++#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */ ++#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */ ++#define CKEN_STUART (5) /* STUART Unit Clock Enable */ ++#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */ ++#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */ ++#define CKEN_SSP (3) /* SSP Unit Clock Enable */ ++#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */ ++#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */ ++#define CKEN_PWM1 (1) /* PWM1 Clock Enable */ ++#define CKEN_PWM0 (0) /* PWM0 Clock Enable */ ++ ++#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ ++#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ ++ ++ ++/* ++ * LCD ++ */ ++ ++#define LCCR0 __REG(0x44000000) /* LCD Controller Control Register 0 */ ++#define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */ ++#define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */ ++#define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */ ++#define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 3 */ ++#define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */ ++#define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */ ++#define LCSR __REG(0x44000038) /* LCD Controller Status Register */ ++#define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */ ++#define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */ ++#define TMEDCR __REG(0x44000044) /* TMED Control Register */ ++ ++#define LCCR3_1BPP (0 << 24) ++#define LCCR3_2BPP (1 << 24) ++#define LCCR3_4BPP (2 << 24) ++#define LCCR3_8BPP (3 << 24) ++#define LCCR3_16BPP (4 << 24) ++ ++#define LCCR3_PDFOR_0 (0 << 30) ++#define LCCR3_PDFOR_1 (1 << 30) ++#define LCCR3_PDFOR_2 (2 << 30) ++#define LCCR3_PDFOR_3 (3 << 30) ++ ++#define LCCR4_PAL_FOR_0 (0 << 15) ++#define LCCR4_PAL_FOR_1 (1 << 15) ++#define LCCR4_PAL_FOR_2 (2 << 15) ++#define LCCR4_PAL_FOR_MASK (3 << 15) ++ ++#define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */ ++#define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */ ++#define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */ ++#define LDCMD0 __REG(0x4400020C) /* DMA Channel 0 Command Register */ ++#define FDADR1 __REG(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */ ++#define FSADR1 __REG(0x44000214) /* DMA Channel 1 Frame Source Address Register */ ++#define FIDR1 __REG(0x44000218) /* DMA Channel 1 Frame ID Register */ ++#define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */ ++ ++#define LCCR0_ENB (1 << 0) /* LCD Controller enable */ ++#define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */ ++#define LCCR0_Color (LCCR0_CMS*0) /* Color display */ ++#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ ++#define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display */ ++ /* Select */ ++#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ ++#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ ++ ++#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */ ++#define LCCR0_SFM (1 << 4) /* Start of frame mask */ ++#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */ ++#define LCCR0_EFM (1 << 6) /* End of Frame mask */ ++#define LCCR0_PAS (1 << 7) /* Passive/Active display Select */ ++#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ ++#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ ++#define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome */ ++ /* display mode) */ ++#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */ ++ /* display */ ++#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */ ++ /* display */ ++#define LCCR0_DIS (1 << 10) /* LCD Disable */ ++#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */ ++#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */ ++#define LCCR0_PDD_S 12 ++#define LCCR0_BM (1 << 20) /* Branch mask */ ++#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ ++#define LCCR0_LCDT (1 << 22) /* LCD panel type */ ++#define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */ ++#define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */ ++#define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */ ++#define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */ ++ ++#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ ++#define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \ ++ (((Pixel) - 1) << FShft (LCCR1_PPL)) ++ ++#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ ++#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ ++ /* pulse Width [1..64 Tpix] */ \ ++ (((Tpix) - 1) << FShft (LCCR1_HSW)) ++ ++#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ ++ /* count - 1 [Tpix] */ ++#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ ++ /* [1..256 Tpix] */ \ ++ (((Tpix) - 1) << FShft (LCCR1_ELW)) ++ ++#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ ++ /* Wait count - 1 [Tpix] */ ++#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ ++ /* [1..256 Tpix] */ \ ++ (((Tpix) - 1) << FShft (LCCR1_BLW)) ++ ++ ++#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ ++#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ ++ (((Line) - 1) << FShft (LCCR2_LPP)) ++ ++#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ ++ /* Width - 1 [Tln] (L_FCLK) */ ++#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ ++ /* Width [1..64 Tln] */ \ ++ (((Tln) - 1) << FShft (LCCR2_VSW)) ++ ++#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ ++ /* count [Tln] */ ++#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ ++ /* [0..255 Tln] */ \ ++ ((Tln) << FShft (LCCR2_EFW)) ++ ++#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ ++ /* Wait count [Tln] */ ++#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ ++ /* [0..255 Tln] */ \ ++ ((Tln) << FShft (LCCR2_BFW)) ++ ++#if 0 ++#define LCCR3_PCD (0xff) /* Pixel clock divisor */ ++#define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */ ++#define LCCR3_ACB_S 8 ++#endif ++ ++#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ ++#define LCCR3_API_S 16 ++#define LCCR3_VSP (1 << 20) /* vertical sync polarity */ ++#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ ++#define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */ ++#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ ++#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ ++ ++#define LCCR3_OEP (1 << 23) /* Output Enable Polarity (L_BIAS, */ ++ /* active display mode) */ ++#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ ++#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ ++ ++#if 0 ++#define LCCR3_BPP (7 << 24) /* bits per pixel */ ++#define LCCR3_BPP_S 24 ++#endif ++#define LCCR3_DPC (1 << 27) /* double pixel clock mode */ ++ ++ ++#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ ++#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \ ++ (((Div) << FShft (LCCR3_PCD))) ++ ++ ++#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */ ++#define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \ ++ (((Bpp) << FShft (LCCR3_BPP))) ++ ++#define LCCR3_ACB Fld (8, 8) /* AC Bias */ ++#define LCCR3_Acb(Acb) /* BAC Bias */ \ ++ (((Acb) << FShft (LCCR3_ACB))) ++ ++#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ ++ /* pulse active High */ ++#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ ++ ++#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ ++ /* active High */ ++#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ ++ /* active Low */ ++ ++#define LCSR_LDD (1 << 0) /* LCD Disable Done */ ++#define LCSR_SOF (1 << 1) /* Start of frame */ ++#define LCSR_BER (1 << 2) /* Bus error */ ++#define LCSR_ABC (1 << 3) /* AC Bias count */ ++#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */ ++#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */ ++#define LCSR_OU (1 << 6) /* output FIFO underrun */ ++#define LCSR_QD (1 << 7) /* quick disable */ ++#define LCSR_EOF (1 << 8) /* end of frame */ ++#define LCSR_BS (1 << 9) /* branch status */ ++#define LCSR_SINT (1 << 10) /* subsequent interrupt */ ++ ++#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ ++ ++#define LCSR_LDD (1 << 0) /* LCD Disable Done */ ++#define LCSR_SOF (1 << 1) /* Start of frame */ ++#define LCSR_BER (1 << 2) /* Bus error */ ++#define LCSR_ABC (1 << 3) /* AC Bias count */ ++#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */ ++#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */ ++#define LCSR_OU (1 << 6) /* output FIFO underrun */ ++#define LCSR_QD (1 << 7) /* quick disable */ ++#define LCSR_EOF (1 << 8) /* end of frame */ ++#define LCSR_BS (1 << 9) /* branch status */ ++#define LCSR_SINT (1 << 10) /* subsequent interrupt */ ++ ++#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ ++ ++#ifdef CONFIG_PXA27x ++ ++/* ++ * Keypad ++ */ ++#define KPC __REG(0x41500000) /* Keypad Interface Control register */ ++#define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */ ++#define KPREC __REG(0x41500010) /* Keypad Interface Rotary Encoder register */ ++#define KPMK __REG(0x41500018) /* Keypad Interface Matrix Key register */ ++#define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */ ++#define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */ ++#define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */ ++#define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */ ++#define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */ ++#define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */ ++ ++#define KPC_AS (0x1 << 30) /* Automatic Scan bit */ ++#define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */ ++#define KPC_MI (0x1 << 22) /* Matrix interrupt bit */ ++#define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */ ++#define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */ ++#define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */ ++#define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */ ++#define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */ ++#define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */ ++#define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */ ++#define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */ ++#define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */ ++#define KPC_MS_ALL (KPC_MS0 | KPC_MS1 | KPC_MS2 | KPC_MS3 | KPC_MS4 | KPC_MS5 | KPC_MS6 | KPC_MS7) ++#define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */ ++#define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */ ++#define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Keypad Debounce Select */ ++#define KPC_DI (0x1 << 5) /* Direct key interrupt bit */ ++#define KPC_RE_ZERO_DEB (0x1 << 4) /* Rotary Encoder Zero Debounce */ ++#define KPC_REE1 (0x1 << 3) /* Rotary Encoder1 Enable */ ++#define KPC_REE0 (0x1 << 2) /* Rotary Encoder0 Enable */ ++#define KPC_DE (0x1 << 1) /* Direct Keypad Enable */ ++#define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */ ++ ++#define KPDK_DKP (0x1 << 31) ++#define KPDK_DK7 (0x1 << 7) ++#define KPDK_DK6 (0x1 << 6) ++#define KPDK_DK5 (0x1 << 5) ++#define KPDK_DK4 (0x1 << 4) ++#define KPDK_DK3 (0x1 << 3) ++#define KPDK_DK2 (0x1 << 2) ++#define KPDK_DK1 (0x1 << 1) ++#define KPDK_DK0 (0x1 << 0) ++ ++#define KPREC_OF1 (0x1 << 31) ++#define kPREC_UF1 (0x1 << 30) ++#define KPREC_OF0 (0x1 << 15) ++#define KPREC_UF0 (0x1 << 14) ++ ++#define KPMK_MKP (0x1 << 31) ++#define KPAS_SO (0x1 << 31) ++#define KPASMKPx_SO (0x1 << 31) ++ ++/* Camera Interface */ ++#define CICR0 __REG(0x50000000) ++#define CICR1 __REG(0x50000004) ++#define CICR2 __REG(0x50000008) ++#define CICR3 __REG(0x5000000C) ++#define CICR4 __REG(0x50000010) ++#define CISR __REG(0x50000014) ++#define CIFR __REG(0x50000018) ++#define CITOR __REG(0x5000001C) ++#define CIBR0 __REG(0x50000028) ++#define CIBR1 __REG(0x50000030) ++#define CIBR2 __REG(0x50000038) ++ ++#define CICR0_DMAEN (1 << 31) /* DMA request enable */ ++#define CICR0_PAR_EN (1 << 30) /* Parity enable */ ++#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */ ++#define CICR0_ENB (1 << 28) /* Camera interface enable */ ++#define CICR0_DIS (1 << 27) /* Camera interface disable */ ++#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ ++#define CICR0_TOM (1 << 9) /* Time-out mask */ ++#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ ++#define CICR0_FEM (1 << 7) /* FIFO-empty mask */ ++#define CICR0_EOLM (1 << 6) /* End-of-line mask */ ++#define CICR0_PERRM (1 << 5) /* Parity-error mask */ ++#define CICR0_QDM (1 << 4) /* Quick-disable mask */ ++#define CICR0_CDM (1 << 3) /* Disable-done mask */ ++#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */ ++#define CICR0_EOFM (1 << 1) /* End-of-frame mask */ ++#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */ ++ ++#define CICR1_TBIT (1 << 31) /* Transparency bit */ ++#define CICR1_RGBT_CONV (0x3 << 30) /* RGBT conversion mask */ ++#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */ ++#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */ ++#define CICR1_RGB_F (1 << 11) /* RGB format */ ++#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */ ++#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */ ++#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */ ++#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */ ++#define CICR1_DW (0x7 << 0) /* Data width mask */ ++ ++#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock ++ wait count mask */ ++#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock ++ wait count mask */ ++#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */ ++#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock ++ wait count mask */ ++#define CICR2_FSW (0x7 << 0) /* Frame stabilization ++ wait count mask */ ++ ++#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock ++ wait count mask */ ++#define CICR3_EFW (0xff << 16) /* End-of-frame line clock ++ wait count mask */ ++#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */ ++#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock ++ wait count mask */ ++#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */ ++ ++#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */ ++#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */ ++#define CICR4_PCP (1 << 22) /* Pixel clock polarity */ ++#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */ ++#define CICR4_VSP (1 << 20) /* Vertical sync polarity */ ++#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */ ++#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ ++#define CICR4_DIV (0xff << 0) /* Clock divisor mask */ ++ ++#define CISR_FTO (1 << 15) /* FIFO time-out */ ++#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ ++#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ ++#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */ ++#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */ ++#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */ ++#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */ ++#define CISR_EOL (1 << 8) /* End of line */ ++#define CISR_PAR_ERR (1 << 7) /* Parity error */ ++#define CISR_CQD (1 << 6) /* Camera interface quick disable */ ++#define CISR_CDD (1 << 5) /* Camera interface disable done */ ++#define CISR_SOF (1 << 4) /* Start of frame */ ++#define CISR_EOF (1 << 3) /* End of frame */ ++#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */ ++#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */ ++#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */ ++ ++#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */ ++#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */ ++#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */ ++#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */ ++#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */ ++#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */ ++#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */ ++#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */ ++ ++#define SRAM_SIZE 0x40000 /* 4x64K */ ++ ++#define SRAM_MEM_PHYS 0x5C000000 ++ ++#define IMPMCR __REG(0x58000000) /* IM Power Management Control Reg */ ++#define IMPMSR __REG(0x58000008) /* IM Power Management Status Reg */ ++ ++#define IMPMCR_PC3 (0x3 << 22) /* Bank 3 Power Control */ ++#define IMPMCR_PC3_RUN_MODE (0x0 << 22) /* Run mode */ ++#define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /* Standby mode */ ++#define IMPMCR_PC3_AUTO_MODE (0x3 << 22) /* Automatically controlled */ ++ ++#define IMPMCR_PC2 (0x3 << 20) /* Bank 2 Power Control */ ++#define IMPMCR_PC2_RUN_MODE (0x0 << 20) /* Run mode */ ++#define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /* Standby mode */ ++#define IMPMCR_PC2_AUTO_MODE (0x3 << 20) /* Automatically controlled */ ++ ++#define IMPMCR_PC1 (0x3 << 18) /* Bank 1 Power Control */ ++#define IMPMCR_PC1_RUN_MODE (0x0 << 18) /* Run mode */ ++#define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /* Standby mode */ ++#define IMPMCR_PC1_AUTO_MODE (0x3 << 18) /* Automatically controlled */ ++ ++#define IMPMCR_PC0 (0x3 << 16) /* Bank 0 Power Control */ ++#define IMPMCR_PC0_RUN_MODE (0x0 << 16) /* Run mode */ ++#define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /* Standby mode */ ++#define IMPMCR_PC0_AUTO_MODE (0x3 << 16) /* Automatically controlled */ ++ ++#define IMPMCR_AW3 (1 << 11) /* Bank 3 Automatic Wake-up enable */ ++#define IMPMCR_AW2 (1 << 10) /* Bank 2 Automatic Wake-up enable */ ++#define IMPMCR_AW1 (1 << 9) /* Bank 1 Automatic Wake-up enable */ ++#define IMPMCR_AW0 (1 << 8) /* Bank 0 Automatic Wake-up enable */ ++ ++#define IMPMCR_DST (0xFF << 0) /* Delay Standby Time, ms */ ++ ++#define IMPMSR_PS3 (0x3 << 6) /* Bank 3 Power Status: */ ++#define IMPMSR_PS3_RUN_MODE (0x0 << 6) /* Run mode */ ++#define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /* Standby mode */ ++ ++#define IMPMSR_PS2 (0x3 << 4) /* Bank 2 Power Status: */ ++#define IMPMSR_PS2_RUN_MODE (0x0 << 4) /* Run mode */ ++#define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /* Standby mode */ ++ ++#define IMPMSR_PS1 (0x3 << 2) /* Bank 1 Power Status: */ ++#define IMPMSR_PS1_RUN_MODE (0x0 << 2) /* Run mode */ ++#define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /* Standby mode */ ++ ++#define IMPMSR_PS0 (0x3 << 0) /* Bank 0 Power Status: */ ++#define IMPMSR_PS0_RUN_MODE (0x0 << 0) /* Run mode */ ++#define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /* Standby mode */ ++ ++#endif ++ ++#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) ++/* ++ * UHC: USB Host Controller (OHCI-like) register definitions ++ */ ++#define UHC_BASE_PHYS (0x4C000000) ++#define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */ ++#define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */ ++#define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */ ++#define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */ ++#define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */ ++#define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */ ++#define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */ ++#define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */ ++#define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */ ++#define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */ ++#define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */ ++#define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */ ++#define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */ ++#define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */ ++#define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */ ++#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */ ++#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */ ++#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */ ++ ++#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */ ++#define UHCRHDA_NOCP (1 << 12) /* No over current protection */ ++ ++#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */ ++#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */ ++#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */ ++#define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */ ++#define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */ ++ ++#define UHCSTAT __REG(0x4C000060) /* UHC Status Register */ ++#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */ ++#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/ ++#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/ ++#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */ ++#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */ ++#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */ ++#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */ ++#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */ ++#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */ ++ ++#define UHCHR __REG(0x4C000064) /* UHC Reset Register */ ++#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */ ++#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */ ++#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */ ++#define UHCHR_PCPL (1 << 7) /* Power control polarity low */ ++#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */ ++#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */ ++#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */ ++#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */ ++#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */ ++#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */ ++#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */ ++ ++#define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/ ++#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */ ++#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */ ++#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */ ++#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */ ++#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort ++ Interrupt Enable*/ ++#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */ ++#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */ ++ ++#define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */ ++ ++#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */ ++ ++/* PWRMODE register M field values */ ++ ++#define PWRMODE_IDLE 0x1 ++#define PWRMODE_STANDBY 0x2 ++#define PWRMODE_SLEEP 0x3 ++#define PWRMODE_DEEPSLEEP 0x7 ++ ++#endif +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/regs-ssp.h linux-2.6.25-rc4/include/asm-arm/arch/regs-ssp.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/regs-ssp.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/regs-ssp.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,113 @@ ++#ifndef __ASM_ARCH_REGS_SSP_H ++#define __ASM_ARCH_REGS_SSP_H ++ ++/* ++ * SSP Serial Port Registers ++ * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different. ++ * PXA255, PXA26x and PXA27x have extra ports, registers and bits. ++ */ ++ ++#define SSCR0 (0x00) /* SSP Control Register 0 */ ++#define SSCR1 (0x04) /* SSP Control Register 1 */ ++#define SSSR (0x08) /* SSP Status Register */ ++#define SSITR (0x0C) /* SSP Interrupt Test Register */ ++#define SSDR (0x10) /* SSP Data Write/Data Read Register */ ++ ++#define SSTO (0x28) /* SSP Time Out Register */ ++#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */ ++#define SSTSA (0x30) /* SSP Tx Timeslot Active */ ++#define SSRSA (0x34) /* SSP Rx Timeslot Active */ ++#define SSTSS (0x38) /* SSP Timeslot Status */ ++#define SSACD (0x3C) /* SSP Audio Clock Divider */ ++ ++/* Common PXA2xx bits first */ ++#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ ++#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ ++#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */ ++#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */ ++#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */ ++#define SSCR0_National (0x2 << 4) /* National Microwire */ ++#define SSCR0_ECS (1 << 6) /* External clock select */ ++#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ ++#if defined(CONFIG_PXA25x) ++#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ ++#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ ++#elif defined(CONFIG_PXA27x) ++#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ ++#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ ++#define SSCR0_EDSS (1 << 20) /* Extended data size select */ ++#define SSCR0_NCS (1 << 21) /* Network clock select */ ++#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */ ++#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ ++#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ ++#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ ++#define SSCR0_ADC (1 << 30) /* Audio clock select */ ++#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ ++#endif ++ ++#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ ++#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ ++#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ ++#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */ ++#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ ++#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ ++#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */ ++#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */ ++#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */ ++#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ ++ ++#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ ++#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ ++#define SSSR_BSY (1 << 4) /* SSP Busy */ ++#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ ++#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ ++#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ ++ ++#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */ ++#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */ ++#define SSCR0_NCS (1 << 21) /* Network Clock Select */ ++#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */ ++ ++/* extra bits in PXA255, PXA26x and PXA27x SSP ports */ ++#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */ ++#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */ ++#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */ ++#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */ ++#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */ ++#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */ ++#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */ ++#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */ ++#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */ ++#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */ ++#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */ ++#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */ ++#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */ ++#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */ ++#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */ ++#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */ ++#define SSCR1_IFS (1 << 16) /* Invert Frame Signal */ ++#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */ ++#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */ ++ ++#define SSSR_BCE (1 << 23) /* Bit Count Error */ ++#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */ ++#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */ ++#define SSSR_EOC (1 << 20) /* End Of Chain */ ++#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ ++#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ ++ ++#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ ++#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ ++#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ ++#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */ ++#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */ ++#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */ ++#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */ ++#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */ ++#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */ ++ ++#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */ ++#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ ++#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ ++ ++#endif /* __ASM_ARCH_REGS_SSP_H */ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/sharpsl.h linux-2.6.25-rc4/include/asm-arm/arch/sharpsl.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/sharpsl.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/sharpsl.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,34 @@ ++/* ++ * SharpSL SSP Driver ++ */ ++ ++unsigned long corgi_ssp_ads7846_putget(unsigned long); ++unsigned long corgi_ssp_ads7846_get(void); ++void corgi_ssp_ads7846_put(unsigned long data); ++void corgi_ssp_ads7846_lock(void); ++void corgi_ssp_ads7846_unlock(void); ++void corgi_ssp_lcdtg_send (unsigned char adrs, unsigned char data); ++void corgi_ssp_blduty_set(int duty); ++int corgi_ssp_max1111_get(unsigned long data); ++ ++/* ++ * SharpSL Touchscreen Driver ++ */ ++ ++struct corgits_machinfo { ++ unsigned long (*get_hsync_invperiod)(void); ++ void (*put_hsync)(void); ++ void (*wait_hsync)(void); ++}; ++ ++ ++/* ++ * SharpSL Backlight ++ */ ++extern void corgibl_limit_intensity(int limit); ++ ++ ++/* ++ * SharpSL Battery/PM Driver ++ */ ++extern void sharpsl_battery_kick(void); +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/spitz.h linux-2.6.25-rc4/include/asm-arm/arch/spitz.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/spitz.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/spitz.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,158 @@ ++/* ++ * Hardware specific definitions for SL-Cx000 series of PDAs ++ * ++ * Copyright (c) 2005 Alexander Wykes ++ * Copyright (c) 2005 Richard Purdie ++ * ++ * Based on Sharp's 2.4 kernel patches ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++#ifndef __ASM_ARCH_SPITZ_H ++#define __ASM_ARCH_SPITZ_H 1 ++#endif ++ ++#include <linux/fb.h> ++ ++/* Spitz/Akita GPIOs */ ++ ++#define SPITZ_GPIO_KEY_INT (0) /* Key Interrupt */ ++#define SPITZ_GPIO_RESET (1) ++#define SPITZ_GPIO_nSD_DETECT (9) ++#define SPITZ_GPIO_TP_INT (11) /* Touch Panel interrupt */ ++#define SPITZ_GPIO_AK_INT (13) /* Remote Control */ ++#define SPITZ_GPIO_ADS7846_CS (14) ++#define SPITZ_GPIO_SYNC (16) ++#define SPITZ_GPIO_MAX1111_CS (20) ++#define SPITZ_GPIO_FATAL_BAT (21) ++#define SPITZ_GPIO_HSYNC (22) ++#define SPITZ_GPIO_nSD_CLK (32) ++#define SPITZ_GPIO_USB_DEVICE (35) ++#define SPITZ_GPIO_USB_HOST (37) ++#define SPITZ_GPIO_USB_CONNECT (41) ++#define SPITZ_GPIO_LCDCON_CS (53) ++#define SPITZ_GPIO_nPCE (54) ++#define SPITZ_GPIO_nSD_WP (81) ++#define SPITZ_GPIO_ON_RESET (89) ++#define SPITZ_GPIO_BAT_COVER (90) ++#define SPITZ_GPIO_CF_CD (94) ++#define SPITZ_GPIO_ON_KEY (95) ++#define SPITZ_GPIO_SWA (97) ++#define SPITZ_GPIO_SWB (96) ++#define SPITZ_GPIO_CHRG_FULL (101) ++#define SPITZ_GPIO_CO (101) ++#define SPITZ_GPIO_CF_IRQ (105) ++#define SPITZ_GPIO_AC_IN (115) ++#define SPITZ_GPIO_HP_IN (116) ++ ++/* Spitz Only GPIOs */ ++ ++#define SPITZ_GPIO_CF2_IRQ (106) /* CF slot1 Ready */ ++#define SPITZ_GPIO_CF2_CD (93) ++ ++ ++/* Spitz/Akita Keyboard Definitions */ ++ ++#define SPITZ_KEY_STROBE_NUM (11) ++#define SPITZ_KEY_SENSE_NUM (7) ++#define SPITZ_GPIO_G0_STROBE_BIT 0x0f800000 ++#define SPITZ_GPIO_G1_STROBE_BIT 0x00100000 ++#define SPITZ_GPIO_G2_STROBE_BIT 0x01000000 ++#define SPITZ_GPIO_G3_STROBE_BIT 0x00041880 ++#define SPITZ_GPIO_G0_SENSE_BIT 0x00021000 ++#define SPITZ_GPIO_G1_SENSE_BIT 0x000000d4 ++#define SPITZ_GPIO_G2_SENSE_BIT 0x08000000 ++#define SPITZ_GPIO_G3_SENSE_BIT 0x00000000 ++ ++#define SPITZ_GPIO_KEY_STROBE0 88 ++#define SPITZ_GPIO_KEY_STROBE1 23 ++#define SPITZ_GPIO_KEY_STROBE2 24 ++#define SPITZ_GPIO_KEY_STROBE3 25 ++#define SPITZ_GPIO_KEY_STROBE4 26 ++#define SPITZ_GPIO_KEY_STROBE5 27 ++#define SPITZ_GPIO_KEY_STROBE6 52 ++#define SPITZ_GPIO_KEY_STROBE7 103 ++#define SPITZ_GPIO_KEY_STROBE8 107 ++#define SPITZ_GPIO_KEY_STROBE9 108 ++#define SPITZ_GPIO_KEY_STROBE10 114 ++ ++#define SPITZ_GPIO_KEY_SENSE0 12 ++#define SPITZ_GPIO_KEY_SENSE1 17 ++#define SPITZ_GPIO_KEY_SENSE2 91 ++#define SPITZ_GPIO_KEY_SENSE3 34 ++#define SPITZ_GPIO_KEY_SENSE4 36 ++#define SPITZ_GPIO_KEY_SENSE5 38 ++#define SPITZ_GPIO_KEY_SENSE6 39 ++ ++ ++/* Spitz Scoop Device (No. 1) GPIOs */ ++/* Suspend States in comments */ ++#define SPITZ_SCP_LED_GREEN SCOOP_GPCR_PA11 /* Keep */ ++#define SPITZ_SCP_JK_B SCOOP_GPCR_PA12 /* Keep */ ++#define SPITZ_SCP_CHRG_ON SCOOP_GPCR_PA13 /* Keep */ ++#define SPITZ_SCP_MUTE_L SCOOP_GPCR_PA14 /* Low */ ++#define SPITZ_SCP_MUTE_R SCOOP_GPCR_PA15 /* Low */ ++#define SPITZ_SCP_CF_POWER SCOOP_GPCR_PA16 /* Keep */ ++#define SPITZ_SCP_LED_ORANGE SCOOP_GPCR_PA17 /* Keep */ ++#define SPITZ_SCP_JK_A SCOOP_GPCR_PA18 /* Low */ ++#define SPITZ_SCP_ADC_TEMP_ON SCOOP_GPCR_PA19 /* Low */ ++ ++#define SPITZ_SCP_IO_DIR (SPITZ_SCP_LED_GREEN | SPITZ_SCP_JK_B | SPITZ_SCP_CHRG_ON | \ ++ SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_LED_ORANGE | \ ++ SPITZ_SCP_CF_POWER | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON) ++#define SPITZ_SCP_IO_OUT (SPITZ_SCP_CHRG_ON | SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R) ++#define SPITZ_SCP_SUS_CLR (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON) ++#define SPITZ_SCP_SUS_SET 0 ++ ++/* Spitz Scoop Device (No. 2) GPIOs */ ++/* Suspend States in comments */ ++#define SPITZ_SCP2_IR_ON SCOOP_GPCR_PA11 /* High */ ++#define SPITZ_SCP2_AKIN_PULLUP SCOOP_GPCR_PA12 /* Keep */ ++#define SPITZ_SCP2_RESERVED_1 SCOOP_GPCR_PA13 /* High */ ++#define SPITZ_SCP2_RESERVED_2 SCOOP_GPCR_PA14 /* Low */ ++#define SPITZ_SCP2_RESERVED_3 SCOOP_GPCR_PA15 /* Low */ ++#define SPITZ_SCP2_RESERVED_4 SCOOP_GPCR_PA16 /* Low */ ++#define SPITZ_SCP2_BACKLIGHT_CONT SCOOP_GPCR_PA17 /* Low */ ++#define SPITZ_SCP2_BACKLIGHT_ON SCOOP_GPCR_PA18 /* Low */ ++#define SPITZ_SCP2_MIC_BIAS SCOOP_GPCR_PA19 /* Low */ ++ ++#define SPITZ_SCP2_IO_DIR (SPITZ_SCP2_IR_ON | SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1 | \ ++ SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \ ++ SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS) ++ ++#define SPITZ_SCP2_IO_OUT (SPITZ_SCP2_IR_ON | SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1) ++#define SPITZ_SCP2_SUS_CLR (SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \ ++ SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS) ++#define SPITZ_SCP2_SUS_SET (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1) ++ ++ ++/* Spitz IRQ Definitions */ ++ ++#define SPITZ_IRQ_GPIO_KEY_INT IRQ_GPIO(SPITZ_GPIO_KEY_INT) ++#define SPITZ_IRQ_GPIO_AC_IN IRQ_GPIO(SPITZ_GPIO_AC_IN) ++#define SPITZ_IRQ_GPIO_AK_INT IRQ_GPIO(SPITZ_GPIO_AK_INT) ++#define SPITZ_IRQ_GPIO_HP_IN IRQ_GPIO(SPITZ_GPIO_HP_IN) ++#define SPITZ_IRQ_GPIO_TP_INT IRQ_GPIO(SPITZ_GPIO_TP_INT) ++#define SPITZ_IRQ_GPIO_SYNC IRQ_GPIO(SPITZ_GPIO_SYNC) ++#define SPITZ_IRQ_GPIO_ON_KEY IRQ_GPIO(SPITZ_GPIO_ON_KEY) ++#define SPITZ_IRQ_GPIO_SWA IRQ_GPIO(SPITZ_GPIO_SWA) ++#define SPITZ_IRQ_GPIO_SWB IRQ_GPIO(SPITZ_GPIO_SWB) ++#define SPITZ_IRQ_GPIO_BAT_COVER IRQ_GPIO(SPITZ_GPIO_BAT_COVER) ++#define SPITZ_IRQ_GPIO_FATAL_BAT IRQ_GPIO(SPITZ_GPIO_FATAL_BAT) ++#define SPITZ_IRQ_GPIO_CO IRQ_GPIO(SPITZ_GPIO_CO) ++#define SPITZ_IRQ_GPIO_CF_IRQ IRQ_GPIO(SPITZ_GPIO_CF_IRQ) ++#define SPITZ_IRQ_GPIO_CF_CD IRQ_GPIO(SPITZ_GPIO_CF_CD) ++#define SPITZ_IRQ_GPIO_CF2_IRQ IRQ_GPIO(SPITZ_GPIO_CF2_IRQ) ++#define SPITZ_IRQ_GPIO_nSD_INT IRQ_GPIO(SPITZ_GPIO_nSD_INT) ++#define SPITZ_IRQ_GPIO_nSD_DETECT IRQ_GPIO(SPITZ_GPIO_nSD_DETECT) ++ ++/* ++ * Shared data structures ++ */ ++extern struct platform_device spitzscoop_device; ++extern struct platform_device spitzscoop2_device; ++extern struct platform_device spitzssp_device; ++extern struct sharpsl_charger_machinfo spitz_pm_machinfo; +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/ssp.h linux-2.6.25-rc4/include/asm-arm/arch/ssp.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/ssp.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/ssp.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,83 @@ ++/* ++ * ssp.h ++ * ++ * Copyright (C) 2003 Russell King, All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This driver supports the following PXA CPU/SSP ports:- ++ * ++ * PXA250 SSP ++ * PXA255 SSP, NSSP ++ * PXA26x SSP, NSSP, ASSP ++ * PXA27x SSP1, SSP2, SSP3 ++ * PXA3xx SSP1, SSP2, SSP3, SSP4 ++ */ ++ ++#ifndef __ASM_ARCH_SSP_H ++#define __ASM_ARCH_SSP_H ++ ++#include <linux/list.h> ++ ++enum pxa_ssp_type { ++ SSP_UNDEFINED = 0, ++ PXA25x_SSP, /* pxa 210, 250, 255, 26x */ ++ PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */ ++ PXA27x_SSP, ++}; ++ ++struct ssp_device { ++ struct platform_device *pdev; ++ struct list_head node; ++ ++ struct clk *clk; ++ void __iomem *mmio_base; ++ unsigned long phys_base; ++ ++ const char *label; ++ int port_id; ++ int type; ++ int use_count; ++ int irq; ++ int drcmr_rx; ++ int drcmr_tx; ++}; ++ ++/* ++ * SSP initialisation flags ++ */ ++#define SSP_NO_IRQ 0x1 /* don't register an irq handler in SSP driver */ ++ ++struct ssp_state { ++ u32 cr0; ++ u32 cr1; ++ u32 to; ++ u32 psp; ++}; ++ ++struct ssp_dev { ++ struct ssp_device *ssp; ++ u32 port; ++ u32 mode; ++ u32 flags; ++ u32 psp_flags; ++ u32 speed; ++ int irq; ++}; ++ ++int ssp_write_word(struct ssp_dev *dev, u32 data); ++int ssp_read_word(struct ssp_dev *dev, u32 *data); ++int ssp_flush(struct ssp_dev *dev); ++void ssp_enable(struct ssp_dev *dev); ++void ssp_disable(struct ssp_dev *dev); ++void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp); ++void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp); ++int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags); ++int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed); ++void ssp_exit(struct ssp_dev *dev); ++ ++struct ssp_device *ssp_request(int port, const char *label); ++void ssp_free(struct ssp_device *); ++#endif /* __ASM_ARCH_SSP_H */ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/system.h linux-2.6.25-rc4/include/asm-arm/arch/system.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/system.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/system.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,35 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/system.h ++ * ++ * Author: Nicolas Pitre ++ * Created: Jun 15, 2001 ++ * Copyright: MontaVista Software Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include <asm/proc-fns.h> ++#include "hardware.h" ++#include "pxa-regs.h" ++ ++static inline void arch_idle(void) ++{ ++ cpu_do_idle(); ++} ++ ++ ++static inline void arch_reset(char mode) ++{ ++ if (mode == 's') { ++ /* Jump into ROM at address 0 */ ++ cpu_reset(0); ++ } else { ++ /* Initialize the watchdog and let it fire */ ++ OWER = OWER_WME; ++ OSSR = OSSR_M3; ++ OSMR3 = OSCR + 368640; /* ... in 100 ms */ ++ } ++} ++ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/timex.h linux-2.6.25-rc4/include/asm-arm/arch/timex.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/timex.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/timex.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,26 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/timex.h ++ * ++ * Author: Nicolas Pitre ++ * Created: Jun 15, 2001 ++ * Copyright: MontaVista Software Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++ ++#if defined(CONFIG_PXA25x) ++/* PXA250/210 timer base */ ++#define CLOCK_TICK_RATE 3686400 ++#elif defined(CONFIG_PXA27x) ++/* PXA27x timer base */ ++#ifdef CONFIG_MACH_MAINSTONE ++#define CLOCK_TICK_RATE 3249600 ++#else ++#define CLOCK_TICK_RATE 3250000 ++#endif ++#else ++#define CLOCK_TICK_RATE 3250000 ++#endif +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/tosa.h linux-2.6.25-rc4/include/asm-arm/arch/tosa.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/tosa.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/tosa.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,196 @@ ++/* ++ * Hardware specific definitions for Sharp SL-C6000x series of PDAs ++ * ++ * Copyright (c) 2005 Dirk Opfer ++ * ++ * Based on Sharp's 2.4 kernel patches ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++#ifndef _ASM_ARCH_TOSA_H_ ++#define _ASM_ARCH_TOSA_H_ 1 ++ ++/* TOSA Chip selects */ ++#define TOSA_LCDC_PHYS PXA_CS4_PHYS ++/* Internel Scoop */ ++#define TOSA_CF_PHYS (PXA_CS2_PHYS + 0x00800000) ++/* Jacket Scoop */ ++#define TOSA_SCOOP_PHYS (PXA_CS5_PHYS + 0x00800000) ++ ++/* ++ * SCOOP2 internal GPIOs ++ */ ++#define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11 ++#define TOSA_SCOOP_TC6393_REST_IN SCOOP_GPCR_PA12 ++#define TOSA_SCOOP_IR_POWERDWN SCOOP_GPCR_PA13 ++#define TOSA_SCOOP_SD_WP SCOOP_GPCR_PA14 ++#define TOSA_SCOOP_PWR_ON SCOOP_GPCR_PA15 ++#define TOSA_SCOOP_AUD_PWR_ON SCOOP_GPCR_PA16 ++#define TOSA_SCOOP_BT_RESET SCOOP_GPCR_PA17 ++#define TOSA_SCOOP_BT_PWR_EN SCOOP_GPCR_PA18 ++#define TOSA_SCOOP_AC_IN_OL SCOOP_GPCR_PA19 ++ ++/* GPIO Direction 1 : output mode / 0:input mode */ ++#define TOSA_SCOOP_IO_DIR ( TOSA_SCOOP_PXA_VCORE1 | TOSA_SCOOP_TC6393_REST_IN | \ ++ TOSA_SCOOP_IR_POWERDWN | TOSA_SCOOP_PWR_ON | TOSA_SCOOP_AUD_PWR_ON |\ ++ TOSA_SCOOP_BT_RESET | TOSA_SCOOP_BT_PWR_EN ) ++/* GPIO out put level when init 1: Hi */ ++#define TOSA_SCOOP_IO_OUT ( TOSA_SCOOP_TC6393_REST_IN ) ++ ++/* ++ * SCOOP2 jacket GPIOs ++ */ ++#define TOSA_SCOOP_JC_BT_LED SCOOP_GPCR_PA11 ++#define TOSA_SCOOP_JC_NOTE_LED SCOOP_GPCR_PA12 ++#define TOSA_SCOOP_JC_CHRG_ERR_LED SCOOP_GPCR_PA13 ++#define TOSA_SCOOP_JC_USB_PULLUP SCOOP_GPCR_PA14 ++#define TOSA_SCOOP_JC_TC6393_SUSPEND SCOOP_GPCR_PA15 ++#define TOSA_SCOOP_JC_TC3693_L3V_ON SCOOP_GPCR_PA16 ++#define TOSA_SCOOP_JC_WLAN_DETECT SCOOP_GPCR_PA17 ++#define TOSA_SCOOP_JC_WLAN_LED SCOOP_GPCR_PA18 ++#define TOSA_SCOOP_JC_CARD_LIMIT_SEL SCOOP_GPCR_PA19 ++ ++/* GPIO Direction 1 : output mode / 0:input mode */ ++#define TOSA_SCOOP_JC_IO_DIR ( TOSA_SCOOP_JC_BT_LED | TOSA_SCOOP_JC_NOTE_LED | \ ++ TOSA_SCOOP_JC_CHRG_ERR_LED | TOSA_SCOOP_JC_USB_PULLUP | \ ++ TOSA_SCOOP_JC_TC6393_SUSPEND | TOSA_SCOOP_JC_TC3693_L3V_ON | \ ++ TOSA_SCOOP_JC_WLAN_LED | TOSA_SCOOP_JC_CARD_LIMIT_SEL ) ++/* GPIO out put level when init 1: Hi */ ++#define TOSA_SCOOP_JC_IO_OUT ( 0 ) ++ ++/* ++ * Timing Generator ++ */ ++#define TG_PNLCTL 0x00 ++#define TG_TPOSCTL 0x01 ++#define TG_DUTYCTL 0x02 ++#define TG_GPOSR 0x03 ++#define TG_GPODR1 0x04 ++#define TG_GPODR2 0x05 ++#define TG_PINICTL 0x06 ++#define TG_HPOSCTL 0x07 ++ ++/* ++ * LED ++ */ ++#define TOSA_SCOOP_LED_BLUE TOSA_SCOOP_GPCR_PA11 ++#define TOSA_SCOOP_LED_GREEN TOSA_SCOOP_GPCR_PA12 ++#define TOSA_SCOOP_LED_ORANGE TOSA_SCOOP_GPCR_PA13 ++#define TOSA_SCOOP_LED_WLAN TOSA_SCOOP_GPCR_PA18 ++ ++ ++/* ++ * PXA GPIOs ++ */ ++#define TOSA_GPIO_POWERON (0) ++#define TOSA_GPIO_RESET (1) ++#define TOSA_GPIO_AC_IN (2) ++#define TOSA_GPIO_RECORD_BTN (3) ++#define TOSA_GPIO_SYNC (4) /* Cradle SYNC Button */ ++#define TOSA_GPIO_USB_IN (5) ++#define TOSA_GPIO_JACKET_DETECT (7) ++#define TOSA_GPIO_nSD_DETECT (9) ++#define TOSA_GPIO_nSD_INT (10) ++#define TOSA_GPIO_TC6393_CLK (11) ++#define TOSA_GPIO_BAT1_CRG (12) ++#define TOSA_GPIO_CF_CD (13) ++#define TOSA_GPIO_BAT0_CRG (14) ++#define TOSA_GPIO_TC6393_INT (15) ++#define TOSA_GPIO_BAT0_LOW (17) ++#define TOSA_GPIO_TC6393_RDY (18) ++#define TOSA_GPIO_ON_RESET (19) ++#define TOSA_GPIO_EAR_IN (20) ++#define TOSA_GPIO_CF_IRQ (21) /* CF slot0 Ready */ ++#define TOSA_GPIO_ON_KEY (22) ++#define TOSA_GPIO_VGA_LINE (27) ++#define TOSA_GPIO_TP_INT (32) /* Touch Panel pen down interrupt */ ++#define TOSA_GPIO_JC_CF_IRQ (36) /* CF slot1 Ready */ ++#define TOSA_GPIO_BAT_LOCKED (38) /* Battery locked */ ++#define TOSA_GPIO_TG_SPI_SCLK (81) ++#define TOSA_GPIO_TG_SPI_CS (82) ++#define TOSA_GPIO_TG_SPI_MOSI (83) ++#define TOSA_GPIO_BAT1_LOW (84) ++ ++#define TOSA_GPIO_HP_IN GPIO_EAR_IN ++ ++#define TOSA_GPIO_MAIN_BAT_LOW GPIO_BAT0_LOW ++ ++#define TOSA_KEY_STROBE_NUM (11) ++#define TOSA_KEY_SENSE_NUM (7) ++ ++#define TOSA_GPIO_HIGH_STROBE_BIT (0xfc000000) ++#define TOSA_GPIO_LOW_STROBE_BIT (0x0000001f) ++#define TOSA_GPIO_ALL_SENSE_BIT (0x00000fe0) ++#define TOSA_GPIO_ALL_SENSE_RSHIFT (5) ++#define TOSA_GPIO_STROBE_BIT(a) GPIO_bit(58+(a)) ++#define TOSA_GPIO_SENSE_BIT(a) GPIO_bit(69+(a)) ++#define TOSA_GAFR_HIGH_STROBE_BIT (0xfff00000) ++#define TOSA_GAFR_LOW_STROBE_BIT (0x000003ff) ++#define TOSA_GAFR_ALL_SENSE_BIT (0x00fffc00) ++#define TOSA_GPIO_KEY_SENSE(a) (69+(a)) ++#define TOSA_GPIO_KEY_STROBE(a) (58+(a)) ++ ++/* ++ * Interrupts ++ */ ++#define TOSA_IRQ_GPIO_WAKEUP IRQ_GPIO(TOSA_GPIO_WAKEUP) ++#define TOSA_IRQ_GPIO_AC_IN IRQ_GPIO(TOSA_GPIO_AC_IN) ++#define TOSA_IRQ_GPIO_RECORD_BTN IRQ_GPIO(TOSA_GPIO_RECORD_BTN) ++#define TOSA_IRQ_GPIO_SYNC IRQ_GPIO(TOSA_GPIO_SYNC) ++#define TOSA_IRQ_GPIO_USB_IN IRQ_GPIO(TOSA_GPIO_USB_IN) ++#define TOSA_IRQ_GPIO_JACKET_DETECT IRQ_GPIO(TOSA_GPIO_JACKET_DETECT) ++#define TOSA_IRQ_GPIO_nSD_INT IRQ_GPIO(TOSA_GPIO_nSD_INT) ++#define TOSA_IRQ_GPIO_nSD_DETECT IRQ_GPIO(TOSA_GPIO_nSD_DETECT) ++#define TOSA_IRQ_GPIO_BAT1_CRG IRQ_GPIO(TOSA_GPIO_BAT1_CRG) ++#define TOSA_IRQ_GPIO_CF_CD IRQ_GPIO(TOSA_GPIO_CF_CD) ++#define TOSA_IRQ_GPIO_BAT0_CRG IRQ_GPIO(TOSA_GPIO_BAT0_CRG) ++#define TOSA_IRQ_GPIO_TC6393_INT IRQ_GPIO(TOSA_GPIO_TC6393_INT) ++#define TOSA_IRQ_GPIO_BAT0_LOW IRQ_GPIO(TOSA_GPIO_BAT0_LOW) ++#define TOSA_IRQ_GPIO_EAR_IN IRQ_GPIO(TOSA_GPIO_EAR_IN) ++#define TOSA_IRQ_GPIO_CF_IRQ IRQ_GPIO(TOSA_GPIO_CF_IRQ) ++#define TOSA_IRQ_GPIO_ON_KEY IRQ_GPIO(TOSA_GPIO_ON_KEY) ++#define TOSA_IRQ_GPIO_VGA_LINE IRQ_GPIO(TOSA_GPIO_VGA_LINE) ++#define TOSA_IRQ_GPIO_TP_INT IRQ_GPIO(TOSA_GPIO_TP_INT) ++#define TOSA_IRQ_GPIO_JC_CF_IRQ IRQ_GPIO(TOSA_GPIO_JC_CF_IRQ) ++#define TOSA_IRQ_GPIO_BAT_LOCKED IRQ_GPIO(TOSA_GPIO_BAT_LOCKED) ++#define TOSA_IRQ_GPIO_BAT1_LOW IRQ_GPIO(TOSA_GPIO_BAT1_LOW) ++#define TOSA_IRQ_GPIO_KEY_SENSE(a) IRQ_GPIO(69+(a)) ++ ++#define TOSA_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(TOSA_GPIO_MAIN_BAT_LOW) ++ ++extern struct platform_device tosascoop_jc_device; ++extern struct platform_device tosascoop_device; ++ ++#define TOSA_KEY_SYNC KEY_102ND /* ??? */ ++ ++ ++#ifndef CONFIG_KEYBOARD_TOSA_USE_EXT_KEYCODES ++#define TOSA_KEY_RECORD KEY_YEN ++#define TOSA_KEY_ADDRESSBOOK KEY_KATAKANA ++#define TOSA_KEY_CANCEL KEY_ESC ++#define TOSA_KEY_CENTER KEY_HIRAGANA ++#define TOSA_KEY_OK KEY_HENKAN ++#define TOSA_KEY_CALENDAR KEY_KATAKANAHIRAGANA ++#define TOSA_KEY_HOMEPAGE KEY_HANGEUL ++#define TOSA_KEY_LIGHT KEY_MUHENKAN ++#define TOSA_KEY_MENU KEY_HANJA ++#define TOSA_KEY_FN KEY_RIGHTALT ++#define TOSA_KEY_MAIL KEY_ZENKAKUHANKAKU ++#else ++#define TOSA_KEY_RECORD KEY_RECORD ++#define TOSA_KEY_ADDRESSBOOK KEY_ADDRESSBOOK ++#define TOSA_KEY_CANCEL KEY_CANCEL ++#define TOSA_KEY_CENTER KEY_SELECT /* ??? */ ++#define TOSA_KEY_OK KEY_OK ++#define TOSA_KEY_CALENDAR KEY_CALENDAR ++#define TOSA_KEY_HOMEPAGE KEY_HOMEPAGE ++#define TOSA_KEY_LIGHT KEY_KBDILLUMTOGGLE ++#define TOSA_KEY_MENU KEY_MENU ++#define TOSA_KEY_FN KEY_FN ++#define TOSA_KEY_MAIL KEY_MAIL ++#endif ++ ++#endif /* _ASM_ARCH_TOSA_H_ */ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/trizeps4.h linux-2.6.25-rc4/include/asm-arm/arch/trizeps4.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/trizeps4.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/trizeps4.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,106 @@ ++/************************************************************************ ++ * Include file for TRIZEPS4 SoM and ConXS eval-board ++ * Copyright (c) Jürgen Schindele ++ * 2006 ++ ************************************************************************/ ++ ++/* ++ * Includes/Defines ++ */ ++#ifndef _TRIPEPS4_H_ ++#define _TRIPEPS4_H_ ++ ++/* physical memory regions */ ++#define TRIZEPS4_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */ ++#define TRIZEPS4_DISK_PHYS (PXA_CS1_PHYS) /* Disk On Chip region */ ++#define TRIZEPS4_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */ ++#define TRIZEPS4_PIC_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board */ ++#define TRIZEPS4_SDRAM_BASE 0xa0000000 /* SDRAM region */ ++ ++#define TRIZEPS4_CFSR_PHYS (PXA_CS3_PHYS) /* Logic chip on ConXS-Board CSFR register */ ++#define TRIZEPS4_BOCR_PHYS (PXA_CS3_PHYS+0x02000000) /* Logic chip on ConXS-Board BOCR register */ ++#define TRIZEPS4_IRCR_PHYS (PXA_CS3_PHYS+0x02400000) /* Logic chip on ConXS-Board IRCR register*/ ++#define TRIZEPS4_UPSR_PHYS (PXA_CS3_PHYS+0x02800000) /* Logic chip on ConXS-Board UPSR register*/ ++#define TRIZEPS4_DICR_PHYS (PXA_CS3_PHYS+0x03800000) /* Logic chip on ConXS-Board DICR register*/ ++ ++/* virtual memory regions */ ++#define TRIZEPS4_DISK_VIRT 0xF0000000 /* Disk On Chip region */ ++ ++#define TRIZEPS4_PIC_VIRT 0xF0100000 /* not used */ ++#define TRIZEPS4_CFSR_VIRT 0xF0100000 ++#define TRIZEPS4_BOCR_VIRT 0xF0200000 ++#define TRIZEPS4_DICR_VIRT 0xF0300000 ++#define TRIZEPS4_IRCR_VIRT 0xF0400000 ++#define TRIZEPS4_UPSR_VIRT 0xF0500000 ++ ++/* size of flash */ ++#define TRIZEPS4_FLASH_SIZE 0x02000000 /* Flash size 32 MB */ ++ ++/* Ethernet Controller Davicom DM9000 */ ++#define GPIO_DM9000 101 ++#define TRIZEPS4_ETH_IRQ IRQ_GPIO(GPIO_DM9000) ++ ++/* UCB1400 audio / TS-controller */ ++#define GPIO_UCB1400 1 ++#define TRIZEPS4_UCB1400_IRQ IRQ_GPIO(GPIO_UCB1400) ++ ++/* PCMCIA socket Compact Flash */ ++#define GPIO_PCD 11 /* PCMCIA Card Detect */ ++#define TRIZEPS4_CD_IRQ IRQ_GPIO(GPIO_PCD) ++#define GPIO_PRDY 13 /* READY / nINT */ ++#define TRIZEPS4_READY_NINT IRQ_GPIO(GPIO_PRDY) ++ ++/* MMC socket */ ++#define GPIO_MMC_DET 12 ++#define TRIZEPS4_MMC_IRQ IRQ_GPIO(GPIO_MMC_DET) ++ ++/* LEDS using tx2 / rx2 */ ++#define GPIO_SYS_BUSY_LED 46 ++#define GPIO_HEARTBEAT_LED 47 ++ ++/* Off-module PIC on ConXS board */ ++#define GPIO_PIC 0 ++#define TRIZEPS4_PIC_IRQ IRQ_GPIO(GPIO_PIC) ++ ++#define CFSR_P2V(x) ((x) - TRIZEPS4_CFSR_PHYS + TRIZEPS4_CFSR_VIRT) ++#define CFSR_V2P(x) ((x) - TRIZEPS4_CFSR_VIRT + TRIZEPS4_CFSR_PHYS) ++ ++#define BCR_P2V(x) ((x) - TRIZEPS4_BOCR_PHYS + TRIZEPS4_BOCR_VIRT) ++#define BCR_V2P(x) ((x) - TRIZEPS4_BOCR_VIRT + TRIZEPS4_BOCR_PHYS) ++ ++#define DCR_P2V(x) ((x) - TRIZEPS4_DICR_PHYS + TRIZEPS4_DICR_VIRT) ++#define DCR_V2P(x) ((x) - TRIZEPS4_DICR_VIRT + TRIZEPS4_DICR_PHYS) ++ ++#ifndef __ASSEMBLY__ ++#define ConXS_CFSR (*((volatile unsigned short *)CFSR_P2V(0x0C000000))) ++#define ConXS_BCR (*((volatile unsigned short *)BCR_P2V(0x0E000000))) ++#define ConXS_DCR (*((volatile unsigned short *)DCR_P2V(0x0F800000))) ++#else ++#define ConXS_CFSR CFSR_P2V(0x0C000000) ++#define ConXS_BCR BCR_P2V(0x0E000000) ++#define ConXS_DCR DCR_P2V(0x0F800000) ++#endif ++ ++#define ConXS_CFSR_BVD_MASK 0x0003 ++#define ConXS_CFSR_BVD1 (1 << 0) ++#define ConXS_CFSR_BVD2 (1 << 1) ++#define ConXS_CFSR_VS_MASK 0x000C ++#define ConXS_CFSR_VS1 (1 << 2) ++#define ConXS_CFSR_VS2 (1 << 3) ++#define ConXS_CFSR_VS_5V (0x3 << 2) ++#define ConXS_CFSR_VS_3V3 0x0 ++ ++#define ConXS_BCR_S0_POW_EN0 (1 << 0) ++#define ConXS_BCR_S0_POW_EN1 (1 << 1) ++#define ConXS_BCR_L_DISP (1 << 4) ++#define ConXS_BCR_CF_BUF_EN (1 << 5) ++#define ConXS_BCR_CF_RESET (1 << 7) ++#define ConXS_BCR_S0_VCC_3V3 0x1 ++#define ConXS_BCR_S0_VCC_5V0 0x2 ++#define ConXS_BCR_S0_VPP_12V 0x4 ++#define ConXS_BCR_S0_VPP_3V3 0x8 ++ ++#define ConXS_IRCR_MODE (1 << 0) ++#define ConXS_IRCR_SD (1 << 1) ++ ++#endif /* _TRIPEPS4_H_ */ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/udc.h linux-2.6.25-rc4/include/asm-arm/arch/udc.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/udc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/udc.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,8 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/udc.h ++ * ++ */ ++#include <asm/mach/udc_pxa2xx.h> ++ ++extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info); ++ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/uncompress.h linux-2.6.25-rc4/include/asm-arm/arch/uncompress.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/uncompress.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/uncompress.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,40 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/uncompress.h ++ * ++ * Author: Nicolas Pitre ++ * Copyright: (C) 2001 MontaVista Software Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include <linux/serial_reg.h> ++#include <asm/arch/pxa-regs.h> ++ ++#define __REG(x) ((volatile unsigned long *)x) ++ ++#define UART FFUART ++ ++ ++static inline void putc(char c) ++{ ++ if (!(UART[UART_IER] & IER_UUE)) ++ return; ++ while (!(UART[UART_LSR] & LSR_TDRQ)) ++ barrier(); ++ UART[UART_TX] = c; ++} ++ ++/* ++ * This does not append a newline ++ */ ++static inline void flush(void) ++{ ++} ++ ++/* ++ * nothing to do ++ */ ++#define arch_decomp_setup() ++#define arch_decomp_wdog() +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/vmalloc.h linux-2.6.25-rc4/include/asm-arm/arch/vmalloc.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/vmalloc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/vmalloc.h 2008-02-26 01:20:20.000000000 +0100 +@@ -0,0 +1,11 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/vmalloc.h ++ * ++ * Author: Nicolas Pitre ++ * Copyright: (C) 2001 MontaVista Software Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#define VMALLOC_END (0xe8000000) +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch/zylonite.h linux-2.6.25-rc4/include/asm-arm/arch/zylonite.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch/zylonite.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch/zylonite.h 2008-03-08 16:11:19.000000000 +0100 +@@ -0,0 +1,44 @@ ++#ifndef __ASM_ARCH_ZYLONITE_H ++#define __ASM_ARCH_ZYLONITE_H ++ ++#define ZYLONITE_ETH_PHYS 0x14000000 ++ ++#define EXT_GPIO(x) (128 + (x)) ++ ++/* the following variables are processor specific and initialized ++ * by the corresponding zylonite_pxa3xx_init() ++ */ ++struct platform_mmc_slot { ++ int gpio_cd; ++ int gpio_wp; ++}; ++ ++extern struct platform_mmc_slot zylonite_mmc_slot[]; ++ ++extern int gpio_backlight; ++extern int gpio_eth_irq; ++ ++extern int lcd_id; ++extern int lcd_orientation; ++ ++#ifdef CONFIG_CPU_PXA300 ++extern void zylonite_pxa300_init(void); ++#else ++static inline void zylonite_pxa300_init(void) ++{ ++ if (cpu_is_pxa300() || cpu_is_pxa310()) ++ panic("%s: PXA300/PXA310 not supported\n", __FUNCTION__); ++} ++#endif ++ ++#ifdef CONFIG_CPU_PXA320 ++extern void zylonite_pxa320_init(void); ++#else ++static inline void zylonite_pxa320_init(void) ++{ ++ if (cpu_is_pxa320()) ++ panic("%s: PXA320 not supported\n", __FUNCTION__); ++} ++#endif ++ ++#endif /* __ASM_ARCH_ZYLONITE_H */ +diff -NbBur linux-2.6.25-rc4-orig/include/asm-arm/arch-pxa/pxa27x_keypad.h linux-2.6.25-rc4/include/asm-arm/arch-pxa/pxa27x_keypad.h +--- linux-2.6.25-rc4-orig/include/asm-arm/arch-pxa/pxa27x_keypad.h 2008-03-08 18:26:06.000000000 +0100 ++++ linux-2.6.25-rc4/include/asm-arm/arch-pxa/pxa27x_keypad.h 2008-03-08 16:22:35.000000000 +0100 +@@ -53,4 +53,6 @@ + + #define KEY(row, col, val) (((row) << 28) | ((col) << 24) | (val)) + ++extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info); ++ + #endif /* __ASM_ARCH_PXA27x_KEYPAD_H */ + diff --git a/packages/linux/linux-mainstone/mainstone/.mtn2git_empty b/packages/linux/linux-mainstone/mainstone/.mtn2git_empty new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/packages/linux/linux-mainstone/mainstone/.mtn2git_empty diff --git a/packages/linux/linux-mainstone/mainstone/defconfig b/packages/linux/linux-mainstone/mainstone/defconfig new file mode 100644 index 0000000000..cbea28d485 --- /dev/null +++ b/packages/linux/linux-mainstone/mainstone/defconfig @@ -0,0 +1,1608 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.25-rc4 +# Sat Mar 8 18:03:28 2008 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_SUPPORTS_AOUT=y +CONFIG_ZONE_DMA=y +CONFIG_ARCH_MTD_XIP=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_GROUP_SCHED=y +# CONFIG_FAIR_GROUP_SCHED is not set +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +# CONFIG_MARKERS is not set +CONFIG_OPROFILE=m +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y +# CONFIG_PREEMPT_RCU is not set + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION is not set +# CONFIG_ARCH_PNX4008 is not set +CONFIG_ARCH_PXA=y +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM7X00A is not set + +# +# Intel PXA2xx/PXA3xx Implementations +# +# CONFIG_ARCH_LUBBOCK is not set +# CONFIG_MACH_LOGICPD_PXA270 is not set +CONFIG_MACH_MAINSTONE=y +# CONFIG_ARCH_PXA_IDP is not set +# CONFIG_PXA_SHARPSL is not set +# CONFIG_ARCH_PXA_ESERIES is not set +# CONFIG_MACH_TRIZEPS4 is not set +# CONFIG_MACH_EM_X270 is not set +# CONFIG_MACH_COLIBRI is not set +# CONFIG_MACH_ZYLONITE is not set +# CONFIG_MACH_LITTLETON is not set +# CONFIG_MACH_ARMCORE is not set +# CONFIG_MACH_MAGICIAN is not set +# CONFIG_MACH_PCM027 is not set +CONFIG_PXA27x=y +CONFIG_PXA_SSP=y + +# +# Boot options +# + +# +# Power management +# + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_XSCALE=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_THUMB is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_OUTER_CACHE is not set +CONFIG_IWMMXT=y +CONFIG_XSCALE_PMU=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCCARD=m +# CONFIG_PCMCIA_DEBUG is not set +CONFIG_PCMCIA=m +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_IOCTL=y + +# +# PC-card bridges +# +CONFIG_PCMCIA_PXA2XX=m + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_LEDS=y +CONFIG_LEDS_CPU=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS0,115200 mem=64M console=ttyS0 debug " +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +CONFIG_PM_LEGACY=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_APM_EMULATION=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE=m +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=m +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +# CONFIG_IPV6_ROUTE_INFO is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_TUNNEL=m +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +CONFIG_IRDA=m + +# +# IrDA protocols +# +# CONFIG_IRLAN is not set +# CONFIG_IRNET is not set +# CONFIG_IRCOMM is not set +# CONFIG_IRDA_ULTRA is not set + +# +# IrDA options +# +# CONFIG_IRDA_CACHE_LAST_LSAP is not set +# CONFIG_IRDA_FAST_RR is not set +# CONFIG_IRDA_DEBUG is not set + +# +# Infrared-port device drivers +# + +# +# SIR device drivers +# +# CONFIG_IRTTY_SIR is not set + +# +# Dongle support +# +# CONFIG_KINGSUN_DONGLE is not set +# CONFIG_KSDAZZLE_DONGLE is not set +# CONFIG_KS959_DONGLE is not set + +# +# FIR device drivers +# +# CONFIG_USB_IRDA is not set +# CONFIG_SIGMATEL_FIR is not set +# CONFIG_PXA_FICP is not set +# CONFIG_MCS_FIR is not set +CONFIG_BT=m +# CONFIG_BT_L2CAP is not set +# CONFIG_BT_SCO is not set + +# +# Bluetooth device drivers +# +# CONFIG_BT_HCIUSB is not set +# CONFIG_BT_HCIBTUSB is not set +# CONFIG_BT_HCIBTSDIO is not set +# CONFIG_BT_HCIUART is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBFUSB is not set +# CONFIG_BT_HCIDTL1 is not set +# CONFIG_BT_HCIBT3C is not set +# CONFIG_BT_HCIBLUECARD is not set +# CONFIG_BT_HCIBTUART is not set +# CONFIG_BT_HCIVHCI is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +# CONFIG_IEEE80211_CRYPT_CCMP is not set +# CONFIG_IEEE80211_CRYPT_TKIP is not set +CONFIG_IEEE80211_SOFTMAC=m +# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_FW_LOADER=m +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +# CONFIG_MTD_CFI_I1 is not set +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_XIP is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PXA2XX=y +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_SHARP_SL is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_CRYPTOLOOP=m +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_HAVE_IDE=y +CONFIG_IDE=y +CONFIG_IDE_MAX_HWIFS=4 +CONFIG_BLK_DEV_IDE=m + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=m +# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_BLK_DEV_IDECS=m +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_BLK_DEV_IDESCSI is not set +# CONFIG_IDE_TASK_IOCTL is not set +# CONFIG_IDE_PROC_FS is not set + +# +# IDE chipset support/bugfixes +# +# CONFIG_IDE_GENERIC is not set +# CONFIG_BLK_DEV_PLATFORM is not set +# CONFIG_BLK_DEV_IDEDMA is not set +CONFIG_IDE_ARCH_OBSOLETE_INIT=y +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +# CONFIG_BLK_DEV_SD is not set +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +CONFIG_SMC91X=y +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_SMC911X is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +CONFIG_WLAN_80211=y +CONFIG_PCMCIA_RAYCS=m +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +# CONFIG_LIBERTAS_CS is not set +# CONFIG_LIBERTAS_SDIO is not set +# CONFIG_LIBERTAS_DEBUG is not set +CONFIG_HERMES=m +CONFIG_PCMCIA_HERMES=m +CONFIG_PCMCIA_SPECTRUM=m +CONFIG_ATMEL=m +CONFIG_PCMCIA_ATMEL=m +CONFIG_AIRO_CS=m +CONFIG_PCMCIA_WL3501=m +CONFIG_USB_ZD1201=m +# CONFIG_USB_NET_RNDIS_WLAN is not set +CONFIG_HOSTAP=m +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_HOSTAP_CS=m + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_NET_PCMCIA is not set +# CONFIG_WAN is not set +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +# CONFIG_PPPOL2TP is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=m +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +CONFIG_INPUT_APMPOWER=y + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_PXA27x=y +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +CONFIG_TOUCHSCREEN_UCB1400=y +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_PXA=y +CONFIG_SERIAL_PXA_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +CONFIG_CARDMAN_4000=m +CONFIG_CARDMAN_4040=m +# CONFIG_IPWIRELESS is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Algorithms +# +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m + +# +# I2C Hardware Bus support +# +CONFIG_I2C_GPIO=m +CONFIG_I2C_PXA=y +CONFIG_I2C_PXA_SLAVE=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_TPS65010 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_BITBANG is not set +CONFIG_SPI_PXA2XX=y + +# +# SPI Protocol Masters +# +# CONFIG_SPI_AT25 is not set +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +CONFIG_HAVE_GPIO_LIB=y + +# +# GPIO Support +# +# CONFIG_DEBUG_GPIO is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MCP23S08 is not set +CONFIG_W1=y +CONFIG_W1_CON=y + +# +# 1-wire Bus Masters +# +# CONFIG_W1_MASTER_DS2490 is not set +# CONFIG_W1_MASTER_DS2482 is not set +# CONFIG_W1_MASTER_DS1WM is not set +# CONFIG_W1_MASTER_GPIO is not set + +# +# 1-wire Slaves +# +# CONFIG_W1_SLAVE_THERM is not set +# CONFIG_W1_SLAVE_SMEM is not set +# CONFIG_W1_SLAVE_DS2433 is not set +CONFIG_W1_SLAVE_DS2760=y +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_PDA_POWER=y +CONFIG_APM_POWER=y +CONFIG_BATTERY_DS2760=y +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_PXA=y +# CONFIG_FB_PXA_PARAMETERS is not set +# CONFIG_FB_MBX is not set +# CONFIG_FB_VIRTUAL is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_LTV350QV is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_CORGI=y + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=y + +# +# Display hardware drivers +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +# CONFIG_SND_SUPPORT_OLD_API is not set +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +CONFIG_SND_AC97_CODEC=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# ALSA ARM devices +# +CONFIG_SND_PXA2XX_PCM=y +CONFIG_SND_PXA2XX_AC97=y + +# +# SPI devices +# + +# +# USB devices +# +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set + +# +# PCMCIA devices +# +# CONFIG_SND_VXPOCKET is not set +# CONFIG_SND_PDAUDIOCF is not set + +# +# System on Chip audio support +# +# CONFIG_SND_SOC is not set + +# +# SoC Audio support for SuperH +# + +# +# ALSA SoC audio for Freescale SOCs +# + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=y +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_DEBUG=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=m +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=m +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_PERSIST is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +CONFIG_USB_MON=y + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_AT91 is not set +CONFIG_USB_GADGET_DUMMY_HCD=y +CONFIG_USB_DUMMY_HCD=m +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_FILE_STORAGE=m +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set + +# +# MMC/SD Host Controller Drivers +# +CONFIG_MMC_PXA=m +# CONFIG_MMC_SPI is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=m + +# +# LED drivers +# +CONFIG_LEDS_GPIO=m + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=m +# CONFIG_LEDS_TRIGGER_IDE_DISK is not set +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_SA1100=y + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=m +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_BIND34 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SAMPLES is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_BLKCIPHER=m +# CONFIG_CRYPTO_SEQIV is not set +CONFIG_CRYPTO_HASH=m +CONFIG_CRYPTO_MANAGER=m +CONFIG_CRYPTO_HMAC=m +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +CONFIG_CRYPTO_ARC4=m +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SALSA20 is not set +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_LZO is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/packages/linux/linux-mainstone_2.6.25-rc4.bb b/packages/linux/linux-mainstone_2.6.25-rc4.bb new file mode 100644 index 0000000000..fd5c30e37f --- /dev/null +++ b/packages/linux/linux-mainstone_2.6.25-rc4.bb @@ -0,0 +1,25 @@ +require linux.inc + +SECTION = "kernel" +DESCRIPTION = "Linux kernel for the Mainstone (PXA270 ref design)" +LICENSE = "GPL" +PR = "r0" + +SRC_URI = "${KERNELORG_MIRROR}/pub/linux/kernel/v2.6/linux-2.6.24.tar.bz2 \ + ${KERNELORG_MIRROR}/pub/linux/kernel/v2.6/testing/patch-2.6.25-rc4.bz2;patch=1 \ + file://mainstone-keypad.patch;patch=1 \ + file://defconfig" + +S = "${WORKDIR}/linux-2.6.24" + +COMPATIBLE_HOST = 'arm.*-linux' + +ARCH = "arm" + +CMDLINE_CONSOLE ?= "ttyS0,115200n8" +#CMDLINE_ROOT = "root=/dev/slug rootfstype=ext2,jffs2 initrd=0x01000000,10M mem=32M@0x00000000" +#CMDLINE_ROOT = "root=/dev/ram0 rw rootfstype=ext2,jffs2 initrd=0x01000000,10M init=/linuxrc mem=32M@0x00000000" +CMDLINE_ROOT = "root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS0,115200 mem=64M" +CMDLINE = "${CMDLINE_ROOT} ${CMDLINE_CONSOLE}" + +COMPATIBLE_MACHINE = "mainstone" diff --git a/packages/linux/linux-omap.inc b/packages/linux/linux-omap.inc index 52b0d27a6d..c706a3f919 100644 --- a/packages/linux/linux-omap.inc +++ b/packages/linux/linux-omap.inc @@ -1,39 +1,7 @@ -SECTION = "kernel" -DESCRIPTION = "Linux kernel for OMAP processors" -LICENSE = "GPL" -#DEPENDS = ${@['u-boot','u-boot-omap2430sdp'][bb.data.getVar('MACHINE',d,1) == 'omap2430sdp']} - -DEPENDS = "u-boot-utils-native" - -inherit kernel +require linux.inc +DESCRIPTION = "Linux kernel for OMAP processors" KERNEL_IMAGETYPE = "uImage" module_autoload_ohci-hcd_omap5912osk = "ohci-hcd" -do_configure_prepend() { - - rm -f ${S}/.config || true - - if [ "${TARGET_OS}" = "linux-gnueabi" -o "${TARGET_OS}" = "linux-uclibcgnueabi" ]; then - echo "CONFIG_AEABI=y" >> ${S}/.config - echo "CONFIG_OABI_COMPAT=y" >> ${S}/.config - else - echo "# CONFIG_AEABI is not set" >> ${S}/.config - echo "# CONFIG_OABI_COMPAT is not set" >> ${S}/.config - fi - - sed -e '/CONFIG_AEABI/d' \ - -e '/CONFIG_OABI_COMPAT=/d' \ - '${WORKDIR}/defconfig' >>'${S}/.config' - - yes '' | oe_runmake oldconfig -} -do_deploy() { - install -d ${DEPLOY_DIR_IMAGE} - install -m 0644 arch/${ARCH}/boot/${KERNEL_IMAGETYPE} ${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${PV}-${MACHINE}-${DATETIME} -} - -do_deploy[dirs] = "${S}" - -addtask deploy before do_build after do_compile diff --git a/packages/linux/linux-openmoko_2.6.22.5.bb b/packages/linux/linux-openmoko_2.6.22.5.bb index fc702c8719..fe46c59a58 100644 --- a/packages/linux/linux-openmoko_2.6.22.5.bb +++ b/packages/linux/linux-openmoko_2.6.22.5.bb @@ -60,18 +60,12 @@ module_autoload_snd-mixer-oss = "snd-mixer-oss" # sd/mmc module_autoload_s3cmci = "s3cmci" -python do_patch_prepend() { - def runcmd(cmd): - import commands - (status, output) = commands.getstatusoutput(cmd) - if status != 0: - raise Exception, "Status %i: %s" % (status >> 8, output) - return output - runcmd('mv %(WORKDIR)s/patches %(S)s/patches && cd %(S)s && ' - 'quilt push -av && mv patches patches.openmoko && ' - 'mv .pc .pc.old && mv %(WORKDIR)s/defconfig-%(KERNEL_RELEASE)s %(WORKDIR)s/defconfig' % - {'WORKDIR': bb.data.getVar('WORKDIR', d, 1), - 'S': bb.data.getVar('S', d, 1), - 'KERNEL_RELEASE': bb.data.getVar('KERNEL_RELEASE', d, 1)}) - del runcmd +do_prepatch() { + mv ${WORKDIR}/patches ${S}/patches && cd ${S} && quilt push -av + mv patches patches.openmoko + mv .pc .pc.old + mv ${WORKDIR}/defconfig-${KERNEL_RELEASE} ${WORKDIR}/defconfig } + +addtask prepatch after do_unpack before do_patch + diff --git a/packages/linux/linux-openmoko_2.6.24.bb b/packages/linux/linux-openmoko_2.6.24.bb index b316f4ae4e..0a7b34ba30 100644 --- a/packages/linux/linux-openmoko_2.6.24.bb +++ b/packages/linux/linux-openmoko_2.6.24.bb @@ -8,8 +8,13 @@ KERNEL_RELEASE = "2.6.24" # need to synchronize with LOCALVERSION, if set KERNEL_VERSION = "${KERNEL_RELEASE}" -PV = "${VANILLA_VERSION}+svnr${SRCREV}" -PR = "r3" +# re-enabled this when feature is fully implemented in OE +#SRCREV_FORMAT = "patches-rconfig" +SRCREV_FORMAT = "patches" +CONFIG_REV = "4165" + +PV = "${VANILLA_VERSION}+svnr${SRCREV}-r${CONFIG_REV}" +PR = "r4" KERNEL_IMAGETYPE = "uImage" UBOOT_ENTRYPOINT = "30008000" @@ -17,11 +22,10 @@ UBOOT_ENTRYPOINT = "30008000" ############################################################## # source and patches # -SRCREV_FORMAT = "patches-rconfig" SRC_URI = "${KERNELORG_MIRROR}/pub/linux/kernel/v2.6/linux-${VANILLA_VERSION}.tar.bz2 \ svn://svn.openmoko.org/branches/src/target/kernel/2.6.24.x;module=patches;proto=http;name=patches \ - svn://svn.openmoko.org/branches/src/target/kernel/2.6.24.x;module=config;proto=http;name=config " + svn://svn.openmoko.org/branches/src/target/kernel/2.6.24.x;module=config;proto=http;rev=${CONFIG_REV};name=config " S = "${WORKDIR}/linux-${VANILLA_VERSION}" diff --git a/packages/linux/linux-rp-2.6.24/defconfig-tosa b/packages/linux/linux-rp-2.6.24/defconfig-tosa new file mode 100644 index 0000000000..34f0cc1210 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/defconfig-tosa @@ -0,0 +1,1728 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.24 +# Mon Feb 25 01:57:38 2008 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_ARCH_MTD_XIP=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FAIR_USER_SCHED=y +# CONFIG_FAIR_CGROUP_SCHED is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_HAVE_CLOCK_LIB=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +# CONFIG_ELF_CORE is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=m +CONFIG_IOSCHED_DEADLINE=m +CONFIG_IOSCHED_CFQ=m +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_PNX4008 is not set +CONFIG_ARCH_PXA=y +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +CONFIG_DMABOUNCE=y + +# +# Intel PXA2xx/PXA3xx Implementations +# +# CONFIG_ARCH_LUBBOCK is not set +# CONFIG_MACH_LOGICPD_PXA270 is not set +# CONFIG_MACH_MAINSTONE is not set +# CONFIG_ARCH_PXA_IDP is not set +CONFIG_PXA_SHARPSL=y +# CONFIG_MACH_TRIZEPS4 is not set +# CONFIG_MACH_HX2750 is not set +# CONFIG_MACH_EM_X270 is not set +# CONFIG_MACH_ZYLONITE is not set +# CONFIG_MACH_ARMCORE is not set +CONFIG_PXA_SHARPSL_25x=y +# CONFIG_PXA_SHARPSL_27x is not set +# CONFIG_MACH_HTCUNIVERSAL is not set +# CONFIG_MACH_POODLE is not set +# CONFIG_MACH_CORGI is not set +# CONFIG_MACH_SHEPHERD is not set +# CONFIG_MACH_HUSKY is not set +CONFIG_MACH_TOSA=y +CONFIG_PXA25x=y +CONFIG_PXA_SSP=y +# CONFIG_PXA_KEYS is not set + +# +# Boot options +# + +# +# Power management +# + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_XSCALE=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_OUTER_CACHE is not set +# CONFIG_IWMMXT is not set +CONFIG_XSCALE_PMU=y +CONFIG_SHARP_PARAM=y +CONFIG_SHARP_SCOOP=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCCARD=y +# CONFIG_PCMCIA_DEBUG is not set +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y +# CONFIG_PCMCIA_IOCTL is not set + +# +# PC-card bridges +# +CONFIG_PCMCIA_PXA2XX=y + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0,115200n8 console=tty1 noinitrd root=/dev/mtdblock2 rootfstype=jffs2 dyntick=enable debug" +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y +CONFIG_CPU_FREQ_PXA25x=y + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=m +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=m +CONFIG_CPU_FREQ_GOV_USERSPACE=m +CONFIG_CPU_FREQ_GOV_ONDEMAND=m +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=m + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_LEGACY is not set +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND_UP_POSSIBLE=y +CONFIG_SUSPEND=y +CONFIG_APM_EMULATION=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=m +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=m +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IP_VS is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_TUNNEL=m +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK is not set +# CONFIG_NF_CONNTRACK_ENABLED is not set +# CONFIG_NF_CONNTRACK is not set +CONFIG_NETFILTER_XTABLES=m +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_TRACE is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set + +# +# IP: Netfilter Configuration +# +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_IPRANGE=m +CONFIG_IP_NF_MATCH_TOS=m +CONFIG_IP_NF_MATCH_RECENT=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_MATCH_OWNER=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_TOS=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# IPv6: Netfilter Configuration (EXPERIMENTAL) +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +CONFIG_IRDA=m + +# +# IrDA protocols +# +CONFIG_IRLAN=m +CONFIG_IRNET=m +CONFIG_IRCOMM=m +# CONFIG_IRDA_ULTRA is not set + +# +# IrDA options +# +# CONFIG_IRDA_CACHE_LAST_LSAP is not set +# CONFIG_IRDA_FAST_RR is not set +# CONFIG_IRDA_DEBUG is not set + +# +# Infrared-port device drivers +# + +# +# SIR device drivers +# +# CONFIG_IRTTY_SIR is not set + +# +# Dongle support +# +# CONFIG_KINGSUN_DONGLE is not set +# CONFIG_KSDAZZLE_DONGLE is not set +# CONFIG_KS959_DONGLE is not set + +# +# Old SIR device drivers +# +# CONFIG_IRPORT_SIR is not set + +# +# Old Serial dongle support +# + +# +# FIR device drivers +# +# CONFIG_USB_IRDA is not set +# CONFIG_SIGMATEL_FIR is not set +CONFIG_PXA_FICP=m +# CONFIG_MCS_FIR is not set +CONFIG_BT=m +CONFIG_BT_L2CAP=m +CONFIG_BT_SCO=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIUSB=m +# CONFIG_BT_HCIUSB_SCO is not set +# CONFIG_BT_HCIBTSDIO is not set +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +# CONFIG_BT_HCIUART_LL is not set +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIDTL1=m +CONFIG_BT_HCIBT3C=m +CONFIG_BT_HCIBLUECARD=m +CONFIG_BT_HCIBTUART=m +CONFIG_BT_HCIVHCI=m +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT=y +# CONFIG_MAC80211 is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m +# CONFIG_IEEE80211_SOFTMAC is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +CONFIG_MTD_ROM=y +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_SHARP_SL=y +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_H1900 is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_SHARPSL is not set +CONFIG_MTD_NAND_TMIO=y +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +CONFIG_IDE=y +CONFIG_IDE_MAX_HWIFS=4 +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_BLK_DEV_IDEDISK=y +# CONFIG_IDEDISK_MULTI_MODE is not set +CONFIG_BLK_DEV_IDECS=y +CONFIG_BLK_DEV_IDECD=m +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_BLK_DEV_IDESCSI is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# +# CONFIG_IDE_GENERIC is not set +# CONFIG_BLK_DEV_PLATFORM is not set +# CONFIG_IDE_ARM is not set +# CONFIG_BLK_DEV_IDEDMA is not set +CONFIG_IDE_ARCH_OBSOLETE_INIT=y +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m +CONFIG_BLK_DEV_SR=m +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set +# CONFIG_ATA is not set +CONFIG_MD=y +# CONFIG_BLK_DEV_MD is not set +CONFIG_BLK_DEV_DM=m +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_MIRROR=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_EMC=m +# CONFIG_DM_MULTIPATH_RDAC is not set +# CONFIG_DM_MULTIPATH_HP is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_UEVENT is not set +CONFIG_NETDEVICES=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=m +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_SMC911X is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +CONFIG_NETDEV_1000=y +CONFIG_NETDEV_10000=y + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# USB Network Adapters +# +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_CDCETHER=m +# CONFIG_USB_NET_DM9601 is not set +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +# CONFIG_USB_NET_MCS7830 is not set +# CONFIG_USB_NET_RNDIS_HOST is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set +CONFIG_NET_PCMCIA=y +# CONFIG_PCMCIA_3C589 is not set +# CONFIG_PCMCIA_3C574 is not set +# CONFIG_PCMCIA_FMVJ18X is not set +CONFIG_PCMCIA_PCNET=m +# CONFIG_PCMCIA_NMCLAN is not set +# CONFIG_PCMCIA_SMC91C92 is not set +# CONFIG_PCMCIA_XIRC2PS is not set +# CONFIG_PCMCIA_AXNET is not set +# CONFIG_WAN is not set +CONFIG_PPP=m +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=m +# CONFIG_PPP_SYNC_TTY is not set +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +# CONFIG_PPP_MPPE is not set +# CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=m +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=m +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=480 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=640 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +# CONFIG_INPUT_POWER is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_CORGI is not set +# CONFIG_KEYBOARD_SPITZ is not set +CONFIG_KEYBOARD_TOSA=y +# CONFIG_KEYBOARD_TOSA_USE_EXT_KEYCODES is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_CORGI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +CONFIG_TOUCHSCREEN_WM97XX=y +# CONFIG_TOUCHSCREEN_WM9705 is not set +CONFIG_TOUCHSCREEN_WM9712=y +# CONFIG_TOUCHSCREEN_WM9713 is not set +# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set +CONFIG_TOUCHSCREEN_WM97XX_TOSA=y +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_UCB1400 is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +CONFIG_INPUT_UINPUT=m + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=m +CONFIG_SERIAL_8250_CS=m +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_PXA=y +CONFIG_SERIAL_PXA_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_NVRAM is not set +# CONFIG_R3964 is not set + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +# CONFIG_CARDMAN_4000 is not set +# CONFIG_CARDMAN_4040 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_CHARDEV is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_PXA=y +# CONFIG_I2C_PXA_SLAVE is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set +CONFIG_HAVE_GPIO_LIB=y + +# +# GPIO Support +# + +# +# I2C GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_PDA_POWER=y +CONFIG_APM_POWER=y +# CONFIG_BATTERY_DS2760 is not set +CONFIG_BATTERY_TOSA=y +# CONFIG_HWMON is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=y +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +CONFIG_MFD_TC6393XB=y +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_ASIC3 is not set +# CONFIG_HTC_ASIC3_DS1WM is not set + +# +# Multimedia devices +# +CONFIG_VIDEO_DEV=m +CONFIG_VIDEO_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_TUNER_3036 is not set +CONFIG_V4L_USB_DRIVERS=y +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_VIDEO_USBVISION is not set +CONFIG_VIDEO_USBVIDEO=m +CONFIG_USB_VICAM=m +CONFIG_USB_IBMCAM=m +CONFIG_USB_KONICAWC=m +# CONFIG_USB_QUICKCAM_MESSENGER is not set +# CONFIG_USB_ET61X251 is not set +# CONFIG_VIDEO_OVCAMCHIP is not set +# CONFIG_USB_W9968CF is not set +CONFIG_USB_OV511=m +CONFIG_USB_SE401=m +CONFIG_USB_SN9C102=m +CONFIG_USB_STV680=m +# CONFIG_USB_ZC0301 is not set +# CONFIG_USB_PWC is not set +# CONFIG_USB_ZR364XX is not set +CONFIG_RADIO_ADAPTERS=y +CONFIG_USB_DSBR=m +# CONFIG_DVB_CORE is not set +CONFIG_DAB=y +CONFIG_USB_DABUSB=m + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_DEFERRED_IO is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_PXA is not set +# CONFIG_FB_MBX is not set +# CONFIG_FB_W100 is not set +CONFIG_FB_TMIO=y +CONFIG_FB_TMIO_ACCELL=y +# CONFIG_FB_VIRTUAL is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_CORGI is not set +CONFIG_BACKLIGHT_TOSA=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +# CONFIG_FONT_8x16 is not set +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +# CONFIG_LOGO is not set + +# +# Sound +# +CONFIG_SOUND=y + +# +# Advanced Linux Sound Architecture +# +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=m +CONFIG_SND_RAWMIDI=m +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +# CONFIG_SND_SUPPORT_OLD_API is not set +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set + +# +# Generic devices +# +CONFIG_SND_DUMMY=m +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# ALSA ARM devices +# +# CONFIG_SND_PXA2XX_AC97 is not set + +# +# USB devices +# +CONFIG_SND_USB_AUDIO=m +# CONFIG_SND_USB_CAIAQ is not set + +# +# PCMCIA devices +# +# CONFIG_SND_VXPOCKET is not set +# CONFIG_SND_PDAUDIOCF is not set + +# +# System on Chip audio support +# +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC=y +CONFIG_SND_PXA2XX_SOC=y +CONFIG_SND_PXA2XX_SOC_AC97=y +CONFIG_SND_PXA2XX_SOC_TOSA=y + +# +# SoC Audio support for SuperH +# +CONFIG_SND_SOC_WM9712=y + +# +# Open Sound System +# +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=y +CONFIG_HID_SUPPORT=y +CONFIG_HID=m +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=m +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=m +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_PERSIST is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=m +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SL811_HCD=m +CONFIG_USB_SL811_CS=m +# CONFIG_USB_R8A66597_HCD is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USB_MON=y + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_AIRPRIME is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +CONFIG_USB_SERIAL_BELKIN=m +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +# CONFIG_USB_SERIAL_CP2101 is not set +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +# CONFIG_USB_SERIAL_FUNSOFT is not set +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +# CONFIG_USB_SERIAL_KEYSPAN_MPR is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19QW is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19QI is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA49WLC is not set +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +CONFIG_USB_SERIAL_PL2303=m +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_HP4X is not set +CONFIG_USB_SERIAL_SAFE=m +# CONFIG_USB_SERIAL_SAFE_PADDED is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_XIRCOM=m +# CONFIG_USB_SERIAL_OPTION is not set +CONFIG_USB_SERIAL_OMNINET=m +# CONFIG_USB_SERIAL_DEBUG is not set +CONFIG_USB_EZUSB=y + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +# CONFIG_USB_ADUTUX is not set +CONFIG_USB_AUERSWALD=m +CONFIG_USB_RIO500=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +# CONFIG_USB_BERRY_CHARGE is not set +CONFIG_USB_LED=m +# CONFIG_USB_CYPRESS_CY7C63 is not set +CONFIG_USB_CYTHERM=m +# CONFIG_USB_PHIDGET is not set +CONFIG_USB_IDMOUSE=m +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_NET2280 is not set +CONFIG_USB_GADGET_PXA2XX=y +CONFIG_USB_PXA2XX=m +# CONFIG_USB_PXA2XX_SMALL is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +# CONFIG_USB_GADGET_DUALSPEED is not set +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +# CONFIG_USB_FILE_STORAGE_TEST is not set +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_SDIO_UART=m + +# +# MMC/SD Host Controller Drivers +# +CONFIG_MMC_PXA=y +# CONFIG_MMC_TMIO is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +CONFIG_LEDS_TOSA=y +# CONFIG_LEDS_GPIO is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_IDE_DISK=y +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_SA1100=y + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=m +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=m +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=m + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +# CONFIG_ZISOFS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_SYSFS is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +# CONFIG_SUNRPC_BIND34 is not set +CONFIG_RPCSEC_GSS_KRB5=m +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +CONFIG_SMB_NLS_DEFAULT=y +CONFIG_SMB_NLS_REMOTE="cp437" +CONFIG_CIFS=m +# CONFIG_CIFS_STATS is not set +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_XATTR is not set +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_EXPERIMENTAL is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=m +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set +# CONFIG_INSTRUMENTATION is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_FRAME_POINTER=y +# CONFIG_SAMPLES is not set +# CONFIG_DEBUG_USER is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_HASH=m +CONFIG_CRYPTO_MANAGER=m +CONFIG_CRYPTO_HMAC=m +# CONFIG_CRYPTO_XCBC is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_ANUBIS=m +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_LZO is not set +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_CAMELLIA is not set +CONFIG_CRYPTO_TEST=m +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/packages/linux/linux-rp-2.6.24/htcuni.patch b/packages/linux/linux-rp-2.6.24/htcuni.patch index f462650566..8448c4ec06 100644 --- a/packages/linux/linux-rp-2.6.24/htcuni.patch +++ b/packages/linux/linux-rp-2.6.24/htcuni.patch @@ -57,10 +57,10 @@ include/linux/soc/tmio_mmc.h | 17 56 files changed, 7469 insertions(+), 1 deletion(-) -Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/Makefile +Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/Makefile =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/htcuniversal/Makefile 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/Makefile 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,19 @@ +# +# Makefile for HTC Universal @@ -81,10 +81,10 @@ Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/Makefile +obj-$(CONFIG_HTCUNIVERSAL_UDC) += htcuniversal_udc.o + +obj-$(CONFIG_HTCUNIVERSAL_AK4641) += htcuniversal_ak4641.o -Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal.c +Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal.c 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal.c 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,468 @@ +/* + * Hardware definitions for HTC Universal @@ -554,10 +554,10 @@ Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal.c + .init_machine = htcuniversal_init, + .timer = &pxa_timer, +MACHINE_END -Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_ak4641.c +Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_ak4641.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_ak4641.c 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_ak4641.c 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,917 @@ +/* + * Audio support for codec Asahi Kasei AK4641 @@ -1476,10 +1476,10 @@ Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_ak4641.c +MODULE_LICENSE("GPL"); + +/* end {{ Module }} */ -Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_ak4641.h +Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_ak4641.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_ak4641.h 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_ak4641.h 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,65 @@ +/* + * Audio support for codec Asahi Kasei AK4641 @@ -1546,10 +1546,10 @@ Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_ak4641.h +void snd_ak4641_hp_detected(struct snd_ak4641 *ak, int detected); /* atomic context */ + +#endif /* __SOUND_AK4641_H */ -Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_asic3_leds.c +Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_asic3_leds.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_asic3_leds.c 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_asic3_leds.c 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,143 @@ +/* + * LEDs support for the HP iPaq hx4700 @@ -1694,10 +1694,10 @@ Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_asic3_leds.c +MODULE_AUTHOR("Anton Vorontsov <cbou@mail.ru>"); +MODULE_DESCRIPTION("htcuniversal LEDs driver"); +MODULE_LICENSE("GPL"); -Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_bl.c +Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_bl.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_bl.c 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_bl.c 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,61 @@ +/* + * Use consistent with the GNU GPL is permitted, @@ -1760,10 +1760,10 @@ Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_bl.c +MODULE_AUTHOR("Paul Sokolovsky <pmiscml@gmail.com>"); +MODULE_DESCRIPTION("Backlight driver for HTC Universal"); +MODULE_LICENSE("GPL"); -Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_bt.c +Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_bt.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_bt.c 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_bt.c 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,135 @@ +/* Bluetooth interface driver for TI BRF6150 on HX4700 + * @@ -1900,10 +1900,10 @@ Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_bt.c + +/* vim600: set noexpandtab sw=8 ts=8 :*/ + -Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_bt.h +Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_bt.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_bt.h 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_bt.h 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,17 @@ +/* + * Bluetooth support file for calling bluetooth configuration functions @@ -1922,10 +1922,10 @@ Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_bt.h + + +#endif -Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_buttons.c +Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_buttons.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_buttons.c 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_buttons.c 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,87 @@ +/* + * Buttons driver for HTC Universal @@ -2014,10 +2014,10 @@ Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_buttons.c +MODULE_AUTHOR ("Joshua Wise, Pawel Kolodziejski, Paul Sokolosvky"); +MODULE_DESCRIPTION ("Buttons support for HTC Universal"); +MODULE_LICENSE ("GPL"); -Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_core.c +Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_core.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_core.c 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_core.c 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,226 @@ +/* Core Hardware driver for Hx4700 (Serial, ASIC3, EGPIOs) + * @@ -2245,10 +2245,10 @@ Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_core.c +MODULE_LICENSE("GPL"); + +/* vim600: set noexpandtab sw=8 ts=8 :*/ -Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_lcd.c +Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_lcd.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_lcd.c 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_lcd.c 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,212 @@ +/* + * Use consistent with the GNU GPL is permitted, @@ -2462,10 +2462,10 @@ Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_lcd.c +MODULE_DESCRIPTION("Framebuffer driver for HTC Universal"); +MODULE_LICENSE("GPL"); + -Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_phone.c +Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_phone.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_phone.c 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_phone.c 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,167 @@ + +/* Phone interface driver for Qualcomm MSM6250 on HTC Universal @@ -2634,10 +2634,10 @@ Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_phone.c +MODULE_LICENSE("GPL"); + +/* vim600: set noexpandtab sw=8 ts=8 :*/ -Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_phone.h +Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_phone.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_phone.h 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_phone.h 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,16 @@ +/* + * Bluetooth support file for calling bluetooth configuration functions @@ -2655,10 +2655,10 @@ Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_phone.h +}; + +#endif -Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_pm.c +Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_pm.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_pm.c 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_pm.c 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,69 @@ +/* + * MyPal 716 power management support for the original HTC IPL in DoC G3 @@ -2729,10 +2729,10 @@ Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_pm.c + pxa_pm_set_ll_ops(&htcuniversal_ll_pm_ops); +} +#endif /* CONFIG_PM */ -Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_power2.c +Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_power2.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_power2.c 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_power2.c 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,97 @@ +/* + * pda_power driver for HTC Universal @@ -2831,10 +2831,10 @@ Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_power2.c + +MODULE_DESCRIPTION("Power driver for HTC Universal"); +MODULE_LICENSE("GPL"); -Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_ts2.c +Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_ts2.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_ts2.c 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_ts2.c 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,490 @@ +/* Touch screen driver for the TI something-or-other + * @@ -3326,10 +3326,10 @@ Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_ts2.c +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Aric Blumer, SDG Systems, LLC"); +MODULE_DESCRIPTION("HTC Universal Touch Screen Driver"); -Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_udc.c +Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_udc.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_udc.c 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/htcuniversal_udc.c 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,71 @@ + +/* @@ -3402,10 +3402,10 @@ Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/htcuniversal_udc.c + +module_init(htcuniversal_udc_init); +MODULE_LICENSE("GPL"); -Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/tsc2046_ts.h +Index: linux-2.6.24/arch/arm/mach-pxa/htcuniversal/tsc2046_ts.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/htcuniversal/tsc2046_ts.h 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/htcuniversal/tsc2046_ts.h 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,20 @@ +/* + * temporary TSC2046 touchscreen hack @@ -3427,13 +3427,13 @@ Index: linux-2.6.23/arch/arm/mach-pxa/htcuniversal/tsc2046_ts.h +#define TSC2046_SAMPLE_Y 0x90 + +#endif -Index: linux-2.6.23/arch/arm/mach-pxa/Kconfig +Index: linux-2.6.24/arch/arm/mach-pxa/Kconfig =================================================================== ---- linux-2.6.23.orig/arch/arm/mach-pxa/Kconfig 2008-01-20 18:59:41.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/Kconfig 2008-01-20 18:59:46.000000000 +0000 -@@ -92,6 +92,14 @@ config MACH_HX2750 - help - This enables support for the HP iPAQ HX2750 handheld. +--- linux-2.6.24.orig/arch/arm/mach-pxa/Kconfig 2008-03-10 16:08:01.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/Kconfig 2008-03-10 16:09:23.000000000 +0000 +@@ -92,6 +92,14 @@ + bool "Sharp PXA270 models (SL-Cxx00)" + select PXA27x +config MACH_HTCUNIVERSAL + bool "HTC Universal" @@ -3446,7 +3446,7 @@ Index: linux-2.6.23/arch/arm/mach-pxa/Kconfig endchoice endif -@@ -111,6 +119,86 @@ endchoice +@@ -111,6 +119,86 @@ endif @@ -3533,16 +3533,16 @@ Index: linux-2.6.23/arch/arm/mach-pxa/Kconfig endmenu config MACH_POODLE -@@ -196,4 +284,3 @@ config PXA_KEYS +@@ -196,4 +284,3 @@ depends on (PXA25x || PXA27x) && INPUT endif - -Index: linux-2.6.23/arch/arm/mach-pxa/Makefile +Index: linux-2.6.24/arch/arm/mach-pxa/Makefile =================================================================== ---- linux-2.6.23.orig/arch/arm/mach-pxa/Makefile 2008-01-20 18:59:41.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/Makefile 2008-01-20 18:59:46.000000000 +0000 -@@ -23,6 +23,7 @@ obj-$(CONFIG_MACH_POODLE) += poodle.o co +--- linux-2.6.24.orig/arch/arm/mach-pxa/Makefile 2008-03-10 16:08:01.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/Makefile 2008-03-10 16:09:23.000000000 +0000 +@@ -23,6 +23,7 @@ obj-$(CONFIG_MACH_TOSA) += tosa.o obj-$(CONFIG_MACH_EM_X270) += em-x270.o obj-$(CONFIG_MACH_HX2750) += hx2750.o hx2750_test.o @@ -3550,11 +3550,11 @@ Index: linux-2.6.23/arch/arm/mach-pxa/Makefile ifeq ($(CONFIG_MACH_ZYLONITE),y) obj-y += zylonite.o -Index: linux-2.6.23/drivers/leds/Kconfig +Index: linux-2.6.24/drivers/leds/Kconfig =================================================================== ---- linux-2.6.23.orig/drivers/leds/Kconfig 2008-01-20 18:59:17.000000000 +0000 -+++ linux-2.6.23/drivers/leds/Kconfig 2008-01-20 18:59:46.000000000 +0000 -@@ -114,6 +114,13 @@ config LEDS_CM_X270 +--- linux-2.6.24.orig/drivers/leds/Kconfig 2008-01-24 22:58:37.000000000 +0000 ++++ linux-2.6.24/drivers/leds/Kconfig 2008-03-10 16:09:23.000000000 +0000 +@@ -114,6 +114,13 @@ help This option enables support for the CM-X270 LEDs. @@ -3568,10 +3568,10 @@ Index: linux-2.6.23/drivers/leds/Kconfig comment "LED Triggers" config LEDS_TRIGGERS -Index: linux-2.6.23/drivers/leds/leds-asic3.c +Index: linux-2.6.24/drivers/leds/leds-asic3.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/drivers/leds/leds-asic3.c 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/drivers/leds/leds-asic3.c 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,189 @@ +/* + * LEDs support for HTC ASIC3 devices. @@ -3762,11 +3762,11 @@ Index: linux-2.6.23/drivers/leds/leds-asic3.c +MODULE_AUTHOR("Anton Vorontsov <cbou@mail.ru>"); +MODULE_DESCRIPTION("HTC ASIC3 LEDs driver"); +MODULE_LICENSE("GPL"); -Index: linux-2.6.23/drivers/mfd/Kconfig +Index: linux-2.6.24/drivers/mfd/Kconfig =================================================================== ---- linux-2.6.23.orig/drivers/mfd/Kconfig 2008-01-20 18:59:38.000000000 +0000 -+++ linux-2.6.23/drivers/mfd/Kconfig 2008-01-20 18:59:46.000000000 +0000 -@@ -21,6 +21,16 @@ config MFD_TSC2101 +--- linux-2.6.24.orig/drivers/mfd/Kconfig 2008-03-10 16:07:51.000000000 +0000 ++++ linux-2.6.24/drivers/mfd/Kconfig 2008-03-10 16:09:23.000000000 +0000 +@@ -21,6 +21,16 @@ help Support for TI TSC2101 Touchscreen and Audio Codec @@ -3783,10 +3783,10 @@ Index: linux-2.6.23/drivers/mfd/Kconfig endmenu menu "Multimedia Capabilities Port drivers" -Index: linux-2.6.23/drivers/mfd/Makefile +Index: linux-2.6.24/drivers/mfd/Makefile =================================================================== ---- linux-2.6.23.orig/drivers/mfd/Makefile 2008-01-20 18:59:38.000000000 +0000 -+++ linux-2.6.23/drivers/mfd/Makefile 2008-01-20 18:59:46.000000000 +0000 +--- linux-2.6.24.orig/drivers/mfd/Makefile 2008-03-10 16:07:51.000000000 +0000 ++++ linux-2.6.24/drivers/mfd/Makefile 2008-03-10 16:09:23.000000000 +0000 @@ -2,6 +2,8 @@ # Makefile for multifunction miscellaneous devices # @@ -3796,10 +3796,10 @@ Index: linux-2.6.23/drivers/mfd/Makefile obj-$(CONFIG_MFD_SM501) += sm501.o obj-$(CONFIG_MCP) += mcp-core.o -Index: linux-2.6.23/drivers/mfd/asic3_base.c +Index: linux-2.6.24/drivers/mfd/asic3_base.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/drivers/mfd/asic3_base.c 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/drivers/mfd/asic3_base.c 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,1208 @@ +/* + * Driver interface to HTC "ASIC3" @@ -5009,10 +5009,10 @@ Index: linux-2.6.23/drivers/mfd/asic3_base.c +MODULE_AUTHOR("Phil Blundell <pb@handhelds.org>"); +MODULE_DESCRIPTION("Core driver for HTC ASIC3"); +MODULE_SUPPORTED_DEVICE("asic3"); -Index: linux-2.6.23/drivers/mfd/soc-core.c +Index: linux-2.6.24/drivers/mfd/soc-core.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/drivers/mfd/soc-core.c 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/drivers/mfd/soc-core.c 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,106 @@ +/* + * drivers/soc/soc-core.c @@ -5089,7 +5089,7 @@ Index: linux-2.6.23/drivers/mfd/soc-core.c + if (blk->res[r].flags & IORESOURCE_MEM) { + base = mem->start; + } else if ((blk->res[r].flags & IORESOURCE_IRQ) && -+ (blk->res[r].flags & IORESOURCE_IRQ_SOC_SUBDEVICE)) { ++ (blk->res[r].flags & IORESOURCE_IRQ_MFD_SUBDEVICE)) { + base = irq_base; + } + @@ -5120,10 +5120,10 @@ Index: linux-2.6.23/drivers/mfd/soc-core.c + return NULL; +} +EXPORT_SYMBOL_GPL(soc_add_devices); -Index: linux-2.6.23/drivers/mfd/soc-core.h +Index: linux-2.6.24/drivers/mfd/soc-core.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/drivers/mfd/soc-core.h 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/drivers/mfd/soc-core.h 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,30 @@ +/* + * drivers/soc/soc-core.h @@ -5155,10 +5155,10 @@ Index: linux-2.6.23/drivers/mfd/soc-core.h + +void soc_free_devices(struct platform_device *devices, int nr_devs); + -Index: linux-2.6.23/include/asm-arm/arch-pxa/clock.h +Index: linux-2.6.24/include/asm-arm/arch-pxa/clock.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/include/asm-arm/arch-pxa/clock.h 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/include/asm-arm/arch-pxa/clock.h 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,27 @@ +/* + * linux/include/asm-arm/arch-pxa/clock.h @@ -5187,10 +5187,10 @@ Index: linux-2.6.23/include/asm-arm/arch-pxa/clock.h + +extern int clk_register(struct clk *clk); +extern void clk_unregister(struct clk *clk); -Index: linux-2.6.23/include/asm-arm/arch-pxa/htcuniversal-asic.h +Index: linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal-asic.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/include/asm-arm/arch-pxa/htcuniversal-asic.h 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal-asic.h 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,213 @@ +/* + * include/asm/arm/arch-pxa/htcuniversal-asic.h @@ -5405,10 +5405,10 @@ Index: linux-2.6.23/include/asm-arm/arch-pxa/htcuniversal-asic.h + +#endif /* _HTCUNIVERSAL_ASIC_H_ */ + -Index: linux-2.6.23/include/asm-arm/arch-pxa/htcuniversal-gpio.h +Index: linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal-gpio.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/include/asm-arm/arch-pxa/htcuniversal-gpio.h 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal-gpio.h 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,220 @@ +/* + * include/asm-arm/arch-pxa/htcuniversal-gpio.h @@ -5630,10 +5630,10 @@ Index: linux-2.6.23/include/asm-arm/arch-pxa/htcuniversal-gpio.h +#define GPIO_NR_HTCUNIVERSAL_I2C_SDA_MD (118 | GPIO_ALT_FN_1_OUT) + +#endif /* _HTCUNIVERSAL_GPIO_H */ -Index: linux-2.6.23/include/asm-arm/arch-pxa/htcuniversal-init.h +Index: linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal-init.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/include/asm-arm/arch-pxa/htcuniversal-init.h 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal-init.h 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,14 @@ +/* + * include/asm/arm/arch-pxa/htcuniversal-init.h @@ -5649,18 +5649,18 @@ Index: linux-2.6.23/include/asm-arm/arch-pxa/htcuniversal-init.h + +#endif /* _HTCUNIVERSAL_INIT_H_ */ + -Index: linux-2.6.23/include/asm-arm/arch-pxa/htcuniversal.h +Index: linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/include/asm-arm/arch-pxa/htcuniversal.h 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/include/asm-arm/arch-pxa/htcuniversal.h 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,3 @@ +#include <asm/arch/irqs.h> + +#define HTCUNIVERSAL_ASIC3_IRQ_BASE IRQ_BOARD_START -Index: linux-2.6.23/include/asm-arm/arch-pxa/pxa-pm_ll.h +Index: linux-2.6.24/include/asm-arm/arch-pxa/pxa-pm_ll.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/include/asm-arm/arch-pxa/pxa-pm_ll.h 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/include/asm-arm/arch-pxa/pxa-pm_ll.h 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,6 @@ +struct pxa_ll_pm_ops { + void (*suspend)(unsigned long); @@ -5668,10 +5668,10 @@ Index: linux-2.6.23/include/asm-arm/arch-pxa/pxa-pm_ll.h +}; + +extern struct pxa_ll_pm_ops *pxa_pm_set_ll_ops(struct pxa_ll_pm_ops *new_ops); -Index: linux-2.6.23/include/asm-arm/hardware/asic3_keys.h +Index: linux-2.6.24/include/asm-arm/hardware/asic3_keys.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/include/asm-arm/hardware/asic3_keys.h 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/include/asm-arm/hardware/asic3_keys.h 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,18 @@ +#include <linux/input.h> + @@ -5691,10 +5691,10 @@ Index: linux-2.6.23/include/asm-arm/hardware/asic3_keys.h + struct input_dev *input; + struct device *asic3_dev; +}; -Index: linux-2.6.23/include/asm-arm/hardware/asic3_leds.h +Index: linux-2.6.24/include/asm-arm/hardware/asic3_leds.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/include/asm-arm/hardware/asic3_leds.h 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/include/asm-arm/hardware/asic3_leds.h 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,34 @@ +/* + * LEDs support for HTC ASIC3 devices. @@ -5730,10 +5730,10 @@ Index: linux-2.6.23/include/asm-arm/hardware/asic3_leds.h +extern int asic3_leds_register(void); +extern void asic3_leds_unregister(void); + -Index: linux-2.6.23/include/asm-arm/hardware/ipaq-asic3.h +Index: linux-2.6.24/include/asm-arm/hardware/ipaq-asic3.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/include/asm-arm/hardware/ipaq-asic3.h 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/include/asm-arm/hardware/ipaq-asic3.h 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,602 @@ +/* + * @@ -6337,10 +6337,10 @@ Index: linux-2.6.23/include/asm-arm/hardware/ipaq-asic3.h +#define IPAQ_ASIC3_MAP_SIZE 0x2000 + +#endif -Index: linux-2.6.23/include/linux/gpiodev.h +Index: linux-2.6.24/include/linux/gpiodev.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/include/linux/gpiodev.h 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/include/linux/gpiodev.h 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,44 @@ +#ifndef __GPIODEV_H +#define __GPIODEV_H @@ -6386,10 +6386,10 @@ Index: linux-2.6.23/include/linux/gpiodev.h +} + +#endif /* __GPIODEV_H */ -Index: linux-2.6.23/include/linux/input_pda.h +Index: linux-2.6.24/include/linux/input_pda.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/include/linux/input_pda.h 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/include/linux/input_pda.h 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,47 @@ +#ifndef _INPUT_PDA_H +#define _INPUT_PDA_H @@ -6438,10 +6438,10 @@ Index: linux-2.6.23/include/linux/input_pda.h +#define _KEY_HOMEPAGE _KEY_APP4 + +#endif -Index: linux-2.6.23/include/linux/soc/asic3_base.h +Index: linux-2.6.24/include/linux/soc/asic3_base.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/include/linux/soc/asic3_base.h 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/include/linux/soc/asic3_base.h 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,104 @@ +#include <asm/types.h> +#include <linux/gpiodev.h> @@ -6547,10 +6547,10 @@ Index: linux-2.6.23/include/linux/soc/asic3_base.h + + struct tmio_mmc_hwconfig *tmio_mmc_hwconfig; +}; -Index: linux-2.6.23/include/linux/soc/tmio_mmc.h +Index: linux-2.6.24/include/linux/soc/tmio_mmc.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/include/linux/soc/tmio_mmc.h 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/include/linux/soc/tmio_mmc.h 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,17 @@ +#include <linux/platform_device.h> + @@ -6569,10 +6569,10 @@ Index: linux-2.6.23/include/linux/soc/tmio_mmc.h + int (*mmc_get_ro)(struct platform_device *pdev); + short address_shift; +}; -Index: linux-2.6.23/include/asm-arm/arch-pxa/pxa-regs.h +Index: linux-2.6.24/include/asm-arm/arch-pxa/pxa-regs.h =================================================================== ---- linux-2.6.23.orig/include/asm-arm/arch-pxa/pxa-regs.h 2008-01-20 18:59:40.000000000 +0000 -+++ linux-2.6.23/include/asm-arm/arch-pxa/pxa-regs.h 2008-01-20 18:59:46.000000000 +0000 +--- linux-2.6.24.orig/include/asm-arm/arch-pxa/pxa-regs.h 2008-03-10 16:07:59.000000000 +0000 ++++ linux-2.6.24/include/asm-arm/arch-pxa/pxa-regs.h 2008-03-10 16:09:23.000000000 +0000 @@ -2058,6 +2058,8 @@ #define LDCMD_SOFINT (1 << 22) #define LDCMD_EOFINT (1 << 21) @@ -6582,25 +6582,11 @@ Index: linux-2.6.23/include/asm-arm/arch-pxa/pxa-regs.h #define LCCR5_SOFM1 (1<<0) /* Start Of Frame Mask for Overlay 1 (channel 1) */ #define LCCR5_SOFM2 (1<<1) /* Start Of Frame Mask for Overlay 2 (channel 2) */ -Index: linux-2.6.23/drivers/mmc/host/Kconfig -=================================================================== ---- linux-2.6.23.orig/drivers/mmc/host/Kconfig 2008-01-20 18:59:18.000000000 +0000 -+++ linux-2.6.23/drivers/mmc/host/Kconfig 2008-01-20 18:59:46.000000000 +0000 -@@ -130,3 +130,9 @@ config MMC_SPI - - If unsure, or if your system has no SPI master driver, say N. - -+config MMC_ASIC3 -+ tristate "HTC ASIC3 SD/MMC support" -+ depends on MMC && HTC_ASIC3 -+ help -+ This provides support for the ASIC3 SD/MMC controller, used -+ in the iPAQ hx4700 and others. -Index: linux-2.6.23/drivers/mmc/host/Makefile +Index: linux-2.6.24/drivers/mmc/host/Makefile =================================================================== ---- linux-2.6.23.orig/drivers/mmc/host/Makefile 2008-01-20 18:59:18.000000000 +0000 -+++ linux-2.6.23/drivers/mmc/host/Makefile 2008-01-20 21:12:10.000000000 +0000 -@@ -13,6 +13,7 @@ obj-$(CONFIG_MMC_SDHCI) += sdhci.o +--- linux-2.6.24.orig/drivers/mmc/host/Makefile 2008-01-24 22:58:37.000000000 +0000 ++++ linux-2.6.24/drivers/mmc/host/Makefile 2008-03-10 16:09:23.000000000 +0000 +@@ -13,6 +13,7 @@ obj-$(CONFIG_MMC_RICOH_MMC) += ricoh_mmc.o obj-$(CONFIG_MMC_WBSD) += wbsd.o obj-$(CONFIG_MMC_AU1X) += au1xmmc.o @@ -6608,10 +6594,10 @@ Index: linux-2.6.23/drivers/mmc/host/Makefile obj-$(CONFIG_MMC_OMAP) += omap.o obj-$(CONFIG_MMC_AT91) += at91_mci.o obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o -Index: linux-2.6.23/drivers/mmc/host/asic3_mmc.c +Index: linux-2.6.24/drivers/mmc/host/asic3_mmc.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/drivers/mmc/host/asic3_mmc.c 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/drivers/mmc/host/asic3_mmc.c 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,900 @@ +/* Note that this driver can likely be merged into the tmio driver, so + * consider this code temporary. It works, though. @@ -7513,10 +7499,10 @@ Index: linux-2.6.23/drivers/mmc/host/asic3_mmc.c +MODULE_AUTHOR("Aric Blumer, SDG Systems, LLC"); +MODULE_LICENSE("GPL"); + -Index: linux-2.6.23/drivers/mmc/host/asic3_mmc.h +Index: linux-2.6.24/drivers/mmc/host/asic3_mmc.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/drivers/mmc/host/asic3_mmc.h 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/drivers/mmc/host/asic3_mmc.h 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,25 @@ +#ifndef __ASIC3_MMC_H +#define __ASIC3_MMC_H @@ -7543,22 +7529,10 @@ Index: linux-2.6.23/drivers/mmc/host/asic3_mmc.h +#define DONT_CARE_BUFFER_BITS ( SD_CTRL_INTMASKBUFFER_UNK7 | SD_CTRL_INTMASKBUFFER_CMD_BUSY ) + +#endif // __ASIC3_MMC_H -Index: linux-2.6.23/drivers/input/keyboard/Makefile -=================================================================== ---- linux-2.6.23.orig/drivers/input/keyboard/Makefile 2008-01-20 18:59:16.000000000 +0000 -+++ linux-2.6.23/drivers/input/keyboard/Makefile 2008-01-20 21:11:40.000000000 +0000 -@@ -15,6 +15,7 @@ obj-$(CONFIG_KEYBOARD_NEWTON) += newton - obj-$(CONFIG_KEYBOARD_STOWAWAY) += stowaway.o - obj-$(CONFIG_KEYBOARD_CORGI) += corgikbd.o - obj-$(CONFIG_KEYBOARD_SPITZ) += spitzkbd.o -+obj-$(CONFIG_KEYBOARD_ASIC3) += asic3_keys.o - obj-$(CONFIG_KEYBOARD_HIL) += hil_kbd.o - obj-$(CONFIG_KEYBOARD_HIL_OLD) += hilkbd.o - obj-$(CONFIG_KEYBOARD_OMAP) += omap-keypad.o -Index: linux-2.6.23/drivers/input/keyboard/asic3_keys.c +Index: linux-2.6.24/drivers/input/keyboard/asic3_keys.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/drivers/input/keyboard/asic3_keys.c 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/drivers/input/keyboard/asic3_keys.c 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,131 @@ +/* + * Generic buttons driver for ASIC3 SoC. @@ -7691,10 +7665,10 @@ Index: linux-2.6.23/drivers/input/keyboard/asic3_keys.c +MODULE_AUTHOR("Joshua Wise, Pawel Kolodziejski, Paul Sokolovsky"); +MODULE_DESCRIPTION("Buttons driver for HTC ASIC3 SoC"); +MODULE_LICENSE("GPL"); -Index: linux-2.6.23/include/asm-arm/arch-pxa/irqs.h +Index: linux-2.6.24/include/asm-arm/arch-pxa/irqs.h =================================================================== ---- linux-2.6.23.orig/include/asm-arm/arch-pxa/irqs.h 2008-01-20 18:59:28.000000000 +0000 -+++ linux-2.6.23/include/asm-arm/arch-pxa/irqs.h 2008-01-20 18:59:46.000000000 +0000 +--- linux-2.6.24.orig/include/asm-arm/arch-pxa/irqs.h 2008-01-24 22:58:37.000000000 +0000 ++++ linux-2.6.24/include/asm-arm/arch-pxa/irqs.h 2008-03-10 16:09:23.000000000 +0000 @@ -182,6 +182,8 @@ defined(CONFIG_MACH_LOGICPD_PXA270) || \ defined(CONFIG_MACH_MAINSTONE) @@ -7704,22 +7678,10 @@ Index: linux-2.6.23/include/asm-arm/arch-pxa/irqs.h #else #define NR_IRQS (IRQ_BOARD_START) #endif -Index: linux-2.6.23/include/linux/ioport.h -=================================================================== ---- linux-2.6.23.orig/include/linux/ioport.h 2008-01-20 18:59:31.000000000 +0000 -+++ linux-2.6.23/include/linux/ioport.h 2008-01-20 18:59:46.000000000 +0000 -@@ -56,6 +56,7 @@ struct resource_list { - #define IORESOURCE_IRQ_HIGHLEVEL (1<<2) - #define IORESOURCE_IRQ_LOWLEVEL (1<<3) - #define IORESOURCE_IRQ_SHAREABLE (1<<4) -+#define IORESOURCE_IRQ_SOC_SUBDEVICE (1<<5) - - /* ISA PnP DMA specific bits (IORESOURCE_BITS) */ - #define IORESOURCE_DMA_TYPE_MASK (3<<0) -Index: linux-2.6.23/include/asm-arm/arch-pxa/serial.h +Index: linux-2.6.24/include/asm-arm/arch-pxa/serial.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.23/include/asm-arm/arch-pxa/serial.h 2008-01-20 18:59:46.000000000 +0000 ++++ linux-2.6.24/include/asm-arm/arch-pxa/serial.h 2008-03-10 16:09:23.000000000 +0000 @@ -0,0 +1,78 @@ +/* + * linux/include/asm-arm/arch-pxa/serial.h @@ -7799,10 +7761,10 @@ Index: linux-2.6.23/include/asm-arm/arch-pxa/serial.h +void pxa_set_btuart_info(struct platform_pxa_serial_funcs *btuart_funcs); +void pxa_set_stuart_info(struct platform_pxa_serial_funcs *stuart_funcs); +void pxa_set_hwuart_info(struct platform_pxa_serial_funcs *hwuart_funcs); -Index: linux-2.6.23/drivers/serial/pxa.c +Index: linux-2.6.24/drivers/serial/pxa.c =================================================================== ---- linux-2.6.23.orig/drivers/serial/pxa.c 2008-01-20 18:59:23.000000000 +0000 -+++ linux-2.6.23/drivers/serial/pxa.c 2008-01-20 18:59:46.000000000 +0000 +--- linux-2.6.24.orig/drivers/serial/pxa.c 2008-01-24 22:58:37.000000000 +0000 ++++ linux-2.6.24/drivers/serial/pxa.c 2008-03-10 16:09:23.000000000 +0000 @@ -47,6 +47,7 @@ #include <asm/io.h> #include <asm/hardware.h> @@ -7811,7 +7773,7 @@ Index: linux-2.6.23/drivers/serial/pxa.c #include <asm/arch/pxa-regs.h> -@@ -60,6 +61,14 @@ struct uart_pxa_port { +@@ -60,6 +61,14 @@ char *name; }; @@ -7826,7 +7788,7 @@ Index: linux-2.6.23/drivers/serial/pxa.c static inline unsigned int serial_in(struct uart_pxa_port *up, int offset) { offset <<= 2; -@@ -347,6 +356,9 @@ static int serial_pxa_startup(struct uar +@@ -347,6 +356,9 @@ unsigned long flags; int retval; @@ -7836,7 +7798,7 @@ Index: linux-2.6.23/drivers/serial/pxa.c if (port->line == 3) /* HWUART */ up->mcr |= UART_MCR_AFE; else -@@ -404,6 +416,12 @@ static int serial_pxa_startup(struct uar +@@ -404,6 +416,12 @@ (void) serial_in(up, UART_IIR); (void) serial_in(up, UART_MSR); @@ -7849,7 +7811,7 @@ Index: linux-2.6.23/drivers/serial/pxa.c return 0; } -@@ -412,6 +430,8 @@ static void serial_pxa_shutdown(struct u +@@ -412,6 +430,8 @@ struct uart_pxa_port *up = (struct uart_pxa_port *)port; unsigned long flags; @@ -7858,7 +7820,7 @@ Index: linux-2.6.23/drivers/serial/pxa.c free_irq(up->port.irq, up); /* -@@ -433,6 +453,8 @@ static void serial_pxa_shutdown(struct u +@@ -433,6 +453,8 @@ UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); serial_out(up, UART_FCR, 0); @@ -7867,10 +7829,10 @@ Index: linux-2.6.23/drivers/serial/pxa.c } static void -Index: linux-2.6.23/arch/arm/mach-pxa/generic.c +Index: linux-2.6.24/arch/arm/mach-pxa/generic.c =================================================================== ---- linux-2.6.23.orig/arch/arm/mach-pxa/generic.c 2008-01-20 18:59:09.000000000 +0000 -+++ linux-2.6.23/arch/arm/mach-pxa/generic.c 2008-01-20 18:59:46.000000000 +0000 +--- linux-2.6.24.orig/arch/arm/mach-pxa/generic.c 2008-01-24 22:58:37.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/generic.c 2008-03-10 16:09:23.000000000 +0000 @@ -38,6 +38,7 @@ #include <asm/arch/mmc.h> #include <asm/arch/irda.h> @@ -7879,7 +7841,7 @@ Index: linux-2.6.23/arch/arm/mach-pxa/generic.c #include "devices.h" #include "generic.h" -@@ -412,6 +413,18 @@ struct platform_device pxa_device_hwuart +@@ -412,6 +413,18 @@ .num_resources = ARRAY_SIZE(pxa_resource_hwuart), }; @@ -7898,11 +7860,11 @@ Index: linux-2.6.23/arch/arm/mach-pxa/generic.c static struct resource pxai2c_resources[] = { { .start = 0x40301680, -Index: linux-2.6.23/drivers/leds/Makefile +Index: linux-2.6.24/drivers/leds/Makefile =================================================================== ---- linux-2.6.23.orig/drivers/leds/Makefile 2008-01-20 18:59:17.000000000 +0000 -+++ linux-2.6.23/drivers/leds/Makefile 2008-01-20 21:10:45.000000000 +0000 -@@ -15,6 +15,7 @@ obj-$(CONFIG_LEDS_AMS_DELTA) += leds-am +--- linux-2.6.24.orig/drivers/leds/Makefile 2008-01-24 22:58:37.000000000 +0000 ++++ linux-2.6.24/drivers/leds/Makefile 2008-03-10 16:09:23.000000000 +0000 +@@ -15,6 +15,7 @@ obj-$(CONFIG_LEDS_NET48XX) += leds-net48xx.o obj-$(CONFIG_LEDS_WRAP) += leds-wrap.o obj-$(CONFIG_LEDS_H1940) += leds-h1940.o @@ -7910,11 +7872,11 @@ Index: linux-2.6.23/drivers/leds/Makefile obj-$(CONFIG_LEDS_COBALT_QUBE) += leds-cobalt-qube.o obj-$(CONFIG_LEDS_COBALT_RAQ) += leds-cobalt-raq.o obj-$(CONFIG_LEDS_GPIO) += leds-gpio.o -Index: linux-2.6.23/drivers/input/keyboard/Kconfig +Index: linux-2.6.24/drivers/input/keyboard/Kconfig =================================================================== ---- linux-2.6.23.orig/drivers/input/keyboard/Kconfig 2008-01-20 18:59:16.000000000 +0000 -+++ linux-2.6.23/drivers/input/keyboard/Kconfig 2008-01-20 18:59:46.000000000 +0000 -@@ -293,4 +293,11 @@ config KEYBOARD_BFIN +--- linux-2.6.24.orig/drivers/input/keyboard/Kconfig 2008-01-24 22:58:37.000000000 +0000 ++++ linux-2.6.24/drivers/input/keyboard/Kconfig 2008-03-10 16:09:23.000000000 +0000 +@@ -293,4 +293,11 @@ To compile this driver as a module, choose M here: the module will be called bf54x-keys. @@ -7926,3 +7888,33 @@ Index: linux-2.6.23/drivers/input/keyboard/Kconfig + HTC ASIC3 peripheral controller. + endif +Index: linux-2.6.24/drivers/mmc/host/Kconfig +=================================================================== +--- linux-2.6.24.orig/drivers/mmc/host/Kconfig 2008-01-24 22:58:37.000000000 +0000 ++++ linux-2.6.24/drivers/mmc/host/Kconfig 2008-03-10 16:09:59.000000000 +0000 +@@ -24,6 +24,13 @@ + + If unsure, say N. + ++config MMC_ASIC3 ++ tristate "HTC ASIC3 SD/MMC support" ++ depends on MMC && HTC_ASIC3 ++ help ++ This provides support for the ASIC3 SD/MMC controller, used ++ in the iPAQ hx4700 and others. ++ + config MMC_SDHCI + tristate "Secure Digital Host Controller Interface support (EXPERIMENTAL)" + depends on PCI && EXPERIMENTAL +Index: linux-2.6.24/drivers/input/keyboard/Makefile +=================================================================== +--- linux-2.6.24.orig/drivers/input/keyboard/Makefile 2008-01-24 22:58:37.000000000 +0000 ++++ linux-2.6.24/drivers/input/keyboard/Makefile 2008-03-10 16:10:28.000000000 +0000 +@@ -6,6 +6,7 @@ + + obj-$(CONFIG_KEYBOARD_ATKBD) += atkbd.o + obj-$(CONFIG_KEYBOARD_SUNKBD) += sunkbd.o ++obj-$(CONFIG_KEYBOARD_ASIC3) += asic3_keys.o + obj-$(CONFIG_KEYBOARD_LKKBD) += lkkbd.o + obj-$(CONFIG_KEYBOARD_XTKBD) += xtkbd.o + obj-$(CONFIG_KEYBOARD_AMIGA) += amikbd.o diff --git a/packages/linux/linux-rp-2.6.24/sharpsl-rc-r1.patch b/packages/linux/linux-rp-2.6.24/sharpsl-rc-r1.patch index 453010a197..32a94c7cea 100644 --- a/packages/linux/linux-rp-2.6.24/sharpsl-rc-r1.patch +++ b/packages/linux/linux-rp-2.6.24/sharpsl-rc-r1.patch @@ -1,7 +1,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/spitz.c =================================================================== ---- linux-2.6.24.orig/arch/arm/mach-pxa/spitz.c 2008-01-27 02:10:17.000000000 +0000 -+++ linux-2.6.24/arch/arm/mach-pxa/spitz.c 2008-01-27 02:10:52.000000000 +0000 +--- linux-2.6.24.orig/arch/arm/mach-pxa/spitz.c 2008-03-10 17:05:37.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/spitz.c 2008-03-10 17:05:55.000000000 +0000 @@ -259,6 +259,13 @@ .id = -1, }; @@ -26,8 +26,8 @@ Index: linux-2.6.24/arch/arm/mach-pxa/spitz.c &spitzled_device, Index: linux-2.6.24/drivers/input/keyboard/Kconfig =================================================================== ---- linux-2.6.24.orig/drivers/input/keyboard/Kconfig 2008-01-27 02:10:20.000000000 +0000 -+++ linux-2.6.24/drivers/input/keyboard/Kconfig 2008-01-27 02:10:52.000000000 +0000 +--- linux-2.6.24.orig/drivers/input/keyboard/Kconfig 2008-03-10 17:05:40.000000000 +0000 ++++ linux-2.6.24/drivers/input/keyboard/Kconfig 2008-03-10 17:05:55.000000000 +0000 @@ -154,6 +154,17 @@ To compile this driver as a module, choose M here: the module will be called spitzkbd. @@ -48,20 +48,18 @@ Index: linux-2.6.24/drivers/input/keyboard/Kconfig depends on AMIGA Index: linux-2.6.24/drivers/input/keyboard/Makefile =================================================================== ---- linux-2.6.24.orig/drivers/input/keyboard/Makefile 2008-01-27 02:10:20.000000000 +0000 -+++ linux-2.6.24/drivers/input/keyboard/Makefile 2008-01-27 02:11:43.000000000 +0000 -@@ -15,6 +15,7 @@ - obj-$(CONFIG_KEYBOARD_STOWAWAY) += stowaway.o - obj-$(CONFIG_KEYBOARD_CORGI) += corgikbd.o - obj-$(CONFIG_KEYBOARD_SPITZ) += spitzkbd.o +--- linux-2.6.24.orig/drivers/input/keyboard/Makefile 2008-03-10 17:05:40.000000000 +0000 ++++ linux-2.6.24/drivers/input/keyboard/Makefile 2008-03-10 17:06:17.000000000 +0000 +@@ -26,3 +26,5 @@ + obj-$(CONFIG_KEYBOARD_HP7XX) += jornada720_kbd.o + obj-$(CONFIG_KEYBOARD_MAPLE) += maple_keyb.o + obj-$(CONFIG_KEYBOARD_BFIN) += bf54x-keys.o +obj-$(CONFIG_SHARPSL_RC) += sharpsl_rc.o - obj-$(CONFIG_KEYBOARD_ASIC3) += asic3_keys.o - obj-$(CONFIG_KEYBOARD_HIL) += hil_kbd.o - obj-$(CONFIG_KEYBOARD_HIL_OLD) += hilkbd.o ++ Index: linux-2.6.24/drivers/input/keyboard/sharpsl_rc.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.24/drivers/input/keyboard/sharpsl_rc.c 2008-01-27 02:10:52.000000000 +0000 ++++ linux-2.6.24/drivers/input/keyboard/sharpsl_rc.c 2008-03-10 17:05:55.000000000 +0000 @@ -0,0 +1,291 @@ +/* + * Keyboard driver for Sharp Clamshell Models (SL-Cxx00) @@ -357,7 +355,7 @@ Index: linux-2.6.24/drivers/input/keyboard/sharpsl_rc.c Index: linux-2.6.24/drivers/input/keyboard/spitzkbd.c =================================================================== --- linux-2.6.24.orig/drivers/input/keyboard/spitzkbd.c 2008-01-24 22:58:37.000000000 +0000 -+++ linux-2.6.24/drivers/input/keyboard/spitzkbd.c 2008-01-27 02:10:52.000000000 +0000 ++++ linux-2.6.24/drivers/input/keyboard/spitzkbd.c 2008-03-10 17:05:55.000000000 +0000 @@ -19,6 +19,7 @@ #include <linux/jiffies.h> #include <linux/module.h> @@ -440,8 +438,8 @@ Index: linux-2.6.24/drivers/input/keyboard/spitzkbd.c del_timer_sync(&spitzkbd->htimer); Index: linux-2.6.24/arch/arm/mach-pxa/sharpsl.h =================================================================== ---- linux-2.6.24.orig/arch/arm/mach-pxa/sharpsl.h 2008-01-27 02:10:15.000000000 +0000 -+++ linux-2.6.24/arch/arm/mach-pxa/sharpsl.h 2008-01-27 02:10:52.000000000 +0000 +--- linux-2.6.24.orig/arch/arm/mach-pxa/sharpsl.h 2008-03-10 17:05:35.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/sharpsl.h 2008-03-10 17:05:55.000000000 +0000 @@ -37,15 +37,10 @@ */ #define READ_GPIO_BIT(x) (GPLR(x) & GPIO_bit(x)) @@ -462,7 +460,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/sharpsl.h Index: linux-2.6.24/arch/arm/mach-pxa/sharpsl_pm.c =================================================================== --- linux-2.6.24.orig/arch/arm/mach-pxa/sharpsl_pm.c 2008-01-24 22:58:37.000000000 +0000 -+++ linux-2.6.24/arch/arm/mach-pxa/sharpsl_pm.c 2008-01-27 02:10:52.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/sharpsl_pm.c 2008-03-10 17:05:55.000000000 +0000 @@ -135,6 +135,8 @@ | MAXCTRL_SGL | MAXCTRL_UNI | MAXCTRL_STR); } @@ -475,7 +473,7 @@ Index: linux-2.6.24/arch/arm/mach-pxa/sharpsl_pm.c Index: linux-2.6.24/include/asm-arm/hardware/sharpsl_pm.h =================================================================== --- linux-2.6.24.orig/include/asm-arm/hardware/sharpsl_pm.h 2008-01-24 22:58:37.000000000 +0000 -+++ linux-2.6.24/include/asm-arm/hardware/sharpsl_pm.h 2008-01-27 02:10:52.000000000 +0000 ++++ linux-2.6.24/include/asm-arm/hardware/sharpsl_pm.h 2008-03-10 17:05:55.000000000 +0000 @@ -104,3 +104,10 @@ irqreturn_t sharpsl_chrg_full_isr(int irq, void *dev_id); irqreturn_t sharpsl_fatal_isr(int irq, void *dev_id); @@ -490,7 +488,7 @@ Index: linux-2.6.24/include/asm-arm/hardware/sharpsl_pm.h Index: linux-2.6.24/include/linux/input.h =================================================================== --- linux-2.6.24.orig/include/linux/input.h 2008-01-24 22:58:37.000000000 +0000 -+++ linux-2.6.24/include/linux/input.h 2008-01-27 02:10:52.000000000 +0000 ++++ linux-2.6.24/include/linux/input.h 2008-03-10 17:05:55.000000000 +0000 @@ -636,6 +636,7 @@ #define SW_TABLET_MODE 0x01 /* set = tablet mode */ #define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ @@ -501,8 +499,8 @@ Index: linux-2.6.24/include/linux/input.h Index: linux-2.6.24/arch/arm/mach-pxa/spitz_pm.c =================================================================== ---- linux-2.6.24.orig/arch/arm/mach-pxa/spitz_pm.c 2008-01-24 22:58:37.000000000 +0000 -+++ linux-2.6.24/arch/arm/mach-pxa/spitz_pm.c 2008-01-27 02:10:52.000000000 +0000 +--- linux-2.6.24.orig/arch/arm/mach-pxa/spitz_pm.c 2008-03-10 17:05:40.000000000 +0000 ++++ linux-2.6.24/arch/arm/mach-pxa/spitz_pm.c 2008-03-10 17:05:55.000000000 +0000 @@ -162,6 +162,13 @@ if (resume_on_alarm && (PEDR & PWER_RTC)) is_resume |= PWER_RTC; diff --git a/packages/linux/linux-rp-2.6.24/tosa/.mtn2git_empty b/packages/linux/linux-rp-2.6.24/tosa/.mtn2git_empty new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/.mtn2git_empty diff --git a/packages/linux/linux-rp-2.6.24/tosa/0001-Allow-runtime-registration-of-regions-of-memory-that.patch b/packages/linux/linux-rp-2.6.24/tosa/0001-Allow-runtime-registration-of-regions-of-memory-that.patch new file mode 100644 index 0000000000..ba79b4a470 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0001-Allow-runtime-registration-of-regions-of-memory-that.patch @@ -0,0 +1,201 @@ +From d48a09b301d9a460d5ce027433e8cb8872e7b5c3 Mon Sep 17 00:00:00 2001 +From: Ian Molton <spyro@f2s.com> +Date: Fri, 4 Jan 2008 18:26:38 +0000 +Subject: [PATCH 01/64] Allow runtime registration of regions of memory that require dma bouncing. + +--- + arch/arm/common/Kconfig | 4 ++ + arch/arm/common/dmabounce.c | 82 ++++++++++++++++++++++++++++++++++++- + arch/arm/common/sa1111.c | 2 +- + arch/arm/mach-ixp4xx/Kconfig | 1 + + arch/arm/mach-ixp4xx/common-pci.c | 2 +- + 5 files changed, 87 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig +index 3e07346..5f357fb 100644 +--- a/arch/arm/common/Kconfig ++++ b/arch/arm/common/Kconfig +@@ -13,10 +13,14 @@ config ICST307 + config SA1111 + bool + select DMABOUNCE ++ select PLATFORM_DMABOUNCE + + config DMABOUNCE + bool + ++config PLATFORM_DMABOUNCE ++ bool ++ + config TIMER_ACORN + bool + +diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c +index 52fc6a8..ed80abe 100644 +--- a/arch/arm/common/dmabounce.c ++++ b/arch/arm/common/dmabounce.c +@@ -16,6 +16,7 @@ + * + * Copyright (C) 2002 Hewlett Packard Company. + * Copyright (C) 2004 MontaVista Software, Inc. ++ * Copyright (C) 2007 Dmitry Baryshkov <dbaryshkov@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License +@@ -24,6 +25,7 @@ + + #include <linux/module.h> + #include <linux/init.h> ++#include <linux/rwsem.h> + #include <linux/slab.h> + #include <linux/device.h> + #include <linux/dma-mapping.h> +@@ -80,6 +82,80 @@ struct dmabounce_device_info { + rwlock_t lock; + }; + ++struct dmabounce_check_entry { ++ struct list_head list; ++ dmabounce_check checker; ++ void *data; ++}; ++ ++static struct list_head checkers = LIST_HEAD_INIT(checkers); ++static rwlock_t checkers_lock = RW_LOCK_UNLOCKED; ++ ++int ++dmabounce_register_checker(dmabounce_check function, void *data) ++{ ++ unsigned long flags; ++ struct dmabounce_check_entry *entry = ++ kzalloc(sizeof(struct dmabounce_check_entry), GFP_ATOMIC); ++ ++ if (!entry) ++ return ENOMEM; ++ ++ INIT_LIST_HEAD(&entry->list); ++ entry->checker = function; ++ entry->data = data; ++ ++ write_lock_irqsave(&checkers_lock, flags); ++ list_add(&entry->list, &checkers); ++ write_unlock_irqrestore(&checkers_lock, flags); ++ ++ return 0; ++} ++ ++void ++dmabounce_remove_checker(dmabounce_check function, void *data) ++{ ++ unsigned long flags; ++ struct list_head *pos; ++ ++ write_lock_irqsave(&checkers_lock, flags); ++ __list_for_each(pos, &checkers) { ++ struct dmabounce_check_entry *entry = container_of(pos, ++ struct dmabounce_check_entry, list); ++ if (entry->checker == function && entry->data == data) { ++ list_del(pos); ++ write_unlock_irqrestore(&checkers_lock, flags); ++ kfree(entry); ++ return; ++ } ++ } ++ ++ write_unlock_irqrestore(&checkers_lock, flags); ++ printk(KERN_WARNING "dmabounce checker not found: %p\n", function); ++} ++ ++static int dma_needs_bounce(struct device *dev, dma_addr_t dma, size_t size) ++{ ++ unsigned long flags; ++ struct list_head *pos; ++ ++ read_lock_irqsave(&checkers_lock, flags); ++ __list_for_each(pos, &checkers) { ++ struct dmabounce_check_entry *entry = container_of(pos, ++ struct dmabounce_check_entry, list); ++ if (entry->checker(dev, dma, size, entry->data)) { ++ read_unlock_irqrestore(&checkers_lock, flags); ++ return 1; ++ } ++ } ++ ++ read_unlock_irqrestore(&checkers_lock, flags); ++#ifdef CONFIG_PLATFORM_DMABOUNCE ++ return platform_dma_needs_bounce(dev, dma, size); ++#else ++ return 0; ++#endif ++} + #ifdef STATS + static ssize_t dmabounce_show(struct device *dev, struct device_attribute *attr, + char *buf) +@@ -239,7 +315,7 @@ map_single(struct device *dev, void *ptr, size_t size, + struct safe_buffer *buf; + + buf = alloc_safe_buffer(device_info, ptr, size, dir); +- if (buf == 0) { ++ if (buf == NULL) { + dev_err(dev, "%s: unable to map unsafe buffer %p!\n", + __func__, ptr); + return 0; +@@ -643,7 +719,6 @@ dmabounce_unregister_dev(struct device *dev) + dev->bus_id, dev->bus->name); + } + +- + EXPORT_SYMBOL(dma_map_single); + EXPORT_SYMBOL(dma_unmap_single); + EXPORT_SYMBOL(dma_map_sg); +@@ -653,6 +728,9 @@ EXPORT_SYMBOL(dma_sync_single_for_device); + EXPORT_SYMBOL(dma_sync_sg); + EXPORT_SYMBOL(dmabounce_register_dev); + EXPORT_SYMBOL(dmabounce_unregister_dev); ++EXPORT_SYMBOL(dmabounce_register_checker); ++EXPORT_SYMBOL(dmabounce_remove_checker); ++ + + MODULE_AUTHOR("Christopher Hoover <ch@hpl.hp.com>, Deepak Saxena <dsaxena@plexity.net>"); + MODULE_DESCRIPTION("Special dma_{map/unmap/dma_sync}_* routines for systems with limited DMA windows"); +diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c +index eb06d0b..3b8fbdd 100644 +--- a/arch/arm/common/sa1111.c ++++ b/arch/arm/common/sa1111.c +@@ -778,7 +778,7 @@ static void __sa1111_remove(struct sa1111 *sachip) + * This should only get called for sa1111_device types due to the + * way we configure our device dma_masks. + */ +-int dma_needs_bounce(struct device *dev, dma_addr_t addr, size_t size) ++int platform_dma_needs_bounce(struct device *dev, dma_addr_t addr, size_t size) + { + /* + * Section 4.6 of the "Intel StrongARM SA-1111 Development Module +diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig +index 61b2dfc..5870371 100644 +--- a/arch/arm/mach-ixp4xx/Kconfig ++++ b/arch/arm/mach-ixp4xx/Kconfig +@@ -161,6 +161,7 @@ comment "IXP4xx Options" + config DMABOUNCE + bool + default y ++ select PLATFORM_DMABOUNCE + depends on PCI + + config IXP4XX_INDIRECT_PCI +diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c +index bf04121..ac46492 100644 +--- a/arch/arm/mach-ixp4xx/common-pci.c ++++ b/arch/arm/mach-ixp4xx/common-pci.c +@@ -336,7 +336,7 @@ static int ixp4xx_pci_platform_notify_remove(struct device *dev) + return 0; + } + +-int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) ++int platform_dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) + { + return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M); + } +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0002-Modify-dma_alloc_coherent-on-ARM-so-that-it-supports.patch b/packages/linux/linux-rp-2.6.24/tosa/0002-Modify-dma_alloc_coherent-on-ARM-so-that-it-supports.patch new file mode 100644 index 0000000000..a562ef921b --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0002-Modify-dma_alloc_coherent-on-ARM-so-that-it-supports.patch @@ -0,0 +1,260 @@ +From 8e95f90487d2fb46fd862744ddb34f47c30b0c5a Mon Sep 17 00:00:00 2001 +From: Ian Molton <spyro@f2s.com> +Date: Fri, 4 Jan 2008 18:27:50 +0000 +Subject: [PATCH 02/64] Modify dma_alloc_coherent on ARM so that it supports device local DMA. + +--- + arch/arm/mm/consistent.c | 125 +++++++++++++++++++++++++++++++++++++++++ + include/asm-arm/dma-mapping.h | 37 +++++++------ + 2 files changed, 145 insertions(+), 17 deletions(-) + +diff --git a/arch/arm/mm/consistent.c b/arch/arm/mm/consistent.c +index 333a82a..3da0f94 100644 +--- a/arch/arm/mm/consistent.c ++++ b/arch/arm/mm/consistent.c +@@ -3,6 +3,8 @@ + * + * Copyright (C) 2000-2004 Russell King + * ++ * Device local coherent memory support added by Ian Molton (spyro@f2s.com) ++ * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +@@ -20,6 +22,7 @@ + + #include <asm/memory.h> + #include <asm/cacheflush.h> ++#include <asm/io.h> + #include <asm/tlbflush.h> + #include <asm/sizes.h> + +@@ -35,6 +38,13 @@ + #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT) + #define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT) + ++struct dma_coherent_mem { ++ void *virt_base; ++ u32 device_base; ++ int size; ++ int flags; ++ unsigned long *bitmap; ++}; + + /* + * These are the page tables (2MB each) covering uncached, DMA consistent allocations +@@ -153,6 +163,13 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, + unsigned long order; + u64 mask = ISA_DMA_THRESHOLD, limit; + ++ /* Following is a work-around (a.k.a. hack) to prevent pages ++ * with __GFP_COMP being passed to split_page() which cannot ++ * handle them. The real problem is that this flag probably ++ * should be 0 on ARM as it is not supported on this ++ * platform--see CONFIG_HUGETLB_PAGE. */ ++ gfp &= ~(__GFP_COMP); ++ + if (!consistent_pte[0]) { + printk(KERN_ERR "%s: not initialised\n", __func__); + dump_stack(); +@@ -160,6 +177,26 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, + } + + if (dev) { ++ ++ if (dev->dma_mem) { ++ unsigned long flags; ++ int pgnum; ++ void *ret; ++ ++ spin_lock_irqsave(&consistent_lock, flags); ++ pgnum = bitmap_find_free_region(dev->dma_mem->bitmap, ++ dev->dma_mem->size, ++ get_order(size)); ++ spin_unlock_irqrestore(&consistent_lock, flags); ++ ++ if (pgnum >= 0) { ++ *handle = dev->dma_mem->device_base + (pgnum << PAGE_SHIFT); ++ ret = dev->dma_mem->virt_base + (pgnum << PAGE_SHIFT); ++ memset(ret, 0, size); ++ return ret; ++ } ++ } ++ + mask = dev->coherent_dma_mask; + + /* +@@ -177,6 +214,9 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, + mask, (unsigned long long)ISA_DMA_THRESHOLD); + goto no_page; + } ++ ++ if (dev->dma_mem && dev->dma_mem->flags & DMA_MEMORY_EXCLUSIVE) ++ return NULL; + } + + /* +@@ -359,6 +399,8 @@ void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr + pte_t *ptep; + int idx; + u32 off; ++ struct dma_coherent_mem *mem = dev ? dev->dma_mem : NULL; ++ unsigned long order; + + WARN_ON(irqs_disabled()); + +@@ -368,6 +410,15 @@ void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr + } + + size = PAGE_ALIGN(size); ++ order = get_order(size); ++ ++ /* What if mem is valid and the range is not? */ ++ if (mem && cpu_addr >= mem->virt_base && cpu_addr < (mem->virt_base + (mem->size << PAGE_SHIFT))) { ++ int page = (cpu_addr - mem->virt_base) >> PAGE_SHIFT; ++ ++ bitmap_release_region(mem->bitmap, page, order); ++ return; ++ } + + spin_lock_irqsave(&consistent_lock, flags); + c = vm_region_find(&consistent_head, (unsigned long)cpu_addr); +@@ -437,6 +488,80 @@ void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr + } + EXPORT_SYMBOL(dma_free_coherent); + ++int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, ++ dma_addr_t device_addr, size_t size, int flags) ++{ ++ void __iomem *mem_base; ++ int pages = size >> PAGE_SHIFT; ++ int bitmap_size = (pages + 31)/32; ++ ++ if ((flags & (DMA_MEMORY_MAP | DMA_MEMORY_IO)) == 0) ++ goto out; ++ if (!size) ++ goto out; ++ if (dev->dma_mem) ++ goto out; ++ ++ /* FIXME: this routine just ignores DMA_MEMORY_INCLUDES_CHILDREN */ ++ mem_base = ioremap_nocache(bus_addr, size); ++ if (!mem_base) ++ goto out; ++ ++ dev->dma_mem = kzalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL); ++ if (!dev->dma_mem) ++ goto out; ++ memset(dev->dma_mem, 0, sizeof(struct dma_coherent_mem)); ++ dev->dma_mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL); ++ if (!dev->dma_mem->bitmap) ++ goto free1_out; ++ ++ dev->dma_mem->virt_base = mem_base; ++ dev->dma_mem->device_base = device_addr; ++ dev->dma_mem->size = pages; ++ dev->dma_mem->flags = flags; ++ ++ if (flags & DMA_MEMORY_MAP) ++ return DMA_MEMORY_MAP; ++ ++ return DMA_MEMORY_IO; ++ ++ free1_out: ++ kfree(dev->dma_mem->bitmap); ++ out: ++ return 0; ++} ++EXPORT_SYMBOL(dma_declare_coherent_memory); ++ ++void dma_release_declared_memory(struct device *dev) ++{ ++ struct dma_coherent_mem *mem = dev->dma_mem; ++ ++ if (!mem) ++ return; ++ dev->dma_mem = NULL; ++ kfree(mem->bitmap); ++ kfree(mem); ++} ++EXPORT_SYMBOL(dma_release_declared_memory); ++ ++void *dma_mark_declared_memory_occupied(struct device *dev, ++ dma_addr_t device_addr, size_t size) ++{ ++ struct dma_coherent_mem *mem = dev->dma_mem; ++ int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; ++ int pos, err; ++ ++ if (!mem) ++ return ERR_PTR(-EINVAL); ++ ++ pos = (device_addr - mem->device_base) >> PAGE_SHIFT; ++ err = bitmap_allocate_region(mem->bitmap, pos, get_order(pages)); ++ if (err != 0) ++ return ERR_PTR(err); ++ return mem->virt_base + (pos << PAGE_SHIFT); ++} ++EXPORT_SYMBOL(dma_mark_declared_memory_occupied); ++ + /* + * Initialise the consistent memory allocation. + */ +diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h +index e99406a..f18ba05 100644 +--- a/include/asm-arm/dma-mapping.h ++++ b/include/asm-arm/dma-mapping.h +@@ -7,6 +7,19 @@ + + #include <linux/scatterlist.h> + ++#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY ++extern int ++dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, ++ dma_addr_t device_addr, size_t size, int flags); ++ ++extern void ++dma_release_declared_memory(struct device *dev); ++ ++extern void * ++dma_mark_declared_memory_occupied(struct device *dev, ++ dma_addr_t device_addr, size_t size); ++ ++ + /* + * DMA-consistent mapping functions. These allocate/free a region of + * uncached, unwrite-buffered mapped memory space for use with DMA +@@ -433,23 +446,13 @@ extern int dmabounce_register_dev(struct device *, unsigned long, unsigned long) + */ + extern void dmabounce_unregister_dev(struct device *); + +-/** +- * dma_needs_bounce +- * +- * @dev: valid struct device pointer +- * @dma_handle: dma_handle of unbounced buffer +- * @size: size of region being mapped +- * +- * Platforms that utilize the dmabounce mechanism must implement +- * this function. +- * +- * The dmabounce routines call this function whenever a dma-mapping +- * is requested to determine whether a given buffer needs to be bounced +- * or not. The function must return 0 if the buffer is OK for +- * DMA access and 1 if the buffer needs to be bounced. +- * +- */ +-extern int dma_needs_bounce(struct device*, dma_addr_t, size_t); ++typedef int (*dmabounce_check)(struct device *dev, dma_addr_t dma, size_t size, void *data); ++extern int dmabounce_register_checker(dmabounce_check, void *data); ++extern void dmabounce_remove_checker(dmabounce_check, void *data); ++#ifdef CONFIG_PLATFORM_DMABOUNCE ++extern int platform_dma_needs_bounce(struct device *dev, dma_addr_t dma, size_t size, void *data); ++#endif ++ + #endif /* CONFIG_DMABOUNCE */ + + #endif /* __KERNEL__ */ +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0003-Core-MFD-support.patch b/packages/linux/linux-rp-2.6.24/tosa/0003-Core-MFD-support.patch new file mode 100644 index 0000000000..d84a4f7835 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0003-Core-MFD-support.patch @@ -0,0 +1,243 @@ +From a07910753f9965842b6647f0561db125b538f5ed Mon Sep 17 00:00:00 2001 +From: Ian Molton <spyro@f2s.com> +Date: Fri, 4 Jan 2008 18:32:44 +0000 +Subject: [PATCH 03/64] Core MFD support + +This patch provides a common subdevice registration system for MFD type +chips, using platfrom device. + +It also provides a new resource type for IRQs such that a subdevices IRQ may +be computed based on the MFD cores IRQ handler, since many MFDs provide an IRQ +multiplex. +--- + drivers/mfd/Kconfig | 4 ++ + drivers/mfd/Makefile | 2 + + drivers/mfd/mfd-core.c | 116 ++++++++++++++++++++++++++++++++++++++++++++++ + include/linux/ioport.h | 1 + + include/linux/mfd-core.h | 51 ++++++++++++++++++++ + 5 files changed, 174 insertions(+), 0 deletions(-) + create mode 100644 drivers/mfd/mfd-core.c + create mode 100644 include/linux/mfd-core.h + +diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig +index 2571619..1205c89 100644 +--- a/drivers/mfd/Kconfig ++++ b/drivers/mfd/Kconfig +@@ -5,6 +5,10 @@ + menu "Multifunction device drivers" + depends on HAS_IOMEM + ++config MFD_CORE ++ tristate ++ default n ++ + config MFD_SM501 + tristate "Support for Silicon Motion SM501" + ---help--- +diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile +index 5143209..6c20064 100644 +--- a/drivers/mfd/Makefile ++++ b/drivers/mfd/Makefile +@@ -4,6 +4,8 @@ + + obj-$(CONFIG_MFD_SM501) += sm501.o + ++obj-$(CONFIG_MFD_CORE) += mfd-core.o ++ + obj-$(CONFIG_MCP) += mcp-core.o + obj-$(CONFIG_MCP_SA11X0) += mcp-sa11x0.o + obj-$(CONFIG_MCP_UCB1200) += ucb1x00-core.o +diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c +new file mode 100644 +index 0000000..88874e1 +--- /dev/null ++++ b/drivers/mfd/mfd-core.c +@@ -0,0 +1,116 @@ ++/* ++ * drivers/mfd/mfd-core.c ++ * ++ * core MFD support ++ * Copyright (c) 2006 Ian Molton ++ * Copyright (c) 2007 Dmitry Baryshkov ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/platform_device.h> ++#include <linux/mfd-core.h> ++ ++#define SIGNED_SHIFT(val, shift) ((shift) >= 0 ? \ ++ ((val) << (shift)) : \ ++ ((val) >> -(shift))) ++ ++int mfd_add_devices( ++ struct platform_device *parent, ++ const struct mfd_cell *cells, int n_devs, ++ struct resource *mem, ++ int relative_addr_shift, ++ int irq_base) ++{ ++ int i; ++ ++ for (i = 0; i < n_devs; i++) { ++ struct resource *res = NULL; ++ const struct mfd_cell *cell = cells + i; ++ struct platform_device *pdev; ++ int ret = -ENOMEM; ++ int r; ++ ++ pdev = platform_device_alloc(cell->name, -1); ++ if (!pdev) ++ goto fail_alloc; ++ ++ pdev->dev.uevent_suppress = 0; ++ pdev->dev.parent = &parent->dev; ++ ++ ret = platform_device_add_data(pdev, &cell, sizeof(struct mfd_cell *)); ++ if (ret) ++ goto fail_device; ++ ++ res = kzalloc(cell->num_resources * sizeof(struct resource), ++ GFP_KERNEL); ++ if (!res) ++ goto fail_device; ++ ++ for (r = 0; r < cell->num_resources; r++) { ++ res[r].name = cell->resources[r].name; ++ ++ /* Find out base to use */ ++ if (cell->resources[r].flags & IORESOURCE_MEM) { ++ res[r].parent = mem; ++ res[r].start = mem->start + ++ SIGNED_SHIFT(cell->resources[r].start, ++ relative_addr_shift); ++ res[r].end = mem->start + ++ SIGNED_SHIFT(cell->resources[r].end, ++ relative_addr_shift); ++ } else if ((cell->resources[r].flags & IORESOURCE_IRQ) && ++ (cell->resources[r].flags & IORESOURCE_IRQ_MFD_SUBDEVICE)) { ++ res[r].start = irq_base + ++ cell->resources[r].start; ++ res[r].end = irq_base + ++ cell->resources[r].end; ++ } else { ++ res[r].start = cell->resources[r].start; ++ res[r].end = cell->resources[r].end; ++ } ++ ++ res[r].flags = cell->resources[r].flags; ++ } ++ ++ ret = platform_device_add_resources(pdev, ++ res, ++ cell->num_resources); ++ kfree(res); ++ ++ if (ret) ++ goto fail_device; ++ ++ ret = platform_device_add(pdev); ++ ++ if (ret) { ++ platform_device_del(pdev); ++fail_device: ++ platform_device_put(pdev); ++fail_alloc: ++ mfd_remove_devices(parent); ++ return ret; ++ } ++ } ++ return 0; ++} ++EXPORT_SYMBOL(mfd_add_devices); ++ ++static int mfd_remove_devices_fn(struct device *dev, void *unused) ++{ ++ platform_device_unregister(container_of(dev, struct platform_device, dev)); ++ return 0; ++} ++ ++void mfd_remove_devices(struct platform_device *parent) ++{ ++ device_for_each_child(&parent->dev, NULL, mfd_remove_devices_fn); ++} ++EXPORT_SYMBOL(mfd_remove_devices); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Ian Molton, Dmitry Baryshkov"); +diff --git a/include/linux/ioport.h b/include/linux/ioport.h +index 6187a85..0348c71 100644 +--- a/include/linux/ioport.h ++++ b/include/linux/ioport.h +@@ -56,6 +56,7 @@ struct resource_list { + #define IORESOURCE_IRQ_HIGHLEVEL (1<<2) + #define IORESOURCE_IRQ_LOWLEVEL (1<<3) + #define IORESOURCE_IRQ_SHAREABLE (1<<4) ++#define IORESOURCE_IRQ_MFD_SUBDEVICE (1<<5) + + /* ISA PnP DMA specific bits (IORESOURCE_BITS) */ + #define IORESOURCE_DMA_TYPE_MASK (3<<0) +diff --git a/include/linux/mfd-core.h b/include/linux/mfd-core.h +new file mode 100644 +index 0000000..0e9de78 +--- /dev/null ++++ b/include/linux/mfd-core.h +@@ -0,0 +1,51 @@ ++#ifndef MFD_CORE_H ++#define MFD_CORE_H ++/* ++ * drivers/mfd/mfd-core.h ++ * ++ * core MFD support ++ * Copyright (c) 2006 Ian Molton ++ * Copyright (c) 2007 Dmitry Baryshkov ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include <linux/platform_device.h> ++ ++struct mfd_cell { ++ const char *name; ++ ++ int (*enable)(struct platform_device *dev); ++ int (*disable)(struct platform_device *dev); ++ int (*suspend)(struct platform_device *dev); ++ int (*resume)(struct platform_device *dev); ++ ++ void *driver_data; /* data passed to drivers */ ++ ++ /* ++ * This resources can be specified relatievly to the parent device. ++ * For accessing device you should use resources from device ++ */ ++ int num_resources; ++ const struct resource *resources; ++}; ++ ++static inline __maybe_unused struct mfd_cell * ++mfd_get_cell(struct platform_device *pdev) ++{ ++ return *((struct mfd_cell **)(pdev->dev.platform_data)); ++} ++ ++extern int mfd_add_devices( ++ struct platform_device *parent, ++ const struct mfd_cell *cells, int n_devs, ++ struct resource *mem, ++ int relative_addr_shift, ++ int irq_base); ++ ++extern void mfd_remove_devices(struct platform_device *parent); ++ ++#endif +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0004-Add-support-for-tc6393xb-MFD-core.patch b/packages/linux/linux-rp-2.6.24/tosa/0004-Add-support-for-tc6393xb-MFD-core.patch new file mode 100644 index 0000000000..a78c0f37f3 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0004-Add-support-for-tc6393xb-MFD-core.patch @@ -0,0 +1,907 @@ +From 3f56cac281fb407b7d8e574d18ee7d72aa7e7c28 Mon Sep 17 00:00:00 2001 +From: Ian Molton <spyro@f2s.com> +Date: Sat, 29 Dec 2007 15:02:30 +0000 +Subject: [PATCH 04/64] Add support for tc6393xb MFD core + +--- + drivers/mfd/Kconfig | 6 + + drivers/mfd/Makefile | 2 + + drivers/mfd/tc6393xb.c | 740 ++++++++++++++++++++++++++++++++++++++++++ + include/linux/mfd/tc6393xb.h | 108 ++++++ + 4 files changed, 856 insertions(+), 0 deletions(-) + create mode 100644 drivers/mfd/tc6393xb.c + create mode 100644 include/linux/mfd/tc6393xb.h + +diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig +index 1205c89..9903d0a 100644 +--- a/drivers/mfd/Kconfig ++++ b/drivers/mfd/Kconfig +@@ -9,6 +9,12 @@ config MFD_CORE + tristate + default n + ++config MFD_TC6393XB ++ bool "Support Toshiba TC6393XB" ++ select MFD_CORE ++ help ++ Support for Toshiba Mobile IO Controller TC6393XB ++ + config MFD_SM501 + tristate "Support for Silicon Motion SM501" + ---help--- +diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile +index 6c20064..ffd342e 100644 +--- a/drivers/mfd/Makefile ++++ b/drivers/mfd/Makefile +@@ -6,6 +6,8 @@ obj-$(CONFIG_MFD_SM501) += sm501.o + + obj-$(CONFIG_MFD_CORE) += mfd-core.o + ++obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o ++ + obj-$(CONFIG_MCP) += mcp-core.o + obj-$(CONFIG_MCP_SA11X0) += mcp-sa11x0.o + obj-$(CONFIG_MCP_UCB1200) += ucb1x00-core.o +diff --git a/drivers/mfd/tc6393xb.c b/drivers/mfd/tc6393xb.c +new file mode 100644 +index 0000000..9439f39 +--- /dev/null ++++ b/drivers/mfd/tc6393xb.c +@@ -0,0 +1,740 @@ ++/* ++ * Toshiba TC6393XB SoC support ++ * ++ * Copyright(c) 2005-2006 Chris Humbert ++ * Copyright(c) 2005 Dirk Opfer ++ * Copyright(c) 2005 Ian Molton <spyro@f2s.com> ++ * Copyright(c) 2007 Dmitry Baryshkov ++ * ++ * Based on code written by Sharp/Lineo for 2.4 kernels ++ * Based on locomo.c ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/io.h> ++#include <linux/irq.h> ++#include <linux/platform_device.h> ++#include <linux/fb.h> ++#include <linux/mfd-core.h> ++#include <linux/mfd/tmio.h> ++#include <linux/mfd/tc6393xb.h> ++ ++struct tc6393xb_scr { ++ u8 x00[8]; ++ u8 revid; /* 0x08 Revision ID */ ++ u8 x01[0x47]; ++ u8 isr; /* 0x50 Interrupt Status */ ++ u8 x02; ++ u8 imr; /* 0x52 Interrupt Mask */ ++ u8 x03; ++ u8 irr; /* 0x54 Interrupt Routing */ ++ u8 x04[0x0b]; ++ u16 gper; /* 0x60 GP Enable */ ++ u8 x05[2]; ++ u16 gpi_sr[2]; /* 0x64 GPI Status */ ++ u16 gpi_imr[2]; /* 0x68 GPI INT Mask */ ++ u16 gpi_eder[2]; /* 0x6c GPI Edge Detect Enable */ ++ u16 gpi_lir[4]; /* 0x70 GPI Level Invert */ ++ u16 gpo_dsr[2]; /* 0x78 GPO Data Set */ ++ u16 gpo_doecr[2]; /* 0x7c GPO Data OE Control */ ++ u16 gp_iarcr[2]; /* 0x80 GP Internal Active Reg Control */ ++ u16 gp_iarlcr[2]; /* 0x84 GP Internal Active Reg Level Con*/ ++ u8 gpi_bcr[4]; /* 0x88 GPI Buffer Control */ ++ u16 gpa_iarcr; /* 0x8c GPa Internal Active Reg Control */ ++ u8 x06[2]; ++ u16 gpa_iarlcr; /* 0x90 GPa Internal Active Reg Level Co*/ ++ u8 x07[2]; ++ u16 gpa_bcr; /* 0x94 GPa Buffer Control */ ++ u8 x08[2]; ++ u16 ccr; /* 0x98 Clock Control */ ++ u16 pll2cr; /* 0x9a PLL2 Control */ ++ u16 pll1cr[2]; /* 0x9c PLL1 Control */ ++ u8 diarcr; /* 0xa0 Device Internal Active Reg Contr*/ ++ u8 dbocr; /* 0xa1 Device Buffer Off Control */ ++ u8 x09[0x3e]; ++ u8 fer; /* 0xe0 Function Enable */ ++ u8 x10[3]; ++ u16 mcr; /* 0xe4 Mode Control */ ++ u8 x11[0x14]; ++ u8 config; /* 0xfc Configuration Control */ ++ u8 x12[2]; ++ u8 debug; /* 0xff Debug */ ++} __attribute__ ((packed)); ++ ++/*--------------------------------------------------------------------------*/ ++ ++struct tc6393xb { ++ struct tc6393xb_scr __iomem *scr; ++ ++ spinlock_t lock; /* protects RMW cycles */ ++ ++ struct { ++ union tc6393xb_scr_fer fer; ++ union tc6393xb_scr_ccr ccr; ++ u8 gpi_bcr[4]; ++ } suspend_state; ++ ++ struct resource rscr; ++ struct resource *iomem; ++ int irq; ++}; ++ ++/*--------------------------------------------------------------------------*/ ++ ++static int tc6393xb_mmc_enable(struct platform_device *mmc) { ++ struct platform_device *dev = to_platform_device(mmc->dev.parent); ++ struct tc6393xb *tc6393xb = platform_get_drvdata(dev); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ union tc6393xb_scr_ccr ccr; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&tc6393xb->lock, flags); ++ ccr.raw = ioread16(&scr->ccr); ++ ccr.bits.ck32ken = 1; ++ iowrite16(ccr.raw, &scr->ccr); ++ spin_unlock_irqrestore(&tc6393xb->lock, flags); ++ ++ return 0; ++} ++ ++static int tc6393xb_mmc_disable(struct platform_device *mmc) { ++ struct platform_device *dev = to_platform_device(mmc->dev.parent); ++ struct tc6393xb *tc6393xb = platform_get_drvdata(dev); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ union tc6393xb_scr_ccr ccr; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&tc6393xb->lock, flags); ++ ccr.raw = ioread16(&scr->ccr); ++ ccr.bits.ck32ken = 0; ++ iowrite16(ccr.raw, &scr->ccr); ++ spin_unlock_irqrestore(&tc6393xb->lock, flags); ++ ++ return 0; ++} ++ ++/*--------------------------------------------------------------------------*/ ++ ++static int tc6393xb_nand_disable(struct platform_device *nand) ++{ ++ return 0; ++} ++ ++static int tc6393xb_nand_enable(struct platform_device *nand) ++{ ++ struct platform_device *dev = to_platform_device(nand->dev.parent); ++ struct tc6393xb *tc6393xb = platform_get_drvdata(dev); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&tc6393xb->lock, flags); ++ ++ /* SMD buffer on */ ++ dev_dbg(&dev->dev, "SMD buffer on\n"); ++ iowrite8(0xff, scr->gpi_bcr + 1); ++ ++ spin_unlock_irqrestore(&tc6393xb->lock, flags); ++ ++ return 0; ++} ++ ++int tc6393xb_lcd_set_power(struct platform_device *fb, bool on) ++{ ++ struct platform_device *dev = to_platform_device(fb->dev.parent); ++ struct tc6393xb *tc6393xb = platform_get_drvdata(dev); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ union tc6393xb_scr_fer fer; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&tc6393xb->lock, flags); ++ ++ fer.raw = ioread8(&scr->fer); ++ fer.bits.slcden = on ? 1 : 0; ++ iowrite8(fer.raw, &scr->fer); ++ ++ spin_unlock_irqrestore(&tc6393xb->lock, flags); ++ ++ return 0; ++} ++EXPORT_SYMBOL(tc6393xb_lcd_set_power); ++ ++int tc6393xb_lcd_mode(struct platform_device *fb_dev, ++ struct fb_videomode *mode) { ++ struct tc6393xb *tc6393xb = ++ platform_get_drvdata(to_platform_device(fb_dev->dev.parent)); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ ++ iowrite16(mode->pixclock, scr->pll1cr + 0); ++ iowrite16(mode->pixclock >> 16, scr->pll1cr + 1); ++ ++ return 0; ++} ++EXPORT_SYMBOL(tc6393xb_lcd_mode); ++ ++static int tc6393xb_ohci_disable(struct platform_device *ohci) ++{ ++ struct platform_device *dev = to_platform_device(ohci->dev.parent); ++ struct tc6393xb *tc6393xb = platform_get_drvdata(dev); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ union tc6393xb_scr_ccr ccr; ++ union tc6393xb_scr_fer fer; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&tc6393xb->lock, flags); ++ ++ fer.raw = ioread8(&scr->fer); ++ fer.bits.usben = 0; ++ iowrite8(fer.raw, &scr->fer); ++ ++ ccr.raw = ioread16(&scr->ccr); ++ ccr.bits.usbcken = 0; ++ iowrite16(ccr.raw, &scr->ccr); ++ ++ spin_unlock_irqrestore(&tc6393xb->lock, flags); ++ ++ return 0; ++} ++ ++static int tc6393xb_ohci_enable(struct platform_device *ohci) ++{ ++ struct platform_device *dev = to_platform_device(ohci->dev.parent); ++ struct tc6393xb *tc6393xb = platform_get_drvdata(dev); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ union tc6393xb_scr_ccr ccr; ++ union tc6393xb_scr_fer fer; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&tc6393xb->lock, flags); ++ ++ ccr.raw = ioread16(&scr->ccr); ++ ccr.bits.usbcken = 1; ++ iowrite16(ccr.raw, &scr->ccr); ++ ++ fer.raw = ioread8(&scr->fer); ++ fer.bits.usben = 1; ++ iowrite8(fer.raw, &scr->fer); ++ ++ spin_unlock_irqrestore(&tc6393xb->lock, flags); ++ ++ return 0; ++} ++ ++static int tc6393xb_fb_disable(struct platform_device *fb) ++{ ++ struct platform_device *dev = to_platform_device(fb->dev.parent); ++ struct tc6393xb *tc6393xb = platform_get_drvdata(dev); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ union tc6393xb_scr_ccr ccr; ++ union tc6393xb_scr_fer fer; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&tc6393xb->lock, flags); ++ ++ /* ++ * FIXME: is this correct or it should be moved to other _disable? ++ */ ++ fer.raw = ioread8(&scr->fer); ++ fer.bits.slcden = 0; ++/* fer.bits.lcdcven = 0; */ ++ iowrite8(fer.raw, &scr->fer); ++ ++ ccr.raw = ioread16(&scr->ccr); ++ ccr.bits.mclksel = disable; ++ iowrite16(ccr.raw, &scr->ccr); ++ ++ spin_unlock_irqrestore(&tc6393xb->lock, flags); ++ ++ return 0; ++} ++ ++static int tc6393xb_fb_enable(struct platform_device *fb) ++{ ++ struct platform_device *dev = to_platform_device(fb->dev.parent); ++ struct tc6393xb *tc6393xb = platform_get_drvdata(dev); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ union tc6393xb_scr_ccr ccr; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&tc6393xb->lock, flags); ++ ++ ccr.raw = ioread16(&scr->ccr); ++ ccr.bits.mclksel = m48MHz; ++ iowrite16(ccr.raw, &scr->ccr); ++ ++ spin_unlock_irqrestore(&tc6393xb->lock, flags); ++ ++ return 0; ++} ++ ++static int tc6393xb_fb_suspend(struct platform_device *fb) ++{ ++ struct platform_device *dev = to_platform_device(fb->dev.parent); ++ struct tc6393xb *tc6393xb = platform_get_drvdata(dev); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ union tc6393xb_scr_ccr ccr; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&tc6393xb->lock, flags); ++ ++ ccr.raw = ioread16(&scr->ccr); ++ ccr.bits.mclksel = disable; ++ iowrite16(ccr.raw, &scr->ccr); ++ ++ spin_unlock_irqrestore(&tc6393xb->lock, flags); ++ ++ return 0; ++} ++ ++static int tc6393xb_fb_resume(struct platform_device *fb) ++{ ++ struct platform_device *dev = to_platform_device(fb->dev.parent); ++ struct tc6393xb *tc6393xb = platform_get_drvdata(dev); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ union tc6393xb_scr_ccr ccr; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&tc6393xb->lock, flags); ++ ++ ccr.raw = ioread16(&scr->ccr); ++ ccr.bits.mclksel = m48MHz; ++ iowrite16(ccr.raw, &scr->ccr); ++ ++ spin_unlock_irqrestore(&tc6393xb->lock, flags); ++ ++ return 0; ++} ++ ++static struct resource tc6393xb_mmc_resources[] = { ++ { ++ .name = TMIO_MMC_CONTROL, ++ .start = 0x800, ++ .end = 0x9ff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = TMIO_MMC_CONFIG, ++ .start = 0x200, ++ .end = 0x2ff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = TMIO_MMC_IRQ, ++ .start = IRQ_TC6393_MMC, ++ .end = IRQ_TC6393_MMC, ++ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_MFD_SUBDEVICE, ++ }, ++}; ++ ++const static struct resource tc6393xb_nand_resources[] = { ++ { ++ .name = TMIO_NAND_CONFIG, ++ .start = 0x0100, ++ .end = 0x01ff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = TMIO_NAND_CONTROL, ++ .start = 0x1000, ++ .end = 0x1007, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = TMIO_NAND_IRQ, ++ .start = IRQ_TC6393_NAND, ++ .end = IRQ_TC6393_NAND, ++ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_MFD_SUBDEVICE, ++ }, ++}; ++ ++const static struct resource tc6393xb_ohci_resources[] = { ++ { ++ .name = TMIO_OHCI_CONFIG, ++ .start = 0x0300, ++ .end = 0x03ff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = TMIO_OHCI_CONTROL, ++ .start = 0x3000, ++ .end = 0x31ff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = TMIO_OHCI_SRAM, ++ .start = 0x010000, ++ .end = 0x017fff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = TMIO_OHCI_SRAM_ALIAS, ++ .start = 0x018000, ++ .end = 0x01ffff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = TMIO_OHCI_IRQ, ++ .start = IRQ_TC6393_OHCI, ++ .end = IRQ_TC6393_OHCI, ++ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_MFD_SUBDEVICE, ++ }, ++}; ++ ++const static struct resource tc6393xb_fb_resources[] = { ++ { ++ .name = TMIO_FB_CONFIG, ++ .start = 0x0500, ++ .end = 0x05ff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = TMIO_FB_CONTROL, ++ .start = 0x5000, ++ .end = 0x51ff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = TMIO_FB_VRAM, ++ .start = 0x100000, ++ .end = 0x1fffff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = TMIO_FB_IRQ, ++ .start = IRQ_TC6393_FB, ++ .end = IRQ_TC6393_FB, ++ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_MFD_SUBDEVICE, ++ }, ++}; ++ ++static struct mfd_cell tc6393xb_cells[] = { ++ { ++ .name = "tmio-nand", ++ .enable = tc6393xb_nand_enable, ++ .disable = tc6393xb_nand_disable, ++ .num_resources = ARRAY_SIZE(tc6393xb_nand_resources), ++ .resources = tc6393xb_nand_resources, ++ }, ++ { ++ .name = "tmio-ohci", ++ .enable = tc6393xb_ohci_enable, ++ .disable = tc6393xb_ohci_disable, ++ .num_resources = ARRAY_SIZE(tc6393xb_ohci_resources), ++ .resources = tc6393xb_ohci_resources, ++ }, ++ { ++ .name = "tmio-fb", ++ .enable = tc6393xb_fb_enable, ++ .disable = tc6393xb_fb_disable, ++ .suspend = tc6393xb_fb_suspend, ++ .resume = tc6393xb_fb_resume, ++ .num_resources = ARRAY_SIZE(tc6393xb_fb_resources), ++ .resources = tc6393xb_fb_resources, ++ }, ++ { ++ .name = "tmio-mmc", ++ .enable = tc6393xb_mmc_enable, ++ .disable = tc6393xb_mmc_disable, ++ .num_resources = ARRAY_SIZE(tc6393xb_mmc_resources), ++ .resources = tc6393xb_mmc_resources, ++ }, ++}; ++ ++/*--------------------------------------------------------------------------*/ ++ ++static void ++tc6393xb_irq(unsigned int irq, struct irq_desc *desc) ++{ ++ struct platform_device *dev = get_irq_chip_data(irq); ++ struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; ++ struct tc6393xb *tc6393xb = platform_get_drvdata(dev); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ unsigned int isr; ++ unsigned int i; ++ ++ desc->chip->ack(irq); ++ ++ while ((isr = ioread8(&scr->isr) & ~ioread8(&scr->imr))) ++ for (i = 0; i < TC6393XB_NR_IRQS; i++) { ++ if (isr & (1 << i)) ++ desc_handle_irq(tcpd->irq_base + i, ++ irq_desc + tcpd->irq_base + i); ++ } ++} ++ ++static void tc6393xb_irq_ack(unsigned int irq) ++{ ++} ++ ++static void tc6393xb_irq_mask(unsigned int irq) ++{ ++ struct platform_device *dev = get_irq_chip_data(irq); ++ struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; ++ struct tc6393xb *tc6393xb = platform_get_drvdata(dev); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&tc6393xb->lock, flags); ++ iowrite8(ioread8(&scr->imr) | (1 << (irq - tcpd->irq_base)), ++ &scr->imr); ++ spin_unlock_irqrestore(&tc6393xb->lock, flags); ++} ++ ++static void tc6393xb_irq_unmask(unsigned int irq) ++{ ++ struct platform_device *dev = get_irq_chip_data(irq); ++ struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; ++ struct tc6393xb *tc6393xb = platform_get_drvdata(dev); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&tc6393xb->lock, flags); ++ iowrite8(ioread8(&scr->imr) & ~(1 << (irq - tcpd->irq_base)), ++ &scr->imr); ++ spin_unlock_irqrestore(&tc6393xb->lock, flags); ++} ++ ++static struct irq_chip tc6393xb_chip = { ++ .name = "tc6393xb", ++ .ack = tc6393xb_irq_ack, ++ .mask = tc6393xb_irq_mask, ++ .unmask = tc6393xb_irq_unmask, ++}; ++ ++static void tc6393xb_attach_irq(struct platform_device *dev) ++{ ++ struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; ++ struct tc6393xb *tc6393xb = platform_get_drvdata(dev); ++ unsigned int irq; ++ ++ for ( ++ irq = tcpd->irq_base; ++ irq <= tcpd->irq_base + TC6393XB_NR_IRQS; ++ irq++) { ++ set_irq_chip(irq, &tc6393xb_chip); ++ set_irq_chip_data(irq, dev); ++ set_irq_handler(irq, handle_edge_irq); ++ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); ++ } ++ ++ set_irq_type(tc6393xb->irq, IRQT_FALLING); ++ set_irq_chip_data(tc6393xb->irq, dev); ++ set_irq_chained_handler(tc6393xb->irq, tc6393xb_irq); ++} ++ ++static void tc6393xb_detach_irq(struct platform_device *dev) ++{ ++ struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; ++ struct tc6393xb *tc6393xb = platform_get_drvdata(dev); ++ unsigned int irq; ++ ++ set_irq_chained_handler(tc6393xb->irq, NULL); ++ set_irq_chip_data(tc6393xb->irq, NULL); ++ ++ for ( ++ irq = tcpd->irq_base; ++ irq <= tcpd->irq_base + TC6393XB_NR_IRQS; ++ irq++) { ++ set_irq_flags(irq, 0); ++ set_irq_chip(irq, NULL); ++ set_irq_chip_data(irq, NULL); ++ } ++} ++ ++static int tc6393xb_hw_init(struct platform_device *dev, int resume) ++{ ++ struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; ++ struct tc6393xb *tc6393xb = platform_get_drvdata(dev); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ int ret; ++ int i; ++ ++ if (resume) ++ ret = tcpd->resume(dev); ++ else ++ ret = tcpd->enable(dev); ++ if (ret) ++ return ret; ++ ++ iowrite8(resume ? ++ tc6393xb->suspend_state.fer.raw : ++ 0, &scr->fer); ++ iowrite16(tcpd->scr_pll2cr, &scr->pll2cr); ++ iowrite16(resume? ++ tc6393xb->suspend_state.ccr.raw : ++ tcpd->scr_ccr.raw, &scr->ccr); ++ iowrite16(tcpd->scr_mcr.raw, &scr->mcr); ++ iowrite16(tcpd->scr_gper, &scr->gper); ++ iowrite8(0, &scr->irr); ++ iowrite8(0xbf, &scr->imr); ++ iowrite16(tcpd->scr_gpo_dsr, scr->gpo_dsr + 0); ++ iowrite16(tcpd->scr_gpo_dsr >> 16, scr->gpo_dsr + 1); ++ iowrite16(tcpd->scr_gpo_doecr, scr->gpo_doecr + 0); ++ iowrite16(tcpd->scr_gpo_doecr >> 16, scr->gpo_doecr + 1); ++ ++ if (resume) ++ for (i = 0; i < 4; i++) ++ iowrite8(tc6393xb->suspend_state.gpi_bcr[i], ++ scr->gpi_bcr + i); ++ ++ return 0; ++} ++ ++static int __devinit tc6393xb_probe(struct platform_device *dev) ++{ ++ struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; ++ struct tc6393xb *tc6393xb; ++ struct resource *iomem; ++ struct resource *rscr; ++ int retval; ++ ++ iomem = platform_get_resource(dev, IORESOURCE_MEM, 0); ++ if (!iomem) ++ return -EINVAL; ++ ++ tc6393xb = kzalloc(sizeof *tc6393xb, GFP_KERNEL); ++ if (!tc6393xb) { ++ retval = -ENOMEM; ++ goto err_kzalloc; ++ } ++ ++ spin_lock_init(&tc6393xb->lock); ++ ++ platform_set_drvdata(dev, tc6393xb); ++ tc6393xb->iomem = iomem; ++ tc6393xb->irq = platform_get_irq(dev, 0); ++ ++ rscr = &tc6393xb->rscr; ++ rscr->name = "tc6393xb-core"; ++ rscr->start = iomem->start; ++ rscr->end = iomem->start + 0xff; ++ rscr->flags = IORESOURCE_MEM; ++ ++ retval = request_resource(iomem, rscr); ++ if (retval) ++ goto err_request_scr; ++ ++ tc6393xb->scr = ioremap(rscr->start, rscr->end - rscr->start + 1); ++ if (!tc6393xb->scr) { ++ retval = -ENOMEM; ++ goto err_ioremap; ++ } ++ ++ retval = tc6393xb_hw_init(dev, 0); ++ if (retval) ++ goto err_hw_init; ++ ++ printk(KERN_INFO "Toshiba tc6393xb revision %d at 0x%08lx, irq %d\n", ++ ioread8(&tc6393xb->scr->revid), ++ (unsigned long) iomem->start, tc6393xb->irq); ++ ++ if (tc6393xb->irq) ++ tc6393xb_attach_irq(dev); ++ ++ tc6393xb_cells[0].driver_data = tcpd->nand_data; ++ tc6393xb_cells[1].driver_data = NULL; /* tcpd->ohci_data; */ ++ tc6393xb_cells[2].driver_data = tcpd->fb_data; ++ ++ retval = mfd_add_devices(dev, ++ tc6393xb_cells, ARRAY_SIZE(tc6393xb_cells), ++ iomem, 0, tcpd->irq_base); ++ ++ if (retval == 0) ++ return 0; ++ ++ if (tc6393xb->irq) ++ tc6393xb_detach_irq(dev); ++ ++err_hw_init: ++ iounmap(tc6393xb->scr); ++err_ioremap: ++ release_resource(rscr); ++err_request_scr: ++ kfree(tc6393xb); ++err_kzalloc: ++ release_resource(iomem); ++ return retval; ++} ++ ++static int __devexit tc6393xb_remove(struct platform_device *dev) { ++ struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; ++ struct tc6393xb *tc6393xb = platform_get_drvdata(dev); ++ int ret; ++ ++ if (tc6393xb->irq) ++ tc6393xb_detach_irq(dev); ++ ++ ret = tcpd->disable(dev); ++ ++ iounmap(tc6393xb->scr); ++ release_resource(&tc6393xb->rscr); ++ release_resource(tc6393xb->iomem); ++ ++ mfd_remove_devices(dev); ++ ++ platform_set_drvdata(dev, NULL); ++ ++ kfree(tc6393xb); ++ ++ return ret; ++} ++ ++#ifdef CONFIG_PM ++static int tc6393xb_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; ++ struct tc6393xb *tc6393xb = platform_get_drvdata(dev); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ int i; ++ ++ ++ tc6393xb->suspend_state.ccr.raw = ioread16(&scr->ccr); ++ tc6393xb->suspend_state.fer.raw = ioread8(&scr->fer); ++ for (i = 0; i < 4; i++) ++ tc6393xb->suspend_state.gpi_bcr[i] = ++ ioread8(scr->gpi_bcr + i); ++ ++ return tcpd->suspend(dev); ++} ++ ++static int tc6393xb_resume(struct platform_device *dev) ++{ ++ return tc6393xb_hw_init(dev, 1); ++} ++#else ++#define tc6393xb_suspend NULL ++#define tc6393xb_resume NULL ++#endif ++ ++static struct platform_driver tc6393xb_driver = { ++ .probe = tc6393xb_probe, ++ .remove = __devexit_p(tc6393xb_remove), ++ .suspend = tc6393xb_suspend, ++ .resume = tc6393xb_resume, ++ ++ .driver = { ++ .name = "tc6393xb", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init tc6393xb_init(void) ++{ ++ return platform_driver_register(&tc6393xb_driver); ++} ++ ++static void __exit tc6393xb_exit(void) ++{ ++ platform_driver_unregister(&tc6393xb_driver); ++} ++ ++module_init(tc6393xb_init); ++module_exit(tc6393xb_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Ian Molton, Dmitry Baryshkov and Dirk Opfer"); ++MODULE_DESCRIPTION("tc6393xb Toshiba Mobile IO Controller"); +diff --git a/include/linux/mfd/tc6393xb.h b/include/linux/mfd/tc6393xb.h +new file mode 100644 +index 0000000..e699294 +--- /dev/null ++++ b/include/linux/mfd/tc6393xb.h +@@ -0,0 +1,108 @@ ++/* ++ * Toshiba TC6393XB SoC support ++ * ++ * Copyright(c) 2005-2006 Chris Humbert ++ * Copyright(c) 2005 Dirk Opfer ++ * Copyright(c) 2005 Ian Molton <spyro@f2s.com> ++ * Copyright(c) 2007 Dmitry Baryshkov ++ * ++ * Based on code written by Sharp/Lineo for 2.4 kernels ++ * Based on locomo.c ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef TC6393XB_H ++#define TC6393XB_H ++ ++#include <linux/mfd-core.h> ++#include <linux/mfd/tmio.h> ++ ++union tc6393xb_scr_fer { ++ u8 raw; ++struct { ++ unsigned usben:1; /* D0 USB enable */ ++ unsigned lcdcven:1; /* D1 polysylicon TFT enable */ ++ unsigned slcden:1; /* D2 SLCD enable */ ++} __attribute__ ((packed)) bits; ++} __attribute__ ((packed)); ++ ++union tc6393xb_scr_ccr { ++ u16 raw; ++struct { ++ unsigned ck32ken:1; /* D0 SD host clock enable */ ++ unsigned usbcken:1; /* D1 USB host clock enable */ ++ unsigned x00:2; ++ unsigned sharp:1; /* D4 ??? set in Sharp's code */ ++ unsigned x01:3; ++ enum { disable = 0, ++ m12MHz = 1, ++ m24MHz = 2, ++ m48MHz = 3, ++ } mclksel:3; /* D10-D8 LCD controller clock */ ++ unsigned x02:1; ++ enum { h24MHz = 0, ++ h48MHz = 1, ++ } hclksel:2; /* D13-D12 host bus clock */ ++ unsigned x03:2; ++} __attribute__ ((packed)) bits; ++} __attribute__ ((packed)); ++ ++enum pincontrol { ++ opendrain = 0, ++ tristate = 1, ++ pushpull = 2, ++ /* reserved = 3, */ ++}; ++ ++union tc6393xb_scr_mcr { ++ u16 raw; ++struct { ++ enum pincontrol rdyst:2; /* D1-D0 HRDY control */ ++ unsigned x00:1; ++ unsigned aren:1; /* D3 HRDY pull up resistance cut off */ ++ enum pincontrol intst:2; /* D5-D4 #HINT control */ ++ unsigned x01:1; ++ unsigned aien:1; /* D7 #HINT pull up resitance cut off */ ++ unsigned x02:8; ++} __attribute__ ((packed)) bits; ++} __attribute__ ((packed)); ++ ++struct tc6393xb_platform_data { ++ u16 scr_pll2cr; /* PLL2 Control */ ++ union tc6393xb_scr_ccr scr_ccr; /* Clock Control */ ++ union tc6393xb_scr_mcr scr_mcr; /* Mode Control */ ++ u16 scr_gper; /* GP Enable */ ++ u32 scr_gpo_doecr; /* GPO Data OE Control */ ++ u32 scr_gpo_dsr; /* GPO Data Set */ ++ ++ int (*enable)(struct platform_device *dev); ++ int (*disable)(struct platform_device *dev); ++ int (*suspend)(struct platform_device *dev); ++ int (*resume)(struct platform_device *dev); ++ ++ int irq_base; /* a base for cascaded irq */ ++ ++ struct tmio_nand_data *nand_data; ++ struct tmio_fb_data *fb_data; ++}; ++ ++extern int tc6393xb_lcd_set_power(struct platform_device *fb_dev, bool on); ++extern int tc6393xb_lcd_mode(struct platform_device *fb_dev, ++ struct fb_videomode *mode); ++ ++ ++/* ++ * Relative to irq_base ++ */ ++#define IRQ_TC6393_NAND 0 ++#define IRQ_TC6393_MMC 1 ++#define IRQ_TC6393_OHCI 2 ++#define IRQ_TC6393_SERIAL 3 ++#define IRQ_TC6393_FB 4 ++ ++#define TC6393XB_NR_IRQS 8 ++ ++#endif +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0005-Add-support-for-tc6387xb-MFD-core.patch b/packages/linux/linux-rp-2.6.24/tosa/0005-Add-support-for-tc6387xb-MFD-core.patch new file mode 100644 index 0000000000..7183e3af6d --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0005-Add-support-for-tc6387xb-MFD-core.patch @@ -0,0 +1,249 @@ +From a6a6faf1dbb90c950fe55a1719720457bfb5830a Mon Sep 17 00:00:00 2001 +From: Ian Molton <spyro@f2s.com> +Date: Sun, 16 Dec 2007 02:19:49 +0000 +Subject: [PATCH 05/64] Add support for tc6387xb MFD core + +--- + drivers/mfd/Kconfig | 6 ++ + drivers/mfd/Makefile | 1 + + drivers/mfd/tc6387xb.c | 163 ++++++++++++++++++++++++++++++++++++++++++ + include/linux/mfd/tc6387xb.h | 28 +++++++ + 4 files changed, 198 insertions(+), 0 deletions(-) + create mode 100644 drivers/mfd/tc6387xb.c + create mode 100644 include/linux/mfd/tc6387xb.h + +diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig +index 9903d0a..1575323 100644 +--- a/drivers/mfd/Kconfig ++++ b/drivers/mfd/Kconfig +@@ -9,6 +9,12 @@ config MFD_CORE + tristate + default n + ++config MFD_TC6387XB ++ bool "Support Toshiba TC6387XB" ++ select MFD_CORE ++ help ++ Support for Toshiba Mobile IO Controller TC6387XB ++ + config MFD_TC6393XB + bool "Support Toshiba TC6393XB" + select MFD_CORE +diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile +index ffd342e..41b2190 100644 +--- a/drivers/mfd/Makefile ++++ b/drivers/mfd/Makefile +@@ -6,6 +6,7 @@ obj-$(CONFIG_MFD_SM501) += sm501.o + + obj-$(CONFIG_MFD_CORE) += mfd-core.o + ++obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o + obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o + + obj-$(CONFIG_MCP) += mcp-core.o +diff --git a/drivers/mfd/tc6387xb.c b/drivers/mfd/tc6387xb.c +new file mode 100644 +index 0000000..c81fca2 +--- /dev/null ++++ b/drivers/mfd/tc6387xb.c +@@ -0,0 +1,163 @@ ++/* ++ * Toshiba TC6387XB support ++ * Copyright (c) 2005 Ian Molton ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This file contains TC6387XB base support. ++ * ++ */ ++ ++#include <linux/module.h> ++#include <linux/init.h> ++#include <linux/delay.h> ++#include <linux/platform_device.h> ++ ++#include <asm/hardware.h> ++#include <asm/mach-types.h> ++ ++#include <linux/mfd-core.h> ++#include <linux/mfd/tc6387xb.h> ++ ++#ifdef CONFIG_PM ++static int tc6387xb_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ struct tc6387xb_platform_data *pdata = platform_get_drvdata(dev); ++ ++ if (pdata && pdata->suspend) ++ pdata->suspend(dev); ++ ++ return 0; ++} ++ ++static int tc6387xb_resume(struct platform_device *dev) ++{ ++ struct tc6387xb_platform_data *pdata = platform_get_drvdata(dev); ++ ++ if (pdata && pdata->resume) ++ pdata->resume(dev); ++ ++ return 0; ++} ++#else ++#define tc6387xb_suspend NULL ++#define tc6387xb_resume NULL ++#endif ++ ++/*--------------------------------------------------------------------------*/ ++ ++static int tc6387xb_mmc_enable(struct platform_device *mmc) { ++ struct platform_device *dev = to_platform_device(mmc->dev.parent); ++ struct tc6387xb_platform_data *tc6387xb = dev->dev.platform_data; ++ ++ if(tc6387xb->enable_mmc_clock) ++ tc6387xb->enable_mmc_clock(dev); ++ ++ return 0; ++} ++ ++static int tc6387xb_mmc_disable(struct platform_device *mmc) { ++ struct platform_device *dev = to_platform_device(mmc->dev.parent); ++ struct tc6387xb_platform_data *tc6387xb = dev->dev.platform_data; ++ ++ if(tc6387xb->disable_mmc_clock) ++ tc6387xb->disable_mmc_clock(dev); ++ ++ return 0; ++} ++ ++ ++/*--------------------------------------------------------------------------*/ ++ ++static struct resource tc6387xb_mmc_resources[] = { ++ { ++ .name = TMIO_MMC_CONTROL, ++ .start = 0x800, ++ .end = 0x9ff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = TMIO_MMC_CONFIG, ++ .start = 0x200, ++ .end = 0x2ff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = TMIO_MMC_IRQ, ++ .start = 0, ++ .end = 0, ++ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_MFD_SUBDEVICE, ++ }, ++}; ++ ++static struct mfd_cell tc6387xb_cells[] = { ++ { ++ .name = "tmio-mmc", ++ .enable = tc6387xb_mmc_enable, ++ .disable = tc6387xb_mmc_disable, ++ .num_resources = ARRAY_SIZE(tc6387xb_mmc_resources), ++ .resources = tc6387xb_mmc_resources, ++ }, ++}; ++ ++static int tc6387xb_probe(struct platform_device *dev) ++{ ++ struct tc6387xb_platform_data *data = platform_get_drvdata(dev); ++ struct resource *iomem; ++ int irq; ++ ++ iomem = platform_get_resource(dev, IORESOURCE_MEM, 0); ++ if (!iomem) ++ return -EINVAL; ++ ++ irq = platform_get_irq(dev, 0); ++ ++ if(data && data->enable) ++ data->enable(dev); ++ ++ printk(KERN_INFO "Toshiba tc6393xb initialised\n"); ++ ++ return mfd_add_devices(dev, tc6387xb_cells, ARRAY_SIZE(tc6387xb_cells), ++ iomem, 0, irq); ++} ++ ++static int tc6387xb_remove(struct platform_device *dev) ++{ ++ struct tc6387xb_platform_data *data = platform_get_drvdata(dev); ++ ++ if(data && data->disable) ++ data->disable(dev); ++ ++ return 0; ++} ++ ++ ++static struct platform_driver tc6387xb_platform_driver = { ++ .driver = { ++ .name = "tc6387xb", ++ }, ++ .probe = tc6387xb_probe, ++ .remove = tc6387xb_remove, ++ .suspend = tc6387xb_suspend, ++ .resume = tc6387xb_resume, ++}; ++ ++ ++static int __init tc6387xb_init(void) ++{ ++ return platform_driver_register (&tc6387xb_platform_driver); ++} ++ ++static void __exit tc6387xb_exit(void) ++{ ++ platform_driver_unregister(&tc6387xb_platform_driver); ++} ++ ++module_init(tc6387xb_init); ++module_exit(tc6387xb_exit); ++ ++MODULE_DESCRIPTION("Toshiba TC6387XB core driver"); ++MODULE_LICENSE("GPLv2"); ++MODULE_AUTHOR("Ian Molton"); +diff --git a/include/linux/mfd/tc6387xb.h b/include/linux/mfd/tc6387xb.h +new file mode 100644 +index 0000000..496770b +--- /dev/null ++++ b/include/linux/mfd/tc6387xb.h +@@ -0,0 +1,28 @@ ++/* ++ * linux/include/asm-arm/hardware/tc6387xb.h ++ * ++ * This file contains the definitions for the TC6393XB ++ * ++ * (C) Copyright 2005 Ian Molton <spyro@f2s.com> ++ * ++ * May be copied or modified under the terms of the GNU General Public ++ * License. See linux/COPYING for more information. ++ * ++ */ ++#ifndef MFD_T7L66XB_H ++#define MFD_T7L66XB_H ++ ++#include <linux/mfd-core.h> ++#include <linux/mfd/tmio.h> ++ ++struct tc6387xb_platform_data ++{ ++ int (*enable_mmc_clock)(struct platform_device *dev); ++ int (*disable_mmc_clock)(struct platform_device *dev); ++ int (*enable)(struct platform_device *dev); ++ int (*disable)(struct platform_device *dev); ++ int (*suspend)(struct platform_device *dev); ++ int (*resume)(struct platform_device *dev); ++}; ++ ++#endif +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0006-Add-support-for-t7l66xb-MFD-core.patch b/packages/linux/linux-rp-2.6.24/tosa/0006-Add-support-for-t7l66xb-MFD-core.patch new file mode 100644 index 0000000000..e7aff2455b --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0006-Add-support-for-t7l66xb-MFD-core.patch @@ -0,0 +1,653 @@ +From 2e31fea352ca97988452f1f2c94809de2977ce40 Mon Sep 17 00:00:00 2001 +From: Ian Molton <spyro@f2s.com> +Date: Sat, 29 Dec 2007 15:08:52 +0000 +Subject: [PATCH 06/64] Add support for t7l66xb MFD core + +--- + drivers/mfd/Kconfig | 6 + + drivers/mfd/Makefile | 1 + + drivers/mfd/t7l66xb.c | 550 +++++++++++++++++++++++++++++++++++++++++++ + include/linux/mfd/t7l66xb.h | 45 ++++ + 4 files changed, 602 insertions(+), 0 deletions(-) + create mode 100644 drivers/mfd/t7l66xb.c + create mode 100644 include/linux/mfd/t7l66xb.h + +diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig +index 1575323..f79a969 100644 +--- a/drivers/mfd/Kconfig ++++ b/drivers/mfd/Kconfig +@@ -9,6 +9,12 @@ config MFD_CORE + tristate + default n + ++config MFD_T7L66XB ++ bool "Support Toshiba T7L66XB" ++ select MFD_CORE ++ help ++ Support for Toshiba Mobile IO Controller T7L66XB ++ + config MFD_TC6387XB + bool "Support Toshiba TC6387XB" + select MFD_CORE +diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile +index 41b2190..b2037ae 100644 +--- a/drivers/mfd/Makefile ++++ b/drivers/mfd/Makefile +@@ -6,6 +6,7 @@ obj-$(CONFIG_MFD_SM501) += sm501.o + + obj-$(CONFIG_MFD_CORE) += mfd-core.o + ++obj-$(CONFIG_MFD_T7L66XB) += t7l66xb.o + obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o + obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o + +diff --git a/drivers/mfd/t7l66xb.c b/drivers/mfd/t7l66xb.c +new file mode 100644 +index 0000000..308776a +--- /dev/null ++++ b/drivers/mfd/t7l66xb.c +@@ -0,0 +1,550 @@ ++/* ++ * ++ * Toshiba T7L66XB core mfd support ++ * ++ * Copyright (c) 2005 Ian Molton ++ * Copyright (c) 2007 Ian Molton ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * T7L66 features: ++ * ++ * Supported in this driver: ++ * SD/MMC ++ * SM/NAND flash controller ++ * OHCI controller ++ * ++ * As yet not supported ++ * GPIO interface (on NAND pins) ++ * Serial interface ++ * TFT 'interface converter' ++ * PCMCIA interface logic ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/io.h> ++#include <linux/irq.h> ++#include <linux/platform_device.h> ++#include <linux/fb.h> ++#include <linux/mfd-core.h> ++#include <linux/mfd/tmio.h> ++#include <linux/mfd/t7l66xb.h> ++ ++union t7l66xb_dev_ctl { ++ u8 raw; ++struct { ++ unsigned usb_en:1; /* D0 USB enable */ ++ unsigned mmc_en:1; /* D1 MMC enable */ ++} __attribute__ ((packed)); ++} __attribute__ ((packed)); ++ ++ ++struct t7l66xb_scr { ++ u8 x00[8]; ++ u8 revid; /* 0x08 Revision ID */ ++ u8 x01[57]; ++ u8 imr; /* 0x42 Interrupt Mask */ ++ u8 x03[157]; ++ union t7l66xb_dev_ctl dev_ctl; /* 0xe0 Device control */ ++ u8 isr; /* 0xe1 Interrupt Status */ ++ u8 x04[14]; ++ u8 gpio_output_ctl; /* 0xf0 */ ++ u8 gpio_output_status; /* 0xf1 */ ++ u16 gpio_input_status; /* 0xf2 */ ++ u8 x05[4]; ++ u8 active_pullup_down_ctl; /* 0xf8 */ ++ u8 x06[7]; ++} __attribute__ ((packed)); ++ ++ ++/*--------------------------------------------------------------------------*/ ++ ++struct t7l66xb ++{ ++ struct t7l66xb_scr __iomem *scr; ++ spinlock_t lock; ++ ++ struct resource rscr; ++ struct resource *iomem; ++ int irq; ++}; ++ ++/*--------------------------------------------------------------------------*/ ++ ++static int t7l66xb_ohci_enable(struct platform_device *ohci) ++{ ++ struct platform_device *dev = to_platform_device(ohci->dev.parent); ++ struct t7l66xb *t7l66xb = platform_get_drvdata(dev); ++ struct t7l66xb_scr __iomem *scr = t7l66xb->scr; ++ unsigned long flags; ++ union t7l66xb_dev_ctl dev_ctl; ++ ++ spin_lock_irqsave(&t7l66xb->lock, flags); ++ ++ dev_ctl.raw = readb(&scr->dev_ctl); ++ dev_ctl.usb_en = 1; ++ writeb(dev_ctl.raw, &scr->dev_ctl); ++ ++ spin_unlock_irqrestore(&t7l66xb->lock, flags); ++ ++ return 0; ++} ++ ++static int t7l66xb_ohci_disable(struct platform_device *ohci) ++{ ++ struct platform_device *dev = to_platform_device(ohci->dev.parent); ++ struct t7l66xb *t7l66xb = platform_get_drvdata(dev); ++ struct t7l66xb_scr __iomem *scr = t7l66xb->scr; ++ unsigned long flags; ++ union t7l66xb_dev_ctl dev_ctl; ++ ++ spin_lock_irqsave(&t7l66xb->lock, flags); ++ ++ dev_ctl.raw = readb(&scr->dev_ctl); ++ dev_ctl.usb_en = 0; ++ writeb(dev_ctl.raw, &scr->dev_ctl); ++ ++ spin_unlock_irqrestore(&t7l66xb->lock, flags); ++ ++ return 0; ++} ++ ++/*--------------------------------------------------------------------------*/ ++ ++static int t7l66xb_mmc_enable(struct platform_device *ohci) ++{ ++ struct platform_device *dev = to_platform_device(ohci->dev.parent); ++ struct t7l66xb_platform_data *pdata = dev->dev.platform_data; ++ struct t7l66xb *t7l66xb = platform_get_drvdata(dev); ++ struct t7l66xb_scr __iomem *scr = t7l66xb->scr; ++ unsigned long flags; ++ union t7l66xb_dev_ctl dev_ctl; ++ ++ spin_lock_irqsave(&t7l66xb->lock, flags); ++ ++ if(pdata->enable_clk32k) ++ pdata->enable_clk32k(dev); ++ dev_ctl.raw = readb(&scr->dev_ctl); ++ dev_ctl.mmc_en = 1; ++ writeb(dev_ctl.raw, &scr->dev_ctl); ++ ++ spin_unlock_irqrestore(&t7l66xb->lock, flags); ++ ++ return 0; ++} ++ ++static int t7l66xb_mmc_disable(struct platform_device *ohci) ++{ ++ struct platform_device *dev = to_platform_device(ohci->dev.parent); ++ struct t7l66xb_platform_data *pdata = dev->dev.platform_data; ++ struct t7l66xb *t7l66xb = platform_get_drvdata(dev); ++ struct t7l66xb_scr __iomem *scr = t7l66xb->scr; ++ unsigned long flags; ++ union t7l66xb_dev_ctl dev_ctl; ++ ++ spin_lock_irqsave(&t7l66xb->lock, flags); ++ ++ dev_ctl.raw = readb(&scr->dev_ctl); ++ dev_ctl.mmc_en = 0; ++ writeb(dev_ctl.raw, &scr->dev_ctl); ++ if(pdata->disable_clk32k) ++ pdata->disable_clk32k(dev); ++ ++ spin_unlock_irqrestore(&t7l66xb->lock, flags); ++ ++ return 0; ++} ++ ++/*--------------------------------------------------------------------------*/ ++ ++static int t7l66xb_nand_disable(struct platform_device *nand) ++{ ++ struct platform_device *dev = to_platform_device(nand->dev.parent); ++ struct t7l66xb *t7l66xb = platform_get_drvdata(dev); ++ struct t7l66xb_scr __iomem *scr = t7l66xb->scr; ++ unsigned long flags; ++ union t7l66xb_dev_ctl dev_ctl; ++ ++ spin_lock_irqsave(&t7l66xb->lock, flags); ++ ++ dev_ctl.raw = readb(&scr->dev_ctl); ++// dev_ctl.nand_en = 0; ++ writeb(dev_ctl.raw, &scr->dev_ctl); ++ ++ spin_unlock_irqrestore(&t7l66xb->lock, flags); ++ ++ return 0; ++} ++ ++static int t7l66xb_nand_enable(struct platform_device *nand) ++{ ++ struct platform_device *dev = to_platform_device(nand->dev.parent); ++ struct t7l66xb *t7l66xb = platform_get_drvdata(dev); ++ struct t7l66xb_scr __iomem *scr = t7l66xb->scr; ++ unsigned long flags; ++ union t7l66xb_dev_ctl dev_ctl; ++ ++ spin_lock_irqsave(&t7l66xb->lock, flags); ++ ++ dev_ctl.raw = readb(&scr->dev_ctl); ++ // dev_ctl.nand_en = 1; ++ writeb(dev_ctl.raw, &scr->dev_ctl); ++ ++ spin_unlock_irqrestore(&t7l66xb->lock, flags); ++ ++ return 0; ++} ++ ++/*--------------------------------------------------------------------------*/ ++ ++const static struct resource t7l66xb_mmc_resources[] = { ++ { ++ .name = TMIO_MMC_CONTROL, ++ .start = 0x800, ++ .end = 0x9ff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = TMIO_MMC_CONFIG, ++ .start = 0x200, ++ .end = 0x2ff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = TMIO_MMC_IRQ, ++ .start = IRQ_T7L66XB_MMC, ++ .end = IRQ_T7L66XB_MMC, ++ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_MFD_SUBDEVICE, ++ }, ++}; ++ ++const static struct resource t7l66xb_ohci_resources[] = { ++ { ++ .name = TMIO_OHCI_CONFIG, ++ .start = 0x0300, ++ .end = 0x03ff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = TMIO_OHCI_CONTROL, ++ .start = 0xa00, ++ .end = 0xbff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = TMIO_OHCI_SRAM, ++ .start = 0x01000, ++ .end = 0x02fff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = TMIO_OHCI_IRQ, ++ .start = IRQ_T7L66XB_OHCI, ++ .end = IRQ_T7L66XB_OHCI, ++ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_MFD_SUBDEVICE, ++ }, ++}; ++ ++const static struct resource t7l66xb_nand_resources[] = { ++ { ++ .name = TMIO_NAND_CONFIG, ++ .start = 0x0100, ++ .end = 0x01ff, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = TMIO_NAND_CONTROL, ++ .start = 0xc00, ++ .end = 0xc07, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = TMIO_NAND_IRQ, ++ .start = IRQ_T7L66XB_NAND, ++ .end = IRQ_T7L66XB_NAND, ++ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_MFD_SUBDEVICE, ++ }, ++}; ++ ++static struct mfd_cell t7l66xb_cells[] = { ++ { ++ .name = "tmio-mmc", ++ .enable = t7l66xb_mmc_enable, ++ .disable = t7l66xb_mmc_disable, ++ .num_resources = ARRAY_SIZE(t7l66xb_mmc_resources), ++ .resources = t7l66xb_mmc_resources, ++ }, ++ { ++ .name = "tmio-ohci", ++ .enable = t7l66xb_ohci_enable, ++ .disable = t7l66xb_ohci_disable, ++ .num_resources = ARRAY_SIZE(t7l66xb_ohci_resources), ++ .resources = t7l66xb_ohci_resources, ++ }, ++ { ++ .name = "tmio-nand", ++ .enable = t7l66xb_nand_enable, ++ .disable = t7l66xb_nand_disable, ++ .num_resources = ARRAY_SIZE(t7l66xb_nand_resources), ++ .resources = t7l66xb_nand_resources, ++ }, ++}; ++ ++/*--------------------------------------------------------------------------*/ ++ ++/* Handle the T7L66XB interrupt mux */ ++static void t7l66xb_irq(unsigned int irq, struct irq_desc *desc) ++{ ++ struct platform_device *dev = get_irq_chip_data(irq); ++ struct t7l66xb_platform_data *tcpd = dev->dev.platform_data; ++ struct t7l66xb *t7l66xb = platform_get_drvdata(dev); ++ struct t7l66xb_scr __iomem *scr = t7l66xb->scr; ++ unsigned int isr; ++ unsigned int i; ++ ++ desc->chip->ack(irq); ++ while ((isr = readb(&scr->isr) & ~readb(&scr->imr))) ++ for (i = 0; i < T7L66XB_NR_IRQS; i++) ++ if (isr & (1 << i)) ++ desc_handle_irq(tcpd->irq_base + i, ++ irq_desc + tcpd->irq_base + i); ++} ++ ++static void t7l66xb_irq_mask(unsigned int irq) ++{ ++ struct platform_device *dev = get_irq_chip_data(irq); ++ struct t7l66xb_platform_data *tcpd = dev->dev.platform_data; ++ struct t7l66xb *t7l66xb = platform_get_drvdata(dev); ++ struct t7l66xb_scr __iomem *scr = t7l66xb->scr; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&t7l66xb->lock, flags); ++ iowrite8(ioread8(&scr->imr) | (1 << (irq - tcpd->irq_base)), ++ &scr->imr); ++ spin_unlock_irqrestore(&t7l66xb->lock, flags); ++} ++ ++static void t7l66xb_irq_unmask(unsigned int irq) ++{ ++ struct platform_device *dev = get_irq_chip_data(irq); ++ struct t7l66xb_platform_data *tcpd = dev->dev.platform_data; ++ struct t7l66xb *t7l66xb = platform_get_drvdata(dev); ++ struct t7l66xb_scr __iomem *scr = t7l66xb->scr; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&t7l66xb->lock, flags); ++ iowrite8(ioread8(&scr->imr) & ~(1 << (irq - tcpd->irq_base)), ++ &scr->imr); ++ spin_unlock_irqrestore(&t7l66xb->lock, flags); ++} ++ ++static struct irq_chip t7l66xb_chip = { ++ .name = "t7l66xb", ++ .ack = t7l66xb_irq_mask, ++ .mask = t7l66xb_irq_mask, ++ .unmask = t7l66xb_irq_unmask, ++}; ++ ++/*--------------------------------------------------------------------------*/ ++ ++/* Install the IRQ handler */ ++static void t7l66xb_attach_irq(struct platform_device *dev) ++{ ++ struct t7l66xb_platform_data *tcpd = dev->dev.platform_data; ++ struct t7l66xb *t7l66xb = platform_get_drvdata(dev); ++ unsigned int irq; ++ ++ for ( ++ irq = tcpd->irq_base; ++ irq <= tcpd->irq_base + T7L66XB_NR_IRQS; ++ irq++) { ++ set_irq_chip (irq, &t7l66xb_chip); ++ set_irq_chip_data (irq, dev); ++ set_irq_handler(irq, handle_level_irq); ++ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); ++ } ++ ++ set_irq_type (t7l66xb->irq, IRQT_FALLING); ++ set_irq_chip_data (t7l66xb->irq, dev); ++ set_irq_chained_handler (t7l66xb->irq, t7l66xb_irq); ++} ++ ++static void t7l66xb_detach_irq(struct platform_device *dev) ++{ ++ struct t7l66xb_platform_data *tcpd = dev->dev.platform_data; ++ struct t7l66xb *t7l66xb = platform_get_drvdata(dev); ++ unsigned int irq; ++ ++ set_irq_chained_handler(t7l66xb->irq, NULL); ++ set_irq_chip_data(t7l66xb->irq, NULL); ++ ++ for ( ++ irq = tcpd->irq_base; ++ irq <= tcpd->irq_base + T7L66XB_NR_IRQS; ++ irq++) { ++ set_irq_flags(irq, 0); ++ set_irq_chip(irq, NULL); ++ set_irq_chip_data(irq, NULL); ++ } ++} ++ ++/*--------------------------------------------------------------------------*/ ++ ++#ifdef CONFIG_PM ++static int t7l66xb_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ struct t7l66xb_platform_data *pdata = dev->dev.platform_data; ++ ++ ++ if (pdata && pdata->suspend) ++ pdata->suspend(dev); ++ ++ return 0; ++} ++ ++static int t7l66xb_resume(struct platform_device *dev) ++{ ++ struct t7l66xb_platform_data *pdata = dev->dev.platform_data; ++ ++ if (pdata && pdata->resume) ++ pdata->resume(dev); ++ ++ return 0; ++} ++#else ++#define t7l66xb_suspend NULL ++#define t7l66xb_resume NULL ++#endif ++ ++/*--------------------------------------------------------------------------*/ ++ ++static int t7l66xb_probe(struct platform_device *dev) ++{ ++ struct t7l66xb_platform_data *pdata = dev->dev.platform_data; ++ struct t7l66xb *t7l66xb; ++ struct resource *iomem; ++ struct resource *rscr; ++ int retval = -ENOMEM; ++ ++ iomem = platform_get_resource(dev, IORESOURCE_MEM, 0); ++ if (!iomem) ++ return -EINVAL; ++ ++ t7l66xb = kzalloc (sizeof *t7l66xb, GFP_KERNEL); ++ if (!t7l66xb) ++ goto err_kzalloc; ++ ++ spin_lock_init(&t7l66xb->lock); ++ ++ platform_set_drvdata(dev, t7l66xb); ++ t7l66xb->iomem = iomem; ++ t7l66xb->irq = platform_get_irq(dev, 0); ++ ++ rscr = &t7l66xb->rscr; ++ rscr->name = "t7l66xb-core"; ++ rscr->start = iomem->start; ++ rscr->end = iomem->start + 0xff; ++ rscr->flags = IORESOURCE_MEM; ++ ++ if((retval = request_resource(iomem, rscr))) ++ goto err_request_scr; ++ ++ t7l66xb->scr = ioremap(rscr->start, rscr->end - rscr->start + 1); ++ if (!t7l66xb->scr) { ++ retval = -ENOMEM; ++ goto err_ioremap; ++ } ++ ++ if (pdata && pdata->enable) ++ pdata->enable(dev); ++ ++ writeb(0xbf, &t7l66xb->scr->imr); /* Mask all interrupts */ ++ ++ printk(KERN_INFO "%s rev %d @ 0x%08lx, irq %d\n", ++ dev->name, readb(&t7l66xb->scr->revid), ++ (unsigned long)t7l66xb->scr, t7l66xb->irq); ++ ++ if(t7l66xb->irq) ++ t7l66xb_attach_irq(dev); ++ ++ t7l66xb_cells[2].driver_data = pdata->nand_data; ++ ++ if(!(retval = mfd_add_devices(dev, t7l66xb_cells, ++ ARRAY_SIZE(t7l66xb_cells), ++ iomem, 0, pdata->irq_base))) ++ return 0; ++ ++ if(t7l66xb->irq) ++ t7l66xb_detach_irq(dev); ++ ++ iounmap(t7l66xb->scr); ++err_ioremap: ++ release_resource(rscr); ++err_request_scr: ++ kfree(t7l66xb); ++err_kzalloc: ++ release_resource(iomem); ++ return retval; ++} ++ ++static int t7l66xb_remove(struct platform_device *dev) ++{ ++ struct t7l66xb_platform_data *pdata = dev->dev.platform_data; ++ struct t7l66xb *t7l66xb = platform_get_drvdata(dev); ++ int ret; ++ ++ if (t7l66xb->irq) ++ t7l66xb_detach_irq(dev); ++ ++ ret = pdata->disable(dev); ++ ++ iounmap(t7l66xb->scr); ++ release_resource(&t7l66xb->rscr); ++ release_resource(t7l66xb->iomem); ++ ++ mfd_remove_devices(dev); ++ ++ platform_set_drvdata(dev, NULL); ++ ++ kfree(t7l66xb); ++ ++ return ret; ++ ++} ++ ++static struct platform_driver t7l66xb_platform_driver = { ++ .driver = { ++ .name = "t7l66xb", ++ .owner = THIS_MODULE, ++ }, ++ .suspend = t7l66xb_suspend, ++ .resume = t7l66xb_resume, ++ .probe = t7l66xb_probe, ++ .remove = t7l66xb_remove, ++}; ++ ++/*--------------------------------------------------------------------------*/ ++ ++static int __init t7l66xb_init(void) ++{ ++ int retval = 0; ++ ++ retval = platform_driver_register (&t7l66xb_platform_driver); ++ return retval; ++} ++ ++static void __exit t7l66xb_exit(void) ++{ ++ platform_driver_unregister(&t7l66xb_platform_driver); ++} ++ ++module_init(t7l66xb_init); ++module_exit(t7l66xb_exit); ++ ++MODULE_DESCRIPTION("Toshiba T7L66XB core driver"); ++MODULE_LICENSE("GPLv2"); ++MODULE_AUTHOR("Ian Molton"); ++ +diff --git a/include/linux/mfd/t7l66xb.h b/include/linux/mfd/t7l66xb.h +new file mode 100644 +index 0000000..06b8de5 +--- /dev/null ++++ b/include/linux/mfd/t7l66xb.h +@@ -0,0 +1,45 @@ ++/* ++ * linux/include/asm-arm/hardware/t7l66xb.h ++ * ++ * This file contains the definitions for the T7L66XB ++ * ++ * (C) Copyright 2005 Ian Molton <spyro@f2s.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++#ifndef _ASM_ARCH_T7L66XB_SOC ++#define _ASM_ARCH_T7L66XB_SOC ++ ++#include <linux/mfd-core.h> ++#include <linux/mfd/tmio.h> ++ ++ ++struct t7l66xb_platform_data ++{ ++ int (*enable_clk32k)(struct platform_device *dev); ++ int (*disable_clk32k)(struct platform_device *dev); ++ ++ int (*enable)(struct platform_device *dev); ++ int (*disable)(struct platform_device *dev); ++ int (*suspend)(struct platform_device *dev); ++ int (*resume)(struct platform_device *dev); ++ ++ int irq_base; /* a base for cascaded irq */ ++ ++ struct tmio_nand_data *nand_data; ++}; ++ ++ ++#define T7L66XB_NAND_CNF_BASE (0x000100) ++#define T7L66XB_NAND_CTL_BASE (0x001000) ++ ++#define IRQ_T7L66XB_NAND (3) ++#define IRQ_T7L66XB_MMC (1) ++#define IRQ_T7L66XB_OHCI (2) ++ ++#define T7L66XB_NR_IRQS 8 ++ ++#endif +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0007-Common-headers-for-TMIO-MFD-subdevices.patch b/packages/linux/linux-rp-2.6.24/tosa/0007-Common-headers-for-TMIO-MFD-subdevices.patch new file mode 100644 index 0000000000..2f5f11400c --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0007-Common-headers-for-TMIO-MFD-subdevices.patch @@ -0,0 +1,81 @@ +From d6e8b347dbcce9e0e8d2204b774c1c33cfcb483e Mon Sep 17 00:00:00 2001 +From: Ian Molton <spyro@f2s.com> +Date: Sat, 29 Dec 2007 15:27:43 +0000 +Subject: [PATCH 07/64] Common headers for TMIO MFD subdevices + +--- + include/linux/mfd/tmio.h | 62 ++++++++++++++++++++++++++++++++++++++++++++++ + 1 files changed, 62 insertions(+), 0 deletions(-) + create mode 100644 include/linux/mfd/tmio.h + +diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h +new file mode 100644 +index 0000000..b42a4c3 +--- /dev/null ++++ b/include/linux/mfd/tmio.h +@@ -0,0 +1,62 @@ ++#ifndef MFD_TMIO_H ++#define MFD_TMIO_H ++ ++#include <linux/io.h> ++#include <linux/platform_device.h> ++ ++struct fb_videomode; ++ ++/* ++ * data for the NAND controller ++ */ ++struct tmio_nand_data { ++ struct nand_bbt_descr *badblock_pattern; ++ struct mtd_partition *partition; ++ unsigned int num_partitions; ++}; ++ ++struct tmio_fb_data { ++ int (*lcd_set_power)(struct platform_device *fb_dev, ++ bool on); ++ int (*lcd_mode)(struct platform_device *fb_dev, ++ struct fb_videomode *mode); ++ int num_modes; ++ struct fb_videomode *modes; ++}; ++ ++static u32 __maybe_unused tmio_ioread32(const void __iomem *addr) ++{ ++ return ((u32) ioread16(addr)) | (((u32) ioread16(addr + 2)) << 16); ++} ++ ++static u32 __maybe_unused tmio_iowrite32(u32 val, const void __iomem *addr) ++{ ++ iowrite16(val, addr); ++ iowrite16(val >> 16, addr + 2); ++ return val; ++} ++ ++#define FBIO_TMIO_ACC_WRITE 0x7C639300 ++#define FBIO_TMIO_ACC_SYNC 0x7C639301 ++ ++#define TMIO_MMC_CONFIG "tmio-mmc-config" ++#define TMIO_MMC_CONTROL "tmio-mmc-control" ++#define TMIO_MMC_IRQ "tmio-mmc" ++ ++#define TMIO_NAND_CONFIG "tmio-nand-config" ++#define TMIO_NAND_CONTROL "tmio-nand-control" ++#define TMIO_NAND_IRQ "tmio-nand" ++ ++#define TMIO_FB_CONFIG "tmio-fb-config" ++#define TMIO_FB_CONTROL "tmio-fb-control" ++#define TMIO_FB_VRAM "tmio-fb-vram" ++#define TMIO_FB_IRQ "tmio-fb" ++ ++#define TMIO_OHCI_CONFIG "tmio-ohci-config" ++#define TMIO_OHCI_CONTROL "tmio-ohci-control" ++#define TMIO_OHCI_SRAM "tmio-ohci-sram" ++#define TMIO_OHCI_SRAM_ALIAS "tmio-ohci-sram-alias" ++#define TMIO_OHCI_IRQ "tmio-ohci" ++ ++#endif ++ +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0008-Nand-driver-for-TMIO-devices.patch b/packages/linux/linux-rp-2.6.24/tosa/0008-Nand-driver-for-TMIO-devices.patch new file mode 100644 index 0000000000..48b8000ab7 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0008-Nand-driver-for-TMIO-devices.patch @@ -0,0 +1,608 @@ +From 917b3997a39396f5f51418930de7b933ad053bad Mon Sep 17 00:00:00 2001 +From: Ian Molton <spyro@f2s.com> +Date: Sat, 29 Dec 2007 15:14:23 +0000 +Subject: [PATCH 08/64] Nand driver for TMIO devices + +--- + drivers/mtd/nand/Kconfig | 7 + + drivers/mtd/nand/Makefile | 1 + + drivers/mtd/nand/tmio_nand.c | 557 ++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 565 insertions(+), 0 deletions(-) + create mode 100644 drivers/mtd/nand/tmio_nand.c + +diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig +index 246d451..43e489a 100644 +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -284,6 +284,13 @@ config MTD_NAND_CM_X270 + depends on MTD_NAND && MACH_ARMCORE + + ++config MTD_NAND_TMIO ++ tristate "NAND Flash device on Toshiba Mobile IO Controller" ++ depends on MTD_NAND && MFD_CORE ++ help ++ Support for NAND flash connected to a Toshiba Mobile IO ++ Controller in some PDAs, including the Sharp SL6000x. ++ + config MTD_NAND_NANDSIM + tristate "Support for NAND Flash Simulator" + depends on MTD_PARTITIONS +diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile +index 3ad6c01..d839ebd 100644 +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -27,6 +27,7 @@ obj-$(CONFIG_MTD_NAND_NDFC) += ndfc.o + obj-$(CONFIG_MTD_NAND_AT91) += at91_nand.o + obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o + obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) += excite_nandflash.o ++obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o + obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o + obj-$(CONFIG_MTD_ALAUDA) += alauda.o + +diff --git a/drivers/mtd/nand/tmio_nand.c b/drivers/mtd/nand/tmio_nand.c +new file mode 100644 +index 0000000..450b4ec +--- /dev/null ++++ b/drivers/mtd/nand/tmio_nand.c +@@ -0,0 +1,557 @@ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/platform_device.h> ++#include <linux/mfd-core.h> ++#include <linux/mfd/tmio.h> ++#include <linux/delay.h> ++#include <linux/io.h> ++#include <linux/irq.h> ++#include <linux/interrupt.h> ++#include <linux/ioport.h> ++#include <linux/mtd/mtd.h> ++#include <linux/mtd/nand.h> ++#include <linux/mtd/nand_ecc.h> ++#include <linux/mtd/partitions.h> ++ ++/*--------------------------------------------------------------------------*/ ++ ++/* tmio_nfcr.mode Register Command List */ ++#define FCR_MODE_DATA 0x94 /* Data Data_Mode */ ++#define FCR_MODE_COMMAND 0x95 /* Data Command_Mode */ ++#define FCR_MODE_ADDRESS 0x96 /* Data Address_Mode */ ++ ++#define FCR_MODE_HWECC_CALC 0xB4 /* HW-ECC Data */ ++#define FCR_MODE_HWECC_RESULT 0xD4 /* HW-ECC Calculation Result Read_Mode */ ++#define FCR_MODE_HWECC_RESET 0xF4 /* HW-ECC Reset */ ++ ++#define FCR_MODE_POWER_ON 0x0C /* Power Supply ON to SSFDC card */ ++#define FCR_MODE_POWER_OFF 0x08 /* Power Supply OFF to SSFDC card */ ++ ++#define FCR_MODE_LED_OFF 0x00 /* LED OFF */ ++#define FCR_MODE_LED_ON 0x04 /* LED ON */ ++ ++#define FCR_MODE_EJECT_ON 0x68 /* Ejection Demand from Penguin is Advanced */ ++#define FCR_MODE_EJECT_OFF 0x08 /* Ejection Demand from Penguin is Not Advanced */ ++ ++#define FCR_MODE_LOCK 0x6C /* Operates By Lock_Mode. Ejection Switch is Invalid */ ++#define FCR_MODE_UNLOCK 0x0C /* Operates By UnLock_Mode.Ejection Switch is Effective */ ++ ++#define FCR_MODE_CONTROLLER_ID 0x40 /* Controller ID Read */ ++#define FCR_MODE_STANDBY 0x00 /* SSFDC card Changes Standby State */ ++ ++#define FCR_MODE_WE 0x80 ++#define FCR_MODE_ECC1 0x40 ++#define FCR_MODE_ECC0 0x20 ++#define FCR_MODE_CE 0x10 ++#define FCR_MODE_PCNT1 0x08 ++#define FCR_MODE_PCNT0 0x04 ++#define FCR_MODE_ALE 0x02 ++#define FCR_MODE_CLE 0x01 ++ ++#define FCR_STATUS_BUSY 0x80 ++ ++/* ++ *NAND Flash Host Controller Configuration Register ++ */ ++struct tmio_nfhccr { ++ u8 x00[4]; ++ u16 command; /* 0x04 Command */ ++ u8 x01[0x0a]; ++ u16 base[2]; /* 0x10 NAND Flash Control Reg Base Addr*/ ++ u8 x02[0x29]; ++ u8 intp; /* 0x3d Interrupt Pin */ ++ u8 x03[0x0a]; ++ u8 inte; /* 0x48 Interrupt Enable */ ++ u8 x04; ++ u8 ec; /* 0x4a Event Control */ ++ u8 x05; ++ u8 icc; /* 0x4c Internal Clock Control */ ++ u8 x06[0x0e]; ++ u8 eccc; /* 0x5b ECC Control */ ++ u8 x07[4]; ++ u8 nftc; /* 0x60 NAND Flash Transaction Control */ ++ u8 nfm; /* 0x61 NAND Flash Monitor */ ++ u8 nfpsc; /* 0x62 NAND Flash Power Supply Control */ ++ u8 nfdc; /* 0x63 NAND Flash Detect Control */ ++ u8 x08[0x9c]; ++} __attribute__ ((packed)); ++ ++/* ++ *NAND Flash Control Register ++ */ ++struct tmio_nfcr { ++union { ++ u8 u8; /* 0x00 Data Register */ ++ u16 u16; ++ u32 u32; ++} __attribute__ ((packed)); ++ u8 mode; /* 0x04 Mode Register */ ++ u8 status; /* 0x05 Status Register */ ++ u8 isr; /* 0x06 Interrupt Status Register */ ++ u8 imr; /* 0x07 Interrupt Mask Register */ ++} __attribute__ ((packed)); ++ ++struct tmio_nand { ++ struct mtd_info mtd; ++ struct nand_chip chip; ++ ++ struct platform_device *dev; ++ ++ struct tmio_nfhccr __iomem *ccr; ++ struct tmio_nfcr __iomem *fcr; ++ ++ unsigned int irq; ++ ++ /* for tmio_nand_read_byte */ ++ u8 read; ++ unsigned read_good:1; ++}; ++ ++#define mtd_to_tmio(m) container_of(m, struct tmio_nand, mtd) ++ ++#ifdef CONFIG_MTD_CMDLINE_PARTS ++static const char *part_probes[] = { "cmdlinepart", NULL }; ++#endif ++ ++/*--------------------------------------------------------------------------*/ ++ ++static void tmio_nand_hwcontrol(struct mtd_info *mtd, int cmd, ++ unsigned int ctrl) ++{ ++ struct tmio_nand *tmio = mtd_to_tmio(mtd); ++ struct tmio_nfcr __iomem *fcr = tmio->fcr; ++ struct nand_chip *chip = mtd->priv; ++ ++ if (ctrl & NAND_CTRL_CHANGE) { ++ u8 mode; ++ ++ if (ctrl & NAND_NCE) { ++ mode = FCR_MODE_DATA; ++ ++ if (ctrl & NAND_CLE) ++ mode |= FCR_MODE_CLE; ++ else ++ mode &= ~FCR_MODE_CLE; ++ ++ if (ctrl & NAND_ALE) ++ mode |= FCR_MODE_ALE; ++ else ++ mode &= ~FCR_MODE_ALE; ++ } else { ++ mode = FCR_MODE_STANDBY; ++ } ++ ++ iowrite8(mode, &fcr->mode); ++ tmio->read_good = 0; ++ } ++ ++ if (cmd != NAND_CMD_NONE) ++ writeb(cmd, chip->IO_ADDR_W); ++} ++ ++static int tmio_nand_dev_ready(struct mtd_info *mtd) ++{ ++ struct tmio_nand *tmio = mtd_to_tmio(mtd); ++ struct tmio_nfcr __iomem *fcr = tmio->fcr; ++ ++ return !(ioread8(&fcr->status) & FCR_STATUS_BUSY); ++} ++ ++static irqreturn_t tmio_irq(int irq, void *__dev) ++{ ++ struct platform_device *dev = __dev; ++ struct tmio_nand *tmio = platform_get_drvdata(dev); ++ struct nand_chip *nand_chip = &tmio->chip; ++ struct tmio_nfcr __iomem *fcr = tmio->fcr; ++ ++ /* disable RDYREQ interrupt */ ++ iowrite8(0x00, &fcr->imr); ++ ++ if (unlikely(!waitqueue_active(&nand_chip->controller->wq))) ++ dev_warn(&dev->dev, "spurious interrupt\n"); ++ ++ wake_up(&nand_chip->controller->wq); ++ return IRQ_HANDLED; ++} ++ ++/* ++ *The TMIO core has a RDYREQ interrupt on the posedge of #SMRB. ++ *This interrupt is normally disabled, but for long operations like ++ *erase and write, we enable it to wake us up. The irq handler ++ *disables the interrupt. ++ */ ++static int ++tmio_nand_wait(struct mtd_info *mtd, struct nand_chip *nand_chip) ++{ ++ struct tmio_nand *tmio = mtd_to_tmio(mtd); ++ struct tmio_nfcr __iomem *fcr = tmio->fcr; ++ long timeout; ++ ++ /* enable RDYREQ interrupt */ ++ iowrite8(0x0f, &fcr->isr); ++ iowrite8(0x81, &fcr->imr); ++ ++ timeout = wait_event_timeout(nand_chip->controller->wq, tmio_nand_dev_ready(mtd), ++ msecs_to_jiffies(nand_chip->state == FL_ERASING ? 400 : 20)); ++ ++ if (unlikely(!tmio_nand_dev_ready(mtd))) { ++ iowrite8(0x00, &fcr->imr); ++ dev_warn(&tmio->dev->dev, "still busy with %s after %d ms\n", ++ nand_chip->state == FL_ERASING ? "erase" : "program", ++ nand_chip->state == FL_ERASING ? 400 : 20); ++ ++ } else if (unlikely(!timeout)) { ++ iowrite8(0x00, &fcr->imr); ++ dev_warn(&tmio->dev->dev, "timeout waiting for interrupt\n"); ++ } ++ ++ nand_chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); ++ return nand_chip->read_byte(mtd); ++} ++ ++/* ++ *The TMIO controller combines two 8-bit data bytes into one 16-bit ++ *word. This function separates them so nand_base.c works as expected, ++ *especially its NAND_CMD_READID routines. ++ * ++ *To prevent stale data from being read, tmio_nand_hwcontrol() clears ++ *tmio->read_good. ++ */ ++static u_char tmio_nand_read_byte(struct mtd_info *mtd) ++{ ++ struct tmio_nand *tmio = mtd_to_tmio(mtd); ++ struct tmio_nfcr __iomem *fcr = tmio->fcr; ++ unsigned int data; ++ ++ if (tmio->read_good--) ++ return tmio->read; ++ ++ data = ioread16(&fcr->u16); ++ tmio->read = data >> 8; ++ return data; ++} ++ ++/* ++ *The TMIO controller converts an 8-bit NAND interface to a 16-bit ++ *bus interface, so all data reads and writes must be 16-bit wide. ++ *Thus, we implement 16-bit versions of the read, write, and verify ++ *buffer functions. ++ */ ++static void ++tmio_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) ++{ ++ struct tmio_nand *tmio = mtd_to_tmio(mtd); ++ struct tmio_nfcr __iomem *fcr = tmio->fcr; ++ ++ iowrite16_rep(&fcr->u16, buf, len >> 1); ++} ++ ++static void tmio_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) ++{ ++ struct tmio_nand *tmio = mtd_to_tmio(mtd); ++ struct tmio_nfcr __iomem *fcr = tmio->fcr; ++ ++ ioread16_rep(&fcr->u16, buf, len >> 1); ++} ++ ++static int ++tmio_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) ++{ ++ struct tmio_nand *tmio = mtd_to_tmio(mtd); ++ struct tmio_nfcr __iomem *fcr = tmio->fcr; ++ u16 *p = (u16 *) buf; ++ ++ for (len >>= 1; len; len--) ++ if (*(p++) != ioread16(&fcr->u16)) ++ return -EFAULT; ++ return 0; ++} ++ ++static void tmio_nand_enable_hwecc(struct mtd_info *mtd, int mode) ++{ ++ struct tmio_nand *tmio = mtd_to_tmio(mtd); ++ struct tmio_nfcr __iomem *fcr = tmio->fcr; ++ ++ iowrite8(FCR_MODE_HWECC_RESET, &fcr->mode); ++ ioread8(&fcr->u8); /* dummy read */ ++ iowrite8(FCR_MODE_HWECC_CALC, &fcr->mode); ++} ++ ++static int tmio_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, ++ u_char *ecc_code) ++{ ++ struct tmio_nand *tmio = mtd_to_tmio(mtd); ++ struct tmio_nfcr __iomem *fcr = tmio->fcr; ++ unsigned int ecc; ++ ++ iowrite8(FCR_MODE_HWECC_RESULT, &fcr->mode); ++ ++ ecc = ioread16(&fcr->u16); ++ ecc_code[1] = ecc; /* 000-255 LP7-0 */ ++ ecc_code[0] = ecc >> 8; /* 000-255 LP15-8 */ ++ ecc = ioread16(&fcr->u16); ++ ecc_code[2] = ecc; /* 000-255 CP5-0,11b */ ++ ecc_code[4] = ecc >> 8; /* 256-511 LP7-0 */ ++ ecc = ioread16(&fcr->u16); ++ ecc_code[3] = ecc; /* 256-511 LP15-8 */ ++ ecc_code[5] = ecc >> 8; /* 256-511 CP5-0,11b */ ++ ++ iowrite8(FCR_MODE_DATA, &fcr->mode); ++ return 0; ++} ++ ++static int tmio_hw_init(struct platform_device *dev, struct tmio_nand *tmio) ++{ ++ struct mfd_cell *cell = mfd_get_cell(dev); ++ const struct resource *nfcr = NULL; ++ struct tmio_nfhccr __iomem *ccr = tmio->ccr; ++ struct tmio_nfcr __iomem *fcr = tmio->fcr; ++ unsigned long base; ++ int i; ++ ++ for (i = 0; i < cell->num_resources; i++) ++ if (!strcmp((cell->resources+i)->name, TMIO_NAND_CONTROL)) ++ nfcr = &cell->resources[i]; ++ ++ if (nfcr == NULL) ++ return -ENOMEM; ++ ++ if (!cell->enable) { ++ printk(KERN_ERR "null cell enable!"); ++ return -EINVAL; ++ } ++ ++ cell->enable(dev); ++ ++ /* (4Ch) CLKRUN Enable 1st spcrunc */ ++ iowrite8(0x81, &ccr->icc); ++ ++ /* (10h)BaseAddress 0x1000 spba.spba2 */ ++ base = nfcr->start; ++ iowrite16(base, ccr->base + 0); ++ iowrite16(base >> 16, ccr->base + 1); ++ ++ /* (04h)Command Register I/O spcmd */ ++ iowrite8(0x02, &ccr->command); ++ ++ /* (62h) Power Supply Control ssmpwc */ ++ /* HardPowerOFF - SuspendOFF - PowerSupplyWait_4MS */ ++ iowrite8(0x02, &ccr->nfpsc); ++ ++ /* (63h) Detect Control ssmdtc */ ++ iowrite8(0x02, &ccr->nfdc); ++ ++ /* Interrupt status register clear sintst */ ++ iowrite8(0x0f, &fcr->isr); ++ ++ /* After power supply, Media are reset smode */ ++ iowrite8(FCR_MODE_POWER_ON, &fcr->mode); ++ iowrite8(FCR_MODE_COMMAND, &fcr->mode); ++ iowrite8(NAND_CMD_RESET, &fcr->u8); ++ ++ /* Standby Mode smode */ ++ iowrite8(FCR_MODE_STANDBY, &fcr->mode); ++ ++ mdelay(5); ++ ++ return 0; ++} ++ ++static void tmio_hw_stop(struct platform_device *dev, struct tmio_nand *tmio) ++{ ++ struct mfd_cell *cell = mfd_get_cell(dev); ++ struct tmio_nfcr __iomem *fcr = tmio->fcr; ++ ++ iowrite8(FCR_MODE_POWER_OFF, &fcr->mode); ++ cell->disable(dev); ++} ++ ++static int tmio_probe(struct platform_device *dev) ++{ ++ struct mfd_cell *cell = mfd_get_cell(dev); ++ struct tmio_nand_data *data = cell->driver_data; ++ struct resource *ccr = platform_get_resource_byname(dev, IORESOURCE_MEM, TMIO_NAND_CONFIG); ++ struct resource *fcr = platform_get_resource_byname(dev, IORESOURCE_MEM, TMIO_NAND_CONTROL); ++ int irq = platform_get_irq(dev, 0); ++ struct tmio_nand *tmio; ++ struct mtd_info *mtd; ++ struct nand_chip *nand_chip; ++ struct mtd_partition *parts; ++ int nbparts = 0; ++ int retval; ++ ++ if (data == NULL) { ++ dev_err(&dev->dev, "NULL platform data!\n"); ++ return -EINVAL; ++ } ++ ++ tmio = kzalloc(sizeof *tmio, GFP_KERNEL); ++ if (!tmio) { ++ retval = -ENOMEM; ++ goto err_kzalloc; ++ } ++ ++ tmio->dev = dev; ++ ++ platform_set_drvdata(dev, tmio); ++ mtd = &tmio->mtd; ++ nand_chip = &tmio->chip; ++ mtd->priv = nand_chip; ++ mtd->name = "tmio-nand"; ++ ++ tmio->ccr = ioremap(ccr->start, ccr->end - ccr->start + 1); ++ if (!tmio->ccr) { ++ retval = -EIO; ++ goto err_iomap_ccr; ++ } ++ ++ tmio->fcr = ioremap(fcr->start, fcr->end - fcr->start + 1); ++ if (!tmio->fcr) { ++ retval = -EIO; ++ goto err_iomap_fcr; ++ } ++ ++ retval = tmio_hw_init(dev, tmio); ++ if (retval) ++ goto err_hwinit; ++ ++ /* Set address of NAND IO lines */ ++ nand_chip->IO_ADDR_R = tmio->fcr; ++ nand_chip->IO_ADDR_W = tmio->fcr; ++ ++ /* Set address of hardware control function */ ++ nand_chip->cmd_ctrl = tmio_nand_hwcontrol; ++ nand_chip->dev_ready = tmio_nand_dev_ready; ++ nand_chip->read_byte = tmio_nand_read_byte; ++ nand_chip->write_buf = tmio_nand_write_buf; ++ nand_chip->read_buf = tmio_nand_read_buf; ++ nand_chip->verify_buf = tmio_nand_verify_buf; ++ ++ /* set eccmode using hardware ECC */ ++ nand_chip->ecc.mode = NAND_ECC_HW; ++ nand_chip->ecc.size = 512; ++ nand_chip->ecc.bytes = 6; ++ nand_chip->ecc.hwctl = tmio_nand_enable_hwecc; ++ nand_chip->ecc.calculate = tmio_nand_calculate_ecc; ++ nand_chip->ecc.correct = nand_correct_data; ++ nand_chip->badblock_pattern = data->badblock_pattern; ++ ++ /* 15 us command delay time */ ++ nand_chip->chip_delay = 15; ++ ++ retval = request_irq(irq, &tmio_irq, ++ IRQF_DISABLED, dev->dev.bus_id, dev); ++ if (retval) { ++ dev_err(&dev->dev, "request_irq error %d\n", retval); ++ goto err_irq; ++ } ++ ++ tmio->irq = irq; ++ nand_chip->waitfunc = tmio_nand_wait; ++ ++ /* Scan to find existence of the device */ ++ if (nand_scan(mtd, 1)) { ++ retval = -ENODEV; ++ goto err_scan; ++ } ++ /* Register the partitions */ ++#ifdef CONFIG_MTD_PARTITIONS ++#ifdef CONFIG_MTD_CMDLINE_PARTS ++ nbparts = parse_mtd_partitions(mtd, part_probes, &parts, 0); ++#endif ++ if (nbparts <= 0) { ++ parts = data->partition; ++ nbparts = data->num_partitions; ++ } ++ ++ retval = add_mtd_partitions(mtd, parts, nbparts); ++#else ++ retval = add_mtd_device(mtd); ++#endif ++ ++ if (!retval) ++ return retval; ++ ++ nand_release(mtd); ++ ++err_scan: ++ if (tmio->irq) ++ free_irq(tmio->irq, dev); ++err_irq: ++ tmio_hw_stop(dev, tmio); ++err_hwinit: ++ iounmap(tmio->fcr); ++err_iomap_fcr: ++ iounmap(tmio->ccr); ++err_iomap_ccr: ++ kfree(tmio); ++err_kzalloc: ++ return retval; ++} ++ ++static int tmio_remove(struct platform_device *dev) ++{ ++ struct tmio_nand *tmio = platform_get_drvdata(dev); ++ ++ nand_release(&tmio->mtd); ++ if (tmio->irq) ++ free_irq(tmio->irq, tmio); ++ tmio_hw_stop(dev, tmio); ++ iounmap(tmio->fcr); ++ iounmap(tmio->ccr); ++ kfree(tmio); ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int tmio_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ struct mfd_cell *cell = mfd_get_cell(dev); ++ ++ if (cell->suspend) ++ cell->suspend(dev); ++ ++ tmio_hw_stop(dev, platform_get_drvdata(dev)); ++ return 0; ++} ++ ++static int tmio_resume(struct platform_device *dev) ++{ ++ struct mfd_cell *cell = mfd_get_cell(dev); ++ ++ tmio_hw_init(dev, platform_get_drvdata(dev)); ++ ++ if (cell->resume) ++ cell->resume(dev); ++ ++ return 0; ++} ++#endif ++ ++static struct platform_driver tmio_driver = { ++ .driver.name = "tmio-nand", ++ .driver.owner = THIS_MODULE, ++ .probe = tmio_probe, ++ .remove = tmio_remove, ++#ifdef CONFIG_PM ++ .suspend = tmio_suspend, ++ .resume = tmio_resume, ++#endif ++}; ++ ++static int __init tmio_init(void) ++{ ++ return platform_driver_register(&tmio_driver); ++} ++ ++static void __exit tmio_exit(void) ++{ ++ platform_driver_unregister(&tmio_driver); ++} ++ ++module_init(tmio_init); ++module_exit(tmio_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Dirk Opfer, Chris Humbert, Dmitry Baryshkov"); ++MODULE_DESCRIPTION("NAND flash driver on Toshiba Mobile IO controller"); +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0009-FB-driver-for-TMIO-devices.patch b/packages/linux/linux-rp-2.6.24/tosa/0009-FB-driver-for-TMIO-devices.patch new file mode 100644 index 0000000000..5fc96f8973 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0009-FB-driver-for-TMIO-devices.patch @@ -0,0 +1,1128 @@ +From 519d015892ab0a7cad1f6b26fcd38117171384ce Mon Sep 17 00:00:00 2001 +From: Ian Molton <spyro@f2s.com> +Date: Tue, 1 Jan 2008 21:22:23 +0000 +Subject: [PATCH 09/64] FB driver for TMIO devices + +--- + drivers/video/Kconfig | 22 + + drivers/video/Makefile | 1 + + drivers/video/tmiofb.c | 1062 ++++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 1085 insertions(+), 0 deletions(-) + create mode 100644 drivers/video/tmiofb.c + +diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig +index 5b3dbcf..6d0df58 100644 +--- a/drivers/video/Kconfig ++++ b/drivers/video/Kconfig +@@ -1782,6 +1782,28 @@ config FB_W100 + + If unsure, say N. + ++config FB_TMIO ++ tristate "Toshiba Mobice IO FrameBuffer support" ++ depends on FB && MFD_CORE ++ select FB_CFB_FILLRECT ++ select FB_CFB_COPYAREA ++ select FB_CFB_IMAGEBLIT ++ ---help--- ++ Frame buffer driver for the Toshiba Mobile IO integrated as found ++ on the Sharp SL-6000 series ++ ++ This driver is also available as a module ( = code which can be ++ inserted and removed from the running kernel whenever you want). The ++ module will be called tmiofb. If you want to compile it as a module, ++ say M here and read <file:Documentation/kbuild/modules.txt>. ++ ++ If unsure, say N. ++ ++config FB_TMIO_ACCELL ++ bool "tmiofb acceleration" ++ depends on FB_TMIO ++ default y ++ + config FB_S3C2410 + tristate "S3C2410 LCD framebuffer support" + depends on FB && ARCH_S3C2410 +diff --git a/drivers/video/Makefile b/drivers/video/Makefile +index 83e02b3..74e9384 100644 +--- a/drivers/video/Makefile ++++ b/drivers/video/Makefile +@@ -97,6 +97,7 @@ obj-$(CONFIG_FB_CIRRUS) += cirrusfb.o + obj-$(CONFIG_FB_ASILIANT) += asiliantfb.o + obj-$(CONFIG_FB_PXA) += pxafb.o + obj-$(CONFIG_FB_W100) += w100fb.o ++obj-$(CONFIG_FB_TMIO) += tmiofb.o + obj-$(CONFIG_FB_AU1100) += au1100fb.o + obj-$(CONFIG_FB_AU1200) += au1200fb.o + obj-$(CONFIG_FB_PMAG_AA) += pmag-aa-fb.o +diff --git a/drivers/video/tmiofb.c b/drivers/video/tmiofb.c +new file mode 100644 +index 0000000..6b963a1 +--- /dev/null ++++ b/drivers/video/tmiofb.c +@@ -0,0 +1,1062 @@ ++/* ++ * Frame Buffer Device for Toshiba Mobile IO(TMIO) controller ++ * ++ * Copyright(C) 2005-2006 Chris Humbert ++ * Copyright(C) 2005 Dirk Opfer ++ * ++ * Based on: ++ * drivers/video/w100fb.c ++ * code written by Sharp/Lineo for 2.4 kernels ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/platform_device.h> ++#include <linux/mfd-core.h> ++#include <linux/mfd/tmio.h> ++#include <linux/fb.h> ++#include <linux/interrupt.h> ++#include <linux/delay.h> ++/* Why should fb driver call console functions? because acquire_console_sem() */ ++#include <linux/console.h> ++#include <linux/uaccess.h> ++#include <linux/vmalloc.h> ++ ++/* ++ * accelerator commands ++ */ ++#define TMIOFB_ACC_CSADR(x) (0x00000000 | ((x) & 0x001ffffe)) ++#define TMIOFB_ACC_CHPIX(x) (0x01000000 | ((x) & 0x000003ff)) ++#define TMIOFB_ACC_CVPIX(x) (0x02000000 | ((x) & 0x000003ff)) ++#define TMIOFB_ACC_PSADR(x) (0x03000000 | ((x) & 0x00fffffe)) ++#define TMIOFB_ACC_PHPIX(x) (0x04000000 | ((x) & 0x000003ff)) ++#define TMIOFB_ACC_PVPIX(x) (0x05000000 | ((x) & 0x000003ff)) ++#define TMIOFB_ACC_PHOFS(x) (0x06000000 | ((x) & 0x000003ff)) ++#define TMIOFB_ACC_PVOFS(x) (0x07000000 | ((x) & 0x000003ff)) ++#define TMIOFB_ACC_POADR(x) (0x08000000 | ((x) & 0x00fffffe)) ++#define TMIOFB_ACC_RSTR(x) (0x09000000 | ((x) & 0x000000ff)) ++#define TMIOFB_ACC_TCLOR(x) (0x0A000000 | ((x) & 0x0000ffff)) ++#define TMIOFB_ACC_FILL(x) (0x0B000000 | ((x) & 0x0000ffff)) ++#define TMIOFB_ACC_DSADR(x) (0x0C000000 | ((x) & 0x00fffffe)) ++#define TMIOFB_ACC_SSADR(x) (0x0D000000 | ((x) & 0x00fffffe)) ++#define TMIOFB_ACC_DHPIX(x) (0x0E000000 | ((x) & 0x000003ff)) ++#define TMIOFB_ACC_DVPIX(x) (0x0F000000 | ((x) & 0x000003ff)) ++#define TMIOFB_ACC_SHPIX(x) (0x10000000 | ((x) & 0x000003ff)) ++#define TMIOFB_ACC_SVPIX(x) (0x11000000 | ((x) & 0x000003ff)) ++#define TMIOFB_ACC_LBINI(x) (0x12000000 | ((x) & 0x0000ffff)) ++#define TMIOFB_ACC_LBK2(x) (0x13000000 | ((x) & 0x0000ffff)) ++#define TMIOFB_ACC_SHBINI(x) (0x14000000 | ((x) & 0x0000ffff)) ++#define TMIOFB_ACC_SHBK2(x) (0x15000000 | ((x) & 0x0000ffff)) ++#define TMIOFB_ACC_SVBINI(x) (0x16000000 | ((x) & 0x0000ffff)) ++#define TMIOFB_ACC_SVBK2(x) (0x17000000 | ((x) & 0x0000ffff)) ++ ++#define TMIOFB_ACC_CMGO 0x20000000 ++#define TMIOFB_ACC_CMGO_CEND 0x00000001 ++#define TMIOFB_ACC_CMGO_INT 0x00000002 ++#define TMIOFB_ACC_CMGO_CMOD 0x00000010 ++#define TMIOFB_ACC_CMGO_CDVRV 0x00000020 ++#define TMIOFB_ACC_CMGO_CDHRV 0x00000040 ++#define TMIOFB_ACC_CMGO_RUND 0x00008000 ++#define TMIOFB_ACC_SCGO 0x21000000 ++#define TMIOFB_ACC_SCGO_CEND 0x00000001 ++#define TMIOFB_ACC_SCGO_INT 0x00000002 ++#define TMIOFB_ACC_SCGO_ROP3 0x00000004 ++#define TMIOFB_ACC_SCGO_TRNS 0x00000008 ++#define TMIOFB_ACC_SCGO_DVRV 0x00000010 ++#define TMIOFB_ACC_SCGO_DHRV 0x00000020 ++#define TMIOFB_ACC_SCGO_SVRV 0x00000040 ++#define TMIOFB_ACC_SCGO_SHRV 0x00000080 ++#define TMIOFB_ACC_SCGO_DSTXY 0x00008000 ++#define TMIOFB_ACC_SBGO 0x22000000 ++#define TMIOFB_ACC_SBGO_CEND 0x00000001 ++#define TMIOFB_ACC_SBGO_INT 0x00000002 ++#define TMIOFB_ACC_SBGO_DVRV 0x00000010 ++#define TMIOFB_ACC_SBGO_DHRV 0x00000020 ++#define TMIOFB_ACC_SBGO_SVRV 0x00000040 ++#define TMIOFB_ACC_SBGO_SHRV 0x00000080 ++#define TMIOFB_ACC_SBGO_SBMD 0x00000100 ++#define TMIOFB_ACC_FLGO 0x23000000 ++#define TMIOFB_ACC_FLGO_CEND 0x00000001 ++#define TMIOFB_ACC_FLGO_INT 0x00000002 ++#define TMIOFB_ACC_FLGO_ROP3 0x00000004 ++#define TMIOFB_ACC_LDGO 0x24000000 ++#define TMIOFB_ACC_LDGO_CEND 0x00000001 ++#define TMIOFB_ACC_LDGO_INT 0x00000002 ++#define TMIOFB_ACC_LDGO_ROP3 0x00000004 ++#define TMIOFB_ACC_LDGO_ENDPX 0x00000008 ++#define TMIOFB_ACC_LDGO_LVRV 0x00000010 ++#define TMIOFB_ACC_LDGO_LHRV 0x00000020 ++#define TMIOFB_ACC_LDGO_LDMOD 0x00000040 ++ ++/* a FIFO is always allocated, even if acceleration is not used */ ++#define TMIOFB_FIFO_SIZE 512 ++ ++/* ++ * LCD Host Controller Configuration Register ++ * ++ * This iomem area supports only 16-bit IO. ++ */ ++struct tmio_lhccr { ++ u16 x00[2]; ++ u16 cmd; /* 0x04 Command */ ++ u16 x01; ++ u16 revid; /* 0x08 Revision ID */ ++ u16 x02[3]; ++ u16 basel; /* 0x10 LCD Control Reg Base Addr Low */ ++ u16 baseh; /* 0x12 LCD Control Reg Base Addr High */ ++ u16 x03[0x16]; ++ u16 ugcc; /* 0x40 Unified Gated Clock Control */ ++ u16 gcc; /* 0x42 Gated Clock Control */ ++ u16 x04[6]; ++ u16 usc; /* 0x50 Unified Software Clear */ ++ u16 x05[7]; ++ u16 vramrtc; /* 0x60 VRAM Timing Control */ ++ /* 0x61 VRAM Refresh Control */ ++ u16 vramsac; /* 0x62 VRAM Access Control */ ++ /* 0x63 VRAM Status */ ++ u16 vrambc; /* 0x64 VRAM Block Control */ ++ u16 x06[0x4d]; ++}; ++ ++/* ++ * LCD Control Register ++ * ++ * This iomem area supports only 16-bit IO. ++ */ ++struct tmio_lcr { ++ u16 uis; /* 0x000 Unified Interrupt Status */ ++ u16 x00[3]; ++ u16 vhpn; /* 0x008 VRAM Horizontal Pixel Number */ ++ u16 cfsal; /* 0x00a Command FIFO Start Address Low */ ++ u16 cfsah; /* 0x00c Command FIFO Start Address High */ ++ u16 cfs; /* 0x00e Command FIFO Size */ ++ u16 cfws; /* 0x010 Command FIFO Writeable Size */ ++ u16 bbie; /* 0x012 BitBLT Interrupt Enable */ ++ u16 bbisc; /* 0x014 BitBLT Interrupt Status and Clear */ ++ u16 ccs; /* 0x016 Command Count Status */ ++ u16 bbes; /* 0x018 BitBLT Execution Status */ ++ u16 x01; ++ u16 cmdl; /* 0x01c Command Low */ ++ u16 cmdh; /* 0x01e Command High */ ++ u16 x02; ++ u16 cfc; /* 0x022 Command FIFO Clear */ ++ u16 ccifc; /* 0x024 CMOS Camera IF Control */ ++ u16 hwt; /* 0x026 Hardware Test */ ++ u16 x03[0x6c]; ++ u16 lcdccrc;/* 0x100 LCDC Clock and Reset Control */ ++ u16 lcdcc; /* 0x102 LCDC Control */ ++ u16 lcdcopc;/* 0x104 LCDC Output Pin Control */ ++ u16 x04; ++ u16 lcdis; /* 0x108 LCD Interrupt Status */ ++ u16 lcdim; /* 0x10a LCD Interrupt Mask */ ++ u16 lcdie; /* 0x10c LCD Interrupt Enable */ ++ u16 x05[10]; ++ u16 gdsal; /* 0x122 Graphics Display Start Address Low */ ++ u16 gdsah; /* 0x124 Graphics Display Start Address High */ ++ u16 x06[2]; ++ u16 vhpcl; /* 0x12a VRAM Horizontal Pixel Count Low */ ++ u16 vhpch; /* 0x12c VRAM Horizontal Pixel Count High */ ++ u16 gm; /* 0x12e Graphic Mode(VRAM access enable) */ ++ u16 x07[8]; ++ u16 ht; /* 0x140 Horizontal Total */ ++ u16 hds; /* 0x142 Horizontal Display Start */ ++ u16 hss; /* 0x144 H-Sync Start */ ++ u16 hse; /* 0x146 H-Sync End */ ++ u16 x08[2]; ++ u16 hnp; /* 0x14c Horizontal Number of Pixels */ ++ u16 x09; ++ u16 vt; /* 0x150 Vertical Total */ ++ u16 vds; /* 0x152 Vertical Display Start */ ++ u16 vss; /* 0x154 V-Sync Start */ ++ u16 vse; /* 0x156 V-Sync End */ ++ u16 x0a[4]; ++ u16 cdln; /* 0x160 Current Display Line Number */ ++ u16 iln; /* 0x162 Interrupt Line Number */ ++ u16 sp; /* 0x164 Sync Polarity */ ++ u16 misc; /* 0x166 MISC(RGB565 mode) */ ++ u16 x0b; ++ u16 vihss; /* 0x16a Video Interface H-Sync Start */ ++ u16 vivs; /* 0x16c Video Interface Vertical Start */ ++ u16 vive; /* 0x16e Video Interface Vertical End */ ++ u16 vivss; /* 0x170 Video Interface V-Sync Start */ ++ u16 x0c[6]; ++ u16 vccis; /* 0x17e Video / CMOS Camera Interface Select */ ++ u16 vidwsal;/* 0x180 VI Data Write Start Address Low */ ++ u16 vidwsah;/* 0x182 VI Data Write Start Address High */ ++ u16 vidrsal;/* 0x184 VI Data Read Start Address Low */ ++ u16 vidrsah;/* 0x186 VI Data Read Start Address High */ ++ u16 vipddst;/* 0x188 VI Picture Data Display Start Timing */ ++ u16 vipddet;/* 0x186 VI Picture Data Display End Timing */ ++ u16 vie; /* 0x18c Video Interface Enable */ ++ u16 vcs; /* 0x18e Video/Camera Select */ ++ u16 x0d[2]; ++ u16 vphwc; /* 0x194 Video Picture Horizontal Wait Count */ ++ u16 vphs; /* 0x196 Video Picture Horizontal Size */ ++ u16 vpvwc; /* 0x198 Video Picture Vertical Wait Count */ ++ u16 vpvs; /* 0x19a Video Picture Vertical Size */ ++ u16 x0e[2]; ++ u16 plhpix; /* 0x1a0 PLHPIX */ ++ u16 xs; /* 0x1a2 XStart */ ++ u16 xckhw; /* 0x1a4 XCK High Width */ ++ u16 x0f; ++ u16 sths; /* 0x1a8 STH Start */ ++ u16 vt2; /* 0x1aa Vertical Total */ ++ u16 ycksw; /* 0x1ac YCK Start Wait */ ++ u16 ysts; /* 0x1ae YST Start */ ++ u16 ppols; /* 0x1b0 #PPOL Start */ ++ u16 precw; /* 0x1b2 PREC Width */ ++ u16 vclkhw; /* 0x1b4 VCLK High Width */ ++ u16 oc; /* 0x1b6 Output Control */ ++ u16 x10[0x24]; ++}; ++static char *mode_option __devinitdata; ++ ++struct tmiofb_par { ++ u32 pseudo_palette[16]; ++ ++#ifdef CONFIG_FB_TMIO_ACCELL ++ wait_queue_head_t wait_acc; ++ bool use_polling; ++#endif ++ ++ struct tmio_lhccr __iomem *ccr; ++ struct tmio_lcr __iomem *lcr; ++ void __iomem *vram; ++}; ++ ++/*--------------------------------------------------------------------------*/ ++ ++static irqreturn_t tmiofb_irq(int irq, void *__info); ++ ++/*--------------------------------------------------------------------------*/ ++ ++ ++/* ++ * Turns off the LCD controller and LCD host controller. ++ */ ++static int tmiofb_hw_stop(struct platform_device *dev) ++{ ++ struct mfd_cell *cell = mfd_get_cell(dev); ++ struct tmio_fb_data *data = cell->driver_data; ++ struct fb_info *info = platform_get_drvdata(dev); ++ struct tmiofb_par *par = info->par; ++ struct tmio_lhccr __iomem *ccr = par->ccr; ++ struct tmio_lcr __iomem *lcr = par->lcr; ++ ++ iowrite16(0, &ccr->ugcc); ++ iowrite16(0, &lcr->gm); ++ data->lcd_set_power(dev, 0); ++ iowrite16(0x0010, &lcr->lcdccrc); ++ ++ return 0; ++} ++ ++/* ++ * Initializes the LCD host controller. ++ */ ++static int tmiofb_hw_init(struct platform_device *dev) ++{ ++ struct mfd_cell *cell = mfd_get_cell(dev); ++ struct tmio_fb_data *data = cell->driver_data; ++ struct fb_info *info = platform_get_drvdata(dev); ++ struct tmiofb_par *par = info->par; ++ struct tmio_lhccr __iomem *ccr = par->ccr; ++ struct tmio_lcr __iomem *lcr = par->lcr; ++ const struct resource *nlcr = NULL; ++ const struct resource *vram = NULL; ++ unsigned long base; ++ int i; ++ ++ for (i = 0; i < cell->num_resources; i++) { ++ if (!strcmp((cell->resources+i)->name, TMIO_FB_CONTROL)) ++ nlcr = &cell->resources[i]; ++ if (!strcmp((cell->resources+i)->name, TMIO_FB_VRAM)) ++ vram = &cell->resources[i]; ++ } ++ ++ if (nlcr == NULL || vram == NULL) ++ return -EINVAL; ++ ++ base = nlcr->start; ++ ++ if (info->mode == NULL) { ++ printk(KERN_ERR "tmio-fb: null info->mode\n"); ++ info->mode = data->modes; ++ } ++ ++ data->lcd_mode(dev, info->mode); ++ ++ iowrite16(0x003a, &ccr->ugcc); ++ iowrite16(0x003a, &ccr->gcc); ++ iowrite16(0x3f00, &ccr->usc); ++ ++ data->lcd_set_power(dev, 1); ++ mdelay(2); ++ ++ iowrite16(0x0000, &ccr->usc); ++ iowrite16(base >> 16, &ccr->baseh); ++ iowrite16(base, &ccr->basel); ++ iowrite16(0x0002, &ccr->cmd); /* base address enable */ ++ iowrite16(0x40a8, &ccr->vramrtc); /* VRAMRC, VRAMTC */ ++ iowrite16(0x0018, &ccr->vramsac); /* VRAMSTS, VRAMAC */ ++ iowrite16(0x0002, &ccr->vrambc); ++ mdelay(2); ++ iowrite16(0x000b, &ccr->vrambc); ++ ++ base = vram->start + info->screen_size; ++ iowrite16(base >> 16, &lcr->cfsah); ++ iowrite16(base, &lcr->cfsal); ++ iowrite16(TMIOFB_FIFO_SIZE - 1, &lcr->cfs); ++ iowrite16(1, &lcr->cfc); ++ iowrite16(1, &lcr->bbie); ++ iowrite16(0, &lcr->cfws); ++ ++ return 0; ++} ++ ++/* ++ * Sets the LCD controller's output resolution and pixel clock ++ */ ++static void tmiofb_hw_mode(struct platform_device *dev) ++{ ++ struct mfd_cell *cell = mfd_get_cell(dev); ++ struct tmio_fb_data *data = cell->driver_data; ++ struct fb_info *info = platform_get_drvdata(dev); ++ struct fb_videomode *mode = info->mode; ++ struct tmiofb_par *par = info->par; ++ struct tmio_lcr __iomem *lcr = par->lcr; ++ unsigned int i; ++ ++ iowrite16(0, &lcr->gm); ++ data->lcd_set_power(dev, 0); ++ iowrite16(0x0010, &lcr->lcdccrc); ++ data->lcd_mode(dev, mode); ++ data->lcd_set_power(dev, 1); ++ ++ iowrite16(i = mode->xres * 2, &lcr->vhpn); ++ iowrite16(0, &lcr->gdsah); ++ iowrite16(0, &lcr->gdsal); ++ iowrite16(i >> 16, &lcr->vhpch); ++ iowrite16(i, &lcr->vhpcl); ++ iowrite16(i = 0, &lcr->hss); ++ iowrite16(i += mode->hsync_len, &lcr->hse); ++ iowrite16(i += mode->left_margin, &lcr->hds); ++ iowrite16(i += mode->xres + mode->right_margin, &lcr->ht); ++ iowrite16(mode->xres, &lcr->hnp); ++ iowrite16(i = 0, &lcr->vss); ++ iowrite16(i += mode->vsync_len, &lcr->vse); ++ iowrite16(i += mode->upper_margin, &lcr->vds); ++ iowrite16(i += mode->yres, &lcr->iln); ++ iowrite16(i += mode->lower_margin, &lcr->vt); ++ iowrite16(3, /* RGB565 mode */ &lcr->misc); ++ iowrite16(1, /* VRAM enable */ &lcr->gm); ++ iowrite16(0x4007, &lcr->lcdcc); ++ iowrite16(3, /* sync polarity */ &lcr->sp); ++ ++ iowrite16(0x0010, &lcr->lcdccrc); ++ mdelay(5); ++ iowrite16(0x0014, &lcr->lcdccrc); /* STOP_CKP */ ++ mdelay(5); ++ iowrite16(0x0015, &lcr->lcdccrc); /* STOP_CKP | SOFT_RESET */ ++ iowrite16(0xfffa, &lcr->vcs); ++} ++ ++/*--------------------------------------------------------------------------*/ ++ ++#ifdef CONFIG_FB_TMIO_ACCELL ++static int __must_check ++tmiofb_acc_wait(struct fb_info *info, unsigned int ccs) ++{ ++ struct tmiofb_par *par = info->par; ++ struct tmio_lcr __iomem *lcr = par->lcr; ++ if (in_atomic() || par->use_polling) { ++ int i = 0; ++ while (ioread16(&lcr->ccs) > ccs) { ++ udelay(1); ++ i++; ++ if (i > 10000) { ++ printk(KERN_ERR "tmiofb: timeout waiting for %d\n", ccs); ++ return -ETIMEDOUT; ++ } ++ tmiofb_irq(-1, info); ++ } ++ } else { ++ if (!wait_event_interruptible_timeout(par->wait_acc, ++ ioread16(&par->lcr->ccs) <= ccs, 1000)) { ++ printk(KERN_ERR "tmiofb: timeout waiting for %d\n", ccs); ++ return -ETIMEDOUT; ++ } ++ } ++ ++ return 0; ++} ++ ++/* ++ * Writes an accelerator command to the accelerator's FIFO. ++ */ ++static int ++tmiofb_acc_write(struct fb_info *info, const u32 *cmd, unsigned int count) ++{ ++ struct tmiofb_par *par = info->par; ++ struct tmio_lcr __iomem *lcr = par->lcr; ++ int ret; ++ ++ ret = tmiofb_acc_wait(info, TMIOFB_FIFO_SIZE - count); ++ if (ret) ++ return ret; ++ ++ for (; count; count--, cmd++) { ++ iowrite16(*cmd >> 16, &lcr->cmdh); ++ iowrite16(*cmd, &lcr->cmdl); ++ } ++ ++ return ret; ++} ++ ++/* ++ * Wait for the accelerator to finish its operations before writing ++ * to the framebuffer for consistent display output. ++ */ ++static int tmiofb_sync(struct fb_info *fbi) ++{ ++ struct tmiofb_par *par = fbi->par; ++ ++ int ret; ++ int i = 0; ++ ++ ret = tmiofb_acc_wait(fbi, 0); ++ ++ while (ioread16(&par->lcr->bbes) & 2) { /* blit active */ ++ udelay(1); ++ i++ ; ++ if (i > 10000) { ++ printk(KERN_ERR "timeout waiting for blit to end!\n"); ++ return -ETIMEDOUT; ++ } ++ } ++ ++ return ret; ++} ++ ++static void ++tmiofb_fillrect(struct fb_info *fbi, const struct fb_fillrect *rect) ++{ ++ const u32 cmd [] = { ++ TMIOFB_ACC_DSADR((rect->dy * fbi->mode->xres + rect->dx) * 2), ++ TMIOFB_ACC_DHPIX(rect->width - 1), ++ TMIOFB_ACC_DVPIX(rect->height - 1), ++ TMIOFB_ACC_FILL(rect->color), ++ TMIOFB_ACC_FLGO, ++ }; ++ ++ if (fbi->state != FBINFO_STATE_RUNNING || ++ fbi->flags & FBINFO_HWACCEL_DISABLED) { ++ cfb_fillrect(fbi, rect); ++ return; ++ } ++ ++ tmiofb_acc_write(fbi, cmd, ARRAY_SIZE(cmd)); ++} ++ ++static void ++tmiofb_copyarea(struct fb_info *fbi, const struct fb_copyarea *area) ++{ ++ const u32 cmd [] = { ++ TMIOFB_ACC_DSADR((area->dy * fbi->mode->xres + area->dx) * 2), ++ TMIOFB_ACC_DHPIX(area->width - 1), ++ TMIOFB_ACC_DVPIX(area->height - 1), ++ TMIOFB_ACC_SSADR((area->sy * fbi->mode->xres + area->sx) * 2), ++ TMIOFB_ACC_SCGO, ++ }; ++ ++ if (fbi->state != FBINFO_STATE_RUNNING || ++ fbi->flags & FBINFO_HWACCEL_DISABLED) { ++ cfb_copyarea(fbi, area); ++ return; ++ } ++ ++ tmiofb_acc_write(fbi, cmd, ARRAY_SIZE(cmd)); ++} ++#endif ++ ++static void tmiofb_clearscreen(struct fb_info *info) ++{ ++ const struct fb_fillrect rect = { ++ .dx = 0, ++ .dy = 0, ++ .width = info->mode->xres, ++ .height = info->mode->yres, ++ .color = 0, ++ }; ++ ++ info->fbops->fb_fillrect(info, &rect); ++} ++ ++static int tmiofb_vblank(struct fb_info *fbi, struct fb_vblank *vblank) ++{ ++ struct tmiofb_par *par = fbi->par; ++ struct fb_videomode *mode = fbi->mode; ++ unsigned int vcount = ioread16(&par->lcr->cdln); ++ unsigned int vds = mode->vsync_len + mode->upper_margin; ++ ++ vblank->vcount = vcount; ++ vblank->flags = FB_VBLANK_HAVE_VBLANK | FB_VBLANK_HAVE_VCOUNT ++ | FB_VBLANK_HAVE_VSYNC; ++ ++ if (vcount < mode->vsync_len) ++ vblank->flags |= FB_VBLANK_VSYNCING; ++ ++ if (vcount < vds || vcount > vds + mode->yres) ++ vblank->flags |= FB_VBLANK_VBLANKING; ++ ++ return 0; ++} ++ ++ ++static int tmiofb_ioctl(struct fb_info *fbi, ++ unsigned int cmd, unsigned long arg) ++{ ++ switch (cmd) { ++ case FBIOGET_VBLANK: { ++ struct fb_vblank vblank = {0}; ++ void __user *argp = (void __user *) arg; ++ ++ tmiofb_vblank(fbi, &vblank); ++ if (copy_to_user(argp, &vblank, sizeof vblank)) ++ return -EFAULT; ++ return 0; ++ } ++ ++#ifdef CONFIG_FB_TMIO_ACCELL ++ case FBIO_TMIO_ACC_SYNC: ++ tmiofb_sync(fbi); ++ return 0; ++ ++ case FBIO_TMIO_ACC_WRITE: { ++ u32 __user *argp = (void __user *) arg; ++ u32 len; ++ u32 acc [16]; ++ ++ if (copy_from_user(&len, argp, sizeof(u32))) ++ return -EFAULT; ++ if (len > ARRAY_SIZE(acc)) ++ return -EINVAL; ++ if (copy_from_user(acc, argp + 1, sizeof(u32) * len)) ++ return -EFAULT; ++ ++ return tmiofb_acc_write(fbi, acc, len); ++ } ++#endif ++ } ++ ++ return -EINVAL; ++} ++ ++/*--------------------------------------------------------------------------*/ ++ ++/* Select the smallest mode that allows the desired resolution to be ++ * displayed. If desired, the x and y parameters can be rounded up to ++ * match the selected mode. ++ */ ++static struct fb_videomode* ++tmiofb_find_mode(struct fb_info *info, struct fb_var_screeninfo *var) ++{ ++ struct mfd_cell *cell = mfd_get_cell(to_platform_device(info->device)); ++ struct tmio_fb_data *data = cell->driver_data; ++ struct fb_videomode *best = NULL; ++ int i; ++ ++ for (i = 0; i < data->num_modes; i++) { ++ struct fb_videomode *mode = data->modes + i; ++ ++ if (mode->xres >= var->xres && mode->yres >= var->yres ++ && (!best || (mode->xres < best->xres ++ && mode->yres < best->yres))) ++ best = mode; ++ } ++ ++ return best; ++} ++ ++static int tmiofb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) ++{ ++ ++ struct fb_videomode *mode; ++ ++ mode = tmiofb_find_mode(info, var); ++ if (!mode || var->bits_per_pixel > 16) ++ return -EINVAL; ++ ++ fb_videomode_to_var(var, mode); ++ ++ var->xres_virtual = mode->xres; ++ var->yres_virtual = info->screen_size / (mode->xres * 2); ++ var->xoffset = 0; ++ var->yoffset = 0; ++ var->bits_per_pixel = 16; ++ var->grayscale = 0; ++ var->red.offset = 11; var->red.length = 5; ++ var->green.offset = 5; var->green.length = 6; ++ var->blue.offset = 0; var->blue.length = 5; ++ var->transp.offset = 0; var->transp.length = 0; ++ var->nonstd = 0; ++ var->height = 82; /* mm */ ++ var->width = 60; /* mm */ ++ var->rotate = 0; ++ return 0; ++} ++ ++static int tmiofb_set_par(struct fb_info *info) ++{ ++/* struct fb_var_screeninfo *var = &info->var; ++ struct fb_videomode *mode; ++ ++ mode = tmiofb_find_mode(info, var); ++ if (!mode) ++ return -EINVAL; ++ ++ if (info->mode == mode) ++ return 0; ++ ++ info->mode = mode; */ ++ info->fix.line_length = info->mode->xres * 2; ++ ++ tmiofb_hw_mode(to_platform_device(info->device)); ++ tmiofb_clearscreen(info); ++ return 0; ++} ++ ++static int tmiofb_setcolreg(unsigned regno, unsigned red, unsigned green, ++ unsigned blue, unsigned transp, ++ struct fb_info *info) ++{ ++ struct tmiofb_par *par = info->par; ++ ++ if (regno < ARRAY_SIZE(par->pseudo_palette)) { ++ par->pseudo_palette [regno] = ++ ((red & 0xf800)) | ++ ((green & 0xfc00) >> 5) | ++ ((blue & 0xf800) >> 11); ++ return 0; ++ } ++ ++ return 1; ++} ++ ++static struct fb_ops tmiofb_ops = { ++ .owner = THIS_MODULE, ++ ++ .fb_ioctl = tmiofb_ioctl, ++ .fb_check_var = tmiofb_check_var, ++ .fb_set_par = tmiofb_set_par, ++ .fb_setcolreg = tmiofb_setcolreg, ++ .fb_imageblit = cfb_imageblit, ++#ifdef CONFIG_FB_TMIO_ACCELL ++ .fb_sync = tmiofb_sync, ++ .fb_fillrect = tmiofb_fillrect, ++ .fb_copyarea = tmiofb_copyarea, ++#else ++ .fb_fillrect = cfb_fillrect, ++ .fb_copyarea = cfb_copyarea, ++#endif ++}; ++ ++/*--------------------------------------------------------------------------*/ ++ ++/* ++ * reasons for an interrupt: ++ * uis bbisc lcdis ++ * 0100 0001 accelerator command completed ++ * 2000 0001 vsync start ++ * 2000 0002 display start ++ * 2000 0004 line number match(0x1ff mask???) ++ */ ++static irqreturn_t tmiofb_irq(int irq, void *__info) ++{ ++ struct fb_info *info = __info; ++ struct tmiofb_par *par = info->par; ++ struct tmio_lcr __iomem *lcr = par->lcr; ++ unsigned int bbisc = ioread16(&lcr->bbisc); ++ ++ ++ if (unlikely(par->use_polling && irq != -1)) { ++ printk(KERN_INFO "tmiofb: switching to waitq\n"); ++ par->use_polling = false; ++ } ++ ++ iowrite16(bbisc, &lcr->bbisc); ++ ++#ifdef CONFIG_FB_TMIO_ACCELL ++ if (bbisc & 1) ++ wake_up(&par->wait_acc); ++#endif ++ ++ return IRQ_HANDLED; ++} ++ ++static int tmiofb_probe(struct platform_device *dev) ++{ ++ struct mfd_cell *cell = mfd_get_cell(dev); ++ struct tmio_fb_data *data = cell->driver_data; ++ struct resource *ccr = platform_get_resource_byname(dev, IORESOURCE_MEM, TMIO_FB_CONFIG); ++ struct resource *lcr = platform_get_resource_byname(dev, IORESOURCE_MEM, TMIO_FB_CONTROL); ++ struct resource *vram = platform_get_resource_byname(dev, IORESOURCE_MEM, TMIO_FB_VRAM); ++ int irq = platform_get_irq(dev, 0); ++ struct fb_info *info; ++ struct tmiofb_par *par; ++ int retval; ++ ++ if (data == NULL) { ++ dev_err(&dev->dev, "NULL platform data!\n"); ++ return -EINVAL; ++ } ++ ++ info = framebuffer_alloc(sizeof(struct tmiofb_par), &dev->dev); ++ ++ if (!info) { ++ retval = -ENOMEM; ++ goto err_framebuffer_alloc; ++ } ++ ++ par = info->par; ++ platform_set_drvdata(dev, info); ++ ++#ifdef CONFIG_FB_TMIO_ACCELL ++ init_waitqueue_head(&par->wait_acc); ++ ++ par->use_polling = true; ++ ++ info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA ++ | FBINFO_HWACCEL_FILLRECT; ++#else ++ info->flags = FBINFO_DEFAULT; ++#endif ++ ++ info->fbops = &tmiofb_ops; ++ ++ strcpy(info->fix.id, "tmio-fb"); ++ info->fix.smem_start = vram->start; ++ info->fix.smem_len = vram->end - vram->start + 1; ++ info->fix.type = FB_TYPE_PACKED_PIXELS; ++ info->fix.visual = FB_VISUAL_TRUECOLOR; ++ info->fix.mmio_start = lcr->start; ++ info->fix.mmio_len = lcr->end - lcr->start + 1; ++ info->fix.accel = FB_ACCEL_NONE; ++ info->screen_size = info->fix.smem_len - (4 * TMIOFB_FIFO_SIZE); ++ info->pseudo_palette = par->pseudo_palette; ++ ++ par->ccr = ioremap(ccr->start, ccr->end - ccr->start + 1); ++ if (!par->ccr) { ++ retval = -ENOMEM; ++ goto err_ioremap_ccr; ++ } ++ ++ par->lcr = ioremap(info->fix.mmio_start, info->fix.mmio_len); ++ if (!par->lcr) { ++ retval = -ENOMEM; ++ goto err_ioremap_lcr; ++ } ++ ++ par->vram = ioremap(info->fix.smem_start, info->fix.smem_len); ++ if (!par->vram) { ++ retval = -ENOMEM; ++ goto err_ioremap_vram; ++ } ++ info->screen_base = par->vram; ++ ++ retval = request_irq(irq, &tmiofb_irq, IRQF_DISABLED, ++ dev->dev.bus_id, info); ++ ++ if (retval) ++ goto err_request_irq; ++ ++ retval = fb_find_mode(&info->var, info, mode_option, ++ data->modes, data->num_modes, ++ data->modes, 16); ++ if (!retval) { ++ retval = -EINVAL; ++ goto err_find_mode; ++ } ++ ++ retval = cell->enable(dev); ++ if (retval) ++ goto err_enable; ++ ++ retval = tmiofb_hw_init(dev); ++ if (retval) ++ goto err_hw_init; ++ ++/* retval = tmiofb_set_par(info); ++ if (retval) ++ goto err_set_par;*/ ++ ++ retval = register_framebuffer(info); ++ if (retval < 0) ++ goto err_register_framebuffer; ++ ++ printk(KERN_INFO "fb%d: %s frame buffer device\n", ++ info->node, info->fix.id); ++ ++ return 0; ++ ++err_register_framebuffer: ++/*err_set_par:*/ ++ tmiofb_hw_stop(dev); ++err_hw_init: ++ cell->disable(dev); ++err_enable: ++err_find_mode: ++ free_irq(irq, info); ++err_request_irq: ++ iounmap(par->vram); ++err_ioremap_vram: ++ iounmap(par->lcr); ++err_ioremap_lcr: ++ iounmap(par->ccr); ++err_ioremap_ccr: ++ platform_set_drvdata(dev, NULL); ++ framebuffer_release(info); ++err_framebuffer_alloc: ++ return retval; ++} ++ ++static int __devexit tmiofb_remove(struct platform_device *dev) ++{ ++ struct mfd_cell *cell = mfd_get_cell(dev); ++ struct fb_info *info = platform_get_drvdata(dev); ++ int irq = platform_get_irq(dev, 0); ++ struct tmiofb_par *par; ++ ++ if (info) { ++ par = info->par; ++ unregister_framebuffer(info); ++ ++ tmiofb_hw_stop(dev); ++ ++ cell->disable(dev); ++ ++ free_irq(irq, info); ++ ++ iounmap(par->vram); ++ iounmap(par->lcr); ++ iounmap(par->ccr); ++ ++ framebuffer_release(info); ++ platform_set_drvdata(dev, NULL); ++ } ++ ++ return 0; ++} ++ ++#if 0 ++static void tmiofb_dump_regs(struct platform_device *dev) ++{ ++ struct fb_info *info = platform_get_drvdata(dev); ++ struct tmiofb_par *par = info->par; ++ struct tmio_lhccr __iomem *ccr = par->ccr; ++ struct tmio_lcr __iomem *lcr = par->lcr; ++ ++ printk("lhccr:\n"); ++#define CCR_PR(n) printk("\t" #n " = \t%04x\n", ioread16(&ccr->n)); ++ CCR_PR(cmd); ++ CCR_PR(revid); ++ CCR_PR(basel); ++ CCR_PR(baseh); ++ CCR_PR(ugcc); ++ CCR_PR(gcc); ++ CCR_PR(usc); ++ CCR_PR(vramrtc); ++ CCR_PR(vramsac); ++ CCR_PR(vrambc); ++#undef CCR_PR ++ ++ printk("lcr: \n"); ++#define LCR_PR(n) printk("\t" #n " = \t%04x\n", ioread16(&lcr->n)); ++ LCR_PR(uis); ++ LCR_PR(vhpn); ++ LCR_PR(cfsal); ++ LCR_PR(cfsah); ++ LCR_PR(cfs); ++ LCR_PR(cfws); ++ LCR_PR(bbie); ++ LCR_PR(bbisc); ++ LCR_PR(ccs); ++ LCR_PR(bbes); ++ LCR_PR(cmdl); ++ LCR_PR(cmdh); ++ LCR_PR(cfc); ++ LCR_PR(ccifc); ++ LCR_PR(hwt); ++ LCR_PR(lcdccrc); ++ LCR_PR(lcdcc); ++ LCR_PR(lcdcopc); ++ LCR_PR(lcdis); ++ LCR_PR(lcdim); ++ LCR_PR(lcdie); ++ LCR_PR(gdsal); ++ LCR_PR(gdsah); ++ LCR_PR(vhpcl); ++ LCR_PR(vhpch); ++ LCR_PR(gm); ++ LCR_PR(ht); ++ LCR_PR(hds); ++ LCR_PR(hss); ++ LCR_PR(hse); ++ LCR_PR(hnp); ++ LCR_PR(vt); ++ LCR_PR(vds); ++ LCR_PR(vss); ++ LCR_PR(vse); ++ LCR_PR(cdln); ++ LCR_PR(iln); ++ LCR_PR(sp); ++ LCR_PR(misc); ++ LCR_PR(vihss); ++ LCR_PR(vivs); ++ LCR_PR(vive); ++ LCR_PR(vivss); ++ LCR_PR(vccis); ++ LCR_PR(vidwsal); ++ LCR_PR(vidwsah); ++ LCR_PR(vidrsal); ++ LCR_PR(vidrsah); ++ LCR_PR(vipddst); ++ LCR_PR(vipddet); ++ LCR_PR(vie); ++ LCR_PR(vcs); ++ LCR_PR(vphwc); ++ LCR_PR(vphs); ++ LCR_PR(vpvwc); ++ LCR_PR(vpvs); ++ LCR_PR(plhpix); ++ LCR_PR(xs); ++ LCR_PR(xckhw); ++ LCR_PR(sths); ++ LCR_PR(vt2); ++ LCR_PR(ycksw); ++ LCR_PR(ysts); ++ LCR_PR(ppols); ++ LCR_PR(precw); ++ LCR_PR(vclkhw); ++ LCR_PR(oc); ++#undef LCR_PR ++} ++#endif ++ ++#ifdef CONFIG_PM ++static int tmiofb_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ struct fb_info *info = platform_get_drvdata(dev); ++ struct tmiofb_par *par = info->par; ++ struct mfd_cell *cell = mfd_get_cell(dev); ++ int retval = 0; ++ ++ acquire_console_sem(); ++ ++ fb_set_suspend(info, 1); ++ ++ if (info->fbops->fb_sync) ++ info->fbops->fb_sync(info); ++ ++ ++ printk(KERN_INFO "tmiofb: switching to polling\n"); ++ par->use_polling = true; ++ tmiofb_hw_stop(dev); ++ ++ if (cell->suspend) ++ retval = cell->suspend(dev); ++ ++ release_console_sem(); ++ ++ return retval; ++} ++ ++static int tmiofb_resume(struct platform_device *dev) ++{ ++ struct fb_info *info = platform_get_drvdata(dev); ++ struct mfd_cell *cell = mfd_get_cell(dev); ++ int retval; ++ ++ acquire_console_sem(); ++ ++ if (cell->resume) { ++ retval = cell->resume(dev); ++ if (retval) ++ return retval; ++ } ++ ++ tmiofb_irq(-1, info); ++ ++ tmiofb_hw_init(dev); ++ ++ tmiofb_hw_mode(dev); ++ ++ fb_set_suspend(info, 0); ++ release_console_sem(); ++ return 0; ++} ++#endif ++ ++static struct platform_driver tmiofb_driver = { ++ .driver.name = "tmio-fb", ++ .driver.owner = THIS_MODULE, ++ .probe = tmiofb_probe, ++ .remove = __devexit_p(tmiofb_remove), ++#ifdef CONFIG_PM ++ .suspend = tmiofb_suspend, ++ .resume = tmiofb_resume, ++#endif ++}; ++ ++/*--------------------------------------------------------------------------*/ ++ ++#ifndef MODULE ++static void __init tmiofb_setup(char *options) ++{ ++ char *this_opt; ++ ++ if (!options || !*options) ++ return; ++ ++ while ((this_opt = strsep(&options, ",")) != NULL) { ++ if (!*this_opt) continue; ++ /* ++ * FIXME ++ */ ++ } ++} ++#endif ++ ++static int __init tmiofb_init(void) ++{ ++#ifndef MODULE ++ char *option = NULL; ++ ++ if (fb_get_options("tmiofb", &option)) ++ return -ENODEV; ++ tmiofb_setup(option); ++#endif ++ return platform_driver_register(&tmiofb_driver); ++} ++ ++static void __exit tmiofb_cleanup(void) ++{ ++ platform_driver_unregister(&tmiofb_driver); ++} ++ ++module_init(tmiofb_init); ++module_exit(tmiofb_cleanup); ++ ++MODULE_DESCRIPTION("TMIO framebuffer driver"); ++MODULE_AUTHOR("Chris Humbert, Dirk Opfer, Dmitry Baryshkov"); ++MODULE_LICENSE("GPL"); +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0010-OHCI-driver-for-TMIO-devices.patch b/packages/linux/linux-rp-2.6.24/tosa/0010-OHCI-driver-for-TMIO-devices.patch new file mode 100644 index 0000000000..f358c069d0 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0010-OHCI-driver-for-TMIO-devices.patch @@ -0,0 +1,431 @@ +From e5f06830bc8d3ef4792c9c0569825d0347b39852 Mon Sep 17 00:00:00 2001 +From: Ian Molton <spyro@f2s.com> +Date: Fri, 4 Jan 2008 18:43:31 +0000 +Subject: [PATCH 10/64] OHCI driver for TMIO devices + +--- + drivers/usb/Kconfig | 1 + + drivers/usb/host/Kconfig | 1 + + drivers/usb/host/ohci-hcd.c | 5 + + drivers/usb/host/ohci-tmio.c | 369 ++++++++++++++++++++++++++++++++++++++++++ + 4 files changed, 376 insertions(+), 0 deletions(-) + create mode 100644 drivers/usb/host/ohci-tmio.c + +diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig +index 7580aa5..8912042 100644 +--- a/drivers/usb/Kconfig ++++ b/drivers/usb/Kconfig +@@ -36,6 +36,7 @@ config USB_ARCH_HAS_OHCI + default y if ARCH_EP93XX + default y if ARCH_AT91 + default y if ARCH_PNX4008 ++ default y if MFD_TC6393XB + # PPC: + default y if STB03xxx + default y if PPC_MPC52xx +diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig +index 49a91c5..5ae3589 100644 +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -101,6 +101,7 @@ config USB_OHCI_HCD + depends on USB && USB_ARCH_HAS_OHCI + select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3 + select I2C if ARCH_PNX4008 ++ select DMABOUNCE if MFD_TC6393XB + ---help--- + The Open Host Controller Interface (OHCI) is a standard for accessing + USB 1.1 host controller hardware. It does more in hardware than Intel's +diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c +index ecfe800..77abf3e 100644 +--- a/drivers/usb/host/ohci-hcd.c ++++ b/drivers/usb/host/ohci-hcd.c +@@ -1043,6 +1043,11 @@ MODULE_LICENSE ("GPL"); + #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver + #endif + ++#ifdef CONFIG_MFD_TC6393XB ++#include "ohci-tmio.c" ++#define PLATFORM_DRIVER ohci_hcd_tmio_driver ++#endif ++ + #ifdef CONFIG_USB_OHCI_HCD_SSB + #include "ohci-ssb.c" + #define SSB_OHCI_DRIVER ssb_ohci_driver +diff --git a/drivers/usb/host/ohci-tmio.c b/drivers/usb/host/ohci-tmio.c +new file mode 100644 +index 0000000..be609f3 +--- /dev/null ++++ b/drivers/usb/host/ohci-tmio.c +@@ -0,0 +1,369 @@ ++/* ++ * OHCI HCD(Host Controller Driver) for USB. ++ * ++ *(C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> ++ *(C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net> ++ *(C) Copyright 2002 Hewlett-Packard Company ++ * ++ * Bus glue for Toshiba Mobile IO(TMIO) Controller's OHCI core ++ *(C) Copyright 2005 Chris Humbert <mahadri-usb@drigon.com> ++ * ++ * This is known to work with the following variants: ++ * TC6393XB revision 3 (32kB SRAM) ++ * ++ * The TMIO's OHCI core DMAs through a small internal buffer that ++ * is directly addressable by the CPU. dma_declare_coherent_memory ++ * and DMA bounce buffers allow the higher-level OHCI host driver to ++ * work. However, the dma API doesn't handle dma mapping failures ++ * well(dma_sg_map() is a prime example), so it is unusable. ++ * ++ * This HC pretends be a PIO-ish controller and uses the kernel's ++ * generic allocator for the entire SRAM. Using the USB core's ++ * usb_operations, we provide hcd_buffer_alloc/free. Using the OHCI's ++ * ohci_ops, we provide memory management for OHCI's TDs and EDs. We ++ * internally queue a URB's TDs until enough dma memory is available ++ * to enqueue them with the HC. ++ * ++ * Written from sparse documentation from Toshiba and Sharp's driver ++ * for the 2.4 kernel, ++ * usb-ohci-tc6393.c(C) Copyright 2004 Lineo Solutions, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++/*#include <linux/fs.h> ++#include <linux/mount.h> ++#include <linux/pagemap.h> ++#include <linux/init.h> ++#include <linux/namei.h> ++#include <linux/sched.h>*/ ++#include <linux/platform_device.h> ++#include <linux/mfd-core.h> ++#include <linux/mfd/tmio.h> ++#include <linux/dma-mapping.h> ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* ++ * USB Host Controller Configuration Register ++ */ ++struct tmio_uhccr { ++ u8 x00[8]; ++ u8 revid; /* 0x08 Revision ID */ ++ u8 x01[7]; ++ u16 basel; /* 0x10 USB Control Register Base Address Low */ ++ u16 baseh; /* 0x12 USB Control Register Base Address High */ ++ u8 x02[0x2c]; ++ u8 ilme; /* 0x40 Internal Local Memory Enable */ ++ u8 x03[0x0b]; ++ u16 pm; /* 0x4c Power Management */ ++ u8 x04[2]; ++ u8 intc; /* 0x50 INT Control */ ++ u8 x05[3]; ++ u16 lmw1l; /* 0x54 Local Memory Window 1 LMADRS Low */ ++ u16 lmw1h; /* 0x56 Local Memory Window 1 LMADRS High */ ++ u16 lmw1bl; /* 0x58 Local Memory Window 1 Base Address Low */ ++ u16 lmw1bh; /* 0x5A Local Memory Window 1 Base Address High */ ++ u16 lmw2l; /* 0x5C Local Memory Window 2 LMADRS Low */ ++ u16 lmw2h; /* 0x5E Local Memory Window 2 LMADRS High */ ++ u16 lmw2bl; /* 0x60 Local Memory Window 2 Base Address Low */ ++ u16 lmw2bh; /* 0x62 Local Memory Window 2 Base Address High */ ++ u8 x06[0x98]; ++ u8 misc; /* 0xFC MISC */ ++ u8 x07[3]; ++} __attribute__((packed)); ++ ++#define UHCCR_PM_GKEN 0x0001 ++#define UHCCR_PM_CKRNEN 0x0002 ++#define UHCCR_PM_USBPW1 0x0004 ++#define UHCCR_PM_USBPW2 0x0008 ++#define UHCCR_PM_PMEE 0x0100 ++#define UHCCR_PM_PMES 0x8000 ++ ++/*-------------------------------------------------------------------------*/ ++ ++struct tmio_hcd { ++ struct tmio_uhccr __iomem *ccr; ++}; ++ ++#define hcd_to_tmio(hcd) ((struct tmio_hcd *)(hcd_to_ohci(hcd) + 1)) ++#define ohci_to_tmio(ohci) ((struct tmio_hcd *)(ohci + 1)) ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void tmio_stop_hc(struct platform_device *dev) ++{ ++ struct mfd_cell *cell = mfd_get_cell(dev); ++ struct usb_hcd *hcd = platform_get_drvdata(dev); ++ struct tmio_hcd *tmio = hcd_to_tmio(hcd); ++ struct tmio_uhccr __iomem *ccr = tmio->ccr; ++ u16 pm; ++ ++ pm = UHCCR_PM_GKEN | UHCCR_PM_CKRNEN | UHCCR_PM_USBPW1 | UHCCR_PM_USBPW2; ++ iowrite8(0, &ccr->intc); ++ iowrite8(0, &ccr->ilme); ++ iowrite16(0, &ccr->basel); ++ iowrite16(0, &ccr->baseh); ++ iowrite16(pm, &ccr->pm); ++ ++ cell->disable(dev); ++} ++ ++static void tmio_start_hc(struct platform_device *dev) ++{ ++ struct mfd_cell *cell = mfd_get_cell(dev); ++ struct usb_hcd *hcd = platform_get_drvdata(dev); ++ struct tmio_hcd *tmio = hcd_to_tmio(hcd); ++ struct tmio_uhccr __iomem *ccr = tmio->ccr; ++ u16 pm; ++ unsigned long base = hcd->rsrc_start; ++ ++ pm = UHCCR_PM_CKRNEN | UHCCR_PM_GKEN | UHCCR_PM_PMEE | UHCCR_PM_PMES; ++ cell->enable(dev); ++ ++ iowrite16(pm, &ccr->pm); ++ iowrite16(base, &ccr->basel); ++ iowrite16(base >> 16, &ccr->baseh); ++ iowrite8(1, &ccr->ilme); ++ iowrite8(2, &ccr->intc); ++ ++ dev_info(&dev->dev, "revision %d @ 0x%08llx, irq %d\n", ++ ioread8(&ccr->revid), hcd->rsrc_start, hcd->irq); ++} ++ ++static int usb_hcd_tmio_probe(const struct hc_driver *driver, ++ struct platform_device *dev) ++{ ++ struct resource *config = platform_get_resource_byname(dev, IORESOURCE_MEM, TMIO_OHCI_CONFIG); ++ struct resource *regs = platform_get_resource_byname(dev, IORESOURCE_MEM, TMIO_OHCI_CONTROL); ++ struct resource *sram = platform_get_resource_byname(dev, IORESOURCE_MEM, TMIO_OHCI_SRAM); ++ int irq = platform_get_irq(dev, 0); ++ struct tmio_hcd *tmio; ++ struct ohci_hcd *ohci; ++ struct usb_hcd *hcd; ++ int retval; ++ ++ if (usb_disabled()) ++ return -ENODEV; ++ ++ hcd = usb_create_hcd(driver, &dev->dev, dev->dev.bus_id); ++ if (!hcd) { ++ retval = -ENOMEM; ++ goto err_usb_create_hcd; ++ } ++ ++ hcd->rsrc_start = regs->start; ++ hcd->rsrc_len = regs->end - regs->start + 1; ++ ++ tmio = hcd_to_tmio(hcd); ++ ++ tmio->ccr = ioremap(config->start, config->end - config->start + 1); ++ if (!tmio->ccr) { ++ retval = -ENOMEM; ++ goto err_ioremap_ccr; ++ } ++ ++ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); ++ if (!hcd->regs) { ++ retval = -ENOMEM; ++ goto err_ioremap_regs; ++ } ++ ++ if (dma_declare_coherent_memory(&dev->dev, sram->start, ++ sram->start, ++ sram->end - sram->start + 1, ++ DMA_MEMORY_MAP) != DMA_MEMORY_MAP) { ++ retval = -EBUSY; ++ goto err_dma_declare; ++ } ++ ++ retval = dmabounce_register_dev(&dev->dev, 512, 4096); ++ if (retval) ++ goto err_dmabounce_register_dev; ++ ++ tmio_start_hc(dev); ++ ohci = hcd_to_ohci(hcd); ++ ohci_hcd_init(ohci); ++ ++ retval = usb_add_hcd(hcd, irq, IRQF_DISABLED); ++ ++ if (retval == 0) ++ return retval; ++ ++ tmio_stop_hc(dev); ++ ++ dmabounce_unregister_dev(&dev->dev); ++err_dmabounce_register_dev: ++ dma_release_declared_memory(&dev->dev); ++err_dma_declare: ++ iounmap(hcd->regs); ++err_ioremap_regs: ++ iounmap(tmio->ccr); ++err_ioremap_ccr: ++ usb_put_hcd(hcd); ++err_usb_create_hcd: ++ ++ return retval; ++} ++ ++static void usb_hcd_tmio_remove(struct usb_hcd *hcd, struct platform_device *dev) ++{ ++ struct tmio_hcd *tmio = hcd_to_tmio(hcd); ++ ++ usb_remove_hcd(hcd); ++ tmio_stop_hc(dev); ++ dmabounce_unregister_dev(&dev->dev); ++ dma_release_declared_memory(&dev->dev); ++ iounmap(hcd->regs); ++ iounmap(tmio->ccr); ++ usb_put_hcd(hcd); ++} ++ ++static int __devinit ++ohci_tmio_start(struct usb_hcd *hcd) ++{ ++ struct ohci_hcd *ohci = hcd_to_ohci(hcd); ++ int retval; ++ ++ if ((retval = ohci_init(ohci)) < 0) ++ return retval; ++ ++ if ((retval = ohci_run(ohci)) < 0) { ++ err("can't start %s", hcd->self.bus_name); ++ ohci_stop(hcd); ++ return retval; ++ } ++ ++ return 0; ++} ++ ++static const struct hc_driver ohci_tmio_hc_driver = { ++ .description = hcd_name, ++ .product_desc = "TMIO OHCI USB Host Controller", ++ .hcd_priv_size = sizeof(struct ohci_hcd) + sizeof (struct tmio_hcd), ++ ++ /* generic hardware linkage */ ++ .irq = ohci_irq, ++ .flags = HCD_USB11 | HCD_MEMORY, ++ ++ /* basic lifecycle operations */ ++ .start = ohci_tmio_start, ++ .stop = ohci_stop, ++ .shutdown = ohci_shutdown, ++ ++ /* managing i/o requests and associated device resources */ ++ .urb_enqueue = ohci_urb_enqueue, ++ .urb_dequeue = ohci_urb_dequeue, ++ .endpoint_disable = ohci_endpoint_disable, ++ ++ /* scheduling support */ ++ .get_frame_number = ohci_get_frame, ++ ++ /* root hub support */ ++ .hub_status_data = ohci_hub_status_data, ++ .hub_control = ohci_hub_control, ++ .hub_irq_enable = ohci_rhsc_enable, ++#ifdef CONFIG_PM ++ .bus_suspend = ohci_bus_suspend, ++ .bus_resume = ohci_bus_resume, ++#endif ++ .start_port_reset = ohci_start_port_reset, ++}; ++ ++/*-------------------------------------------------------------------------*/ ++static struct platform_driver ohci_hcd_tmio_driver; ++ ++static int ++tmio_dmabounce_check(struct device *dev, dma_addr_t dma, size_t size, void *data) ++{ ++ struct resource *sram = data; ++#ifdef DEBUG ++ printk(KERN_ERR "tmio_dmabounce_check: %08x %d\n", dma, size); ++#endif ++ ++ if (dev->driver != &ohci_hcd_tmio_driver.driver) ++ return 0; ++ ++ if (sram->start <= dma && dma + size <= sram->end) ++ return 0; ++ ++ return 1; ++} ++ ++static u64 dma_mask = DMA_32BIT_MASK; ++ ++static int ohci_hcd_tmio_drv_probe(struct platform_device *dev) ++{ ++ struct resource *sram = platform_get_resource_byname(dev, IORESOURCE_MEM, TMIO_OHCI_SRAM); ++ ++ dev->dev.dma_mask = &dma_mask; ++ dev->dev.coherent_dma_mask = DMA_32BIT_MASK; ++ ++ dmabounce_register_checker(tmio_dmabounce_check, sram); ++ ++ return usb_hcd_tmio_probe(&ohci_tmio_hc_driver, dev); ++} ++ ++static int ohci_hcd_tmio_drv_remove(struct platform_device *dev) ++{ ++ struct usb_hcd *hcd = platform_get_drvdata(dev); ++ struct resource *sram = platform_get_resource_byname(dev, IORESOURCE_MEM, TMIO_OHCI_SRAM); ++ ++ usb_hcd_tmio_remove(hcd, dev); ++ ++ platform_set_drvdata(dev, NULL); ++ ++ dmabounce_remove_checker(tmio_dmabounce_check, sram); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int ohci_hcd_tmio_drv_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ struct usb_hcd *hcd = platform_get_drvdata(dev); ++ struct ohci_hcd *ohci = hcd_to_ohci(hcd); ++ ++ if (time_before(jiffies, ohci->next_statechange)) ++ msleep(5); ++ ohci->next_statechange = jiffies; ++ ++ tmio_stop_hc(dev); ++ hcd->state = HC_STATE_SUSPENDED; ++ dev->dev.power.power_state = PMSG_SUSPEND; ++ ++ return 0; ++} ++ ++static int ohci_hcd_tmio_drv_resume(struct platform_device *dev) ++{ ++ struct usb_hcd *hcd = platform_get_drvdata(dev); ++ struct ohci_hcd *ohci = hcd_to_ohci(hcd); ++ ++ if (time_before(jiffies, ohci->next_statechange)) ++ msleep(5); ++ ohci->next_statechange = jiffies; ++ ++ tmio_start_hc(dev); ++ ++ dev->dev.power.power_state = PMSG_ON; ++ usb_hcd_resume_root_hub(hcd); ++ ++ return 0; ++} ++#endif ++ ++static struct platform_driver ohci_hcd_tmio_driver = { ++ .probe = ohci_hcd_tmio_drv_probe, ++ .remove = ohci_hcd_tmio_drv_remove, ++ .shutdown = usb_hcd_platform_shutdown, ++#ifdef CONFIG_PM ++ .suspend = ohci_hcd_tmio_drv_suspend, ++ .resume = ohci_hcd_tmio_drv_resume, ++#endif ++ .driver = { ++ .name = "tmio-ohci", ++ }, ++}; +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0011-MMC-driver-for-TMIO-devices.patch b/packages/linux/linux-rp-2.6.24/tosa/0011-MMC-driver-for-TMIO-devices.patch new file mode 100644 index 0000000000..6ff752d1ff --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0011-MMC-driver-for-TMIO-devices.patch @@ -0,0 +1,891 @@ +From b358a64c1fdd1eb80da57f919c893d910db95e37 Mon Sep 17 00:00:00 2001 +From: Ian Molton <spyro@f2s.com> +Date: Sat, 29 Dec 2007 15:26:19 +0000 +Subject: [PATCH 11/64] MMC driver for TMIO devices + +--- + drivers/mmc/host/Kconfig | 6 + + drivers/mmc/host/Makefile | 1 + + drivers/mmc/host/tmio_mmc.c | 633 +++++++++++++++++++++++++++++++++++++++++++ + drivers/mmc/host/tmio_mmc.h | 205 ++++++++++++++ + 4 files changed, 845 insertions(+), 0 deletions(-) + create mode 100644 drivers/mmc/host/tmio_mmc.c + create mode 100644 drivers/mmc/host/tmio_mmc.h + +diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig +index 5fef678..f8f9b7e 100644 +--- a/drivers/mmc/host/Kconfig ++++ b/drivers/mmc/host/Kconfig +@@ -130,3 +130,9 @@ config MMC_SPI + + If unsure, or if your system has no SPI master driver, say N. + ++config MMC_TMIO ++ tristate "Toshiba Mobile IO Controller (TMIO) MMC/SD function support" ++ depends on MMC ++ help ++ This provides support for the SD/MMC cell found in TC6393XB, ++ T7L66XB and also ipaq ASIC3 +diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile +index 3877c87..7ac956b 100644 +--- a/drivers/mmc/host/Makefile ++++ b/drivers/mmc/host/Makefile +@@ -17,4 +17,5 @@ obj-$(CONFIG_MMC_OMAP) += omap.o + obj-$(CONFIG_MMC_AT91) += at91_mci.o + obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o + obj-$(CONFIG_MMC_SPI) += mmc_spi.o ++obj-$(CONFIG_MMC_TMIO) += tmio_mmc.o + +diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c +new file mode 100644 +index 0000000..735c386 +--- /dev/null ++++ b/drivers/mmc/host/tmio_mmc.c +@@ -0,0 +1,633 @@ ++/* ++ * linux/drivers/mmc/tmio_mmc.c ++ * ++ * Copyright (C) 2004 Ian Molton ++ * Copyright (C) 2007 Ian Molton ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * Driver for the MMC / SD / SDIO cell found in: ++ * ++ * TC6393XB TC6391XB TC6387XB T7L66XB ++ * ++ * This driver draws mainly on scattered spec sheets, Reverse engineering ++ * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit ++ * support). (Further 4 bit support from a later datasheet). ++ * ++ * TODO: ++ * Investigate using a workqueue for PIO transfers ++ * Eliminate FIXMEs ++ * SDIO support ++ * Better Power management ++ * Handle MMC errors better ++ * double buffer support ++ * ++ */ ++#include <linux/module.h> ++#include <linux/irq.h> ++#include <linux/device.h> ++#include <linux/delay.h> ++#include <linux/mmc/mmc.h> ++#include <linux/mmc/host.h> ++#include <linux/mfd-core.h> ++#include <linux/mfd/tmio.h> ++ ++#include "tmio_mmc.h" ++ ++/* ++ * Fixme - documentation conflicts on what the clock values are for the ++ * various dividers. ++ * One document I have says that its a divisor of a 24MHz clock, another 33. ++ * This probably depends on HCLK for a given platform, so we may need to ++ * require HCLK be passed to us from the MFD core. ++ * ++ */ ++ ++static void tmio_mmc_set_clock (struct tmio_mmc_host *host, int new_clock) { ++ struct tmio_mmc_cnf __iomem *cnf = host->cnf; ++ struct tmio_mmc_ctl __iomem *ctl = host->ctl; ++ u32 clk = 0, clock; ++ ++ if (new_clock) { ++ for(clock = 46875, clk = 0x100; new_clock >= (clock<<1); ){ ++ clock <<= 1; ++ clk >>= 1; ++ } ++ if(clk & 0x1) ++ clk = 0x20000; ++ ++ clk >>= 2; ++ if(clk & 0x8000) /* For full speed we disable the divider. */ ++ writeb(0, &cnf->sd_clk_mode); ++ else ++ writeb(1, &cnf->sd_clk_mode); ++ clk |= 0x100; ++ } ++ ++ writew(clk, &ctl->sd_card_clk_ctl); ++} ++ ++static void tmio_mmc_clk_stop (struct tmio_mmc_host *host) { ++ struct tmio_mmc_ctl __iomem *ctl = host->ctl; ++ ++ writew(0x0000, &ctl->clk_and_wait_ctl); ++ msleep(10); ++ writew(readw(&ctl->sd_card_clk_ctl) & ~0x0100, &ctl->sd_card_clk_ctl); ++ msleep(10); ++} ++ ++static void tmio_mmc_clk_start (struct tmio_mmc_host *host) { ++ struct tmio_mmc_ctl __iomem *ctl = host->ctl; ++ ++ writew(readw(&ctl->sd_card_clk_ctl) | 0x0100, &ctl->sd_card_clk_ctl); ++ msleep(10); ++ writew(0x0100, &ctl->clk_and_wait_ctl); ++ msleep(10); ++} ++ ++static void reset(struct tmio_mmc_host *host) { ++ struct tmio_mmc_ctl __iomem *ctl = host->ctl; ++ ++ /* FIXME - should we set stop clock reg here */ ++ writew(0x0000, &ctl->reset_sd); ++ writew(0x0000, &ctl->reset_sdio); ++ msleep(10); ++ writew(0x0001, &ctl->reset_sd); ++ writew(0x0001, &ctl->reset_sdio); ++ msleep(10); ++} ++ ++static void ++tmio_mmc_finish_request(struct tmio_mmc_host *host) ++{ ++ struct mmc_request *mrq = host->mrq; ++ ++ host->mrq = NULL; ++ host->cmd = NULL; ++ host->data = NULL; ++ ++ mmc_request_done(host->mmc, mrq); ++} ++ ++/* These are the bitmasks the tmio chip requires to implement the MMC response ++ * types. Note that R1 and R6 are the same in this scheme. */ ++#define APP_CMD 0x0040 ++#define RESP_NONE 0x0300 ++#define RESP_R1 0x0400 ++#define RESP_R1B 0x0500 ++#define RESP_R2 0x0600 ++#define RESP_R3 0x0700 ++#define DATA_PRESENT 0x0800 ++#define TRANSFER_READ 0x1000 ++#define TRANSFER_MULTI 0x2000 ++#define SECURITY_CMD 0x4000 ++ ++static void ++tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd) ++{ ++ struct tmio_mmc_ctl __iomem *ctl = host->ctl; ++ struct mmc_data *data = host->data; ++ int c = cmd->opcode; ++ ++ if(cmd->opcode == MMC_STOP_TRANSMISSION) { ++ writew(0x001, &ctl->stop_internal_action); ++ return; ++ } ++ ++ switch(mmc_resp_type(cmd)) { ++ case MMC_RSP_NONE: c |= RESP_NONE; break; ++ case MMC_RSP_R1: c |= RESP_R1; break; ++ case MMC_RSP_R1B: c |= RESP_R1B; break; ++ case MMC_RSP_R2: c |= RESP_R2; break; ++ case MMC_RSP_R3: c |= RESP_R3; break; ++ default: ++ DBG("Unknown response type %d\n", mmc_resp_type(cmd)); ++ } ++ ++ host->cmd = cmd; ++ ++/* FIXME - this seems to be ok comented out but the spec suggest this bit should ++ * be set when issuing app commands. ++ * if(cmd->flags & MMC_FLAG_ACMD) ++ * c |= APP_CMD; ++ */ ++ if(data) { ++ c |= DATA_PRESENT; ++ if(data->blocks > 1) { ++ writew(0x100, &ctl->stop_internal_action); ++ c |= TRANSFER_MULTI; ++ } ++ if(data->flags & MMC_DATA_READ) ++ c |= TRANSFER_READ; ++ } ++ ++ enable_mmc_irqs(ctl, TMIO_MASK_CMD); ++ ++ /* Fire off the command */ ++ tmio_iowrite32(cmd->arg, ctl->arg_reg); ++ writew(c, &ctl->sd_cmd); ++} ++ ++/* This chip always returns (at least?) as much data as you ask for. ++ * Im unsure what happens if you ask for less than a block. This should be ++ * looked into to ensure that a funny length read doesnt hose the controller. ++ * ++ * FIXME - this chip cannot do 1 and 2 byte data requests in 4 bit mode ++ */ ++static inline void tmio_mmc_pio_irq(struct tmio_mmc_host *host) { ++ struct tmio_mmc_ctl __iomem *ctl = host->ctl; ++ struct mmc_data *data = host->data; ++ unsigned short *buf; ++ unsigned int count; ++ unsigned long flags; ++ ++ if(!data){ ++ DBG("Spurious PIO IRQ\n"); ++ return; ++ } ++ ++ buf = (unsigned short *)(tmio_mmc_kmap_atomic(host, &flags) + ++ host->sg_off); ++ ++ /* Ensure we dont read more than one block. The chip will interrupt us ++ * When the next block is available. ++ * FIXME - this is probably not true now IRQ handling is fixed ++ */ ++ count = host->sg_ptr->length - host->sg_off; ++ if(count > data->blksz) ++ count = data->blksz; ++ ++ DBG("count: %08x offset: %08x flags %08x\n", ++ count, host->sg_off, data->flags); ++ ++ /* Transfer the data */ ++ if(data->flags & MMC_DATA_READ) ++ readsw(&ctl->sd_data_port[0], buf, count >> 1); ++ else ++ writesw(&ctl->sd_data_port[0], buf, count >> 1); ++ ++ host->sg_off += count; ++ ++ tmio_mmc_kunmap_atomic(host, &flags); ++ ++ if(host->sg_off == host->sg_ptr->length) ++ tmio_mmc_next_sg(host); ++ ++ return; ++} ++ ++static inline void tmio_mmc_data_irq(struct tmio_mmc_host *host) { ++ struct tmio_mmc_ctl __iomem *ctl = host->ctl; ++ struct mmc_data *data = host->data; ++ ++ host->data = NULL; ++ ++ if(!data){ ++ DBG("Spurious data end IRQ\n"); ++ return; ++ } ++ ++ /* FIXME - return correct transfer count on errors */ ++ if (!data->error) ++ data->bytes_xfered = data->blocks * data->blksz; ++ else ++ data->bytes_xfered = 0; ++ ++ DBG("Completed data request\n"); ++ ++ /*FIXME - other drivers allow an optional stop command of any given type ++ * which we dont do, as the chip can auto generate them. ++ * Perhaps we can be smarter about when to use auto CMD12 and ++ * only issue the auto request when we know this is the desired ++ * stop command, allowing fallback to the stop command the ++ * upper layers expect. For now, we do what works. ++ */ ++ ++ writew(0x000, &ctl->stop_internal_action); ++ ++ if(data->flags & MMC_DATA_READ) ++ disable_mmc_irqs(ctl, TMIO_MASK_READOP); ++ else ++ disable_mmc_irqs(ctl, TMIO_MASK_WRITEOP); ++ ++ tmio_mmc_finish_request(host); ++} ++ ++static inline void tmio_mmc_cmd_irq(struct tmio_mmc_host *host, unsigned int stat) { ++ struct tmio_mmc_ctl __iomem *ctl = host->ctl; ++ struct mmc_command *cmd = host->cmd; ++ ++ if(!host->cmd) { ++ DBG("Spurious CMD irq\n"); ++ return; ++ } ++ ++ host->cmd = NULL; ++ ++ /* This controller is sicker than the PXA one. not only do we need to ++ * drop the top 8 bits of the first response word, we also need to ++ * modify the order of the response for short response command types. ++ */ ++ ++ /* FIXME - this works but readl is wrong and will break on asic3... */ ++ cmd->resp[3] = tmio_ioread32(&ctl->response[0]); ++ cmd->resp[2] = tmio_ioread32(&ctl->response[2]); ++ cmd->resp[1] = tmio_ioread32(&ctl->response[4]); ++ cmd->resp[0] = tmio_ioread32(&ctl->response[6]); ++ ++ if(cmd->flags & MMC_RSP_136) { ++ cmd->resp[0] = (cmd->resp[0] <<8) | (cmd->resp[1] >>24); ++ cmd->resp[1] = (cmd->resp[1] <<8) | (cmd->resp[2] >>24); ++ cmd->resp[2] = (cmd->resp[2] <<8) | (cmd->resp[3] >>24); ++ cmd->resp[3] <<= 8; ++ } ++ else if(cmd->flags & MMC_RSP_R3) { ++ cmd->resp[0] = cmd->resp[3]; ++ } ++ ++ if (stat & TMIO_STAT_CMDTIMEOUT) ++ cmd->error = -ETIMEDOUT; ++ else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC) ++ cmd->error = -EILSEQ; ++ ++ /* If there is data to handle we enable data IRQs here, and ++ * we will ultimatley finish the request in the data_end handler. ++ * If theres no data or we encountered an error, finish now. ++ */ ++ if(host->data && !cmd->error){ ++ if(host->data->flags & MMC_DATA_READ) ++ enable_mmc_irqs(ctl, TMIO_MASK_READOP); ++ else ++ enable_mmc_irqs(ctl, TMIO_MASK_WRITEOP); ++ } ++ else { ++ tmio_mmc_finish_request(host); ++ } ++ ++ return; ++} ++ ++ ++static irqreturn_t tmio_mmc_irq(int irq, void *devid) ++{ ++ struct tmio_mmc_host *host = devid; ++ struct tmio_mmc_ctl __iomem *ctl = host->ctl; ++ unsigned int ireg, irq_mask, status; ++ ++ DBG("MMC IRQ begin\n"); ++ ++ status = tmio_ioread32(ctl->status); ++ irq_mask = tmio_ioread32(ctl->irq_mask); ++ ireg = status & TMIO_MASK_IRQ & ~irq_mask; ++ ++#ifdef CONFIG_MMC_DEBUG ++ debug_status(status); ++ debug_status(ireg); ++#endif ++ if (!ireg) { ++ disable_mmc_irqs(ctl, status & ~irq_mask); ++#ifdef CONFIG_MMC_DEBUG ++ WARN("tmio_mmc: Spurious MMC irq, disabling! 0x%08x 0x%08x 0x%08x\n", status, irq_mask, ireg); ++ debug_status(status); ++#endif ++ goto out; ++ } ++ ++ while (ireg) { ++ /* Card insert / remove attempts */ ++ if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)){ ++ ack_mmc_irqs(ctl, TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE); ++ mmc_detect_change(host->mmc,0); ++ } ++ ++ /* CRC and other errors */ ++/* if (ireg & TMIO_STAT_ERR_IRQ) ++ * handled |= tmio_error_irq(host, irq, stat); ++ */ ++ ++ /* Command completion */ ++ if (ireg & TMIO_MASK_CMD) { ++ tmio_mmc_cmd_irq(host, status); ++ ack_mmc_irqs(ctl, TMIO_MASK_CMD); ++ } ++ ++ /* Data transfer */ ++ if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) { ++ ack_mmc_irqs(ctl, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ); ++ tmio_mmc_pio_irq(host); ++ } ++ ++ /* Data transfer completion */ ++ if (ireg & TMIO_STAT_DATAEND) { ++ tmio_mmc_data_irq(host); ++ ack_mmc_irqs(ctl, TMIO_STAT_DATAEND); ++ } ++ ++ /* Check status - keep going until we've handled it all */ ++ status = tmio_ioread32(ctl->status); ++ irq_mask = tmio_ioread32(ctl->irq_mask); ++ ireg = status & TMIO_MASK_IRQ & ~irq_mask; ++ ++#ifdef CONFIG_MMC_DEBUG ++ DBG("Status at end of loop: %08x\n", status); ++ debug_status(status); ++#endif ++ } ++ DBG("MMC IRQ end\n"); ++ ++out: ++ return IRQ_HANDLED; ++} ++ ++static void tmio_mmc_start_data(struct tmio_mmc_host *host, struct mmc_data *data) ++{ ++ struct tmio_mmc_ctl __iomem *ctl = host->ctl; ++ ++ DBG("setup data transfer: blocksize %08x nr_blocks %d\n", ++ data->blksz, data->blocks); ++ ++ tmio_mmc_init_sg(host, data); ++ host->data = data; ++ ++ /* Set transfer length / blocksize */ ++ writew(data->blksz, &ctl->sd_xfer_len); ++ writew(data->blocks, &ctl->xfer_blk_count); ++} ++ ++/* Process requests from the MMC layer */ ++static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) ++{ ++ struct tmio_mmc_host *host = mmc_priv(mmc); ++ ++ WARN_ON(host->mrq != NULL); ++ ++ host->mrq = mrq; ++ ++ /* If we're performing a data request we need to setup some ++ extra information */ ++ if (mrq->data) ++ tmio_mmc_start_data(host, mrq->data); ++ ++ tmio_mmc_start_command(host, mrq->cmd); ++} ++ ++/* Set MMC clock / power. ++ * Note: This controller uses a simple divider scheme therefore it cannot ++ * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as ++ * MMC wont run that fast, it has to be clocked at 12MHz which is the next ++ * slowest setting. ++ */ ++static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) ++{ ++ struct tmio_mmc_host *host = mmc_priv(mmc); ++ struct tmio_mmc_cnf __iomem *cnf = host->cnf; ++ struct tmio_mmc_ctl __iomem *ctl = host->ctl; ++ ++ if(ios->clock) ++ tmio_mmc_set_clock (host, ios->clock); ++ ++ /* Power sequence - OFF -> ON -> UP */ ++ switch (ios->power_mode) { ++ case MMC_POWER_OFF: ++ writeb(0x00, &cnf->pwr_ctl[1]); /* power down SD bus */ ++ tmio_mmc_clk_stop(host); ++ break; ++ case MMC_POWER_ON: ++ writeb(0x02, &cnf->pwr_ctl[1]); /* power up SD bus */ ++ break; ++ case MMC_POWER_UP: ++ tmio_mmc_clk_start(host); /* start bus clock */ ++ break; ++ } ++ ++ switch (ios->bus_width) { ++ case MMC_BUS_WIDTH_1: ++ writew(0x80e0, &ctl->sd_mem_card_opt); ++ break; ++ case MMC_BUS_WIDTH_4: ++ writew(0x00e0, &ctl->sd_mem_card_opt); ++ break; ++ } ++ ++ /* Potentially we may need a 140us pause here. FIXME */ ++ udelay(140); ++} ++ ++static int tmio_mmc_get_ro(struct mmc_host *mmc) { ++ struct tmio_mmc_host *host = mmc_priv(mmc); ++ struct tmio_mmc_ctl __iomem *ctl = host->ctl; ++ ++ return (readw(&ctl->status[0]) & TMIO_STAT_WRPROTECT)?0:1; ++} ++ ++static struct mmc_host_ops tmio_mmc_ops = { ++ .request = tmio_mmc_request, ++ .set_ios = tmio_mmc_set_ios, ++ .get_ro = tmio_mmc_get_ro, ++}; ++ ++static int tmio_mmc_suspend(struct platform_device *dev, pm_message_t state) { ++ struct mfd_cell *cell = mfd_get_cell(dev); ++ struct mmc_host *mmc = platform_get_drvdata(dev); ++ int ret; ++ ++ ret = mmc_suspend_host(mmc, state); ++ ++ /* Tell MFD core it can disable us now.*/ ++ if(!ret && cell->disable) ++ cell->disable(dev); ++ ++ return ret; ++} ++ ++static int tmio_mmc_resume(struct platform_device *dev) { ++ struct mfd_cell *cell = mfd_get_cell(dev); ++ struct mmc_host *mmc = platform_get_drvdata(dev); ++ struct tmio_mmc_host *host = mmc_priv(mmc); ++ struct tmio_mmc_cnf __iomem *cnf = host->cnf; ++ ++ /* Enable the MMC/SD Control registers */ ++ writew(SDCREN, &cnf->cmd); ++ writel(dev->resource[0].start & 0xfffe, &cnf->ctl_base); ++ ++ /* Tell the MFD core we are ready to be enabled */ ++ if(cell->enable) ++ cell->enable(dev); ++ ++ mmc_resume_host(mmc); ++ ++ return 0; ++} ++ ++static int __devinit tmio_mmc_probe(struct platform_device *dev) ++{ ++ struct mfd_cell *cell = mfd_get_cell(dev); ++ struct tmio_mmc_cnf __iomem *cnf; ++ struct tmio_mmc_ctl __iomem *ctl; ++ struct tmio_mmc_host *host; ++ struct mmc_host *mmc; ++ int ret = -ENOMEM; ++ ++ mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &dev->dev); ++ if (!mmc) { ++ goto out; ++ } ++ ++ host = mmc_priv(mmc); ++ host->mmc = mmc; ++ platform_set_drvdata(dev, mmc); /* Used so we can de-init safely. */ ++ ++ host->cnf = cnf = ioremap((unsigned long)dev->resource[1].start, ++ (unsigned long)dev->resource[1].end - ++ (unsigned long)dev->resource[1].start); ++ if(!host->cnf) ++ goto host_free; ++ ++ host->ctl = ctl = ioremap((unsigned long)dev->resource[0].start, ++ (unsigned long)dev->resource[0].end - ++ (unsigned long)dev->resource[0].start); ++ if (!host->ctl) { ++ goto unmap_cnf; ++ } ++ ++ mmc->ops = &tmio_mmc_ops; ++ mmc->caps = MMC_CAP_4_BIT_DATA; ++ mmc->f_min = 46875; ++ mmc->f_max = 24000000; ++ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; ++ ++ /* Enable the MMC/SD Control registers */ ++ writew(SDCREN, &cnf->cmd); ++ writel(dev->resource[0].start & 0xfffe, &cnf->ctl_base); ++ ++ /* Tell the MFD core we are ready to be enabled */ ++ if(cell->enable) ++ cell->enable(dev); ++ ++ writeb(0x01,&cnf->pwr_ctl[2]); /* Disable SD power during suspend */ ++ writeb(0x1f, &cnf->stop_clk_ctl); /* Route clock to SDIO??? FIXME */ ++ writeb(0x0, &cnf->pwr_ctl[1]); /* Power down SD bus*/ ++ tmio_mmc_clk_stop(host); /* Stop bus clock */ ++ reset(host); /* Reset MMC HC */ ++ ++ host->irq = (unsigned long)dev->resource[2].start; ++ ret = request_irq(host->irq, tmio_mmc_irq, IRQF_DISABLED, "tmio-mmc", host); ++ if (ret){ ++ ret = -ENODEV; ++ DBG("Failed to allocate IRQ.\n"); ++ goto unmap_ctl; ++ } ++ set_irq_type(host->irq, IRQT_FALLING); ++ ++ mmc_add_host(mmc); ++ ++ printk(KERN_INFO "%s at 0x%08lx irq %d\n", mmc_hostname(host->mmc), ++ (unsigned long)host->ctl, host->irq); ++ ++ /* Lets unmask the IRQs we want to know about */ ++ disable_mmc_irqs(ctl, TMIO_MASK_ALL); ++ enable_mmc_irqs(ctl, TMIO_MASK_IRQ); ++ ++ return 0; ++ ++unmap_ctl: ++ iounmap(host->ctl); ++unmap_cnf: ++ iounmap(host->cnf); ++host_free: ++ mmc_free_host(mmc); ++out: ++ return ret; ++} ++ ++static int __devexit tmio_mmc_remove(struct platform_device *dev) ++{ ++ struct mmc_host *mmc = platform_get_drvdata(dev); ++ ++ platform_set_drvdata(dev, NULL); ++ ++ if (mmc) { ++ struct tmio_mmc_host *host = mmc_priv(mmc); ++ mmc_remove_host(mmc); ++ free_irq(host->irq, host); ++ /* FIXME - we might want to consider stopping the chip here. */ ++ iounmap(host->ctl); ++ iounmap(host->cnf); ++ mmc_free_host(mmc); /* FIXME - why does this call hang ? */ ++ } ++ return 0; ++} ++ ++/* ------------------- device registration ----------------------- */ ++ ++static struct platform_driver tmio_mmc_driver = { ++ .driver = { ++ .name = "tmio-mmc", ++ }, ++ .probe = tmio_mmc_probe, ++ .remove = __devexit_p(tmio_mmc_remove), ++#ifdef CONFIG_PM ++ .suspend = tmio_mmc_suspend, ++ .resume = tmio_mmc_resume, ++#endif ++}; ++ ++ ++static int __init tmio_mmc_init(void) ++{ ++ return platform_driver_register (&tmio_mmc_driver); ++} ++ ++static void __exit tmio_mmc_exit(void) ++{ ++ platform_driver_unregister (&tmio_mmc_driver); ++} ++ ++module_init(tmio_mmc_init); ++module_exit(tmio_mmc_exit); ++ ++MODULE_DESCRIPTION("Toshiba TMIO SD/MMC driver"); ++MODULE_AUTHOR("Ian Molton <spyro@f2s.com>"); ++MODULE_LICENSE("GPLv2"); +diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h +new file mode 100644 +index 0000000..d4d9f8f +--- /dev/null ++++ b/drivers/mmc/host/tmio_mmc.h +@@ -0,0 +1,205 @@ ++/* Definitons for use with the tmio_mmc.c ++ * ++ * (c) 2005 Ian Molton <spyro@f2s.com> ++ * (c) 2007 Ian Molton <spyro@f2s.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++struct tmio_mmc_cnf { ++ u8 x00[4]; ++ u16 cmd; ++ u8 x01[10]; ++ u32 ctl_base; ++ u8 x02[41]; ++ u8 int_pin; ++ u8 x03[2]; ++ u8 stop_clk_ctl; ++ u8 gclk_ctl; /* Gated Clock Control */ ++ u8 sd_clk_mode; /* 0x42 */ ++ u8 x04; ++ u16 pin_status; ++ u8 x05[2]; ++ u8 pwr_ctl[3]; ++ u8 x06; ++ u8 card_detect_mode; ++ u8 x07[3]; ++ u8 sd_slot; ++ u8 x08[159]; ++ u8 ext_gclk_ctl_1; /* Extended Gated Clock Control 1 */ ++ u8 ext_gclk_ctl_2; /* Extended Gated Clock Control 2 */ ++ u8 x09[7]; ++ u8 ext_gclk_ctl_3; /* Extended Gated Clock Control 3 */ ++ u8 sd_led_en_1; ++ u8 x10[3]; ++ u8 sd_led_en_2; ++ u8 x11; ++} __attribute__ ((packed)); ++ ++#define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/ ++ ++struct tmio_mmc_ctl { ++ u16 sd_cmd; ++ u16 x00; ++ u16 arg_reg[2]; ++ u16 stop_internal_action; ++ u16 xfer_blk_count; ++ u16 response[8]; ++ u16 status[2]; ++ u16 irq_mask[2]; ++ u16 sd_card_clk_ctl; ++ u16 sd_xfer_len; ++ u16 sd_mem_card_opt; ++ u16 x01; ++ u16 sd_error_detail_status[2]; ++ u16 sd_data_port[2]; ++ u16 transaction_ctl; ++ u16 x02[85]; ++ u16 reset_sd; ++ u16 x03[15]; ++ u16 sdio_regs[28]; ++ u16 clk_and_wait_ctl; ++ u16 x04[83]; ++ u16 reset_sdio; ++ u16 x05[15]; ++} __attribute__ ((packed)); ++ ++/* Definitions for values the CTRL_STATUS register can take. */ ++#define TMIO_STAT_CMDRESPEND 0x00000001 ++#define TMIO_STAT_DATAEND 0x00000004 ++#define TMIO_STAT_CARD_REMOVE 0x00000008 ++#define TMIO_STAT_CARD_INSERT 0x00000010 ++#define TMIO_STAT_SIGSTATE 0x00000020 ++#define TMIO_STAT_WRPROTECT 0x00000080 ++#define TMIO_STAT_CARD_REMOVE_A 0x00000100 ++#define TMIO_STAT_CARD_INSERT_A 0x00000200 ++#define TMIO_STAT_SIGSTATE_A 0x00000400 ++#define TMIO_STAT_CMD_IDX_ERR 0x00010000 ++#define TMIO_STAT_CRCFAIL 0x00020000 ++#define TMIO_STAT_STOPBIT_ERR 0x00040000 ++#define TMIO_STAT_DATATIMEOUT 0x00080000 ++#define TMIO_STAT_RXOVERFLOW 0x00100000 ++#define TMIO_STAT_TXUNDERRUN 0x00200000 ++#define TMIO_STAT_CMDTIMEOUT 0x00400000 ++#define TMIO_STAT_RXRDY 0x01000000 ++#define TMIO_STAT_TXRQ 0x02000000 ++#define TMIO_STAT_ILL_FUNC 0x20000000 ++#define TMIO_STAT_CMD_BUSY 0x40000000 ++#define TMIO_STAT_ILL_ACCESS 0x80000000 ++ ++/* Define some IRQ masks */ ++/* This is the mask used at reset by the chip */ ++#define TMIO_MASK_ALL 0x837f031d ++#define TMIO_MASK_READOP (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND | \ ++ TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT) ++#define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND | \ ++ TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT) ++#define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \ ++ TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT) ++#define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD) ++ ++#define enable_mmc_irqs(ctl, i) \ ++ do { \ ++ u32 mask;\ ++ mask = tmio_ioread32((ctl)->irq_mask); \ ++ mask &= ~((i) & TMIO_MASK_IRQ); \ ++ tmio_iowrite32(mask, (ctl)->irq_mask); \ ++ } while (0) ++ ++#define disable_mmc_irqs(ctl, i) \ ++ do { \ ++ u32 mask;\ ++ mask = tmio_ioread32((ctl)->irq_mask); \ ++ mask |= ((i) & TMIO_MASK_IRQ); \ ++ tmio_iowrite32(mask, (ctl)->irq_mask); \ ++ } while (0) ++ ++#define ack_mmc_irqs(ctl, i) \ ++ do { \ ++ u32 mask;\ ++ mask = tmio_ioread32((ctl)->status); \ ++ mask &= ~((i) & TMIO_MASK_IRQ); \ ++ tmio_iowrite32(mask, (ctl)->status); \ ++ } while (0) ++ ++ ++struct tmio_mmc_host { ++ struct tmio_mmc_cnf __iomem *cnf; ++ struct tmio_mmc_ctl __iomem *ctl; ++ struct mmc_command *cmd; ++ struct mmc_request *mrq; ++ struct mmc_data *data; ++ struct mmc_host *mmc; ++ int irq; ++ ++ /* pio related stuff */ ++ struct scatterlist *sg_ptr; ++ unsigned int sg_len; ++ unsigned int sg_off; ++}; ++ ++#include <linux/scatterlist.h> ++#include <linux/blkdev.h> ++ ++static inline void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data) ++{ ++ host->sg_len = data->sg_len; ++ host->sg_ptr = data->sg; ++ host->sg_off = 0; ++} ++ ++static inline int tmio_mmc_next_sg(struct tmio_mmc_host *host) ++{ ++ host->sg_ptr++; ++ host->sg_off = 0; ++ return --host->sg_len; ++} ++ ++static inline char *tmio_mmc_kmap_atomic(struct tmio_mmc_host *host, unsigned long *flags) ++{ ++ struct scatterlist *sg = host->sg_ptr; ++ ++ local_irq_save(*flags); ++ return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; ++} ++ ++static inline void tmio_mmc_kunmap_atomic(struct tmio_mmc_host *host, unsigned long *flags) ++{ ++ kunmap_atomic(sg_page(host->sg_ptr), KM_BIO_SRC_IRQ); ++ local_irq_restore(*flags); ++} ++ ++#ifdef CONFIG_MMC_DEBUG ++#define DBG(args...) printk(args) ++ ++void debug_status(u32 status){ ++ printk("status: %08x = ", status); ++ if(status & TMIO_STAT_CARD_REMOVE) printk("Card_removed "); ++ if(status & TMIO_STAT_CARD_INSERT) printk("Card_insert "); ++ if(status & TMIO_STAT_SIGSTATE) printk("Sigstate "); ++ if(status & TMIO_STAT_WRPROTECT) printk("Write_protect "); ++ if(status & TMIO_STAT_CARD_REMOVE_A) printk("Card_remove_A "); ++ if(status & TMIO_STAT_CARD_INSERT_A) printk("Card_insert_A "); ++ if(status & TMIO_STAT_SIGSTATE_A) printk("Sigstate_A "); ++ if(status & TMIO_STAT_CMD_IDX_ERR) printk("Cmd_IDX_Err "); ++ if(status & TMIO_STAT_STOPBIT_ERR) printk("Stopbit_ERR "); ++ if(status & TMIO_STAT_ILL_FUNC) printk("ILLEGAL_FUNC "); ++ if(status & TMIO_STAT_CMD_BUSY) printk("CMD_BUSY "); ++ if(status & TMIO_STAT_CMDRESPEND) printk("Response_end "); ++ if(status & TMIO_STAT_DATAEND) printk("Data_end "); ++ if(status & TMIO_STAT_CRCFAIL) printk("CRC_failure "); ++ if(status & TMIO_STAT_DATATIMEOUT) printk("Data_timeout "); ++ if(status & TMIO_STAT_CMDTIMEOUT) printk("Command_timeout "); ++ if(status & TMIO_STAT_RXOVERFLOW) printk("RX_OVF "); ++ if(status & TMIO_STAT_TXUNDERRUN) printk("TX_UND "); ++ if(status & TMIO_STAT_RXRDY) printk("RX_rdy "); ++ if(status & TMIO_STAT_TXRQ) printk("TX_req "); ++ if(status & TMIO_STAT_ILL_ACCESS) printk("ILLEGAL_ACCESS "); ++ printk("\n"); ++} ++#else ++#define DBG(fmt,args...) do { } while (0) ++#endif +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0012-Tosa-keyboard-support.patch b/packages/linux/linux-rp-2.6.24/tosa/0012-Tosa-keyboard-support.patch new file mode 100644 index 0000000000..0fa10ebd4c --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0012-Tosa-keyboard-support.patch @@ -0,0 +1,593 @@ +From 6d377e8f80ce421e6842ac5f42081345fbc70002 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Wed, 9 Jan 2008 01:27:41 +0300 +Subject: [PATCH 12/64] Tosa keyboard support + +Support keyboard on tosa (Sharp Zaurus SL-6000x). +Largely based on patches by Dirk Opfer. + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + arch/arm/mach-pxa/tosa.c | 43 ++++ + drivers/input/keyboard/Kconfig | 21 ++ + drivers/input/keyboard/Makefile | 1 + + drivers/input/keyboard/tosakbd.c | 415 ++++++++++++++++++++++++++++++++++++++ + include/asm-arm/arch-pxa/tosa.h | 30 +++ + 5 files changed, 510 insertions(+), 0 deletions(-) + create mode 100644 drivers/input/keyboard/tosakbd.c + +diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c +index 240fd04..e7e0f52 100644 +--- a/arch/arm/mach-pxa/tosa.c ++++ b/arch/arm/mach-pxa/tosa.c +@@ -21,6 +21,8 @@ + #include <linux/mmc/host.h> + #include <linux/pm.h> + #include <linux/delay.h> ++#include <linux/gpio_keys.h> ++#include <linux/input.h> + + #include <asm/setup.h> + #include <asm/memory.h> +@@ -253,6 +255,46 @@ static struct platform_device tosakbd_device = { + .id = -1, + }; + ++static struct gpio_keys_button tosa_gpio_keys[] = { ++ { ++ .type = EV_PWR, ++ .code = KEY_SUSPEND, ++ .gpio = TOSA_GPIO_ON_KEY, ++ .desc = "On key", ++ .wakeup = 1, ++ .active_low = 1, ++ }, ++ { ++ .type = EV_KEY, ++ .code = TOSA_KEY_RECORD, ++ .gpio = TOSA_GPIO_RECORD_BTN, ++ .desc = "Record Button", ++ .wakeup = 1, ++ .active_low = 1, ++ }, ++ { ++ .type = EV_KEY, ++ .code = TOSA_KEY_SYNC, ++ .gpio = TOSA_GPIO_SYNC, ++ .desc = "Sync Button", ++ .wakeup = 1, ++ .active_low = 1, ++ }, ++}; ++ ++static struct gpio_keys_platform_data tosa_gpio_keys_platform_data = { ++ .buttons = tosa_gpio_keys, ++ .nbuttons = ARRAY_SIZE(tosa_gpio_keys), ++}; ++ ++static struct platform_device tosa_gpio_keys_device = { ++ .name = "gpio-keys", ++ .id = -1, ++ .dev = { ++ .platform_data = &tosa_gpio_keys_platform_data, ++ }, ++}; ++ + /* + * Tosa LEDs + */ +@@ -265,6 +307,7 @@ static struct platform_device *devices[] __initdata = { + &tosascoop_device, + &tosascoop_jc_device, + &tosakbd_device, ++ &tosa_gpio_keys_device, + &tosaled_device, + }; + +diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig +index 086d58c..0c32762 100644 +--- a/drivers/input/keyboard/Kconfig ++++ b/drivers/input/keyboard/Kconfig +@@ -154,6 +154,27 @@ config KEYBOARD_SPITZ + To compile this driver as a module, choose M here: the + module will be called spitzkbd. + ++config KEYBOARD_TOSA ++ tristate "Tosa keyboard" ++ depends on MACH_TOSA ++ default y ++ help ++ Say Y here to enable the keyboard on the Sharp Zaurus SL-6000x (Tosa) ++ ++ To compile this driver as a module, choose M here: the ++ module will be called tosakbd. ++ ++config KEYBOARD_TOSA_USE_EXT_KEYCODES ++ bool "Tosa keyboard: use extended keycodes" ++ depends on KEYBOARD_TOSA ++ default n ++ help ++ Say Y here to enable the tosa keyboard driver to generate extended ++ (>= 127) keycodes. Be aware, that they can't be correctly interpreted ++ by either console keyboard driver or by Kdrive keybd driver. ++ ++ Say Y only if you know, what you are doing! ++ + config KEYBOARD_AMIGA + tristate "Amiga keyboard" + depends on AMIGA +diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile +index e97455f..6caa065 100644 +--- a/drivers/input/keyboard/Makefile ++++ b/drivers/input/keyboard/Makefile +@@ -15,6 +15,7 @@ obj-$(CONFIG_KEYBOARD_NEWTON) += newtonkbd.o + obj-$(CONFIG_KEYBOARD_STOWAWAY) += stowaway.o + obj-$(CONFIG_KEYBOARD_CORGI) += corgikbd.o + obj-$(CONFIG_KEYBOARD_SPITZ) += spitzkbd.o ++obj-$(CONFIG_KEYBOARD_TOSA) += tosakbd.o + obj-$(CONFIG_KEYBOARD_HIL) += hil_kbd.o + obj-$(CONFIG_KEYBOARD_HIL_OLD) += hilkbd.o + obj-$(CONFIG_KEYBOARD_OMAP) += omap-keypad.o +diff --git a/drivers/input/keyboard/tosakbd.c b/drivers/input/keyboard/tosakbd.c +new file mode 100644 +index 0000000..3884d1e +--- /dev/null ++++ b/drivers/input/keyboard/tosakbd.c +@@ -0,0 +1,415 @@ ++/* ++ * Keyboard driver for Sharp Tosa models (SL-6000x) ++ * ++ * Copyright (c) 2005 Dirk Opfer ++ * Copyright (c) 2007 Dmitry Baryshkov ++ * ++ * Based on xtkbd.c/locomkbd.c/corgikbd.c ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/platform_device.h> ++#include <linux/input.h> ++#include <linux/delay.h> ++#include <linux/interrupt.h> ++ ++#include <asm/arch/gpio.h> ++#include <asm/arch/tosa.h> ++ ++#define KB_ROWMASK(r) (1 << (r)) ++#define SCANCODE(r, c) (((r)<<4) + (c) + 1) ++#define NR_SCANCODES SCANCODE(TOSA_KEY_SENSE_NUM - 1, TOSA_KEY_STROBE_NUM - 1) + 1 ++ ++#define SCAN_INTERVAL (HZ/10) ++ ++#define KB_DISCHARGE_DELAY 10 ++#define KB_ACTIVATE_DELAY 10 ++ ++static unsigned int tosakbd_keycode[NR_SCANCODES] = { ++0, ++0, KEY_W, 0, 0, 0, KEY_K, KEY_BACKSPACE, KEY_P, ++0, 0, 0, 0, 0, 0, 0, 0, ++KEY_Q, KEY_E, KEY_T, KEY_Y, 0, KEY_O, KEY_I, KEY_COMMA, ++0, 0, 0, 0, 0, 0, 0, 0, ++KEY_A, KEY_D, KEY_G, KEY_U, 0, KEY_L, KEY_ENTER, KEY_DOT, ++0, 0, 0, 0, 0, 0, 0, 0, ++KEY_Z, KEY_C, KEY_V, KEY_J, TOSA_KEY_ADDRESSBOOK, TOSA_KEY_CANCEL, TOSA_KEY_CENTER, TOSA_KEY_OK, ++KEY_LEFTSHIFT, 0, 0, 0, 0, 0, 0, 0, ++KEY_S, KEY_R, KEY_B, KEY_N, TOSA_KEY_CALENDAR, TOSA_KEY_HOMEPAGE, KEY_LEFTCTRL, TOSA_KEY_LIGHT, ++0, KEY_RIGHTSHIFT, 0, 0, 0, 0, 0, 0, ++KEY_TAB, KEY_SLASH, KEY_H, KEY_M, TOSA_KEY_MENU, 0, KEY_UP, 0, ++0, 0, TOSA_KEY_FN, 0, 0, 0, 0, 0, ++KEY_X, KEY_F, KEY_SPACE, KEY_APOSTROPHE, TOSA_KEY_MAIL, KEY_LEFT, KEY_DOWN, KEY_RIGHT, ++0, 0, 0, ++}; ++ ++struct tosakbd { ++ unsigned int keycode[ARRAY_SIZE(tosakbd_keycode)]; ++ struct input_dev *input; ++ ++ spinlock_t lock; /* protect kbd scanning */ ++ struct timer_list timer; ++}; ++ ++ ++/* Helper functions for reading the keyboard matrix ++ * Note: We should really be using pxa_gpio_mode to alter GPDR but it ++ * requires a function call per GPIO bit which is excessive ++ * when we need to access 12 bits at once, multiple times. ++ * These functions must be called within local_irq_save()/local_irq_restore() ++ * or similar. ++ */ ++#define GET_ROWS_STATUS(c) ((GPLR2 & TOSA_GPIO_ALL_SENSE_BIT) >> TOSA_GPIO_ALL_SENSE_RSHIFT) ++ ++static inline void tosakbd_discharge_all(void) ++{ ++ /* STROBE All HiZ */ ++ GPCR1 = TOSA_GPIO_HIGH_STROBE_BIT; ++ GPDR1 &= ~TOSA_GPIO_HIGH_STROBE_BIT; ++ GPCR2 = TOSA_GPIO_LOW_STROBE_BIT; ++ GPDR2 &= ~TOSA_GPIO_LOW_STROBE_BIT; ++} ++ ++static inline void tosakbd_activate_all(void) ++{ ++ /* STROBE ALL -> High */ ++ GPSR1 = TOSA_GPIO_HIGH_STROBE_BIT; ++ GPDR1 |= TOSA_GPIO_HIGH_STROBE_BIT; ++ GPSR2 = TOSA_GPIO_LOW_STROBE_BIT; ++ GPDR2 |= TOSA_GPIO_LOW_STROBE_BIT; ++ ++ udelay(KB_DISCHARGE_DELAY); ++ ++ /* STATE CLEAR */ ++ GEDR2 |= TOSA_GPIO_ALL_SENSE_BIT; ++} ++ ++static inline void tosakbd_activate_col(int col) ++{ ++ if (col <= 5) { ++ /* STROBE col -> High, not col -> HiZ */ ++ GPSR1 = TOSA_GPIO_STROBE_BIT(col); ++ GPDR1 = (GPDR1 & ~TOSA_GPIO_HIGH_STROBE_BIT) | TOSA_GPIO_STROBE_BIT(col); ++ } else { ++ /* STROBE col -> High, not col -> HiZ */ ++ GPSR2 = TOSA_GPIO_STROBE_BIT(col); ++ GPDR2 = (GPDR2 & ~TOSA_GPIO_LOW_STROBE_BIT) | TOSA_GPIO_STROBE_BIT(col); ++ } ++} ++ ++static inline void tosakbd_reset_col(int col) ++{ ++ if (col <= 5) { ++ /* STROBE col -> Low */ ++ GPCR1 = TOSA_GPIO_STROBE_BIT(col); ++ /* STROBE col -> out, not col -> HiZ */ ++ GPDR1 = (GPDR1 & ~TOSA_GPIO_HIGH_STROBE_BIT) | TOSA_GPIO_STROBE_BIT(col); ++ } else { ++ /* STROBE col -> Low */ ++ GPCR2 = TOSA_GPIO_STROBE_BIT(col); ++ /* STROBE col -> out, not col -> HiZ */ ++ GPDR2 = (GPDR2 & ~TOSA_GPIO_LOW_STROBE_BIT) | TOSA_GPIO_STROBE_BIT(col); ++ } ++} ++/* ++ * The tosa keyboard only generates interrupts when a key is pressed. ++ * So when a key is pressed, we enable a timer. This timer scans the ++ * keyboard, and this is how we detect when the key is released. ++ */ ++ ++/* Scan the hardware keyboard and push any changes up through the input layer */ ++static void tosakbd_scankeyboard(struct platform_device *dev) ++{ ++ struct tosakbd *tosakbd = platform_get_drvdata(dev); ++ unsigned int row, col, rowd; ++ unsigned long flags; ++ unsigned int num_pressed = 0; ++ ++ spin_lock_irqsave(&tosakbd->lock, flags); ++ ++ for (col = 0; col < TOSA_KEY_STROBE_NUM; col++) { ++ /* ++ * Discharge the output driver capacitatance ++ * in the keyboard matrix. (Yes it is significant..) ++ */ ++ tosakbd_discharge_all(); ++ udelay(KB_DISCHARGE_DELAY); ++ ++ tosakbd_activate_col(col); ++ udelay(KB_ACTIVATE_DELAY); ++ ++ rowd = GET_ROWS_STATUS(col); ++ ++ for (row = 0; row < TOSA_KEY_SENSE_NUM; row++) { ++ unsigned int scancode, pressed; ++ scancode = SCANCODE(row, col); ++ pressed = rowd & KB_ROWMASK(row); ++ ++ if (pressed && !tosakbd->keycode[scancode]) ++ dev_warn(&dev->dev, ++ "unhandled scancode: 0x%02x\n", ++ scancode); ++ ++ input_report_key(tosakbd->input, ++ tosakbd->keycode[scancode], ++ pressed); ++ if (pressed) ++ num_pressed++; ++ } ++ ++ tosakbd_reset_col(col); ++ } ++ ++ tosakbd_activate_all(); ++ ++ input_sync(tosakbd->input); ++ ++ /* if any keys are pressed, enable the timer */ ++ if (num_pressed) ++ mod_timer(&tosakbd->timer, jiffies + SCAN_INTERVAL); ++ ++ spin_unlock_irqrestore(&tosakbd->lock, flags); ++} ++ ++/* ++ * tosa keyboard interrupt handler. ++ */ ++static irqreturn_t tosakbd_interrupt(int irq, void *__dev) ++{ ++ struct platform_device *dev = __dev; ++ struct tosakbd *tosakbd = platform_get_drvdata(dev); ++ ++ if (!timer_pending(&tosakbd->timer)) { ++ /** wait chattering delay **/ ++ udelay(20); ++ tosakbd_scankeyboard(dev); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++/* ++ * tosa timer checking for released keys ++ */ ++static void tosakbd_timer_callback(unsigned long __dev) ++{ ++ struct platform_device *dev = (struct platform_device *)__dev; ++ tosakbd_scankeyboard(dev); ++} ++ ++#ifdef CONFIG_PM ++static int tosakbd_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ struct tosakbd *tosakbd = platform_get_drvdata(dev); ++ ++ del_timer_sync(&tosakbd->timer); ++ ++ return 0; ++} ++ ++static int tosakbd_resume(struct platform_device *dev) ++{ ++ tosakbd_scankeyboard(dev); ++ ++ return 0; ++} ++#else ++#define tosakbd_suspend NULL ++#define tosakbd_resume NULL ++#endif ++ ++static int __devinit tosakbd_probe(struct platform_device *pdev) { ++ ++ int i; ++ struct tosakbd *tosakbd; ++ struct input_dev *input_dev; ++ int error; ++ ++ tosakbd = kzalloc(sizeof(struct tosakbd), GFP_KERNEL); ++ if (!tosakbd) ++ return -ENOMEM; ++ ++ input_dev = input_allocate_device(); ++ if (!input_dev) { ++ kfree(tosakbd); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(pdev, tosakbd); ++ ++ spin_lock_init(&tosakbd->lock); ++ ++ /* Init Keyboard rescan timer */ ++ init_timer(&tosakbd->timer); ++ tosakbd->timer.function = tosakbd_timer_callback; ++ tosakbd->timer.data = (unsigned long) pdev; ++ ++ tosakbd->input = input_dev; ++ ++ input_set_drvdata(input_dev, tosakbd); ++ input_dev->name = "Tosa Keyboard"; ++ input_dev->phys = "tosakbd/input0"; ++ input_dev->dev.parent = &pdev->dev; ++ ++ input_dev->id.bustype = BUS_HOST; ++ input_dev->id.vendor = 0x0001; ++ input_dev->id.product = 0x0001; ++ input_dev->id.version = 0x0100; ++ ++ input_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_REP); ++ input_dev->keycode = tosakbd->keycode; ++ input_dev->keycodesize = sizeof(unsigned int); ++ input_dev->keycodemax = ARRAY_SIZE(tosakbd_keycode); ++ ++ memcpy(tosakbd->keycode, tosakbd_keycode, sizeof(tosakbd_keycode)); ++ ++ for (i = 0; i < ARRAY_SIZE(tosakbd_keycode); i++) ++ __set_bit(tosakbd->keycode[i], input_dev->keybit); ++ clear_bit(0, input_dev->keybit); ++ ++ /* Setup sense interrupts - RisingEdge Detect, sense lines as inputs */ ++ for (i = 0; i < TOSA_KEY_SENSE_NUM; i++) { ++ int gpio = TOSA_GPIO_KEY_SENSE(i); ++ int irq; ++ error = gpio_request(gpio, "tosakbd"); ++ if (error < 0) { ++ printk(KERN_ERR "tosakbd: failed to request GPIO %d, " ++ " error %d\n", gpio, error); ++ goto fail; ++ } ++ ++ error = gpio_direction_input(TOSA_GPIO_KEY_SENSE(i)); ++ if (error < 0) { ++ printk(KERN_ERR "tosakbd: failed to configure input" ++ " direction for GPIO %d, error %d\n", ++ gpio, error); ++ gpio_free(gpio); ++ goto fail; ++ } ++ ++ irq = gpio_to_irq(gpio); ++ if (irq < 0) { ++ error = irq; ++ printk(KERN_ERR "gpio-keys: Unable to get irq number" ++ " for GPIO %d, error %d\n", ++ gpio, error); ++ gpio_free(gpio); ++ goto fail; ++ } ++ ++ error = request_irq(irq, tosakbd_interrupt, ++ IRQF_DISABLED | IRQF_TRIGGER_RISING, ++ "tosakbd", pdev); ++ ++ if (error) { ++ printk("tosakbd: Can't get IRQ: %d: error %d!\n", ++ irq, error); ++ gpio_free(gpio); ++ goto fail; ++ } ++ } ++ ++ /* Set Strobe lines as outputs - set high */ ++ for (i = 0; i < TOSA_KEY_STROBE_NUM; i++) { ++ int gpio = TOSA_GPIO_KEY_STROBE(i); ++ error = gpio_request(gpio, "tosakbd"); ++ if (error < 0) { ++ printk(KERN_ERR "tosakbd: failed to request GPIO %d, " ++ " error %d\n", gpio, error); ++ goto fail2; ++ } ++ ++ error = gpio_direction_output(gpio, 1); ++ if (error < 0) { ++ printk(KERN_ERR "tosakbd: failed to configure input" ++ " direction for GPIO %d, error %d\n", ++ gpio, error); ++ gpio_free(gpio); ++ goto fail; ++ } ++ ++ } ++ ++ error = input_register_device(input_dev); ++ if (error) { ++ printk(KERN_ERR "tosakbd: Unable to register input device, " ++ "error: %d\n", error); ++ goto fail; ++ } ++ ++ printk(KERN_INFO "input: Tosa Keyboard Registered\n"); ++ ++ return 0; ++ ++fail2: ++ while (--i >= 0) ++ gpio_free(TOSA_GPIO_KEY_STROBE(i)); ++ ++ i = TOSA_KEY_SENSE_NUM; ++fail: ++ while (--i >= 0) { ++ free_irq(gpio_to_irq(TOSA_GPIO_KEY_SENSE(i)), pdev); ++ gpio_free(TOSA_GPIO_KEY_SENSE(i)); ++ } ++ ++ platform_set_drvdata(pdev, NULL); ++ input_free_device(input_dev); ++ kfree(tosakbd); ++ ++ return error; ++} ++ ++static int __devexit tosakbd_remove(struct platform_device *dev) { ++ ++ int i; ++ struct tosakbd *tosakbd = platform_get_drvdata(dev); ++ ++ for (i = 0; i < TOSA_KEY_STROBE_NUM; i++) ++ gpio_free(TOSA_GPIO_KEY_STROBE(i)); ++ ++ for (i = 0; i < TOSA_KEY_SENSE_NUM; i++) { ++ free_irq(gpio_to_irq(TOSA_GPIO_KEY_SENSE(i)), dev); ++ gpio_free(TOSA_GPIO_KEY_SENSE(i)); ++ } ++ ++ del_timer_sync(&tosakbd->timer); ++ ++ input_unregister_device(tosakbd->input); ++ ++ kfree(tosakbd); ++ ++ return 0; ++} ++ ++static struct platform_driver tosakbd_driver = { ++ .probe = tosakbd_probe, ++ .remove = __devexit_p(tosakbd_remove), ++ .suspend = tosakbd_suspend, ++ .resume = tosakbd_resume, ++ .driver = { ++ .name = "tosa-keyboard", ++ }, ++}; ++ ++static int __devinit tosakbd_init(void) ++{ ++ return platform_driver_register(&tosakbd_driver); ++} ++ ++static void __exit tosakbd_exit(void) ++{ ++ platform_driver_unregister(&tosakbd_driver); ++} ++ ++module_init(tosakbd_init); ++module_exit(tosakbd_exit); ++ ++MODULE_AUTHOR("Dirk Opfer <Dirk@Opfer-Online.de>"); ++MODULE_DESCRIPTION("Tosa Keyboard Driver"); ++MODULE_LICENSE("GPL v2"); +diff --git a/include/asm-arm/arch-pxa/tosa.h b/include/asm-arm/arch-pxa/tosa.h +index c3364a2..c05e4fa 100644 +--- a/include/asm-arm/arch-pxa/tosa.h ++++ b/include/asm-arm/arch-pxa/tosa.h +@@ -163,4 +163,34 @@ + + extern struct platform_device tosascoop_jc_device; + extern struct platform_device tosascoop_device; ++ ++#define TOSA_KEY_SYNC KEY_102ND /* ??? */ ++ ++ ++#ifndef CONFIG_KEYBOARD_TOSA_USE_EXT_KEYCODES ++#define TOSA_KEY_RECORD KEY_YEN ++#define TOSA_KEY_ADDRESSBOOK KEY_KATAKANA ++#define TOSA_KEY_CANCEL KEY_ESC ++#define TOSA_KEY_CENTER KEY_HIRAGANA ++#define TOSA_KEY_OK KEY_HENKAN ++#define TOSA_KEY_CALENDAR KEY_KATAKANAHIRAGANA ++#define TOSA_KEY_HOMEPAGE KEY_HANGEUL ++#define TOSA_KEY_LIGHT KEY_MUHENKAN ++#define TOSA_KEY_MENU KEY_HANJA ++#define TOSA_KEY_FN KEY_RIGHTALT ++#define TOSA_KEY_MAIL KEY_ZENKAKUHANKAKU ++#else ++#define TOSA_KEY_RECORD KEY_RECORD ++#define TOSA_KEY_ADDRESSBOOK KEY_ADDRESSBOOK ++#define TOSA_KEY_CANCEL KEY_CANCEL ++#define TOSA_KEY_CENTER KEY_SELECT /* ??? */ ++#define TOSA_KEY_OK KEY_OK ++#define TOSA_KEY_CALENDAR KEY_CALENDAR ++#define TOSA_KEY_HOMEPAGE KEY_HOMEPAGE ++#define TOSA_KEY_LIGHT KEY_KBDILLUMTOGGLE ++#define TOSA_KEY_MENU KEY_MENU ++#define TOSA_KEY_FN KEY_FN ++#define TOSA_KEY_MAIL KEY_MAIL ++#endif ++ + #endif /* _ASM_ARCH_TOSA_H_ */ +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0013-USB-gadget-pxa2xx_udc-supports-inverted-vbus.patch b/packages/linux/linux-rp-2.6.24/tosa/0013-USB-gadget-pxa2xx_udc-supports-inverted-vbus.patch new file mode 100644 index 0000000000..082a2c72b8 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0013-USB-gadget-pxa2xx_udc-supports-inverted-vbus.patch @@ -0,0 +1,61 @@ +From 18c1a92a09faf75ebdac7ac471c741a6622cf3e2 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Wed, 9 Jan 2008 01:27:49 +0300 +Subject: [PATCH 13/64] USB: gadget: pxa2xx_udc supports inverted vbus + +Some boards (like e.g. Tosa) invert the VBUS-detection signal: +it's low when a host is supplying VBUS, and high otherwise. +Allow specifying whether gpio_vbus value is inverted. + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> +Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> +--- + drivers/usb/gadget/pxa2xx_udc.c | 9 +++++++-- + include/asm-arm/mach/udc_pxa2xx.h | 2 ++ + 2 files changed, 9 insertions(+), 2 deletions(-) + +diff --git a/drivers/usb/gadget/pxa2xx_udc.c b/drivers/usb/gadget/pxa2xx_udc.c +index 3173b39..4f7d4ef 100644 +--- a/drivers/usb/gadget/pxa2xx_udc.c ++++ b/drivers/usb/gadget/pxa2xx_udc.c +@@ -127,8 +127,10 @@ static int is_vbus_present(void) + { + struct pxa2xx_udc_mach_info *mach = the_controller->mach; + +- if (mach->gpio_vbus) +- return gpio_get_value(mach->gpio_vbus); ++ if (mach->gpio_vbus) { ++ int value = gpio_get_value(mach->gpio_vbus); ++ return mach->gpio_vbus_inverted ? !value : value; ++ } + if (mach->udc_is_connected) + return mach->udc_is_connected(); + return 1; +@@ -1397,6 +1399,9 @@ static irqreturn_t udc_vbus_irq(int irq, void *_dev) + struct pxa2xx_udc *dev = _dev; + int vbus = gpio_get_value(dev->mach->gpio_vbus); + ++ if (dev->mach->gpio_vbus_inverted) ++ vbus = !vbus; ++ + pxa2xx_udc_vbus_session(&dev->gadget, vbus); + return IRQ_HANDLED; + } +diff --git a/include/asm-arm/mach/udc_pxa2xx.h b/include/asm-arm/mach/udc_pxa2xx.h +index ff0a957..f191e14 100644 +--- a/include/asm-arm/mach/udc_pxa2xx.h ++++ b/include/asm-arm/mach/udc_pxa2xx.h +@@ -19,7 +19,9 @@ struct pxa2xx_udc_mach_info { + * with on-chip GPIOs not Lubbock's wierd hardware, can have a sane + * VBUS IRQ and omit the methods above. Store the GPIO number + * here; for GPIO 0, also mask in one of the pxa_gpio_mode() bits. ++ * Note that sometimes the signals go through inverters... + */ ++ bool gpio_vbus_inverted; + u16 gpio_vbus; /* high == vbus present */ + u16 gpio_pullup; /* high == pullup activated */ + }; +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0014-tosa_udc_use_gpio_vbus.patch.patch b/packages/linux/linux-rp-2.6.24/tosa/0014-tosa_udc_use_gpio_vbus.patch.patch new file mode 100644 index 0000000000..98783efea0 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0014-tosa_udc_use_gpio_vbus.patch.patch @@ -0,0 +1,38 @@ +From 932ff38b17c7847c43e2bad01b510b64c27f9810 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Wed, 9 Jan 2008 01:27:59 +0300 +Subject: [PATCH 14/64] tosa_udc_use_gpio_vbus.patch + +Use gpio_vbus instead of udc_is_connected for udc on tosa. + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> +--- + arch/arm/mach-pxa/tosa.c | 9 ++------- + 1 files changed, 2 insertions(+), 7 deletions(-) + +diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c +index e7e0f52..5268e94 100644 +--- a/arch/arm/mach-pxa/tosa.c ++++ b/arch/arm/mach-pxa/tosa.c +@@ -159,15 +159,10 @@ static void tosa_udc_command(int cmd) + } + } + +-static int tosa_udc_is_connected(void) +-{ +- return ((GPLR(TOSA_GPIO_USB_IN) & GPIO_bit(TOSA_GPIO_USB_IN)) == 0); +-} +- +- + static struct pxa2xx_udc_mach_info udc_info __initdata = { + .udc_command = tosa_udc_command, +- .udc_is_connected = tosa_udc_is_connected, ++ .gpio_vbus = TOSA_GPIO_USB_IN, ++ .gpio_vbus_inverted = 1, + }; + + /* +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0015-sharpsl-export-params.patch b/packages/linux/linux-rp-2.6.24/tosa/0015-sharpsl-export-params.patch new file mode 100644 index 0000000000..f8e57e8306 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0015-sharpsl-export-params.patch @@ -0,0 +1,32 @@ +From bba216220d17d1091413e82c9924ac5614402c05 Mon Sep 17 00:00:00 2001 +From: Ian Molton <spyro@f2s.com> +Date: Wed, 9 Jan 2008 01:28:06 +0300 +Subject: [PATCH 15/64] sharpsl export params + +--- + arch/arm/common/sharpsl_param.c | 2 ++ + 1 files changed, 2 insertions(+), 0 deletions(-) + +diff --git a/arch/arm/common/sharpsl_param.c b/arch/arm/common/sharpsl_param.c +index aad4d94..d56c932 100644 +--- a/arch/arm/common/sharpsl_param.c ++++ b/arch/arm/common/sharpsl_param.c +@@ -12,6 +12,7 @@ + */ + + #include <linux/kernel.h> ++#include <linux/module.h> + #include <linux/string.h> + #include <asm/mach/sharpsl_param.h> + +@@ -36,6 +37,7 @@ + #define PHAD_MAGIC MAGIC_CHG('P','H','A','D') + + struct sharpsl_param_info sharpsl_param; ++EXPORT_SYMBOL(sharpsl_param); + + void sharpsl_save_param(void) + { +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0016-This-patch-fixes-the-pxa25x-clocks-definitions-to-ad.patch b/packages/linux/linux-rp-2.6.24/tosa/0016-This-patch-fixes-the-pxa25x-clocks-definitions-to-ad.patch new file mode 100644 index 0000000000..d73de0698c --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0016-This-patch-fixes-the-pxa25x-clocks-definitions-to-ad.patch @@ -0,0 +1,44 @@ +From 0fe7b491b70efafbd41185f8e95a3eada65984a1 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Mon, 28 Jan 2008 01:49:28 +0300 +Subject: [PATCH 16/64] This patch fixes the pxa25x clocks definitions to add hwuart. + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + arch/arm/mach-pxa/pxa25x.c | 9 ++++++++- + 1 files changed, 8 insertions(+), 1 deletions(-) + +diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c +index 9732d5d..006a6e0 100644 +--- a/arch/arm/mach-pxa/pxa25x.c ++++ b/arch/arm/mach-pxa/pxa25x.c +@@ -111,11 +111,14 @@ static const struct clkops clk_pxa25x_lcd_ops = { + * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz + * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly) + */ ++static struct clk pxa25x_hwuart_clk = ++ INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev) ++; ++ + static struct clk pxa25x_clks[] = { + INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev), + INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev), + INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), +- INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), + INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL), + INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev), + INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev), +@@ -303,6 +306,10 @@ static int __init pxa25x_init(void) + { + int ret = 0; + ++ /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ ++ if (cpu_is_pxa25x()) ++ clks_register(&pxa25x_hwuart_clk, 1); ++ + if (cpu_is_pxa21x() || cpu_is_pxa25x()) { + clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks)); + +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0017-Convert-pxa2xx-UDC-to-use-debugfs.patch b/packages/linux/linux-rp-2.6.24/tosa/0017-Convert-pxa2xx-UDC-to-use-debugfs.patch new file mode 100644 index 0000000000..5163361da3 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0017-Convert-pxa2xx-UDC-to-use-debugfs.patch @@ -0,0 +1,280 @@ +From 71857e8f6c4a8d2d3eac3037f02e0c30c6fdb37e Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Wed, 9 Jan 2008 01:43:28 +0300 +Subject: [PATCH 17/64] Convert pxa2xx UDC to use debugfs + +Use debugfs instead of /proc/driver/udc + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + drivers/usb/gadget/pxa2xx_udc.c | 100 +++++++++++++++++---------------------- + drivers/usb/gadget/pxa2xx_udc.h | 10 +++- + 2 files changed, 51 insertions(+), 59 deletions(-) + +diff --git a/drivers/usb/gadget/pxa2xx_udc.c b/drivers/usb/gadget/pxa2xx_udc.c +index 4f7d4ef..2900556 100644 +--- a/drivers/usb/gadget/pxa2xx_udc.c ++++ b/drivers/usb/gadget/pxa2xx_udc.c +@@ -38,13 +38,14 @@ + #include <linux/timer.h> + #include <linux/list.h> + #include <linux/interrupt.h> +-#include <linux/proc_fs.h> + #include <linux/mm.h> + #include <linux/platform_device.h> + #include <linux/dma-mapping.h> + #include <linux/irq.h> + #include <linux/clk.h> + #include <linux/err.h> ++#include <linux/seq_file.h> ++#include <linux/debugfs.h> + + #include <asm/byteorder.h> + #include <asm/dma.h> +@@ -993,45 +994,36 @@ static const struct usb_gadget_ops pxa2xx_udc_ops = { + + /*-------------------------------------------------------------------------*/ + +-#ifdef CONFIG_USB_GADGET_DEBUG_FILES +- +-static const char proc_node_name [] = "driver/udc"; ++#ifdef CONFIG_USB_GADGET_DEBUG_FS + ++static struct pxa2xx_udc memory; + static int +-udc_proc_read(char *page, char **start, off_t off, int count, +- int *eof, void *_dev) ++udc_seq_show(struct seq_file *m, void *d) + { +- char *buf = page; +- struct pxa2xx_udc *dev = _dev; +- char *next = buf; +- unsigned size = count; ++ struct pxa2xx_udc *dev = m->private; + unsigned long flags; +- int i, t; ++ int i; + u32 tmp; + +- if (off != 0) +- return 0; ++ ++ BUG_ON(dev == NULL); + + local_irq_save(flags); + + /* basic device status */ +- t = scnprintf(next, size, DRIVER_DESC "\n" ++ seq_printf(m, DRIVER_DESC "\n" + "%s version: %s\nGadget driver: %s\nHost %s\n\n", + driver_name, DRIVER_VERSION SIZE_STR "(pio)", + dev->driver ? dev->driver->driver.name : "(none)", + is_vbus_present() ? "full speed" : "disconnected"); +- size -= t; +- next += t; + + /* registers for device and ep0 */ +- t = scnprintf(next, size, ++ seq_printf(m, + "uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n", + UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL); +- size -= t; +- next += t; + + tmp = UDCCR; +- t = scnprintf(next, size, ++ seq_printf(m, + "udccr %02X =%s%s%s%s%s%s%s%s\n", tmp, + (tmp & UDCCR_REM) ? " rem" : "", + (tmp & UDCCR_RSTIR) ? " rstir" : "", +@@ -1041,11 +1033,9 @@ udc_proc_read(char *page, char **start, off_t off, int count, + (tmp & UDCCR_RSM) ? " rsm" : "", + (tmp & UDCCR_UDA) ? " uda" : "", + (tmp & UDCCR_UDE) ? " ude" : ""); +- size -= t; +- next += t; + + tmp = UDCCS0; +- t = scnprintf(next, size, ++ seq_printf(m, + "udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp, + (tmp & UDCCS0_SA) ? " sa" : "", + (tmp & UDCCS0_RNE) ? " rne" : "", +@@ -1055,28 +1045,22 @@ udc_proc_read(char *page, char **start, off_t off, int count, + (tmp & UDCCS0_FTF) ? " ftf" : "", + (tmp & UDCCS0_IPR) ? " ipr" : "", + (tmp & UDCCS0_OPR) ? " opr" : ""); +- size -= t; +- next += t; + + if (dev->has_cfr) { + tmp = UDCCFR; +- t = scnprintf(next, size, ++ seq_printf(m, + "udccfr %02X =%s%s\n", tmp, + (tmp & UDCCFR_AREN) ? " aren" : "", + (tmp & UDCCFR_ACM) ? " acm" : ""); +- size -= t; +- next += t; + } + + if (!is_vbus_present() || !dev->driver) + goto done; + +- t = scnprintf(next, size, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n", ++ seq_printf(m, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n", + dev->stats.write.bytes, dev->stats.write.ops, + dev->stats.read.bytes, dev->stats.read.ops, + dev->stats.irqs); +- size -= t; +- next += t; + + /* dump endpoint queues */ + for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { +@@ -1090,55 +1074,57 @@ udc_proc_read(char *page, char **start, off_t off, int count, + if (!d) + continue; + tmp = *dev->ep [i].reg_udccs; +- t = scnprintf(next, size, ++ seq_printf(m, + "%s max %d %s udccs %02x irqs %lu\n", + ep->ep.name, le16_to_cpu (d->wMaxPacketSize), + "pio", tmp, ep->pio_irqs); + /* TODO translate all five groups of udccs bits! */ + + } else /* ep0 should only have one transfer queued */ +- t = scnprintf(next, size, "ep0 max 16 pio irqs %lu\n", ++ seq_printf(m, "ep0 max 16 pio irqs %lu\n", + ep->pio_irqs); +- if (t <= 0 || t > size) +- goto done; +- size -= t; +- next += t; + + if (list_empty(&ep->queue)) { +- t = scnprintf(next, size, "\t(nothing queued)\n"); +- if (t <= 0 || t > size) +- goto done; +- size -= t; +- next += t; ++ seq_printf(m, "\t(nothing queued)\n"); + continue; + } + list_for_each_entry(req, &ep->queue, queue) { +- t = scnprintf(next, size, ++ seq_printf(m, + "\treq %p len %d/%d buf %p\n", + &req->req, req->req.actual, + req->req.length, req->req.buf); +- if (t <= 0 || t > size) +- goto done; +- size -= t; +- next += t; + } + } + + done: + local_irq_restore(flags); +- *eof = 1; +- return count - size; ++ return 0; + } + +-#define create_proc_files() \ +- create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev) +-#define remove_proc_files() \ +- remove_proc_entry(proc_node_name, NULL) ++static int ++udc_debugfs_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, udc_seq_show, inode->i_private); ++} ++ ++static const struct file_operations debug_fops = { ++ .open = udc_debugfs_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++ .owner = THIS_MODULE, ++}; ++ ++#define create_debug_files(dev) \ ++ dev->debugfs_udc = debugfs_create_file(dev->gadget.name, S_IRUGO, \ ++ NULL, dev, &debug_fops) ++#define remove_debug_files(dev) \ ++ if (dev->debugfs_udc) debugfs_remove(dev->debugfs_udc) + + #else /* !CONFIG_USB_GADGET_DEBUG_FILES */ + +-#define create_proc_files() do {} while (0) +-#define remove_proc_files() do {} while (0) ++#define create_debug_files(dev) do {} while (0) ++#define remove_debug_files(dev) do {} while (0) + + #endif /* CONFIG_USB_GADGET_DEBUG_FILES */ + +@@ -2245,7 +2231,7 @@ lubbock_fail0: + goto err_vbus_irq; + } + } +- create_proc_files(); ++ create_debug_files(dev); + + return 0; + +@@ -2282,7 +2268,7 @@ static int __exit pxa2xx_udc_remove(struct platform_device *pdev) + return -EBUSY; + + udc_disable(dev); +- remove_proc_files(); ++ remove_debug_files(dev); + + if (dev->got_irq) { + free_irq(platform_get_irq(pdev, 0), dev); +diff --git a/drivers/usb/gadget/pxa2xx_udc.h b/drivers/usb/gadget/pxa2xx_udc.h +index 1db46d7..c08b1a2 100644 +--- a/drivers/usb/gadget/pxa2xx_udc.h ++++ b/drivers/usb/gadget/pxa2xx_udc.h +@@ -129,6 +129,10 @@ struct pxa2xx_udc { + struct pxa2xx_udc_mach_info *mach; + u64 dma_mask; + struct pxa2xx_ep ep [PXA_UDC_NUM_ENDPOINTS]; ++ ++#ifdef CONFIG_USB_GADGET_DEBUG_FS ++ struct dentry *debugfs_udc; ++#endif + }; + + /*-------------------------------------------------------------------------*/ +@@ -153,6 +157,8 @@ static struct pxa2xx_udc *the_controller; + + #ifdef DEBUG + ++static int is_vbus_present(void); ++ + static const char *state_name[] = { + "EP0_IDLE", + "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE", +@@ -207,8 +213,7 @@ dump_state(struct pxa2xx_udc *dev) + unsigned i; + + DMSG("%s %s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n", +- //is_usb_connected() ? "host " : "disconnected", +- "host ", ++ is_vbus_present() ? "host " : "disconnected", + state_name[dev->ep0state], + UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL); + dump_udccr("udccr"); +@@ -224,7 +230,7 @@ dump_state(struct pxa2xx_udc *dev) + } else + DMSG("ep0 driver '%s'\n", dev->driver->driver.name); + +- //if (!is_usb_connected()) +- // return; ++ if (!is_vbus_present()) ++ return; + + dump_udccs0 ("udccs0"); +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0018-Fix-the-pxa2xx_udc-to-balance-calls-to-clk_enable-cl.patch b/packages/linux/linux-rp-2.6.24/tosa/0018-Fix-the-pxa2xx_udc-to-balance-calls-to-clk_enable-cl.patch new file mode 100644 index 0000000000..7bf4ad02d6 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0018-Fix-the-pxa2xx_udc-to-balance-calls-to-clk_enable-cl.patch @@ -0,0 +1,225 @@ +From b9a0fdbf333b461682d5da8b9aaa42f4de91ffcf Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Sun, 10 Feb 2008 03:29:17 +0300 +Subject: [PATCH 18/64] Fix the pxa2xx_udc to balance calls to clk_enable/clk_disable + +Signed-off-by: Dmitry Baryshkov dbaryshkov@gmail.com +--- + drivers/usb/gadget/pxa2xx_udc.c | 84 +++++++++++++++++++++++---------------- + drivers/usb/gadget/pxa2xx_udc.h | 6 ++- + 2 files changed, 54 insertions(+), 36 deletions(-) + +diff --git a/drivers/usb/gadget/pxa2xx_udc.c b/drivers/usb/gadget/pxa2xx_udc.c +index 2900556..8e32d07 100644 +--- a/drivers/usb/gadget/pxa2xx_udc.c ++++ b/drivers/usb/gadget/pxa2xx_udc.c +@@ -680,7 +680,7 @@ pxa2xx_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) + + /* kickstart this i/o queue? */ + if (list_empty(&ep->queue) && !ep->stopped) { +- if (ep->desc == 0 /* ep0 */) { ++ if (ep->desc == NULL /* ep0 */) { + unsigned length = _req->length; + + switch (dev->ep0state) { +@@ -734,7 +734,7 @@ pxa2xx_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) + } + + /* pio or dma irq handler advances the queue. */ +- if (likely (req != 0)) ++ if (likely (req != NULL)) + list_add_tail(&req->queue, &ep->queue); + local_irq_restore(flags); + +@@ -934,20 +934,35 @@ static void udc_disable(struct pxa2xx_udc *); + /* We disable the UDC -- and its 48 MHz clock -- whenever it's not + * in active use. + */ +-static int pullup(struct pxa2xx_udc *udc, int is_active) ++static int pullup(struct pxa2xx_udc *udc) + { +- is_active = is_active && udc->vbus && udc->pullup; ++ int is_active = udc->vbus && udc->pullup && ! udc->suspended; + DMSG("%s\n", is_active ? "active" : "inactive"); +- if (is_active) +- udc_enable(udc); +- else { +- if (udc->gadget.speed != USB_SPEED_UNKNOWN) { +- DMSG("disconnect %s\n", udc->driver +- ? udc->driver->driver.name +- : "(no driver)"); +- stop_activity(udc, udc->driver); ++ if (is_active) { ++ if (!udc->active) { ++ udc->active = 1; ++#ifdef CONFIG_ARCH_PXA ++ /* Enable clock for USB device */ ++ clk_enable(udc->clk); ++#endif ++ udc_enable(udc); + } +- udc_disable(udc); ++ } else { ++ if (udc->active) { ++ if (udc->gadget.speed != USB_SPEED_UNKNOWN) { ++ DMSG("disconnect %s\n", udc->driver ++ ? udc->driver->driver.name ++ : "(no driver)"); ++ stop_activity(udc, udc->driver); ++ } ++ udc_disable(udc); ++#ifdef CONFIG_ARCH_PXA ++ /* Disable clock for USB device */ ++ clk_disable(udc->clk); ++#endif ++ udc->active = 0; ++ } ++ + } + return 0; + } +@@ -958,9 +973,9 @@ static int pxa2xx_udc_vbus_session(struct usb_gadget *_gadget, int is_active) + struct pxa2xx_udc *udc; + + udc = container_of(_gadget, struct pxa2xx_udc, gadget); +- udc->vbus = is_active = (is_active != 0); ++ udc->vbus = (is_active != 0); + DMSG("vbus %s\n", is_active ? "supplied" : "inactive"); +- pullup(udc, is_active); ++ pullup(udc); + return 0; + } + +@@ -975,9 +990,8 @@ static int pxa2xx_udc_pullup(struct usb_gadget *_gadget, int is_active) + if (!udc->mach->gpio_pullup && !udc->mach->udc_command) + return -EOPNOTSUPP; + +- is_active = (is_active != 0); +- udc->pullup = is_active; +- pullup(udc, is_active); ++ udc->pullup = (is_active != 0); ++ pullup(udc); + return 0; + } + +@@ -998,7 +1012,7 @@ static const struct usb_gadget_ops pxa2xx_udc_ops = { + + static struct pxa2xx_udc memory; + static int +-udc_seq_show(struct seq_file *m, void *d) ++udc_seq_show(struct seq_file *m, void *_d) + { + struct pxa2xx_udc *dev = m->private; + unsigned long flags; +@@ -1145,11 +1159,6 @@ static void udc_disable(struct pxa2xx_udc *dev) + + udc_clear_mask_UDCCR(UDCCR_UDE); + +-#ifdef CONFIG_ARCH_PXA +- /* Disable clock for USB device */ +- clk_disable(dev->clk); +-#endif +- + ep0_idle (dev); + dev->gadget.speed = USB_SPEED_UNKNOWN; + } +@@ -1190,11 +1199,6 @@ static void udc_enable (struct pxa2xx_udc *dev) + { + udc_clear_mask_UDCCR(UDCCR_UDE); + +-#ifdef CONFIG_ARCH_PXA +- /* Enable clock for USB device */ +- clk_enable(dev->clk); +-#endif +- + /* try to clear these bits before we enable the udc */ + udc_ack_int_UDCCR(UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR); + +@@ -1285,7 +1289,7 @@ fail: + * for set_configuration as well as eventual disconnect. + */ + DMSG("registered gadget driver '%s'\n", driver->driver.name); +- pullup(dev, 1); ++ pullup(dev); + dump_state(dev); + return 0; + } +@@ -1328,7 +1332,8 @@ int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) + return -EINVAL; + + local_irq_disable(); +- pullup(dev, 0); ++ dev->pullup = 0; ++ pullup(dev); + stop_activity(dev, driver); + local_irq_enable(); + +@@ -2267,7 +2272,9 @@ static int __exit pxa2xx_udc_remove(struct platform_device *pdev) + if (dev->driver) + return -EBUSY; + +- udc_disable(dev); ++ dev->pullup = 0; ++ pullup(dev); ++ + remove_debug_files(dev); + + if (dev->got_irq) { +@@ -2315,10 +2322,15 @@ static int __exit pxa2xx_udc_remove(struct platform_device *pdev) + static int pxa2xx_udc_suspend(struct platform_device *dev, pm_message_t state) + { + struct pxa2xx_udc *udc = platform_get_drvdata(dev); ++ unsigned long flags; + + if (!udc->mach->gpio_pullup && !udc->mach->udc_command) + WARN("USB host won't detect disconnect!\n"); +- pullup(udc, 0); ++ udc->suspended = 1; ++ ++ local_irq_save(flags); ++ pullup(udc); ++ local_irq_restore(flags); + + return 0; + } +@@ -2326,8 +2338,12 @@ static int pxa2xx_udc_suspend(struct platform_device *dev, pm_message_t state) + static int pxa2xx_udc_resume(struct platform_device *dev) + { + struct pxa2xx_udc *udc = platform_get_drvdata(dev); ++ unsigned long flags; + +- pullup(udc, 1); ++ udc->suspended = 0; ++ local_irq_save(flags); ++ pullup(udc); ++ local_irq_restore(flags); + + return 0; + } +diff --git a/drivers/usb/gadget/pxa2xx_udc.h b/drivers/usb/gadget/pxa2xx_udc.h +index c08b1a2..93586b2 100644 +--- a/drivers/usb/gadget/pxa2xx_udc.h ++++ b/drivers/usb/gadget/pxa2xx_udc.h +@@ -119,7 +119,9 @@ struct pxa2xx_udc { + has_cfr : 1, + req_pending : 1, + req_std : 1, +- req_config : 1; ++ req_config : 1, ++ suspended : 1, ++ active : 1; + + #define start_watchdog(dev) mod_timer(&dev->timer, jiffies + (HZ/200)) + struct timer_list timer; +@@ -239,7 +241,7 @@ dump_state(struct pxa2xx_udc *dev) + dev->stats.read.bytes, dev->stats.read.ops); + + for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) { +- if (dev->ep [i].desc == 0) ++ if (dev->ep [i].desc == NULL) + continue; + DMSG ("udccs%d = %02x\n", i, *dev->ep->reg_udccs); + } +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0019-pxa-remove-periodic-mode-emulation-support.patch b/packages/linux/linux-rp-2.6.24/tosa/0019-pxa-remove-periodic-mode-emulation-support.patch new file mode 100644 index 0000000000..4b4107d655 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0019-pxa-remove-periodic-mode-emulation-support.patch @@ -0,0 +1,128 @@ +From bda65817167cce5294e1d84670f36815262ed550 Mon Sep 17 00:00:00 2001 +From: Russell King <rmk@dyn-67.arm.linux.org.uk> +Date: Sun, 3 Feb 2008 21:58:12 +0300 +Subject: [PATCH 19/64] pxa: remove periodic mode emulation support + +Apparantly, the generic time subsystem can accurately emulate periodic +mode via the one-shot support code, so we don't need our own periodic +emulation code anymore. Just ensure that we build support for one shot +into the generic time subsystem. + +Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> +--- + arch/arm/Kconfig | 1 + + arch/arm/mach-pxa/time.c | 61 ++++++---------------------------------------- + 2 files changed, 9 insertions(+), 53 deletions(-) + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index a04f507..1be7182 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -345,6 +345,7 @@ config ARCH_PXA + select GENERIC_GPIO + select GENERIC_TIME + select GENERIC_CLOCKEVENTS ++ select TICK_ONESHOT + help + Support for Intel/Marvell's PXA2xx/PXA3xx processor line. + +diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c +index fbfa192..3c4abbf 100644 +--- a/arch/arm/mach-pxa/time.c ++++ b/arch/arm/mach-pxa/time.c +@@ -59,55 +59,17 @@ unsigned long long sched_clock(void) + } + + ++#define MIN_OSCR_DELTA 16 ++ + static irqreturn_t + pxa_ost0_interrupt(int irq, void *dev_id) + { +- int next_match; + struct clock_event_device *c = dev_id; + +- if (c->mode == CLOCK_EVT_MODE_ONESHOT) { +- /* Disarm the compare/match, signal the event. */ +- OIER &= ~OIER_E0; +- OSSR = OSSR_M0; +- c->event_handler(c); +- } else if (c->mode == CLOCK_EVT_MODE_PERIODIC) { +- /* Call the event handler as many times as necessary +- * to recover missed events, if any (if we update +- * OSMR0 and OSCR0 is still ahead of us, we've missed +- * the event). As we're dealing with that, re-arm the +- * compare/match for the next event. +- * +- * HACK ALERT: +- * +- * There's a latency between the instruction that +- * writes to OSMR0 and the actual commit to the +- * physical hardware, because the CPU doesn't (have +- * to) run at bus speed, there's a write buffer +- * between the CPU and the bus, etc. etc. So if the +- * target OSCR0 is "very close", to the OSMR0 load +- * value, the update to OSMR0 might not get to the +- * hardware in time and we'll miss that interrupt. +- * +- * To be safe, if the new OSMR0 is "very close" to the +- * target OSCR0 value, we call the event_handler as +- * though the event actually happened. According to +- * Nico's comment in the previous version of this +- * code, experience has shown that 6 OSCR ticks is +- * "very close" but he went with 8. We will use 16, +- * based on the results of testing on PXA270. +- * +- * To be doubly sure, we also tell clkevt via +- * clockevents_register_device() not to ask for +- * anything that might put us "very close". +- */ +-#define MIN_OSCR_DELTA 16 +- do { +- OSSR = OSSR_M0; +- next_match = (OSMR0 += LATCH); +- c->event_handler(c); +- } while (((signed long)(next_match - OSCR) <= MIN_OSCR_DELTA) +- && (c->mode == CLOCK_EVT_MODE_PERIODIC)); +- } ++ /* Disarm the compare/match, signal the event. */ ++ OIER &= ~OIER_E0; ++ OSSR = OSSR_M0; ++ c->event_handler(c); + + return IRQ_HANDLED; + } +@@ -133,14 +95,6 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev) + unsigned long irqflags; + + switch (mode) { +- case CLOCK_EVT_MODE_PERIODIC: +- raw_local_irq_save(irqflags); +- OSSR = OSSR_M0; +- OIER |= OIER_E0; +- OSMR0 = OSCR + LATCH; +- raw_local_irq_restore(irqflags); +- break; +- + case CLOCK_EVT_MODE_ONESHOT: + raw_local_irq_save(irqflags); + OIER &= ~OIER_E0; +@@ -158,13 +112,14 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev) + break; + + case CLOCK_EVT_MODE_RESUME: ++ case CLOCK_EVT_MODE_PERIODIC: + break; + } + } + + static struct clock_event_device ckevt_pxa_osmr0 = { + .name = "osmr0", +- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, ++ .features = CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .rating = 200, + .cpumask = CPU_MASK_CPU0, +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0020-Provide-dew-device-clock-backports-from-2.6.24-git.patch b/packages/linux/linux-rp-2.6.24/tosa/0020-Provide-dew-device-clock-backports-from-2.6.24-git.patch new file mode 100644 index 0000000000..0a42bc5855 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0020-Provide-dew-device-clock-backports-from-2.6.24-git.patch @@ -0,0 +1,257 @@ +From ee8ca5742e0000dd2369ef4d328c2c1117276a3b Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Mon, 4 Feb 2008 02:56:28 +0300 +Subject: [PATCH 20/64] Provide dew device/clock backports from 2.6.24-git + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + arch/arm/Kconfig | 1 + + arch/arm/mach-pxa/devices.h | 12 ++++++++++++ + arch/arm/mach-pxa/pxa25x.c | 18 ++++++++++++------ + arch/arm/mach-pxa/pxa27x.c | 22 ++++++++++++++++------ + arch/arm/mach-pxa/pxa3xx.c | 30 ++++++++++++++++++++++++++++++ + kernel/Makefile | 1 + + 6 files changed, 72 insertions(+), 12 deletions(-) + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 1be7182..10faf9c 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -367,6 +367,7 @@ config ARCH_SA1100 + select ARCH_DISCONTIGMEM_ENABLE + select ARCH_MTD_XIP + select GENERIC_GPIO ++ select GENERIC_TIME + help + Support for StrongARM 11x0 based boards. + +diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h +index 94c8d5c..96c7c89 100644 +--- a/arch/arm/mach-pxa/devices.h ++++ b/arch/arm/mach-pxa/devices.h +@@ -1,4 +1,6 @@ + extern struct platform_device pxa_device_mci; ++extern struct platform_device pxa3xx_device_mci2; ++extern struct platform_device pxa3xx_device_mci3; + extern struct platform_device pxa_device_udc; + extern struct platform_device pxa_device_fb; + extern struct platform_device pxa_device_ffuart; +@@ -12,3 +14,13 @@ extern struct platform_device pxa_device_rtc; + + extern struct platform_device pxa27x_device_i2c_power; + extern struct platform_device pxa27x_device_ohci; ++ ++extern struct platform_device pxa25x_device_ssp; ++extern struct platform_device pxa25x_device_nssp; ++extern struct platform_device pxa25x_device_assp; ++extern struct platform_device pxa27x_device_ssp1; ++extern struct platform_device pxa27x_device_ssp2; ++extern struct platform_device pxa27x_device_ssp3; ++extern struct platform_device pxa3xx_device_ssp4; ++ ++void __init pxa_register_device(struct platform_device *dev, void *data); +diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c +index 006a6e0..5988d99 100644 +--- a/arch/arm/mach-pxa/pxa25x.c ++++ b/arch/arm/mach-pxa/pxa25x.c +@@ -123,12 +123,15 @@ static struct clk pxa25x_clks[] = { + INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev), + INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev), + INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev), ++ ++ INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev), ++ INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev), ++ INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev), ++ + /* + INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), + INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), +- INIT_CKEN("SSPCLK", SSP, 3686400, 0, NULL), + INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL), +- INIT_CKEN("NSSPCLK", NSSP, 3686400, 0, NULL), + */ + INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), + }; +@@ -216,8 +219,6 @@ static void pxa25x_cpu_pm_restore(unsigned long *sleep_save) + + static void pxa25x_cpu_pm_enter(suspend_state_t state) + { +- CKEN = 0; +- + switch (state) { + case PM_SUSPEND_MEM: + /* set resume return address */ +@@ -239,6 +240,8 @@ static void __init pxa25x_init_pm(void) + { + pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns; + } ++#else ++static inline void pxa25x_init_pm(void) {} + #endif + + /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm +@@ -300,6 +303,9 @@ static struct platform_device *pxa25x_devices[] __initdata = { + &pxa_device_i2s, + &pxa_device_ficp, + &pxa_device_rtc, ++ &pxa25x_device_ssp, ++ &pxa25x_device_nssp, ++ &pxa25x_device_assp, + }; + + static int __init pxa25x_init(void) +@@ -315,9 +321,9 @@ static int __init pxa25x_init(void) + + if ((ret = pxa_init_dma(16))) + return ret; +-#ifdef CONFIG_PM ++ + pxa25x_init_pm(); +-#endif ++ + ret = platform_add_devices(pxa25x_devices, + ARRAY_SIZE(pxa25x_devices)); + } +diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c +index 8e126e6..30ca4fd 100644 +--- a/arch/arm/mach-pxa/pxa27x.c ++++ b/arch/arm/mach-pxa/pxa27x.c +@@ -150,11 +150,12 @@ static struct clk pxa27x_clks[] = { + INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev), + INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL), + ++ INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), ++ INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), ++ INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), ++ + /* + INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL), +- INIT_CKEN("SSPCLK", SSP1, 13000000, 0, NULL), +- INIT_CKEN("SSPCLK", SSP2, 13000000, 0, NULL), +- INIT_CKEN("SSPCLK", SSP3, 13000000, 0, NULL), + INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL), + INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL), + INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL), +@@ -304,6 +305,8 @@ static void __init pxa27x_init_pm(void) + { + pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns; + } ++#else ++static inline void pxa27x_init_pm(void) {} + #endif + + /* PXA27x: Various gpios can issue wakeup events. This logic only +@@ -423,6 +426,11 @@ struct platform_device pxa27x_device_i2c_power = { + .num_resources = ARRAY_SIZE(i2c_power_resources), + }; + ++void __init pxa_set_i2c_power_info(struct i2c_pxa_platform_data *info) ++{ ++ pxa27x_device_i2c_power.dev.platform_data = info; ++} ++ + static struct platform_device *devices[] __initdata = { + &pxa_device_mci, + &pxa_device_udc, +@@ -435,7 +443,9 @@ static struct platform_device *devices[] __initdata = { + &pxa_device_ficp, + &pxa_device_rtc, + &pxa27x_device_i2c_power, +- &pxa27x_device_ohci, ++ &pxa27x_device_ssp1, ++ &pxa27x_device_ssp2, ++ &pxa27x_device_ssp3, + }; + + static int __init pxa27x_init(void) +@@ -446,9 +456,9 @@ static int __init pxa27x_init(void) + + if ((ret = pxa_init_dma(32))) + return ret; +-#ifdef CONFIG_PM ++ + pxa27x_init_pm(); +-#endif ++ + ret = platform_add_devices(devices, ARRAY_SIZE(devices)); + } + return ret; +diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c +index 61d9c9d..ccab9da 100644 +--- a/arch/arm/mach-pxa/pxa3xx.c ++++ b/arch/arm/mach-pxa/pxa3xx.c +@@ -189,8 +189,31 @@ static struct clk pxa3xx_clks[] = { + + PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), + PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev), ++ PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev), ++ ++ PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), ++ PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), ++ PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), ++ PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev), ++ ++ PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev), ++ PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev), ++ PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev), + }; + ++#ifdef CONFIG_PM ++#define SLEEP_SAVE_SIZE 4 ++ ++#define ISRAM_START 0x5c000000 ++#define ISRAM_SIZE SZ_256K ++ ++static inline void pxa3xx_init_pm(void) {} ++static inline void pxa3xx_init_irq_pm(void) {} ++#else ++static inline void pxa3xx_init_pm(void) {} ++static inline void pxa3xx_init_irq_pm(void) {} ++#endif ++ + void __init pxa3xx_init_irq(void) + { + /* enable CP6 access */ +@@ -202,6 +225,7 @@ void __init pxa3xx_init_irq(void) + pxa_init_irq_low(); + pxa_init_irq_high(); + pxa_init_irq_gpio(128); ++ pxa3xx_init_irq_pm(); + } + + /* +@@ -219,6 +243,10 @@ static struct platform_device *devices[] __initdata = { + &pxa_device_i2s, + &pxa_device_ficp, + &pxa_device_rtc, ++ &pxa27x_device_ssp1, ++ &pxa27x_device_ssp2, ++ &pxa27x_device_ssp3, ++ &pxa3xx_device_ssp4, + }; + + static int __init pxa3xx_init(void) +@@ -231,6 +259,8 @@ static int __init pxa3xx_init(void) + if ((ret = pxa_init_dma(32))) + return ret; + ++ pxa3xx_init_pm(); ++ + return platform_add_devices(devices, ARRAY_SIZE(devices)); + } + return 0; +diff --git a/kernel/Makefile b/kernel/Makefile +index dfa9695..6d9a87c 100644 +--- a/kernel/Makefile ++++ b/kernel/Makefile +@@ -57,6 +57,7 @@ obj-$(CONFIG_SYSCTL) += utsname_sysctl.o + obj-$(CONFIG_TASK_DELAY_ACCT) += delayacct.o + obj-$(CONFIG_TASKSTATS) += taskstats.o tsacct.o + obj-$(CONFIG_MARKERS) += marker.o ++obj-$(CONFIG_LATENCYTOP) += latencytop.o + + ifneq ($(CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER),y) + # According to Alan Modra <alan@linuxcare.com.au>, the -fno-omit-frame-pointer is +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0021-Add-an-empty-drivers-gpio-directory-for-gpiolib-infr.patch b/packages/linux/linux-rp-2.6.24/tosa/0021-Add-an-empty-drivers-gpio-directory-for-gpiolib-infr.patch new file mode 100644 index 0000000000..3f8512128a --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0021-Add-an-empty-drivers-gpio-directory-for-gpiolib-infr.patch @@ -0,0 +1,121 @@ +From b77665c545bc260d2b93add129413e4a724d7e6e Mon Sep 17 00:00:00 2001 +From: David Brownell <dbrownell@users.sourceforge.net> +Date: Fri, 18 Jan 2008 00:35:00 +0300 +Subject: [PATCH 21/64] Add an empty drivers/gpio directory for gpiolib infrastructure and GPIO + expanders. It will be populated by later patches. + +This won't be the only place to hold such gpio_chip code. Many external chips +add a few GPIOs as secondary functionality (such as MFD drivers) and platform +code frequently needs to closely integrate GPIO and IRQ support. + +This is placed *early* in the build/link sequence since it's common for other +drivers to depend on GPIOs to do their work, so they must be initialized early +in the device_initcall() sequence. + +Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> +Acked-by: Jean Delvare <khali@linux-fr.org> +Cc: Eric Miao <eric.miao@marvell.com> +Cc: Sam Ravnborg <sam@ravnborg.org> +Cc: Haavard Skinnemoen <hskinnemoen@atmel.com> +Cc: Philipp Zabel <philipp.zabel@gmail.com> +Cc: Russell King <rmk@arm.linux.org.uk> +Cc: Ben Gardner <bgardner@wabtec.com> +Signed-off-by: Andrew Morton <akpm@linux-foundation.org> +--- + arch/arm/Kconfig | 2 ++ + drivers/Kconfig | 2 ++ + drivers/Makefile | 1 + + drivers/gpio/Kconfig | 32 ++++++++++++++++++++++++++++++++ + drivers/gpio/Makefile | 3 +++ + 5 files changed, 40 insertions(+), 0 deletions(-) + create mode 100644 drivers/gpio/Kconfig + create mode 100644 drivers/gpio/Makefile + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 10faf9c..06ca241 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -1042,6 +1042,8 @@ source "drivers/i2c/Kconfig" + + source "drivers/spi/Kconfig" + ++source "drivers/gpio/Kconfig" ++ + source "drivers/w1/Kconfig" + + source "drivers/power/Kconfig" +diff --git a/drivers/Kconfig b/drivers/Kconfig +index f4076d9..90e295a 100644 +--- a/drivers/Kconfig ++++ b/drivers/Kconfig +@@ -52,6 +52,8 @@ source "drivers/i2c/Kconfig" + + source "drivers/spi/Kconfig" + ++source "drivers/gpio/Kconfig" ++ + source "drivers/w1/Kconfig" + + source "drivers/power/Kconfig" +diff --git a/drivers/Makefile b/drivers/Makefile +index 8cb37e3..8e5101f 100644 +--- a/drivers/Makefile ++++ b/drivers/Makefile +@@ -5,6 +5,7 @@ + # Rewritten to use lists instead of if-statements. + # + ++obj-$(CONFIG_HAVE_GPIO_LIB) += gpio/ + obj-$(CONFIG_PCI) += pci/ + obj-$(CONFIG_PARISC) += parisc/ + obj-$(CONFIG_RAPIDIO) += rapidio/ +diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig +new file mode 100644 +index 0000000..560687c +--- /dev/null ++++ b/drivers/gpio/Kconfig +@@ -0,0 +1,32 @@ ++# ++# GPIO infrastructure and expanders ++# ++ ++config HAVE_GPIO_LIB ++ bool ++ help ++ Platforms select gpiolib if they use this infrastructure ++ for all their GPIOs, usually starting with ones integrated ++ into SOC processors. ++ ++menu "GPIO Support" ++ depends on HAVE_GPIO_LIB ++ ++config DEBUG_GPIO ++ bool "Debug GPIO calls" ++ depends on DEBUG_KERNEL ++ help ++ Say Y here to add some extra checks and diagnostics to GPIO calls. ++ The checks help ensure that GPIOs have been properly initialized ++ before they are used and that sleeping calls aren not made from ++ nonsleeping contexts. They can make bitbanged serial protocols ++ slower. The diagnostics help catch the type of setup errors ++ that are most common when setting up new platforms or boards. ++ ++# put expanders in the right section, in alphabetical order ++ ++comment "I2C GPIO expanders:" ++ ++comment "SPI GPIO expanders:" ++ ++endmenu +diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile +new file mode 100644 +index 0000000..cdbba6b +--- /dev/null ++++ b/drivers/gpio/Makefile +@@ -0,0 +1,3 @@ ++# gpio support: dedicated expander chips, etc ++ ++ccflags-$(CONFIG_DEBUG_GPIO) += -DDEBUG +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0022-Provide-new-implementation-infrastructure-that-platf.patch b/packages/linux/linux-rp-2.6.24/tosa/0022-Provide-new-implementation-infrastructure-that-platf.patch new file mode 100644 index 0000000000..f39fedbbaa --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0022-Provide-new-implementation-infrastructure-that-platf.patch @@ -0,0 +1,746 @@ +From 3a0251c01446f3a6763e4406ca5495102db63aa4 Mon Sep 17 00:00:00 2001 +From: David Brownell <dbrownell@users.sourceforge.net> +Date: Fri, 18 Jan 2008 00:35:20 +0300 +Subject: [PATCH 22/64] Provide new implementation infrastructure that platforms may choose to use + when implementing the GPIO programming interface. Platforms can update their + GPIO support to use this. In many cases the incremental cost to access a + non-inlined GPIO should be less than a dozen instructions, with the memory + cost being about a page (total) of extra data and code. The upside is: + + * Providing two features which were "want to have (but OK to defer)" when + GPIO interfaces were first discussed in November 2006: + + - A "struct gpio_chip" to plug in GPIOs that aren't directly supported + by SOC platforms, but come from FPGAs or other multifunction devices + using conventional device registers (like UCB-1x00 or SM501 GPIOs, + and southbridges in PCs with more open specs than usual). + + - Full support for message-based GPIO expanders, where registers are + accessed through sleeping I/O calls. Previous support for these + "cansleep" calls was just stubs. (One example: the widely used + pcf8574 I2C chips, with 8 GPIOs each.) + + * Including a non-stub implementation of the gpio_{request,free}() calls, + making those calls much more useful. The diagnostic labels are also + recorded given DEBUG_FS, so /sys/kernel/debug/gpio can show a snapshot + of all GPIOs known to this infrastructure. + +The driver programming interfaces introduced in 2.6.21 do not change at all; +this infrastructure is entirely below those covers. + +Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> +Cc: Sam Ravnborg <sam@ravnborg.org> +Cc: Jean Delvare <khali@linux-fr.org> +Cc: Eric Miao <eric.miao@marvell.com> +Cc: Haavard Skinnemoen <hskinnemoen@atmel.com> +Cc: Philipp Zabel <philipp.zabel@gmail.com> +Cc: Russell King <rmk@arm.linux.org.uk> +Cc: Ben Gardner <bgardner@wabtec.com> +Signed-off-by: Andrew Morton <akpm@linux-foundation.org> +--- + drivers/gpio/Makefile | 2 + + drivers/gpio/gpiolib.c | 567 ++++++++++++++++++++++++++++++++++++++++++++ + include/asm-generic/gpio.h | 98 ++++++++ + 3 files changed, 667 insertions(+), 0 deletions(-) + create mode 100644 drivers/gpio/gpiolib.c + +diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile +index cdbba6b..2db28ce 100644 +--- a/drivers/gpio/Makefile ++++ b/drivers/gpio/Makefile +@@ -1,3 +1,5 @@ + # gpio support: dedicated expander chips, etc + + ccflags-$(CONFIG_DEBUG_GPIO) += -DDEBUG ++ ++obj-$(CONFIG_HAVE_GPIO_LIB) += gpiolib.o +diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c +new file mode 100644 +index 0000000..d8db2f8 +--- /dev/null ++++ b/drivers/gpio/gpiolib.c +@@ -0,0 +1,567 @@ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/irq.h> ++#include <linux/spinlock.h> ++ ++#include <asm/gpio.h> ++ ++ ++/* Optional implementation infrastructure for GPIO interfaces. ++ * ++ * Platforms may want to use this if they tend to use very many GPIOs ++ * that aren't part of a System-On-Chip core; or across I2C/SPI/etc. ++ * ++ * When kernel footprint or instruction count is an issue, simpler ++ * implementations may be preferred. The GPIO programming interface ++ * allows for inlining speed-critical get/set operations for common ++ * cases, so that access to SOC-integrated GPIOs can sometimes cost ++ * only an instruction or two per bit. ++ */ ++ ++ ++/* When debugging, extend minimal trust to callers and platform code. ++ * Also emit diagnostic messages that may help initial bringup, when ++ * board setup or driver bugs are most common. ++ * ++ * Otherwise, minimize overhead in what may be bitbanging codepaths. ++ */ ++#ifdef DEBUG ++#define extra_checks 1 ++#else ++#define extra_checks 0 ++#endif ++ ++/* gpio_lock prevents conflicts during gpio_desc[] table updates. ++ * While any GPIO is requested, its gpio_chip is not removable; ++ * each GPIO's "requested" flag serves as a lock and refcount. ++ */ ++static DEFINE_SPINLOCK(gpio_lock); ++ ++struct gpio_desc { ++ struct gpio_chip *chip; ++ unsigned long flags; ++/* flag symbols are bit numbers */ ++#define FLAG_REQUESTED 0 ++#define FLAG_IS_OUT 1 ++ ++#ifdef CONFIG_DEBUG_FS ++ const char *label; ++#endif ++}; ++static struct gpio_desc gpio_desc[ARCH_NR_GPIOS]; ++ ++static inline void desc_set_label(struct gpio_desc *d, const char *label) ++{ ++#ifdef CONFIG_DEBUG_FS ++ d->label = label; ++#endif ++} ++ ++/* Warn when drivers omit gpio_request() calls -- legal but ill-advised ++ * when setting direction, and otherwise illegal. Until board setup code ++ * and drivers use explicit requests everywhere (which won't happen when ++ * those calls have no teeth) we can't avoid autorequesting. This nag ++ * message should motivate switching to explicit requests... ++ */ ++static void gpio_ensure_requested(struct gpio_desc *desc) ++{ ++ if (test_and_set_bit(FLAG_REQUESTED, &desc->flags) == 0) { ++ pr_warning("GPIO-%d autorequested\n", (int)(desc - gpio_desc)); ++ desc_set_label(desc, "[auto]"); ++ } ++} ++ ++/* caller holds gpio_lock *OR* gpio is marked as requested */ ++static inline struct gpio_chip *gpio_to_chip(unsigned gpio) ++{ ++ return gpio_desc[gpio].chip; ++} ++ ++/** ++ * gpiochip_add() - register a gpio_chip ++ * @chip: the chip to register, with chip->base initialized ++ * Context: potentially before irqs or kmalloc will work ++ * ++ * Returns a negative errno if the chip can't be registered, such as ++ * because the chip->base is invalid or already associated with a ++ * different chip. Otherwise it returns zero as a success code. ++ */ ++int gpiochip_add(struct gpio_chip *chip) ++{ ++ unsigned long flags; ++ int status = 0; ++ unsigned id; ++ ++ /* NOTE chip->base negative is reserved to mean a request for ++ * dynamic allocation. We don't currently support that. ++ */ ++ ++ if (chip->base < 0 || (chip->base + chip->ngpio) >= ARCH_NR_GPIOS) { ++ status = -EINVAL; ++ goto fail; ++ } ++ ++ spin_lock_irqsave(&gpio_lock, flags); ++ ++ /* these GPIO numbers must not be managed by another gpio_chip */ ++ for (id = chip->base; id < chip->base + chip->ngpio; id++) { ++ if (gpio_desc[id].chip != NULL) { ++ status = -EBUSY; ++ break; ++ } ++ } ++ if (status == 0) { ++ for (id = chip->base; id < chip->base + chip->ngpio; id++) { ++ gpio_desc[id].chip = chip; ++ gpio_desc[id].flags = 0; ++ } ++ } ++ ++ spin_unlock_irqrestore(&gpio_lock, flags); ++fail: ++ /* failures here can mean systems won't boot... */ ++ if (status) ++ pr_err("gpiochip_add: gpios %d..%d (%s) not registered\n", ++ chip->base, chip->base + chip->ngpio, ++ chip->label ? : "generic"); ++ return status; ++} ++EXPORT_SYMBOL_GPL(gpiochip_add); ++ ++/** ++ * gpiochip_remove() - unregister a gpio_chip ++ * @chip: the chip to unregister ++ * ++ * A gpio_chip with any GPIOs still requested may not be removed. ++ */ ++int gpiochip_remove(struct gpio_chip *chip) ++{ ++ unsigned long flags; ++ int status = 0; ++ unsigned id; ++ ++ spin_lock_irqsave(&gpio_lock, flags); ++ ++ for (id = chip->base; id < chip->base + chip->ngpio; id++) { ++ if (test_bit(FLAG_REQUESTED, &gpio_desc[id].flags)) { ++ status = -EBUSY; ++ break; ++ } ++ } ++ if (status == 0) { ++ for (id = chip->base; id < chip->base + chip->ngpio; id++) ++ gpio_desc[id].chip = NULL; ++ } ++ ++ spin_unlock_irqrestore(&gpio_lock, flags); ++ return status; ++} ++EXPORT_SYMBOL_GPL(gpiochip_remove); ++ ++ ++/* These "optional" allocation calls help prevent drivers from stomping ++ * on each other, and help provide better diagnostics in debugfs. ++ * They're called even less than the "set direction" calls. ++ */ ++int gpio_request(unsigned gpio, const char *label) ++{ ++ struct gpio_desc *desc; ++ int status = -EINVAL; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&gpio_lock, flags); ++ ++ if (gpio >= ARCH_NR_GPIOS) ++ goto done; ++ desc = &gpio_desc[gpio]; ++ if (desc->chip == NULL) ++ goto done; ++ ++ /* NOTE: gpio_request() can be called in early boot, ++ * before IRQs are enabled. ++ */ ++ ++ if (test_and_set_bit(FLAG_REQUESTED, &desc->flags) == 0) { ++ desc_set_label(desc, label ? : "?"); ++ status = 0; ++ } else ++ status = -EBUSY; ++ ++done: ++ if (status) ++ pr_debug("gpio_request: gpio-%d (%s) status %d\n", ++ gpio, label ? : "?", status); ++ spin_unlock_irqrestore(&gpio_lock, flags); ++ return status; ++} ++EXPORT_SYMBOL_GPL(gpio_request); ++ ++void gpio_free(unsigned gpio) ++{ ++ unsigned long flags; ++ struct gpio_desc *desc; ++ ++ if (gpio >= ARCH_NR_GPIOS) { ++ WARN_ON(extra_checks); ++ return; ++ } ++ ++ spin_lock_irqsave(&gpio_lock, flags); ++ ++ desc = &gpio_desc[gpio]; ++ if (desc->chip && test_and_clear_bit(FLAG_REQUESTED, &desc->flags)) ++ desc_set_label(desc, NULL); ++ else ++ WARN_ON(extra_checks); ++ ++ spin_unlock_irqrestore(&gpio_lock, flags); ++} ++EXPORT_SYMBOL_GPL(gpio_free); ++ ++ ++/** ++ * gpiochip_is_requested - return string iff signal was requested ++ * @chip: controller managing the signal ++ * @offset: of signal within controller's 0..(ngpio - 1) range ++ * ++ * Returns NULL if the GPIO is not currently requested, else a string. ++ * If debugfs support is enabled, the string returned is the label passed ++ * to gpio_request(); otherwise it is a meaningless constant. ++ * ++ * This function is for use by GPIO controller drivers. The label can ++ * help with diagnostics, and knowing that the signal is used as a GPIO ++ * can help avoid accidentally multiplexing it to another controller. ++ */ ++const char *gpiochip_is_requested(struct gpio_chip *chip, unsigned offset) ++{ ++ unsigned gpio = chip->base + offset; ++ ++ if (gpio >= ARCH_NR_GPIOS || gpio_desc[gpio].chip != chip) ++ return NULL; ++ if (test_bit(FLAG_REQUESTED, &gpio_desc[gpio].flags) == 0) ++ return NULL; ++#ifdef CONFIG_DEBUG_FS ++ return gpio_desc[gpio].label; ++#else ++ return "?"; ++#endif ++} ++EXPORT_SYMBOL_GPL(gpiochip_is_requested); ++ ++ ++/* Drivers MUST set GPIO direction before making get/set calls. In ++ * some cases this is done in early boot, before IRQs are enabled. ++ * ++ * As a rule these aren't called more than once (except for drivers ++ * using the open-drain emulation idiom) so these are natural places ++ * to accumulate extra debugging checks. Note that we can't (yet) ++ * rely on gpio_request() having been called beforehand. ++ */ ++ ++int gpio_direction_input(unsigned gpio) ++{ ++ unsigned long flags; ++ struct gpio_chip *chip; ++ struct gpio_desc *desc = &gpio_desc[gpio]; ++ int status = -EINVAL; ++ ++ spin_lock_irqsave(&gpio_lock, flags); ++ ++ if (gpio >= ARCH_NR_GPIOS) ++ goto fail; ++ chip = desc->chip; ++ if (!chip || !chip->get || !chip->direction_input) ++ goto fail; ++ gpio -= chip->base; ++ if (gpio >= chip->ngpio) ++ goto fail; ++ gpio_ensure_requested(desc); ++ ++ /* now we know the gpio is valid and chip won't vanish */ ++ ++ spin_unlock_irqrestore(&gpio_lock, flags); ++ ++ might_sleep_if(extra_checks && chip->can_sleep); ++ ++ status = chip->direction_input(chip, gpio); ++ if (status == 0) ++ clear_bit(FLAG_IS_OUT, &desc->flags); ++ return status; ++fail: ++ spin_unlock_irqrestore(&gpio_lock, flags); ++ if (status) ++ pr_debug("%s: gpio-%d status %d\n", ++ __FUNCTION__, gpio, status); ++ return status; ++} ++EXPORT_SYMBOL_GPL(gpio_direction_input); ++ ++int gpio_direction_output(unsigned gpio, int value) ++{ ++ unsigned long flags; ++ struct gpio_chip *chip; ++ struct gpio_desc *desc = &gpio_desc[gpio]; ++ int status = -EINVAL; ++ ++ spin_lock_irqsave(&gpio_lock, flags); ++ ++ if (gpio >= ARCH_NR_GPIOS) ++ goto fail; ++ chip = desc->chip; ++ if (!chip || !chip->set || !chip->direction_output) ++ goto fail; ++ gpio -= chip->base; ++ if (gpio >= chip->ngpio) ++ goto fail; ++ gpio_ensure_requested(desc); ++ ++ /* now we know the gpio is valid and chip won't vanish */ ++ ++ spin_unlock_irqrestore(&gpio_lock, flags); ++ ++ might_sleep_if(extra_checks && chip->can_sleep); ++ ++ status = chip->direction_output(chip, gpio, value); ++ if (status == 0) ++ set_bit(FLAG_IS_OUT, &desc->flags); ++ return status; ++fail: ++ spin_unlock_irqrestore(&gpio_lock, flags); ++ if (status) ++ pr_debug("%s: gpio-%d status %d\n", ++ __FUNCTION__, gpio, status); ++ return status; ++} ++EXPORT_SYMBOL_GPL(gpio_direction_output); ++ ++ ++/* I/O calls are only valid after configuration completed; the relevant ++ * "is this a valid GPIO" error checks should already have been done. ++ * ++ * "Get" operations are often inlinable as reading a pin value register, ++ * and masking the relevant bit in that register. ++ * ++ * When "set" operations are inlinable, they involve writing that mask to ++ * one register to set a low value, or a different register to set it high. ++ * Otherwise locking is needed, so there may be little value to inlining. ++ * ++ *------------------------------------------------------------------------ ++ * ++ * IMPORTANT!!! The hot paths -- get/set value -- assume that callers ++ * have requested the GPIO. That can include implicit requesting by ++ * a direction setting call. Marking a gpio as requested locks its chip ++ * in memory, guaranteeing that these table lookups need no more locking ++ * and that gpiochip_remove() will fail. ++ * ++ * REVISIT when debugging, consider adding some instrumentation to ensure ++ * that the GPIO was actually requested. ++ */ ++ ++/** ++ * __gpio_get_value() - return a gpio's value ++ * @gpio: gpio whose value will be returned ++ * Context: any ++ * ++ * This is used directly or indirectly to implement gpio_get_value(). ++ * It returns the zero or nonzero value provided by the associated ++ * gpio_chip.get() method; or zero if no such method is provided. ++ */ ++int __gpio_get_value(unsigned gpio) ++{ ++ struct gpio_chip *chip; ++ ++ chip = gpio_to_chip(gpio); ++ WARN_ON(extra_checks && chip->can_sleep); ++ return chip->get ? chip->get(chip, gpio - chip->base) : 0; ++} ++EXPORT_SYMBOL_GPL(__gpio_get_value); ++ ++/** ++ * __gpio_set_value() - assign a gpio's value ++ * @gpio: gpio whose value will be assigned ++ * @value: value to assign ++ * Context: any ++ * ++ * This is used directly or indirectly to implement gpio_set_value(). ++ * It invokes the associated gpio_chip.set() method. ++ */ ++void __gpio_set_value(unsigned gpio, int value) ++{ ++ struct gpio_chip *chip; ++ ++ chip = gpio_to_chip(gpio); ++ WARN_ON(extra_checks && chip->can_sleep); ++ chip->set(chip, gpio - chip->base, value); ++} ++EXPORT_SYMBOL_GPL(__gpio_set_value); ++ ++/** ++ * __gpio_cansleep() - report whether gpio value access will sleep ++ * @gpio: gpio in question ++ * Context: any ++ * ++ * This is used directly or indirectly to implement gpio_cansleep(). It ++ * returns nonzero if access reading or writing the GPIO value can sleep. ++ */ ++int __gpio_cansleep(unsigned gpio) ++{ ++ struct gpio_chip *chip; ++ ++ /* only call this on GPIOs that are valid! */ ++ chip = gpio_to_chip(gpio); ++ ++ return chip->can_sleep; ++} ++EXPORT_SYMBOL_GPL(__gpio_cansleep); ++ ++ ++ ++/* There's no value in making it easy to inline GPIO calls that may sleep. ++ * Common examples include ones connected to I2C or SPI chips. ++ */ ++ ++int gpio_get_value_cansleep(unsigned gpio) ++{ ++ struct gpio_chip *chip; ++ ++ might_sleep_if(extra_checks); ++ chip = gpio_to_chip(gpio); ++ return chip->get(chip, gpio - chip->base); ++} ++EXPORT_SYMBOL_GPL(gpio_get_value_cansleep); ++ ++void gpio_set_value_cansleep(unsigned gpio, int value) ++{ ++ struct gpio_chip *chip; ++ ++ might_sleep_if(extra_checks); ++ chip = gpio_to_chip(gpio); ++ chip->set(chip, gpio - chip->base, value); ++} ++EXPORT_SYMBOL_GPL(gpio_set_value_cansleep); ++ ++ ++#ifdef CONFIG_DEBUG_FS ++ ++#include <linux/debugfs.h> ++#include <linux/seq_file.h> ++ ++ ++static void gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip) ++{ ++ unsigned i; ++ unsigned gpio = chip->base; ++ struct gpio_desc *gdesc = &gpio_desc[gpio]; ++ int is_out; ++ ++ for (i = 0; i < chip->ngpio; i++, gpio++, gdesc++) { ++ if (!test_bit(FLAG_REQUESTED, &gdesc->flags)) ++ continue; ++ ++ is_out = test_bit(FLAG_IS_OUT, &gdesc->flags); ++ seq_printf(s, " gpio-%-3d (%-12s) %s %s", ++ gpio, gdesc->label, ++ is_out ? "out" : "in ", ++ chip->get ++ ? (chip->get(chip, i) ? "hi" : "lo") ++ : "? "); ++ ++ if (!is_out) { ++ int irq = gpio_to_irq(gpio); ++ struct irq_desc *desc = irq_desc + irq; ++ ++ /* This races with request_irq(), set_irq_type(), ++ * and set_irq_wake() ... but those are "rare". ++ * ++ * More significantly, trigger type flags aren't ++ * currently maintained by genirq. ++ */ ++ if (irq >= 0 && desc->action) { ++ char *trigger; ++ ++ switch (desc->status & IRQ_TYPE_SENSE_MASK) { ++ case IRQ_TYPE_NONE: ++ trigger = "(default)"; ++ break; ++ case IRQ_TYPE_EDGE_FALLING: ++ trigger = "edge-falling"; ++ break; ++ case IRQ_TYPE_EDGE_RISING: ++ trigger = "edge-rising"; ++ break; ++ case IRQ_TYPE_EDGE_BOTH: ++ trigger = "edge-both"; ++ break; ++ case IRQ_TYPE_LEVEL_HIGH: ++ trigger = "level-high"; ++ break; ++ case IRQ_TYPE_LEVEL_LOW: ++ trigger = "level-low"; ++ break; ++ default: ++ trigger = "?trigger?"; ++ break; ++ } ++ ++ seq_printf(s, " irq-%d %s%s", ++ irq, trigger, ++ (desc->status & IRQ_WAKEUP) ++ ? " wakeup" : ""); ++ } ++ } ++ ++ seq_printf(s, "\n"); ++ } ++} ++ ++static int gpiolib_show(struct seq_file *s, void *unused) ++{ ++ struct gpio_chip *chip = NULL; ++ unsigned gpio; ++ int started = 0; ++ ++ /* REVISIT this isn't locked against gpio_chip removal ... */ ++ ++ for (gpio = 0; gpio < ARCH_NR_GPIOS; gpio++) { ++ if (chip == gpio_desc[gpio].chip) ++ continue; ++ chip = gpio_desc[gpio].chip; ++ if (!chip) ++ continue; ++ ++ seq_printf(s, "%sGPIOs %d-%d, %s%s:\n", ++ started ? "\n" : "", ++ chip->base, chip->base + chip->ngpio - 1, ++ chip->label ? : "generic", ++ chip->can_sleep ? ", can sleep" : ""); ++ started = 1; ++ if (chip->dbg_show) ++ chip->dbg_show(s, chip); ++ else ++ gpiolib_dbg_show(s, chip); ++ } ++ return 0; ++} ++ ++static int gpiolib_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, gpiolib_show, NULL); ++} ++ ++static struct file_operations gpiolib_operations = { ++ .open = gpiolib_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++static int __init gpiolib_debugfs_init(void) ++{ ++ /* /sys/kernel/debug/gpio */ ++ (void) debugfs_create_file("gpio", S_IFREG | S_IRUGO, ++ NULL, NULL, &gpiolib_operations); ++ return 0; ++} ++subsys_initcall(gpiolib_debugfs_init); ++ ++#endif /* DEBUG_FS */ +diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h +index 2d0aab1..f29a502 100644 +--- a/include/asm-generic/gpio.h ++++ b/include/asm-generic/gpio.h +@@ -1,6 +1,102 @@ + #ifndef _ASM_GENERIC_GPIO_H + #define _ASM_GENERIC_GPIO_H + ++#ifdef CONFIG_HAVE_GPIO_LIB ++ ++/* Platforms may implement their GPIO interface with library code, ++ * at a small performance cost for non-inlined operations and some ++ * extra memory (for code and for per-GPIO table entries). ++ * ++ * While the GPIO programming interface defines valid GPIO numbers ++ * to be in the range 0..MAX_INT, this library restricts them to the ++ * smaller range 0..ARCH_NR_GPIOS. ++ */ ++ ++#ifndef ARCH_NR_GPIOS ++#define ARCH_NR_GPIOS 256 ++#endif ++ ++struct seq_file; ++ ++/** ++ * struct gpio_chip - abstract a GPIO controller ++ * @label: for diagnostics ++ * @direction_input: configures signal "offset" as input, or returns error ++ * @get: returns value for signal "offset"; for output signals this ++ * returns either the value actually sensed, or zero ++ * @direction_output: configures signal "offset" as output, or returns error ++ * @set: assigns output value for signal "offset" ++ * @dbg_show: optional routine to show contents in debugfs; default code ++ * will be used when this is omitted, but custom code can show extra ++ * state (such as pullup/pulldown configuration). ++ * @base: identifies the first GPIO number handled by this chip; or, if ++ * negative during registration, requests dynamic ID allocation. ++ * @ngpio: the number of GPIOs handled by this controller; the last GPIO ++ * handled is (base + ngpio - 1). ++ * @can_sleep: flag must be set iff get()/set() methods sleep, as they ++ * must while accessing GPIO expander chips over I2C or SPI ++ * ++ * A gpio_chip can help platforms abstract various sources of GPIOs so ++ * they can all be accessed through a common programing interface. ++ * Example sources would be SOC controllers, FPGAs, multifunction ++ * chips, dedicated GPIO expanders, and so on. ++ * ++ * Each chip controls a number of signals, identified in method calls ++ * by "offset" values in the range 0..(@ngpio - 1). When those signals ++ * are referenced through calls like gpio_get_value(gpio), the offset ++ * is calculated by subtracting @base from the gpio number. ++ */ ++struct gpio_chip { ++ char *label; ++ ++ int (*direction_input)(struct gpio_chip *chip, ++ unsigned offset); ++ int (*get)(struct gpio_chip *chip, ++ unsigned offset); ++ int (*direction_output)(struct gpio_chip *chip, ++ unsigned offset, int value); ++ void (*set)(struct gpio_chip *chip, ++ unsigned offset, int value); ++ void (*dbg_show)(struct seq_file *s, ++ struct gpio_chip *chip); ++ int base; ++ u16 ngpio; ++ unsigned can_sleep:1; ++}; ++ ++extern const char *gpiochip_is_requested(struct gpio_chip *chip, ++ unsigned offset); ++ ++/* add/remove chips */ ++extern int gpiochip_add(struct gpio_chip *chip); ++extern int __must_check gpiochip_remove(struct gpio_chip *chip); ++ ++ ++/* Always use the library code for GPIO management calls, ++ * or when sleeping may be involved. ++ */ ++extern int gpio_request(unsigned gpio, const char *label); ++extern void gpio_free(unsigned gpio); ++ ++extern int gpio_direction_input(unsigned gpio); ++extern int gpio_direction_output(unsigned gpio, int value); ++ ++extern int gpio_get_value_cansleep(unsigned gpio); ++extern void gpio_set_value_cansleep(unsigned gpio, int value); ++ ++ ++/* A platform's <asm/gpio.h> code may want to inline the I/O calls when ++ * the GPIO is constant and refers to some always-present controller, ++ * giving direct access to chip registers and tight bitbanging loops. ++ */ ++extern int __gpio_get_value(unsigned gpio); ++extern void __gpio_set_value(unsigned gpio, int value); ++ ++extern int __gpio_cansleep(unsigned gpio); ++ ++ ++#else ++ + /* platforms that don't directly support access to GPIOs through I2C, SPI, + * or other blocking infrastructure can use these wrappers. + */ +@@ -22,4 +118,6 @@ static inline void gpio_set_value_cansleep(unsigned gpio, int value) + gpio_set_value(gpio, value); + } + ++#endif ++ + #endif /* _ASM_GENERIC_GPIO_H */ +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0023-This-adds-gpiolib-support-for-the-PXA-architecture.patch b/packages/linux/linux-rp-2.6.24/tosa/0023-This-adds-gpiolib-support-for-the-PXA-architecture.patch new file mode 100644 index 0000000000..7a37be85cf --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0023-This-adds-gpiolib-support-for-the-PXA-architecture.patch @@ -0,0 +1,498 @@ +From 49da9bd487e54164a75503e0037a054cce697ed5 Mon Sep 17 00:00:00 2001 +From: Philipp Zabel <philipp.zabel@gmail.com> +Date: Tue, 12 Feb 2008 04:38:12 +0300 +Subject: [PATCH 23/64] This adds gpiolib support for the PXA architecture: + - move all GPIO API functions from generic.c into gpio.c + - convert the gpio_get/set_value macros into inline functions + +This makes it easier to hook up GPIOs provided by external chips like +ASICs and CPLDs. + +Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> +Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> +Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> +Cc: Jean Delvare <khali@linux-fr.org> +Cc: Eric Miao <eric.miao@marvell.com> +Cc: Sam Ravnborg <sam@ravnborg.org> +Cc: Haavard Skinnemoen <hskinnemoen@atmel.com> +Cc: Ben Gardner <bgardner@wabtec.com> +Signed-off-by: Andrew Morton <akpm@linux-foundation.org> +--- + arch/arm/Kconfig | 1 + + arch/arm/mach-pxa/Makefile | 3 +- + arch/arm/mach-pxa/generic.c | 93 ---------------- + arch/arm/mach-pxa/generic.h | 1 + + arch/arm/mach-pxa/gpio.c | 197 +++++++++++++++++++++++++++++++++++ + arch/arm/mach-pxa/irq.c | 2 + + include/asm-arm/arch-pxa/gpio.h | 48 ++++----- + include/asm-arm/arch-pxa/pxa-regs.h | 13 +++ + 8 files changed, 236 insertions(+), 122 deletions(-) + create mode 100644 arch/arm/mach-pxa/gpio.c + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 06ca241..423e953 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -346,6 +346,7 @@ config ARCH_PXA + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select TICK_ONESHOT ++ select HAVE_GPIO_LIB + help + Support for Intel/Marvell's PXA2xx/PXA3xx processor line. + +diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile +index 4263527..5cb0216 100644 +--- a/arch/arm/mach-pxa/Makefile ++++ b/arch/arm/mach-pxa/Makefile +@@ -3,7 +3,8 @@ + # + + # Common support (must be linked before board specific support) +-obj-y += clock.o generic.o irq.o dma.o time.o ++obj-y += clock.o generic.o irq.o dma.o \ ++ time.o gpio.o + obj-$(CONFIG_PXA25x) += pxa25x.o + obj-$(CONFIG_PXA27x) += pxa27x.o + obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o +diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c +index 1c34946..6c07292 100644 +--- a/arch/arm/mach-pxa/generic.c ++++ b/arch/arm/mach-pxa/generic.c +@@ -32,7 +32,6 @@ + #include <asm/mach/map.h> + + #include <asm/arch/pxa-regs.h> +-#include <asm/arch/gpio.h> + #include <asm/arch/udc.h> + #include <asm/arch/pxafb.h> + #include <asm/arch/mmc.h> +@@ -73,97 +72,6 @@ unsigned int get_memclk_frequency_10khz(void) + EXPORT_SYMBOL(get_memclk_frequency_10khz); + + /* +- * Handy function to set GPIO alternate functions +- */ +-int pxa_last_gpio; +- +-int pxa_gpio_mode(int gpio_mode) +-{ +- unsigned long flags; +- int gpio = gpio_mode & GPIO_MD_MASK_NR; +- int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; +- int gafr; +- +- if (gpio > pxa_last_gpio) +- return -EINVAL; +- +- local_irq_save(flags); +- if (gpio_mode & GPIO_DFLT_LOW) +- GPCR(gpio) = GPIO_bit(gpio); +- else if (gpio_mode & GPIO_DFLT_HIGH) +- GPSR(gpio) = GPIO_bit(gpio); +- if (gpio_mode & GPIO_MD_MASK_DIR) +- GPDR(gpio) |= GPIO_bit(gpio); +- else +- GPDR(gpio) &= ~GPIO_bit(gpio); +- gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2)); +- GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2)); +- local_irq_restore(flags); +- +- return 0; +-} +- +-EXPORT_SYMBOL(pxa_gpio_mode); +- +-int gpio_direction_input(unsigned gpio) +-{ +- unsigned long flags; +- u32 mask; +- +- if (gpio > pxa_last_gpio) +- return -EINVAL; +- +- mask = GPIO_bit(gpio); +- local_irq_save(flags); +- GPDR(gpio) &= ~mask; +- local_irq_restore(flags); +- +- return 0; +-} +-EXPORT_SYMBOL(gpio_direction_input); +- +-int gpio_direction_output(unsigned gpio, int value) +-{ +- unsigned long flags; +- u32 mask; +- +- if (gpio > pxa_last_gpio) +- return -EINVAL; +- +- mask = GPIO_bit(gpio); +- local_irq_save(flags); +- if (value) +- GPSR(gpio) = mask; +- else +- GPCR(gpio) = mask; +- GPDR(gpio) |= mask; +- local_irq_restore(flags); +- +- return 0; +-} +-EXPORT_SYMBOL(gpio_direction_output); +- +-/* +- * Return GPIO level +- */ +-int pxa_gpio_get_value(unsigned gpio) +-{ +- return __gpio_get_value(gpio); +-} +- +-EXPORT_SYMBOL(pxa_gpio_get_value); +- +-/* +- * Set output GPIO level +- */ +-void pxa_gpio_set_value(unsigned gpio, int value) +-{ +- __gpio_set_value(gpio, value); +-} +- +-EXPORT_SYMBOL(pxa_gpio_set_value); +- +-/* + * Routine to safely enable or disable a clock in the CKEN + */ + void __pxa_set_cken(int clock, int enable) +@@ -178,7 +86,6 @@ void __pxa_set_cken(int clock, int enable) + + local_irq_restore(flags); + } +- + EXPORT_SYMBOL(__pxa_set_cken); + + /* +diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h +index b30f240..727a9f5 100644 +--- a/arch/arm/mach-pxa/generic.h ++++ b/arch/arm/mach-pxa/generic.h +@@ -16,6 +16,7 @@ extern void __init pxa_init_irq_low(void); + extern void __init pxa_init_irq_high(void); + extern void __init pxa_init_irq_gpio(int gpio_nr); + extern void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int)); ++extern void __init pxa_init_gpio(int gpio_nr); + extern void __init pxa25x_init_irq(void); + extern void __init pxa27x_init_irq(void); + extern void __init pxa3xx_init_irq(void); +diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c +new file mode 100644 +index 0000000..8638dd7 +--- /dev/null ++++ b/arch/arm/mach-pxa/gpio.c +@@ -0,0 +1,197 @@ ++/* ++ * linux/arch/arm/mach-pxa/gpio.c ++ * ++ * Generic PXA GPIO handling ++ * ++ * Author: Nicolas Pitre ++ * Created: Jun 15, 2001 ++ * Copyright: MontaVista Software Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include <linux/init.h> ++#include <linux/module.h> ++ ++#include <asm/gpio.h> ++#include <asm/hardware.h> ++#include <asm/io.h> ++#include <asm/arch/pxa-regs.h> ++ ++#include "generic.h" ++ ++ ++struct pxa_gpio_chip { ++ struct gpio_chip chip; ++ void __iomem *regbase; ++}; ++ ++int pxa_last_gpio; ++ ++/* ++ * Configure pins for GPIO or other functions ++ */ ++int pxa_gpio_mode(int gpio_mode) ++{ ++ unsigned long flags; ++ int gpio = gpio_mode & GPIO_MD_MASK_NR; ++ int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; ++ int gafr; ++ ++ if (gpio > pxa_last_gpio) ++ return -EINVAL; ++ ++ local_irq_save(flags); ++ if (gpio_mode & GPIO_DFLT_LOW) ++ GPCR(gpio) = GPIO_bit(gpio); ++ else if (gpio_mode & GPIO_DFLT_HIGH) ++ GPSR(gpio) = GPIO_bit(gpio); ++ if (gpio_mode & GPIO_MD_MASK_DIR) ++ GPDR(gpio) |= GPIO_bit(gpio); ++ else ++ GPDR(gpio) &= ~GPIO_bit(gpio); ++ gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2)); ++ GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2)); ++ local_irq_restore(flags); ++ ++ return 0; ++} ++EXPORT_SYMBOL(pxa_gpio_mode); ++ ++static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) ++{ ++ unsigned long flags; ++ u32 mask = 1 << offset; ++ u32 value; ++ struct pxa_gpio_chip *pxa; ++ void __iomem *gpdr; ++ ++ pxa = container_of(chip, struct pxa_gpio_chip, chip); ++ gpdr = pxa->regbase + GPDR_OFFSET; ++ local_irq_save(flags); ++ value = __raw_readl(gpdr); ++ value &= ~mask; ++ __raw_writel(value, gpdr); ++ local_irq_restore(flags); ++ ++ return 0; ++} ++ ++static int pxa_gpio_direction_output(struct gpio_chip *chip, ++ unsigned offset, int value) ++{ ++ unsigned long flags; ++ u32 mask = 1 << offset; ++ u32 tmp; ++ struct pxa_gpio_chip *pxa; ++ void __iomem *gpdr; ++ ++ pxa = container_of(chip, struct pxa_gpio_chip, chip); ++ __raw_writel(mask, ++ pxa->regbase + (value ? GPSR_OFFSET : GPCR_OFFSET)); ++ gpdr = pxa->regbase + GPDR_OFFSET; ++ local_irq_save(flags); ++ tmp = __raw_readl(gpdr); ++ tmp |= mask; ++ __raw_writel(tmp, gpdr); ++ local_irq_restore(flags); ++ ++ return 0; ++} ++ ++/* ++ * Return GPIO level ++ */ ++static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) ++{ ++ u32 mask = 1 << offset; ++ struct pxa_gpio_chip *pxa; ++ ++ pxa = container_of(chip, struct pxa_gpio_chip, chip); ++ return __raw_readl(pxa->regbase + GPLR_OFFSET) & mask; ++} ++ ++/* ++ * Set output GPIO level ++ */ ++static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) ++{ ++ u32 mask = 1 << offset; ++ struct pxa_gpio_chip *pxa; ++ ++ pxa = container_of(chip, struct pxa_gpio_chip, chip); ++ ++ if (value) ++ __raw_writel(mask, pxa->regbase + GPSR_OFFSET); ++ else ++ __raw_writel(mask, pxa->regbase + GPCR_OFFSET); ++} ++ ++static struct pxa_gpio_chip pxa_gpio_chip[] = { ++ [0] = { ++ .regbase = GPIO0_BASE, ++ .chip = { ++ .label = "gpio-0", ++ .direction_input = pxa_gpio_direction_input, ++ .direction_output = pxa_gpio_direction_output, ++ .get = pxa_gpio_get, ++ .set = pxa_gpio_set, ++ .base = 0, ++ .ngpio = 32, ++ }, ++ }, ++ [1] = { ++ .regbase = GPIO1_BASE, ++ .chip = { ++ .label = "gpio-1", ++ .direction_input = pxa_gpio_direction_input, ++ .direction_output = pxa_gpio_direction_output, ++ .get = pxa_gpio_get, ++ .set = pxa_gpio_set, ++ .base = 32, ++ .ngpio = 32, ++ }, ++ }, ++ [2] = { ++ .regbase = GPIO2_BASE, ++ .chip = { ++ .label = "gpio-2", ++ .direction_input = pxa_gpio_direction_input, ++ .direction_output = pxa_gpio_direction_output, ++ .get = pxa_gpio_get, ++ .set = pxa_gpio_set, ++ .base = 64, ++ .ngpio = 32, /* 21 for PXA25x */ ++ }, ++ }, ++#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) ++ [3] = { ++ .regbase = GPIO3_BASE, ++ .chip = { ++ .label = "gpio-3", ++ .direction_input = pxa_gpio_direction_input, ++ .direction_output = pxa_gpio_direction_output, ++ .get = pxa_gpio_get, ++ .set = pxa_gpio_set, ++ .base = 96, ++ .ngpio = 32, ++ }, ++ }, ++#endif ++}; ++ ++void __init pxa_init_gpio(int gpio_nr) ++{ ++ int i; ++ ++ /* add a GPIO chip for each register bank. ++ * the last PXA25x register only contains 21 GPIOs ++ */ ++ for (i = 0; i < gpio_nr; i += 32) { ++ if (i+32 > gpio_nr) ++ pxa_gpio_chip[i/32].chip.ngpio = gpio_nr - i; ++ gpiochip_add(&pxa_gpio_chip[i/32].chip); ++ } ++} +diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c +index 07acb45..d0965ef 100644 +--- a/arch/arm/mach-pxa/irq.c ++++ b/arch/arm/mach-pxa/irq.c +@@ -310,6 +310,8 @@ void __init pxa_init_irq_gpio(int gpio_nr) + /* Install handler for GPIO>=2 edge detect interrupts */ + set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low); + set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); ++ ++ pxa_init_gpio(gpio_nr); + } + + void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int)) +diff --git a/include/asm-arm/arch-pxa/gpio.h b/include/asm-arm/arch-pxa/gpio.h +index 9dbc2dc..bdbf5f9 100644 +--- a/include/asm-arm/arch-pxa/gpio.h ++++ b/include/asm-arm/arch-pxa/gpio.h +@@ -28,43 +28,35 @@ + #include <asm/irq.h> + #include <asm/hardware.h> + +-static inline int gpio_request(unsigned gpio, const char *label) +-{ +- return 0; +-} ++#include <asm-generic/gpio.h> + +-static inline void gpio_free(unsigned gpio) +-{ +- return; +-} + +-extern int gpio_direction_input(unsigned gpio); +-extern int gpio_direction_output(unsigned gpio, int value); ++/* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85). ++ * Those cases currently cause holes in the GPIO number space. ++ */ ++#define NR_BUILTIN_GPIO 128 + +-static inline int __gpio_get_value(unsigned gpio) ++static inline int gpio_get_value(unsigned gpio) + { +- return GPLR(gpio) & GPIO_bit(gpio); ++ if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) ++ return GPLR(gpio) & GPIO_bit(gpio); ++ else ++ return __gpio_get_value(gpio); + } + +-#define gpio_get_value(gpio) \ +- (__builtin_constant_p(gpio) ? \ +- __gpio_get_value(gpio) : \ +- pxa_gpio_get_value(gpio)) +- +-static inline void __gpio_set_value(unsigned gpio, int value) ++static inline void gpio_set_value(unsigned gpio, int value) + { +- if (value) +- GPSR(gpio) = GPIO_bit(gpio); +- else +- GPCR(gpio) = GPIO_bit(gpio); ++ if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) { ++ if (value) ++ GPSR(gpio) = GPIO_bit(gpio); ++ else ++ GPCR(gpio) = GPIO_bit(gpio); ++ } else { ++ __gpio_set_value(gpio, value); ++ } + } + +-#define gpio_set_value(gpio,value) \ +- (__builtin_constant_p(gpio) ? \ +- __gpio_set_value(gpio, value) : \ +- pxa_gpio_set_value(gpio, value)) +- +-#include <asm-generic/gpio.h> /* cansleep wrappers */ ++#define gpio_cansleep __gpio_cansleep + + #define gpio_to_irq(gpio) IRQ_GPIO(gpio) + #define irq_to_gpio(irq) IRQ_TO_GPIO(irq) +diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h +index 1bd398d..bd57417 100644 +--- a/include/asm-arm/arch-pxa/pxa-regs.h ++++ b/include/asm-arm/arch-pxa/pxa-regs.h +@@ -1131,6 +1131,19 @@ + * General Purpose I/O + */ + ++#define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000)) ++#define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004)) ++#define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008)) ++#define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100)) ++ ++#define GPLR_OFFSET 0x00 ++#define GPDR_OFFSET 0x0C ++#define GPSR_OFFSET 0x18 ++#define GPCR_OFFSET 0x24 ++#define GRER_OFFSET 0x30 ++#define GFER_OFFSET 0x3C ++#define GEDR_OFFSET 0x48 ++ + #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ + #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ + #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0024-Update-Documentation-gpio.txt-primarily-to-include.patch b/packages/linux/linux-rp-2.6.24/tosa/0024-Update-Documentation-gpio.txt-primarily-to-include.patch new file mode 100644 index 0000000000..e460379de6 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0024-Update-Documentation-gpio.txt-primarily-to-include.patch @@ -0,0 +1,238 @@ +From 7ba82399f2d2df6114ad552999f2e1b9a19cb47a Mon Sep 17 00:00:00 2001 +From: David Brownell <dbrownell@users.sourceforge.net> +Date: Sat, 19 Jan 2008 19:41:18 +0300 +Subject: [PATCH 24/64] Update Documentation/gpio.txt, primarily to include the new "gpiolib" + infrastructure. + +Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> +Cc: Jean Delvare <khali@linux-fr.org> +Cc: Eric Miao <eric.miao@marvell.com> +Cc: Sam Ravnborg <sam@ravnborg.org> +Cc: Haavard Skinnemoen <hskinnemoen@atmel.com> +Cc: Philipp Zabel <philipp.zabel@gmail.com> +Cc: Russell King <rmk@arm.linux.org.uk> +Cc: Ben Gardner <bgardner@wabtec.com> +Signed-off-by: Andrew Morton <akpm@linux-foundation.org> +--- + Documentation/gpio.txt | 133 +++++++++++++++++++++++++++++++++++++++++++---- + 1 files changed, 121 insertions(+), 12 deletions(-) + +diff --git a/Documentation/gpio.txt b/Documentation/gpio.txt +index 6bc2ba2..8da724e 100644 +--- a/Documentation/gpio.txt ++++ b/Documentation/gpio.txt +@@ -32,7 +32,7 @@ The exact capabilities of GPIOs vary between systems. Common options: + - Input values are likewise readable (1, 0). Some chips support readback + of pins configured as "output", which is very useful in such "wire-OR" + cases (to support bidirectional signaling). GPIO controllers may have +- input de-glitch logic, sometimes with software controls. ++ input de-glitch/debounce logic, sometimes with software controls. + + - Inputs can often be used as IRQ signals, often edge triggered but + sometimes level triggered. Such IRQs may be configurable as system +@@ -60,10 +60,13 @@ used on a board that's wired differently. Only least-common-denominator + functionality can be very portable. Other features are platform-specific, + and that can be critical for glue logic. + +-Plus, this doesn't define an implementation framework, just an interface. ++Plus, this doesn't require any implementation framework, just an interface. + One platform might implement it as simple inline functions accessing chip + registers; another might implement it by delegating through abstractions +-used for several very different kinds of GPIO controller. ++used for several very different kinds of GPIO controller. (There is some ++optional code supporting such an implementation strategy, described later ++in this document, but drivers acting as clients to the GPIO interface must ++not care how it's implemented.) + + That said, if the convention is supported on their platform, drivers should + use it when possible. Platforms should declare GENERIC_GPIO support in +@@ -121,6 +124,11 @@ before tasking is enabled, as part of early board setup. + For output GPIOs, the value provided becomes the initial output value. + This helps avoid signal glitching during system startup. + ++For compatibility with legacy interfaces to GPIOs, setting the direction ++of a GPIO implicitly requests that GPIO (see below) if it has not been ++requested already. That compatibility may be removed in the future; ++explicitly requesting GPIOs is strongly preferred. ++ + Setting the direction can fail if the GPIO number is invalid, or when + that particular GPIO can't be used in that mode. It's generally a bad + idea to rely on boot firmware to have set the direction correctly, since +@@ -133,6 +141,7 @@ Spinlock-Safe GPIO access + ------------------------- + Most GPIO controllers can be accessed with memory read/write instructions. + That doesn't need to sleep, and can safely be done from inside IRQ handlers. ++(That includes hardirq contexts on RT kernels.) + + Use these calls to access such GPIOs: + +@@ -145,7 +154,7 @@ Use these calls to access such GPIOs: + The values are boolean, zero for low, nonzero for high. When reading the + value of an output pin, the value returned should be what's seen on the + pin ... that won't always match the specified output value, because of +-issues including wire-OR and output latencies. ++issues including open-drain signaling and output latencies. + + The get/set calls have no error returns because "invalid GPIO" should have + been reported earlier from gpio_direction_*(). However, note that not all +@@ -170,7 +179,8 @@ get to the head of a queue to transmit a command and get its response. + This requires sleeping, which can't be done from inside IRQ handlers. + + Platforms that support this type of GPIO distinguish them from other GPIOs +-by returning nonzero from this call: ++by returning nonzero from this call (which requires a valid GPIO number, ++either explicitly or implicitly requested): + + int gpio_cansleep(unsigned gpio); + +@@ -209,8 +219,11 @@ before tasking is enabled, as part of early board setup. + These calls serve two basic purposes. One is marking the signals which + are actually in use as GPIOs, for better diagnostics; systems may have + several hundred potential GPIOs, but often only a dozen are used on any +-given board. Another is to catch conflicts between drivers, reporting +-errors when drivers wrongly think they have exclusive use of that signal. ++given board. Another is to catch conflicts, identifying errors when ++(a) two or more drivers wrongly think they have exclusive use of that ++signal, or (b) something wrongly believes it's safe to remove drivers ++needed to manage a signal that's in active use. That is, requesting a ++GPIO can serve as a kind of lock. + + These two calls are optional because not not all current Linux platforms + offer such functionality in their GPIO support; a valid implementation +@@ -223,6 +236,9 @@ Note that requesting a GPIO does NOT cause it to be configured in any + way; it just marks that GPIO as in use. Separate code must handle any + pin setup (e.g. controlling which pin the GPIO uses, pullup/pulldown). + ++Also note that it's your responsibility to have stopped using a GPIO ++before you free it. ++ + + GPIOs mapped to IRQs + -------------------- +@@ -238,7 +254,7 @@ map between them using calls like: + + Those return either the corresponding number in the other namespace, or + else a negative errno code if the mapping can't be done. (For example, +-some GPIOs can't used as IRQs.) It is an unchecked error to use a GPIO ++some GPIOs can't be used as IRQs.) It is an unchecked error to use a GPIO + number that wasn't set up as an input using gpio_direction_input(), or + to use an IRQ number that didn't originally come from gpio_to_irq(). + +@@ -299,17 +315,110 @@ Related to multiplexing is configuration and enabling of the pullups or + pulldowns integrated on some platforms. Not all platforms support them, + or support them in the same way; and any given board might use external + pullups (or pulldowns) so that the on-chip ones should not be used. ++(When a circuit needs 5 kOhm, on-chip 100 kOhm resistors won't do.) + + There are other system-specific mechanisms that are not specified here, + like the aforementioned options for input de-glitching and wire-OR output. + Hardware may support reading or writing GPIOs in gangs, but that's usually + configuration dependent: for GPIOs sharing the same bank. (GPIOs are + commonly grouped in banks of 16 or 32, with a given SOC having several such +-banks.) Some systems can trigger IRQs from output GPIOs. Code relying on +-such mechanisms will necessarily be nonportable. ++banks.) Some systems can trigger IRQs from output GPIOs, or read values ++from pins not managed as GPIOs. Code relying on such mechanisms will ++necessarily be nonportable. + +-Dynamic definition of GPIOs is not currently supported; for example, as ++Dynamic definition of GPIOs is not currently standard; for example, as + a side effect of configuring an add-on board with some GPIO expanders. + + These calls are purely for kernel space, but a userspace API could be built +-on top of it. ++on top of them. ++ ++ ++GPIO implementor's framework (OPTIONAL) ++======================================= ++As noted earlier, there is an optional implementation framework making it ++easier for platforms to support different kinds of GPIO controller using ++the same programming interface. ++ ++As a debugging aid, if debugfs is available a /sys/kernel/debug/gpio file ++will be found there. That will list all the controllers registered through ++this framework, and the state of the GPIOs currently in use. ++ ++ ++Controller Drivers: gpio_chip ++----------------------------- ++In this framework each GPIO controller is packaged as a "struct gpio_chip" ++with information common to each controller of that type: ++ ++ - methods to establish GPIO direction ++ - methods used to access GPIO values ++ - flag saying whether calls to its methods may sleep ++ - optional debugfs dump method (showing extra state like pullup config) ++ - label for diagnostics ++ ++There is also per-instance data, which may come from device.platform_data: ++the number of its first GPIO, and how many GPIOs it exposes. ++ ++The code implementing a gpio_chip should support multiple instances of the ++controller, possibly using the driver model. That code will configure each ++gpio_chip and issue gpiochip_add(). Removing a GPIO controller should be ++rare; use gpiochip_remove() when it is unavoidable. ++ ++Most often a gpio_chip is part of an instance-specific structure with state ++not exposed by the GPIO interfaces, such as addressing, power management, ++and more. Chips such as codecs will have complex non-GPIO state, ++ ++Any debugfs dump method should normally ignore signals which haven't been ++requested as GPIOs. They can use gpiochip_is_requested(), which returns ++either NULL or the label associated with that GPIO when it was requested. ++ ++ ++Platform Support ++---------------- ++To support this framework, a platform's Kconfig will "select HAVE_GPIO_LIB" ++and arrange that its <asm/gpio.h> includes <asm-generic/gpio.h> and defines ++three functions: gpio_get_value(), gpio_set_value(), and gpio_cansleep(). ++They may also want to provide a custom value for ARCH_NR_GPIOS. ++ ++Trivial implementations of those functions can directly use framework ++code, which always dispatches through the gpio_chip: ++ ++ #define gpio_get_value __gpio_get_value ++ #define gpio_set_value __gpio_set_value ++ #define gpio_cansleep __gpio_cansleep ++ ++Fancier implementations could instead define those as inline functions with ++logic optimizing access to specific SOC-based GPIOs. For example, if the ++referenced GPIO is the constant "12", getting or setting its value could ++cost as little as two or three instructions, never sleeping. When such an ++optimization is not possible those calls must delegate to the framework ++code, costing at least a few dozen instructions. For bitbanged I/O, such ++instruction savings can be significant. ++ ++For SOCs, platform-specific code defines and registers gpio_chip instances ++for each bank of on-chip GPIOs. Those GPIOs should be numbered/labeled to ++match chip vendor documentation, and directly match board schematics. They ++may well start at zero and go up to a platform-specific limit. Such GPIOs ++are normally integrated into platform initialization to make them always be ++available, from arch_initcall() or earlier; they can often serve as IRQs. ++ ++ ++Board Support ++------------- ++For external GPIO controllers -- such as I2C or SPI expanders, ASICs, multi ++function devices, FPGAs or CPLDs -- most often board-specific code handles ++registering controller devices and ensures that their drivers know what GPIO ++numbers to use with gpiochip_add(). Their numbers often start right after ++platform-specific GPIOs. ++ ++For example, board setup code could create structures identifying the range ++of GPIOs that chip will expose, and passes them to each GPIO expander chip ++using platform_data. Then the chip driver's probe() routine could pass that ++data to gpiochip_add(). ++ ++Initialization order can be important. For example, when a device relies on ++an I2C-based GPIO, its probe() routine should only be called after that GPIO ++becomes available. That may mean the device should not be registered until ++calls for that GPIO can work. One way to address such dependencies is for ++such gpio_chip controllers to provide setup() and teardown() callbacks to ++board specific code; those board specific callbacks would register devices ++once all the necessary resources are available. +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0025-Signed-off-by-Dmitry-Baryshkov-dbaryshkov-gmail.co.patch b/packages/linux/linux-rp-2.6.24/tosa/0025-Signed-off-by-Dmitry-Baryshkov-dbaryshkov-gmail.co.patch new file mode 100644 index 0000000000..84d0fd3e19 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0025-Signed-off-by-Dmitry-Baryshkov-dbaryshkov-gmail.co.patch @@ -0,0 +1,434 @@ +From 39717c1328f6aa13330eded0e0e268993cfd1eea Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Tue, 12 Feb 2008 10:39:53 +0300 +Subject: [PATCH 25/64] Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> + +--- + arch/arm/mach-pxa/Makefile | 2 +- + arch/arm/mach-pxa/devices.c | 401 +++++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 402 insertions(+), 1 deletions(-) + create mode 100644 arch/arm/mach-pxa/devices.c + +diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile +index 5cb0216..f276d24 100644 +--- a/arch/arm/mach-pxa/Makefile ++++ b/arch/arm/mach-pxa/Makefile +@@ -4,7 +4,7 @@ + + # Common support (must be linked before board specific support) + obj-y += clock.o generic.o irq.o dma.o \ +- time.o gpio.o ++ time.o gpio.o devices.o + obj-$(CONFIG_PXA25x) += pxa25x.o + obj-$(CONFIG_PXA27x) += pxa27x.o + obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o +diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c +new file mode 100644 +index 0000000..928131a +--- /dev/null ++++ b/arch/arm/mach-pxa/devices.c +@@ -0,0 +1,401 @@ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/platform_device.h> ++#include <linux/dma-mapping.h> ++ ++#include <asm/arch/gpio.h> ++#include <asm/arch/udc.h> ++#include <asm/arch/pxafb.h> ++#include <asm/arch/mmc.h> ++#include <asm/arch/irda.h> ++#include <asm/arch/i2c.h> ++#include <asm/arch/ohci.h> ++ ++#include "devices.h" ++ ++#ifdef CONFIG_PXA25x ++ ++static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32); ++ ++static struct resource pxa25x_resource_ssp[] = { ++ [0] = { ++ .start = 0x41000000, ++ .end = 0x4100001f, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_SSP, ++ .end = IRQ_SSP, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ /* DRCMR for RX */ ++ .start = 13, ++ .end = 13, ++ .flags = IORESOURCE_DMA, ++ }, ++ [3] = { ++ /* DRCMR for TX */ ++ .start = 14, ++ .end = 14, ++ .flags = IORESOURCE_DMA, ++ }, ++}; ++ ++struct platform_device pxa25x_device_ssp = { ++ .name = "pxa25x-ssp", ++ .id = 0, ++ .dev = { ++ .dma_mask = &pxa25x_ssp_dma_mask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++ .resource = pxa25x_resource_ssp, ++ .num_resources = ARRAY_SIZE(pxa25x_resource_ssp), ++}; ++ ++static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32); ++ ++static struct resource pxa25x_resource_nssp[] = { ++ [0] = { ++ .start = 0x41400000, ++ .end = 0x4140002f, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_NSSP, ++ .end = IRQ_NSSP, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ /* DRCMR for RX */ ++ .start = 15, ++ .end = 15, ++ .flags = IORESOURCE_DMA, ++ }, ++ [3] = { ++ /* DRCMR for TX */ ++ .start = 16, ++ .end = 16, ++ .flags = IORESOURCE_DMA, ++ }, ++}; ++ ++struct platform_device pxa25x_device_nssp = { ++ .name = "pxa25x-nssp", ++ .id = 1, ++ .dev = { ++ .dma_mask = &pxa25x_nssp_dma_mask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++ .resource = pxa25x_resource_nssp, ++ .num_resources = ARRAY_SIZE(pxa25x_resource_nssp), ++}; ++ ++static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32); ++ ++static struct resource pxa25x_resource_assp[] = { ++ [0] = { ++ .start = 0x41500000, ++ .end = 0x4150002f, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_ASSP, ++ .end = IRQ_ASSP, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ /* DRCMR for RX */ ++ .start = 23, ++ .end = 23, ++ .flags = IORESOURCE_DMA, ++ }, ++ [3] = { ++ /* DRCMR for TX */ ++ .start = 24, ++ .end = 24, ++ .flags = IORESOURCE_DMA, ++ }, ++}; ++ ++struct platform_device pxa25x_device_assp = { ++ /* ASSP is basically equivalent to NSSP */ ++ .name = "pxa25x-nssp", ++ .id = 2, ++ .dev = { ++ .dma_mask = &pxa25x_assp_dma_mask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++ .resource = pxa25x_resource_assp, ++ .num_resources = ARRAY_SIZE(pxa25x_resource_assp), ++}; ++#endif /* CONFIG_PXA25x */ ++ ++#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) ++ ++static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32); ++ ++static struct resource pxa27x_resource_ohci[] = { ++ [0] = { ++ .start = 0x4C000000, ++ .end = 0x4C00ff6f, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_USBH1, ++ .end = IRQ_USBH1, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++struct platform_device pxa27x_device_ohci = { ++ .name = "pxa27x-ohci", ++ .id = -1, ++ .dev = { ++ .dma_mask = &pxa27x_ohci_dma_mask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++ .num_resources = ARRAY_SIZE(pxa27x_resource_ohci), ++ .resource = pxa27x_resource_ohci, ++}; ++ ++void __init pxa_set_ohci_info(struct pxaohci_platform_data *info) ++{ ++ pxa_register_device(&pxa27x_device_ohci, info); ++} ++ ++static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32); ++ ++static struct resource pxa27x_resource_ssp1[] = { ++ [0] = { ++ .start = 0x41000000, ++ .end = 0x4100003f, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_SSP, ++ .end = IRQ_SSP, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ /* DRCMR for RX */ ++ .start = 13, ++ .end = 13, ++ .flags = IORESOURCE_DMA, ++ }, ++ [3] = { ++ /* DRCMR for TX */ ++ .start = 14, ++ .end = 14, ++ .flags = IORESOURCE_DMA, ++ }, ++}; ++ ++struct platform_device pxa27x_device_ssp1 = { ++ .name = "pxa27x-ssp", ++ .id = 0, ++ .dev = { ++ .dma_mask = &pxa27x_ssp1_dma_mask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++ .resource = pxa27x_resource_ssp1, ++ .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1), ++}; ++ ++static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32); ++ ++static struct resource pxa27x_resource_ssp2[] = { ++ [0] = { ++ .start = 0x41700000, ++ .end = 0x4170003f, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_SSP2, ++ .end = IRQ_SSP2, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ /* DRCMR for RX */ ++ .start = 15, ++ .end = 15, ++ .flags = IORESOURCE_DMA, ++ }, ++ [3] = { ++ /* DRCMR for TX */ ++ .start = 16, ++ .end = 16, ++ .flags = IORESOURCE_DMA, ++ }, ++}; ++ ++struct platform_device pxa27x_device_ssp2 = { ++ .name = "pxa27x-ssp", ++ .id = 1, ++ .dev = { ++ .dma_mask = &pxa27x_ssp2_dma_mask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++ .resource = pxa27x_resource_ssp2, ++ .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2), ++}; ++ ++static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32); ++ ++static struct resource pxa27x_resource_ssp3[] = { ++ [0] = { ++ .start = 0x41900000, ++ .end = 0x4190003f, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_SSP3, ++ .end = IRQ_SSP3, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ /* DRCMR for RX */ ++ .start = 66, ++ .end = 66, ++ .flags = IORESOURCE_DMA, ++ }, ++ [3] = { ++ /* DRCMR for TX */ ++ .start = 67, ++ .end = 67, ++ .flags = IORESOURCE_DMA, ++ }, ++}; ++ ++struct platform_device pxa27x_device_ssp3 = { ++ .name = "pxa27x-ssp", ++ .id = 2, ++ .dev = { ++ .dma_mask = &pxa27x_ssp3_dma_mask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++ .resource = pxa27x_resource_ssp3, ++ .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3), ++}; ++#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */ ++ ++#ifdef CONFIG_PXA3xx ++static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32); ++ ++static struct resource pxa3xx_resource_ssp4[] = { ++ [0] = { ++ .start = 0x41a00000, ++ .end = 0x41a0003f, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_SSP4, ++ .end = IRQ_SSP4, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ /* DRCMR for RX */ ++ .start = 2, ++ .end = 2, ++ .flags = IORESOURCE_DMA, ++ }, ++ [3] = { ++ /* DRCMR for TX */ ++ .start = 3, ++ .end = 3, ++ .flags = IORESOURCE_DMA, ++ }, ++}; ++ ++struct platform_device pxa3xx_device_ssp4 = { ++ /* PXA3xx SSP is basically equivalent to PXA27x */ ++ .name = "pxa27x-ssp", ++ .id = 3, ++ .dev = { ++ .dma_mask = &pxa3xx_ssp4_dma_mask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++ .resource = pxa3xx_resource_ssp4, ++ .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4), ++}; ++ ++static struct resource pxa3xx_resources_mci2[] = { ++ [0] = { ++ .start = 0x42000000, ++ .end = 0x42000fff, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_MMC2, ++ .end = IRQ_MMC2, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = 93, ++ .end = 93, ++ .flags = IORESOURCE_DMA, ++ }, ++ [3] = { ++ .start = 94, ++ .end = 94, ++ .flags = IORESOURCE_DMA, ++ }, ++}; ++ ++struct platform_device pxa3xx_device_mci2 = { ++ .name = "pxa2xx-mci", ++ .id = 1, ++ .dev = { ++ .dma_mask = &pxamci_dmamask, ++ .coherent_dma_mask = 0xffffffff, ++ }, ++ .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2), ++ .resource = pxa3xx_resources_mci2, ++}; ++ ++void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info) ++{ ++ pxa_register_device(&pxa3xx_device_mci2, info); ++} ++ ++static struct resource pxa3xx_resources_mci3[] = { ++ [0] = { ++ .start = 0x42500000, ++ .end = 0x42500fff, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_MMC3, ++ .end = IRQ_MMC3, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [2] = { ++ .start = 100, ++ .end = 100, ++ .flags = IORESOURCE_DMA, ++ }, ++ [3] = { ++ .start = 101, ++ .end = 101, ++ .flags = IORESOURCE_DMA, ++ }, ++}; ++ ++struct platform_device pxa3xx_device_mci3 = { ++ .name = "pxa2xx-mci", ++ .id = 2, ++ .dev = { ++ .dma_mask = &pxamci_dmamask, ++ .coherent_dma_mask = 0xffffffff, ++ }, ++ .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3), ++ .resource = pxa3xx_resources_mci3, ++}; ++ ++void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info) ++{ ++ pxa_register_device(&pxa3xx_device_mci3, info); ++} ++ ++#endif /* CONFIG_PXA3xx */ +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0026-I-don-t-think-we-should-check-for-IRQs-when-determin.patch b/packages/linux/linux-rp-2.6.24/tosa/0026-I-don-t-think-we-should-check-for-IRQs-when-determin.patch new file mode 100644 index 0000000000..e1323e4edc --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0026-I-don-t-think-we-should-check-for-IRQs-when-determin.patch @@ -0,0 +1,134 @@ +From cbe46408b666983284e8be290950d526dbc0f0a4 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Wed, 9 Jan 2008 02:08:16 +0300 +Subject: [PATCH 26/64] I don't think we should check for IRQs when determining which one + of power supplies to register. Better use is_{ac,usb}_online + callbacks, this will not produce an obstacle to implement polling -- + when irqs aren't mandatory. I'll send my two pending patches to show + the idea. + +For this particular issue, I think something like that should work. +If it works for you, I'll commit that version, preserving your +authorship, of course. +--- + drivers/power/pda_power.c | 80 ++++++++++++++++++++++++-------------------- + 1 files changed, 44 insertions(+), 36 deletions(-) + +diff --git a/drivers/power/pda_power.c b/drivers/power/pda_power.c +index c058f28..d98622f 100644 +--- a/drivers/power/pda_power.c ++++ b/drivers/power/pda_power.c +@@ -168,66 +168,74 @@ static int pda_power_probe(struct platform_device *pdev) + pda_power_supplies[1].num_supplicants = pdata->num_supplicants; + } + +- ret = power_supply_register(&pdev->dev, &pda_power_supplies[0]); +- if (ret) { +- dev_err(dev, "failed to register %s power supply\n", +- pda_power_supplies[0].name); +- goto supply0_failed; +- } ++ if (pdata->is_ac_online) { ++ ret = power_supply_register(&pdev->dev, &pda_power_supplies[0]); ++ if (ret) { ++ dev_err(dev, "failed to register %s power supply\n", ++ pda_power_supplies[0].name); ++ goto ac_supply_failed; ++ } + +- ret = power_supply_register(&pdev->dev, &pda_power_supplies[1]); +- if (ret) { +- dev_err(dev, "failed to register %s power supply\n", +- pda_power_supplies[1].name); +- goto supply1_failed; ++ if (ac_irq) { ++ ret = request_irq(ac_irq->start, power_changed_isr, ++ get_irq_flags(ac_irq), ac_irq->name, ++ &pda_power_supplies[0]); ++ if (ret) { ++ dev_err(dev, "request ac irq failed\n"); ++ goto ac_irq_failed; ++ } ++ } + } + +- if (ac_irq) { +- ret = request_irq(ac_irq->start, power_changed_isr, +- get_irq_flags(ac_irq), ac_irq->name, +- &pda_power_supplies[0]); ++ if (pdata->is_usb_online) { ++ ret = power_supply_register(&pdev->dev, &pda_power_supplies[1]); + if (ret) { +- dev_err(dev, "request ac irq failed\n"); +- goto ac_irq_failed; ++ dev_err(dev, "failed to register %s power supply\n", ++ pda_power_supplies[1].name); ++ goto usb_supply_failed; + } +- } + +- if (usb_irq) { +- ret = request_irq(usb_irq->start, power_changed_isr, +- get_irq_flags(usb_irq), usb_irq->name, +- &pda_power_supplies[1]); +- if (ret) { +- dev_err(dev, "request usb irq failed\n"); +- goto usb_irq_failed; ++ if (usb_irq) { ++ ret = request_irq(usb_irq->start, power_changed_isr, ++ get_irq_flags(usb_irq), ++ usb_irq->name, ++ &pda_power_supplies[1]); ++ if (ret) { ++ dev_err(dev, "request usb irq failed\n"); ++ goto usb_irq_failed; ++ } + } + } + +- goto success; ++ return 0; + + usb_irq_failed: +- if (ac_irq) ++ if (pdata->is_usb_online) ++ power_supply_unregister(&pda_power_supplies[1]); ++usb_supply_failed: ++ if (pdata->is_ac_online && ac_irq) + free_irq(ac_irq->start, &pda_power_supplies[0]); + ac_irq_failed: +- power_supply_unregister(&pda_power_supplies[1]); +-supply1_failed: +- power_supply_unregister(&pda_power_supplies[0]); +-supply0_failed: ++ if (pdata->is_ac_online) ++ power_supply_unregister(&pda_power_supplies[0]); ++ac_supply_failed: + noirqs: + wrongid: +-success: + return ret; + } + + static int pda_power_remove(struct platform_device *pdev) + { +- if (usb_irq) ++ if (pdata->is_usb_online && usb_irq) + free_irq(usb_irq->start, &pda_power_supplies[1]); +- if (ac_irq) ++ if (pdata->is_ac_online && ac_irq) + free_irq(ac_irq->start, &pda_power_supplies[0]); + del_timer_sync(&charger_timer); + del_timer_sync(&supply_timer); +- power_supply_unregister(&pda_power_supplies[1]); +- power_supply_unregister(&pda_power_supplies[0]); ++ if (pdata->is_usb_online) ++ power_supply_unregister(&pda_power_supplies[1]); ++ if (pdata->is_ac_online) ++ power_supply_unregister(&pda_power_supplies[0]); + return 0; + } + +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0027-Add-LiMn-one-of-the-most-common-for-small-non-recha.patch b/packages/linux/linux-rp-2.6.24/tosa/0027-Add-LiMn-one-of-the-most-common-for-small-non-recha.patch new file mode 100644 index 0000000000..240d2d0bd9 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0027-Add-LiMn-one-of-the-most-common-for-small-non-recha.patch @@ -0,0 +1,59 @@ +From e5e9808fd5ed9cb54dd9da9fb91b32c4f7e9da52 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Wed, 9 Jan 2008 02:08:17 +0300 +Subject: [PATCH 27/64] Add LiMn (one of the most common for small non-rechargable batteries)i + battery technology and voltage_min/_max properties support. + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + drivers/power/power_supply_sysfs.c | 5 ++++- + include/linux/power_supply.h | 3 +++ + 2 files changed, 7 insertions(+), 1 deletions(-) + +diff --git a/drivers/power/power_supply_sysfs.c b/drivers/power/power_supply_sysfs.c +index 249f61b..45d2f95 100644 +--- a/drivers/power/power_supply_sysfs.c ++++ b/drivers/power/power_supply_sysfs.c +@@ -46,7 +46,8 @@ static ssize_t power_supply_show_property(struct device *dev, + "Unspecified failure" + }; + static char *technology_text[] = { +- "Unknown", "NiMH", "Li-ion", "Li-poly", "LiFe", "NiCd" ++ "Unknown", "NiMH", "Li-ion", "Li-poly", "LiFe", "NiCd", ++ "LiMn" + }; + static char *capacity_level_text[] = { + "Unknown", "Critical", "Low", "Normal", "High", "Full" +@@ -88,6 +89,8 @@ static struct device_attribute power_supply_attrs[] = { + POWER_SUPPLY_ATTR(present), + POWER_SUPPLY_ATTR(online), + POWER_SUPPLY_ATTR(technology), ++ POWER_SUPPLY_ATTR(voltage_max), ++ POWER_SUPPLY_ATTR(voltage_min), + POWER_SUPPLY_ATTR(voltage_max_design), + POWER_SUPPLY_ATTR(voltage_min_design), + POWER_SUPPLY_ATTR(voltage_now), +diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h +index 606c095..cdbc5b8 100644 +--- a/include/linux/power_supply.h ++++ b/include/linux/power_supply.h +@@ -54,6 +54,7 @@ enum { + POWER_SUPPLY_TECHNOLOGY_LIPO, + POWER_SUPPLY_TECHNOLOGY_LiFe, + POWER_SUPPLY_TECHNOLOGY_NiCd, ++ POWER_SUPPLY_TECHNOLOGY_LiMn, + }; + + enum { +@@ -72,6 +73,8 @@ enum power_supply_property { + POWER_SUPPLY_PROP_PRESENT, + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_TECHNOLOGY, ++ POWER_SUPPLY_PROP_VOLTAGE_MAX, ++ POWER_SUPPLY_PROP_VOLTAGE_MIN, + POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, + POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, + POWER_SUPPLY_PROP_VOLTAGE_NOW, +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0028-Add-suspend-resume-wakeup-support-for-pda_power.patch b/packages/linux/linux-rp-2.6.24/tosa/0028-Add-suspend-resume-wakeup-support-for-pda_power.patch new file mode 100644 index 0000000000..ac5df97dff --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0028-Add-suspend-resume-wakeup-support-for-pda_power.patch @@ -0,0 +1,72 @@ +From df0801d2cd6a7081700c79f437d1185cbe1960a7 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Wed, 9 Jan 2008 02:08:18 +0300 +Subject: [PATCH 28/64] Add suspend/resume/wakeup support for pda_power. + Now with device_init_wakeup. + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + drivers/power/pda_power.c | 34 ++++++++++++++++++++++++++++++++++ + 1 files changed, 34 insertions(+), 0 deletions(-) + +diff --git a/drivers/power/pda_power.c b/drivers/power/pda_power.c +index d98622f..28360e8 100644 +--- a/drivers/power/pda_power.c ++++ b/drivers/power/pda_power.c +@@ -207,6 +207,8 @@ static int pda_power_probe(struct platform_device *pdev) + } + } + ++ device_init_wakeup(&pdev->dev, 1); ++ + return 0; + + usb_irq_failed: +@@ -239,12 +241,44 @@ static int pda_power_remove(struct platform_device *pdev) + return 0; + } + ++#ifdef CONFIG_PM ++static int pda_power_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ if (device_may_wakeup(&pdev->dev)) { ++ if (ac_irq) ++ enable_irq_wake(ac_irq->start); ++ if (usb_irq) ++ enable_irq_wake(usb_irq->start); ++ } ++ ++ return 0; ++} ++ ++static int pda_power_resume(struct platform_device *pdev) ++{ ++ if (device_may_wakeup(&pdev->dev)) { ++ if (usb_irq) ++ disable_irq_wake(usb_irq->start); ++ if (ac_irq) ++ disable_irq_wake(ac_irq->start); ++ } ++ ++ return 0; ++} ++#else ++#define pda_power_suspend NULL ++#define pda_power_resume NULL ++#endif ++ ++ + static struct platform_driver pda_power_pdrv = { + .driver = { + .name = "pda-power", + }, + .probe = pda_power_probe, + .remove = pda_power_remove, ++ .suspend = pda_power_suspend, ++ .resume = pda_power_resume, + }; + + static int __init pda_power_init(void) +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0029-Support-using-VOLTAGE_-properties-for-apm-calculati.patch b/packages/linux/linux-rp-2.6.24/tosa/0029-Support-using-VOLTAGE_-properties-for-apm-calculati.patch new file mode 100644 index 0000000000..7347fd5a00 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0029-Support-using-VOLTAGE_-properties-for-apm-calculati.patch @@ -0,0 +1,163 @@ +From 57d1450b4e5f27fa78c75895dc30213bde7191bc Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Wed, 9 Jan 2008 02:08:18 +0300 +Subject: [PATCH 29/64] Support using VOLTAGE_* properties for apm calculations. It's pretty + dummy, but useful for batteries for which we can only get voltages. + +--- + drivers/power/apm_power.c | 63 ++++++++++++++++++++++++++++++++++++-------- + 1 files changed, 51 insertions(+), 12 deletions(-) + +diff --git a/drivers/power/apm_power.c b/drivers/power/apm_power.c +index bbf3ee1..526c96e 100644 +--- a/drivers/power/apm_power.c ++++ b/drivers/power/apm_power.c +@@ -13,6 +13,12 @@ + #include <linux/power_supply.h> + #include <linux/apm-emulation.h> + ++typedef enum { ++ SOURCE_ENERGY, ++ SOURCE_CHARGE, ++ SOURCE_VOLTAGE, ++} apm_source; ++ + #define PSY_PROP(psy, prop, val) psy->get_property(psy, \ + POWER_SUPPLY_PROP_##prop, val) + +@@ -87,7 +93,7 @@ static void find_main_battery(void) + } + } + +-static int calculate_time(int status, int using_charge) ++static int calculate_time(int status, apm_source source) + { + union power_supply_propval full; + union power_supply_propval empty; +@@ -106,20 +112,34 @@ static int calculate_time(int status, int using_charge) + return -1; + } + +- if (using_charge) { ++ switch (source) { ++ case SOURCE_CHARGE: + full_prop = POWER_SUPPLY_PROP_CHARGE_FULL; + full_design_prop = POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN; + empty_prop = POWER_SUPPLY_PROP_CHARGE_EMPTY; + empty_design_prop = POWER_SUPPLY_PROP_CHARGE_EMPTY; + cur_avg_prop = POWER_SUPPLY_PROP_CHARGE_AVG; + cur_now_prop = POWER_SUPPLY_PROP_CHARGE_NOW; +- } else { ++ break; ++ case SOURCE_ENERGY: + full_prop = POWER_SUPPLY_PROP_ENERGY_FULL; + full_design_prop = POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN; + empty_prop = POWER_SUPPLY_PROP_ENERGY_EMPTY; + empty_design_prop = POWER_SUPPLY_PROP_CHARGE_EMPTY; + cur_avg_prop = POWER_SUPPLY_PROP_ENERGY_AVG; + cur_now_prop = POWER_SUPPLY_PROP_ENERGY_NOW; ++ break; ++ case SOURCE_VOLTAGE: ++ full_prop = POWER_SUPPLY_PROP_VOLTAGE_MAX; ++ full_design_prop = POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN; ++ empty_prop = POWER_SUPPLY_PROP_VOLTAGE_MIN; ++ empty_design_prop = POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN; ++ cur_avg_prop = POWER_SUPPLY_PROP_VOLTAGE_AVG; ++ cur_now_prop = POWER_SUPPLY_PROP_VOLTAGE_NOW; ++ break; ++ default: ++ printk(KERN_ERR "Unsupported source: %d\n", source); ++ return -1; + } + + if (_MPSY_PROP(full_prop, &full)) { +@@ -146,7 +166,7 @@ static int calculate_time(int status, int using_charge) + return -((cur.intval - empty.intval) * 60L) / I.intval; + } + +-static int calculate_capacity(int using_charge) ++static int calculate_capacity(apm_source source) + { + enum power_supply_property full_prop, empty_prop; + enum power_supply_property full_design_prop, empty_design_prop; +@@ -154,20 +174,33 @@ static int calculate_capacity(int using_charge) + union power_supply_propval empty, full, cur; + int ret; + +- if (using_charge) { ++ switch (source) { ++ case SOURCE_CHARGE: + full_prop = POWER_SUPPLY_PROP_CHARGE_FULL; + empty_prop = POWER_SUPPLY_PROP_CHARGE_EMPTY; + full_design_prop = POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN; + empty_design_prop = POWER_SUPPLY_PROP_CHARGE_EMPTY_DESIGN; + now_prop = POWER_SUPPLY_PROP_CHARGE_NOW; + avg_prop = POWER_SUPPLY_PROP_CHARGE_AVG; +- } else { ++ break; ++ case SOURCE_ENERGY: + full_prop = POWER_SUPPLY_PROP_ENERGY_FULL; + empty_prop = POWER_SUPPLY_PROP_ENERGY_EMPTY; + full_design_prop = POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN; + empty_design_prop = POWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN; + now_prop = POWER_SUPPLY_PROP_ENERGY_NOW; + avg_prop = POWER_SUPPLY_PROP_ENERGY_AVG; ++ case SOURCE_VOLTAGE: ++ full_prop = POWER_SUPPLY_PROP_VOLTAGE_MAX; ++ empty_prop = POWER_SUPPLY_PROP_VOLTAGE_MIN; ++ full_design_prop = POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN; ++ empty_design_prop = POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN; ++ now_prop = POWER_SUPPLY_PROP_VOLTAGE_NOW; ++ avg_prop = POWER_SUPPLY_PROP_VOLTAGE_AVG; ++ break; ++ default: ++ printk(KERN_ERR "Unsupported source: %d\n", source); ++ return -1; + } + + if (_MPSY_PROP(full_prop, &full)) { +@@ -234,10 +267,12 @@ static void apm_battery_apm_get_power_status(struct apm_power_info *info) + info->battery_life = capacity.intval; + } else { + /* try calculate using energy */ +- info->battery_life = calculate_capacity(0); ++ info->battery_life = calculate_capacity(SOURCE_ENERGY); + /* if failed try calculate using charge instead */ + if (info->battery_life == -1) +- info->battery_life = calculate_capacity(1); ++ info->battery_life = calculate_capacity(SOURCE_CHARGE); ++ if (info->battery_life == -1) ++ info->battery_life = calculate_capacity(SOURCE_VOLTAGE); + } + + /* charging status */ +@@ -263,18 +298,22 @@ static void apm_battery_apm_get_power_status(struct apm_power_info *info) + !MPSY_PROP(TIME_TO_FULL_NOW, &time_to_full)) { + info->time = time_to_full.intval / 60; + } else { +- info->time = calculate_time(status.intval, 0); ++ info->time = calculate_time(status.intval, SOURCE_ENERGY); + if (info->time == -1) +- info->time = calculate_time(status.intval, 1); ++ info->time = calculate_time(status.intval, SOURCE_CHARGE); ++ if (info->time == -1) ++ info->time = calculate_time(status.intval, SOURCE_VOLTAGE); + } + } else { + if (!MPSY_PROP(TIME_TO_EMPTY_AVG, &time_to_empty) || + !MPSY_PROP(TIME_TO_EMPTY_NOW, &time_to_empty)) { + info->time = time_to_empty.intval / 60; + } else { +- info->time = calculate_time(status.intval, 0); ++ info->time = calculate_time(status.intval, SOURCE_ENERGY); ++ if (info->time == -1) ++ info->time = calculate_time(status.intval, SOURCE_CHARGE); + if (info->time == -1) +- info->time = calculate_time(status.intval, 1); ++ info->time = calculate_time(status.intval, SOURCE_VOLTAGE); + } + } + +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0030-Core-driver-for-WM97xx-touchscreens.patch b/packages/linux/linux-rp-2.6.24/tosa/0030-Core-driver-for-WM97xx-touchscreens.patch new file mode 100644 index 0000000000..1c86a39c74 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0030-Core-driver-for-WM97xx-touchscreens.patch @@ -0,0 +1,1083 @@ +From d3e044e0e10e6c6b75716cb927e92b4ec284132f Mon Sep 17 00:00:00 2001 +From: Mark Brown <broonie@opensource.wolfsonmicro.com> +Date: Sat, 26 Jan 2008 21:14:20 +0300 +Subject: [PATCH 30/64] Core driver for WM97xx touchscreens + +This patch series adds support for the touchscreen controllers provided +by Wolfson Microelectronics WM97xx series chips in both polled and +streaming modes. + +These drivers have been maintained out of tree since 2003. During that +time the driver the primary maintainer was Liam Girdwood and a number of +people have made contributions including Stanley Cai, Rodolfo Giometti, +Russell King, Marc Kleine-Budde, Ian Molton, Vincent Sanders, Andrew +Zabolotny, Graeme Gregory, Mike Arthur and myself. Apologies to anyone +I have omitted. + +Signed-off-by: Liam Girdwood <liam.girdwood@wolfsonmicro.com> +Signed-off-by: Graeme Gregory <gg@opensource.wolfsonmicro.com> +Signed-off-by: Mike Arthur <mike.arthur@wolfsonmicro.com> +Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> +Cc: Dmitry Baryshkov <dbaryshkov@gmail.com> +Cc: Stanley Cai <stanley.cai@intel.com> +Cc: Rodolfo Giometti <giometti@enneenne.com> +Cc: Russell King <rmk@arm.linux.org.uk> +Cc: Marc Kleine-Budde <mkl@pengutronix.de> +Cc: Ian Molton <spyro@f2s.com> +Cc: Vincent Sanders <vince@kyllikki.org> +Cc: Andrew Zabolotny <zap@homelink.ru> +--- + drivers/input/touchscreen/wm97xx-core.c | 724 +++++++++++++++++++++++++++++++ + include/linux/wm97xx.h | 309 +++++++++++++ + 2 files changed, 1033 insertions(+), 0 deletions(-) + create mode 100644 drivers/input/touchscreen/wm97xx-core.c + create mode 100644 include/linux/wm97xx.h + +diff --git a/drivers/input/touchscreen/wm97xx-core.c b/drivers/input/touchscreen/wm97xx-core.c +new file mode 100644 +index 0000000..27a0a99 +--- /dev/null ++++ b/drivers/input/touchscreen/wm97xx-core.c +@@ -0,0 +1,724 @@ ++/* ++ * wm97xx-core.c -- Touch screen driver core for Wolfson WM9705, WM9712 ++ * and WM9713 AC97 Codecs. ++ * ++ * Copyright 2003, 2004, 2005, 2006, 2007, 2008 Wolfson Microelectronics PLC. ++ * Author: Liam Girdwood ++ * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com ++ * Parts Copyright : Ian Molton <spyro@f2s.com> ++ * Andrew Zabolotny <zap@homelink.ru> ++ * Russell King <rmk@arm.linux.org.uk> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * Notes: ++ * ++ * Features: ++ * - supports WM9705, WM9712, WM9713 ++ * - polling mode ++ * - continuous mode (arch-dependent) ++ * - adjustable rpu/dpp settings ++ * - adjustable pressure current ++ * - adjustable sample settle delay ++ * - 4 and 5 wire touchscreens (5 wire is WM9712 only) ++ * - pen down detection ++ * - battery monitor ++ * - sample AUX adcs ++ * - power management ++ * - codec GPIO ++ * - codec event notification ++ * Todo ++ * - Support for async sampling control for noisy LCDs. ++ * ++ */ ++ ++#include <linux/module.h> ++#include <linux/moduleparam.h> ++#include <linux/version.h> ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/delay.h> ++#include <linux/string.h> ++#include <linux/proc_fs.h> ++#include <linux/pm.h> ++#include <linux/interrupt.h> ++#include <linux/bitops.h> ++#include <linux/workqueue.h> ++#include <linux/wm97xx.h> ++#include <linux/uaccess.h> ++#include <linux/io.h> ++ ++#define TS_NAME "wm97xx" ++#define WM_CORE_VERSION "0.65" ++#define DEFAULT_PRESSURE 0xb0c0 ++ ++ ++/* ++ * Touchscreen absolute values ++ * ++ * These parameters are used to help the input layer discard out of ++ * range readings and reduce jitter etc. ++ * ++ * o min, max:- indicate the min and max values your touch screen returns ++ * o fuzz:- use a higher number to reduce jitter ++ * ++ * The default values correspond to Mainstone II in QVGA mode ++ * ++ * Please read ++ * Documentation/input/input-programming.txt for more details. ++ */ ++ ++static int abs_x[3] = {350, 3900, 5}; ++module_param_array(abs_x, int, NULL, 0); ++MODULE_PARM_DESC(abs_x, "Touchscreen absolute X min, max, fuzz"); ++ ++static int abs_y[3] = {320, 3750, 40}; ++module_param_array(abs_y, int, NULL, 0); ++MODULE_PARM_DESC(abs_y, "Touchscreen absolute Y min, max, fuzz"); ++ ++static int abs_p[3] = {0, 150, 4}; ++module_param_array(abs_p, int, NULL, 0); ++MODULE_PARM_DESC(abs_p, "Touchscreen absolute Pressure min, max, fuzz"); ++ ++/* ++ * wm97xx IO access, all IO locking done by AC97 layer ++ */ ++int wm97xx_reg_read(struct wm97xx *wm, u16 reg) ++{ ++ if (wm->ac97) ++ return wm->ac97->bus->ops->read(wm->ac97, reg); ++ else ++ return -1; ++} ++EXPORT_SYMBOL_GPL(wm97xx_reg_read); ++ ++void wm97xx_reg_write(struct wm97xx *wm, u16 reg, u16 val) ++{ ++ /* cache digitiser registers */ ++ if (reg >= AC97_WM9713_DIG1 && reg <= AC97_WM9713_DIG3) ++ wm->dig[(reg - AC97_WM9713_DIG1) >> 1] = val; ++ ++ /* cache gpio regs */ ++ if (reg >= AC97_GPIO_CFG && reg <= AC97_MISC_AFE) ++ wm->gpio[(reg - AC97_GPIO_CFG) >> 1] = val; ++ ++ /* wm9713 irq reg */ ++ if (reg == 0x5a) ++ wm->misc = val; ++ ++ if (wm->ac97) ++ wm->ac97->bus->ops->write(wm->ac97, reg, val); ++} ++EXPORT_SYMBOL_GPL(wm97xx_reg_write); ++ ++/** ++ * wm97xx_read_aux_adc - Read the aux adc. ++ * @wm: wm97xx device. ++ * @adcsel: codec ADC to be read ++ * ++ * Reads the selected AUX ADC. ++ */ ++ ++int wm97xx_read_aux_adc(struct wm97xx *wm, u16 adcsel) ++{ ++ int power_adc = 0, auxval; ++ u16 power = 0; ++ ++ /* get codec */ ++ mutex_lock(&wm->codec_mutex); ++ ++ /* When the touchscreen is not in use, we may have to power up ++ * the AUX ADC before we can use sample the AUX inputs-> ++ */ ++ if (wm->id == WM9713_ID2 && ++ (power = wm97xx_reg_read(wm, AC97_EXTENDED_MID)) & 0x8000) { ++ power_adc = 1; ++ wm97xx_reg_write(wm, AC97_EXTENDED_MID, power & 0x7fff); ++ } ++ ++ /* Prepare the codec for AUX reading */ ++ wm->codec->aux_prepare(wm); ++ ++ /* Turn polling mode on to read AUX ADC */ ++ wm->pen_probably_down = 1; ++ wm->codec->poll_sample(wm, adcsel, &auxval); ++ ++ if (power_adc) ++ wm97xx_reg_write(wm, AC97_EXTENDED_MID, power | 0x8000); ++ ++ wm->codec->dig_restore(wm); ++ ++ wm->pen_probably_down = 0; ++ ++ mutex_unlock(&wm->codec_mutex); ++ return auxval & 0xfff; ++} ++EXPORT_SYMBOL_GPL(wm97xx_read_aux_adc); ++ ++/** ++ * wm97xx_get_gpio - Get the status of a codec GPIO. ++ * @wm: wm97xx device. ++ * @gpio: gpio ++ * ++ * Get the status of a codec GPIO pin ++ */ ++ ++enum wm97xx_gpio_status wm97xx_get_gpio(struct wm97xx *wm, u32 gpio) ++{ ++ u16 status; ++ enum wm97xx_gpio_status ret; ++ ++ mutex_lock(&wm->codec_mutex); ++ status = wm97xx_reg_read(wm, AC97_GPIO_STATUS); ++ ++ if (status & gpio) ++ ret = WM97XX_GPIO_HIGH; ++ else ++ ret = WM97XX_GPIO_LOW; ++ ++ mutex_unlock(&wm->codec_mutex); ++ return ret; ++} ++EXPORT_SYMBOL_GPL(wm97xx_get_gpio); ++ ++/** ++ * wm97xx_set_gpio - Set the status of a codec GPIO. ++ * @wm: wm97xx device. ++ * @gpio: gpio ++ * ++ * ++ * Set the status of a codec GPIO pin ++ */ ++ ++void wm97xx_set_gpio(struct wm97xx *wm, u32 gpio, ++ enum wm97xx_gpio_status status) ++{ ++ u16 reg; ++ ++ mutex_lock(&wm->codec_mutex); ++ reg = wm97xx_reg_read(wm, AC97_GPIO_STATUS); ++ ++ if (status & WM97XX_GPIO_HIGH) ++ reg |= gpio; ++ else ++ reg &= ~gpio; ++ ++ if (wm->id == WM9712_ID2) ++ wm97xx_reg_write(wm, AC97_GPIO_STATUS, reg << 1); ++ else ++ wm97xx_reg_write(wm, AC97_GPIO_STATUS, reg); ++ mutex_unlock(&wm->codec_mutex); ++} ++EXPORT_SYMBOL_GPL(wm97xx_set_gpio); ++ ++/* ++ * Codec GPIO pin configuration, this sets pin direction, polarity, ++ * stickyness and wake up. ++ */ ++void wm97xx_config_gpio(struct wm97xx *wm, u32 gpio, enum wm97xx_gpio_dir dir, ++ enum wm97xx_gpio_pol pol, enum wm97xx_gpio_sticky sticky, ++ enum wm97xx_gpio_wake wake) ++{ ++ u16 reg; ++ ++ mutex_lock(&wm->codec_mutex); ++ reg = wm97xx_reg_read(wm, AC97_GPIO_POLARITY); ++ ++ if (pol == WM97XX_GPIO_POL_HIGH) ++ reg |= gpio; ++ else ++ reg &= ~gpio; ++ ++ wm97xx_reg_write(wm, AC97_GPIO_POLARITY, reg); ++ reg = wm97xx_reg_read(wm, AC97_GPIO_STICKY); ++ ++ if (sticky == WM97XX_GPIO_STICKY) ++ reg |= gpio; ++ else ++ reg &= ~gpio; ++ ++ wm97xx_reg_write(wm, AC97_GPIO_STICKY, reg); ++ reg = wm97xx_reg_read(wm, AC97_GPIO_WAKEUP); ++ ++ if (wake == WM97XX_GPIO_WAKE) ++ reg |= gpio; ++ else ++ reg &= ~gpio; ++ ++ wm97xx_reg_write(wm, AC97_GPIO_WAKEUP, reg); ++ reg = wm97xx_reg_read(wm, AC97_GPIO_CFG); ++ ++ if (dir == WM97XX_GPIO_IN) ++ reg |= gpio; ++ else ++ reg &= ~gpio; ++ ++ wm97xx_reg_write(wm, AC97_GPIO_CFG, reg); ++ mutex_unlock(&wm->codec_mutex); ++} ++EXPORT_SYMBOL_GPL(wm97xx_config_gpio); ++ ++/* ++ * Handle a pen down interrupt. ++ */ ++static void wm97xx_pen_irq_worker(struct work_struct *work) ++{ ++ struct wm97xx *wm = container_of(work, struct wm97xx, pen_event_work); ++ ++ /* do we need to enable the touch panel reader */ ++ if (wm->id == WM9705_ID2) { ++ if (wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD) & ++ WM97XX_PEN_DOWN) ++ wm->pen_is_down = 1; ++ else ++ wm->pen_is_down = 0; ++ } else { ++ u16 status, pol; ++ mutex_lock(&wm->codec_mutex); ++ status = wm97xx_reg_read(wm, AC97_GPIO_STATUS); ++ pol = wm97xx_reg_read(wm, AC97_GPIO_POLARITY); ++ ++ if (WM97XX_GPIO_13 & pol & status) { ++ wm->pen_is_down = 1; ++ wm97xx_reg_write(wm, AC97_GPIO_POLARITY, pol & ++ ~WM97XX_GPIO_13); ++ } else { ++ wm->pen_is_down = 0; ++ wm97xx_reg_write(wm, AC97_GPIO_POLARITY, pol | ++ WM97XX_GPIO_13); ++ } ++ ++ if (wm->id == WM9712_ID2) ++ wm97xx_reg_write(wm, AC97_GPIO_STATUS, (status & ++ ~WM97XX_GPIO_13) << 1); ++ else ++ wm97xx_reg_write(wm, AC97_GPIO_STATUS, status & ++ ~WM97XX_GPIO_13); ++ mutex_unlock(&wm->codec_mutex); ++ } ++ ++ queue_delayed_work(wm->ts_workq, &wm->ts_reader, 0); ++ ++ if (!wm->pen_is_down && wm->mach_ops && wm->mach_ops->acc_enabled) ++ wm->mach_ops->acc_pen_up(wm); ++ wm->mach_ops->irq_enable(wm, 1); ++} ++ ++/* ++ * Codec PENDOWN irq handler ++ * ++ * We have to disable the codec interrupt in the handler because it can ++ * take upto 1ms to clear the interrupt source. The interrupt is then enabled ++ * again in the slow handler when the source has been cleared. ++ */ ++static irqreturn_t wm97xx_pen_interrupt(int irq, void *dev_id) ++{ ++ struct wm97xx *wm = dev_id; ++ wm->mach_ops->irq_enable(wm, 0); ++ queue_work(wm->ts_workq, &wm->pen_event_work); ++ return IRQ_HANDLED; ++} ++ ++/* ++ * initialise pen IRQ handler and workqueue ++ */ ++static int wm97xx_init_pen_irq(struct wm97xx *wm) ++{ ++ u16 reg; ++ ++ /* If an interrupt is supplied an IRQ enable operation must also be ++ * provided. */ ++ BUG_ON(!wm->mach_ops->irq_enable); ++ ++ INIT_WORK(&wm->pen_event_work, wm97xx_pen_irq_worker); ++ ++ if (request_irq(wm->pen_irq, wm97xx_pen_interrupt, IRQF_SHARED, ++ "wm97xx-pen", wm)) { ++ dev_err(wm->dev, ++ "Failed to register pen down interrupt, polling"); ++ wm->pen_irq = 0; ++ return -EINVAL; ++ } ++ ++ /* enable PEN down on wm9712/13 */ ++ if (wm->id != WM9705_ID2) { ++ reg = wm97xx_reg_read(wm, AC97_MISC_AFE); ++ wm97xx_reg_write(wm, AC97_MISC_AFE, reg & 0xfffb); ++ reg = wm97xx_reg_read(wm, 0x5a); ++ wm97xx_reg_write(wm, 0x5a, reg & ~0x0001); ++ } ++ ++ return 0; ++} ++ ++static int wm97xx_read_samples(struct wm97xx *wm) ++{ ++ struct wm97xx_data data; ++ int rc; ++ ++ mutex_lock(&wm->codec_mutex); ++ ++ if (wm->mach_ops && wm->mach_ops->acc_enabled) ++ rc = wm->mach_ops->acc_pen_down(wm); ++ else ++ rc = wm->codec->poll_touch(wm, &data); ++ ++ if (rc & RC_PENUP) { ++ if (wm->pen_is_down) { ++ wm->pen_is_down = 0; ++ dev_dbg(wm->dev, "pen up\n"); ++ input_report_abs(wm->input_dev, ABS_PRESSURE, 0); ++ input_sync(wm->input_dev); ++ } else if (!(rc & RC_AGAIN)) { ++ /* We need high frequency updates only while ++ * pen is down, the user never will be able to ++ * touch screen faster than a few times per ++ * second... On the other hand, when the user ++ * is actively working with the touchscreen we ++ * don't want to lose the quick response. So we ++ * will slowly increase sleep time after the ++ * pen is up and quicky restore it to ~one task ++ * switch when pen is down again. ++ */ ++ if (wm->ts_reader_interval < HZ / 10) ++ wm->ts_reader_interval++; ++ } ++ ++ } else if (rc & RC_VALID) { ++ dev_dbg(wm->dev, ++ "pen down: x=%x:%d, y=%x:%d, pressure=%x:%d\n", ++ data.x >> 12, data.x & 0xfff, data.y >> 12, ++ data.y & 0xfff, data.p >> 12, data.p & 0xfff); ++ input_report_abs(wm->input_dev, ABS_X, data.x & 0xfff); ++ input_report_abs(wm->input_dev, ABS_Y, data.y & 0xfff); ++ input_report_abs(wm->input_dev, ABS_PRESSURE, data.p & 0xfff); ++ input_sync(wm->input_dev); ++ wm->pen_is_down = 1; ++ wm->ts_reader_interval = wm->ts_reader_min_interval; ++ } else if (rc & RC_PENDOWN) { ++ dev_dbg(wm->dev, "pen down"); ++ wm->pen_is_down = 1; ++ wm->ts_reader_interval = wm->ts_reader_min_interval; ++ } ++ ++ mutex_unlock(&wm->codec_mutex); ++ return rc; ++} ++ ++/* ++* The touchscreen sample reader. ++*/ ++static void wm97xx_ts_reader(struct work_struct *work) ++{ ++ int rc; ++ struct wm97xx *wm = container_of(work, struct wm97xx, ts_reader.work); ++ ++ BUG_ON(!wm->codec); ++ ++ do { ++ rc = wm97xx_read_samples(wm); ++ } while (rc & RC_AGAIN); ++ ++ if (wm->pen_is_down || !wm->pen_irq) ++ queue_delayed_work(wm->ts_workq, &wm->ts_reader, ++ wm->ts_reader_interval); ++} ++ ++/** ++ * wm97xx_ts_input_open - Open the touch screen input device. ++ * @idev: Input device to be opened. ++ * ++ * Called by the input sub system to open a wm97xx touchscreen device. ++ * Starts the touchscreen thread and touch digitiser. ++ */ ++static int wm97xx_ts_input_open(struct input_dev *idev) ++{ ++ struct wm97xx *wm = input_get_drvdata(idev); ++ ++ wm->ts_workq = create_singlethread_workqueue("kwm97xx"); ++ if (wm->ts_workq == NULL) { ++ dev_err(wm->dev, ++ "Failed to create workqueue\n"); ++ return -EINVAL; ++ } ++ ++ /* start digitiser */ ++ if (wm->mach_ops && wm->mach_ops->acc_enabled) ++ wm->codec->acc_enable(wm, 1); ++ wm->codec->dig_enable(wm, 1); ++ ++ INIT_DELAYED_WORK(&wm->ts_reader, wm97xx_ts_reader); ++ ++ wm->ts_reader_min_interval = HZ >= 100 ? HZ / 100 : 1; ++ if (wm->ts_reader_min_interval < 1) ++ wm->ts_reader_min_interval = 1; ++ wm->ts_reader_interval = wm->ts_reader_min_interval; ++ ++ wm->pen_is_down = 0; ++ if (wm->pen_irq) ++ wm97xx_init_pen_irq(wm); ++ else ++ dev_err(wm->dev, "No IRQ specified\n"); ++ ++ /* If we either don't have an interrupt for pen down events or ++ * failed to acquire it then we need to poll. ++ */ ++ if (wm->pen_irq == 0) ++ queue_delayed_work(wm->ts_workq, &wm->ts_reader, ++ wm->ts_reader_interval); ++ ++ return 0; ++} ++ ++/** ++ * wm97xx_ts_input_close - Close the touch screen input device. ++ * @idev: Input device to be closed. ++ * ++ * Called by the input sub system to close a wm97xx touchscreen device. ++ * Kills the touchscreen thread and stops the touch digitiser. ++ */ ++ ++static void wm97xx_ts_input_close(struct input_dev *idev) ++{ ++ struct wm97xx *wm = input_get_drvdata(idev); ++ ++ if (wm->pen_irq) ++ free_irq(wm->pen_irq, wm); ++ ++ wm->pen_is_down = 0; ++ ++ /* ts_reader rearms itself so we need to explicitly stop it ++ * before we destroy the workqueue. ++ */ ++ cancel_delayed_work_sync(&wm->ts_reader); ++ destroy_workqueue(wm->ts_workq); ++ ++ /* stop digitiser */ ++ wm->codec->dig_enable(wm, 0); ++ if (wm->mach_ops && wm->mach_ops->acc_enabled) ++ wm->codec->acc_enable(wm, 0); ++} ++ ++static int wm97xx_probe(struct device *dev) ++{ ++ struct wm97xx *wm; ++ int ret = 0, id = 0; ++ ++ wm = kzalloc(sizeof(struct wm97xx), GFP_KERNEL); ++ if (!wm) ++ return -ENOMEM; ++ mutex_init(&wm->codec_mutex); ++ ++ wm->dev = dev; ++ dev->driver_data = wm; ++ wm->ac97 = to_ac97_t(dev); ++ ++ /* check that we have a supported codec */ ++ id = wm97xx_reg_read(wm, AC97_VENDOR_ID1); ++ if (id != WM97XX_ID1) { ++ dev_err(dev, "Device with vendor %04x is not a wm97xx\n", id); ++ kfree(wm); ++ return -ENODEV; ++ } ++ ++ wm->id = wm97xx_reg_read(wm, AC97_VENDOR_ID2); ++ ++ dev_info(wm->dev, "detected a wm97%02x codec", wm->id & 0xff); ++ ++ switch (wm->id & 0xff) { ++#ifdef CONFIG_TOUCHSCREEN_WM9705 ++ case 0x05: ++ wm->codec = &wm9705_codec; ++ break; ++#endif ++#ifdef CONFIG_TOUCHSCREEN_WM9712 ++ case 0x12: ++ wm->codec = &wm9712_codec; ++ break; ++#endif ++#ifdef CONFIG_TOUCHSCREEN_WM9713 ++ case 0x13: ++ wm->codec = &wm9713_codec; ++ break; ++#endif ++ default: ++ dev_err(wm->dev, "Support for wm97%02x not compiled in.\n", ++ wm->id & 0xff); ++ kfree(wm); ++ return -ENODEV; ++ } ++ ++ wm->input_dev = input_allocate_device(); ++ if (wm->input_dev == NULL) { ++ kfree(wm); ++ return -ENOMEM; ++ } ++ ++ /* set up touch configuration */ ++ wm->input_dev->name = "wm97xx touchscreen"; ++ wm->input_dev->open = wm97xx_ts_input_open; ++ wm->input_dev->close = wm97xx_ts_input_close; ++ set_bit(EV_ABS, wm->input_dev->evbit); ++ set_bit(ABS_X, wm->input_dev->absbit); ++ set_bit(ABS_Y, wm->input_dev->absbit); ++ set_bit(ABS_PRESSURE, wm->input_dev->absbit); ++ input_set_abs_params(wm->input_dev, ABS_X, abs_x[0], abs_x[1], ++ abs_x[2], 0); ++ input_set_abs_params(wm->input_dev, ABS_Y, abs_y[0], abs_y[1], ++ abs_y[2], 0); ++ input_set_abs_params(wm->input_dev, ABS_PRESSURE, abs_p[0], abs_p[1], ++ abs_p[2], 0); ++ input_set_drvdata(wm->input_dev, wm); ++ wm->input_dev->dev.parent = dev; ++ ret = input_register_device(wm->input_dev); ++ if (ret < 0) { ++ input_free_device(wm->input_dev); ++ kfree(wm); ++ return -ENOMEM; ++ } ++ ++ /* set up physical characteristics */ ++ wm->codec->phy_init(wm); ++ ++ /* load gpio cache */ ++ wm->gpio[0] = wm97xx_reg_read(wm, AC97_GPIO_CFG); ++ wm->gpio[1] = wm97xx_reg_read(wm, AC97_GPIO_POLARITY); ++ wm->gpio[2] = wm97xx_reg_read(wm, AC97_GPIO_STICKY); ++ wm->gpio[3] = wm97xx_reg_read(wm, AC97_GPIO_WAKEUP); ++ wm->gpio[4] = wm97xx_reg_read(wm, AC97_GPIO_STATUS); ++ wm->gpio[5] = wm97xx_reg_read(wm, AC97_MISC_AFE); ++ ++ /* register our battery device */ ++ wm->battery_dev = platform_device_alloc("wm97xx-battery", 0); ++ if (!wm->battery_dev) ++ goto batt_err; ++ platform_set_drvdata(wm->battery_dev, wm); ++ wm->battery_dev->dev.parent = dev; ++ ret = platform_device_register(wm->battery_dev); ++ if (ret < 0) ++ goto batt_reg_err; ++ ++ /* register our extended touch device (for machine specific ++ * extensions) */ ++ wm->touch_dev = platform_device_alloc("wm97xx-touch", 0); ++ if (!wm->touch_dev) ++ goto touch_err; ++ platform_set_drvdata(wm->touch_dev, wm); ++ wm->touch_dev->dev.parent = dev; ++ ret = platform_device_register(wm->touch_dev); ++ if (ret < 0) ++ goto touch_reg_err; ++ ++ return ret; ++ ++ touch_reg_err: ++ platform_device_put(wm->touch_dev); ++ touch_err: ++ platform_device_unregister(wm->battery_dev); ++ batt_reg_err: ++ platform_device_put(wm->battery_dev); ++ batt_err: ++ input_unregister_device(wm->input_dev); ++ kfree(wm); ++ return ret; ++} ++ ++static int wm97xx_remove(struct device *dev) ++{ ++ struct wm97xx *wm = dev_get_drvdata(dev); ++ ++ platform_device_unregister(wm->battery_dev); ++ platform_device_unregister(wm->touch_dev); ++ input_unregister_device(wm->input_dev); ++ ++ kfree(wm); ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int wm97xx_resume(struct device *dev) ++{ ++ struct wm97xx *wm = dev_get_drvdata(dev); ++ ++ /* restore digitiser and gpios */ ++ if (wm->id == WM9713_ID2) { ++ wm97xx_reg_write(wm, AC97_WM9713_DIG1, wm->dig[0]); ++ wm97xx_reg_write(wm, 0x5a, wm->misc); ++ if (wm->input_dev->users) { ++ u16 reg; ++ reg = wm97xx_reg_read(wm, AC97_EXTENDED_MID) & 0x7fff; ++ wm97xx_reg_write(wm, AC97_EXTENDED_MID, reg); ++ } ++ } ++ ++ wm97xx_reg_write(wm, AC97_WM9713_DIG2, wm->dig[1]); ++ wm97xx_reg_write(wm, AC97_WM9713_DIG3, wm->dig[2]); ++ ++ wm97xx_reg_write(wm, AC97_GPIO_CFG, wm->gpio[0]); ++ wm97xx_reg_write(wm, AC97_GPIO_POLARITY, wm->gpio[1]); ++ wm97xx_reg_write(wm, AC97_GPIO_STICKY, wm->gpio[2]); ++ wm97xx_reg_write(wm, AC97_GPIO_WAKEUP, wm->gpio[3]); ++ wm97xx_reg_write(wm, AC97_GPIO_STATUS, wm->gpio[4]); ++ wm97xx_reg_write(wm, AC97_MISC_AFE, wm->gpio[5]); ++ ++ return 0; ++} ++ ++#else ++#define wm97xx_resume NULL ++#endif ++ ++/* ++ * Machine specific operations ++ */ ++int wm97xx_register_mach_ops(struct wm97xx *wm, ++ struct wm97xx_mach_ops *mach_ops) ++{ ++ mutex_lock(&wm->codec_mutex); ++ if (wm->mach_ops) { ++ mutex_unlock(&wm->codec_mutex); ++ return -EINVAL; ++ } ++ wm->mach_ops = mach_ops; ++ mutex_unlock(&wm->codec_mutex); ++ return 0; ++} ++EXPORT_SYMBOL_GPL(wm97xx_register_mach_ops); ++ ++void wm97xx_unregister_mach_ops(struct wm97xx *wm) ++{ ++ mutex_lock(&wm->codec_mutex); ++ wm->mach_ops = NULL; ++ mutex_unlock(&wm->codec_mutex); ++} ++EXPORT_SYMBOL_GPL(wm97xx_unregister_mach_ops); ++ ++static struct device_driver wm97xx_driver = { ++ .name = "ac97", ++ .bus = &ac97_bus_type, ++ .owner = THIS_MODULE, ++ .probe = wm97xx_probe, ++ .remove = wm97xx_remove, ++ .resume = wm97xx_resume, ++}; ++ ++static int __init wm97xx_init(void) ++{ ++ return driver_register(&wm97xx_driver); ++} ++ ++static void __exit wm97xx_exit(void) ++{ ++ driver_unregister(&wm97xx_driver); ++} ++ ++module_init(wm97xx_init); ++module_exit(wm97xx_exit); ++ ++/* Module information */ ++MODULE_AUTHOR("Liam Girdwood <liam.girdwood@wolfsonmicro.com>"); ++MODULE_DESCRIPTION("WM97xx Core - Touch Screen / AUX ADC / GPIO Driver"); ++MODULE_LICENSE("GPL"); +diff --git a/include/linux/wm97xx.h b/include/linux/wm97xx.h +new file mode 100644 +index 0000000..fc6e0b3 +--- /dev/null ++++ b/include/linux/wm97xx.h +@@ -0,0 +1,309 @@ ++ ++/* ++ * Register bits and API for Wolfson WM97xx series of codecs ++ */ ++ ++#ifndef _LINUX_WM97XX_H ++#define _LINUX_WM97XX_H ++ ++#include <sound/driver.h> ++#include <sound/core.h> ++#include <sound/pcm.h> ++#include <sound/ac97_codec.h> ++#include <sound/initval.h> ++#include <linux/types.h> ++#include <linux/list.h> ++#include <linux/input.h> /* Input device layer */ ++#include <linux/platform_device.h> ++ ++/* ++ * WM97xx AC97 Touchscreen registers ++ */ ++#define AC97_WM97XX_DIGITISER1 0x76 ++#define AC97_WM97XX_DIGITISER2 0x78 ++#define AC97_WM97XX_DIGITISER_RD 0x7a ++#define AC97_WM9713_DIG1 0x74 ++#define AC97_WM9713_DIG2 AC97_WM97XX_DIGITISER1 ++#define AC97_WM9713_DIG3 AC97_WM97XX_DIGITISER2 ++ ++/* ++ * WM97xx register bits ++ */ ++#define WM97XX_POLL 0x8000 /* initiate a polling measurement */ ++#define WM97XX_ADCSEL_X 0x1000 /* x coord measurement */ ++#define WM97XX_ADCSEL_Y 0x2000 /* y coord measurement */ ++#define WM97XX_ADCSEL_PRES 0x3000 /* pressure measurement */ ++#define WM97XX_ADCSEL_MASK 0x7000 ++#define WM97XX_COO 0x0800 /* enable coordinate mode */ ++#define WM97XX_CTC 0x0400 /* enable continuous mode */ ++#define WM97XX_CM_RATE_93 0x0000 /* 93.75Hz continuous rate */ ++#define WM97XX_CM_RATE_187 0x0100 /* 187.5Hz continuous rate */ ++#define WM97XX_CM_RATE_375 0x0200 /* 375Hz continuous rate */ ++#define WM97XX_CM_RATE_750 0x0300 /* 750Hz continuous rate */ ++#define WM97XX_CM_RATE_8K 0x00f0 /* 8kHz continuous rate */ ++#define WM97XX_CM_RATE_12K 0x01f0 /* 12kHz continuous rate */ ++#define WM97XX_CM_RATE_24K 0x02f0 /* 24kHz continuous rate */ ++#define WM97XX_CM_RATE_48K 0x03f0 /* 48kHz continuous rate */ ++#define WM97XX_CM_RATE_MASK 0x03f0 ++#define WM97XX_RATE(i) (((i & 3) << 8) | ((i & 4) ? 0xf0 : 0)) ++#define WM97XX_DELAY(i) ((i << 4) & 0x00f0) /* sample delay times */ ++#define WM97XX_DELAY_MASK 0x00f0 ++#define WM97XX_SLEN 0x0008 /* slot read back enable */ ++#define WM97XX_SLT(i) ((i - 5) & 0x7) /* panel slot (5-11) */ ++#define WM97XX_SLT_MASK 0x0007 ++#define WM97XX_PRP_DETW 0x4000 /* detect on, digitise off, wake */ ++#define WM97XX_PRP_DET 0x8000 /* detect on, digitise off, no wake */ ++#define WM97XX_PRP_DET_DIG 0xc000 /* setect on, digitise on */ ++#define WM97XX_RPR 0x2000 /* wake up on pen down */ ++#define WM97XX_PEN_DOWN 0x8000 /* pen is down */ ++#define WM97XX_ADCSRC_MASK 0x7000 /* ADC source mask */ ++ ++#define WM97XX_AUX_ID1 0x8001 ++#define WM97XX_AUX_ID2 0x8002 ++#define WM97XX_AUX_ID3 0x8003 ++#define WM97XX_AUX_ID4 0x8004 ++ ++ ++/* WM9712 Bits */ ++#define WM9712_45W 0x1000 /* set for 5-wire touchscreen */ ++#define WM9712_PDEN 0x0800 /* measure only when pen down */ ++#define WM9712_WAIT 0x0200 /* wait until adc is read before next sample */ ++#define WM9712_PIL 0x0100 /* current used for pressure measurement. set 400uA else 200uA */ ++#define WM9712_MASK_HI 0x0040 /* hi on mask pin (47) stops conversions */ ++#define WM9712_MASK_EDGE 0x0080 /* rising/falling edge on pin delays sample */ ++#define WM9712_MASK_SYNC 0x00c0 /* rising/falling edge on mask initiates sample */ ++#define WM9712_RPU(i) (i&0x3f) /* internal pull up on pen detect (64k / rpu) */ ++#define WM9712_PD(i) (0x1 << i) /* power management */ ++ ++/* WM9712 Registers */ ++#define AC97_WM9712_POWER 0x24 ++#define AC97_WM9712_REV 0x58 ++ ++/* WM9705 Bits */ ++#define WM9705_PDEN 0x1000 /* measure only when pen is down */ ++#define WM9705_PINV 0x0800 /* inverts sense of pen down output */ ++#define WM9705_BSEN 0x0400 /* BUSY flag enable, pin47 is 1 when busy */ ++#define WM9705_BINV 0x0200 /* invert BUSY (pin47) output */ ++#define WM9705_WAIT 0x0100 /* wait until adc is read before next sample */ ++#define WM9705_PIL 0x0080 /* current used for pressure measurement. set 400uA else 200uA */ ++#define WM9705_PHIZ 0x0040 /* set PHONE and PCBEEP inputs to high impedance */ ++#define WM9705_MASK_HI 0x0010 /* hi on mask stops conversions */ ++#define WM9705_MASK_EDGE 0x0020 /* rising/falling edge on pin delays sample */ ++#define WM9705_MASK_SYNC 0x0030 /* rising/falling edge on mask initiates sample */ ++#define WM9705_PDD(i) (i & 0x000f) /* pen detect comparator threshold */ ++ ++ ++/* WM9713 Bits */ ++#define WM9713_PDPOL 0x0400 /* Pen down polarity */ ++#define WM9713_POLL 0x0200 /* initiate a polling measurement */ ++#define WM9713_CTC 0x0100 /* enable continuous mode */ ++#define WM9713_ADCSEL_X 0x0002 /* X measurement */ ++#define WM9713_ADCSEL_Y 0x0004 /* Y measurement */ ++#define WM9713_ADCSEL_PRES 0x0008 /* Pressure measurement */ ++#define WM9713_COO 0x0001 /* enable coordinate mode */ ++#define WM9713_PDEN 0x0800 /* measure only when pen down */ ++#define WM9713_ADCSEL_MASK 0x00fe /* ADC selection mask */ ++#define WM9713_WAIT 0x0200 /* coordinate wait */ ++ ++/* AUX ADC ID's */ ++#define TS_COMP1 0x0 ++#define TS_COMP2 0x1 ++#define TS_BMON 0x2 ++#define TS_WIPER 0x3 ++ ++/* ID numbers */ ++#define WM97XX_ID1 0x574d ++#define WM9712_ID2 0x4c12 ++#define WM9705_ID2 0x4c05 ++#define WM9713_ID2 0x4c13 ++ ++/* Codec GPIO's */ ++#define WM97XX_MAX_GPIO 16 ++#define WM97XX_GPIO_1 (1 << 1) ++#define WM97XX_GPIO_2 (1 << 2) ++#define WM97XX_GPIO_3 (1 << 3) ++#define WM97XX_GPIO_4 (1 << 4) ++#define WM97XX_GPIO_5 (1 << 5) ++#define WM97XX_GPIO_6 (1 << 6) ++#define WM97XX_GPIO_7 (1 << 7) ++#define WM97XX_GPIO_8 (1 << 8) ++#define WM97XX_GPIO_9 (1 << 9) ++#define WM97XX_GPIO_10 (1 << 10) ++#define WM97XX_GPIO_11 (1 << 11) ++#define WM97XX_GPIO_12 (1 << 12) ++#define WM97XX_GPIO_13 (1 << 13) ++#define WM97XX_GPIO_14 (1 << 14) ++#define WM97XX_GPIO_15 (1 << 15) ++ ++ ++#define AC97_LINK_FRAME 21 /* time in uS for AC97 link frame */ ++ ++ ++/*---------------- Return codes from sample reading functions ---------------*/ ++ ++/* More data is available; call the sample gathering function again */ ++#define RC_AGAIN 0x00000001 ++/* The returned sample is valid */ ++#define RC_VALID 0x00000002 ++/* The pen is up (the first RC_VALID without RC_PENUP means pen is down) */ ++#define RC_PENUP 0x00000004 ++/* The pen is down (RC_VALID implies RC_PENDOWN, but sometimes it is helpful ++ to tell the handler that the pen is down but we don't know yet his coords, ++ so the handler should not sleep or wait for pendown irq) */ ++#define RC_PENDOWN 0x00000008 ++ ++/* ++ * The wm97xx driver provides a private API for writing platform-specific ++ * drivers. ++ */ ++ ++/* The structure used to return arch specific sampled data into */ ++struct wm97xx_data { ++ int x; ++ int y; ++ int p; ++}; ++ ++/* ++ * Codec GPIO status ++ */ ++enum wm97xx_gpio_status { ++ WM97XX_GPIO_HIGH, ++ WM97XX_GPIO_LOW ++}; ++ ++/* ++ * Codec GPIO direction ++ */ ++enum wm97xx_gpio_dir { ++ WM97XX_GPIO_IN, ++ WM97XX_GPIO_OUT ++}; ++ ++/* ++ * Codec GPIO polarity ++ */ ++enum wm97xx_gpio_pol { ++ WM97XX_GPIO_POL_HIGH, ++ WM97XX_GPIO_POL_LOW ++}; ++ ++/* ++ * Codec GPIO sticky ++ */ ++enum wm97xx_gpio_sticky { ++ WM97XX_GPIO_STICKY, ++ WM97XX_GPIO_NOTSTICKY ++}; ++ ++/* ++ * Codec GPIO wake ++ */ ++enum wm97xx_gpio_wake { ++ WM97XX_GPIO_WAKE, ++ WM97XX_GPIO_NOWAKE ++}; ++ ++/* ++ * Digitiser ioctl commands ++ */ ++#define WM97XX_DIG_START 0x1 ++#define WM97XX_DIG_STOP 0x2 ++#define WM97XX_PHY_INIT 0x3 ++#define WM97XX_AUX_PREPARE 0x4 ++#define WM97XX_DIG_RESTORE 0x5 ++ ++struct wm97xx; ++ ++extern struct wm97xx_codec_drv wm9705_codec; ++extern struct wm97xx_codec_drv wm9712_codec; ++extern struct wm97xx_codec_drv wm9713_codec; ++ ++/* ++ * Codec driver interface - allows mapping to WM9705/12/13 and newer codecs ++ */ ++struct wm97xx_codec_drv { ++ u16 id; ++ char *name; ++ ++ /* read 1 sample */ ++ int (*poll_sample) (struct wm97xx *, int adcsel, int *sample); ++ ++ /* read X,Y,[P] in poll */ ++ int (*poll_touch) (struct wm97xx *, struct wm97xx_data *); ++ ++ int (*acc_enable) (struct wm97xx *, int enable); ++ void (*phy_init) (struct wm97xx *); ++ void (*dig_enable) (struct wm97xx *, int enable); ++ void (*dig_restore) (struct wm97xx *); ++ void (*aux_prepare) (struct wm97xx *); ++}; ++ ++ ++/* Machine specific and accelerated touch operations */ ++struct wm97xx_mach_ops { ++ ++ /* accelerated touch readback - coords are transmited on AC97 link */ ++ int acc_enabled; ++ void (*acc_pen_up) (struct wm97xx *); ++ int (*acc_pen_down) (struct wm97xx *); ++ int (*acc_startup) (struct wm97xx *); ++ void (*acc_shutdown) (struct wm97xx *); ++ ++ /* interrupt mask control - required for accelerated operation */ ++ void (*irq_enable) (struct wm97xx *, int enable); ++ ++ /* pre and post sample - can be used to minimise any analog noise */ ++ void (*pre_sample) (int); /* function to run before sampling */ ++ void (*post_sample) (int); /* function to run after sampling */ ++}; ++ ++struct wm97xx { ++ u16 dig[3], id, gpio[6], misc; /* Cached codec registers */ ++ u16 dig_save[3]; /* saved during aux reading */ ++ struct wm97xx_codec_drv *codec; /* attached codec driver*/ ++ struct input_dev *input_dev; /* touchscreen input device */ ++ struct snd_ac97 *ac97; /* ALSA codec access */ ++ struct device *dev; /* ALSA device */ ++ struct platform_device *battery_dev; ++ struct platform_device *touch_dev; ++ struct wm97xx_mach_ops *mach_ops; ++ struct mutex codec_mutex; ++ struct delayed_work ts_reader; /* Used to poll touchscreen */ ++ unsigned long ts_reader_interval; /* Current interval for timer */ ++ unsigned long ts_reader_min_interval; /* Minimum interval */ ++ unsigned int pen_irq; /* Pen IRQ number in use */ ++ struct workqueue_struct *ts_workq; ++ struct work_struct pen_event_work; ++ u16 acc_slot; /* AC97 slot used for acc touch data */ ++ u16 acc_rate; /* acc touch data rate */ ++ unsigned pen_is_down:1; /* Pen is down */ ++ unsigned aux_waiting:1; /* aux measurement waiting */ ++ unsigned pen_probably_down:1; /* used in polling mode */ ++}; ++ ++/* ++ * Codec GPIO access (not supported on WM9705) ++ * This can be used to set/get codec GPIO and Virtual GPIO status. ++ */ ++enum wm97xx_gpio_status wm97xx_get_gpio(struct wm97xx *wm, u32 gpio); ++void wm97xx_set_gpio(struct wm97xx *wm, u32 gpio, ++ enum wm97xx_gpio_status status); ++void wm97xx_config_gpio(struct wm97xx *wm, u32 gpio, ++ enum wm97xx_gpio_dir dir, ++ enum wm97xx_gpio_pol pol, ++ enum wm97xx_gpio_sticky sticky, ++ enum wm97xx_gpio_wake wake); ++ ++/* codec AC97 IO access */ ++int wm97xx_reg_read(struct wm97xx *wm, u16 reg); ++void wm97xx_reg_write(struct wm97xx *wm, u16 reg, u16 val); ++ ++/* aux adc readback */ ++int wm97xx_read_aux_adc(struct wm97xx *wm, u16 adcsel); ++ ++/* machine ops */ ++int wm97xx_register_mach_ops(struct wm97xx *, struct wm97xx_mach_ops *); ++void wm97xx_unregister_mach_ops(struct wm97xx *); ++ ++#endif +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0031-Add-chip-driver-for-WM9705-touchscreen.patch b/packages/linux/linux-rp-2.6.24/tosa/0031-Add-chip-driver-for-WM9705-touchscreen.patch new file mode 100644 index 0000000000..3890795f61 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0031-Add-chip-driver-for-WM9705-touchscreen.patch @@ -0,0 +1,383 @@ +From 7b366ca784d0540613a43908de803e4dedc100d3 Mon Sep 17 00:00:00 2001 +From: Mark Brown <broonie@opensource.wolfsonmicro.com> +Date: Sat, 26 Jan 2008 21:14:20 +0300 +Subject: [PATCH 31/64] Add chip driver for WM9705 touchscreen + +Signed-off-by: Liam Girdwood <liam.girdwood@wolfsonmicro.com> +Signed-off-by: Graeme Gregory <gg@opensource.wolfsonmicro.com> +Signed-off-by: Mike Arthur <mike.arthur@wolfsonmicro.com> +Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> +Cc: Dmitry Baryshkov <dbaryshkov@gmail.com> +Cc: Stanley Cai <stanley.cai@intel.com> +Cc: Rodolfo Giometti <giometti@enneenne.com> +Cc: Russell King <rmk@arm.linux.org.uk> +Cc: Marc Kleine-Budde <mkl@pengutronix.de> +Cc: Ian Molton <spyro@f2s.com> +Cc: Vince Sanders <vince@kyllikki.org> +Cc: Andrew Zabolotny <zap@homelink.ru> +--- + drivers/input/touchscreen/wm9705.c | 352 ++++++++++++++++++++++++++++++++++++ + 1 files changed, 352 insertions(+), 0 deletions(-) + create mode 100644 drivers/input/touchscreen/wm9705.c + +diff --git a/drivers/input/touchscreen/wm9705.c b/drivers/input/touchscreen/wm9705.c +new file mode 100644 +index 0000000..f185104 +--- /dev/null ++++ b/drivers/input/touchscreen/wm9705.c +@@ -0,0 +1,352 @@ ++/* ++ * wm9705.c -- Codec driver for Wolfson WM9705 AC97 Codec. ++ * ++ * Copyright 2003, 2004, 2005, 2006, 2007 Wolfson Microelectronics PLC. ++ * Author: Liam Girdwood ++ * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com ++ * Parts Copyright : Ian Molton <spyro@f2s.com> ++ * Andrew Zabolotny <zap@homelink.ru> ++ * Russell King <rmk@arm.linux.org.uk> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#include <linux/module.h> ++#include <linux/moduleparam.h> ++#include <linux/version.h> ++#include <linux/kernel.h> ++#include <linux/input.h> ++#include <linux/delay.h> ++#include <linux/bitops.h> ++#include <linux/wm97xx.h> ++ ++#define TS_NAME "wm97xx" ++#define WM9705_VERSION "0.62" ++#define DEFAULT_PRESSURE 0xb0c0 ++ ++/* ++ * Module parameters ++ */ ++ ++/* ++ * Set current used for pressure measurement. ++ * ++ * Set pil = 2 to use 400uA ++ * pil = 1 to use 200uA and ++ * pil = 0 to disable pressure measurement. ++ * ++ * This is used to increase the range of values returned by the adc ++ * when measureing touchpanel pressure. ++ */ ++static int pil; ++module_param(pil, int, 0); ++MODULE_PARM_DESC(pil, "Set current used for pressure measurement."); ++ ++/* ++ * Set threshold for pressure measurement. ++ * ++ * Pen down pressure below threshold is ignored. ++ */ ++static int pressure = DEFAULT_PRESSURE & 0xfff; ++module_param(pressure, int, 0); ++MODULE_PARM_DESC(pressure, "Set threshold for pressure measurement."); ++ ++/* ++ * Set adc sample delay. ++ * ++ * For accurate touchpanel measurements, some settling time may be ++ * required between the switch matrix applying a voltage across the ++ * touchpanel plate and the ADC sampling the signal. ++ * ++ * This delay can be set by setting delay = n, where n is the array ++ * position of the delay in the array delay_table below. ++ * Long delays > 1ms are supported for completeness, but are not ++ * recommended. ++ */ ++static int delay = 4; ++module_param(delay, int, 0); ++MODULE_PARM_DESC(delay, "Set adc sample delay."); ++ ++/* ++ * Pen detect comparator threshold. ++ * ++ * 0 to Vmid in 15 steps, 0 = use zero power comparator with Vmid threshold ++ * i.e. 1 = Vmid/15 threshold ++ * 15 = Vmid/1 threshold ++ * ++ * Adjust this value if you are having problems with pen detect not ++ * detecting any down events. ++ */ ++static int pdd = 8; ++module_param(pdd, int, 0); ++MODULE_PARM_DESC(pdd, "Set pen detect comparator threshold"); ++ ++/* ++ * Set adc mask function. ++ * ++ * Sources of glitch noise, such as signals driving an LCD display, may feed ++ * through to the touch screen plates and affect measurement accuracy. In ++ * order to minimise this, a signal may be applied to the MASK pin to delay or ++ * synchronise the sampling. ++ * ++ * 0 = No delay or sync ++ * 1 = High on pin stops conversions ++ * 2 = Edge triggered, edge on pin delays conversion by delay param (above) ++ * 3 = Edge triggered, edge on pin starts conversion after delay param ++ */ ++static int mask; ++module_param(mask, int, 0); ++MODULE_PARM_DESC(mask, "Set adc mask function."); ++ ++/* ++ * ADC sample delay times in uS ++ */ ++static const int delay_table[] = { ++ 21, /* 1 AC97 Link frames */ ++ 42, /* 2 */ ++ 84, /* 4 */ ++ 167, /* 8 */ ++ 333, /* 16 */ ++ 667, /* 32 */ ++ 1000, /* 48 */ ++ 1333, /* 64 */ ++ 2000, /* 96 */ ++ 2667, /* 128 */ ++ 3333, /* 160 */ ++ 4000, /* 192 */ ++ 4667, /* 224 */ ++ 5333, /* 256 */ ++ 6000, /* 288 */ ++ 0 /* No delay, switch matrix always on */ ++}; ++ ++/* ++ * Delay after issuing a POLL command. ++ * ++ * The delay is 3 AC97 link frames + the touchpanel settling delay ++ */ ++static inline void poll_delay(int d) ++{ ++ udelay(3 * AC97_LINK_FRAME + delay_table[d]); ++} ++ ++/* ++ * set up the physical settings of the WM9705 ++ */ ++static void wm9705_phy_init(struct wm97xx *wm) ++{ ++ u16 dig1 = 0, dig2 = WM97XX_RPR; ++ ++ /* ++ * mute VIDEO and AUX as they share X and Y touchscreen ++ * inputs on the WM9705 ++ */ ++ wm97xx_reg_write(wm, AC97_AUX, 0x8000); ++ wm97xx_reg_write(wm, AC97_VIDEO, 0x8000); ++ ++ /* touchpanel pressure current*/ ++ if (pil == 2) { ++ dig2 |= WM9705_PIL; ++ dev_dbg(wm->dev, ++ "setting pressure measurement current to 400uA."); ++ } else if (pil) ++ dev_dbg(wm->dev, ++ "setting pressure measurement current to 200uA."); ++ if (!pil) ++ pressure = 0; ++ ++ /* polling mode sample settling delay */ ++ if (delay != 4) { ++ if (delay < 0 || delay > 15) { ++ dev_dbg(wm->dev, "supplied delay out of range."); ++ delay = 4; ++ } ++ } ++ dig1 &= 0xff0f; ++ dig1 |= WM97XX_DELAY(delay); ++ dev_dbg(wm->dev, "setting adc sample delay to %d u Secs.", ++ delay_table[delay]); ++ ++ /* WM9705 pdd */ ++ dig2 |= (pdd & 0x000f); ++ dev_dbg(wm->dev, "setting pdd to Vmid/%d", 1 - (pdd & 0x000f)); ++ ++ /* mask */ ++ dig2 |= ((mask & 0x3) << 4); ++ ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, dig1); ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, dig2); ++} ++ ++static void wm9705_dig_enable(struct wm97xx *wm, int enable) ++{ ++ if (enable) { ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, ++ wm->dig[2] | WM97XX_PRP_DET_DIG); ++ wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); /* dummy read */ ++ } else ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, ++ wm->dig[2] & ~WM97XX_PRP_DET_DIG); ++} ++ ++static void wm9705_aux_prepare(struct wm97xx *wm) ++{ ++ memcpy(wm->dig_save, wm->dig, sizeof(wm->dig)); ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, 0); ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, WM97XX_PRP_DET_DIG); ++} ++ ++static void wm9705_dig_restore(struct wm97xx *wm) ++{ ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, wm->dig_save[1]); ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, wm->dig_save[2]); ++} ++ ++static inline int is_pden(struct wm97xx *wm) ++{ ++ return wm->dig[2] & WM9705_PDEN; ++} ++ ++/* ++ * Read a sample from the WM9705 adc in polling mode. ++ */ ++static int wm9705_poll_sample(struct wm97xx *wm, int adcsel, int *sample) ++{ ++ int timeout = 5 * delay; ++ ++ if (!wm->pen_probably_down) { ++ u16 data = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); ++ if (!(data & WM97XX_PEN_DOWN)) ++ return RC_PENUP; ++ wm->pen_probably_down = 1; ++ } ++ ++ /* set up digitiser */ ++ if (adcsel & 0x8000) ++ adcsel = ((adcsel & 0x7fff) + 3) << 12; ++ ++ if (wm->mach_ops && wm->mach_ops->pre_sample) ++ wm->mach_ops->pre_sample(adcsel); ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, ++ adcsel | WM97XX_POLL | WM97XX_DELAY(delay)); ++ ++ /* wait 3 AC97 time slots + delay for conversion */ ++ poll_delay(delay); ++ ++ /* wait for POLL to go low */ ++ while ((wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER1) & WM97XX_POLL) ++ && timeout) { ++ udelay(AC97_LINK_FRAME); ++ timeout--; ++ } ++ ++ if (timeout <= 0) { ++ /* If PDEN is set, we can get a timeout when pen goes up */ ++ if (is_pden(wm)) ++ wm->pen_probably_down = 0; ++ else ++ dev_dbg(wm->dev, "adc sample timeout"); ++ return RC_PENUP; ++ } ++ ++ *sample = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); ++ if (wm->mach_ops && wm->mach_ops->post_sample) ++ wm->mach_ops->post_sample(adcsel); ++ ++ /* check we have correct sample */ ++ if ((*sample & WM97XX_ADCSEL_MASK) != adcsel) { ++ dev_dbg(wm->dev, "adc wrong sample, read %x got %x", adcsel, ++ *sample & WM97XX_ADCSEL_MASK); ++ return RC_PENUP; ++ } ++ ++ if (!(*sample & WM97XX_PEN_DOWN)) { ++ wm->pen_probably_down = 0; ++ return RC_PENUP; ++ } ++ ++ return RC_VALID; ++} ++ ++/* ++ * Sample the WM9705 touchscreen in polling mode ++ */ ++static int wm9705_poll_touch(struct wm97xx *wm, struct wm97xx_data *data) ++{ ++ int rc; ++ ++ rc = wm9705_poll_sample(wm, WM97XX_ADCSEL_X, &data->x); ++ if (rc != RC_VALID) ++ return rc; ++ rc = wm9705_poll_sample(wm, WM97XX_ADCSEL_Y, &data->y); ++ if (rc != RC_VALID) ++ return rc; ++ if (pil) { ++ rc = wm9705_poll_sample(wm, WM97XX_ADCSEL_PRES, &data->p); ++ if (rc != RC_VALID) ++ return rc; ++ } else ++ data->p = DEFAULT_PRESSURE; ++ ++ return RC_VALID; ++} ++ ++/* ++ * Enable WM9705 continuous mode, i.e. touch data is streamed across ++ * an AC97 slot ++ */ ++static int wm9705_acc_enable(struct wm97xx *wm, int enable) ++{ ++ u16 dig1, dig2; ++ int ret = 0; ++ ++ dig1 = wm->dig[1]; ++ dig2 = wm->dig[2]; ++ ++ if (enable) { ++ /* continous mode */ ++ if (wm->mach_ops->acc_startup && ++ (ret = wm->mach_ops->acc_startup(wm)) < 0) ++ return ret; ++ dig1 &= ~(WM97XX_CM_RATE_MASK | WM97XX_ADCSEL_MASK | ++ WM97XX_DELAY_MASK | WM97XX_SLT_MASK); ++ dig1 |= WM97XX_CTC | WM97XX_COO | WM97XX_SLEN | ++ WM97XX_DELAY(delay) | ++ WM97XX_SLT(wm->acc_slot) | ++ WM97XX_RATE(wm->acc_rate); ++ if (pil) ++ dig1 |= WM97XX_ADCSEL_PRES; ++ dig2 |= WM9705_PDEN; ++ } else { ++ dig1 &= ~(WM97XX_CTC | WM97XX_COO | WM97XX_SLEN); ++ dig2 &= ~WM9705_PDEN; ++ if (wm->mach_ops->acc_shutdown) ++ wm->mach_ops->acc_shutdown(wm); ++ } ++ ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, dig1); ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, dig2); ++ return ret; ++} ++ ++struct wm97xx_codec_drv wm9705_codec = { ++ .id = WM9705_ID2, ++ .name = "wm9705", ++ .poll_sample = wm9705_poll_sample, ++ .poll_touch = wm9705_poll_touch, ++ .acc_enable = wm9705_acc_enable, ++ .phy_init = wm9705_phy_init, ++ .dig_enable = wm9705_dig_enable, ++ .dig_restore = wm9705_dig_restore, ++ .aux_prepare = wm9705_aux_prepare, ++}; ++EXPORT_SYMBOL_GPL(wm9705_codec); ++ ++/* Module information */ ++MODULE_AUTHOR("Liam Girdwood <liam.girdwood@wolfsonmicro.com>"); ++MODULE_DESCRIPTION("WM9705 Touch Screen Driver"); ++MODULE_LICENSE("GPL"); +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0032-Add-chip-driver-for-WM9712-touchscreen.patch b/packages/linux/linux-rp-2.6.24/tosa/0032-Add-chip-driver-for-WM9712-touchscreen.patch new file mode 100644 index 0000000000..6265910a1e --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0032-Add-chip-driver-for-WM9712-touchscreen.patch @@ -0,0 +1,492 @@ +From b2640063b8321bdfb324c00d5f0c3366ac31696b Mon Sep 17 00:00:00 2001 +From: Mark Brown <broonie@opensource.wolfsonmicro.com> +Date: Sat, 26 Jan 2008 21:14:19 +0300 +Subject: [PATCH 32/64] Add chip driver for WM9712 touchscreen + +Signed-off-by: Liam Girdwood <liam.girdwood@wolfsonmicro.com> +Signed-off-by: Graeme Gregory <gg@opensource.wolfsonmicro.com> +Signed-off-by: Mike Arthur <mike.arthur@wolfsonmicro.com> +Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> +Cc: Dmitry Baryshkov <dbaryshkov@gmail.com> +Cc: Stanley Cai <stanley.cai@intel.com> +Cc: Rodolfo Giometti <giometti@enneenne.com> +Cc: Russell King <rmk@arm.linux.org.uk> +Cc: Marc Kleine-Budde <mkl@pengutronix.de> +Cc: Ian Molton <spyro@f2s.com> +Cc: Vince Sanders <vince@kyllikki.org> +Cc: Andrew Zabolotny <zap@homelink.ru> +--- + drivers/input/touchscreen/wm9712.c | 461 ++++++++++++++++++++++++++++++++++++ + 1 files changed, 461 insertions(+), 0 deletions(-) + create mode 100644 drivers/input/touchscreen/wm9712.c + +diff --git a/drivers/input/touchscreen/wm9712.c b/drivers/input/touchscreen/wm9712.c +new file mode 100644 +index 0000000..eaab326 +--- /dev/null ++++ b/drivers/input/touchscreen/wm9712.c +@@ -0,0 +1,461 @@ ++/* ++ * wm9712.c -- Codec driver for Wolfson WM9712 AC97 Codecs. ++ * ++ * Copyright 2003, 2004, 2005, 2006, 2007 Wolfson Microelectronics PLC. ++ * Author: Liam Girdwood ++ * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com ++ * Parts Copyright : Ian Molton <spyro@f2s.com> ++ * Andrew Zabolotny <zap@homelink.ru> ++ * Russell King <rmk@arm.linux.org.uk> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#include <linux/module.h> ++#include <linux/moduleparam.h> ++#include <linux/version.h> ++#include <linux/kernel.h> ++#include <linux/input.h> ++#include <linux/delay.h> ++#include <linux/bitops.h> ++#include <linux/wm97xx.h> ++ ++#define TS_NAME "wm97xx" ++#define WM9712_VERSION "0.61" ++#define DEFAULT_PRESSURE 0xb0c0 ++ ++/* ++ * Module parameters ++ */ ++ ++/* ++ * Set internal pull up for pen detect. ++ * ++ * Pull up is in the range 1.02k (least sensitive) to 64k (most sensitive) ++ * i.e. pull up resistance = 64k Ohms / rpu. ++ * ++ * Adjust this value if you are having problems with pen detect not ++ * detecting any down event. ++ */ ++static int rpu = 8; ++module_param(rpu, int, 0); ++MODULE_PARM_DESC(rpu, "Set internal pull up resitor for pen detect."); ++ ++/* ++ * Set current used for pressure measurement. ++ * ++ * Set pil = 2 to use 400uA ++ * pil = 1 to use 200uA and ++ * pil = 0 to disable pressure measurement. ++ * ++ * This is used to increase the range of values returned by the adc ++ * when measureing touchpanel pressure. ++ */ ++static int pil; ++module_param(pil, int, 0); ++MODULE_PARM_DESC(pil, "Set current used for pressure measurement."); ++ ++/* ++ * Set threshold for pressure measurement. ++ * ++ * Pen down pressure below threshold is ignored. ++ */ ++static int pressure = DEFAULT_PRESSURE & 0xfff; ++module_param(pressure, int, 0); ++MODULE_PARM_DESC(pressure, "Set threshold for pressure measurement."); ++ ++/* ++ * Set adc sample delay. ++ * ++ * For accurate touchpanel measurements, some settling time may be ++ * required between the switch matrix applying a voltage across the ++ * touchpanel plate and the ADC sampling the signal. ++ * ++ * This delay can be set by setting delay = n, where n is the array ++ * position of the delay in the array delay_table below. ++ * Long delays > 1ms are supported for completeness, but are not ++ * recommended. ++ */ ++static int delay = 3; ++module_param(delay, int, 0); ++MODULE_PARM_DESC(delay, "Set adc sample delay."); ++ ++/* ++ * Set five_wire = 1 to use a 5 wire touchscreen. ++ * ++ * NOTE: Five wire mode does not allow for readback of pressure. ++ */ ++static int five_wire; ++module_param(five_wire, int, 0); ++MODULE_PARM_DESC(five_wire, "Set to '1' to use 5-wire touchscreen."); ++ ++/* ++ * Set adc mask function. ++ * ++ * Sources of glitch noise, such as signals driving an LCD display, may feed ++ * through to the touch screen plates and affect measurement accuracy. In ++ * order to minimise this, a signal may be applied to the MASK pin to delay or ++ * synchronise the sampling. ++ * ++ * 0 = No delay or sync ++ * 1 = High on pin stops conversions ++ * 2 = Edge triggered, edge on pin delays conversion by delay param (above) ++ * 3 = Edge triggered, edge on pin starts conversion after delay param ++ */ ++static int mask; ++module_param(mask, int, 0); ++MODULE_PARM_DESC(mask, "Set adc mask function."); ++ ++/* ++ * Coordinate Polling Enable. ++ * ++ * Set to 1 to enable coordinate polling. e.g. x,y[,p] is sampled together ++ * for every poll. ++ */ ++static int coord; ++module_param(coord, int, 0); ++MODULE_PARM_DESC(coord, "Polling coordinate mode"); ++ ++/* ++ * ADC sample delay times in uS ++ */ ++static const int delay_table[] = { ++ 21, /* 1 AC97 Link frames */ ++ 42, /* 2 */ ++ 84, /* 4 */ ++ 167, /* 8 */ ++ 333, /* 16 */ ++ 667, /* 32 */ ++ 1000, /* 48 */ ++ 1333, /* 64 */ ++ 2000, /* 96 */ ++ 2667, /* 128 */ ++ 3333, /* 160 */ ++ 4000, /* 192 */ ++ 4667, /* 224 */ ++ 5333, /* 256 */ ++ 6000, /* 288 */ ++ 0 /* No delay, switch matrix always on */ ++}; ++ ++/* ++ * Delay after issuing a POLL command. ++ * ++ * The delay is 3 AC97 link frames + the touchpanel settling delay ++ */ ++static inline void poll_delay(int d) ++{ ++ udelay(3 * AC97_LINK_FRAME + delay_table[d]); ++} ++ ++/* ++ * set up the physical settings of the WM9712 ++ */ ++static void wm9712_phy_init(struct wm97xx *wm) ++{ ++ u16 dig1 = 0; ++ u16 dig2 = WM97XX_RPR | WM9712_RPU(1); ++ ++ /* WM9712 rpu */ ++ if (rpu) { ++ dig2 &= 0xffc0; ++ dig2 |= WM9712_RPU(rpu); ++ dev_dbg(wm->dev, "setting pen detect pull-up to %d Ohms", ++ 64000 / rpu); ++ } ++ ++ /* touchpanel pressure current*/ ++ if (pil == 2) { ++ dig2 |= WM9712_PIL; ++ dev_dbg(wm->dev, ++ "setting pressure measurement current to 400uA."); ++ } else if (pil) ++ dev_dbg(wm->dev, ++ "setting pressure measurement current to 200uA."); ++ if (!pil) ++ pressure = 0; ++ ++ /* WM9712 five wire */ ++ if (five_wire) { ++ dig2 |= WM9712_45W; ++ dev_dbg(wm->dev, "setting 5-wire touchscreen mode."); ++ } ++ ++ /* polling mode sample settling delay */ ++ if (delay < 0 || delay > 15) { ++ dev_dbg(wm->dev, "supplied delay out of range."); ++ delay = 4; ++ } ++ dig1 &= 0xff0f; ++ dig1 |= WM97XX_DELAY(delay); ++ dev_dbg(wm->dev, "setting adc sample delay to %d u Secs.", ++ delay_table[delay]); ++ ++ /* mask */ ++ dig2 |= ((mask & 0x3) << 6); ++ if (mask) { ++ u16 reg; ++ /* Set GPIO4 as Mask Pin*/ ++ reg = wm97xx_reg_read(wm, AC97_MISC_AFE); ++ wm97xx_reg_write(wm, AC97_MISC_AFE, reg | WM97XX_GPIO_4); ++ reg = wm97xx_reg_read(wm, AC97_GPIO_CFG); ++ wm97xx_reg_write(wm, AC97_GPIO_CFG, reg | WM97XX_GPIO_4); ++ } ++ ++ /* wait - coord mode */ ++ if (coord) ++ dig2 |= WM9712_WAIT; ++ ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, dig1); ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, dig2); ++} ++ ++static void wm9712_dig_enable(struct wm97xx *wm, int enable) ++{ ++ u16 dig2 = wm->dig[2]; ++ ++ if (enable) { ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, ++ dig2 | WM97XX_PRP_DET_DIG); ++ wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); /* dummy read */ ++ } else ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, ++ dig2 & ~WM97XX_PRP_DET_DIG); ++} ++ ++static void wm9712_aux_prepare(struct wm97xx *wm) ++{ ++ memcpy(wm->dig_save, wm->dig, sizeof(wm->dig)); ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, 0); ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, WM97XX_PRP_DET_DIG); ++} ++ ++static void wm9712_dig_restore(struct wm97xx *wm) ++{ ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, wm->dig_save[1]); ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, wm->dig_save[2]); ++} ++ ++static inline int is_pden(struct wm97xx *wm) ++{ ++ return wm->dig[2] & WM9712_PDEN; ++} ++ ++/* ++ * Read a sample from the WM9712 adc in polling mode. ++ */ ++static int wm9712_poll_sample(struct wm97xx *wm, int adcsel, int *sample) ++{ ++ int timeout = 5 * delay; ++ ++ if (!wm->pen_probably_down) { ++ u16 data = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); ++ if (!(data & WM97XX_PEN_DOWN)) ++ return RC_PENUP; ++ wm->pen_probably_down = 1; ++ } ++ ++ /* set up digitiser */ ++ if (adcsel & 0x8000) ++ adcsel = ((adcsel & 0x7fff) + 3) << 12; ++ ++ if (wm->mach_ops && wm->mach_ops->pre_sample) ++ wm->mach_ops->pre_sample(adcsel); ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, ++ adcsel | WM97XX_POLL | WM97XX_DELAY(delay)); ++ ++ /* wait 3 AC97 time slots + delay for conversion */ ++ poll_delay(delay); ++ ++ /* wait for POLL to go low */ ++ while ((wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER1) & WM97XX_POLL) ++ && timeout) { ++ udelay(AC97_LINK_FRAME); ++ timeout--; ++ } ++ ++ if (timeout <= 0) { ++ /* If PDEN is set, we can get a timeout when pen goes up */ ++ if (is_pden(wm)) ++ wm->pen_probably_down = 0; ++ else ++ dev_dbg(wm->dev, "adc sample timeout"); ++ return RC_PENUP; ++ } ++ ++ *sample = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); ++ if (wm->mach_ops && wm->mach_ops->post_sample) ++ wm->mach_ops->post_sample(adcsel); ++ ++ /* check we have correct sample */ ++ if ((*sample & WM97XX_ADCSEL_MASK) != adcsel) { ++ dev_dbg(wm->dev, "adc wrong sample, read %x got %x", adcsel, ++ *sample & WM97XX_ADCSEL_MASK); ++ return RC_PENUP; ++ } ++ ++ if (!(*sample & WM97XX_PEN_DOWN)) { ++ wm->pen_probably_down = 0; ++ return RC_PENUP; ++ } ++ ++ return RC_VALID; ++} ++ ++/* ++ * Read a coord from the WM9712 adc in polling mode. ++ */ ++static int wm9712_poll_coord(struct wm97xx *wm, struct wm97xx_data *data) ++{ ++ int timeout = 5 * delay; ++ ++ if (!wm->pen_probably_down) { ++ u16 data_rd = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); ++ if (!(data_rd & WM97XX_PEN_DOWN)) ++ return RC_PENUP; ++ wm->pen_probably_down = 1; ++ } ++ ++ /* set up digitiser */ ++ if (wm->mach_ops && wm->mach_ops->pre_sample) ++ wm->mach_ops->pre_sample(WM97XX_ADCSEL_X | WM97XX_ADCSEL_Y); ++ ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, ++ WM97XX_COO | WM97XX_POLL | WM97XX_DELAY(delay)); ++ ++ /* wait 3 AC97 time slots + delay for conversion and read x */ ++ poll_delay(delay); ++ data->x = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); ++ /* wait for POLL to go low */ ++ while ((wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER1) & WM97XX_POLL) ++ && timeout) { ++ udelay(AC97_LINK_FRAME); ++ timeout--; ++ } ++ ++ if (timeout <= 0) { ++ /* If PDEN is set, we can get a timeout when pen goes up */ ++ if (is_pden(wm)) ++ wm->pen_probably_down = 0; ++ else ++ dev_dbg(wm->dev, "adc sample timeout"); ++ return RC_PENUP; ++ } ++ ++ /* read back y data */ ++ data->y = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); ++ if (pil) ++ data->p = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); ++ else ++ data->p = DEFAULT_PRESSURE; ++ ++ if (wm->mach_ops && wm->mach_ops->post_sample) ++ wm->mach_ops->post_sample(WM97XX_ADCSEL_X | WM97XX_ADCSEL_Y); ++ ++ /* check we have correct sample */ ++ if (!(data->x & WM97XX_ADCSEL_X) || !(data->y & WM97XX_ADCSEL_Y)) ++ goto err; ++ if (pil && !(data->p & WM97XX_ADCSEL_PRES)) ++ goto err; ++ ++ if (!(data->x & WM97XX_PEN_DOWN)) { ++ wm->pen_probably_down = 0; ++ return RC_PENUP; ++ } ++ return RC_VALID; ++err: ++ return RC_PENUP; ++} ++ ++/* ++ * Sample the WM9712 touchscreen in polling mode ++ */ ++static int wm9712_poll_touch(struct wm97xx *wm, struct wm97xx_data *data) ++{ ++ int rc; ++ ++ if (coord) { ++ rc = wm9712_poll_coord(wm, data); ++ if (rc != RC_VALID) ++ return rc; ++ } else { ++ rc = wm9712_poll_sample(wm, WM97XX_ADCSEL_X, &data->x); ++ if (rc != RC_VALID) ++ return rc; ++ ++ rc = wm9712_poll_sample(wm, WM97XX_ADCSEL_Y, &data->y); ++ if (rc != RC_VALID) ++ return rc; ++ ++ if (pil && !five_wire) { ++ rc = wm9712_poll_sample(wm, WM97XX_ADCSEL_PRES, ++ &data->p); ++ if (rc != RC_VALID) ++ return rc; ++ } else ++ data->p = DEFAULT_PRESSURE; ++ } ++ return RC_VALID; ++} ++ ++/* ++ * Enable WM9712 continuous mode, i.e. touch data is streamed across ++ * an AC97 slot ++ */ ++static int wm9712_acc_enable(struct wm97xx *wm, int enable) ++{ ++ u16 dig1, dig2; ++ int ret = 0; ++ ++ dig1 = wm->dig[1]; ++ dig2 = wm->dig[2]; ++ ++ if (enable) { ++ /* continous mode */ ++ if (wm->mach_ops->acc_startup) { ++ ret = wm->mach_ops->acc_startup(wm); ++ if (ret < 0) ++ return ret; ++ } ++ dig1 &= ~(WM97XX_CM_RATE_MASK | WM97XX_ADCSEL_MASK | ++ WM97XX_DELAY_MASK | WM97XX_SLT_MASK); ++ dig1 |= WM97XX_CTC | WM97XX_COO | WM97XX_SLEN | ++ WM97XX_DELAY(delay) | ++ WM97XX_SLT(wm->acc_slot) | ++ WM97XX_RATE(wm->acc_rate); ++ if (pil) ++ dig1 |= WM97XX_ADCSEL_PRES; ++ dig2 |= WM9712_PDEN; ++ } else { ++ dig1 &= ~(WM97XX_CTC | WM97XX_COO | WM97XX_SLEN); ++ dig2 &= ~WM9712_PDEN; ++ if (wm->mach_ops->acc_shutdown) ++ wm->mach_ops->acc_shutdown(wm); ++ } ++ ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, dig1); ++ wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, dig2); ++ return 0; ++} ++ ++struct wm97xx_codec_drv wm9712_codec = { ++ .id = WM9712_ID2, ++ .name = "wm9712", ++ .poll_sample = wm9712_poll_sample, ++ .poll_touch = wm9712_poll_touch, ++ .acc_enable = wm9712_acc_enable, ++ .phy_init = wm9712_phy_init, ++ .dig_enable = wm9712_dig_enable, ++ .dig_restore = wm9712_dig_restore, ++ .aux_prepare = wm9712_aux_prepare, ++}; ++EXPORT_SYMBOL_GPL(wm9712_codec); ++ ++/* Module information */ ++MODULE_AUTHOR("Liam Girdwood <liam.girdwood@wolfsonmicro.com>"); ++MODULE_DESCRIPTION("WM9712 Touch Screen Driver"); ++MODULE_LICENSE("GPL"); +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0033-Add-chip-driver-for-WM9713-touchscreen.patch b/packages/linux/linux-rp-2.6.24/tosa/0033-Add-chip-driver-for-WM9713-touchscreen.patch new file mode 100644 index 0000000000..a9dfa18557 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0033-Add-chip-driver-for-WM9713-touchscreen.patch @@ -0,0 +1,490 @@ +From 05b2a361eedb5461e902c73ebc6e30f9916b3a8a Mon Sep 17 00:00:00 2001 +From: Mark Brown <broonie@opensource.wolfsonmicro.com> +Date: Sat, 26 Jan 2008 21:14:19 +0300 +Subject: [PATCH 33/64] Add chip driver for WM9713 touchscreen + +Signed-off-by: Liam Girdwood <liam.girdwood@wolfsonmicro.com> +Signed-off-by: Graeme Gregory <gg@opensource.wolfsonmicro.com> +Signed-off-by: Mike Arthur <mike.arthur@wolfsonmicro.com> +Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> +Cc: Dmitry Baryshkov <dbaryshkov@gmail.com> +Cc: Stanley Cai <stanley.cai@intel.com> +Cc: Rodolfo Giometti <giometti@enneenne.com> +Cc: Russell King <rmk@arm.linux.org.uk> +Cc: Marc Kleine-Budde <mkl@pengutronix.de> +Cc: Ian Molton <spyro@f2s.com> +Cc: Vince Sanders <vince@kyllikki.org> +Cc: Andrew Zabolotny <zap@homelink.ru> +--- + drivers/input/touchscreen/wm9713.c | 459 ++++++++++++++++++++++++++++++++++++ + 1 files changed, 459 insertions(+), 0 deletions(-) + create mode 100644 drivers/input/touchscreen/wm9713.c + +diff --git a/drivers/input/touchscreen/wm9713.c b/drivers/input/touchscreen/wm9713.c +new file mode 100644 +index 0000000..5067e59 +--- /dev/null ++++ b/drivers/input/touchscreen/wm9713.c +@@ -0,0 +1,459 @@ ++/* ++ * wm9713.c -- Codec touch driver for Wolfson WM9713 AC97 Codec. ++ * ++ * Copyright 2003, 2004, 2005, 2006, 2007, 2008 Wolfson Microelectronics PLC. ++ * Author: Liam Girdwood ++ * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com ++ * Parts Copyright : Ian Molton <spyro@f2s.com> ++ * Andrew Zabolotny <zap@homelink.ru> ++ * Russell King <rmk@arm.linux.org.uk> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#include <linux/module.h> ++#include <linux/moduleparam.h> ++#include <linux/version.h> ++#include <linux/kernel.h> ++#include <linux/input.h> ++#include <linux/delay.h> ++#include <linux/bitops.h> ++#include <linux/wm97xx.h> ++ ++#define TS_NAME "wm97xx" ++#define WM9713_VERSION "0.53" ++#define DEFAULT_PRESSURE 0xb0c0 ++ ++/* ++ * Module parameters ++ */ ++ ++/* ++ * Set internal pull up for pen detect. ++ * ++ * Pull up is in the range 1.02k (least sensitive) to 64k (most sensitive) ++ * i.e. pull up resistance = 64k Ohms / rpu. ++ * ++ * Adjust this value if you are having problems with pen detect not ++ * detecting any down event. ++ */ ++static int rpu = 8; ++module_param(rpu, int, 0); ++MODULE_PARM_DESC(rpu, "Set internal pull up resitor for pen detect."); ++ ++/* ++ * Set current used for pressure measurement. ++ * ++ * Set pil = 2 to use 400uA ++ * pil = 1 to use 200uA and ++ * pil = 0 to disable pressure measurement. ++ * ++ * This is used to increase the range of values returned by the adc ++ * when measureing touchpanel pressure. ++ */ ++static int pil; ++module_param(pil, int, 0); ++MODULE_PARM_DESC(pil, "Set current used for pressure measurement."); ++ ++/* ++ * Set threshold for pressure measurement. ++ * ++ * Pen down pressure below threshold is ignored. ++ */ ++static int pressure = DEFAULT_PRESSURE & 0xfff; ++module_param(pressure, int, 0); ++MODULE_PARM_DESC(pressure, "Set threshold for pressure measurement."); ++ ++/* ++ * Set adc sample delay. ++ * ++ * For accurate touchpanel measurements, some settling time may be ++ * required between the switch matrix applying a voltage across the ++ * touchpanel plate and the ADC sampling the signal. ++ * ++ * This delay can be set by setting delay = n, where n is the array ++ * position of the delay in the array delay_table below. ++ * Long delays > 1ms are supported for completeness, but are not ++ * recommended. ++ */ ++static int delay = 4; ++module_param(delay, int, 0); ++MODULE_PARM_DESC(delay, "Set adc sample delay."); ++ ++/* ++ * Set adc mask function. ++ * ++ * Sources of glitch noise, such as signals driving an LCD display, may feed ++ * through to the touch screen plates and affect measurement accuracy. In ++ * order to minimise this, a signal may be applied to the MASK pin to delay or ++ * synchronise the sampling. ++ * ++ * 0 = No delay or sync ++ * 1 = High on pin stops conversions ++ * 2 = Edge triggered, edge on pin delays conversion by delay param (above) ++ * 3 = Edge triggered, edge on pin starts conversion after delay param ++ */ ++static int mask; ++module_param(mask, int, 0); ++MODULE_PARM_DESC(mask, "Set adc mask function."); ++ ++/* ++ * Coordinate Polling Enable. ++ * ++ * Set to 1 to enable coordinate polling. e.g. x,y[,p] is sampled together ++ * for every poll. ++ */ ++static int coord; ++module_param(coord, int, 0); ++MODULE_PARM_DESC(coord, "Polling coordinate mode"); ++ ++/* ++ * ADC sample delay times in uS ++ */ ++static const int delay_table[] = { ++ 21, /* 1 AC97 Link frames */ ++ 42, /* 2 */ ++ 84, /* 4 */ ++ 167, /* 8 */ ++ 333, /* 16 */ ++ 667, /* 32 */ ++ 1000, /* 48 */ ++ 1333, /* 64 */ ++ 2000, /* 96 */ ++ 2667, /* 128 */ ++ 3333, /* 160 */ ++ 4000, /* 192 */ ++ 4667, /* 224 */ ++ 5333, /* 256 */ ++ 6000, /* 288 */ ++ 0 /* No delay, switch matrix always on */ ++}; ++ ++/* ++ * Delay after issuing a POLL command. ++ * ++ * The delay is 3 AC97 link frames + the touchpanel settling delay ++ */ ++static inline void poll_delay(int d) ++{ ++ udelay(3 * AC97_LINK_FRAME + delay_table[d]); ++} ++ ++/* ++ * set up the physical settings of the WM9713 ++ */ ++static void wm9713_phy_init(struct wm97xx *wm) ++{ ++ u16 dig1 = 0, dig2, dig3; ++ ++ /* default values */ ++ dig2 = WM97XX_DELAY(4) | WM97XX_SLT(5); ++ dig3 = WM9712_RPU(1); ++ ++ /* rpu */ ++ if (rpu) { ++ dig3 &= 0xffc0; ++ dig3 |= WM9712_RPU(rpu); ++ dev_info(wm->dev, "setting pen detect pull-up to %d Ohms\n", ++ 64000 / rpu); ++ } ++ ++ /* touchpanel pressure */ ++ if (pil == 2) { ++ dig3 |= WM9712_PIL; ++ dev_info(wm->dev, ++ "setting pressure measurement current to 400uA."); ++ } else if (pil) ++ dev_info(wm->dev, ++ "setting pressure measurement current to 200uA."); ++ if (!pil) ++ pressure = 0; ++ ++ /* sample settling delay */ ++ if (delay < 0 || delay > 15) { ++ dev_info(wm->dev, "supplied delay out of range."); ++ delay = 4; ++ dev_info(wm->dev, "setting adc sample delay to %d u Secs.", ++ delay_table[delay]); ++ } ++ dig2 &= 0xff0f; ++ dig2 |= WM97XX_DELAY(delay); ++ ++ /* mask */ ++ dig3 |= ((mask & 0x3) << 4); ++ if (coord) ++ dig3 |= WM9713_WAIT; ++ ++ wm->misc = wm97xx_reg_read(wm, 0x5a); ++ ++ wm97xx_reg_write(wm, AC97_WM9713_DIG1, dig1); ++ wm97xx_reg_write(wm, AC97_WM9713_DIG2, dig2); ++ wm97xx_reg_write(wm, AC97_WM9713_DIG3, dig3); ++ wm97xx_reg_write(wm, AC97_GPIO_STICKY, 0x0); ++} ++ ++static void wm9713_dig_enable(struct wm97xx *wm, int enable) ++{ ++ u16 val; ++ ++ if (enable) { ++ val = wm97xx_reg_read(wm, AC97_EXTENDED_MID); ++ wm97xx_reg_write(wm, AC97_EXTENDED_MID, val & 0x7fff); ++ wm97xx_reg_write(wm, AC97_WM9713_DIG3, wm->dig[2] | ++ WM97XX_PRP_DET_DIG); ++ wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); /* dummy read */ ++ } else { ++ wm97xx_reg_write(wm, AC97_WM9713_DIG3, wm->dig[2] & ++ ~WM97XX_PRP_DET_DIG); ++ val = wm97xx_reg_read(wm, AC97_EXTENDED_MID); ++ wm97xx_reg_write(wm, AC97_EXTENDED_MID, val | 0x8000); ++ } ++} ++ ++static void wm9713_dig_restore(struct wm97xx *wm) ++{ ++ wm97xx_reg_write(wm, AC97_WM9713_DIG1, wm->dig_save[0]); ++ wm97xx_reg_write(wm, AC97_WM9713_DIG2, wm->dig_save[1]); ++ wm97xx_reg_write(wm, AC97_WM9713_DIG3, wm->dig_save[2]); ++} ++ ++static void wm9713_aux_prepare(struct wm97xx *wm) ++{ ++ memcpy(wm->dig_save, wm->dig, sizeof(wm->dig)); ++ wm97xx_reg_write(wm, AC97_WM9713_DIG1, 0); ++ wm97xx_reg_write(wm, AC97_WM9713_DIG2, 0); ++ wm97xx_reg_write(wm, AC97_WM9713_DIG3, WM97XX_PRP_DET_DIG); ++} ++ ++static inline int is_pden(struct wm97xx *wm) ++{ ++ return wm->dig[2] & WM9713_PDEN; ++} ++ ++/* ++ * Read a sample from the WM9713 adc in polling mode. ++ */ ++static int wm9713_poll_sample(struct wm97xx *wm, int adcsel, int *sample) ++{ ++ u16 dig1; ++ int timeout = 5 * delay; ++ ++ if (!wm->pen_probably_down) { ++ u16 data = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); ++ if (!(data & WM97XX_PEN_DOWN)) ++ return RC_PENUP; ++ wm->pen_probably_down = 1; ++ } ++ ++ /* set up digitiser */ ++ if (adcsel & 0x8000) ++ adcsel = 1 << ((adcsel & 0x7fff) + 3); ++ ++ dig1 = wm97xx_reg_read(wm, AC97_WM9713_DIG1); ++ dig1 &= ~WM9713_ADCSEL_MASK; ++ ++ if (wm->mach_ops && wm->mach_ops->pre_sample) ++ wm->mach_ops->pre_sample(adcsel); ++ wm97xx_reg_write(wm, AC97_WM9713_DIG1, dig1 | adcsel | WM9713_POLL); ++ ++ /* wait 3 AC97 time slots + delay for conversion */ ++ poll_delay(delay); ++ ++ /* wait for POLL to go low */ ++ while ((wm97xx_reg_read(wm, AC97_WM9713_DIG1) & WM9713_POLL) && ++ timeout) { ++ udelay(AC97_LINK_FRAME); ++ timeout--; ++ } ++ ++ if (timeout <= 0) { ++ /* If PDEN is set, we can get a timeout when pen goes up */ ++ if (is_pden(wm)) ++ wm->pen_probably_down = 0; ++ else ++ dev_dbg(wm->dev, "adc sample timeout"); ++ return RC_PENUP; ++ } ++ ++ *sample = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); ++ if (wm->mach_ops && wm->mach_ops->post_sample) ++ wm->mach_ops->post_sample(adcsel); ++ ++ /* check we have correct sample */ ++ if ((*sample & WM97XX_ADCSRC_MASK) != ffs(adcsel >> 1) << 12) { ++ dev_dbg(wm->dev, "adc wrong sample, read %x got %x", adcsel, ++ *sample & WM97XX_ADCSRC_MASK); ++ return RC_PENUP; ++ } ++ ++ if (!(*sample & WM97XX_PEN_DOWN)) { ++ wm->pen_probably_down = 0; ++ return RC_PENUP; ++ } ++ ++ return RC_VALID; ++} ++ ++/* ++ * Read a coordinate from the WM9713 adc in polling mode. ++ */ ++static int wm9713_poll_coord(struct wm97xx *wm, struct wm97xx_data *data) ++{ ++ u16 dig1; ++ int timeout = 5 * delay; ++ ++ if (!wm->pen_probably_down) { ++ u16 data = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); ++ if (!(data & WM97XX_PEN_DOWN)) ++ return RC_PENUP; ++ wm->pen_probably_down = 1; ++ } ++ ++ /* set up digitiser */ ++ dig1 = wm97xx_reg_read(wm, AC97_WM9713_DIG1); ++ dig1 &= ~WM9713_ADCSEL_MASK; ++ if (pil) ++ dig1 |= WM97XX_ADCSEL_PRES; ++ ++ if (wm->mach_ops && wm->mach_ops->pre_sample) ++ wm->mach_ops->pre_sample(WM97XX_ADCSEL_X | WM97XX_ADCSEL_Y); ++ wm97xx_reg_write(wm, AC97_WM9713_DIG1, ++ dig1 | WM9713_POLL | WM9713_COO); ++ ++ /* wait 3 AC97 time slots + delay for conversion */ ++ poll_delay(delay); ++ data->x = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); ++ /* wait for POLL to go low */ ++ while ((wm97xx_reg_read(wm, AC97_WM9713_DIG1) & WM9713_POLL) ++ && timeout) { ++ udelay(AC97_LINK_FRAME); ++ timeout--; ++ } ++ ++ if (timeout <= 0) { ++ /* If PDEN is set, we can get a timeout when pen goes up */ ++ if (is_pden(wm)) ++ wm->pen_probably_down = 0; ++ else ++ dev_dbg(wm->dev, "adc sample timeout"); ++ return RC_PENUP; ++ } ++ ++ /* read back data */ ++ data->y = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); ++ if (pil) ++ data->p = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); ++ else ++ data->p = DEFAULT_PRESSURE; ++ ++ if (wm->mach_ops && wm->mach_ops->post_sample) ++ wm->mach_ops->post_sample(WM97XX_ADCSEL_X | WM97XX_ADCSEL_Y); ++ ++ /* check we have correct sample */ ++ if (!(data->x & WM97XX_ADCSEL_X) || !(data->y & WM97XX_ADCSEL_Y)) ++ goto err; ++ if (pil && !(data->p & WM97XX_ADCSEL_PRES)) ++ goto err; ++ ++ if (!(data->x & WM97XX_PEN_DOWN)) { ++ wm->pen_probably_down = 0; ++ return RC_PENUP; ++ } ++ return RC_VALID; ++err: ++ return RC_PENUP; ++} ++ ++/* ++ * Sample the WM9713 touchscreen in polling mode ++ */ ++static int wm9713_poll_touch(struct wm97xx *wm, struct wm97xx_data *data) ++{ ++ int rc; ++ ++ if (coord) { ++ rc = wm9713_poll_coord(wm, data); ++ if (rc != RC_VALID) ++ return rc; ++ } else { ++ rc = wm9713_poll_sample(wm, WM9713_ADCSEL_X, &data->x); ++ if (rc != RC_VALID) ++ return rc; ++ rc = wm9713_poll_sample(wm, WM9713_ADCSEL_Y, &data->y); ++ if (rc != RC_VALID) ++ return rc; ++ if (pil) { ++ rc = wm9713_poll_sample(wm, WM9713_ADCSEL_PRES, ++ &data->p); ++ if (rc != RC_VALID) ++ return rc; ++ } else ++ data->p = DEFAULT_PRESSURE; ++ } ++ return RC_VALID; ++} ++ ++/* ++ * Enable WM9713 continuous mode, i.e. touch data is streamed across ++ * an AC97 slot ++ */ ++static int wm9713_acc_enable(struct wm97xx *wm, int enable) ++{ ++ u16 dig1, dig2, dig3; ++ int ret = 0; ++ ++ dig1 = wm->dig[0]; ++ dig2 = wm->dig[1]; ++ dig3 = wm->dig[2]; ++ ++ if (enable) { ++ /* continous mode */ ++ if (wm->mach_ops->acc_startup && ++ (ret = wm->mach_ops->acc_startup(wm)) < 0) ++ return ret; ++ ++ dig1 &= ~WM9713_ADCSEL_MASK; ++ dig1 |= WM9713_CTC | WM9713_COO | WM9713_ADCSEL_X | ++ WM9713_ADCSEL_Y; ++ if (pil) ++ dig1 |= WM9713_ADCSEL_PRES; ++ dig2 &= ~(WM97XX_DELAY_MASK | WM97XX_SLT_MASK | ++ WM97XX_CM_RATE_MASK); ++ dig2 |= WM97XX_SLEN | WM97XX_DELAY(delay) | ++ WM97XX_SLT(wm->acc_slot) | WM97XX_RATE(wm->acc_rate); ++ dig3 |= WM9713_PDEN; ++ } else { ++ dig1 &= ~(WM9713_CTC | WM9713_COO); ++ dig2 &= ~WM97XX_SLEN; ++ dig3 &= ~WM9713_PDEN; ++ if (wm->mach_ops->acc_shutdown) ++ wm->mach_ops->acc_shutdown(wm); ++ } ++ ++ wm97xx_reg_write(wm, AC97_WM9713_DIG1, dig1); ++ wm97xx_reg_write(wm, AC97_WM9713_DIG2, dig2); ++ wm97xx_reg_write(wm, AC97_WM9713_DIG3, dig3); ++ return ret; ++} ++ ++struct wm97xx_codec_drv wm9713_codec = { ++ .id = WM9713_ID2, ++ .name = "wm9713", ++ .poll_sample = wm9713_poll_sample, ++ .poll_touch = wm9713_poll_touch, ++ .acc_enable = wm9713_acc_enable, ++ .phy_init = wm9713_phy_init, ++ .dig_enable = wm9713_dig_enable, ++ .dig_restore = wm9713_dig_restore, ++ .aux_prepare = wm9713_aux_prepare, ++}; ++EXPORT_SYMBOL_GPL(wm9713_codec); ++ ++/* Module information */ ++MODULE_AUTHOR("Liam Girdwood <liam.girdwood@wolfsonmicro.com>"); ++MODULE_DESCRIPTION("WM9713 Touch Screen Driver"); ++MODULE_LICENSE("GPL"); +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0034-Driver-for-WM97xx-touchscreens-in-streaming-mode-on.patch b/packages/linux/linux-rp-2.6.24/tosa/0034-Driver-for-WM97xx-touchscreens-in-streaming-mode-on.patch new file mode 100644 index 0000000000..0391cfcd83 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0034-Driver-for-WM97xx-touchscreens-in-streaming-mode-on.patch @@ -0,0 +1,329 @@ +From 821604bad5ce1ef942eeb420afd9ea2c5c92875e Mon Sep 17 00:00:00 2001 +From: Mark Brown <broonie@opensource.wolfsonmicro.com> +Date: Sat, 26 Jan 2008 21:14:19 +0300 +Subject: [PATCH 34/64] Driver for WM97xx touchscreens in streaming mode on Mainstone + +Signed-off-by: Liam Girdwood <liam.girdwood@wolfsonmicro.com> +Signed-off-by: Graeme Gregory <gg@opensource.wolfsonmicro.com> +Signed-off-by: Mike Arthur <mike.arthur@wolfsonmicro.com> +Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> +Cc: Dmitry Baryshkov <dbaryshkov@gmail.com> +Cc: Stanley Cai <stanley.cai@intel.com> +Cc: Rodolfo Giometti <giometti@enneenne.com> +Cc: Russell King <rmk@arm.linux.org.uk> +Cc: Marc Kleine-Budde <mkl@pengutronix.de> +Cc: Ian Molton <spyro@f2s.com> +Cc: Vince Sanders <vince@kyllikki.org> +Cc: Andrew Zabolotny <zap@homelink.ru> +--- + drivers/input/touchscreen/mainstone-wm97xx.c | 298 ++++++++++++++++++++++++++ + 1 files changed, 298 insertions(+), 0 deletions(-) + create mode 100644 drivers/input/touchscreen/mainstone-wm97xx.c + +diff --git a/drivers/input/touchscreen/mainstone-wm97xx.c b/drivers/input/touchscreen/mainstone-wm97xx.c +new file mode 100644 +index 0000000..8e1c35d +--- /dev/null ++++ b/drivers/input/touchscreen/mainstone-wm97xx.c +@@ -0,0 +1,298 @@ ++/* ++ * mainstone-wm97xx.c -- Mainstone Continuous Touch screen driver for ++ * Wolfson WM97xx AC97 Codecs. ++ * ++ * Copyright 2004, 2007 Wolfson Microelectronics PLC. ++ * Author: Liam Girdwood ++ * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com ++ * Parts Copyright : Ian Molton <spyro@f2s.com> ++ * Andrew Zabolotny <zap@homelink.ru> ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * Notes: ++ * This is a wm97xx extended touch driver to capture touch ++ * data in a continuous manner on the Intel XScale archictecture ++ * ++ * Features: ++ * - codecs supported:- WM9705, WM9712, WM9713 ++ * - processors supported:- Intel XScale PXA25x, PXA26x, PXA27x ++ * ++ */ ++ ++#include <linux/module.h> ++#include <linux/moduleparam.h> ++#include <linux/version.h> ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/delay.h> ++#include <linux/irq.h> ++#include <linux/interrupt.h> ++#include <linux/wm97xx.h> ++#include <linux/io.h> ++#include <asm/arch/pxa-regs.h> ++ ++#define VERSION "0.13" ++ ++struct continuous { ++ u16 id; /* codec id */ ++ u8 code; /* continuous code */ ++ u8 reads; /* number of coord reads per read cycle */ ++ u32 speed; /* number of coords per second */ ++}; ++ ++#define WM_READS(sp) ((sp / HZ) + 1) ++ ++static const struct continuous cinfo[] = { ++ {WM9705_ID2, 0, WM_READS(94), 94}, ++ {WM9705_ID2, 1, WM_READS(188), 188}, ++ {WM9705_ID2, 2, WM_READS(375), 375}, ++ {WM9705_ID2, 3, WM_READS(750), 750}, ++ {WM9712_ID2, 0, WM_READS(94), 94}, ++ {WM9712_ID2, 1, WM_READS(188), 188}, ++ {WM9712_ID2, 2, WM_READS(375), 375}, ++ {WM9712_ID2, 3, WM_READS(750), 750}, ++ {WM9713_ID2, 0, WM_READS(94), 94}, ++ {WM9713_ID2, 1, WM_READS(120), 120}, ++ {WM9713_ID2, 2, WM_READS(154), 154}, ++ {WM9713_ID2, 3, WM_READS(188), 188}, ++}; ++ ++/* continuous speed index */ ++static int sp_idx; ++static u16 last, tries; ++ ++/* ++ * Pen sampling frequency (Hz) in continuous mode. ++ */ ++static int cont_rate = 200; ++module_param(cont_rate, int, 0); ++MODULE_PARM_DESC(cont_rate, "Sampling rate in continuous mode (Hz)"); ++ ++/* ++ * Pen down detection. ++ * ++ * This driver can either poll or use an interrupt to indicate a pen down ++ * event. If the irq request fails then it will fall back to polling mode. ++ */ ++static int pen_int; ++module_param(pen_int, int, 0); ++MODULE_PARM_DESC(pen_int, "Pen down detection (1 = interrupt, 0 = polling)"); ++ ++/* ++ * Pressure readback. ++ * ++ * Set to 1 to read back pen down pressure ++ */ ++static int pressure; ++module_param(pressure, int, 0); ++MODULE_PARM_DESC(pressure, "Pressure readback (1 = pressure, 0 = no pressure)"); ++ ++/* ++ * AC97 touch data slot. ++ * ++ * Touch screen readback data ac97 slot ++ */ ++static int ac97_touch_slot = 5; ++module_param(ac97_touch_slot, int, 0); ++MODULE_PARM_DESC(ac97_touch_slot, "Touch screen data slot AC97 number"); ++ ++ ++/* flush AC97 slot 5 FIFO on pxa machines */ ++#ifdef CONFIG_PXA27x ++static void wm97xx_acc_pen_up(struct wm97xx *wm) ++{ ++ set_current_state(TASK_INTERRUPTIBLE); ++ schedule_timeout(1); ++ ++ while (MISR & (1 << 2)) ++ MODR; ++} ++#else ++static void wm97xx_acc_pen_up(struct wm97xx *wm) ++{ ++ int count = 16; ++ set_current_state(TASK_INTERRUPTIBLE); ++ schedule_timeout(1); ++ ++ while (count < 16) { ++ MODR; ++ count--; ++ } ++} ++#endif ++ ++static int wm97xx_acc_pen_down(struct wm97xx *wm) ++{ ++ u16 x, y, p = 0x100 | WM97XX_ADCSEL_PRES; ++ int reads = 0; ++ ++ /* data is never immediately available after pen down irq */ ++ set_current_state(TASK_INTERRUPTIBLE); ++ schedule_timeout(1); ++ ++ if (tries > 5) { ++ tries = 0; ++ return RC_PENUP; ++ } ++ ++ x = MODR; ++ if (x == last) { ++ tries++; ++ return RC_AGAIN; ++ } ++ last = x; ++ do { ++ if (reads) ++ x = MODR; ++ y = MODR; ++ if (pressure) ++ p = MODR; ++ ++ /* are samples valid */ ++ if ((x & 0x7000) != WM97XX_ADCSEL_X || ++ (y & 0x7000) != WM97XX_ADCSEL_Y || ++ (p & 0x7000) != WM97XX_ADCSEL_PRES) ++ goto up; ++ ++ /* coordinate is good */ ++ tries = 0; ++ input_report_abs(wm->input_dev, ABS_X, x & 0xfff); ++ input_report_abs(wm->input_dev, ABS_Y, y & 0xfff); ++ input_report_abs(wm->input_dev, ABS_PRESSURE, p & 0xfff); ++ input_sync(wm->input_dev); ++ reads++; ++ } while (reads < cinfo[sp_idx].reads); ++up: ++ return RC_PENDOWN | RC_AGAIN; ++} ++ ++static int wm97xx_acc_startup(struct wm97xx *wm) ++{ ++ int idx = 0; ++ ++ /* check we have a codec */ ++ if (wm->ac97 == NULL) ++ return -ENODEV; ++ ++ /* Go you big red fire engine */ ++ for (idx = 0; idx < ARRAY_SIZE(cinfo); idx++) { ++ if (wm->id != cinfo[idx].id) ++ continue; ++ sp_idx = idx; ++ if (cont_rate <= cinfo[idx].speed) ++ break; ++ } ++ wm->acc_rate = cinfo[sp_idx].code; ++ wm->acc_slot = ac97_touch_slot; ++ dev_info(wm->dev, ++ "mainstone accelerated touchscreen driver, %d samples/sec\n", ++ cinfo[sp_idx].speed); ++ ++ /* codec specific irq config */ ++ if (pen_int) { ++ switch (wm->id) { ++ case WM9705_ID2: ++ wm->pen_irq = IRQ_GPIO(4); ++ set_irq_type(IRQ_GPIO(4), IRQT_BOTHEDGE); ++ break; ++ case WM9712_ID2: ++ case WM9713_ID2: ++ /* enable pen down interrupt */ ++ /* use PEN_DOWN GPIO 13 to assert IRQ on GPIO line 2 */ ++ wm->pen_irq = MAINSTONE_AC97_IRQ; ++ wm97xx_config_gpio(wm, WM97XX_GPIO_13, WM97XX_GPIO_IN, ++ WM97XX_GPIO_POL_HIGH, ++ WM97XX_GPIO_STICKY, ++ WM97XX_GPIO_WAKE); ++ wm97xx_config_gpio(wm, WM97XX_GPIO_2, WM97XX_GPIO_OUT, ++ WM97XX_GPIO_POL_HIGH, ++ WM97XX_GPIO_NOTSTICKY, ++ WM97XX_GPIO_NOWAKE); ++ break; ++ default: ++ dev_err(wm->dev, ++ "pen down irq not supported on this device\n"); ++ pen_int = 0; ++ break; ++ } ++ } ++ ++ return 0; ++} ++ ++static void wm97xx_acc_shutdown(struct wm97xx *wm) ++{ ++ /* codec specific deconfig */ ++ if (pen_int) { ++ switch (wm->id & 0xffff) { ++ case WM9705_ID2: ++ wm->pen_irq = 0; ++ break; ++ case WM9712_ID2: ++ case WM9713_ID2: ++ /* disable interrupt */ ++ wm->pen_irq = 0; ++ break; ++ } ++ } ++} ++ ++static void wm97xx_irq_enable(struct wm97xx *wm, int enable) ++{ ++ if (enable) ++ enable_irq(wm->pen_irq); ++ else ++ disable_irq(wm->pen_irq); ++} ++ ++static struct wm97xx_mach_ops mainstone_mach_ops = { ++ .acc_enabled = 1, ++ .acc_pen_up = wm97xx_acc_pen_up, ++ .acc_pen_down = wm97xx_acc_pen_down, ++ .acc_startup = wm97xx_acc_startup, ++ .acc_shutdown = wm97xx_acc_shutdown, ++ .irq_enable = wm97xx_irq_enable, ++}; ++ ++static int mainstone_wm97xx_probe(struct platform_device *pdev) ++{ ++ struct wm97xx *wm = platform_get_drvdata(pdev); ++ return wm97xx_register_mach_ops(wm, &mainstone_mach_ops); ++} ++ ++static int mainstone_wm97xx_remove(struct platform_device *pdev) ++{ ++ struct wm97xx *wm = platform_get_drvdata(pdev); ++ wm97xx_unregister_mach_ops(wm); ++ return 0; ++} ++ ++static struct platform_driver mainstone_wm97xx_driver = { ++ .probe = mainstone_wm97xx_probe, ++ .remove = mainstone_wm97xx_remove, ++ .driver = { ++ .name = "wm97xx-touch", ++ }, ++}; ++ ++static int __init mainstone_wm97xx_init(void) ++{ ++ return platform_driver_register(&mainstone_wm97xx_driver); ++} ++ ++static void __exit mainstone_wm97xx_exit(void) ++{ ++ platform_driver_unregister(&mainstone_wm97xx_driver); ++} ++ ++module_init(mainstone_wm97xx_init); ++module_exit(mainstone_wm97xx_exit); ++ ++/* Module information */ ++MODULE_AUTHOR("Liam Girdwood <liam.girdwood@wolfsonmicro.com>"); ++MODULE_DESCRIPTION("wm97xx continuous touch driver for mainstone"); ++MODULE_LICENSE("GPL"); +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0035-Build-system-and-MAINTAINERS-entry-for-WM97xx-touchs.patch b/packages/linux/linux-rp-2.6.24/tosa/0035-Build-system-and-MAINTAINERS-entry-for-WM97xx-touchs.patch new file mode 100644 index 0000000000..aa0918f43e --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0035-Build-system-and-MAINTAINERS-entry-for-WM97xx-touchs.patch @@ -0,0 +1,122 @@ +From eba6a504393932764a33aae64021827dd2c5c70c Mon Sep 17 00:00:00 2001 +From: Mark Brown <broonie@opensource.wolfsonmicro.com> +Date: Sat, 26 Jan 2008 21:14:18 +0300 +Subject: [PATCH 35/64] Build system and MAINTAINERS entry for WM97xx touchscreen drivers + +Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> +Signed-off-by: Liam Girdwood <liam.girdwood@wolfsonmicro.com> +--- + MAINTAINERS | 10 +++++++ + drivers/input/touchscreen/Kconfig | 52 ++++++++++++++++++++++++++++++++++++ + drivers/input/touchscreen/Makefile | 7 +++++ + 3 files changed, 69 insertions(+), 0 deletions(-) + +diff --git a/MAINTAINERS b/MAINTAINERS +index 2340cfb..f02851c 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -4204,6 +4204,16 @@ L: linux-wireless@vger.kernel.org + W: http://oops.ghostprotocols.net:81/blog + S: Maintained + ++WM97XX TOUCHSCREEN DRIVERS ++P: Mark Brown ++M: broonie@opensource.wolfsonmicro.com ++P: Liam Girdwood ++M: liam.girdwood@wolfsonmicro.com ++L: linux-input@vger.kernel.org ++T: git git://opensource.wolfsonmicro.com/linux-2.6-touch ++W: http://opensource.wolfsonmicro.com/node/7 ++S: Supported ++ + X.25 NETWORK LAYER + P: Henner Eisen + M: eis@baty.hanse.de +diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig +index 90e8e92..0be05a2 100644 +--- a/drivers/input/touchscreen/Kconfig ++++ b/drivers/input/touchscreen/Kconfig +@@ -158,6 +158,58 @@ config TOUCHSCREEN_TOUCHRIGHT + To compile this driver as a module, choose M here: the + module will be called touchright. + ++config TOUCHSCREEN_WM97XX ++ tristate "Support for WM97xx AC97 touchscreen controllers" ++ depends on AC97_BUS ++ ++config TOUCHSCREEN_WM9705 ++ bool "WM9705 Touchscreen interface support" ++ depends on TOUCHSCREEN_WM97XX ++ help ++ Say Y here if you have a Wolfson Microelectronics WM9705 touchscreen ++ controller connected to your system. ++ ++ If unsure, say N. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called wm9705. ++ ++config TOUCHSCREEN_WM9712 ++ bool "WM9712 Touchscreen interface support" ++ depends on TOUCHSCREEN_WM97XX ++ help ++ Say Y here if you have a Wolfson Microelectronics WM9712 touchscreen ++ controller connected to your system. ++ ++ If unsure, say N. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called wm9712. ++ ++config TOUCHSCREEN_WM9713 ++ bool "WM9713 Touchscreen interface support" ++ depends on TOUCHSCREEN_WM97XX ++ help ++ Say Y here if you have a Wolfson Microelectronics WM9713 touchscreen ++ controller connected to your system. ++ ++ If unsure, say N. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called wm9713. ++ ++config TOUCHSCREEN_WM97XX_MAINSTONE ++ tristate "WM97xx Mainstone accelerated touch" ++ depends on TOUCHSCREEN_WM97XX && ARCH_PXA ++ help ++ Say Y here for support for streaming mode with WM97xx touchscreens ++ on Mainstone systems. ++ ++ If unsure, say N ++ ++ To compile this driver as a module, choose M here: the ++ module will be called mainstone-wm97xx ++ + config TOUCHSCREEN_TOUCHWIN + tristate "Touchwin serial touchscreen" + select SERIO +diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile +index 35d4097..d38156e 100644 +--- a/drivers/input/touchscreen/Makefile ++++ b/drivers/input/touchscreen/Makefile +@@ -4,6 +4,8 @@ + + # Each configuration option enables a list of files. + ++wm97xx-ts-y := wm97xx-core.o ++ + obj-$(CONFIG_TOUCHSCREEN_ADS7846) += ads7846.o + obj-$(CONFIG_TOUCHSCREEN_BITSY) += h3600_ts_input.o + obj-$(CONFIG_TOUCHSCREEN_CORGI) += corgi_ts.o +@@ -19,3 +21,8 @@ obj-$(CONFIG_TOUCHSCREEN_PENMOUNT) += penmount.o + obj-$(CONFIG_TOUCHSCREEN_TOUCHWIN) += touchwin.o + obj-$(CONFIG_TOUCHSCREEN_UCB1400) += ucb1400_ts.o + obj-$(CONFIG_TOUCHSCREEN_TSC2101) += tsc2101_ts.o ++obj-$(CONFIG_TOUCHSCREEN_WM97XX) += wm97xx-ts.o ++obj-$(CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE) += mainstone-wm97xx.o ++wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9705) += wm9705.o ++wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9712) += wm9712.o ++wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9713) += wm9713.o +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0036-Set-id-to-1-for-wm97xx-subdevices.patch b/packages/linux/linux-rp-2.6.24/tosa/0036-Set-id-to-1-for-wm97xx-subdevices.patch new file mode 100644 index 0000000000..dd10b34586 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0036-Set-id-to-1-for-wm97xx-subdevices.patch @@ -0,0 +1,35 @@ +From 9ea478cbd5473f52ca036cccc00dddad717d7861 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Wed, 30 Jan 2008 19:27:13 +0300 +Subject: [PATCH 36/64] Set id to -1 for wm97xx subdevices + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + drivers/input/touchscreen/wm97xx-core.c | 4 ++-- + 1 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/input/touchscreen/wm97xx-core.c b/drivers/input/touchscreen/wm97xx-core.c +index 27a0a99..e066acc 100644 +--- a/drivers/input/touchscreen/wm97xx-core.c ++++ b/drivers/input/touchscreen/wm97xx-core.c +@@ -592,7 +592,7 @@ static int wm97xx_probe(struct device *dev) + wm->gpio[5] = wm97xx_reg_read(wm, AC97_MISC_AFE); + + /* register our battery device */ +- wm->battery_dev = platform_device_alloc("wm97xx-battery", 0); ++ wm->battery_dev = platform_device_alloc("wm97xx-battery", -1); + if (!wm->battery_dev) + goto batt_err; + platform_set_drvdata(wm->battery_dev, wm); +@@ -603,7 +603,7 @@ static int wm97xx_probe(struct device *dev) + + /* register our extended touch device (for machine specific + * extensions) */ +- wm->touch_dev = platform_device_alloc("wm97xx-touch", 0); ++ wm->touch_dev = platform_device_alloc("wm97xx-touch", -1); + if (!wm->touch_dev) + goto touch_err; + platform_set_drvdata(wm->touch_dev, wm); +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0037-Don-t-lock-the-codec-list-in-snd_soc_dapm_new_widget.patch b/packages/linux/linux-rp-2.6.24/tosa/0037-Don-t-lock-the-codec-list-in-snd_soc_dapm_new_widget.patch new file mode 100644 index 0000000000..010194dd96 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0037-Don-t-lock-the-codec-list-in-snd_soc_dapm_new_widget.patch @@ -0,0 +1,41 @@ +From d2888c7643b07687b14a839239cbe7fc5bf565e6 Mon Sep 17 00:00:00 2001 +From: Mark Brown <broonie@opensource.wolfsonmicro.com> +Date: Mon, 14 Jan 2008 23:24:26 +0300 +Subject: [PATCH 37/64] Don't lock the codec list in snd_soc_dapm_new_widgets() + +snd_soc_dapm_new_widgets() takes the codec lock when adding new widgets, +causing lockdep warnings when applications later call down through ALSA +to adjust controls. Since widgets are only added during probe this lock +should be unneeded so don't take it. + +Thanks to Dmitry Baryshkov <dbaryshkov@gmail.com> for reporting this issue. + +Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> +Cc: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + sound/soc/soc-dapm.c | 2 -- + 1 files changed, 0 insertions(+), 2 deletions(-) + +diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c +index 29a546f..e46cdc5 100644 +--- a/sound/soc/soc-dapm.c ++++ b/sound/soc/soc-dapm.c +@@ -963,7 +963,6 @@ int snd_soc_dapm_new_widgets(struct snd_soc_codec *codec) + { + struct snd_soc_dapm_widget *w; + +- mutex_lock(&codec->mutex); + list_for_each_entry(w, &codec->dapm_widgets, list) + { + if (w->new) +@@ -998,7 +997,6 @@ int snd_soc_dapm_new_widgets(struct snd_soc_codec *codec) + } + + dapm_power_widgets(codec, SND_SOC_DAPM_STREAM_NOP); +- mutex_unlock(&codec->mutex); + return 0; + } + EXPORT_SYMBOL_GPL(snd_soc_dapm_new_widgets); +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0038-Don-t-lock-the-codec-list-in-snd_soc_dapm_new_widget.patch b/packages/linux/linux-rp-2.6.24/tosa/0038-Don-t-lock-the-codec-list-in-snd_soc_dapm_new_widget.patch new file mode 100644 index 0000000000..7a3eb61a27 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0038-Don-t-lock-the-codec-list-in-snd_soc_dapm_new_widget.patch @@ -0,0 +1,57 @@ +From 5bae1fab16c7b14a458aa90e5654fe3a1d8d960f Mon Sep 17 00:00:00 2001 +From: Mark Brown <broonie@opensource.wolfsonmicro.com> +Date: Sun, 20 Jan 2008 00:06:06 +0300 +Subject: [PATCH 38/64] Don't lock the codec list in snd_soc_dapm_new_widgets() + +On Wed, Jan 16, 2008 at 02:40:55AM +0300, Dmitry wrote: + +> I'm sorry, but I tested this patch only now. And I just got another +> message from lockdep: + +Could you give this patch a try, please? +--- + sound/soc/soc-core.c | 7 +++++-- + 1 files changed, 5 insertions(+), 2 deletions(-) + +diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c +index e6a67b5..7f3ed9f 100644 +--- a/sound/soc/soc-core.c ++++ b/sound/soc/soc-core.c +@@ -1090,7 +1090,6 @@ int snd_soc_register_card(struct snd_soc_device *socdev) + struct snd_soc_machine *machine = socdev->machine; + int ret = 0, i, ac97 = 0, err = 0; + +- mutex_lock(&codec->mutex); + for(i = 0; i < machine->num_links; i++) { + if (socdev->machine->dai_link[i].init) { + err = socdev->machine->dai_link[i].init(codec); +@@ -1116,12 +1115,14 @@ int snd_soc_register_card(struct snd_soc_device *socdev) + goto out; + } + ++ mutex_lock(&codec->mutex); + #ifdef CONFIG_SND_SOC_AC97_BUS + if (ac97) { + ret = soc_ac97_dev_register(codec); + if (ret < 0) { + printk(KERN_ERR "asoc: AC97 device register failed\n"); + snd_card_free(codec->card); ++ mutex_unlock(&codec->mutex); + goto out; + } + } +@@ -1134,8 +1135,10 @@ int snd_soc_register_card(struct snd_soc_device *socdev) + err = device_create_file(socdev->dev, &dev_attr_codec_reg); + if (err < 0) + printk(KERN_WARNING "asoc: failed to add codec sysfs entries\n"); +-out: ++ + mutex_unlock(&codec->mutex); ++ ++out: + return ret; + } + EXPORT_SYMBOL_GPL(snd_soc_register_card); +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0039-Add-generic-framework-for-managing-clocks.patch b/packages/linux/linux-rp-2.6.24/tosa/0039-Add-generic-framework-for-managing-clocks.patch new file mode 100644 index 0000000000..c09c208c6a --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0039-Add-generic-framework-for-managing-clocks.patch @@ -0,0 +1,446 @@ +From 62c9a23cfa7181369637d0b61a8e90c83c562f03 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Mon, 4 Feb 2008 03:01:06 +0300 +Subject: [PATCH 39/64] Add generic framework for managing clocks. + +Provide a generic framework that platform may choose +to support clocks api. In particular this provides +platform-independant struct clk definition, a full +implementation of clocks api and a set of functions +for registering and unregistering clocks in a safe way. + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + include/linux/clklib.h | 85 ++++++++++++++ + init/Kconfig | 7 + + kernel/Makefile | 1 + + kernel/clklib.c | 295 ++++++++++++++++++++++++++++++++++++++++++++++++ + 4 files changed, 388 insertions(+), 0 deletions(-) + create mode 100644 include/linux/clklib.h + create mode 100644 kernel/clklib.c + +diff --git a/include/linux/clklib.h b/include/linux/clklib.h +new file mode 100644 +index 0000000..4bd9b4a +--- /dev/null ++++ b/include/linux/clklib.h +@@ -0,0 +1,85 @@ ++/* ++ * Copyright (C) 2008 Dmitry Baryshkov ++ * ++ * This file is released under the GPL v2. ++ */ ++ ++#ifndef CLKLIB_H ++#define CLKLIB_H ++ ++#include <linux/list.h> ++ ++struct clk { ++ struct list_head node; ++ struct clk *parent; ++ ++ const char *name; ++ struct module *owner; ++ ++ int users; ++ unsigned long rate; ++ int delay; ++ ++ int (*can_get) (struct clk *, struct device *); ++ int (*set_parent) (struct clk *, struct clk *); ++ int (*enable) (struct clk *); ++ void (*disable) (struct clk *); ++ unsigned long (*getrate) (struct clk*); ++ int (*setrate) (struct clk *, unsigned long); ++ long (*roundrate) (struct clk *, unsigned long); ++ ++ void *priv; ++}; ++ ++int clk_register(struct clk *clk); ++void clk_unregister(struct clk *clk); ++static void __maybe_unused clks_register(struct clk *clks, size_t num) ++{ ++ int i; ++ for (i = 0; i < num; i++) { ++ clk_register(&clks[i]); ++ } ++} ++ ++ ++int clk_alloc_function(const char *parent, struct clk *clk); ++ ++struct clk_function { ++ const char *parent; ++ struct clk *clk; ++}; ++ ++#define CLK_FUNC(_clock, _function, _can_get, _data, _format) \ ++ { \ ++ .parent = _clock, \ ++ .clk = &(struct clk) { \ ++ .name= _function, \ ++ .owner = THIS_MODULE, \ ++ .can_get = _can_get, \ ++ .priv = _data, \ ++ .format = _format, \ ++ }, \ ++ } ++ ++static int __maybe_unused clk_alloc_functions( ++ struct clk_function *funcs, ++ int num) ++{ ++ int i; ++ int rc; ++ ++ for (i = 0; i < num; i++) { ++ rc = clk_alloc_function(funcs[i].parent, funcs[i].clk); ++ ++ if (rc) { ++ printk(KERN_ERR "Error allocating %s.%s function.\n", ++ funcs[i].parent, ++ funcs[i].clk->name); ++ return rc; ++ } ++ } ++ ++ return 0; ++} ++ ++#endif +diff --git a/init/Kconfig b/init/Kconfig +index b9d11a8..05b62ba 100644 +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -435,6 +435,13 @@ config CC_OPTIMIZE_FOR_SIZE + config SYSCTL + bool + ++config HAVE_CLOCK_LIB ++ bool ++ help ++ Platforms select clocklib if they use this infrastructure ++ for managing their clocks both built into SoC and provided ++ by external devices. ++ + menuconfig EMBEDDED + bool "Configure standard kernel features (for small systems)" + help +diff --git a/kernel/Makefile b/kernel/Makefile +index 6d9a87c..0b2ade7 100644 +--- a/kernel/Makefile ++++ b/kernel/Makefile +@@ -58,6 +58,7 @@ obj-$(CONFIG_TASK_DELAY_ACCT) += delayacct.o + obj-$(CONFIG_TASKSTATS) += taskstats.o tsacct.o + obj-$(CONFIG_MARKERS) += marker.o + obj-$(CONFIG_LATENCYTOP) += latencytop.o ++obj-$(CONFIG_HAVE_CLOCK_LIB) += clklib.o + + ifneq ($(CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER),y) + # According to Alan Modra <alan@linuxcare.com.au>, the -fno-omit-frame-pointer is +diff --git a/kernel/clklib.c b/kernel/clklib.c +new file mode 100644 +index 0000000..203af3d +--- /dev/null ++++ b/kernel/clklib.c +@@ -0,0 +1,295 @@ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/clk.h> ++#include <linux/clklib.h> ++#include <linux/spinlock.h> ++#include <linux/err.h> ++#include <linux/delay.h> ++ ++static LIST_HEAD(clocks); ++static DEFINE_SPINLOCK(clocks_lock); ++ ++static int __clk_register(struct clk *clk) ++{ ++ if (clk->parent && ++ !try_module_get(clk->parent->owner)) ++ return -EINVAL; ++ ++ list_add_tail(&clk->node, &clocks); ++ ++ return 0; ++} ++ ++int clk_register(struct clk *clk) ++{ ++ unsigned long flags; ++ int rc; ++ ++ spin_lock_irqsave(&clocks_lock, flags); ++ ++ rc = __clk_register(clk); ++ ++ spin_unlock_irqrestore(&clocks_lock, flags); ++ ++ return rc; ++} ++EXPORT_SYMBOL(clk_register); ++ ++void clk_unregister(struct clk *clk) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&clocks_lock, flags); ++ list_del(&clk->node); ++ if (clk->parent) ++ module_put(clk->parent->owner); ++ spin_unlock_irqrestore(&clocks_lock, flags); ++} ++EXPORT_SYMBOL(clk_unregister); ++ ++struct clk *clk_get(struct device *dev, const char *id) ++{ ++ struct clk *p, *clk = ERR_PTR(-ENOENT); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&clocks_lock, flags); ++ ++ list_for_each_entry(p, &clocks, node) { ++ if (strcmp(id, p->name) == 0 && ++ (!p->can_get || p->can_get(p, dev)) && ++ try_module_get(p->owner)) { ++ clk = p; ++ break; ++ } ++ } ++ ++ spin_unlock_irqrestore(&clocks_lock, flags); ++ ++ return clk; ++} ++EXPORT_SYMBOL(clk_get); ++ ++void clk_put(struct clk *clk) ++{ ++ unsigned long flags; ++ ++ if (!clk || IS_ERR(clk)) ++ return; ++ ++ spin_lock_irqsave(&clocks_lock, flags); ++ ++ module_put(clk->owner); ++ ++ spin_unlock_irqrestore(&clocks_lock, flags); ++} ++EXPORT_SYMBOL(clk_put); ++ ++int clk_set_parent(struct clk *clk, struct clk *parent) ++{ ++ int rc; ++ unsigned long flags; ++ ++ if (!clk || IS_ERR(clk)) ++ return -EINVAL; ++ ++ if (!clk->set_parent) ++ return -EINVAL; ++ ++ spin_lock_irqsave(&clocks_lock, flags); ++ ++ rc = clk->set_parent(clk, parent); ++ if (!rc) ++ clk->parent = parent; ++ ++ spin_unlock_irqrestore(&clocks_lock, flags); ++ ++ return rc; ++} ++EXPORT_SYMBOL(clk_set_parent); ++ ++static int __clk_enable(struct clk *clk) ++{ ++ int rc = 0; ++ ++ if (clk->parent) { ++ rc = __clk_enable(clk->parent); ++ ++ if (rc) ++ return rc; ++ } ++ ++ if (clk->users++ == 0) ++ if (clk->enable) ++ rc = clk->enable(clk); ++ ++ if (clk->delay) ++ udelay(clk->delay); ++ ++ return rc; ++} ++ ++int clk_enable(struct clk *clk) ++{ ++ unsigned long flags; ++ int rc; ++ ++ if (!clk || IS_ERR(clk)) ++ return -EINVAL; ++ ++ spin_lock_irqsave(&clocks_lock, flags); ++ ++ rc = __clk_enable(clk); ++ ++ spin_unlock_irqrestore(&clocks_lock, flags); ++ ++ return rc; ++} ++EXPORT_SYMBOL(clk_enable); ++ ++static void __clk_disable(struct clk *clk) ++{ ++ if (clk->users <= 0) { ++ WARN_ON(1); ++ return; ++ } ++ ++ if (--clk->users == 0) ++ if (clk->disable) ++ clk->disable(clk); ++ ++ if (clk->parent) ++ __clk_disable(clk->parent); ++} ++ ++void clk_disable(struct clk *clk) ++{ ++ unsigned long flags; ++ ++ if (!clk || IS_ERR(clk)) ++ return; ++ ++ spin_lock_irqsave(&clocks_lock, flags); ++ ++ __clk_disable(clk); ++ ++ spin_unlock_irqrestore(&clocks_lock, flags); ++} ++EXPORT_SYMBOL(clk_disable); ++ ++static unsigned long __clk_get_rate(struct clk *clk) ++{ ++ unsigned long rate = 0; ++ ++ for (;;) { ++ if (rate || !clk) ++ return rate; ++ ++ if (clk->getrate) ++ rate = clk->getrate(clk); ++ else if (clk->rate) ++ rate = clk->rate; ++ else ++ clk = clk->parent; ++ } ++} ++ ++unsigned long clk_get_rate(struct clk *clk) ++{ ++ unsigned long rate = 0; ++ unsigned long flags; ++ ++ if (!clk || IS_ERR(clk)) ++ return -EINVAL; ++ ++ spin_lock_irqsave(&clocks_lock, flags); ++ ++ rate = __clk_get_rate(clk); ++ ++ spin_unlock_irqrestore(&clocks_lock, flags); ++ ++ return rate; ++} ++EXPORT_SYMBOL(clk_get_rate); ++ ++long clk_round_rate(struct clk *clk, unsigned long rate) ++{ ++ long res; ++ unsigned long flags; ++ ++ if (!clk || IS_ERR(clk)) ++ return -EINVAL; ++ ++ if (!clk->roundrate) ++ return -EINVAL; ++ ++ spin_lock_irqsave(&clocks_lock, flags); ++ ++ res = clk->roundrate(clk, rate); ++ ++ spin_unlock_irqrestore(&clocks_lock, flags); ++ ++ return res; ++} ++EXPORT_SYMBOL(clk_round_rate); ++ ++int clk_set_rate(struct clk *clk, unsigned long rate) ++{ ++ int rc; ++ unsigned long flags; ++ ++ if (!clk || IS_ERR(clk)) ++ return -EINVAL; ++ ++ if (!clk->setrate) ++ return -EINVAL; ++ ++ spin_lock_irqsave(&clocks_lock, flags); ++ ++ rc = clk->setrate(clk, rate); ++ ++ spin_unlock_irqrestore(&clocks_lock, flags); ++ ++ return rc; ++} ++EXPORT_SYMBOL(clk_set_rate); ++ ++int clk_alloc_function(const char *parent, struct clk *clk) ++{ ++ int rc = 0; ++ unsigned long flags; ++ struct clk *pclk; ++ bool found = false; ++ ++ spin_lock_irqsave(&clocks_lock, flags); ++ ++ list_for_each_entry(pclk, &clocks, node) { ++ if (strcmp(parent, pclk->name) == 0 && ++ try_module_get(pclk->owner)) { ++ found = true; ++ break; ++ } ++ } ++ ++ if (!found) { ++ rc = -ENODEV; ++ goto out; ++ } ++ ++ clk->parent = pclk; ++ ++ __clk_register(clk); ++ /* ++ * We locked parent owner during search ++ * and also in __clk_register. Free one reference ++ */ ++ module_put(pclk->owner); ++ ++out: ++ if (rc) { ++ kfree(clk); ++ } ++ spin_unlock_irqrestore(&clocks_lock, flags); ++ ++ return rc; ++} ++EXPORT_SYMBOL(clk_alloc_function); +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0040-Clocklib-debugfs-support.patch b/packages/linux/linux-rp-2.6.24/tosa/0040-Clocklib-debugfs-support.patch new file mode 100644 index 0000000000..160b274f4f --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0040-Clocklib-debugfs-support.patch @@ -0,0 +1,108 @@ +From cae12d96586dac77d223559d686487ea2d457a41 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Mon, 4 Feb 2008 03:01:05 +0300 +Subject: [PATCH 40/64] Clocklib debugfs support + +Provide /sys/kernel/debug/clock to ease debugging. + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + include/linux/clklib.h | 5 +++ + kernel/clklib.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 73 insertions(+), 0 deletions(-) + +diff --git a/include/linux/clklib.h b/include/linux/clklib.h +index 4bd9b4a..f916693 100644 +--- a/include/linux/clklib.h ++++ b/include/linux/clklib.h +@@ -28,6 +28,11 @@ struct clk { + int (*setrate) (struct clk *, unsigned long); + long (*roundrate) (struct clk *, unsigned long); + ++ /* ++ * format any additional info ++ */ ++ int (*format) (struct clk *, struct seq_file *); ++ + void *priv; + }; + +diff --git a/kernel/clklib.c b/kernel/clklib.c +index 203af3d..b782220 100644 +--- a/kernel/clklib.c ++++ b/kernel/clklib.c +@@ -293,3 +293,71 @@ out: + return rc; + } + EXPORT_SYMBOL(clk_alloc_function); ++ ++#ifdef CONFIG_DEBUG_FS ++ ++#include <linux/debugfs.h> ++#include <linux/seq_file.h> ++static void dump_clocks(struct seq_file *s, struct clk *parent, int nest) ++{ ++ struct clk *clk; ++ int i; ++ ++ list_for_each_entry(clk, &clocks, node) { ++ if (clk->parent == parent) { ++ for (i = 0; i < nest; i++) ++ seq_putc(s, ' '); ++ seq_puts(s, clk->name); ++ ++ i = nest + strlen(clk->name); ++ if (i >= 16) ++ i = 15; ++ for (; i < 16; i++) ++ seq_putc(s, ' '); ++ seq_printf(s, "%c use=%d rate=%lu KHz", ++ clk->set_parent ? '*' : ' ', ++ clk->users, ++ __clk_get_rate(clk)); ++ if (clk->format) ++ clk->format(clk, s); ++ seq_putc(s, '\n'); ++ ++ dump_clocks(s, clk, nest + 1); ++ } ++ } ++} ++ ++static int clocklib_show(struct seq_file *s, void *unused) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&clocks_lock, flags); ++ ++ dump_clocks(s, NULL, 0); ++ ++ spin_unlock_irqrestore(&clocks_lock, flags); ++ ++ return 0; ++} ++ ++static int clocklib_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, clocklib_show, NULL); ++} ++ ++static struct file_operations clocklib_operations = { ++ .open = clocklib_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++static int __init clocklib_debugfs_init(void) ++{ ++ debugfs_create_file("clock", S_IFREG | S_IRUGO, ++ NULL, NULL, &clocklib_operations); ++ return 0; ++} ++subsys_initcall(clocklib_debugfs_init); ++ ++#endif /* DEBUG_FS */ +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0041-From-80a359e60c2aec59ccf4fca0a7fd20495f82b1d2-Mon-Se.patch b/packages/linux/linux-rp-2.6.24/tosa/0041-From-80a359e60c2aec59ccf4fca0a7fd20495f82b1d2-Mon-Se.patch new file mode 100644 index 0000000000..9c95c67e78 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0041-From-80a359e60c2aec59ccf4fca0a7fd20495f82b1d2-Mon-Se.patch @@ -0,0 +1,593 @@ +From 2a143b9546b01fd6c58ebaac7eb46568a17d6a41 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Tue, 12 Feb 2008 04:58:59 +0300 +Subject: [PATCH 41/64] From 80a359e60c2aec59ccf4fca0a7fd20495f82b1d2 Mon Sep 17 00:00:00 2001 + In-Reply-To: <20080207005839.GA28509@doriath.ww600.siemens.net> + References: <20080207005839.GA28509@doriath.ww600.siemens.net> + Date: Thu, 7 Feb 2008 03:35:08 +0300 + Subject: [PATCH 3/5] Use clocklib for ARM pxa sub-arch. + Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> + +--- + arch/arm/Kconfig | 1 + + arch/arm/mach-pxa/clock.c | 108 ++++++-------------------------------------- + arch/arm/mach-pxa/clock.h | 58 +++++++++++++----------- + arch/arm/mach-pxa/pxa25x.c | 64 +++++++++++++++----------- + arch/arm/mach-pxa/pxa27x.c | 61 +++++++++++++----------- + arch/arm/mach-pxa/pxa3xx.c | 91 +++++++++++++++++++++---------------- + 6 files changed, 169 insertions(+), 214 deletions(-) + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 423e953..47f3c73 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -347,6 +347,7 @@ config ARCH_PXA + select GENERIC_CLOCKEVENTS + select TICK_ONESHOT + select HAVE_GPIO_LIB ++ select HAVE_CLOCK_LIB + help + Support for Intel/Marvell's PXA2xx/PXA3xx processor line. + +diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c +index 83ef5ec..3296b02 100644 +--- a/arch/arm/mach-pxa/clock.c ++++ b/arch/arm/mach-pxa/clock.c +@@ -8,6 +8,7 @@ + #include <linux/err.h> + #include <linux/string.h> + #include <linux/clk.h> ++#include <linux/clklib.h> + #include <linux/spinlock.h> + #include <linux/platform_device.h> + #include <linux/delay.h> +@@ -19,123 +20,42 @@ + #include "generic.h" + #include "clock.h" + +-static LIST_HEAD(clocks); +-static DEFINE_MUTEX(clocks_mutex); +-static DEFINE_SPINLOCK(clocks_lock); +- +-struct clk *clk_get(struct device *dev, const char *id) +-{ +- struct clk *p, *clk = ERR_PTR(-ENOENT); +- +- mutex_lock(&clocks_mutex); +- list_for_each_entry(p, &clocks, node) { +- if (strcmp(id, p->name) == 0 && +- (p->dev == NULL || p->dev == dev)) { +- clk = p; +- break; +- } +- } +- mutex_unlock(&clocks_mutex); +- +- return clk; +-} +-EXPORT_SYMBOL(clk_get); +- +-void clk_put(struct clk *clk) ++static int clk_gpio27_enable(struct clk *clk) + { +-} +-EXPORT_SYMBOL(clk_put); +- +-int clk_enable(struct clk *clk) +-{ +- unsigned long flags; +- +- spin_lock_irqsave(&clocks_lock, flags); +- if (clk->enabled++ == 0) +- clk->ops->enable(clk); +- spin_unlock_irqrestore(&clocks_lock, flags); +- +- if (clk->delay) +- udelay(clk->delay); ++ pxa_gpio_mode(GPIO11_3_6MHz_MD); + + return 0; + } +-EXPORT_SYMBOL(clk_enable); +- +-void clk_disable(struct clk *clk) +-{ +- unsigned long flags; +- +- WARN_ON(clk->enabled == 0); +- +- spin_lock_irqsave(&clocks_lock, flags); +- if (--clk->enabled == 0) +- clk->ops->disable(clk); +- spin_unlock_irqrestore(&clocks_lock, flags); +-} +-EXPORT_SYMBOL(clk_disable); +- +-unsigned long clk_get_rate(struct clk *clk) +-{ +- unsigned long rate; +- +- rate = clk->rate; +- if (clk->ops->getrate) +- rate = clk->ops->getrate(clk); +- +- return rate; +-} +-EXPORT_SYMBOL(clk_get_rate); +- +- +-static void clk_gpio27_enable(struct clk *clk) +-{ +- pxa_gpio_mode(GPIO11_3_6MHz_MD); +-} + + static void clk_gpio27_disable(struct clk *clk) + { ++ /* FIXME: disable clock */ + } + +-static const struct clkops clk_gpio27_ops = { +- .enable = clk_gpio27_enable, +- .disable = clk_gpio27_disable, +-}; +- +- +-void clk_cken_enable(struct clk *clk) ++int clk_cken_enable(struct clk *clk) + { +- CKEN |= 1 << clk->cken; ++ int cken = ((struct clk_cken_priv *)clk->priv)->cken; ++ CKEN |= 1 << cken; ++ ++ return 0; + } + + void clk_cken_disable(struct clk *clk) + { +- CKEN &= ~(1 << clk->cken); ++ int cken = ((struct clk_cken_priv *)clk->priv)->cken; ++ CKEN &= ~(1 << cken); + } + +-const struct clkops clk_cken_ops = { +- .enable = clk_cken_enable, +- .disable = clk_cken_disable, +-}; +- + static struct clk common_clks[] = { + { + .name = "GPIO27_CLK", +- .ops = &clk_gpio27_ops, + .rate = 3686400, ++ .owner = THIS_MODULE, ++ .enable = clk_gpio27_enable, ++ .disable = clk_gpio27_disable, + }, + }; + +-void clks_register(struct clk *clks, size_t num) +-{ +- int i; +- +- mutex_lock(&clocks_mutex); +- for (i = 0; i < num; i++) +- list_add(&clks[i].node, &clocks); +- mutex_unlock(&clocks_mutex); +-} +- + static int __init clk_init(void) + { + clks_register(common_clks, ARRAY_SIZE(common_clks)); +diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h +index bc6b77e..5d0d067 100644 +--- a/arch/arm/mach-pxa/clock.h ++++ b/arch/arm/mach-pxa/clock.h +@@ -1,43 +1,47 @@ +-struct clk; ++#include <linux/clklib.h> ++#include <linux/seq_file.h> + +-struct clkops { +- void (*enable)(struct clk *); +- void (*disable)(struct clk *); +- unsigned long (*getrate)(struct clk *); ++struct clk_cken_priv { ++ unsigned int cken; + }; + +-struct clk { +- struct list_head node; +- const char *name; +- struct device *dev; +- const struct clkops *ops; +- unsigned long rate; +- unsigned int cken; +- unsigned int delay; +- unsigned int enabled; +-}; +- +-#define INIT_CKEN(_name, _cken, _rate, _delay, _dev) \ ++#define INIT_CKEN(_name, _cken, _rate, _delay) \ + { \ + .name = _name, \ +- .dev = _dev, \ +- .ops = &clk_cken_ops, \ ++ .enable = clk_cken_enable, \ ++ .disable = clk_cken_disable, \ + .rate = _rate, \ +- .cken = CKEN_##_cken, \ + .delay = _delay, \ ++ .priv = &(struct clk_cken_priv) { \ ++ .cken = CKEN_##_cken, \ ++ }, \ + } + +-#define INIT_CK(_name, _cken, _ops, _dev) \ ++#define INIT_CK(_name, _cken, _getrate) \ + { \ + .name = _name, \ +- .dev = _dev, \ +- .ops = _ops, \ +- .cken = CKEN_##_cken, \ ++ .enable = clk_cken_enable, \ ++ .disable = clk_cken_disable, \ ++ .getrate = _getrate, \ ++ .priv = &(struct clk_cken_priv) { \ ++ .cken = CKEN_##_cken, \ ++ }, \ + } + +-extern const struct clkops clk_cken_ops; +- +-void clk_cken_enable(struct clk *clk); ++int clk_cken_enable(struct clk *clk); + void clk_cken_disable(struct clk *clk); + + void clks_register(struct clk *clks, size_t num); ++ ++static int __maybe_unused clk_dev_can_get(struct clk *clk, struct device *dev) ++{ ++ return (dev == clk->priv); ++} ++ ++static int __maybe_unused clk_dev_format(struct clk *clk, struct seq_file *s) ++{ ++ BUG_ON(!clk->priv); ++ seq_puts(s, "for device "); ++ seq_puts(s, ((struct device *)clk->priv)->bus_id); ++ return 0; ++} +diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c +index 5988d99..ed3719b 100644 +--- a/arch/arm/mach-pxa/pxa25x.c ++++ b/arch/arm/mach-pxa/pxa25x.c +@@ -100,40 +100,50 @@ static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk) + return pxa25x_get_memclk_frequency_10khz() * 10000; + } + +-static const struct clkops clk_pxa25x_lcd_ops = { +- .enable = clk_cken_enable, +- .disable = clk_cken_disable, +- .getrate = clk_pxa25x_lcd_getrate, +-}; +- + /* + * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz) + * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz + * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly) + */ +-static struct clk pxa25x_hwuart_clk = +- INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev) +-; ++static struct clk pxa25x_hwuart_clk[] = { ++ INIT_CKEN("HWUARTCLK", HWUART, 14745600, 1), ++ { ++ .parent = &pxa25x_hwuart_clk[0], ++ .name = "UARTCLK", ++ .can_get = clk_dev_can_get, ++ .priv = &pxa_device_hwuart.dev, ++ }, ++}; + + static struct clk pxa25x_clks[] = { +- INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev), +- INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev), +- INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), +- INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL), +- INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev), +- INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev), +- INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev), +- +- INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev), +- INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev), +- INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev), ++ INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_getrate), ++ INIT_CKEN("FFUARTCLK", FFUART, 14745600, 1), ++ INIT_CKEN("BTUARTCLK", BTUART, 14745600, 1), ++ INIT_CKEN("STUARTCLK", STUART, 14745600, 1), ++ INIT_CKEN("UDCCLK", USB, 47923000, 5), ++ INIT_CKEN("MMCCLK", MMC, 19169000, 0), ++ INIT_CKEN("I2CCLK", I2C, 31949000, 0), ++ ++ INIT_CKEN("SSP_CLK", SSP, 3686400, 0), ++ INIT_CKEN("NSSPCLK", NSSP, 3686400, 0), ++ INIT_CKEN("ASSPCLK", ASSP, 3686400, 0), + + /* +- INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), +- INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL), +- INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL), ++ INIT_CKEN("PWMCLK", PWM0, 3686400, 0), ++ INIT_CKEN("PWMCLK", PWM0, 3686400, 0), ++ INIT_CKEN("I2SCLK", I2S, 14745600, 0), + */ +- INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), ++ INIT_CKEN("FICPCLK", FICP, 47923000, 0), ++}; ++ ++static struct clk_function __initdata pxa25x_clk_funcs[] = { ++ CLK_FUNC("FFUARTCLK", "UARTCLK", clk_dev_can_get, &pxa_device_ffuart.dev, clk_dev_format), ++ CLK_FUNC("BTUARTCLK", "UARTCLK", clk_dev_can_get, &pxa_device_btuart.dev, clk_dev_format), ++ CLK_FUNC("STUARTCLK", "UARTCLK", clk_dev_can_get, &pxa_device_stuart.dev, clk_dev_format), ++ CLK_FUNC("STUARTCLK", "SIRCLK", NULL, NULL, NULL), ++ CLK_FUNC("SSP_CLK", "SSPCLK", clk_dev_can_get, &pxa25x_device_ssp.dev, clk_dev_format), ++ CLK_FUNC("NSSPCLK", "SSPCLK", clk_dev_can_get, &pxa25x_device_nssp.dev, clk_dev_format), ++ CLK_FUNC("ASSPCLK", "SSPCLK", clk_dev_can_get, &pxa25x_device_assp.dev, clk_dev_format), + }; + + #ifdef CONFIG_PM +@@ -313,11 +323,13 @@ static int __init pxa25x_init(void) + int ret = 0; + + /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ +- if (cpu_is_pxa25x()) +- clks_register(&pxa25x_hwuart_clk, 1); ++ if (cpu_is_pxa25x()) { ++ clks_register(pxa25x_hwuart_clk, ARRAY_SIZE(pxa25x_hwuart_clk)); ++ } + + if (cpu_is_pxa21x() || cpu_is_pxa25x()) { + clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks)); ++ clk_alloc_functions(pxa25x_clk_funcs, ARRAY_SIZE(pxa25x_clk_funcs)); + + if ((ret = pxa_init_dma(16))) + return ret; +diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c +index 30ca4fd..c51e7b2 100644 +--- a/arch/arm/mach-pxa/pxa27x.c ++++ b/arch/arm/mach-pxa/pxa27x.c +@@ -126,44 +126,48 @@ static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk) + return pxa27x_get_lcdclk_frequency_10khz() * 10000; + } + +-static const struct clkops clk_pxa27x_lcd_ops = { +- .enable = clk_cken_enable, +- .disable = clk_cken_disable, +- .getrate = clk_pxa27x_lcd_getrate, +-}; +- + static struct clk pxa27x_clks[] = { +- INIT_CK("LCDCLK", LCD, &clk_pxa27x_lcd_ops, &pxa_device_fb.dev), +- INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL), ++ INIT_CK("LCDCLK", LCD, &clk_pxa27x_lcd_getrate), ++ INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_getrate), + +- INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), +- INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), +- INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL), ++ INIT_CKEN("FFUARTCLK", FFUART, 14857000, 1), ++ INIT_CKEN("BTUARTCLK", BTUART, 14857000, 1), ++ INIT_CKEN("STUARTCLK", STUART, 14857000, 1), + +- INIT_CKEN("I2SCLK", I2S, 14682000, 0, &pxa_device_i2s.dev), +- INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), +- INIT_CKEN("UDCCLK", USB, 48000000, 5, &pxa_device_udc.dev), +- INIT_CKEN("MMCCLK", MMC, 19500000, 0, &pxa_device_mci.dev), +- INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev), ++ INIT_CKEN("I2SCLK", I2S, 14682000, 0), ++ INIT_CKEN("I2CCLK", I2C, 32842000, 0), ++ INIT_CKEN("UDCCLK", USB, 48000000, 5), ++ INIT_CKEN("MMCCLK", MMC, 19500000, 0), ++ INIT_CKEN("FICPCLK", FICP, 48000000, 0), + +- INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev), +- INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev), +- INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL), ++ INIT_CKEN("USBCLK", USBHOST, 48000000, 0), ++ INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0), ++ INIT_CKEN("KBDCLK", KEYPAD, 32768, 0), + +- INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), +- INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), +- INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), ++ INIT_CKEN("SSP1CLK", SSP1, 13000000, 0), ++ INIT_CKEN("SSP2CLK", SSP2, 13000000, 0), ++ INIT_CKEN("SSP3CLK", SSP3, 13000000, 0), + + /* +- INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL), +- INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL), +- INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL), +- INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL), +- INIT_CKEN("IMCLK", IM, 0, 0, NULL), +- INIT_CKEN("MEMCLK", MEMC, 0, 0, NULL), ++ INIT_CKEN("PWMCLK", PWM0, 13000000, 0), ++ INIT_CKEN("MSLCLK", MSL, 48000000, 0), ++ INIT_CKEN("USIMCLK", USIM, 48000000, 0), ++ INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0), ++ INIT_CKEN("IMCLK", IM, 0, 0), ++ INIT_CKEN("MEMCLK", MEMC, 0, 0), + */ + }; + ++static struct clk_function __initdata pxa27x_clk_funcs[] = { ++ CLK_FUNC("FFUARTCLK", "UARTCLK", clk_dev_can_get, &pxa_device_ffuart.dev, clk_dev_format), ++ CLK_FUNC("BTUARTCLK", "UARTCLK", clk_dev_can_get, &pxa_device_btuart.dev, clk_dev_format), ++ CLK_FUNC("STUARTCLK", "UARTCLK", clk_dev_can_get, &pxa_device_stuart.dev, clk_dev_format), ++ CLK_FUNC("STUARTCLK", "SIRCLK", NULL, NULL, NULL), ++ CLK_FUNC("SSP1CLK", "SSPCLK", clk_dev_can_get, &pxa27x_device_ssp1.dev, clk_dev_format), ++ CLK_FUNC("SSP2CLK", "SSPCLK", clk_dev_can_get, &pxa27x_device_ssp2.dev, clk_dev_format), ++ CLK_FUNC("SSP3CLK", "SSPCLK", clk_dev_can_get, &pxa27x_device_ssp3.dev, clk_dev_format), ++}; ++ + #ifdef CONFIG_PM + + #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x +@@ -453,6 +457,7 @@ static int __init pxa27x_init(void) + int ret = 0; + if (cpu_is_pxa27x()) { + clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks)); ++ clk_alloc_functions(pxa27x_clk_funcs, ARRAY_SIZE(pxa27x_clk_funcs)); + + if ((ret = pxa_init_dma(32))) + return ret; +diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c +index ccab9da..0f8bbf3 100644 +--- a/arch/arm/mach-pxa/pxa3xx.c ++++ b/arch/arm/mach-pxa/pxa3xx.c +@@ -122,27 +122,31 @@ static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk) + return hsio_clk; + } + +-static void clk_pxa3xx_cken_enable(struct clk *clk) ++static int clk_pxa3xx_cken_enable(struct clk *clk) + { +- unsigned long mask = 1ul << (clk->cken & 0x1f); ++ int cken = ((struct clk_cken_priv *)clk->priv)->cken; ++ unsigned long mask = 1ul << (cken & 0x1f); + + local_irq_disable(); + +- if (clk->cken < 32) ++ if (cken < 32) + CKENA |= mask; + else + CKENB |= mask; + + local_irq_enable(); ++ ++ return 0; + } + + static void clk_pxa3xx_cken_disable(struct clk *clk) + { +- unsigned long mask = 1ul << (clk->cken & 0x1f); ++ int cken = ((struct clk_cken_priv *)clk->priv)->cken; ++ unsigned long mask = 1ul << (cken & 0x1f); + + local_irq_disable(); + +- if (clk->cken < 32) ++ if (cken < 32) + CKENA &= ~mask; + else + CKENB &= ~mask; +@@ -150,55 +154,63 @@ static void clk_pxa3xx_cken_disable(struct clk *clk) + local_irq_enable(); + } + +-static const struct clkops clk_pxa3xx_cken_ops = { +- .enable = clk_pxa3xx_cken_enable, +- .disable = clk_pxa3xx_cken_disable, +-}; +- +-static const struct clkops clk_pxa3xx_hsio_ops = { +- .enable = clk_pxa3xx_cken_enable, +- .disable = clk_pxa3xx_cken_disable, +- .getrate = clk_pxa3xx_hsio_getrate, +-}; +- +-#define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \ ++#define PXA3xx_CKEN(_name, _cken, _rate, _delay) \ + { \ + .name = _name, \ +- .dev = _dev, \ +- .ops = &clk_pxa3xx_cken_ops, \ ++ .enable = clk_pxa3xx_cken_enable, \ ++ .disable = clk_pxa3xx_cken_disable, \ + .rate = _rate, \ +- .cken = CKEN_##_cken, \ + .delay = _delay, \ ++ .priv = &(struct clk_cken_priv) { \ ++ .cken = CKEN_##_cken, \ ++ }, \ + } + +-#define PXA3xx_CK(_name, _cken, _ops, _dev) \ ++#define PXA3xx_CK(_name, _cken, _getrate) \ + { \ + .name = _name, \ +- .dev = _dev, \ +- .ops = _ops, \ +- .cken = CKEN_##_cken, \ ++ .enable = clk_pxa3xx_cken_enable, \ ++ .disable = clk_pxa3xx_cken_disable, \ ++ .getrate = _getrate, \ ++ .priv = &(struct clk_cken_priv) { \ ++ .cken = CKEN_##_cken, \ ++ }, \ + } + + static struct clk pxa3xx_clks[] = { +- PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), +- PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), ++ PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_getrate), ++ PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_getrate), + +- PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), +- PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), +- PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL), ++ PXA3xx_CKEN("FFUARTCLK", FFUART, 14857000, 1), ++ PXA3xx_CKEN("BTUARTCLK", BTUART, 14857000, 1), ++ PXA3xx_CKEN("STUARTCLK", STUART, 14857000, 1), + +- PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), +- PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev), +- PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev), ++ PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0), ++ PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5), ++ PXA3xx_CKEN("USBCLK", USBH, 48000000, 0), + +- PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), +- PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), +- PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev), +- PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev), ++ PXA3xx_CKEN("SSP1CLK", SSP1, 13000000, 0), ++ PXA3xx_CKEN("SSP2CLK", SSP2, 13000000, 0), ++ PXA3xx_CKEN("SSP3CLK", SSP3, 13000000, 0), ++ PXA3xx_CKEN("SSP4CLK", SSP4, 13000000, 0), ++ ++ PXA3xx_CKEN("MMC1CLK", MMC1, 19500000, 0), ++ PXA3xx_CKEN("MMC2CLK", MMC2, 19500000, 0), ++ PXA3xx_CKEN("MMC3CLK", MMC3, 19500000, 0), ++}; + +- PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev), +- PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev), +- PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev), ++static struct clk_function __initdata pxa3xx_clk_funcs[] = { ++ CLK_FUNC("FFUARTCLK", "UARTCLK", clk_dev_can_get, &pxa_device_ffuart.dev, clk_dev_format), ++ CLK_FUNC("BTUARTCLK", "UARTCLK", clk_dev_can_get, &pxa_device_btuart.dev, clk_dev_format), ++ CLK_FUNC("STUARTCLK", "UARTCLK", clk_dev_can_get, &pxa_device_stuart.dev, clk_dev_format), ++ CLK_FUNC("STUARTCLK", "SIRCLK", NULL, NULL, NULL), ++ CLK_FUNC("SSP1CLK", "SSPCLK", clk_dev_can_get, &pxa27x_device_ssp1.dev, clk_dev_format), ++ CLK_FUNC("SSP2CLK", "SSPCLK", clk_dev_can_get, &pxa27x_device_ssp2.dev, clk_dev_format), ++ CLK_FUNC("SSP3CLK", "SSPCLK", clk_dev_can_get, &pxa27x_device_ssp3.dev, clk_dev_format), ++ CLK_FUNC("SSP4CLK", "SSPCLK", clk_dev_can_get, &pxa3xx_device_ssp4.dev, clk_dev_format), ++ CLK_FUNC("MMC1CLK", "MMCCLK", clk_dev_can_get, &pxa_device_mci.dev, clk_dev_format), ++ CLK_FUNC("MMC2CLK", "MMCCLK", clk_dev_can_get, &pxa3xx_device_mci2.dev, clk_dev_format), ++ CLK_FUNC("MMC3CLK", "MMCCLK", clk_dev_can_get, &pxa3xx_device_mci3.dev, clk_dev_format), + }; + + #ifdef CONFIG_PM +@@ -255,6 +267,7 @@ static int __init pxa3xx_init(void) + + if (cpu_is_pxa3xx()) { + clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); ++ clk_alloc_functions(pxa3xx_clk_funcs, ARRAY_SIZE(pxa3xx_clk_funcs)); + + if ((ret = pxa_init_dma(32))) + return ret; +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0042-Use-correct-clock-for-IrDA-on-pxa.patch b/packages/linux/linux-rp-2.6.24/tosa/0042-Use-correct-clock-for-IrDA-on-pxa.patch new file mode 100644 index 0000000000..a605735df0 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0042-Use-correct-clock-for-IrDA-on-pxa.patch @@ -0,0 +1,26 @@ +From 70dfe7e736467af6242c61092cb64f44d2fd50e3 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Mon, 4 Feb 2008 03:01:05 +0300 +Subject: [PATCH 42/64] Use correct clock for IrDA on pxa + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + drivers/net/irda/pxaficp_ir.c | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c +index 8c09344..36d2ec0 100644 +--- a/drivers/net/irda/pxaficp_ir.c ++++ b/drivers/net/irda/pxaficp_ir.c +@@ -814,7 +814,7 @@ static int pxa_irda_probe(struct platform_device *pdev) + si->dev = &pdev->dev; + si->pdata = pdev->dev.platform_data; + +- si->sir_clk = clk_get(&pdev->dev, "UARTCLK"); ++ si->sir_clk = clk_get(&pdev->dev, "SIRCLK"); + si->fir_clk = clk_get(&pdev->dev, "FICPCLK"); + if (IS_ERR(si->sir_clk) || IS_ERR(si->fir_clk)) { + err = PTR_ERR(IS_ERR(si->sir_clk) ? si->sir_clk : si->fir_clk); +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0043-Use-clocklib-for-sa1100-sub-arch.patch b/packages/linux/linux-rp-2.6.24/tosa/0043-Use-clocklib-for-sa1100-sub-arch.patch new file mode 100644 index 0000000000..22b8414b2d --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0043-Use-clocklib-for-sa1100-sub-arch.patch @@ -0,0 +1,153 @@ +From 3932e0f5c4c05200c030b60606ed2eb83550f4bb Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Mon, 4 Feb 2008 03:01:04 +0300 +Subject: [PATCH 43/64] Use clocklib for sa1100 sub-arch. + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + arch/arm/Kconfig | 1 + + arch/arm/mach-sa1100/clock.c | 95 ++--------------------------------------- + 2 files changed, 6 insertions(+), 90 deletions(-) + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 47f3c73..fa47201 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -370,6 +370,7 @@ config ARCH_SA1100 + select ARCH_MTD_XIP + select GENERIC_GPIO + select GENERIC_TIME ++ select HAVE_CLOCK_LIB + help + Support for StrongARM 11x0 based boards. + +diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c +index fc97fe5..6b3cc51 100644 +--- a/arch/arm/mach-sa1100/clock.c ++++ b/arch/arm/mach-sa1100/clock.c +@@ -8,83 +8,13 @@ + #include <linux/err.h> + #include <linux/string.h> + #include <linux/clk.h> ++#include <linux/clklib.h> + #include <linux/spinlock.h> + #include <linux/mutex.h> + + #include <asm/hardware.h> + +-/* +- * Very simple clock implementation - we only have one clock to +- * deal with at the moment, so we only match using the "name". +- */ +-struct clk { +- struct list_head node; +- unsigned long rate; +- const char *name; +- unsigned int enabled; +- void (*enable)(void); +- void (*disable)(void); +-}; +- +-static LIST_HEAD(clocks); +-static DEFINE_MUTEX(clocks_mutex); +-static DEFINE_SPINLOCK(clocks_lock); +- +-struct clk *clk_get(struct device *dev, const char *id) +-{ +- struct clk *p, *clk = ERR_PTR(-ENOENT); +- +- mutex_lock(&clocks_mutex); +- list_for_each_entry(p, &clocks, node) { +- if (strcmp(id, p->name) == 0) { +- clk = p; +- break; +- } +- } +- mutex_unlock(&clocks_mutex); +- +- return clk; +-} +-EXPORT_SYMBOL(clk_get); +- +-void clk_put(struct clk *clk) +-{ +-} +-EXPORT_SYMBOL(clk_put); +- +-int clk_enable(struct clk *clk) +-{ +- unsigned long flags; +- +- spin_lock_irqsave(&clocks_lock, flags); +- if (clk->enabled++ == 0) +- clk->enable(); +- spin_unlock_irqrestore(&clocks_lock, flags); +- return 0; +-} +-EXPORT_SYMBOL(clk_enable); +- +-void clk_disable(struct clk *clk) +-{ +- unsigned long flags; +- +- WARN_ON(clk->enabled == 0); +- +- spin_lock_irqsave(&clocks_lock, flags); +- if (--clk->enabled == 0) +- clk->disable(); +- spin_unlock_irqrestore(&clocks_lock, flags); +-} +-EXPORT_SYMBOL(clk_disable); +- +-unsigned long clk_get_rate(struct clk *clk) +-{ +- return clk->rate; +-} +-EXPORT_SYMBOL(clk_get_rate); +- +- +-static void clk_gpio27_enable(void) ++static int clk_gpio27_enable(struct clk *clk) + { + /* + * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: +@@ -93,9 +23,11 @@ static void clk_gpio27_enable(void) + GAFR |= GPIO_32_768kHz; + GPDR |= GPIO_32_768kHz; + TUCR = TUCR_3_6864MHz; ++ ++ return 0; + } + +-static void clk_gpio27_disable(void) ++static void clk_gpio27_disable(struct clk *clk) + { + TUCR = 0; + GPDR &= ~GPIO_32_768kHz; +@@ -109,23 +41,6 @@ static struct clk clk_gpio27 = { + .disable = clk_gpio27_disable, + }; + +-int clk_register(struct clk *clk) +-{ +- mutex_lock(&clocks_mutex); +- list_add(&clk->node, &clocks); +- mutex_unlock(&clocks_mutex); +- return 0; +-} +-EXPORT_SYMBOL(clk_register); +- +-void clk_unregister(struct clk *clk) +-{ +- mutex_lock(&clocks_mutex); +- list_del(&clk->node); +- mutex_unlock(&clocks_mutex); +-} +-EXPORT_SYMBOL(clk_unregister); +- + static int __init clk_init(void) + { + clk_register(&clk_gpio27); +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0044-fix-tmio_mmc-debug-compilation.patch b/packages/linux/linux-rp-2.6.24/tosa/0044-fix-tmio_mmc-debug-compilation.patch new file mode 100644 index 0000000000..5ca8228604 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0044-fix-tmio_mmc-debug-compilation.patch @@ -0,0 +1,26 @@ +From 03fdebde257197c13c0d10882e16a2a888ab4e0a Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Sat, 2 Feb 2008 20:23:01 +0300 +Subject: [PATCH 44/64] fix tmio_mmc debug compilation + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + drivers/mmc/host/tmio_mmc.c | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c +index 735c386..b0d38e2 100644 +--- a/drivers/mmc/host/tmio_mmc.c ++++ b/drivers/mmc/host/tmio_mmc.c +@@ -329,7 +329,7 @@ static irqreturn_t tmio_mmc_irq(int irq, void *devid) + if (!ireg) { + disable_mmc_irqs(ctl, status & ~irq_mask); + #ifdef CONFIG_MMC_DEBUG +- WARN("tmio_mmc: Spurious MMC irq, disabling! 0x%08x 0x%08x 0x%08x\n", status, irq_mask, ireg); ++ printk(KERN_WARNING "tmio_mmc: Spurious MMC irq, disabling! 0x%08x 0x%08x 0x%08x\n", status, irq_mask, ireg); + debug_status(status); + #endif + goto out; +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0045-Update-tmio_ohci.patch b/packages/linux/linux-rp-2.6.24/tosa/0045-Update-tmio_ohci.patch new file mode 100644 index 0000000000..10f483b89d --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0045-Update-tmio_ohci.patch @@ -0,0 +1,416 @@ +From fe3c05491370965eb821aedc95f771b86ebab3ab Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Wed, 9 Jan 2008 02:01:44 +0300 +Subject: [PATCH 45/64] Update tmio_ohci: + Ports management. + Basic support for ohci suspend/resume. + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + drivers/mfd/tc6393xb.c | 40 ++++++++ + drivers/usb/host/ohci-tmio.c | 206 +++++++++++++++++++++++++++++++++++++++--- + 2 files changed, 235 insertions(+), 11 deletions(-) + +diff --git a/drivers/mfd/tc6393xb.c b/drivers/mfd/tc6393xb.c +index 9439f39..5d17687 100644 +--- a/drivers/mfd/tc6393xb.c ++++ b/drivers/mfd/tc6393xb.c +@@ -224,6 +224,44 @@ static int tc6393xb_ohci_enable(struct platform_device *ohci) + return 0; + } + ++static int tc6393xb_ohci_suspend(struct platform_device *ohci) ++{ ++ struct platform_device *dev = to_platform_device(ohci->dev.parent); ++ struct tc6393xb *tc6393xb = platform_get_drvdata(dev); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ union tc6393xb_scr_ccr ccr; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&tc6393xb->lock, flags); ++ ++ ccr.raw = ioread16(&scr->ccr); ++ ccr.bits.usbcken = 0; ++ iowrite16(ccr.raw, &scr->ccr); ++ ++ spin_unlock_irqrestore(&tc6393xb->lock, flags); ++ ++ return 0; ++} ++ ++static int tc6393xb_ohci_resume(struct platform_device *ohci) ++{ ++ struct platform_device *dev = to_platform_device(ohci->dev.parent); ++ struct tc6393xb *tc6393xb = platform_get_drvdata(dev); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ union tc6393xb_scr_ccr ccr; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&tc6393xb->lock, flags); ++ ++ ccr.raw = ioread16(&scr->ccr); ++ ccr.bits.usbcken = 1; ++ iowrite16(ccr.raw, &scr->ccr); ++ ++ spin_unlock_irqrestore(&tc6393xb->lock, flags); ++ ++ return 0; ++} ++ + static int tc6393xb_fb_disable(struct platform_device *fb) + { + struct platform_device *dev = to_platform_device(fb->dev.parent); +@@ -423,6 +461,8 @@ static struct mfd_cell tc6393xb_cells[] = { + .name = "tmio-ohci", + .enable = tc6393xb_ohci_enable, + .disable = tc6393xb_ohci_disable, ++ .suspend = tc6393xb_ohci_suspend, ++ .resume = tc6393xb_ohci_resume, + .num_resources = ARRAY_SIZE(tc6393xb_ohci_resources), + .resources = tc6393xb_ohci_resources, + }, +diff --git a/drivers/usb/host/ohci-tmio.c b/drivers/usb/host/ohci-tmio.c +index be609f3..65e3cd3 100644 +--- a/drivers/usb/host/ohci-tmio.c ++++ b/drivers/usb/host/ohci-tmio.c +@@ -75,10 +75,13 @@ struct tmio_uhccr { + u8 x07[3]; + } __attribute__((packed)); + ++#define MAX_TMIO_OHCI_PORTS 3 ++ + #define UHCCR_PM_GKEN 0x0001 + #define UHCCR_PM_CKRNEN 0x0002 + #define UHCCR_PM_USBPW1 0x0004 + #define UHCCR_PM_USBPW2 0x0008 ++#define UHCCR_PM_USBPW3 0x0008 + #define UHCCR_PM_PMEE 0x0100 + #define UHCCR_PM_PMES 0x8000 + +@@ -86,44 +89,96 @@ struct tmio_uhccr { + + struct tmio_hcd { + struct tmio_uhccr __iomem *ccr; ++ spinlock_t lock; /* protects RMW cycles and disabled_ports data */ ++ bool disabled_ports[MAX_TMIO_OHCI_PORTS]; + }; + + #define hcd_to_tmio(hcd) ((struct tmio_hcd *)(hcd_to_ohci(hcd) + 1)) + #define ohci_to_tmio(ohci) ((struct tmio_hcd *)(ohci + 1)) + ++struct indexed_device_attribute{ ++ struct device_attribute dev_attr; ++ int index; ++}; ++#define to_indexed_dev_attr(_dev_attr) \ ++ container_of(_dev_attr, struct indexed_device_attribute, dev_attr) ++ ++#define INDEXED_ATTR(_name, _mode, _show, _store, _index) \ ++ { .dev_attr = __ATTR(_name ## _index, _mode, _show, _store), \ ++ .index = _index } ++ ++#define INDEXED_DEVICE_ATTR(_name, _mode, _show, _store, _index) \ ++struct indexed_device_attribute dev_attr_##_name ## _index \ ++ = INDEXED_ATTR(_name, _mode, _show, _store, _index) ++ ++static bool disabled_tmio_ports[MAX_TMIO_OHCI_PORTS]; ++module_param_array(disabled_tmio_ports, bool, NULL, 0644); ++MODULE_PARM_DESC(disabled_tmio_ports, ++ "disable specified TC6393 usb ports (default: all enabled)"); ++ + /*-------------------------------------------------------------------------*/ + ++static void tmio_write_pm(struct platform_device *dev) ++{ ++ struct usb_hcd *hcd = platform_get_drvdata(dev); ++ struct tmio_hcd *tmio = hcd_to_tmio(hcd); ++ struct tmio_uhccr __iomem *ccr = tmio->ccr; ++ u16 pm; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&tmio->lock, flags); ++ ++ pm = UHCCR_PM_GKEN | UHCCR_PM_CKRNEN | ++ UHCCR_PM_PMEE | UHCCR_PM_PMES; ++ ++ if (tmio->disabled_ports[0]) ++ pm |= UHCCR_PM_USBPW1; ++ if (tmio->disabled_ports[1]) ++ pm |= UHCCR_PM_USBPW2; ++ if (tmio->disabled_ports[2]) ++ pm |= UHCCR_PM_USBPW3; ++ ++ iowrite16(pm, &ccr->pm); ++ spin_unlock_irqrestore(&tmio->lock, flags); ++} ++ + static void tmio_stop_hc(struct platform_device *dev) + { + struct mfd_cell *cell = mfd_get_cell(dev); + struct usb_hcd *hcd = platform_get_drvdata(dev); ++ struct ohci_hcd *ohci = hcd_to_ohci(hcd); + struct tmio_hcd *tmio = hcd_to_tmio(hcd); + struct tmio_uhccr __iomem *ccr = tmio->ccr; + u16 pm; + +- pm = UHCCR_PM_GKEN | UHCCR_PM_CKRNEN | UHCCR_PM_USBPW1 | UHCCR_PM_USBPW2; ++ pm = UHCCR_PM_GKEN | UHCCR_PM_CKRNEN; ++ switch (ohci->num_ports) { ++ default: ++ dev_err(&dev->dev, "Unsupported amount of ports: %d\n", ohci->num_ports); ++ case 3: ++ pm |= UHCCR_PM_USBPW3; ++ case 2: ++ pm |= UHCCR_PM_USBPW2; ++ case 1: ++ pm |= UHCCR_PM_USBPW1; ++ } + iowrite8(0, &ccr->intc); + iowrite8(0, &ccr->ilme); + iowrite16(0, &ccr->basel); + iowrite16(0, &ccr->baseh); +- iowrite16(pm, &ccr->pm); ++ iowrite16(pm, &ccr->pm); + + cell->disable(dev); + } + + static void tmio_start_hc(struct platform_device *dev) + { +- struct mfd_cell *cell = mfd_get_cell(dev); + struct usb_hcd *hcd = platform_get_drvdata(dev); + struct tmio_hcd *tmio = hcd_to_tmio(hcd); + struct tmio_uhccr __iomem *ccr = tmio->ccr; +- u16 pm; + unsigned long base = hcd->rsrc_start; + +- pm = UHCCR_PM_CKRNEN | UHCCR_PM_GKEN | UHCCR_PM_PMEE | UHCCR_PM_PMES; +- cell->enable(dev); +- +- iowrite16(pm, &ccr->pm); ++ tmio_write_pm(dev); + iowrite16(base, &ccr->basel); + iowrite16(base >> 16, &ccr->baseh); + iowrite8(1, &ccr->ilme); +@@ -133,9 +188,56 @@ static void tmio_start_hc(struct platform_device *dev) + ioread8(&ccr->revid), hcd->rsrc_start, hcd->irq); + } + ++static ssize_t tmio_disabled_port_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct usb_hcd *hcd = dev_get_drvdata(dev); ++ struct tmio_hcd *tmio = hcd_to_tmio(hcd); ++ int index = to_indexed_dev_attr(attr)->index; ++ return snprintf(buf, PAGE_SIZE, "%c", ++ tmio->disabled_ports[index-1]? 'Y': 'N'); ++} ++ ++static ssize_t tmio_disabled_port_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct usb_hcd *hcd = dev_get_drvdata(dev); ++ struct tmio_hcd *tmio = hcd_to_tmio(hcd); ++ int index = to_indexed_dev_attr(attr)->index; ++ ++ if (!count) ++ return -EINVAL; ++ ++ switch (buf[0]) { ++ case 'y': case 'Y': case '1': ++ tmio->disabled_ports[index-1] = true; ++ break; ++ case 'n': case 'N': case '0': ++ tmio->disabled_ports[index-1] = false; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ tmio_write_pm(to_platform_device(dev)); ++ ++ return 1; ++} ++ ++ ++static INDEXED_DEVICE_ATTR(disabled_usb_port, S_IRUGO | S_IWUSR, ++ tmio_disabled_port_show, tmio_disabled_port_store, 1); ++static INDEXED_DEVICE_ATTR(disabled_usb_port, S_IRUGO | S_IWUSR, ++ tmio_disabled_port_show, tmio_disabled_port_store, 2); ++static INDEXED_DEVICE_ATTR(disabled_usb_port, S_IRUGO | S_IWUSR, ++ tmio_disabled_port_show, tmio_disabled_port_store, 3); ++ + static int usb_hcd_tmio_probe(const struct hc_driver *driver, + struct platform_device *dev) + { ++ struct mfd_cell *cell = mfd_get_cell(dev); + struct resource *config = platform_get_resource_byname(dev, IORESOURCE_MEM, TMIO_OHCI_CONFIG); + struct resource *regs = platform_get_resource_byname(dev, IORESOURCE_MEM, TMIO_OHCI_CONTROL); + struct resource *sram = platform_get_resource_byname(dev, IORESOURCE_MEM, TMIO_OHCI_SRAM); +@@ -159,6 +261,12 @@ static int usb_hcd_tmio_probe(const struct hc_driver *driver, + + tmio = hcd_to_tmio(hcd); + ++ spin_lock_init(&tmio->lock); ++ ++ memcpy(tmio->disabled_ports, ++ disabled_tmio_ports, ++ sizeof(disabled_tmio_ports)); ++ + tmio->ccr = ioremap(config->start, config->end - config->start + 1); + if (!tmio->ccr) { + retval = -ENOMEM; +@@ -183,17 +291,46 @@ static int usb_hcd_tmio_probe(const struct hc_driver *driver, + if (retval) + goto err_dmabounce_register_dev; + ++ retval = cell->enable(dev); ++ if (retval) ++ goto err_enable; ++ + tmio_start_hc(dev); + ohci = hcd_to_ohci(hcd); + ohci_hcd_init(ohci); + + retval = usb_add_hcd(hcd, irq, IRQF_DISABLED); ++ if (retval) ++ goto err_add_hcd; ++ ++ switch (ohci->num_ports) { ++ default: ++ dev_err(&dev->dev, "Unsupported amount of ports: %d\n", ++ ohci->num_ports); ++ case 3: ++ retval |= device_create_file(&dev->dev, ++ &dev_attr_disabled_usb_port3.dev_attr); ++ case 2: ++ retval |= device_create_file(&dev->dev, ++ &dev_attr_disabled_usb_port2.dev_attr); ++ case 1: ++ retval |= device_create_file(&dev->dev, ++ &dev_attr_disabled_usb_port1.dev_attr); ++ } + + if (retval == 0) + return retval; + +- tmio_stop_hc(dev); ++ device_remove_file(&dev->dev, &dev_attr_disabled_usb_port3.dev_attr); ++ device_remove_file(&dev->dev, &dev_attr_disabled_usb_port2.dev_attr); ++ device_remove_file(&dev->dev, &dev_attr_disabled_usb_port1.dev_attr); ++ ++ usb_remove_hcd(hcd); + ++err_add_hcd: ++ tmio_stop_hc(dev); ++ cell->disable(dev); ++err_enable: + dmabounce_unregister_dev(&dev->dev); + err_dmabounce_register_dev: + dma_release_declared_memory(&dev->dev); +@@ -212,6 +349,9 @@ static void usb_hcd_tmio_remove(struct usb_hcd *hcd, struct platform_device *dev + { + struct tmio_hcd *tmio = hcd_to_tmio(hcd); + ++ device_remove_file(&dev->dev, &dev_attr_disabled_usb_port3.dev_attr); ++ device_remove_file(&dev->dev, &dev_attr_disabled_usb_port2.dev_attr); ++ device_remove_file(&dev->dev, &dev_attr_disabled_usb_port1.dev_attr); + usb_remove_hcd(hcd); + tmio_stop_hc(dev); + dmabounce_unregister_dev(&dev->dev); +@@ -297,13 +437,22 @@ static u64 dma_mask = DMA_32BIT_MASK; + static int ohci_hcd_tmio_drv_probe(struct platform_device *dev) + { + struct resource *sram = platform_get_resource_byname(dev, IORESOURCE_MEM, TMIO_OHCI_SRAM); ++ int retval; + + dev->dev.dma_mask = &dma_mask; + dev->dev.coherent_dma_mask = DMA_32BIT_MASK; + ++ /* FIXME: move dmabounce checkers to tc6393xb core? */ + dmabounce_register_checker(tmio_dmabounce_check, sram); + +- return usb_hcd_tmio_probe(&ohci_tmio_hc_driver, dev); ++ retval = usb_hcd_tmio_probe(&ohci_tmio_hc_driver, dev); ++ ++ if (retval == 0) ++ return retval; ++ ++ dmabounce_remove_checker(tmio_dmabounce_check, sram); ++ ++ return retval; + } + + static int ohci_hcd_tmio_drv_remove(struct platform_device *dev) +@@ -323,14 +472,31 @@ static int ohci_hcd_tmio_drv_remove(struct platform_device *dev) + #ifdef CONFIG_PM + static int ohci_hcd_tmio_drv_suspend(struct platform_device *dev, pm_message_t state) + { ++ struct mfd_cell *cell = mfd_get_cell(dev); + struct usb_hcd *hcd = platform_get_drvdata(dev); + struct ohci_hcd *ohci = hcd_to_ohci(hcd); ++ struct tmio_hcd *tmio = hcd_to_tmio(hcd); ++ struct tmio_uhccr __iomem *ccr = tmio->ccr; ++ unsigned long flags; ++ u8 misc; ++ int ret; + + if (time_before(jiffies, ohci->next_statechange)) + msleep(5); + ohci->next_statechange = jiffies; + +- tmio_stop_hc(dev); ++ spin_lock_irqsave(&tmio->lock, flags); ++ ++ misc = ioread8(&ccr->misc); ++ misc |= 1 << 3; /* USSUSP */ ++ iowrite8(misc, &ccr->misc); ++ ++ spin_unlock_irqrestore(&tmio->lock, flags); ++ ++ ret = cell->suspend(dev); ++ if (ret) ++ return ret; ++ + hcd->state = HC_STATE_SUSPENDED; + dev->dev.power.power_state = PMSG_SUSPEND; + +@@ -339,15 +505,33 @@ static int ohci_hcd_tmio_drv_suspend(struct platform_device *dev, pm_message_t s + + static int ohci_hcd_tmio_drv_resume(struct platform_device *dev) + { ++ struct mfd_cell *cell = mfd_get_cell(dev); + struct usb_hcd *hcd = platform_get_drvdata(dev); + struct ohci_hcd *ohci = hcd_to_ohci(hcd); ++ struct tmio_hcd *tmio = hcd_to_tmio(hcd); ++ struct tmio_uhccr __iomem *ccr = tmio->ccr; ++ unsigned long flags; ++ u8 misc; ++ int ret; + + if (time_before(jiffies, ohci->next_statechange)) + msleep(5); + ohci->next_statechange = jiffies; + ++ ret = cell->resume(dev); ++ if (ret) ++ return ret; ++ + tmio_start_hc(dev); + ++ spin_lock_irqsave(&tmio->lock, flags); ++ ++ misc = ioread8(&ccr->misc); ++ misc &= ~(1 << 3); /* USSUSP */ ++ iowrite8(misc, &ccr->misc); ++ ++ spin_unlock_irqrestore(&tmio->lock, flags); ++ + dev->dev.power.power_state = PMSG_ON; + usb_hcd_resume_root_hub(hcd); + +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0046-patch-tc6393xb-cleanup.patch b/packages/linux/linux-rp-2.6.24/tosa/0046-patch-tc6393xb-cleanup.patch new file mode 100644 index 0000000000..c4b57cb2d1 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0046-patch-tc6393xb-cleanup.patch @@ -0,0 +1,66 @@ +From edaab7ec86235871d8ad219a1d225ce12f67f8af Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Wed, 9 Jan 2008 02:13:29 +0300 +Subject: [PATCH 46/64] patch tc6393xb-cleanup + +--- + drivers/mfd/tc6393xb.c | 20 ++++++++++++-------- + 1 files changed, 12 insertions(+), 8 deletions(-) + +diff --git a/drivers/mfd/tc6393xb.c b/drivers/mfd/tc6393xb.c +index 5d17687..dfae61d 100644 +--- a/drivers/mfd/tc6393xb.c ++++ b/drivers/mfd/tc6393xb.c +@@ -590,16 +590,8 @@ static int tc6393xb_hw_init(struct platform_device *dev, int resume) + struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; + struct tc6393xb *tc6393xb = platform_get_drvdata(dev); + struct tc6393xb_scr __iomem *scr = tc6393xb->scr; +- int ret; + int i; + +- if (resume) +- ret = tcpd->resume(dev); +- else +- ret = tcpd->enable(dev); +- if (ret) +- return ret; +- + iowrite8(resume ? + tc6393xb->suspend_state.fer.raw : + 0, &scr->fer); +@@ -664,6 +656,10 @@ static int __devinit tc6393xb_probe(struct platform_device *dev) + goto err_ioremap; + } + ++ retval = tcpd->enable(dev); ++ if (retval) ++ goto err_enable; ++ + retval = tc6393xb_hw_init(dev, 0); + if (retval) + goto err_hw_init; +@@ -690,6 +686,8 @@ static int __devinit tc6393xb_probe(struct platform_device *dev) + tc6393xb_detach_irq(dev); + + err_hw_init: ++ tcpd->disable(dev); ++err_enable: + iounmap(tc6393xb->scr); + err_ioremap: + release_resource(rscr); +@@ -743,6 +741,12 @@ static int tc6393xb_suspend(struct platform_device *dev, pm_message_t state) + + static int tc6393xb_resume(struct platform_device *dev) + { ++ struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; ++ int ret = tcpd->resume(dev); ++ ++ if (ret) ++ return ret; ++ + return tc6393xb_hw_init(dev, 1); + } + #else +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0047-tc6393xb-use-bitmasks-instead-of-bit-field-structs.patch b/packages/linux/linux-rp-2.6.24/tosa/0047-tc6393xb-use-bitmasks-instead-of-bit-field-structs.patch new file mode 100644 index 0000000000..54e88253d1 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0047-tc6393xb-use-bitmasks-instead-of-bit-field-structs.patch @@ -0,0 +1,412 @@ +From c18b8e34c39ec0d395988318e6651076a748d6bd Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Tue, 12 Feb 2008 04:40:54 +0300 +Subject: [PATCH 47/64] tc6393xb: use bitmasks instead of bit-field structs + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + drivers/mfd/tc6393xb.c | 162 ++++++++++++++++++++++++----------------- + include/linux/mfd/tc6393xb.h | 63 +++------------- + 2 files changed, 107 insertions(+), 118 deletions(-) + +diff --git a/drivers/mfd/tc6393xb.c b/drivers/mfd/tc6393xb.c +index dfae61d..1a394e4 100644 +--- a/drivers/mfd/tc6393xb.c ++++ b/drivers/mfd/tc6393xb.c +@@ -24,6 +24,31 @@ + #include <linux/mfd/tmio.h> + #include <linux/mfd/tc6393xb.h> + ++#define TC6393XB_FER_USBEN BIT(0) /* USB host enable */ ++#define TC6393XB_FER_LCDCVEN BIT(1) /* polysilicon TFT enable */ ++#define TC6393XB_FER_SLCDEN BIT(2) /* SLCD enable */ ++ ++enum pincontrol { ++ opendrain = 0, ++ tristate = 1, ++ pushpull = 2, ++ /* reserved = 3, */ ++}; ++ ++#define TC6393XB_MCR_RDY_MASK (3 << 0) ++#define TC6393XB_MCR_RDY_OPENDRAIN (0 << 0) ++#define TC6393XB_MCR_RDY_TRISTATE (1 << 0) ++#define TC6393XB_MCR_RDY_PUSHPULL (2 << 0) ++#define TC6393XB_MCR_RDY_UNK BIT(2) ++#define TC6393XB_MCR_RDY_EN BIT(3) ++#define TC6393XB_MCR_INT_MASK (3 << 4) ++#define TC6393XB_MCR_INT_OPENDRAIN (0 << 4) ++#define TC6393XB_MCR_INT_TRISTATE (1 << 4) ++#define TC6393XB_MCR_INT_PUSHPULL (2 << 4) ++#define TC6393XB_MCR_INT_UNK BIT(6) ++#define TC6393XB_MCR_INT_EN BIT(7) ++/* bits 8 - 16 are unknown */ ++ + struct tc6393xb_scr { + u8 x00[8]; + u8 revid; /* 0x08 Revision ID */ +@@ -74,8 +99,8 @@ struct tc6393xb { + spinlock_t lock; /* protects RMW cycles */ + + struct { +- union tc6393xb_scr_fer fer; +- union tc6393xb_scr_ccr ccr; ++ u8 fer; ++ u16 ccr; + u8 gpi_bcr[4]; + } suspend_state; + +@@ -90,13 +115,13 @@ static int tc6393xb_mmc_enable(struct platform_device *mmc) { + struct platform_device *dev = to_platform_device(mmc->dev.parent); + struct tc6393xb *tc6393xb = platform_get_drvdata(dev); + struct tc6393xb_scr __iomem *scr = tc6393xb->scr; +- union tc6393xb_scr_ccr ccr; ++ u16 ccr; + unsigned long flags; + + spin_lock_irqsave(&tc6393xb->lock, flags); +- ccr.raw = ioread16(&scr->ccr); +- ccr.bits.ck32ken = 1; +- iowrite16(ccr.raw, &scr->ccr); ++ ccr = ioread16(&scr->ccr); ++ ccr |= TC6393XB_CCR_CK32K; ++ iowrite16(ccr, &scr->ccr); + spin_unlock_irqrestore(&tc6393xb->lock, flags); + + return 0; +@@ -106,13 +131,13 @@ static int tc6393xb_mmc_disable(struct platform_device *mmc) { + struct platform_device *dev = to_platform_device(mmc->dev.parent); + struct tc6393xb *tc6393xb = platform_get_drvdata(dev); + struct tc6393xb_scr __iomem *scr = tc6393xb->scr; +- union tc6393xb_scr_ccr ccr; ++ u16 ccr; + unsigned long flags; + + spin_lock_irqsave(&tc6393xb->lock, flags); +- ccr.raw = ioread16(&scr->ccr); +- ccr.bits.ck32ken = 0; +- iowrite16(ccr.raw, &scr->ccr); ++ ccr = ioread16(&scr->ccr); ++ ccr &= ~TC6393XB_CCR_CK32K; ++ iowrite16(ccr, &scr->ccr); + spin_unlock_irqrestore(&tc6393xb->lock, flags); + + return 0; +@@ -148,14 +173,17 @@ int tc6393xb_lcd_set_power(struct platform_device *fb, bool on) + struct platform_device *dev = to_platform_device(fb->dev.parent); + struct tc6393xb *tc6393xb = platform_get_drvdata(dev); + struct tc6393xb_scr __iomem *scr = tc6393xb->scr; +- union tc6393xb_scr_fer fer; ++ u8 fer; + unsigned long flags; + + spin_lock_irqsave(&tc6393xb->lock, flags); + +- fer.raw = ioread8(&scr->fer); +- fer.bits.slcden = on ? 1 : 0; +- iowrite8(fer.raw, &scr->fer); ++ fer = ioread8(&scr->fer); ++ if (on) ++ fer |= TC6393XB_FER_SLCDEN; ++ else ++ fer &= ~TC6393XB_FER_SLCDEN; ++ iowrite8(fer, &scr->fer); + + spin_unlock_irqrestore(&tc6393xb->lock, flags); + +@@ -181,19 +209,19 @@ static int tc6393xb_ohci_disable(struct platform_device *ohci) + struct platform_device *dev = to_platform_device(ohci->dev.parent); + struct tc6393xb *tc6393xb = platform_get_drvdata(dev); + struct tc6393xb_scr __iomem *scr = tc6393xb->scr; +- union tc6393xb_scr_ccr ccr; +- union tc6393xb_scr_fer fer; ++ u16 ccr; ++ u8 fer; + unsigned long flags; + + spin_lock_irqsave(&tc6393xb->lock, flags); + +- fer.raw = ioread8(&scr->fer); +- fer.bits.usben = 0; +- iowrite8(fer.raw, &scr->fer); ++ fer = ioread8(&scr->fer); ++ fer &= ~TC6393XB_FER_USBEN; ++ iowrite8(fer, &scr->fer); + +- ccr.raw = ioread16(&scr->ccr); +- ccr.bits.usbcken = 0; +- iowrite16(ccr.raw, &scr->ccr); ++ ccr = ioread16(&scr->ccr); ++ ccr &= ~TC6393XB_CCR_USBCK; ++ iowrite16(ccr, &scr->ccr); + + spin_unlock_irqrestore(&tc6393xb->lock, flags); + +@@ -205,19 +233,19 @@ static int tc6393xb_ohci_enable(struct platform_device *ohci) + struct platform_device *dev = to_platform_device(ohci->dev.parent); + struct tc6393xb *tc6393xb = platform_get_drvdata(dev); + struct tc6393xb_scr __iomem *scr = tc6393xb->scr; +- union tc6393xb_scr_ccr ccr; +- union tc6393xb_scr_fer fer; ++ u16 ccr; ++ u8 fer; + unsigned long flags; + + spin_lock_irqsave(&tc6393xb->lock, flags); + +- ccr.raw = ioread16(&scr->ccr); +- ccr.bits.usbcken = 1; +- iowrite16(ccr.raw, &scr->ccr); ++ ccr = ioread16(&scr->ccr); ++ ccr |= TC6393XB_CCR_USBCK; ++ iowrite16(ccr, &scr->ccr); + +- fer.raw = ioread8(&scr->fer); +- fer.bits.usben = 1; +- iowrite8(fer.raw, &scr->fer); ++ fer = ioread8(&scr->fer); ++ fer |= TC6393XB_FER_USBEN; ++ iowrite8(fer, &scr->fer); + + spin_unlock_irqrestore(&tc6393xb->lock, flags); + +@@ -229,14 +257,14 @@ static int tc6393xb_ohci_suspend(struct platform_device *ohci) + struct platform_device *dev = to_platform_device(ohci->dev.parent); + struct tc6393xb *tc6393xb = platform_get_drvdata(dev); + struct tc6393xb_scr __iomem *scr = tc6393xb->scr; +- union tc6393xb_scr_ccr ccr; ++ u16 ccr; + unsigned long flags; + + spin_lock_irqsave(&tc6393xb->lock, flags); + +- ccr.raw = ioread16(&scr->ccr); +- ccr.bits.usbcken = 0; +- iowrite16(ccr.raw, &scr->ccr); ++ ccr = ioread16(&scr->ccr); ++ ccr &= ~TC6393XB_CCR_USBCK; ++ iowrite16(ccr, &scr->ccr); + + spin_unlock_irqrestore(&tc6393xb->lock, flags); + +@@ -248,14 +276,14 @@ static int tc6393xb_ohci_resume(struct platform_device *ohci) + struct platform_device *dev = to_platform_device(ohci->dev.parent); + struct tc6393xb *tc6393xb = platform_get_drvdata(dev); + struct tc6393xb_scr __iomem *scr = tc6393xb->scr; +- union tc6393xb_scr_ccr ccr; ++ u16 ccr; + unsigned long flags; + + spin_lock_irqsave(&tc6393xb->lock, flags); + +- ccr.raw = ioread16(&scr->ccr); +- ccr.bits.usbcken = 1; +- iowrite16(ccr.raw, &scr->ccr); ++ ccr = ioread16(&scr->ccr); ++ ccr |= TC6393XB_CCR_USBCK; ++ iowrite16(ccr, &scr->ccr); + + spin_unlock_irqrestore(&tc6393xb->lock, flags); + +@@ -267,8 +295,8 @@ static int tc6393xb_fb_disable(struct platform_device *fb) + struct platform_device *dev = to_platform_device(fb->dev.parent); + struct tc6393xb *tc6393xb = platform_get_drvdata(dev); + struct tc6393xb_scr __iomem *scr = tc6393xb->scr; +- union tc6393xb_scr_ccr ccr; +- union tc6393xb_scr_fer fer; ++ u16 ccr; ++ u8 fer; + unsigned long flags; + + spin_lock_irqsave(&tc6393xb->lock, flags); +@@ -276,14 +304,13 @@ static int tc6393xb_fb_disable(struct platform_device *fb) + /* + * FIXME: is this correct or it should be moved to other _disable? + */ +- fer.raw = ioread8(&scr->fer); +- fer.bits.slcden = 0; +-/* fer.bits.lcdcven = 0; */ +- iowrite8(fer.raw, &scr->fer); ++ fer = ioread8(&scr->fer); ++ fer &= ~TC6393XB_FER_SLCDEN; ++ iowrite8(fer, &scr->fer); + +- ccr.raw = ioread16(&scr->ccr); +- ccr.bits.mclksel = disable; +- iowrite16(ccr.raw, &scr->ccr); ++ ccr = ioread16(&scr->ccr); ++ ccr = (ccr & ~TC6393XB_CCR_MCLK_MASK) | TC6393XB_CCR_MCLK_OFF; ++ iowrite16(ccr, &scr->ccr); + + spin_unlock_irqrestore(&tc6393xb->lock, flags); + +@@ -295,14 +322,14 @@ static int tc6393xb_fb_enable(struct platform_device *fb) + struct platform_device *dev = to_platform_device(fb->dev.parent); + struct tc6393xb *tc6393xb = platform_get_drvdata(dev); + struct tc6393xb_scr __iomem *scr = tc6393xb->scr; +- union tc6393xb_scr_ccr ccr; ++ u16 ccr; + unsigned long flags; + + spin_lock_irqsave(&tc6393xb->lock, flags); + +- ccr.raw = ioread16(&scr->ccr); +- ccr.bits.mclksel = m48MHz; +- iowrite16(ccr.raw, &scr->ccr); ++ ccr = ioread16(&scr->ccr); ++ ccr = (ccr & ~TC6393XB_CCR_MCLK_MASK) | TC6393XB_CCR_MCLK_48; ++ iowrite16(ccr, &scr->ccr); + + spin_unlock_irqrestore(&tc6393xb->lock, flags); + +@@ -314,14 +341,14 @@ static int tc6393xb_fb_suspend(struct platform_device *fb) + struct platform_device *dev = to_platform_device(fb->dev.parent); + struct tc6393xb *tc6393xb = platform_get_drvdata(dev); + struct tc6393xb_scr __iomem *scr = tc6393xb->scr; +- union tc6393xb_scr_ccr ccr; ++ u16 ccr; + unsigned long flags; + + spin_lock_irqsave(&tc6393xb->lock, flags); + +- ccr.raw = ioread16(&scr->ccr); +- ccr.bits.mclksel = disable; +- iowrite16(ccr.raw, &scr->ccr); ++ ccr = ioread16(&scr->ccr); ++ ccr = (ccr & ~TC6393XB_CCR_MCLK_MASK) | TC6393XB_CCR_MCLK_OFF; ++ iowrite16(ccr, &scr->ccr); + + spin_unlock_irqrestore(&tc6393xb->lock, flags); + +@@ -333,14 +360,14 @@ static int tc6393xb_fb_resume(struct platform_device *fb) + struct platform_device *dev = to_platform_device(fb->dev.parent); + struct tc6393xb *tc6393xb = platform_get_drvdata(dev); + struct tc6393xb_scr __iomem *scr = tc6393xb->scr; +- union tc6393xb_scr_ccr ccr; ++ u16 ccr; + unsigned long flags; + + spin_lock_irqsave(&tc6393xb->lock, flags); + +- ccr.raw = ioread16(&scr->ccr); +- ccr.bits.mclksel = m48MHz; +- iowrite16(ccr.raw, &scr->ccr); ++ ccr = ioread16(&scr->ccr); ++ ccr = (ccr & ~TC6393XB_CCR_MCLK_MASK) | TC6393XB_CCR_MCLK_48; ++ iowrite16(ccr, &scr->ccr); + + spin_unlock_irqrestore(&tc6393xb->lock, flags); + +@@ -592,14 +619,15 @@ static int tc6393xb_hw_init(struct platform_device *dev, int resume) + struct tc6393xb_scr __iomem *scr = tc6393xb->scr; + int i; + +- iowrite8(resume ? +- tc6393xb->suspend_state.fer.raw : +- 0, &scr->fer); ++ iowrite8(resume ? tc6393xb->suspend_state.fer : 0, ++ &scr->fer); + iowrite16(tcpd->scr_pll2cr, &scr->pll2cr); + iowrite16(resume? +- tc6393xb->suspend_state.ccr.raw : +- tcpd->scr_ccr.raw, &scr->ccr); +- iowrite16(tcpd->scr_mcr.raw, &scr->mcr); ++ tc6393xb->suspend_state.ccr : ++ tcpd->scr_ccr, &scr->ccr); ++ iowrite16(TC6393XB_MCR_RDY_OPENDRAIN | TC6393XB_MCR_RDY_UNK | TC6393XB_MCR_RDY_EN | ++ TC6393XB_MCR_INT_OPENDRAIN | TC6393XB_MCR_INT_UNK | TC6393XB_MCR_INT_EN | ++ BIT(15), &scr->mcr); + iowrite16(tcpd->scr_gper, &scr->gper); + iowrite8(0, &scr->irr); + iowrite8(0xbf, &scr->imr); +@@ -730,8 +758,8 @@ static int tc6393xb_suspend(struct platform_device *dev, pm_message_t state) + int i; + + +- tc6393xb->suspend_state.ccr.raw = ioread16(&scr->ccr); +- tc6393xb->suspend_state.fer.raw = ioread8(&scr->fer); ++ tc6393xb->suspend_state.ccr = ioread16(&scr->ccr); ++ tc6393xb->suspend_state.fer = ioread8(&scr->fer); + for (i = 0; i < 4; i++) + tc6393xb->suspend_state.gpi_bcr[i] = + ioread8(scr->gpi_bcr + i); +diff --git a/include/linux/mfd/tc6393xb.h b/include/linux/mfd/tc6393xb.h +index e699294..2c69f63 100644 +--- a/include/linux/mfd/tc6393xb.h ++++ b/include/linux/mfd/tc6393xb.h +@@ -20,60 +20,21 @@ + #include <linux/mfd-core.h> + #include <linux/mfd/tmio.h> + +-union tc6393xb_scr_fer { +- u8 raw; +-struct { +- unsigned usben:1; /* D0 USB enable */ +- unsigned lcdcven:1; /* D1 polysylicon TFT enable */ +- unsigned slcden:1; /* D2 SLCD enable */ +-} __attribute__ ((packed)) bits; +-} __attribute__ ((packed)); +- +-union tc6393xb_scr_ccr { +- u16 raw; +-struct { +- unsigned ck32ken:1; /* D0 SD host clock enable */ +- unsigned usbcken:1; /* D1 USB host clock enable */ +- unsigned x00:2; +- unsigned sharp:1; /* D4 ??? set in Sharp's code */ +- unsigned x01:3; +- enum { disable = 0, +- m12MHz = 1, +- m24MHz = 2, +- m48MHz = 3, +- } mclksel:3; /* D10-D8 LCD controller clock */ +- unsigned x02:1; +- enum { h24MHz = 0, +- h48MHz = 1, +- } hclksel:2; /* D13-D12 host bus clock */ +- unsigned x03:2; +-} __attribute__ ((packed)) bits; +-} __attribute__ ((packed)); +- +-enum pincontrol { +- opendrain = 0, +- tristate = 1, +- pushpull = 2, +- /* reserved = 3, */ +-}; +- +-union tc6393xb_scr_mcr { +- u16 raw; +-struct { +- enum pincontrol rdyst:2; /* D1-D0 HRDY control */ +- unsigned x00:1; +- unsigned aren:1; /* D3 HRDY pull up resistance cut off */ +- enum pincontrol intst:2; /* D5-D4 #HINT control */ +- unsigned x01:1; +- unsigned aien:1; /* D7 #HINT pull up resitance cut off */ +- unsigned x02:8; +-} __attribute__ ((packed)) bits; +-} __attribute__ ((packed)); ++#define TC6393XB_CCR_CK32K BIT(0) ++#define TC6393XB_CCR_USBCK BIT(1) ++#define TC6393XB_CCR_UNK1 BIT(4) ++#define TC6393XB_CCR_MCLK_MASK (7 << 8) ++#define TC6393XB_CCR_MCLK_OFF (0 << 8) ++#define TC6393XB_CCR_MCLK_12 (1 << 8) ++#define TC6393XB_CCR_MCLK_24 (2 << 8) ++#define TC6393XB_CCR_MCLK_48 (3 << 8) ++#define TC6393XB_CCR_HCLK_MASK (3 << 12) ++#define TC6393XB_CCR_HCLK_24 (0 << 12) ++#define TC6393XB_CCR_HCLK_48 (1 << 12) + + struct tc6393xb_platform_data { + u16 scr_pll2cr; /* PLL2 Control */ +- union tc6393xb_scr_ccr scr_ccr; /* Clock Control */ +- union tc6393xb_scr_mcr scr_mcr; /* Mode Control */ ++ u16 scr_ccr; /* Clock Control */ + u16 scr_gper; /* GP Enable */ + u32 scr_gpo_doecr; /* GPO Data OE Control */ + u32 scr_gpo_dsr; /* GPO Data Set */ +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0048-tc6393xb-GPIO-support.patch b/packages/linux/linux-rp-2.6.24/tosa/0048-tc6393xb-GPIO-support.patch new file mode 100644 index 0000000000..ef47d6cc21 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0048-tc6393xb-GPIO-support.patch @@ -0,0 +1,225 @@ +From 4fb4d83c7090ea21619bb652f2ea9b5c8c0c453e Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Wed, 9 Jan 2008 01:42:58 +0300 +Subject: [PATCH 48/64] tc6393xb GPIO support + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + drivers/mfd/tc6393xb.c | 124 ++++++++++++++++++++++++++++++++++++++++-- + include/linux/mfd/tc6393xb.h | 2 +- + 2 files changed, 119 insertions(+), 7 deletions(-) + +diff --git a/drivers/mfd/tc6393xb.c b/drivers/mfd/tc6393xb.c +index 1a394e4..9001687 100644 +--- a/drivers/mfd/tc6393xb.c ++++ b/drivers/mfd/tc6393xb.c +@@ -49,6 +49,8 @@ enum pincontrol { + #define TC6393XB_MCR_INT_EN BIT(7) + /* bits 8 - 16 are unknown */ + ++#include <asm/gpio.h> ++ + struct tc6393xb_scr { + u8 x00[8]; + u8 revid; /* 0x08 Revision ID */ +@@ -96,6 +98,8 @@ struct tc6393xb_scr { + struct tc6393xb { + struct tc6393xb_scr __iomem *scr; + ++ struct gpio_chip gpio; ++ + spinlock_t lock; /* protects RMW cycles */ + + struct { +@@ -513,6 +517,96 @@ static struct mfd_cell tc6393xb_cells[] = { + + /*--------------------------------------------------------------------------*/ + ++static int tc6393xb_gpio_get(struct gpio_chip *chip, ++ unsigned offset) ++{ ++ struct tc6393xb *tc6393xb = container_of(chip, ++ struct tc6393xb, gpio); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ u32 mask = 1 << offset; ++ ++ return tmio_ioread32(scr->gpo_dsr) & mask; ++} ++ ++static void __tc6393xb_gpio_set(struct gpio_chip *chip, ++ unsigned offset, int value) ++{ ++ struct tc6393xb *tc6393xb = container_of(chip, ++ struct tc6393xb, gpio); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ u32 dsr; ++ ++ dsr = tmio_ioread32(scr->gpo_dsr); ++ if (value) ++ dsr |= (1L << offset); ++ else ++ dsr &= ~(1L << offset); ++ ++ tmio_iowrite32(dsr, scr->gpo_dsr); ++} ++ ++static void tc6393xb_gpio_set(struct gpio_chip *chip, ++ unsigned offset, int value) ++{ ++ struct tc6393xb *tc6393xb = container_of(chip, ++ struct tc6393xb, gpio); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&tc6393xb->lock, flags); ++ ++ __tc6393xb_gpio_set(chip, offset, value); ++ ++ spin_unlock_irqrestore(&tc6393xb->lock, flags); ++} ++ ++static int tc6393xb_gpio_direction_input(struct gpio_chip *chip, ++ unsigned offset) ++{ ++ struct tc6393xb *tc6393xb = container_of(chip, ++ struct tc6393xb, gpio); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ unsigned long flags; ++ u32 doecr; ++ ++ spin_lock_irqsave(&tc6393xb->lock, flags); ++ ++ doecr = tmio_ioread32(scr->gpo_doecr); ++ ++ doecr &= ~(1 << offset); ++ ++ tmio_iowrite32(doecr, scr->gpo_doecr); ++ ++ spin_unlock_irqrestore(&tc6393xb->lock, flags); ++ ++ return 0; ++} ++ ++static int tc6393xb_gpio_direction_output(struct gpio_chip *chip, ++ unsigned offset, int value) ++{ ++ struct tc6393xb *tc6393xb = container_of(chip, ++ struct tc6393xb, gpio); ++ struct tc6393xb_scr __iomem *scr = tc6393xb->scr; ++ unsigned long flags; ++ u32 doecr; ++ ++ spin_lock_irqsave(&tc6393xb->lock, flags); ++ ++ doecr = tmio_ioread32(scr->gpo_doecr); ++ ++ doecr |= (1 << offset); ++ ++ tmio_iowrite32(doecr, scr->gpo_doecr); ++ ++ __tc6393xb_gpio_set(chip, offset, value); ++ ++ spin_unlock_irqrestore(&tc6393xb->lock, flags); ++ ++ return 0; ++} ++ ++/*--------------------------------------------------------------------------*/ ++ + static void + tc6393xb_irq(unsigned int irq, struct irq_desc *desc) + { +@@ -631,10 +725,8 @@ static int tc6393xb_hw_init(struct platform_device *dev, int resume) + iowrite16(tcpd->scr_gper, &scr->gper); + iowrite8(0, &scr->irr); + iowrite8(0xbf, &scr->imr); +- iowrite16(tcpd->scr_gpo_dsr, scr->gpo_dsr + 0); +- iowrite16(tcpd->scr_gpo_dsr >> 16, scr->gpo_dsr + 1); +- iowrite16(tcpd->scr_gpo_doecr, scr->gpo_doecr + 0); +- iowrite16(tcpd->scr_gpo_doecr >> 16, scr->gpo_doecr + 1); ++ tmio_iowrite32(tcpd->scr_gpo_dsr, &scr->gpo_dsr); ++ tmio_iowrite32(tcpd->scr_gpo_doecr, &scr->gpo_doecr); + + if (resume) + for (i = 0; i < 4; i++) +@@ -650,7 +742,7 @@ static int __devinit tc6393xb_probe(struct platform_device *dev) + struct tc6393xb *tc6393xb; + struct resource *iomem; + struct resource *rscr; +- int retval; ++ int retval, temp; + + iomem = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (!iomem) +@@ -696,6 +788,18 @@ static int __devinit tc6393xb_probe(struct platform_device *dev) + ioread8(&tc6393xb->scr->revid), + (unsigned long) iomem->start, tc6393xb->irq); + ++ tc6393xb->gpio.label = "tc6393xb"; ++ tc6393xb->gpio.base = tcpd->gpio_base; ++ tc6393xb->gpio.ngpio = 16; /* FIXME: actually 32, but I'm not sure */ ++ tc6393xb->gpio.set = tc6393xb_gpio_set; ++ tc6393xb->gpio.get = tc6393xb_gpio_get; ++ tc6393xb->gpio.direction_input = tc6393xb_gpio_direction_input; ++ tc6393xb->gpio.direction_output = tc6393xb_gpio_direction_output; ++ ++ retval = gpiochip_add(&tc6393xb->gpio); ++ if (retval) ++ goto err_gpio_add; ++ + if (tc6393xb->irq) + tc6393xb_attach_irq(dev); + +@@ -713,6 +817,8 @@ static int __devinit tc6393xb_probe(struct platform_device *dev) + if (tc6393xb->irq) + tc6393xb_detach_irq(dev); + ++err_gpio_add: ++ temp = gpiochip_remove(&tc6393xb->gpio); + err_hw_init: + tcpd->disable(dev); + err_enable: +@@ -734,6 +840,12 @@ static int __devexit tc6393xb_remove(struct platform_device *dev) { + if (tc6393xb->irq) + tc6393xb_detach_irq(dev); + ++ ret = gpiochip_remove(&tc6393xb->gpio); ++ if (ret) { ++ dev_err(&dev->dev, "Can't remove gpio chip: %d\n", ret); ++ return ret; ++ } ++ + ret = tcpd->disable(dev); + + iounmap(tc6393xb->scr); +@@ -804,7 +916,7 @@ static void __exit tc6393xb_exit(void) + platform_driver_unregister(&tc6393xb_driver); + } + +-module_init(tc6393xb_init); ++subsys_initcall(tc6393xb_init); + module_exit(tc6393xb_exit); + + MODULE_LICENSE("GPL"); +diff --git a/include/linux/mfd/tc6393xb.h b/include/linux/mfd/tc6393xb.h +index 2c69f63..97c4c7c 100644 +--- a/include/linux/mfd/tc6393xb.h ++++ b/include/linux/mfd/tc6393xb.h +@@ -45,6 +45,7 @@ struct tc6393xb_platform_data { + int (*resume)(struct platform_device *dev); + + int irq_base; /* a base for cascaded irq */ ++ int gpio_base; + + struct tmio_nand_data *nand_data; + struct tmio_fb_data *fb_data; +@@ -54,7 +55,6 @@ extern int tc6393xb_lcd_set_power(struct platform_device *fb_dev, bool on); + extern int tc6393xb_lcd_mode(struct platform_device *fb_dev, + struct fb_videomode *mode); + +- + /* + * Relative to irq_base + */ +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0049-platform-support-for-TMIO-on-tosa.patch b/packages/linux/linux-rp-2.6.24/tosa/0049-platform-support-for-TMIO-on-tosa.patch new file mode 100644 index 0000000000..ff1186cb71 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0049-platform-support-for-TMIO-on-tosa.patch @@ -0,0 +1,373 @@ +From 30588bdd5c5cdd9fbe269643f582862a76f09efb Mon Sep 17 00:00:00 2001 +From: Ian Molton <spyro@f2s.com> +Date: Tue, 12 Feb 2008 04:52:48 +0300 +Subject: [PATCH 49/64] platform support for TMIO on tosa + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + arch/arm/mach-pxa/tosa.c | 179 ++++++++++++++++++++++++++++++++++++++- + include/asm-arm/arch-pxa/irqs.h | 1 + + include/asm-arm/arch-pxa/tosa.h | 45 ++++++++-- + sound/soc/pxa/tosa.c | 3 +- + 4 files changed, 216 insertions(+), 12 deletions(-) + +diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c +index 5268e94..e2eec0f 100644 +--- a/arch/arm/mach-pxa/tosa.c ++++ b/arch/arm/mach-pxa/tosa.c +@@ -18,7 +18,13 @@ + #include <linux/major.h> + #include <linux/fs.h> + #include <linux/interrupt.h> ++#include <linux/delay.h> ++#include <linux/fb.h> + #include <linux/mmc/host.h> ++#include <linux/mfd/tc6393xb.h> ++#include <linux/mfd/tmio.h> ++#include <linux/mtd/nand.h> ++#include <linux/mtd/partitions.h> + #include <linux/pm.h> + #include <linux/delay.h> + #include <linux/gpio_keys.h> +@@ -298,12 +304,183 @@ static struct platform_device tosaled_device = { + .id = -1, + }; + ++/* ++ * Toshiba Mobile IO Controller ++ */ ++static struct resource tc6393xb_resources[] = { ++ [0] = { ++ .start = TOSA_LCDC_PHYS, ++ .end = TOSA_LCDC_PHYS + 0x3ffffff, ++ .flags = IORESOURCE_MEM, ++ }, ++ ++ [1] = { ++ .start = TOSA_IRQ_GPIO_TC6393XB_INT, ++ .end = TOSA_IRQ_GPIO_TC6393XB_INT, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++ ++static int tosa_tc6393xb_enable(struct platform_device *dev) ++{ ++ ++ reset_scoop_gpio(&tosascoop_jc_device.dev, TOSA_SCOOP_JC_TC6393XB_L3V_ON); ++ reset_scoop_gpio(&tosascoop_jc_device.dev, TOSA_SCOOP_JC_TC6393XB_SUSPEND); ++ reset_scoop_gpio(&tosascoop_device.dev, TOSA_SCOOP_TC6393XB_REST_IN); /* #PCLR */ ++ pxa_gpio_mode(GPIO11_3_6MHz_MD); ++ pxa_gpio_mode(GPIO18_RDY_MD); ++ mdelay(1); ++ set_scoop_gpio(&tosascoop_jc_device.dev, TOSA_SCOOP_JC_TC6393XB_SUSPEND); ++ mdelay(10); ++ set_scoop_gpio(&tosascoop_device.dev, TOSA_SCOOP_TC6393XB_REST_IN); /* #PCLR */ ++ set_scoop_gpio(&tosascoop_jc_device.dev, TOSA_SCOOP_JC_TC6393XB_L3V_ON); ++ ++ return 0; ++} ++ ++static int tosa_tc6393xb_disable(struct platform_device *dev) ++{ ++ ++ reset_scoop_gpio(&tosascoop_jc_device.dev, TOSA_SCOOP_JC_TC6393XB_L3V_ON); ++ reset_scoop_gpio(&tosascoop_jc_device.dev, TOSA_SCOOP_JC_TC6393XB_SUSPEND); ++ reset_scoop_gpio(&tosascoop_device.dev, TOSA_SCOOP_TC6393XB_REST_IN); /* #PCLR */ ++ pxa_gpio_mode(GPIO11_3_6MHz_MD|GPIO_OUT); ++ GPSR0 = GPIO_bit(GPIO11_3_6MHz); ++ ++ return 0; ++} ++ ++static int tosa_tc6393xb_resume(struct platform_device *dev) ++{ ++ ++ pxa_gpio_mode(GPIO11_3_6MHz_MD); ++ pxa_gpio_mode(GPIO18_RDY_MD); ++ mdelay(1); ++ set_scoop_gpio(&tosascoop_jc_device.dev, TOSA_SCOOP_JC_TC6393XB_SUSPEND); ++ mdelay(10); ++ set_scoop_gpio(&tosascoop_jc_device.dev, TOSA_SCOOP_JC_TC6393XB_L3V_ON); ++ mdelay(10); ++ ++ return 0; ++} ++ ++static int tosa_tc6393xb_suspend(struct platform_device *dev) ++{ ++ ++ reset_scoop_gpio(&tosascoop_jc_device.dev, TOSA_SCOOP_JC_TC6393XB_L3V_ON); ++ reset_scoop_gpio(&tosascoop_jc_device.dev, TOSA_SCOOP_JC_TC6393XB_SUSPEND); ++ pxa_gpio_mode(GPIO11_3_6MHz_MD|GPIO_OUT); ++ GPSR0 = GPIO_bit(GPIO11_3_6MHz); ++ ++ return 0; ++} ++ ++static struct mtd_partition tosa_nand_partition[] = { ++ { ++ .name = "smf", ++ .offset = 0, ++ .size = 7 * 1024 * 1024, ++ }, ++ { ++ .name = "root", ++ .offset = MTDPART_OFS_APPEND, ++ .size = 28 * 1024 * 1024, ++ }, ++ { ++ .name = "home", ++ .offset = MTDPART_OFS_APPEND, ++ .size = MTDPART_SIZ_FULL, ++ }, ++}; ++ ++static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; ++ ++static struct nand_bbt_descr tosa_tc6393xb_nand_bbt = { ++ .options = 0, ++ .offs = 4, ++ .len = 2, ++ .pattern = scan_ff_pattern ++}; ++ ++static struct tmio_nand_data tosa_tc6393xb_nand_config = { ++ .num_partitions = ARRAY_SIZE(tosa_nand_partition), ++ .partition = tosa_nand_partition, ++ .badblock_pattern = &tosa_tc6393xb_nand_bbt, ++}; ++ ++static struct fb_videomode tosa_tc6393xb_lcd_mode[] = { ++ { ++ .xres = 480, ++ .yres = 640, ++ .pixclock = 0x002cdf00,/* PLL divisor */ ++ .left_margin = 0x004c, ++ .right_margin = 0x005b, ++ .upper_margin = 0x0001, ++ .lower_margin = 0x000d, ++ .hsync_len = 0x0002, ++ .vsync_len = 0x0001, ++ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, ++ .vmode = FB_VMODE_NONINTERLACED, ++ },{ ++ .xres = 240, ++ .yres = 320, ++ .pixclock = 0x00e7f203,/* PLL divisor */ ++ .left_margin = 0x0024, ++ .right_margin = 0x002f, ++ .upper_margin = 0x0001, ++ .lower_margin = 0x000d, ++ .hsync_len = 0x0002, ++ .vsync_len = 0x0001, ++ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, ++ .vmode = FB_VMODE_NONINTERLACED, ++ } ++}; ++ ++static struct tmio_fb_data tosa_tc6393xb_fb_config = { ++ .lcd_set_power = tc6393xb_lcd_set_power, ++ .lcd_mode = tc6393xb_lcd_mode, ++ .num_modes = ARRAY_SIZE(tosa_tc6393xb_lcd_mode), ++ .modes = &tosa_tc6393xb_lcd_mode[0], ++}; ++ ++static struct tc6393xb_platform_data tosa_tc6393xb_setup = { ++ .scr_pll2cr = 0x0cc1, ++ .scr_ccr = TC6393XB_CCR_UNK1 | TC6393XB_CCR_HCLK_48, ++ .scr_gper = 0x3300, ++ .scr_gpo_dsr = TOSA_TC6393XB_CARD_VCC_ON | TOSA_TC6393XB_CHARGE_OFF_JC, ++ .scr_gpo_doecr = TOSA_TC6393XB_GPO_OE, ++ ++ .irq_base = IRQ_BOARD_START, ++ ++ .enable = tosa_tc6393xb_enable, ++ .disable = tosa_tc6393xb_disable, ++ .suspend = tosa_tc6393xb_suspend, ++ .resume = tosa_tc6393xb_resume, ++ ++ .nand_data = &tosa_tc6393xb_nand_config, ++ .fb_data = &tosa_tc6393xb_fb_config, ++}; ++ ++ ++struct platform_device tc6393xb_device = { ++ .name = "tc6393xb", ++ .id = -1, ++ .dev = { ++ .platform_data = &tosa_tc6393xb_setup, ++ }, ++ .num_resources = ARRAY_SIZE(tc6393xb_resources), ++ .resource = tc6393xb_resources, ++}; ++EXPORT_SYMBOL(tc6393xb_device); ++ + static struct platform_device *devices[] __initdata = { + &tosascoop_device, + &tosascoop_jc_device, + &tosakbd_device, + &tosa_gpio_keys_device, + &tosaled_device, ++ &tc6393xb_device, + }; + + static void tosa_poweroff(void) +@@ -332,7 +509,7 @@ static void __init tosa_init(void) + arm_pm_restart = tosa_restart; + + pxa_gpio_mode(TOSA_GPIO_ON_RESET | GPIO_IN); +- pxa_gpio_mode(TOSA_GPIO_TC6393_INT | GPIO_IN); ++ pxa_gpio_mode(TOSA_GPIO_TC6393XB_INT | GPIO_IN); + pxa_gpio_mode(TOSA_GPIO_USB_IN | GPIO_IN); + + /* setup sleep mode values */ +diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h +index b76ee6d..bf622d8 100644 +--- a/include/asm-arm/arch-pxa/irqs.h ++++ b/include/asm-arm/arch-pxa/irqs.h +@@ -180,6 +180,7 @@ + #define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) + #elif defined(CONFIG_ARCH_LUBBOCK) || \ + defined(CONFIG_MACH_LOGICPD_PXA270) || \ ++ defined(CONFIG_MACH_TOSA) || \ + defined(CONFIG_MACH_MAINSTONE) + #define NR_IRQS (IRQ_BOARD_END) + #else +diff --git a/include/asm-arm/arch-pxa/tosa.h b/include/asm-arm/arch-pxa/tosa.h +index c05e4fa..1b202b2 100644 +--- a/include/asm-arm/arch-pxa/tosa.h ++++ b/include/asm-arm/arch-pxa/tosa.h +@@ -20,11 +20,35 @@ + /* Jacket Scoop */ + #define TOSA_SCOOP_PHYS (PXA_CS5_PHYS + 0x00800000) + ++#define TC6393XB_GPIO(i) (1 << (i)) ++/* ++ * TC6393 GPIOs ++ */ ++#define TOSA_TC6393XB_TG_ON TC6393XB_GPIO(0) ++#define TOSA_TC6393XB_L_MUTE TC6393XB_GPIO(1) ++#define TOSA_TC6393XB_BL_C20MA TC6393XB_GPIO(3) ++#define TOSA_TC6393XB_CARD_VCC_ON TC6393XB_GPIO(4) ++#define TOSA_TC6393XB_CHARGE_OFF TC6393XB_GPIO(6) ++#define TOSA_TC6393XB_CHARGE_OFF_JC TC6393XB_GPIO(7) ++#define TOSA_TC6393XB_BAT0_V_ON TC6393XB_GPIO(9) ++#define TOSA_TC6393XB_BAT1_V_ON TC6393XB_GPIO(10) ++#define TOSA_TC6393XB_BU_CHRG_ON TC6393XB_GPIO(11) ++#define TOSA_TC6393XB_BAT_SW_ON TC6393XB_GPIO(12) ++#define TOSA_TC6393XB_BAT0_TH_ON TC6393XB_GPIO(14) ++#define TOSA_TC6393XB_BAT1_TH_ON TC6393XB_GPIO(15) ++ ++#define TOSA_TC6393XB_GPO_OE (TOSA_TC6393XB_TG_ON | TOSA_TC6393XB_L_MUTE | TOSA_TC6393XB_BL_C20MA | \ ++ TOSA_TC6393XB_CARD_VCC_ON | TOSA_TC6393XB_CHARGE_OFF | \ ++ TOSA_TC6393XB_CHARGE_OFF_JC | TOSA_TC6393XB_BAT0_V_ON | \ ++ TOSA_TC6393XB_BAT1_V_ON | TOSA_TC6393XB_BU_CHRG_ON | \ ++ TOSA_TC6393XB_BAT_SW_ON | TOSA_TC6393XB_BAT0_TH_ON | \ ++ TOSA_TC6393XB_BAT1_TH_ON) ++ + /* + * SCOOP2 internal GPIOs + */ + #define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11 +-#define TOSA_SCOOP_TC6393_REST_IN SCOOP_GPCR_PA12 ++#define TOSA_SCOOP_TC6393XB_REST_IN SCOOP_GPCR_PA12 + #define TOSA_SCOOP_IR_POWERDWN SCOOP_GPCR_PA13 + #define TOSA_SCOOP_SD_WP SCOOP_GPCR_PA14 + #define TOSA_SCOOP_PWR_ON SCOOP_GPCR_PA15 +@@ -34,11 +58,11 @@ + #define TOSA_SCOOP_AC_IN_OL SCOOP_GPCR_PA19 + + /* GPIO Direction 1 : output mode / 0:input mode */ +-#define TOSA_SCOOP_IO_DIR ( TOSA_SCOOP_PXA_VCORE1 | TOSA_SCOOP_TC6393_REST_IN | \ ++#define TOSA_SCOOP_IO_DIR ( TOSA_SCOOP_PXA_VCORE1 | TOSA_SCOOP_TC6393XB_REST_IN | \ + TOSA_SCOOP_IR_POWERDWN | TOSA_SCOOP_PWR_ON | TOSA_SCOOP_AUD_PWR_ON |\ + TOSA_SCOOP_BT_RESET | TOSA_SCOOP_BT_PWR_EN ) + /* GPIO out put level when init 1: Hi */ +-#define TOSA_SCOOP_IO_OUT ( TOSA_SCOOP_TC6393_REST_IN ) ++#define TOSA_SCOOP_IO_OUT ( TOSA_SCOOP_TC6393XB_REST_IN ) + + /* + * SCOOP2 jacket GPIOs +@@ -47,8 +71,8 @@ + #define TOSA_SCOOP_JC_NOTE_LED SCOOP_GPCR_PA12 + #define TOSA_SCOOP_JC_CHRG_ERR_LED SCOOP_GPCR_PA13 + #define TOSA_SCOOP_JC_USB_PULLUP SCOOP_GPCR_PA14 +-#define TOSA_SCOOP_JC_TC6393_SUSPEND SCOOP_GPCR_PA15 +-#define TOSA_SCOOP_JC_TC3693_L3V_ON SCOOP_GPCR_PA16 ++#define TOSA_SCOOP_JC_TC6393XB_SUSPEND SCOOP_GPCR_PA15 ++#define TOSA_SCOOP_JC_TC6393XB_L3V_ON SCOOP_GPCR_PA16 + #define TOSA_SCOOP_JC_WLAN_DETECT SCOOP_GPCR_PA17 + #define TOSA_SCOOP_JC_WLAN_LED SCOOP_GPCR_PA18 + #define TOSA_SCOOP_JC_CARD_LIMIT_SEL SCOOP_GPCR_PA19 +@@ -56,7 +80,7 @@ + /* GPIO Direction 1 : output mode / 0:input mode */ + #define TOSA_SCOOP_JC_IO_DIR ( TOSA_SCOOP_JC_BT_LED | TOSA_SCOOP_JC_NOTE_LED | \ + TOSA_SCOOP_JC_CHRG_ERR_LED | TOSA_SCOOP_JC_USB_PULLUP | \ +- TOSA_SCOOP_JC_TC6393_SUSPEND | TOSA_SCOOP_JC_TC3693_L3V_ON | \ ++ TOSA_SCOOP_JC_TC6393XB_SUSPEND | TOSA_SCOOP_JC_TC6393XB_L3V_ON | \ + TOSA_SCOOP_JC_WLAN_LED | TOSA_SCOOP_JC_CARD_LIMIT_SEL ) + /* GPIO out put level when init 1: Hi */ + #define TOSA_SCOOP_JC_IO_OUT ( 0 ) +@@ -94,13 +118,13 @@ + #define TOSA_GPIO_JACKET_DETECT (7) + #define TOSA_GPIO_nSD_DETECT (9) + #define TOSA_GPIO_nSD_INT (10) +-#define TOSA_GPIO_TC6393_CLK (11) ++#define TOSA_GPIO_TC6393XB_CLK (11) + #define TOSA_GPIO_BAT1_CRG (12) + #define TOSA_GPIO_CF_CD (13) + #define TOSA_GPIO_BAT0_CRG (14) +-#define TOSA_GPIO_TC6393_INT (15) ++#define TOSA_GPIO_TC6393XB_INT (15) + #define TOSA_GPIO_BAT0_LOW (17) +-#define TOSA_GPIO_TC6393_RDY (18) ++#define TOSA_GPIO_TC6393XB_RDY (18) + #define TOSA_GPIO_ON_RESET (19) + #define TOSA_GPIO_EAR_IN (20) + #define TOSA_GPIO_CF_IRQ (21) /* CF slot0 Ready */ +@@ -147,7 +171,7 @@ + #define TOSA_IRQ_GPIO_BAT1_CRG IRQ_GPIO(TOSA_GPIO_BAT1_CRG) + #define TOSA_IRQ_GPIO_CF_CD IRQ_GPIO(TOSA_GPIO_CF_CD) + #define TOSA_IRQ_GPIO_BAT0_CRG IRQ_GPIO(TOSA_GPIO_BAT0_CRG) +-#define TOSA_IRQ_GPIO_TC6393_INT IRQ_GPIO(TOSA_GPIO_TC6393_INT) ++#define TOSA_IRQ_GPIO_TC6393XB_INT IRQ_GPIO(TOSA_GPIO_TC6393XB_INT) + #define TOSA_IRQ_GPIO_BAT0_LOW IRQ_GPIO(TOSA_GPIO_BAT0_LOW) + #define TOSA_IRQ_GPIO_EAR_IN IRQ_GPIO(TOSA_GPIO_EAR_IN) + #define TOSA_IRQ_GPIO_CF_IRQ IRQ_GPIO(TOSA_GPIO_CF_IRQ) +@@ -161,6 +185,7 @@ + + #define TOSA_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(TOSA_GPIO_MAIN_BAT_LOW) + ++extern struct platform_device tc6393xb_device; + extern struct platform_device tosascoop_jc_device; + extern struct platform_device tosascoop_device; + +diff --git a/sound/soc/pxa/tosa.c b/sound/soc/pxa/tosa.c +index 5504e30..21c51b5 100644 +--- a/sound/soc/pxa/tosa.c ++++ b/sound/soc/pxa/tosa.c +@@ -32,7 +32,6 @@ + #include <sound/soc-dapm.h> + + #include <asm/mach-types.h> +-#include <asm/hardware/tmio.h> + #include <asm/arch/pxa-regs.h> + #include <asm/arch/hardware.h> + #include <asm/arch/audio.h> +@@ -138,10 +137,12 @@ static int tosa_set_spk(struct snd_kcontrol *kcontrol, + /* tosa dapm event handlers */ + static int tosa_hp_event(struct snd_soc_dapm_widget *w, int event) + { ++#if 0 + if (SND_SOC_DAPM_EVENT_ON(event)) + set_tc6393_gpio(&tc6393_device.dev,TOSA_TC6393_L_MUTE); + else + reset_tc6393_gpio(&tc6393_device.dev,TOSA_TC6393_L_MUTE); ++#endif + return 0; + } + +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0050-tosa-update-for-tc6393xb-gpio.patch b/packages/linux/linux-rp-2.6.24/tosa/0050-tosa-update-for-tc6393xb-gpio.patch new file mode 100644 index 0000000000..c9b5ac29d4 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0050-tosa-update-for-tc6393xb-gpio.patch @@ -0,0 +1,99 @@ +From f24c23ba56cdd072b332e8de3e0cff8a31e7e36a Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Wed, 9 Jan 2008 02:03:19 +0300 +Subject: [PATCH 50/64] tosa update for tc6393xb gpio + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + arch/arm/mach-pxa/tosa.c | 6 +++++- + include/asm-arm/arch-pxa/tosa.h | 36 ++++++++++++++++++++++++------------ + 2 files changed, 29 insertions(+), 13 deletions(-) + +diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c +index e2eec0f..3e832dc 100644 +--- a/arch/arm/mach-pxa/tosa.c ++++ b/arch/arm/mach-pxa/tosa.c +@@ -35,6 +35,7 @@ + #include <asm/mach-types.h> + #include <asm/hardware.h> + #include <asm/irq.h> ++#include <asm/gpio.h> + #include <asm/system.h> + #include <asm/arch/pxa-regs.h> + #include <asm/arch/irda.h> +@@ -448,10 +449,13 @@ static struct tc6393xb_platform_data tosa_tc6393xb_setup = { + .scr_pll2cr = 0x0cc1, + .scr_ccr = TC6393XB_CCR_UNK1 | TC6393XB_CCR_HCLK_48, + .scr_gper = 0x3300, +- .scr_gpo_dsr = TOSA_TC6393XB_CARD_VCC_ON | TOSA_TC6393XB_CHARGE_OFF_JC, ++ .scr_gpo_dsr = ++ TC6393XB_GPIO_BIT(TOSA_TC6393XB_CARD_VCC_ON) | ++ TC6393XB_GPIO_BIT(TOSA_TC6393XB_CHARGE_OFF_JC), + .scr_gpo_doecr = TOSA_TC6393XB_GPO_OE, + + .irq_base = IRQ_BOARD_START, ++ .gpio_base = TOSA_TC6393XB_GPIO_BASE, + + .enable = tosa_tc6393xb_enable, + .disable = tosa_tc6393xb_disable, +diff --git a/include/asm-arm/arch-pxa/tosa.h b/include/asm-arm/arch-pxa/tosa.h +index 1b202b2..410fa9a 100644 +--- a/include/asm-arm/arch-pxa/tosa.h ++++ b/include/asm-arm/arch-pxa/tosa.h +@@ -20,16 +20,21 @@ + /* Jacket Scoop */ + #define TOSA_SCOOP_PHYS (PXA_CS5_PHYS + 0x00800000) + +-#define TC6393XB_GPIO(i) (1 << (i)) + /* + * TC6393 GPIOs + */ +-#define TOSA_TC6393XB_TG_ON TC6393XB_GPIO(0) +-#define TOSA_TC6393XB_L_MUTE TC6393XB_GPIO(1) +-#define TOSA_TC6393XB_BL_C20MA TC6393XB_GPIO(3) +-#define TOSA_TC6393XB_CARD_VCC_ON TC6393XB_GPIO(4) ++ ++#define TOSA_TC6393XB_GPIO_BASE NR_BUILTIN_GPIO ++ ++#define TC6393XB_GPIO(i) (TOSA_TC6393XB_GPIO_BASE + (i)) ++#define TC6393XB_GPIO_BIT(gpio) (1 << (gpio - TOSA_TC6393XB_GPIO_BASE)) ++ ++#define TOSA_TC6393XB_TG_ON TC6393XB_GPIO(0) ++#define TOSA_TC6393XB_L_MUTE TC6393XB_GPIO(1) ++#define TOSA_TC6393XB_BL_C20MA TC6393XB_GPIO(3) ++#define TOSA_TC6393XB_CARD_VCC_ON TC6393XB_GPIO(4) + #define TOSA_TC6393XB_CHARGE_OFF TC6393XB_GPIO(6) +-#define TOSA_TC6393XB_CHARGE_OFF_JC TC6393XB_GPIO(7) ++#define TOSA_TC6393XB_CHARGE_OFF_JC TC6393XB_GPIO(7) + #define TOSA_TC6393XB_BAT0_V_ON TC6393XB_GPIO(9) + #define TOSA_TC6393XB_BAT1_V_ON TC6393XB_GPIO(10) + #define TOSA_TC6393XB_BU_CHRG_ON TC6393XB_GPIO(11) +@@ -37,12 +42,19 @@ + #define TOSA_TC6393XB_BAT0_TH_ON TC6393XB_GPIO(14) + #define TOSA_TC6393XB_BAT1_TH_ON TC6393XB_GPIO(15) + +-#define TOSA_TC6393XB_GPO_OE (TOSA_TC6393XB_TG_ON | TOSA_TC6393XB_L_MUTE | TOSA_TC6393XB_BL_C20MA | \ +- TOSA_TC6393XB_CARD_VCC_ON | TOSA_TC6393XB_CHARGE_OFF | \ +- TOSA_TC6393XB_CHARGE_OFF_JC | TOSA_TC6393XB_BAT0_V_ON | \ +- TOSA_TC6393XB_BAT1_V_ON | TOSA_TC6393XB_BU_CHRG_ON | \ +- TOSA_TC6393XB_BAT_SW_ON | TOSA_TC6393XB_BAT0_TH_ON | \ +- TOSA_TC6393XB_BAT1_TH_ON) ++#define TOSA_TC6393XB_GPO_OE ( \ ++ TC6393XB_GPIO_BIT(TOSA_TC6393XB_TG_ON) | \ ++ TC6393XB_GPIO_BIT(TOSA_TC6393XB_L_MUTE) | \ ++ TC6393XB_GPIO_BIT(TOSA_TC6393XB_BL_C20MA) | \ ++ TC6393XB_GPIO_BIT(TOSA_TC6393XB_CARD_VCC_ON) | \ ++ TC6393XB_GPIO_BIT(TOSA_TC6393XB_CHARGE_OFF) | \ ++ TC6393XB_GPIO_BIT(TOSA_TC6393XB_CHARGE_OFF_JC) | \ ++ TC6393XB_GPIO_BIT(TOSA_TC6393XB_BAT0_V_ON) | \ ++ TC6393XB_GPIO_BIT(TOSA_TC6393XB_BAT1_V_ON) | \ ++ TC6393XB_GPIO_BIT(TOSA_TC6393XB_BU_CHRG_ON) | \ ++ TC6393XB_GPIO_BIT(TOSA_TC6393XB_BAT_SW_ON) | \ ++ TC6393XB_GPIO_BIT(TOSA_TC6393XB_BAT0_TH_ON) | \ ++ TC6393XB_GPIO_BIT(TOSA_TC6393XB_BAT1_TH_ON)) + + /* + * SCOOP2 internal GPIOs +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0051-fix-sound-soc-pxa-tosa.c-to-new-gpio-api.patch b/packages/linux/linux-rp-2.6.24/tosa/0051-fix-sound-soc-pxa-tosa.c-to-new-gpio-api.patch new file mode 100644 index 0000000000..585f1af288 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0051-fix-sound-soc-pxa-tosa.c-to-new-gpio-api.patch @@ -0,0 +1,86 @@ +From 38ef1b452cc3138157b92d02b31cad439d12d0ca Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Wed, 9 Jan 2008 02:03:34 +0300 +Subject: [PATCH 51/64] fix sound/soc/pxa/tosa.c to new gpio api + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + sound/soc/pxa/tosa.c | 33 ++++++++++++++++++++++++++------- + 1 files changed, 26 insertions(+), 7 deletions(-) + +diff --git a/sound/soc/pxa/tosa.c b/sound/soc/pxa/tosa.c +index 21c51b5..b758de8 100644 +--- a/sound/soc/pxa/tosa.c ++++ b/sound/soc/pxa/tosa.c +@@ -36,6 +36,7 @@ + #include <asm/arch/hardware.h> + #include <asm/arch/audio.h> + #include <asm/arch/tosa.h> ++#include <asm/gpio.h> + + #include "../codecs/wm9712.h" + #include "pxa2xx-pcm.h" +@@ -137,11 +138,11 @@ static int tosa_set_spk(struct snd_kcontrol *kcontrol, + /* tosa dapm event handlers */ + static int tosa_hp_event(struct snd_soc_dapm_widget *w, int event) + { +-#if 0 ++#ifdef CONFIG_MFD_TC6393XB + if (SND_SOC_DAPM_EVENT_ON(event)) +- set_tc6393_gpio(&tc6393_device.dev,TOSA_TC6393_L_MUTE); ++ gpio_set_value(TOSA_TC6393XB_L_MUTE, 1); + else +- reset_tc6393_gpio(&tc6393_device.dev,TOSA_TC6393_L_MUTE); ++ gpio_set_value(TOSA_TC6393XB_L_MUTE, 0); + #endif + return 0; + } +@@ -262,16 +263,31 @@ static int __init tosa_init(void) + if (!machine_is_tosa()) + return -ENODEV; + ++#ifdef CONFIG_MFD_TC6393XB ++ ret = gpio_request(TOSA_TC6393XB_L_MUTE, "Headphone Jack"); ++ if (ret) ++ return ret; ++ gpio_direction_output(TOSA_TC6393XB_L_MUTE, 0); ++#endif + tosa_snd_device = platform_device_alloc("soc-audio", -1); +- if (!tosa_snd_device) +- return -ENOMEM; ++ if (!tosa_snd_device) { ++ ret = -ENOMEM; ++ goto err_alloc; ++ } + + platform_set_drvdata(tosa_snd_device, &tosa_snd_devdata); + tosa_snd_devdata.dev = &tosa_snd_device->dev; + ret = platform_device_add(tosa_snd_device); + +- if (ret) +- platform_device_put(tosa_snd_device); ++ if (!ret) ++ return 0; ++ ++ platform_device_put(tosa_snd_device); ++ ++err_alloc: ++#ifdef CONFIG_MFD_TC6393XB ++ gpio_free(TOSA_TC6393XB_L_MUTE); ++#endif + + return ret; + } +@@ -279,6 +295,9 @@ static int __init tosa_init(void) + static void __exit tosa_exit(void) + { + platform_device_unregister(tosa_snd_device); ++#ifdef CONFIG_MFD_TC6393XB ++ gpio_free(TOSA_TC6393XB_L_MUTE); ++#endif + } + + module_init(tosa_init); +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0052-tosa-platform-backlight-support.patch b/packages/linux/linux-rp-2.6.24/tosa/0052-tosa-platform-backlight-support.patch new file mode 100644 index 0000000000..ef5263c18e --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0052-tosa-platform-backlight-support.patch @@ -0,0 +1,400 @@ +From c7537657bc33d4ee1616accd0259e160d57c5c1b Mon Sep 17 00:00:00 2001 +From: Ian Molton <spyro@f2s.com> +Date: Wed, 9 Jan 2008 02:05:40 +0300 +Subject: [PATCH 52/64] tosa platform backlight support + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + drivers/video/backlight/Kconfig | 10 + + drivers/video/backlight/Makefile | 1 + + drivers/video/backlight/tosa_bl.c | 345 +++++++++++++++++++++++++++++++++++++ + 3 files changed, 356 insertions(+), 0 deletions(-) + create mode 100644 drivers/video/backlight/tosa_bl.c + +diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig +index 9609a6c..f47a601 100644 +--- a/drivers/video/backlight/Kconfig ++++ b/drivers/video/backlight/Kconfig +@@ -59,6 +59,16 @@ config BACKLIGHT_CORGI + known as the Corgi backlight driver. If you have a Sharp Zaurus + SL-C7xx, SL-Cxx00 or SL-6000x say y. Most users can say n. + ++config BACKLIGHT_TOSA ++ tristate "Sharp Tosa LCD/Backlight Driver (SL-6000)" ++ depends on BACKLIGHT_CLASS_DEVICE && MACH_TOSA ++ default y ++ select I2C ++ select I2C_PXA ++ select PXA_SSP ++ help ++ If you have a Sharp Zaurus SL-6000y enable this driver. ++ + config BACKLIGHT_LOCOMO + tristate "Sharp LOCOMO LCD/Backlight Driver" + depends on BACKLIGHT_CLASS_DEVICE && SHARP_LOCOMO +diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile +index 965a78b..e8a6a7c 100644 +--- a/drivers/video/backlight/Makefile ++++ b/drivers/video/backlight/Makefile +@@ -5,6 +5,7 @@ obj-$(CONFIG_LCD_LTV350QV) += ltv350qv.o + + obj-$(CONFIG_BACKLIGHT_CLASS_DEVICE) += backlight.o + obj-$(CONFIG_BACKLIGHT_CORGI) += corgi_bl.o ++obj-$(CONFIG_BACKLIGHT_TOSA) += tosa_bl.o + obj-$(CONFIG_BACKLIGHT_HP680) += hp680_bl.o + obj-$(CONFIG_BACKLIGHT_LOCOMO) += locomolcd.o + obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o +diff --git a/drivers/video/backlight/tosa_bl.c b/drivers/video/backlight/tosa_bl.c +new file mode 100644 +index 0000000..11a89c6 +--- /dev/null ++++ b/drivers/video/backlight/tosa_bl.c +@@ -0,0 +1,345 @@ ++/* ++ * LCD / Backlight control code for Sharp SL-6000x (tosa) ++ * ++ * Copyright (c) 2005 Dirk Opfer ++ * Copyright (c) 2007 Dmitry Baryshkov ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/i2c.h> ++#include <linux/backlight.h> ++#include <linux/platform_device.h> ++#include <linux/delay.h> ++#include <linux/fb.h> ++#include <linux/mfd/tc6393xb.h> ++ ++#include <asm/hardware/scoop.h> ++#include <asm/mach/sharpsl_param.h> ++#include <asm/arch/ssp.h> ++#include <asm/arch/pxa-regs.h> ++#include <asm/arch/tosa.h> ++#include <asm/gpio.h> ++ ++#define DAC_BASE 0x4e ++#define DAC_CH1 0 ++#define DAC_CH2 1 ++ ++#define TG_REG0_VQV 0x0001 ++#define TG_REG0_COLOR 0x0002 ++#define TG_REG0_UD 0x0004 ++#define TG_REG0_LR 0x0008 ++#define COMADJ_DEFAULT 97 ++ ++static unsigned short normal_i2c[] = { DAC_BASE, I2C_CLIENT_END }; ++I2C_CLIENT_INSMOD; ++ ++struct tosa_bl_data { ++ struct i2c_client client; ++ ++ int comadj; ++ spinlock_t nssp_lock; ++ struct ssp_dev nssp_dev; ++ struct ssp_state nssp_state; ++ ++ struct backlight_device *bl_dev; ++}; ++ ++static struct i2c_driver tosa_bl_driver; ++ ++static void pxa_nssp_output(struct tosa_bl_data *data, unsigned char reg, unsigned char value) ++{ ++ unsigned long flag; ++ u32 dummy; ++ u32 dat = ( ((reg << 5) & 0xe0) | (value & 0x1f) ); ++ spin_lock_irqsave(&data->nssp_lock, flag); ++ ++ ssp_config(&data->nssp_dev, (SSCR0_Motorola | (SSCR0_DSS & 0x07 )), 0, 0, SSCR0_SerClkDiv(128)); ++ ssp_enable(&data->nssp_dev); ++ ++ ssp_write_word(&data->nssp_dev,dat); ++ ++ /* Read null data back from device to prevent SSP overflow */ ++ ssp_read_word(&data->nssp_dev, &dummy); ++ ssp_disable(&data->nssp_dev); ++ spin_unlock_irqrestore(&data->nssp_lock, flag); ++ ++} ++ ++static void tosa_set_backlight(struct tosa_bl_data *data, int brightness) ++{ ++ /* SetBacklightDuty */ ++ i2c_smbus_write_byte_data(&data->client, DAC_CH2, (unsigned char)brightness); ++ ++ /* SetBacklightVR */ ++ if (brightness) ++ gpio_set_value(TOSA_TC6393XB_BL_C20MA, 1); ++ else ++ gpio_set_value(TOSA_TC6393XB_BL_C20MA, 0); ++ ++ /* bl_enable GP04=1 otherwise GP04=0*/ ++ pxa_nssp_output(data, TG_GPODR2, brightness ? 0x01 : 0x00); ++} ++ ++static void tosa_lcd_tg_init(struct tosa_bl_data *data) ++{ ++ dev_dbg(&data->bl_dev->dev, "tosa_lcd_init\n"); ++ ++ /* L3V On */ ++ set_scoop_gpio( &tosascoop_jc_device.dev,TOSA_SCOOP_JC_TC6393XB_L3V_ON); ++ mdelay(60); ++ ++ /* TG On */ ++ gpio_set_value(TOSA_TC6393XB_TG_ON, 0); ++ mdelay(60); ++ ++ pxa_nssp_output(data, TG_TPOSCTL,0x00); /* delayed 0clk TCTL signal for VGA */ ++ pxa_nssp_output(data, TG_GPOSR,0x02); /* GPOS0=powercontrol, GPOS1=GPIO, GPOS2=TCTL */ ++} ++ ++static void tosa_lcd_tg_on(struct tosa_bl_data *data/*, const struct fb_videomode *mode*/) ++{ ++ const int value = TG_REG0_COLOR | TG_REG0_UD | TG_REG0_LR; ++ ++ tosa_lcd_tg_init(data); ++ ++ dev_dbg(&data->bl_dev->dev, "tosa_lcd_on\n"); ++ pxa_nssp_output(data, TG_PNLCTL, value | (/*mode->yres == 320 ? 0 : */ TG_REG0_VQV)); ++ ++ /* TG LCD pannel power up */ ++ pxa_nssp_output(data, TG_PINICTL,0x4); ++ mdelay(50); ++ ++ /* TG LCD GVSS */ ++ pxa_nssp_output(data, TG_PINICTL,0x0); ++ mdelay(50); ++ ++ /* set common voltage */ ++ i2c_smbus_write_byte_data(&data->client, DAC_CH1, data->comadj); ++} ++ ++static void tosa_lcd_tg_off(struct tosa_bl_data *data) ++{ ++ tosa_set_backlight(data, 0); ++ dev_dbg(&data->bl_dev->dev, "tosa_lcd_off\n"); ++ /* TG LCD VHSA off */ ++ pxa_nssp_output(data, TG_PINICTL,0x4); ++ mdelay(50); ++ ++ /* TG LCD signal off */ ++ pxa_nssp_output(data, TG_PINICTL,0x6); ++ mdelay(50); ++ ++ /* TG Off */ ++ gpio_set_value(TOSA_TC6393XB_TG_ON, 1); ++ mdelay(100); ++ ++ /* L3V Off */ ++ reset_scoop_gpio( &tosascoop_jc_device.dev,TOSA_SCOOP_JC_TC6393XB_L3V_ON); ++} ++ ++ ++static int tosa_bl_update_status(struct backlight_device *dev) ++{ ++ struct backlight_properties *props = &dev->props; ++ struct tosa_bl_data *data = dev_get_drvdata(&dev->dev); ++ int new_power = max(props->power, props->fb_blank); ++ ++ tosa_set_backlight(data, props->brightness); ++ ++ if (new_power) ++ tosa_lcd_tg_off(data); ++ else ++ tosa_lcd_tg_on(data); ++ ++ return 0; ++} ++ ++static int tosa_bl_get_brightness(struct backlight_device *dev) ++{ ++ struct backlight_properties *props = &dev->props; ++ ++ return props->brightness; ++} ++ ++static struct backlight_ops tosa_bl_ops = { ++ .get_brightness = tosa_bl_get_brightness, ++ .update_status = tosa_bl_update_status, ++}; ++ ++static int tosa_bl_detect_client(struct i2c_adapter *adapter, int address, ++ int kind) ++{ ++ int err = 0; ++ struct i2c_client *client; ++ struct tosa_bl_data *data; ++ ++ if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA )) ++ goto out; ++ ++ if (!(data = kzalloc(sizeof(struct tosa_bl_data), GFP_KERNEL))) { ++ err = -ENOMEM; ++ goto out; ++ } ++ ++ client = &data->client; ++ i2c_set_clientdata(client, data); ++ ++ client->addr = address; ++ client->adapter = adapter; ++ client->driver = &tosa_bl_driver; ++ ++ strlcpy(client->name, "tosa_bl", I2C_NAME_SIZE); ++ ++ spin_lock_init(&data->nssp_lock); ++ data->comadj = sharpsl_param.comadj == -1 ? COMADJ_DEFAULT : sharpsl_param.comadj; ++ ++ err = gpio_request(TOSA_TC6393XB_BL_C20MA, "backlight"); ++ if (err) { ++ dev_dbg(&data->bl_dev->dev, "Unable to request gpio!\n"); ++ goto err_gpio_bl; ++ } ++ ++ err = gpio_request(TOSA_TC6393XB_TG_ON, "tg"); ++ if (err) { ++ dev_dbg(&data->bl_dev->dev, "Unable to request gpio!\n"); ++ goto err_gpio_tg; ++ } ++ ++ err = ssp_init(&data->nssp_dev,2,0); ++ if (err) { ++ dev_err(&data->bl_dev->dev, "Unable to register NSSP handler!\n"); ++ goto err_ssp_init; ++ } ++ ++ /* Tell the i2c layer a new client has arrived */ ++ err = i2c_attach_client(client); ++ if (err) ++ goto err_i2c_attach; ++ ++ gpio_direction_output(TOSA_TC6393XB_BL_C20MA, 0); ++ gpio_direction_output(TOSA_TC6393XB_TG_ON, 1); ++ ++ tosa_lcd_tg_init(data); ++ ++ data->bl_dev = backlight_device_register("tosa_bl", ++ &client->dev, data, &tosa_bl_ops); ++ if (err) ++ goto err_bl_register; ++ ++ data->bl_dev->props.brightness = 69; ++ data->bl_dev->props.max_brightness = 255; ++ data->bl_dev->props.power = FB_BLANK_UNBLANK; ++ backlight_update_status(data->bl_dev); ++ ++ ++ return 0; ++ ++err_bl_register: ++ tosa_set_backlight(data, 0); ++ tosa_lcd_tg_off(data); ++ ++ err = i2c_detach_client(client); ++ if (err) ++ return err; ++err_i2c_attach: ++ ssp_exit(&data->nssp_dev); ++err_ssp_init: ++ gpio_free(TOSA_TC6393XB_TG_ON); ++err_gpio_tg: ++ gpio_free(TOSA_TC6393XB_BL_C20MA); ++err_gpio_bl: ++ kfree(data); ++out: ++ return err; ++} ++ ++static int tosa_bl_detach_client(struct i2c_client *client) ++{ ++ int err = 0; ++ struct tosa_bl_data *data = i2c_get_clientdata(client); ++ ++ backlight_device_unregister(data->bl_dev); ++ ++ tosa_set_backlight(data, 0); ++ tosa_lcd_tg_off(data); ++ ++ /* Try to detach the client from i2c space */ ++ if ((err = i2c_detach_client(client))) ++ return err; ++ ++ ssp_exit(&data->nssp_dev); ++ ++ gpio_free(TOSA_TC6393XB_TG_ON); ++ gpio_free(TOSA_TC6393XB_BL_C20MA); ++ ++ kfree(data); ++ ++ return err; ++} ++ ++#ifdef CONFIG_PM ++static int tosa_bl_suspend(struct i2c_client *client, pm_message_t mesg) ++{ ++ struct tosa_bl_data *data = i2c_get_clientdata(client); ++ ++ tosa_lcd_tg_off(data); ++ ssp_flush(&data->nssp_dev); ++ ssp_save_state(&data->nssp_dev,&data->nssp_state); ++ ++ return 0; ++} ++ ++static int tosa_bl_resume(struct i2c_client *client) ++{ ++ struct tosa_bl_data *data = i2c_get_clientdata(client); ++ ++ ssp_restore_state(&data->nssp_dev,&data->nssp_state); ++ ssp_enable(&data->nssp_dev); ++ tosa_bl_update_status(data->bl_dev); ++ ++ return 0; ++} ++#else ++#define tosa_bl_suspend NULL ++#define tosa_bl_resume NULL ++#endif ++ ++static int tosa_bl_attach_adapter(struct i2c_adapter *adapter) ++{ ++ return i2c_probe(adapter, &addr_data, &tosa_bl_detect_client); ++} ++ ++static struct i2c_driver tosa_bl_driver = { ++ .driver = { ++ .name = "tosa_bl", ++ }, ++ ++ .attach_adapter = tosa_bl_attach_adapter, ++ .detach_client = tosa_bl_detach_client, ++ ++ .suspend = tosa_bl_suspend, ++ .resume = tosa_bl_resume, ++}; ++ ++static int __init tosa_bl_init(void) ++{ ++ return i2c_add_driver(&tosa_bl_driver); ++} ++ ++static void __exit tosa_bl_cleanup (void) ++{ ++ i2c_del_driver(&tosa_bl_driver); ++} ++ ++module_init(tosa_bl_init); ++module_exit(tosa_bl_cleanup); ++ ++MODULE_DESCRIPTION("Tosa LCD device"); ++MODULE_AUTHOR("Dirk Opfer, Dmitry Baryshkov"); ++MODULE_LICENSE("GPL v2"); +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0053-sound-soc-codecs-wm9712.c-28.patch b/packages/linux/linux-rp-2.6.24/tosa/0053-sound-soc-codecs-wm9712.c-28.patch new file mode 100644 index 0000000000..0675342508 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0053-sound-soc-codecs-wm9712.c-28.patch @@ -0,0 +1,56 @@ +From 47616d22f8f303dfd66cf3b9125af212194a0f3c Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Wed, 9 Jan 2008 02:08:17 +0300 +Subject: [PATCH 53/64] sound/soc/codecs/wm9712.c | 28 ++++++++++++++++++---------- + 1 file changed, 18 insertions(+), 10 deletions(-) + +Index: git/sound/soc/codecs/wm9712.c +=================================================================== +--- + sound/soc/codecs/wm9712.c | 28 ++++++++++++++++++---------- + 1 files changed, 18 insertions(+), 10 deletions(-) + +diff --git a/sound/soc/codecs/wm9712.c b/sound/soc/codecs/wm9712.c +index 986b5d5..dfb31e1 100644 +--- a/sound/soc/codecs/wm9712.c ++++ b/sound/soc/codecs/wm9712.c +@@ -606,18 +606,26 @@ static int wm9712_dapm_event(struct snd_soc_codec *codec, int event) + + static int wm9712_reset(struct snd_soc_codec *codec, int try_warm) + { +- if (try_warm && soc_ac97_ops.warm_reset) { +- soc_ac97_ops.warm_reset(codec->ac97); +- if (!(ac97_read(codec, 0) & 0x8000)) +- return 1; +- } ++ int retry = 3; + +- soc_ac97_ops.reset(codec->ac97); +- if (ac97_read(codec, 0) & 0x8000) +- goto err; +- return 0; ++ while (retry--) ++ { ++ if(try_warm && soc_ac97_ops.warm_reset) { ++ soc_ac97_ops.warm_reset(codec->ac97); ++ if(ac97_read(codec, 0) & 0x8000) ++ continue; ++ else ++ return 1; ++ } ++ ++ soc_ac97_ops.reset(codec->ac97); ++ if(ac97_read(codec, 0) & 0x8000) ++ continue; ++ else ++ return 0; ++ ++ } + +-err: + printk(KERN_ERR "WM9712 AC97 reset failed\n"); + return -EIO; + } +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0054-sound-soc-codecs-wm9712.c-2.patch b/packages/linux/linux-rp-2.6.24/tosa/0054-sound-soc-codecs-wm9712.c-2.patch new file mode 100644 index 0000000000..be7300ab24 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0054-sound-soc-codecs-wm9712.c-2.patch @@ -0,0 +1,28 @@ +From 08fbae2307163b3f0c3b704c4b00a9447752a45e Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Thu, 10 Jan 2008 17:56:58 +0300 +Subject: [PATCH 54/64] sound/soc/codecs/wm9712.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +Index: git/sound/soc/codecs/wm9712.c +=================================================================== +--- + sound/soc/codecs/wm9712.c | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +diff --git a/sound/soc/codecs/wm9712.c b/sound/soc/codecs/wm9712.c +index dfb31e1..a3d9f96 100644 +--- a/sound/soc/codecs/wm9712.c ++++ b/sound/soc/codecs/wm9712.c +@@ -647,7 +647,7 @@ static int wm9712_soc_resume(struct platform_device *pdev) + int i, ret; + u16 *cache = codec->reg_cache; + +- ret = wm9712_reset(codec, 1); ++ ret = wm9712_reset(codec, 0); + if (ret < 0){ + printk(KERN_ERR "could not reset AC97 codec\n"); + return ret; +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0055-Add-GPIO_POWERON-to-the-list-of-devices-that-we-supp.patch b/packages/linux/linux-rp-2.6.24/tosa/0055-Add-GPIO_POWERON-to-the-list-of-devices-that-we-supp.patch new file mode 100644 index 0000000000..5bf691cbda --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0055-Add-GPIO_POWERON-to-the-list-of-devices-that-we-supp.patch @@ -0,0 +1,30 @@ +From bee8b808445a53a7dbb6c15a27064f14dec410c5 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Sun, 20 Jan 2008 03:01:41 +0300 +Subject: [PATCH 55/64] Add GPIO_POWERON to the list of devices that we support resume on. + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + arch/arm/mach-pxa/tosa.c | 6 +++--- + 1 files changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c +index 3e832dc..d1cf3dc 100644 +--- a/arch/arm/mach-pxa/tosa.c ++++ b/arch/arm/mach-pxa/tosa.c +@@ -517,9 +517,9 @@ static void __init tosa_init(void) + pxa_gpio_mode(TOSA_GPIO_USB_IN | GPIO_IN); + + /* setup sleep mode values */ +- PWER = 0x00000002; +- PFER = 0x00000000; +- PRER = 0x00000002; ++ PWER = BIT(TOSA_GPIO_POWERON) | BIT(TOSA_GPIO_RESET); ++ PFER = 0; ++ PRER = BIT(TOSA_GPIO_POWERON) | BIT(TOSA_GPIO_RESET); + PGSR0 = 0x00000000; + PGSR1 = 0x00FF0002; + PGSR2 = 0x00014000; +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0056-Support-resetting-by-asserting-GPIO-pin.patch b/packages/linux/linux-rp-2.6.24/tosa/0056-Support-resetting-by-asserting-GPIO-pin.patch new file mode 100644 index 0000000000..99220f9200 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0056-Support-resetting-by-asserting-GPIO-pin.patch @@ -0,0 +1,126 @@ +From e039614a0ce6df645f8fa4cbe32e4b21fe46a288 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Sun, 20 Jan 2008 02:44:03 +0300 +Subject: [PATCH 56/64] Support resetting by asserting GPIO pin + +This adds support for resetting via assertion of GPIO pin. +This e.g. is used on Sharp Zaurus SL-6000. + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + arch/arm/mach-pxa/gpio.c | 43 +++++++++++++++++++++++++++++++++++++ + arch/arm/mach-pxa/pm.c | 4 +- + include/asm-arm/arch-pxa/system.h | 10 ++++++++ + 3 files changed, 55 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c +index 8638dd7..589da3b 100644 +--- a/arch/arm/mach-pxa/gpio.c ++++ b/arch/arm/mach-pxa/gpio.c +@@ -19,6 +19,7 @@ + #include <asm/hardware.h> + #include <asm/io.h> + #include <asm/arch/pxa-regs.h> ++#include <asm/arch/system.h> + + #include "generic.h" + +@@ -194,4 +195,46 @@ void __init pxa_init_gpio(int gpio_nr) + pxa_gpio_chip[i/32].chip.ngpio = gpio_nr - i; + gpiochip_add(&pxa_gpio_chip[i/32].chip); + } ++ ++ if (reset_gpio < gpio_nr) ++ init_reset_gpio(); ++} ++ ++int reset_gpio = -1; ++static int __init reset_gpio_setup(char *str) ++{ ++ if (get_option(&str, &reset_gpio) != 1) { ++ printk(KERN_ERR "reset_gpio: bad value secified"); ++ return 0; ++ } ++ ++ return 1; ++} ++ ++__setup("reset_gpio=", reset_gpio_setup); ++ ++int init_reset_gpio(void) ++{ ++ int rc = 0; ++ if (reset_gpio == -1) ++ goto out; ++ ++ rc = gpio_request(reset_gpio, "reset generator"); ++ if (rc) { ++ printk(KERN_ERR "Can't request reset_gpio\n"); ++ goto out; ++ } ++ ++ rc = gpio_direction_input(reset_gpio); ++ if (rc) { ++ printk(KERN_ERR "Can't configure reset_gpio for input\n"); ++ gpio_free(reset_gpio); ++ goto out; ++ } ++ ++out: ++ if (rc) ++ reset_gpio = -1; ++ ++ return rc; + } +diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c +index a941c71..64f37e5 100644 +--- a/arch/arm/mach-pxa/pm.c ++++ b/arch/arm/mach-pxa/pm.c +@@ -40,8 +40,8 @@ int pxa_pm_enter(suspend_state_t state) + + pxa_cpu_pm_fns->save(sleep_save); + +- /* Clear sleep reset status */ +- RCSR = RCSR_SMR; ++ /* Clear reset status */ ++ RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; + + /* before sleeping, calculate and save a checksum */ + for (i = 0; i < pxa_cpu_pm_fns->save_size - 1; i++) +diff --git a/include/asm-arm/arch-pxa/system.h b/include/asm-arm/arch-pxa/system.h +index 1d56a3e..c075018 100644 +--- a/include/asm-arm/arch-pxa/system.h ++++ b/include/asm-arm/arch-pxa/system.h +@@ -11,6 +11,7 @@ + */ + + #include <asm/proc-fns.h> ++#include <asm/gpio.h> + #include "hardware.h" + #include "pxa-regs.h" + +@@ -19,12 +20,21 @@ static inline void arch_idle(void) + cpu_do_idle(); + } + ++extern int reset_gpio; ++ ++int init_reset_gpio(void); + + static inline void arch_reset(char mode) + { ++ RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; ++ + if (mode == 's') { + /* Jump into ROM at address 0 */ + cpu_reset(0); ++ } else if (mode == 'g' && reset_gpio != -1) { ++ /* Use GPIO reset */ ++ gpio_direction_output(reset_gpio, 0); ++ gpio_set_value(reset_gpio, 1); + } else { + /* Initialize the watchdog and let it fire */ + OWER = OWER_WME; +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0057-Clean-up-tosa-resetting.patch b/packages/linux/linux-rp-2.6.24/tosa/0057-Clean-up-tosa-resetting.patch new file mode 100644 index 0000000000..441e1bba75 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0057-Clean-up-tosa-resetting.patch @@ -0,0 +1,70 @@ +From a6f03929fa4d20cef339dbed7ef5cd1e040d0548 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Sun, 20 Jan 2008 02:48:07 +0300 +Subject: [PATCH 57/64] Clean up tosa resetting + +Use new gpio-assertion reset. + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + arch/arm/mach-pxa/tosa.c | 16 +++++++--------- + 1 files changed, 7 insertions(+), 9 deletions(-) + +diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c +index d1cf3dc..2b4aef7 100644 +--- a/arch/arm/mach-pxa/tosa.c ++++ b/arch/arm/mach-pxa/tosa.c +@@ -41,6 +41,8 @@ + #include <asm/arch/irda.h> + #include <asm/arch/mmc.h> + #include <asm/arch/udc.h> ++#include <asm/arch/pm.h> ++#include <asm/arch/system.h> + + #include <asm/mach/arch.h> + #include <asm/mach/map.h> +@@ -489,13 +491,7 @@ static struct platform_device *devices[] __initdata = { + + static void tosa_poweroff(void) + { +- RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; +- +- pxa_gpio_mode(TOSA_GPIO_ON_RESET | GPIO_OUT); +- GPSR(TOSA_GPIO_ON_RESET) = GPIO_bit(TOSA_GPIO_ON_RESET); +- +- mdelay(1000); +- arm_machine_restart('h'); ++ arm_machine_restart('g'); + } + + static void tosa_restart(char mode) +@@ -504,7 +500,7 @@ static void tosa_restart(char mode) + if((MSC0 & 0xffff0000) == 0x7ff00000) + MSC0 = (MSC0 & 0xffff) | 0x7ee00000; + +- tosa_poweroff(); ++ arm_machine_restart('g'); + } + + static void __init tosa_init(void) +@@ -512,7 +508,6 @@ static void __init tosa_init(void) + pm_power_off = tosa_poweroff; + arm_pm_restart = tosa_restart; + +- pxa_gpio_mode(TOSA_GPIO_ON_RESET | GPIO_IN); + pxa_gpio_mode(TOSA_GPIO_TC6393XB_INT | GPIO_IN); + pxa_gpio_mode(TOSA_GPIO_USB_IN | GPIO_IN); + +@@ -544,6 +539,9 @@ static void __init fixup_tosa(struct machine_desc *desc, + mi->bank[0].start = 0xa0000000; + mi->bank[0].node = 0; + mi->bank[0].size = (64*1024*1024); ++ ++ if (reset_gpio == -1) ++ reset_gpio = TOSA_GPIO_ON_RESET; + } + + MACHINE_START(TOSA, "SHARP Tosa") +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0058-Fix-tosakbd-suspend.patch b/packages/linux/linux-rp-2.6.24/tosa/0058-Fix-tosakbd-suspend.patch new file mode 100644 index 0000000000..e965857dff --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0058-Fix-tosakbd-suspend.patch @@ -0,0 +1,27 @@ +From 8b57c409802e5feef64c4bb7659570e06558c0f2 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Sun, 20 Jan 2008 02:24:43 +0300 +Subject: [PATCH 58/64] Fix tosakbd suspend + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + drivers/input/keyboard/tosakbd.c | 3 +++ + 1 files changed, 3 insertions(+), 0 deletions(-) + +diff --git a/drivers/input/keyboard/tosakbd.c b/drivers/input/keyboard/tosakbd.c +index 3884d1e..306cbe8 100644 +--- a/drivers/input/keyboard/tosakbd.c ++++ b/drivers/input/keyboard/tosakbd.c +@@ -210,6 +210,9 @@ static int tosakbd_suspend(struct platform_device *dev, pm_message_t state) + + del_timer_sync(&tosakbd->timer); + ++ PGSR1 = (PGSR1 & ~TOSA_GPIO_LOW_STROBE_BIT); ++ PGSR2 = (PGSR2 & ~TOSA_GPIO_HIGH_STROBE_BIT); ++ + return 0; + } + +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0059-patch-tosa-wakeup-test.patch b/packages/linux/linux-rp-2.6.24/tosa/0059-patch-tosa-wakeup-test.patch new file mode 100644 index 0000000000..812b5bad41 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0059-patch-tosa-wakeup-test.patch @@ -0,0 +1,46 @@ +From 00f6e9b946d1f653fc776d71c86a1f6a7534cd1d Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Fri, 25 Jan 2008 19:16:20 +0300 +Subject: [PATCH 59/64] patch tosa-wakeup-test + +--- + arch/arm/mach-pxa/tosa.c | 18 +++++++++++++++++- + 1 files changed, 17 insertions(+), 1 deletions(-) + +diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c +index 2b4aef7..7008919 100644 +--- a/arch/arm/mach-pxa/tosa.c ++++ b/arch/arm/mach-pxa/tosa.c +@@ -260,12 +260,28 @@ static struct platform_device tosakbd_device = { + }; + + static struct gpio_keys_button tosa_gpio_keys[] = { ++ /* ++ * Two following keys are directly tied to "ON" button of tosa. Why? ++ * The first one can be used as a wakeup source, the second can't: ++ * it's outside of permitted area. ++ */ ++ { ++ .type = EV_PWR, ++ .code = KEY_RESERVED, ++ .gpio = TOSA_GPIO_POWERON, ++ .desc = "Poweron", ++ .wakeup = 1, ++ .active_low = 1, ++ }, + { + .type = EV_PWR, + .code = KEY_SUSPEND, + .gpio = TOSA_GPIO_ON_KEY, + .desc = "On key", +- .wakeup = 1, ++ /* ++ * can't be used as wakeup ++ * .wakeup = 1, ++ */ + .active_low = 1, + }, + { +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0060-Add-support-for-power_supply-on-tosa.patch b/packages/linux/linux-rp-2.6.24/tosa/0060-Add-support-for-power_supply-on-tosa.patch new file mode 100644 index 0000000000..f7420de040 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0060-Add-support-for-power_supply-on-tosa.patch @@ -0,0 +1,623 @@ +From f6ec15733eb55e851c8ad19c2143d425558f6044 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Mon, 4 Feb 2008 20:11:58 +0300 +Subject: [PATCH 60/64] Add support for power_supply on tosa + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + arch/arm/mach-pxa/Makefile | 2 +- + arch/arm/mach-pxa/tosa_power.c | 82 +++++++ + drivers/leds/leds-tosa.c | 2 +- + drivers/power/Kconfig | 7 + + drivers/power/Makefile | 1 + + drivers/power/tosa_battery.c | 458 ++++++++++++++++++++++++++++++++++++++++ + 6 files changed, 550 insertions(+), 2 deletions(-) + create mode 100644 arch/arm/mach-pxa/tosa_power.c + create mode 100644 drivers/power/tosa_battery.c + +diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile +index f276d24..2b68254 100644 +--- a/arch/arm/mach-pxa/Makefile ++++ b/arch/arm/mach-pxa/Makefile +@@ -21,7 +21,7 @@ obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o cor + obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o + obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o + obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o sharpsl_pm.o poodle_pm.o +-obj-$(CONFIG_MACH_TOSA) += tosa.o ++obj-$(CONFIG_MACH_TOSA) += tosa.o tosa_power.o + obj-$(CONFIG_MACH_EM_X270) += em-x270.o + + ifeq ($(CONFIG_MACH_ZYLONITE),y) +diff --git a/arch/arm/mach-pxa/tosa_power.c b/arch/arm/mach-pxa/tosa_power.c +new file mode 100644 +index 0000000..61ca7dc +--- /dev/null ++++ b/arch/arm/mach-pxa/tosa_power.c +@@ -0,0 +1,82 @@ ++/* ++ * Battery and Power Management code for the Sharp SL-6000x ++ * ++ * Copyright (c) 2005 Dirk Opfer ++ * Copyright (c) 2008 Dmitry Baryshkov ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/power_supply.h> ++#include <linux/pda_power.h> ++#include <linux/platform_device.h> ++#include <linux/interrupt.h> ++ ++#include <asm/arch/tosa.h> ++#include <asm/gpio.h> ++ ++static int tosa_power_ac_online(void) ++{ ++ return gpio_get_value(TOSA_GPIO_AC_IN) == 0; ++} ++ ++static char *tosa_ac_supplied_to[] = { ++ "main-battery", ++ "backup-battery", ++ "jacket-battery", ++}; ++ ++static struct pda_power_pdata tosa_power_data = { ++ .is_ac_online = tosa_power_ac_online, ++ .supplied_to = tosa_ac_supplied_to, ++ .num_supplicants = ARRAY_SIZE(tosa_ac_supplied_to), ++}; ++ ++static struct resource tosa_power_resource[] = { ++ { ++ .name = "ac", ++ .start = gpio_to_irq(TOSA_GPIO_AC_IN), ++ .end = gpio_to_irq(TOSA_GPIO_AC_IN), ++ .flags = IORESOURCE_IRQ | ++ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, ++ }, ++}; ++ ++static struct platform_device tosa_power_device = { ++ .name = "pda-power", ++ .id = -1, ++ .dev.platform_data = &tosa_power_data, ++ .resource = tosa_power_resource, ++ .num_resources = ARRAY_SIZE(tosa_power_resource), ++}; ++ ++static int __init tosa_power_init(void) ++{ ++ int ret = gpio_request(TOSA_GPIO_AC_IN, "ac"); ++ if (ret) ++ goto err_gpio_req; ++ ++ ret = gpio_direction_input(TOSA_GPIO_AC_IN); ++ if (ret) ++ goto err_gpio_in; ++ ++ return platform_device_register(&tosa_power_device); ++ ++err_gpio_in: ++ gpio_free(TOSA_GPIO_AC_IN); ++err_gpio_req: ++ return ret; ++} ++ ++static void __exit tosa_power_exit(void) ++{ ++ platform_device_unregister(&tosa_power_device); ++ gpio_free(TOSA_GPIO_AC_IN); ++} ++ ++module_init(tosa_power_init); ++module_exit(tosa_power_exit); +diff --git a/drivers/leds/leds-tosa.c b/drivers/leds/leds-tosa.c +index fb2416a..b4498b5 100644 +--- a/drivers/leds/leds-tosa.c ++++ b/drivers/leds/leds-tosa.c +@@ -46,7 +46,7 @@ static void tosaled_green_set(struct led_classdev *led_cdev, + + static struct led_classdev tosa_amber_led = { + .name = "tosa:amber", +- .default_trigger = "sharpsl-charge", ++ .default_trigger = "main-battery-charging", + .brightness_set = tosaled_amber_set, + }; + +diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig +index 58c806e..e3a9c37 100644 +--- a/drivers/power/Kconfig ++++ b/drivers/power/Kconfig +@@ -49,4 +49,11 @@ config BATTERY_OLPC + help + Say Y to enable support for the battery on the OLPC laptop. + ++config BATTERY_TOSA ++ tristate "Sharp SL-6000 (tosa) battery" ++ depends on MACH_TOSA && MFD_TC6393XB ++ help ++ Say Y to enable support for the battery on the Sharp Zaurus ++ SL-6000 (tosa) models. ++ + endif # POWER_SUPPLY +diff --git a/drivers/power/Makefile b/drivers/power/Makefile +index 6413ded..1e408fa 100644 +--- a/drivers/power/Makefile ++++ b/drivers/power/Makefile +@@ -20,3 +20,4 @@ obj-$(CONFIG_APM_POWER) += apm_power.o + obj-$(CONFIG_BATTERY_DS2760) += ds2760_battery.o + obj-$(CONFIG_BATTERY_PMU) += pmu_battery.o + obj-$(CONFIG_BATTERY_OLPC) += olpc_battery.o ++obj-$(CONFIG_BATTERY_TOSA) += tosa_battery.o +diff --git a/drivers/power/tosa_battery.c b/drivers/power/tosa_battery.c +new file mode 100644 +index 0000000..b0fd2f2 +--- /dev/null ++++ b/drivers/power/tosa_battery.c +@@ -0,0 +1,458 @@ ++/* ++ * Battery and Power Management code for the Sharp SL-6000x ++ * ++ * Copyright (c) 2005 Dirk Opfer ++ * Copyright (c) 2008 Dmitry Baryshkov ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/power_supply.h> ++#include <linux/wm97xx.h> ++#include <linux/delay.h> ++#include <linux/spinlock.h> ++#include <linux/interrupt.h> ++ ++#include <asm/mach-types.h> ++#include <asm/gpio.h> ++#include <asm/arch/tosa.h> ++ ++#define BAT_TO_VOLTS(v) ((v) * 1000000 / 414) ++#define BU_TO_VOLTS(v) ((v) * 1000000 / 1266) ++/* ++ * It's pretty strange value, but that's roughly what I get from ++ * zaurus maintainer menu ++ */ ++//#define BAT_TO_TEMP(t) ((t) * 10000/2000) ++#define BAT_TO_TEMP(t) (t) ++ ++static DEFINE_MUTEX(bat_lock); /* protects gpio pins */ ++static struct work_struct bat_work; ++ ++struct tosa_bat { ++ int status; ++ struct power_supply psy; ++ int full_chrg; ++ ++ struct mutex work_lock; /* protects data */ ++ bool (*is_present)(struct tosa_bat *bat); ++ int gpio_full; ++ int gpio_charge_off; ++ int gpio_bat; ++ int adc_bat; ++ int gpio_temp; ++ int adc_temp; ++}; ++ ++static struct tosa_bat tosa_bat_main; ++static struct tosa_bat tosa_bat_jacket; ++ ++static enum power_supply_property tosa_bat_main_props[] = { ++ POWER_SUPPLY_PROP_STATUS, ++ POWER_SUPPLY_PROP_TECHNOLOGY, ++ POWER_SUPPLY_PROP_VOLTAGE_NOW, ++ POWER_SUPPLY_PROP_VOLTAGE_MAX, ++ POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, ++ POWER_SUPPLY_PROP_TEMP, ++ POWER_SUPPLY_PROP_PRESENT, ++}; ++ ++static enum power_supply_property tosa_bat_bu_props[] = { ++ POWER_SUPPLY_PROP_STATUS, ++ POWER_SUPPLY_PROP_TECHNOLOGY, ++ POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, ++ POWER_SUPPLY_PROP_VOLTAGE_NOW, ++ POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, ++ POWER_SUPPLY_PROP_PRESENT, ++}; ++ ++static unsigned long tosa_read_bat(struct tosa_bat *bat) ++{ ++ unsigned long value = 0; ++ ++ if (bat->gpio_bat < 0 || bat->adc_bat < 0) ++ return 0; ++ ++ mutex_lock(&bat_lock); ++ gpio_set_value(bat->gpio_bat, 1); ++ mdelay(5); ++ value = wm97xx_read_aux_adc(bat->psy.dev->parent->driver_data, bat->adc_bat); ++ gpio_set_value(bat->gpio_bat, 0); ++ mutex_unlock(&bat_lock); ++ return value; ++} ++ ++static unsigned long tosa_read_temp(struct tosa_bat *bat) ++{ ++ unsigned long value = 0; ++ ++ if (bat->gpio_temp < 0 || bat->adc_temp < 0) ++ return 0; ++ ++ mutex_lock(&bat_lock); ++ gpio_set_value(bat->gpio_temp, 1); ++ mdelay(5); ++ value = wm97xx_read_aux_adc(bat->psy.dev->parent->driver_data, bat->adc_temp); ++ gpio_set_value(bat->gpio_temp, 0); ++ mutex_unlock(&bat_lock); ++ return value; ++} ++ ++static int tosa_bat_get_property(struct power_supply *psy, ++ enum power_supply_property psp, ++ union power_supply_propval *val) ++{ ++ int ret = 0; ++ struct tosa_bat *bat = container_of(psy, struct tosa_bat, psy); ++ ++ if (bat->is_present && !bat->is_present(bat) ++ && psp != POWER_SUPPLY_PROP_PRESENT) { ++ return -ENODEV; ++ } ++ ++ switch (psp) { ++ case POWER_SUPPLY_PROP_STATUS: ++ val->intval = bat->status; ++ break; ++ case POWER_SUPPLY_PROP_TECHNOLOGY: ++ val->intval = POWER_SUPPLY_TECHNOLOGY_LIPO; ++ break; ++ case POWER_SUPPLY_PROP_VOLTAGE_NOW: ++ val->intval = BAT_TO_VOLTS(tosa_read_bat(bat)); ++ break; ++ case POWER_SUPPLY_PROP_VOLTAGE_MAX: ++ if (bat->full_chrg == -1) ++ val->intval = -1; ++ else ++ val->intval = BAT_TO_VOLTS(bat->full_chrg); ++ break; ++ case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN: ++ val->intval = BAT_TO_VOLTS(1551); ++ break; ++ case POWER_SUPPLY_PROP_TEMP: ++ val->intval = BAT_TO_TEMP(tosa_read_temp(bat)); ++ break; ++ case POWER_SUPPLY_PROP_PRESENT: ++ val->intval = bat->is_present ? bat->is_present(bat) : 1; ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ return ret; ++} ++ ++static int tosa_bu_get_property(struct power_supply *psy, ++ enum power_supply_property psp, ++ union power_supply_propval *val) ++{ ++ int ret = 0; ++ struct tosa_bat *bat = container_of(psy, struct tosa_bat, psy); ++ ++ switch (psp) { ++ case POWER_SUPPLY_PROP_STATUS: ++ val->intval = POWER_SUPPLY_STATUS_UNKNOWN; ++ break; ++ case POWER_SUPPLY_PROP_TECHNOLOGY: ++ val->intval = POWER_SUPPLY_TECHNOLOGY_LiMn; ++ break; ++ case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN: ++ val->intval = 0; ++ break; ++ case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN: ++ val->intval = 3 * 1000000; /* 3 V */ ++ break; ++ case POWER_SUPPLY_PROP_VOLTAGE_NOW: ++ /* I think so */ ++ val->intval = BU_TO_VOLTS(tosa_read_bat(bat)); ++ break; ++ case POWER_SUPPLY_PROP_PRESENT: ++ val->intval = 1; ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ return ret; ++} ++ ++static bool tosa_jacket_bat_is_present(struct tosa_bat *bat) { ++ // FIXME ++ return 1; ++} ++ ++static void tosa_bat_external_power_changed(struct power_supply *psy) ++{ ++ schedule_work(&bat_work); ++} ++ ++static irqreturn_t tosa_bat_full_isr(int irq, void *data) ++{ ++ printk(KERN_ERR "bat_full irq: %d\n", gpio_get_value(irq_to_gpio(irq))); ++ schedule_work(&bat_work); ++ return IRQ_HANDLED; ++} ++ ++static void tosa_bat_update(struct tosa_bat *bat) ++{ ++ int old = bat->status; ++ struct power_supply *psy = &bat->psy; ++ ++ mutex_lock(&bat->work_lock); ++ ++ if (bat->is_present && !bat->is_present(bat)) { ++ printk(KERN_DEBUG "%s not present\n", psy->name); ++ bat->status = POWER_SUPPLY_STATUS_NOT_CHARGING; ++ bat->full_chrg = -1; ++ } else if (power_supply_am_i_supplied(psy)) { ++ if (gpio_get_value(bat->gpio_full)) { ++ printk(KERN_DEBUG "%s full\n", psy->name); ++ ++ if (old == POWER_SUPPLY_STATUS_CHARGING || bat->full_chrg == -1) ++ bat->full_chrg = tosa_read_bat(bat); ++ ++ gpio_set_value(bat->gpio_charge_off, 1); ++ bat->status = POWER_SUPPLY_STATUS_FULL; ++ } else { ++ printk(KERN_ERR "%s charge\n", psy->name); ++ gpio_set_value(bat->gpio_charge_off, 0); ++ bat->status = POWER_SUPPLY_STATUS_CHARGING; ++ } ++ } else { ++ printk(KERN_ERR "%s discharge\n", psy->name); ++ gpio_set_value(bat->gpio_charge_off, 1); ++ bat->status = POWER_SUPPLY_STATUS_DISCHARGING; ++ } ++ ++ if (old != bat->status) ++ power_supply_changed(psy); ++ ++ mutex_unlock(&bat->work_lock); ++} ++ ++static void tosa_bat_work(struct work_struct *work) ++{ ++ tosa_bat_update(&tosa_bat_main); ++ tosa_bat_update(&tosa_bat_jacket); ++} ++ ++ ++static struct tosa_bat tosa_bat_main = { ++ .status = POWER_SUPPLY_STATUS_UNKNOWN, ++ .full_chrg = -1, ++ .psy = { ++ .name = "main-battery", ++ .type = POWER_SUPPLY_TYPE_BATTERY, ++ .properties = tosa_bat_main_props, ++ .num_properties = ARRAY_SIZE(tosa_bat_main_props), ++ .get_property = tosa_bat_get_property, ++ .external_power_changed = tosa_bat_external_power_changed, ++ .use_for_apm = 1, ++ }, ++ ++ .gpio_full = TOSA_GPIO_BAT0_CRG, ++ .gpio_charge_off = TOSA_TC6393XB_CHARGE_OFF, ++ .gpio_bat = TOSA_TC6393XB_BAT0_V_ON, ++ .adc_bat = WM97XX_AUX_ID3, ++ .gpio_temp = TOSA_TC6393XB_BAT1_TH_ON, ++ .adc_temp = WM97XX_AUX_ID2, ++}; ++ ++static struct tosa_bat tosa_bat_jacket = { ++ .status = POWER_SUPPLY_STATUS_UNKNOWN, ++ .full_chrg = -1, ++ .psy = { ++ .name = "jacket-battery", ++ .type = POWER_SUPPLY_TYPE_BATTERY, ++ .properties = tosa_bat_main_props, ++ .num_properties = ARRAY_SIZE(tosa_bat_main_props), ++ .get_property = tosa_bat_get_property, ++ .external_power_changed = tosa_bat_external_power_changed, ++// .use_for_apm = 1, ++ }, ++ ++ .is_present = tosa_jacket_bat_is_present, ++ .gpio_full = TOSA_GPIO_BAT1_CRG, ++ .gpio_charge_off = TOSA_TC6393XB_CHARGE_OFF_JC, ++ .gpio_bat = TOSA_TC6393XB_BAT1_V_ON, ++ .adc_bat = WM97XX_AUX_ID3, ++ .gpio_temp = TOSA_TC6393XB_BAT0_TH_ON, ++ .adc_temp = WM97XX_AUX_ID2, ++}; ++ ++static struct tosa_bat tosa_bat_bu = { ++ .status = POWER_SUPPLY_STATUS_UNKNOWN, ++ .full_chrg = -1, ++ ++ .psy = { ++ .name = "backup-battery", ++ .type = POWER_SUPPLY_TYPE_BATTERY, ++ .properties = tosa_bat_bu_props, ++ .num_properties = ARRAY_SIZE(tosa_bat_bu_props), ++ .get_property = tosa_bu_get_property, ++ .external_power_changed = tosa_bat_external_power_changed, ++ }, ++ ++ .gpio_full = -1, ++ .gpio_charge_off = -1, ++ .gpio_bat = TOSA_TC6393XB_BU_CHRG_ON, ++ .adc_bat = WM97XX_AUX_ID4, ++ .gpio_temp = -1, ++ .adc_temp = -1, ++}; ++ ++static struct { ++ int gpio; ++ char *name; ++ bool output; ++ int value; ++} gpios[] = { ++ { TOSA_TC6393XB_CHARGE_OFF, "main charge off", 1, 1 }, ++ { TOSA_TC6393XB_CHARGE_OFF_JC, "jacket charge off", 1, 1 }, ++ { TOSA_TC6393XB_BAT_SW_ON, "battery switch", 1, 0 }, ++ { TOSA_TC6393XB_BAT0_V_ON, "main battery", 1, 0 }, ++ { TOSA_TC6393XB_BAT1_V_ON, "jacket battery", 1, 0 }, ++ { TOSA_TC6393XB_BAT1_TH_ON, "main battery temp", 1, 0 }, ++ { TOSA_TC6393XB_BAT0_TH_ON, "jacket battery temp", 1, 0 }, ++ { TOSA_TC6393XB_BU_CHRG_ON, "backup battery", 1, 0 }, ++ { TOSA_GPIO_BAT0_CRG, "main battery full", 0, 0 }, ++ { TOSA_GPIO_BAT1_CRG, "jacket battery full", 0, 0 }, ++ { TOSA_GPIO_BAT0_LOW, "main battery low", 0, 0 }, ++ { TOSA_GPIO_BAT1_LOW, "jacket battery low", 0, 0 }, ++}; ++ ++#ifdef CONFIG_PM ++static int tosa_bat_suspend(struct device *dev, pm_message_t state) ++{ ++ /* do nothing */ ++ return 0; ++} ++ ++static int tosa_bat_resume(struct device *dev) ++{ ++ schedule_work(&bat_work); ++ return 0; ++} ++#else ++#define tosa_bat_suspend NULL ++#define tosa_bat_resume NULL ++#endif ++ ++static int __devinit tosa_bat_probe(struct device *dev) ++{ ++ int ret; ++ int i; ++ ++ if (!machine_is_tosa()) ++ return -ENODEV; ++ ++ for (i = 0; i < ARRAY_SIZE(gpios); i++) { ++ ret = gpio_request(gpios[i].gpio, gpios[i].name); ++ if (ret) { ++ i --; ++ goto err_gpio; ++ } ++ ++ if (gpios[i].output) ++ ret = gpio_direction_output(gpios[i].gpio, ++ gpios[i].value); ++ else ++ ret = gpio_direction_input(gpios[i].gpio); ++ ++ if (ret) ++ goto err_gpio; ++ } ++ ++ mutex_init(&tosa_bat_main.work_lock); ++ mutex_init(&tosa_bat_jacket.work_lock); ++ ++ INIT_WORK(&bat_work, tosa_bat_work); ++ ++ ret = power_supply_register(dev, &tosa_bat_main.psy); ++ if (ret) ++ goto err_psy_reg_main; ++ ret = power_supply_register(dev, &tosa_bat_jacket.psy); ++ if (ret) ++ goto err_psy_reg_jacket; ++ ret = power_supply_register(dev, &tosa_bat_bu.psy); ++ if (ret) ++ goto err_psy_reg_bu; ++ ++ ret = request_irq(gpio_to_irq(TOSA_GPIO_BAT0_CRG), ++ tosa_bat_full_isr, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, ++ "main full", &tosa_bat_main); ++ if (ret) ++ goto err_req_main; ++ ++ ret = request_irq(gpio_to_irq(TOSA_GPIO_BAT1_CRG), ++ tosa_bat_full_isr, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, ++ "jacket full", &tosa_bat_jacket); ++ if (!ret) { ++ schedule_work(&bat_work); ++ return 0; ++ } ++ ++ free_irq(gpio_to_irq(TOSA_GPIO_BAT0_CRG), &tosa_bat_main); ++err_req_main: ++ power_supply_unregister(&tosa_bat_bu.psy); ++err_psy_reg_bu: ++ power_supply_unregister(&tosa_bat_jacket.psy); ++err_psy_reg_jacket: ++ power_supply_unregister(&tosa_bat_main.psy); ++err_psy_reg_main: ++ ++ i --; ++err_gpio: ++ for (; i >= 0; i --) ++ gpio_free(gpios[i].gpio); ++ ++ return ret; ++} ++ ++static int __devexit tosa_bat_remove(struct device *dev) ++{ ++ int i; ++ ++ free_irq(gpio_to_irq(TOSA_GPIO_BAT1_CRG), &tosa_bat_jacket); ++ free_irq(gpio_to_irq(TOSA_GPIO_BAT0_CRG), &tosa_bat_main); ++ ++ power_supply_unregister(&tosa_bat_bu.psy); ++ power_supply_unregister(&tosa_bat_jacket.psy); ++ power_supply_unregister(&tosa_bat_main.psy); ++ ++ for (i = ARRAY_SIZE(gpios) - 1; i >= 0; i --) ++ gpio_free(gpios[i].gpio); ++ ++ return 0; ++} ++ ++static struct device_driver tosa_bat_driver = { ++ .name = "wm97xx-battery", ++ .bus = &wm97xx_bus_type, ++ .owner = THIS_MODULE, ++ .probe = tosa_bat_probe, ++ .remove = __devexit_p(tosa_bat_remove), ++ .suspend = tosa_bat_suspend, ++ .resume = tosa_bat_resume, ++}; ++ ++static int __init tosa_bat_init(void) ++{ ++ return driver_register(&tosa_bat_driver); ++} ++ ++static void __exit tosa_bat_exit(void) ++{ ++ driver_unregister(&tosa_bat_driver); ++} ++ ++module_init(tosa_bat_init); ++module_exit(tosa_bat_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Dmitry Baryshkov"); ++MODULE_DESCRIPTION("Tosa battery driver"); +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0061-tosa-bat-unify.patch b/packages/linux/linux-rp-2.6.24/tosa/0061-tosa-bat-unify.patch new file mode 100644 index 0000000000..2bcede36a9 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0061-tosa-bat-unify.patch @@ -0,0 +1,342 @@ +From f05aa38af5bd5962ae04c4b128644e7f55451527 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Fri, 8 Feb 2008 01:14:48 +0300 +Subject: [PATCH 61/64] tosa-bat-unify + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + drivers/power/tosa_battery.c | 161 ++++++++++++++++++++--------------------- + 1 files changed, 79 insertions(+), 82 deletions(-) + +diff --git a/drivers/power/tosa_battery.c b/drivers/power/tosa_battery.c +index b0fd2f2..008e791 100644 +--- a/drivers/power/tosa_battery.c ++++ b/drivers/power/tosa_battery.c +@@ -21,15 +21,6 @@ + #include <asm/gpio.h> + #include <asm/arch/tosa.h> + +-#define BAT_TO_VOLTS(v) ((v) * 1000000 / 414) +-#define BU_TO_VOLTS(v) ((v) * 1000000 / 1266) +-/* +- * It's pretty strange value, but that's roughly what I get from +- * zaurus maintainer menu +- */ +-//#define BAT_TO_TEMP(t) ((t) * 10000/2000) +-#define BAT_TO_TEMP(t) (t) +- + static DEFINE_MUTEX(bat_lock); /* protects gpio pins */ + static struct work_struct bat_work; + +@@ -39,37 +30,27 @@ struct tosa_bat { + int full_chrg; + + struct mutex work_lock; /* protects data */ ++ + bool (*is_present)(struct tosa_bat *bat); + int gpio_full; + int gpio_charge_off; ++ ++ int technology; ++ + int gpio_bat; + int adc_bat; ++ int adc_bat_divider; ++ int bat_max; ++ int bat_min; ++ + int gpio_temp; + int adc_temp; ++ int adc_temp_divider; + }; + + static struct tosa_bat tosa_bat_main; + static struct tosa_bat tosa_bat_jacket; + +-static enum power_supply_property tosa_bat_main_props[] = { +- POWER_SUPPLY_PROP_STATUS, +- POWER_SUPPLY_PROP_TECHNOLOGY, +- POWER_SUPPLY_PROP_VOLTAGE_NOW, +- POWER_SUPPLY_PROP_VOLTAGE_MAX, +- POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, +- POWER_SUPPLY_PROP_TEMP, +- POWER_SUPPLY_PROP_PRESENT, +-}; +- +-static enum power_supply_property tosa_bat_bu_props[] = { +- POWER_SUPPLY_PROP_STATUS, +- POWER_SUPPLY_PROP_TECHNOLOGY, +- POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, +- POWER_SUPPLY_PROP_VOLTAGE_NOW, +- POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, +- POWER_SUPPLY_PROP_PRESENT, +-}; +- + static unsigned long tosa_read_bat(struct tosa_bat *bat) + { + unsigned long value = 0; +@@ -83,6 +64,9 @@ static unsigned long tosa_read_bat(struct tosa_bat *bat) + value = wm97xx_read_aux_adc(bat->psy.dev->parent->driver_data, bat->adc_bat); + gpio_set_value(bat->gpio_bat, 0); + mutex_unlock(&bat_lock); ++ ++ value = value * 1000000 / bat->adc_bat_divider; ++ + return value; + } + +@@ -99,6 +83,9 @@ static unsigned long tosa_read_temp(struct tosa_bat *bat) + value = wm97xx_read_aux_adc(bat->psy.dev->parent->driver_data, bat->adc_temp); + gpio_set_value(bat->gpio_temp, 0); + mutex_unlock(&bat_lock); ++ ++ value = value * 10000 / bat->adc_temp_divider; ++ + return value; + } + +@@ -119,22 +106,25 @@ static int tosa_bat_get_property(struct power_supply *psy, + val->intval = bat->status; + break; + case POWER_SUPPLY_PROP_TECHNOLOGY: +- val->intval = POWER_SUPPLY_TECHNOLOGY_LIPO; ++ val->intval = bat->technology; + break; + case POWER_SUPPLY_PROP_VOLTAGE_NOW: +- val->intval = BAT_TO_VOLTS(tosa_read_bat(bat)); ++ val->intval = tosa_read_bat(bat); + break; + case POWER_SUPPLY_PROP_VOLTAGE_MAX: + if (bat->full_chrg == -1) +- val->intval = -1; ++ val->intval = bat->bat_max; + else +- val->intval = BAT_TO_VOLTS(bat->full_chrg); ++ val->intval = bat->full_chrg; ++ break; ++ case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN: ++ val->intval = bat->bat_max; + break; + case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN: +- val->intval = BAT_TO_VOLTS(1551); ++ val->intval = bat->bat_min; + break; + case POWER_SUPPLY_PROP_TEMP: +- val->intval = BAT_TO_TEMP(tosa_read_temp(bat)); ++ val->intval = tosa_read_temp(bat); + break; + case POWER_SUPPLY_PROP_PRESENT: + val->intval = bat->is_present ? bat->is_present(bat) : 1; +@@ -146,40 +136,6 @@ static int tosa_bat_get_property(struct power_supply *psy, + return ret; + } + +-static int tosa_bu_get_property(struct power_supply *psy, +- enum power_supply_property psp, +- union power_supply_propval *val) +-{ +- int ret = 0; +- struct tosa_bat *bat = container_of(psy, struct tosa_bat, psy); +- +- switch (psp) { +- case POWER_SUPPLY_PROP_STATUS: +- val->intval = POWER_SUPPLY_STATUS_UNKNOWN; +- break; +- case POWER_SUPPLY_PROP_TECHNOLOGY: +- val->intval = POWER_SUPPLY_TECHNOLOGY_LiMn; +- break; +- case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN: +- val->intval = 0; +- break; +- case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN: +- val->intval = 3 * 1000000; /* 3 V */ +- break; +- case POWER_SUPPLY_PROP_VOLTAGE_NOW: +- /* I think so */ +- val->intval = BU_TO_VOLTS(tosa_read_bat(bat)); +- break; +- case POWER_SUPPLY_PROP_PRESENT: +- val->intval = 1; +- break; +- default: +- ret = -EINVAL; +- break; +- } +- return ret; +-} +- + static bool tosa_jacket_bat_is_present(struct tosa_bat *bat) { + // FIXME + return 1; +@@ -241,6 +197,25 @@ static void tosa_bat_work(struct work_struct *work) + } + + ++static enum power_supply_property tosa_bat_main_props[] = { ++ POWER_SUPPLY_PROP_STATUS, ++ POWER_SUPPLY_PROP_TECHNOLOGY, ++ POWER_SUPPLY_PROP_VOLTAGE_NOW, ++ POWER_SUPPLY_PROP_VOLTAGE_MAX, ++ POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, ++ POWER_SUPPLY_PROP_TEMP, ++ POWER_SUPPLY_PROP_PRESENT, ++}; ++ ++static enum power_supply_property tosa_bat_bu_props[] = { ++ POWER_SUPPLY_PROP_STATUS, ++ POWER_SUPPLY_PROP_TECHNOLOGY, ++ POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, ++ POWER_SUPPLY_PROP_VOLTAGE_NOW, ++ POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, ++ POWER_SUPPLY_PROP_PRESENT, ++}; ++ + static struct tosa_bat tosa_bat_main = { + .status = POWER_SUPPLY_STATUS_UNKNOWN, + .full_chrg = -1, +@@ -256,10 +231,18 @@ static struct tosa_bat tosa_bat_main = { + + .gpio_full = TOSA_GPIO_BAT0_CRG, + .gpio_charge_off = TOSA_TC6393XB_CHARGE_OFF, ++ ++ .technology = POWER_SUPPLY_TECHNOLOGY_LIPO, ++ + .gpio_bat = TOSA_TC6393XB_BAT0_V_ON, + .adc_bat = WM97XX_AUX_ID3, ++ .adc_bat_divider = 414, ++ .bat_max = 4310000, ++ .bat_min = 1551 * 100000 / 414, ++ + .gpio_temp = TOSA_TC6393XB_BAT1_TH_ON, + .adc_temp = WM97XX_AUX_ID2, ++ .adc_temp_divider = 10000, + }; + + static struct tosa_bat tosa_bat_jacket = { +@@ -278,10 +261,18 @@ static struct tosa_bat tosa_bat_jacket = { + .is_present = tosa_jacket_bat_is_present, + .gpio_full = TOSA_GPIO_BAT1_CRG, + .gpio_charge_off = TOSA_TC6393XB_CHARGE_OFF_JC, ++ ++ .technology = POWER_SUPPLY_TECHNOLOGY_LIPO, ++ + .gpio_bat = TOSA_TC6393XB_BAT1_V_ON, + .adc_bat = WM97XX_AUX_ID3, ++ .adc_bat_divider = 414, ++ .bat_max = 4310000, ++ .bat_min = 1551 * 100000 / 414, ++ + .gpio_temp = TOSA_TC6393XB_BAT0_TH_ON, + .adc_temp = WM97XX_AUX_ID2, ++ .adc_temp_divider = 10000, + }; + + static struct tosa_bat tosa_bat_bu = { +@@ -293,16 +284,22 @@ static struct tosa_bat tosa_bat_bu = { + .type = POWER_SUPPLY_TYPE_BATTERY, + .properties = tosa_bat_bu_props, + .num_properties = ARRAY_SIZE(tosa_bat_bu_props), +- .get_property = tosa_bu_get_property, ++ .get_property = tosa_bat_get_property, + .external_power_changed = tosa_bat_external_power_changed, + }, + + .gpio_full = -1, + .gpio_charge_off = -1, ++ ++ .technology = POWER_SUPPLY_TECHNOLOGY_LiMn, ++ + .gpio_bat = TOSA_TC6393XB_BU_CHRG_ON, + .adc_bat = WM97XX_AUX_ID4, ++ .adc_bat_divider = 1266, ++ + .gpio_temp = -1, + .adc_temp = -1, ++ .adc_temp_divider = -1, + }; + + static struct { +@@ -326,13 +323,14 @@ static struct { + }; + + #ifdef CONFIG_PM +-static int tosa_bat_suspend(struct device *dev, pm_message_t state) ++static int tosa_bat_suspend(struct platform_device *dev, pm_message_t state) + { + /* do nothing */ ++ flush_scheduled_work(); + return 0; + } + +-static int tosa_bat_resume(struct device *dev) ++static int tosa_bat_resume(struct platform_device *dev) + { + schedule_work(&bat_work); + return 0; +@@ -342,7 +340,7 @@ static int tosa_bat_resume(struct device *dev) + #define tosa_bat_resume NULL + #endif + +-static int __devinit tosa_bat_probe(struct device *dev) ++static int __devinit tosa_bat_probe(struct platform_device *dev) + { + int ret; + int i; +@@ -372,13 +370,13 @@ static int __devinit tosa_bat_probe(struct device *dev) + + INIT_WORK(&bat_work, tosa_bat_work); + +- ret = power_supply_register(dev, &tosa_bat_main.psy); ++ ret = power_supply_register(&dev->dev, &tosa_bat_main.psy); + if (ret) + goto err_psy_reg_main; +- ret = power_supply_register(dev, &tosa_bat_jacket.psy); ++ ret = power_supply_register(&dev->dev, &tosa_bat_jacket.psy); + if (ret) + goto err_psy_reg_jacket; +- ret = power_supply_register(dev, &tosa_bat_bu.psy); ++ ret = power_supply_register(&dev->dev, &tosa_bat_bu.psy); + if (ret) + goto err_psy_reg_bu; + +@@ -413,7 +411,7 @@ err_gpio: + return ret; + } + +-static int __devexit tosa_bat_remove(struct device *dev) ++static int __devexit tosa_bat_remove(struct platform_device *dev) + { + int i; + +@@ -430,10 +428,9 @@ static int __devexit tosa_bat_remove(struct device *dev) + return 0; + } + +-static struct device_driver tosa_bat_driver = { +- .name = "wm97xx-battery", +- .bus = &wm97xx_bus_type, +- .owner = THIS_MODULE, ++static struct platform_driver tosa_bat_driver = { ++ .driver.name = "wm97xx-battery", ++ .driver.owner = THIS_MODULE, + .probe = tosa_bat_probe, + .remove = __devexit_p(tosa_bat_remove), + .suspend = tosa_bat_suspend, +@@ -442,12 +439,12 @@ static struct device_driver tosa_bat_driver = { + + static int __init tosa_bat_init(void) + { +- return driver_register(&tosa_bat_driver); ++ return platform_driver_register(&tosa_bat_driver); + } + + static void __exit tosa_bat_exit(void) + { +- driver_unregister(&tosa_bat_driver); ++ platform_driver_unregister(&tosa_bat_driver); + } + + module_init(tosa_bat_init); +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0062-tosa-bat-fix-charging.patch b/packages/linux/linux-rp-2.6.24/tosa/0062-tosa-bat-fix-charging.patch new file mode 100644 index 0000000000..e3a6b74772 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0062-tosa-bat-fix-charging.patch @@ -0,0 +1,78 @@ +From 0b9f80ab540b2e51f6e86f6a1adec67761f9368d Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Fri, 8 Feb 2008 00:50:03 +0300 +Subject: [PATCH 62/64] tosa-bat-fix-charging + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + drivers/power/tosa_battery.c | 28 +++++++++++++++++++++------- + 1 files changed, 21 insertions(+), 7 deletions(-) + +diff --git a/drivers/power/tosa_battery.c b/drivers/power/tosa_battery.c +index 008e791..2db9116 100644 +--- a/drivers/power/tosa_battery.c ++++ b/drivers/power/tosa_battery.c +@@ -153,39 +153,53 @@ static irqreturn_t tosa_bat_full_isr(int irq, void *data) + return IRQ_HANDLED; + } + ++static char *status_text[] = { ++ [POWER_SUPPLY_STATUS_UNKNOWN] = "Unknown", ++ [POWER_SUPPLY_STATUS_CHARGING] = "Charging", ++ [POWER_SUPPLY_STATUS_DISCHARGING] = "Discharging", ++ [POWER_SUPPLY_STATUS_NOT_CHARGING] = "Not charging", ++ [POWER_SUPPLY_STATUS_FULL] = "Full", ++}; ++ + static void tosa_bat_update(struct tosa_bat *bat) + { +- int old = bat->status; ++ int old; + struct power_supply *psy = &bat->psy; + + mutex_lock(&bat->work_lock); + ++ old = bat->status; ++ + if (bat->is_present && !bat->is_present(bat)) { +- printk(KERN_DEBUG "%s not present\n", psy->name); ++ printk(KERN_NOTICE "%s not present\n", psy->name); + bat->status = POWER_SUPPLY_STATUS_NOT_CHARGING; + bat->full_chrg = -1; + } else if (power_supply_am_i_supplied(psy)) { ++ if (bat->status == POWER_SUPPLY_STATUS_DISCHARGING) { ++ gpio_set_value(bat->gpio_charge_off, 0); ++ mdelay(15); ++ } + if (gpio_get_value(bat->gpio_full)) { +- printk(KERN_DEBUG "%s full\n", psy->name); +- + if (old == POWER_SUPPLY_STATUS_CHARGING || bat->full_chrg == -1) + bat->full_chrg = tosa_read_bat(bat); + + gpio_set_value(bat->gpio_charge_off, 1); + bat->status = POWER_SUPPLY_STATUS_FULL; + } else { +- printk(KERN_ERR "%s charge\n", psy->name); + gpio_set_value(bat->gpio_charge_off, 0); + bat->status = POWER_SUPPLY_STATUS_CHARGING; + } + } else { +- printk(KERN_ERR "%s discharge\n", psy->name); + gpio_set_value(bat->gpio_charge_off, 1); + bat->status = POWER_SUPPLY_STATUS_DISCHARGING; + } + +- if (old != bat->status) ++ if (old != bat->status) { ++ printk(KERN_NOTICE "%s %s -> %s\n", psy->name, ++ status_text[old], ++ status_text[bat->status]); + power_supply_changed(psy); ++ } + + mutex_unlock(&bat->work_lock); + } +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0063-patch-tosa-bat-jacket-detect.patch b/packages/linux/linux-rp-2.6.24/tosa/0063-patch-tosa-bat-jacket-detect.patch new file mode 100644 index 0000000000..416cae44ec --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0063-patch-tosa-bat-jacket-detect.patch @@ -0,0 +1,84 @@ +From 4ef7289137132959e3db5a1e77580ff9db185d90 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Fri, 8 Feb 2008 01:13:54 +0300 +Subject: [PATCH 63/64] patch tosa-bat-jacket-detect + +--- + drivers/power/tosa_battery.c | 21 +++++++++++++++------ + 1 files changed, 15 insertions(+), 6 deletions(-) + +diff --git a/drivers/power/tosa_battery.c b/drivers/power/tosa_battery.c +index 2db9116..70beed2 100644 +--- a/drivers/power/tosa_battery.c ++++ b/drivers/power/tosa_battery.c +@@ -137,8 +137,7 @@ static int tosa_bat_get_property(struct power_supply *psy, + } + + static bool tosa_jacket_bat_is_present(struct tosa_bat *bat) { +- // FIXME +- return 1; ++ return gpio_get_value(TOSA_GPIO_JACKET_DETECT) == 0; + } + + static void tosa_bat_external_power_changed(struct power_supply *psy) +@@ -146,9 +145,9 @@ static void tosa_bat_external_power_changed(struct power_supply *psy) + schedule_work(&bat_work); + } + +-static irqreturn_t tosa_bat_full_isr(int irq, void *data) ++static irqreturn_t tosa_bat_gpio_isr(int irq, void *data) + { +- printk(KERN_ERR "bat_full irq: %d\n", gpio_get_value(irq_to_gpio(irq))); ++ printk(KERN_ERR "bat_gpio irq: %d\n", gpio_get_value(irq_to_gpio(irq))); + schedule_work(&bat_work); + return IRQ_HANDLED; + } +@@ -334,6 +333,7 @@ static struct { + { TOSA_GPIO_BAT1_CRG, "jacket battery full", 0, 0 }, + { TOSA_GPIO_BAT0_LOW, "main battery low", 0, 0 }, + { TOSA_GPIO_BAT1_LOW, "jacket battery low", 0, 0 }, ++ { TOSA_GPIO_JACKET_DETECT, "jacket detect", 0, 0 }, + }; + + #ifdef CONFIG_PM +@@ -395,19 +395,27 @@ static int __devinit tosa_bat_probe(struct platform_device *dev) + goto err_psy_reg_bu; + + ret = request_irq(gpio_to_irq(TOSA_GPIO_BAT0_CRG), +- tosa_bat_full_isr, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, ++ tosa_bat_gpio_isr, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "main full", &tosa_bat_main); + if (ret) + goto err_req_main; + + ret = request_irq(gpio_to_irq(TOSA_GPIO_BAT1_CRG), +- tosa_bat_full_isr, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, ++ tosa_bat_gpio_isr, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "jacket full", &tosa_bat_jacket); ++ if (ret) ++ goto err_req_jacket; ++ ++ ret = request_irq(gpio_to_irq(TOSA_GPIO_JACKET_DETECT), ++ tosa_bat_gpio_isr, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, ++ "jacket detect", &tosa_bat_jacket); + if (!ret) { + schedule_work(&bat_work); + return 0; + } + ++ free_irq(gpio_to_irq(TOSA_GPIO_BAT1_CRG), &tosa_bat_jacket); ++err_req_jacket: + free_irq(gpio_to_irq(TOSA_GPIO_BAT0_CRG), &tosa_bat_main); + err_req_main: + power_supply_unregister(&tosa_bat_bu.psy); +@@ -429,6 +437,7 @@ static int __devexit tosa_bat_remove(struct platform_device *dev) + { + int i; + ++ free_irq(gpio_to_irq(TOSA_GPIO_JACKET_DETECT), &tosa_bat_jacket); + free_irq(gpio_to_irq(TOSA_GPIO_BAT1_CRG), &tosa_bat_jacket); + free_irq(gpio_to_irq(TOSA_GPIO_BAT0_CRG), &tosa_bat_main); + +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0064-Export-modes-via-sysfs.patch b/packages/linux/linux-rp-2.6.24/tosa/0064-Export-modes-via-sysfs.patch new file mode 100644 index 0000000000..eeb92cfdd5 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0064-Export-modes-via-sysfs.patch @@ -0,0 +1,27 @@ +From feeee5d22c00d9d1e2e06eb5610740be238749b9 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Thu, 7 Feb 2008 22:27:38 +0300 +Subject: [PATCH 64/64] Export modes via sysfs + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + drivers/video/tmiofb.c | 3 +++ + 1 files changed, 3 insertions(+), 0 deletions(-) + +diff --git a/drivers/video/tmiofb.c b/drivers/video/tmiofb.c +index 6b963a1..9389a77 100644 +--- a/drivers/video/tmiofb.c ++++ b/drivers/video/tmiofb.c +@@ -800,6 +800,9 @@ static int tmiofb_probe(struct platform_device *dev) + if (retval) + goto err_set_par;*/ + ++ fb_videomode_to_modelist(data->modes, data->num_modes, ++ &info->modelist); ++ + retval = register_framebuffer(info); + if (retval < 0) + goto err_register_framebuffer; +-- +1.5.3.8 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0065-wm97xx-core-fixes.patch b/packages/linux/linux-rp-2.6.24/tosa/0065-wm97xx-core-fixes.patch new file mode 100644 index 0000000000..5db0cc6ba0 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0065-wm97xx-core-fixes.patch @@ -0,0 +1,49 @@ +From 2544412fc47dc13f4f3935cb4c2fd500d217e905 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Wed, 13 Feb 2008 02:00:15 +0300 +Subject: [PATCH] wm97xx-core fixes + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + drivers/input/touchscreen/wm97xx-core.c | 8 ++++---- + include/linux/wm97xx.h | 1 - + 2 files changed, 4 insertions(+), 5 deletions(-) + +diff --git a/drivers/input/touchscreen/wm97xx-core.c b/drivers/input/touchscreen/wm97xx-core.c +index 840d9ff..4cbb9e5 100644 +--- a/drivers/input/touchscreen/wm97xx-core.c ++++ b/drivers/input/touchscreen/wm97xx-core.c +@@ -596,7 +596,7 @@ static int wm97xx_probe(struct device *dev) + } + platform_set_drvdata(wm->battery_dev, wm); + wm->battery_dev->dev.parent = dev; +- ret = platform_device_register(wm->battery_dev); ++ ret = platform_device_add(wm->battery_dev); + if (ret < 0) + goto batt_reg_err; + +@@ -609,7 +609,7 @@ static int wm97xx_probe(struct device *dev) + } + platform_set_drvdata(wm->touch_dev, wm); + wm->touch_dev->dev.parent = dev; +- ret = platform_device_register(wm->touch_dev); ++ ret = platform_device_add(wm->touch_dev); + if (ret < 0) + goto touch_reg_err; + +@@ -619,10 +619,12 @@ static int wm97xx_probe(struct device *dev) + platform_device_put(wm->touch_dev); + touch_err: + platform_device_unregister(wm->battery_dev); ++ wm->battery_dev = NULL; + batt_reg_err: + platform_device_put(wm->battery_dev); + batt_err: + input_unregister_device(wm->input_dev); ++ wm->input_dev = NULL; + kfree(wm); + return ret; + } +-- +1.5.4.1 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0066-tmiofb_probe-should-be-__devinit.patch b/packages/linux/linux-rp-2.6.24/tosa/0066-tmiofb_probe-should-be-__devinit.patch new file mode 100644 index 0000000000..42320be50b --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0066-tmiofb_probe-should-be-__devinit.patch @@ -0,0 +1,26 @@ +From b6a63ad546cc26519a342f3fdd7b1def49ca33ee Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Wed, 13 Feb 2008 02:00:14 +0300 +Subject: [PATCH] tmiofb_probe should be __devinit + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + drivers/video/tmiofb.c | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +diff --git a/drivers/video/tmiofb.c b/drivers/video/tmiofb.c +index 9389a77..958ee8a 100644 +--- a/drivers/video/tmiofb.c ++++ b/drivers/video/tmiofb.c +@@ -704,7 +704,7 @@ static irqreturn_t tmiofb_irq(int irq, void *__info) + return IRQ_HANDLED; + } + +-static int tmiofb_probe(struct platform_device *dev) ++static int __devinit tmiofb_probe(struct platform_device *dev) + { + struct mfd_cell *cell = mfd_get_cell(dev); + struct tmio_fb_data *data = cell->driver_data; +-- +1.5.4.1 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0067-modeswitching.patch b/packages/linux/linux-rp-2.6.24/tosa/0067-modeswitching.patch new file mode 100644 index 0000000000..42b69d9377 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0067-modeswitching.patch @@ -0,0 +1,225 @@ +From aded2e51a7a2113dae6431c858df1d95fb312851 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Wed, 13 Feb 2008 19:34:08 +0300 +Subject: [PATCH] modeswitching + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + arch/arm/mach-pxa/tosa.c | 33 +++++++++++++++++++++++++++++++- + drivers/mfd/tc6393xb.c | 2 +- + drivers/video/backlight/tosa_bl.c | 38 +++++++++++++++++++++++++++++++++--- + drivers/video/tmiofb.c | 8 +++--- + include/asm-arm/arch-pxa/tosa.h | 2 + + include/linux/mfd/tc6393xb.h | 2 +- + include/linux/mfd/tmio.h | 2 +- + 7 files changed, 75 insertions(+), 12 deletions(-) + +diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c +index 94c9915..6631de2 100644 +--- a/arch/arm/mach-pxa/tosa.c ++++ b/arch/arm/mach-pxa/tosa.c +@@ -455,9 +455,40 @@ static struct fb_videomode tosa_tc6393xb_lcd_mode[] = { + } + }; + ++static DEFINE_SPINLOCK(tosa_lcd_mode_lock); ++ ++static const struct fb_videomode *tosa_lcd_mode = &tosa_tc6393xb_lcd_mode[0]; ++ ++static int tosa_lcd_set_mode(struct platform_device *fb_dev, ++ const struct fb_videomode *mode) ++{ ++ int rc; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&tosa_lcd_mode_lock, flags); ++ rc = tc6393xb_lcd_mode(fb_dev, mode); ++ if (!rc) ++ tosa_lcd_mode = mode; ++ spin_unlock_irqrestore(&tosa_lcd_mode_lock, flags); ++ ++ return rc; ++} ++ ++const struct fb_videomode *tosa_lcd_get_mode(void) ++{ ++ unsigned long flags; ++ const struct fb_videomode *mode; ++ ++ spin_lock_irqsave(&tosa_lcd_mode_lock, flags); ++ mode = tosa_lcd_mode; ++ spin_unlock_irqrestore(&tosa_lcd_mode_lock, flags); ++ ++ return mode; ++} ++ + static struct tmio_fb_data tosa_tc6393xb_fb_config = { + .lcd_set_power = tc6393xb_lcd_set_power, +- .lcd_mode = tc6393xb_lcd_mode, ++ .lcd_mode = tosa_lcd_set_mode, + .num_modes = ARRAY_SIZE(tosa_tc6393xb_lcd_mode), + .modes = &tosa_tc6393xb_lcd_mode[0], + }; +diff --git a/drivers/mfd/tc6393xb.c b/drivers/mfd/tc6393xb.c +index 9001687..21190f3 100644 +--- a/drivers/mfd/tc6393xb.c ++++ b/drivers/mfd/tc6393xb.c +@@ -196,7 +196,7 @@ int tc6393xb_lcd_set_power(struct platform_device *fb, bool on) + EXPORT_SYMBOL(tc6393xb_lcd_set_power); + + int tc6393xb_lcd_mode(struct platform_device *fb_dev, +- struct fb_videomode *mode) { ++ const struct fb_videomode *mode) { + struct tc6393xb *tc6393xb = + platform_get_drvdata(to_platform_device(fb_dev->dev.parent)); + struct tc6393xb_scr __iomem *scr = tc6393xb->scr; +diff --git a/drivers/video/backlight/tosa_bl.c b/drivers/video/backlight/tosa_bl.c +index 9ef0bfb..45fc6ae 100644 +--- a/drivers/video/backlight/tosa_bl.c ++++ b/drivers/video/backlight/tosa_bl.c +@@ -48,6 +48,9 @@ struct tosa_bl_data { + struct ssp_dev nssp_dev; + struct ssp_state nssp_state; + ++ /* listen for mode changes */ ++ struct notifier_block fb_notif; ++ + struct backlight_device *bl_dev; + }; + +@@ -103,14 +106,19 @@ static void tosa_lcd_tg_init(struct tosa_bl_data *data) + pxa_nssp_output(data, TG_GPOSR,0x02); /* GPOS0=powercontrol, GPOS1=GPIO, GPOS2=TCTL */ + } + +-static void tosa_lcd_tg_on(struct tosa_bl_data *data/*, const struct fb_videomode *mode*/) ++static void tosa_lcd_tg_on(struct tosa_bl_data *data) + { +- const int value = TG_REG0_COLOR | TG_REG0_UD | TG_REG0_LR; ++ const struct fb_videomode *mode = tosa_lcd_get_mode(); ++ ++ int value = TG_REG0_COLOR | TG_REG0_UD | TG_REG0_LR; ++ ++ if (mode->yres == 640) ++ value |= TG_REG0_VQV; + + tosa_lcd_tg_init(data); + +- dev_dbg(&data->bl_dev->dev, "tosa_lcd_on\n"); +- pxa_nssp_output(data, TG_PNLCTL, value | (/*mode->yres == 320 ? 0 : */ TG_REG0_VQV)); ++ dev_dbg(&data->bl_dev->dev, "tosa_lcd_on: %04x (%d)\n", value, mode->yres); ++ pxa_nssp_output(data, TG_PNLCTL, value); + + /* TG LCD pannel power up */ + pxa_nssp_output(data, TG_PINICTL,0x4); +@@ -173,6 +181,20 @@ static struct backlight_ops tosa_bl_ops = { + .update_status = tosa_bl_update_status, + }; + ++static int fb_notifier_callback(struct notifier_block *self, ++ unsigned long event, void *_data) ++{ ++ struct tosa_bl_data *bl_data = ++ container_of(self, struct tosa_bl_data, fb_notif); ++ ++ if (event != FB_EVENT_MODE_CHANGE && event != FB_EVENT_MODE_CHANGE_ALL) ++ return 0; ++ ++ tosa_bl_update_status(bl_data->bl_dev); ++ ++ return 0; ++} ++ + static int tosa_bl_detect_client(struct i2c_adapter *adapter, int address, + int kind) + { +@@ -238,9 +260,15 @@ static int tosa_bl_detect_client(struct i2c_adapter *adapter, int address, + data->bl_dev->props.power = FB_BLANK_UNBLANK; + backlight_update_status(data->bl_dev); + ++ data->fb_notif.notifier_call = fb_notifier_callback; ++ err = fb_register_client(&data->fb_notif); ++ if (err) ++ goto err_fb_register; + + return 0; + ++err_fb_register: ++ backlight_device_unregister(data->bl_dev); + err_bl_register: + tosa_set_backlight(data, 0); + tosa_lcd_tg_off(data); +@@ -265,6 +293,8 @@ static int tosa_bl_detach_client(struct i2c_client *client) + int err = 0; + struct tosa_bl_data *data = i2c_get_clientdata(client); + ++ fb_unregister_client(&data->fb_notif); ++ + backlight_device_unregister(data->bl_dev); + + tosa_set_backlight(data, 0); +diff --git a/drivers/video/tmiofb.c b/drivers/video/tmiofb.c +index 958ee8a..cc75df9 100644 +--- a/drivers/video/tmiofb.c ++++ b/drivers/video/tmiofb.c +@@ -618,17 +618,17 @@ static int tmiofb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) + + static int tmiofb_set_par(struct fb_info *info) + { +-/* struct fb_var_screeninfo *var = &info->var; ++ struct fb_var_screeninfo *var = &info->var; + struct fb_videomode *mode; + + mode = tmiofb_find_mode(info, var); + if (!mode) + return -EINVAL; + +- if (info->mode == mode) +- return 0; ++/* if (info->mode == mode) ++ return 0;*/ + +- info->mode = mode; */ ++ info->mode = mode; + info->fix.line_length = info->mode->xres * 2; + + tmiofb_hw_mode(to_platform_device(info->device)); +diff --git a/include/asm-arm/arch-pxa/tosa.h b/include/asm-arm/arch-pxa/tosa.h +index 410fa9a..624c636 100644 +--- a/include/asm-arm/arch-pxa/tosa.h ++++ b/include/asm-arm/arch-pxa/tosa.h +@@ -230,4 +230,6 @@ extern struct platform_device tosascoop_device; + #define TOSA_KEY_MAIL KEY_MAIL + #endif + ++const struct fb_videomode *tosa_lcd_get_mode(void); ++ + #endif /* _ASM_ARCH_TOSA_H_ */ +diff --git a/include/linux/mfd/tc6393xb.h b/include/linux/mfd/tc6393xb.h +index 97c4c7c..8ab9e91 100644 +--- a/include/linux/mfd/tc6393xb.h ++++ b/include/linux/mfd/tc6393xb.h +@@ -53,7 +53,7 @@ struct tc6393xb_platform_data { + + extern int tc6393xb_lcd_set_power(struct platform_device *fb_dev, bool on); + extern int tc6393xb_lcd_mode(struct platform_device *fb_dev, +- struct fb_videomode *mode); ++ const struct fb_videomode *mode); + + /* + * Relative to irq_base +diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h +index b6d4aac..fe7ff2d 100644 +--- a/include/linux/mfd/tmio.h ++++ b/include/linux/mfd/tmio.h +@@ -19,7 +19,7 @@ struct tmio_fb_data { + int (*lcd_set_power)(struct platform_device *fb_dev, + bool on); + int (*lcd_mode)(struct platform_device *fb_dev, +- struct fb_videomode *mode); ++ const struct fb_videomode *mode); + int num_modes; + struct fb_videomode *modes; + }; +-- +1.5.4.1 + diff --git a/packages/linux/linux-rp-2.6.24/tosa/0068-Preliminary-tosa-denoiser.patch b/packages/linux/linux-rp-2.6.24/tosa/0068-Preliminary-tosa-denoiser.patch new file mode 100644 index 0000000000..e90e3751c0 --- /dev/null +++ b/packages/linux/linux-rp-2.6.24/tosa/0068-Preliminary-tosa-denoiser.patch @@ -0,0 +1,239 @@ +From f7dad1cd9c1bd3fce5d228e0b644a51baea50cd9 Mon Sep 17 00:00:00 2001 +From: Dmitry Baryshkov <dbaryshkov@gmail.com> +Date: Fri, 15 Feb 2008 15:35:07 +0300 +Subject: [PATCH] Preliminary tosa denoiser + +Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com> +--- + drivers/input/touchscreen/Kconfig | 12 ++ + drivers/input/touchscreen/Makefile | 1 + + drivers/input/touchscreen/tosa-wm97xx.c | 182 +++++++++++++++++++++++++++++++ + 3 files changed, 195 insertions(+), 0 deletions(-) + create mode 100644 drivers/input/touchscreen/tosa-wm97xx.c + +diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig +index 0be05a2..938aed2 100644 +--- a/drivers/input/touchscreen/Kconfig ++++ b/drivers/input/touchscreen/Kconfig +@@ -210,6 +210,18 @@ config TOUCHSCREEN_WM97XX_MAINSTONE + To compile this driver as a module, choose M here: the + module will be called mainstone-wm97xx + ++config TOUCHSCREEN_WM97XX_TOSA ++ tristate "WM97xx Tosa denoiser" ++ depends on TOUCHSCREEN_WM97XX && MACH_TOSA ++ help ++ Say Y here for support for touchscreen denoising on ++ Sharl Zaurus SL-6000 (tosa) system. ++ ++ If unsure, say N ++ ++ To compile this driver as a module, choose M here: the ++ module will be called tosa-wm97xx ++ + config TOUCHSCREEN_TOUCHWIN + tristate "Touchwin serial touchscreen" + select SERIO +diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile +index d38156e..d86278b 100644 +--- a/drivers/input/touchscreen/Makefile ++++ b/drivers/input/touchscreen/Makefile +@@ -23,6 +23,7 @@ obj-$(CONFIG_TOUCHSCREEN_TOUCHWIN) += touchwin.o + obj-$(CONFIG_TOUCHSCREEN_UCB1400) += ucb1400_ts.o + obj-$(CONFIG_TOUCHSCREEN_WM97XX) += wm97xx-ts.o + obj-$(CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE) += mainstone-wm97xx.o ++obj-$(CONFIG_TOUCHSCREEN_WM97XX_TOSA) += tosa-wm97xx.o + wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9705) += wm9705.o + wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9712) += wm9712.o + wm97xx-ts-$(CONFIG_TOUCHSCREEN_WM9713) += wm9713.o +diff --git a/drivers/input/touchscreen/tosa-wm97xx.c b/drivers/input/touchscreen/tosa-wm97xx.c +new file mode 100644 +index 0000000..8fd542b +--- /dev/null ++++ b/drivers/input/touchscreen/tosa-wm97xx.c +@@ -0,0 +1,182 @@ ++/* ++ * tosa_ts.c -- Touchscreen driver for Sharp SL-6000 (Tosa). ++ * ++ * Copyright 2008 Dmitry Baryshkov ++ * Copyright 2006 Wolfson Microelectronics PLC. ++ * Author: Mike Arthur ++ * linux@wolfsonmicro.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * Revision history ++ * 1st Sep 2006 Initial version. ++ * ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/platform_device.h> ++#include <linux/wm97xx.h> ++#include <linux/fb.h> ++ ++#include <asm/arch/tosa.h> ++#include <asm/gpio.h> ++ ++static unsigned long hsync_time = 0; ++ ++static void calc_hsync_time(const struct fb_videomode *mode) ++{ ++ /* The 25 and 44 'magic numbers' are from Sharp's 2.4 patches */ ++ if (mode->yres == 640) { ++ hsync_time = 25; ++ } else if (mode->yres == 320) { ++ hsync_time = 44; ++ } else { ++ printk(KERN_ERR "unknown video mode res specified: %dx%d!", mode->xres, mode->yres); ++ WARN_ON(1); ++ } ++ ++ printk(KERN_ERR "tosa-wm97xx: using %lu hsync time\n", hsync_time); ++} ++ ++static int fb_notifier_callback(struct notifier_block *self, ++ unsigned long event, void *_data) ++{ ++ if (event != FB_EVENT_MODE_CHANGE && event != FB_EVENT_MODE_CHANGE_ALL) ++ return 0; ++ ++ calc_hsync_time(tosa_lcd_get_mode()); ++ ++ return 0; ++} ++ ++static void tosa_lcd_wait_hsync(void) ++{ ++ /* Waits for a rising edge on the VGA line */ ++ while (gpio_get_value(TOSA_GPIO_VGA_LINE) == 0); ++ while (gpio_get_value(TOSA_GPIO_VGA_LINE) != 0); ++} ++ ++/* Taken from the Sharp 2.4 kernel code */ ++#define CCNT(a) asm volatile ("mrc p14, 0, %0, C1, C1, 0" : "=r"(a)) ++#define CCNT_ON() asm("mcr p14, 0, %0, C0, C0, 0" : : "r"(1)) ++#define CCNT_OFF() asm("mcr p14, 0, %0, C0, C0, 0" : : "r"(0)) ++ ++/* On the Sharp SL-6000 (Tosa), due to a noisy LCD, we need to perform a wait ++ * before sampling the Y axis of the touchscreen */ ++static void tosa_lcd_sync_on(int adcsel) ++{ ++ unsigned long timer1 = 0, timer2 = 0, wait_time = 0; ++ if (adcsel & WM97XX_ADCSEL_Y) { ++ CCNT_ON(); ++ wait_time = hsync_time; ++ ++ if (wait_time) { ++ ++ /* wait for LCD rising edge */ ++ tosa_lcd_wait_hsync(); ++ /* get clock */ ++ CCNT(timer1); ++ CCNT(timer2); ++ ++ while ((timer2 - timer1) < wait_time) { ++ CCNT(timer2); ++ } ++ } ++ } ++} ++ ++static void tosa_lcd_sync_off(int adcsel) ++{ ++ if (adcsel & WM97XX_ADCSEL_Y) ++ CCNT_OFF(); ++} ++ ++static struct wm97xx_mach_ops tosa_mach_ops = { ++ .pre_sample = tosa_lcd_sync_on, ++ .post_sample = tosa_lcd_sync_off, ++}; ++ ++static int __devinit tosa_ts_probe(struct platform_device *dev) { ++ struct wm97xx *wm = platform_get_drvdata(dev); ++ struct notifier_block *notif; ++ int err = -ENOMEM; ++ ++ notif = kzalloc(sizeof(struct notifier_block), GFP_KERNEL); ++ if (!notif) ++ goto err_alloc; ++ ++ notif->notifier_call = fb_notifier_callback; ++ ++ err = gpio_request(TOSA_GPIO_VGA_LINE, "hsync"); ++ if (err) ++ goto err_gpio; ++ ++ err = gpio_direction_input(TOSA_GPIO_VGA_LINE); ++ if (err) ++ goto err_gpio; ++ ++ platform_set_drvdata(dev, notif); ++ ++ err = fb_register_client(notif); ++ if (err) ++ goto err_register; ++ ++ err = wm97xx_register_mach_ops(wm, &tosa_mach_ops); ++ if (err) ++ goto err_wm97xx; ++ ++ calc_hsync_time(tosa_lcd_get_mode()); ++ ++ return 0; ++ ++err_wm97xx: ++ fb_unregister_client(notif); ++err_register: ++ gpio_free(TOSA_GPIO_VGA_LINE); ++err_gpio: ++ kfree(notif); ++err_alloc: ++ return err; ++} ++ ++ ++static int __devexit tosa_ts_remove(struct platform_device *dev) { ++ struct wm97xx *wm = platform_get_drvdata(dev); ++ ++ wm97xx_unregister_mach_ops(wm); ++ ++ fb_unregister_client(platform_get_drvdata(dev)); ++ gpio_free(TOSA_GPIO_VGA_LINE); ++ kfree(platform_get_drvdata(dev)); ++ ++ return 0; ++} ++ ++static struct platform_driver tosa_ts_driver = { ++ .driver.name = "wm97xx-touch", ++ .driver.owner = THIS_MODULE, ++ .probe = tosa_ts_probe, ++ .remove = __devexit_p(tosa_ts_remove), ++}; ++ ++static int __init tosa_ts_init(void) ++{ ++ return platform_driver_register(&tosa_ts_driver); ++} ++ ++static void __exit tosa_ts_exit(void) ++{ ++ platform_driver_unregister(&tosa_ts_driver); ++} ++ ++module_init(tosa_ts_init); ++module_exit(tosa_ts_exit); ++ ++/* Module information */ ++MODULE_AUTHOR("Dmitry Baryshkov, Mike Arthur, mike@mikearthur.co.uk, www.wolfsonmicro.com"); ++MODULE_DESCRIPTION("Sharp SL6000 Tosa Touch Screen Denoiser"); ++MODULE_LICENSE("GPL"); +-- +1.5.4.1 + diff --git a/packages/linux/linux-rp_2.6.24.bb b/packages/linux/linux-rp_2.6.24.bb index b3e04980de..48f964d7e7 100644 --- a/packages/linux/linux-rp_2.6.24.bb +++ b/packages/linux/linux-rp_2.6.24.bb @@ -5,6 +5,7 @@ PR = "r5" DEFAULT_PREFERENCE = "-1" DEFAULT_PREFERENCE_collie = "1" DEFAULT_PREFERENCE_qemux86 = "1" +DEFAULT_PREFERENCE_tosa = "1" # Handy URLs # git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git;protocol=git;tag=ef7d1b244fa6c94fb76d5f787b8629df64ea4046 @@ -68,9 +69,8 @@ SRC_URI = "${KERNELORG_MIRROR}pub/linux/kernel/v2.6/linux-2.6.24.tar.bz2 \ file://defconfig-qemux86 \ file://defconfig-bootcdx86 \ file://defconfig-htcuniversal \ + file://defconfig-tosa \ file://defconfig-zylonite" -# Tosa disabled until the patchset is updated -# file://defconfig-tosa # FIXMEs before made default # ${RPSRC}/mmcsd_no_scr_check-r1.patch;patch=1;status=hack @@ -109,34 +109,75 @@ SRC_URI_append_poodle = "\ " SRC_URI_append_tosa = "\ - ${CHSRC}/tmio-core-r4.patch;patch=1 \ - file://tmio-tc6393-r8.patch;patch=1 \ - file://tmio-nand-r8.patch;patch=1 \ - ${CHSRC}/tmio-fb-r6.patch;patch=1 \ - file://tmio-fb-r6-fix-r0.patch;patch=1 \ - file://tosa-keyboard-r19.patch;patch=1 \ - ${DOSRC}/tosa-pxaac97-r6.patch;patch=1 \ - file://tosa-pxaac97-r6-fix-r0.patch;patch=1 \ - ${DOSRC}/tosa-tmio-r6.patch;patch=1 \ - file://tosa-power-r18.patch;patch=1 \ - file://tosa-power-r18-fix-r0.patch;patch=1 \ - file://tosa-tmio-lcd-r10.patch;patch=1 \ - file://tosa-tmio-lcd-r10-fix-r0.patch;patch=1 \ - file://tosa-bluetooth-r8.patch;patch=1 \ - file://wm97xx-lg13-r0.patch;patch=1 \ - file://wm97xx-lg13-r0-fix-r0.patch;patch=1 \ - file://wm9712-suspend-cold-res-r2.patch;patch=1 \ - file://sharpsl-pm-postresume-r1.patch;patch=1 \ - file://wm9712-reset-loop-r2.patch;patch=1 \ - file://tosa-lcdnoise-r1.patch;patch=1 \ - file://tosa-lcdnoise-r1-fix-r0.patch;patch=1 \ - file://arm-dma-coherent.patch;patch=1 \ - file://usb-ohci-hooks-r3.patch;patch=1 \ - file://tmio-ohci-r9.patch;patch=1 \ - file://pxa2xx_udc_support_inverse_vbus.patch;patch=1 \ - file://tosa_udc_use_gpio_vbus.patch;patch=1 \ + file://tosa/0001-Allow-runtime-registration-of-regions-of-memory-that.patch;patch=1 \ + file://tosa/0002-Modify-dma_alloc_coherent-on-ARM-so-that-it-supports.patch;patch=1 \ + file://tosa/0003-Core-MFD-support.patch;patch=1 \ + file://tosa/0004-Add-support-for-tc6393xb-MFD-core.patch;patch=1 \ + file://tosa/0005-Add-support-for-tc6387xb-MFD-core.patch;patch=1 \ + file://tosa/0006-Add-support-for-t7l66xb-MFD-core.patch;patch=1 \ + file://tosa/0007-Common-headers-for-TMIO-MFD-subdevices.patch;patch=1 \ + file://tosa/0008-Nand-driver-for-TMIO-devices.patch;patch=1 \ + file://tosa/0009-FB-driver-for-TMIO-devices.patch;patch=1 \ + file://tosa/0010-OHCI-driver-for-TMIO-devices.patch;patch=1 \ + file://tosa/0011-MMC-driver-for-TMIO-devices.patch;patch=1 \ + file://tosa/0012-Tosa-keyboard-support.patch;patch=1 \ + file://tosa/0013-USB-gadget-pxa2xx_udc-supports-inverted-vbus.patch;patch=1 \ + file://tosa/0014-tosa_udc_use_gpio_vbus.patch.patch;patch=1 \ + file://tosa/0015-sharpsl-export-params.patch;patch=1 \ + file://tosa/0016-This-patch-fixes-the-pxa25x-clocks-definitions-to-ad.patch;patch=1 \ + file://tosa/0017-Convert-pxa2xx-UDC-to-use-debugfs.patch;patch=1 \ + file://tosa/0018-Fix-the-pxa2xx_udc-to-balance-calls-to-clk_enable-cl.patch;patch=1 \ + file://tosa/0026-I-don-t-think-we-should-check-for-IRQs-when-determin.patch;patch=1 \ + file://tosa/0027-Add-LiMn-one-of-the-most-common-for-small-non-recha.patch;patch=1 \ + file://tosa/0028-Add-suspend-resume-wakeup-support-for-pda_power.patch;patch=1 \ + file://tosa/0029-Support-using-VOLTAGE_-properties-for-apm-calculati.patch;patch=1 \ + file://tosa/0030-Core-driver-for-WM97xx-touchscreens.patch;patch=1 \ + file://tosa/0031-Add-chip-driver-for-WM9705-touchscreen.patch;patch=1 \ + file://tosa/0032-Add-chip-driver-for-WM9712-touchscreen.patch;patch=1 \ + file://tosa/0033-Add-chip-driver-for-WM9713-touchscreen.patch;patch=1 \ + file://tosa/0034-Driver-for-WM97xx-touchscreens-in-streaming-mode-on.patch;patch=1 \ + file://tosa/0035-Build-system-and-MAINTAINERS-entry-for-WM97xx-touchs.patch;patch=1 \ + file://tosa/0036-Set-id-to-1-for-wm97xx-subdevices.patch;patch=1 \ + file://tosa/0037-Don-t-lock-the-codec-list-in-snd_soc_dapm_new_widget.patch;patch=1 \ + file://tosa/0038-Don-t-lock-the-codec-list-in-snd_soc_dapm_new_widget.patch;patch=1 \ + file://tosa/0044-fix-tmio_mmc-debug-compilation.patch;patch=1 \ + file://tosa/0045-Update-tmio_ohci.patch;patch=1 \ + file://tosa/0046-patch-tc6393xb-cleanup.patch;patch=1 \ + file://tosa/0047-tc6393xb-use-bitmasks-instead-of-bit-field-structs.patch;patch=1 \ + file://tosa/0048-tc6393xb-GPIO-support.patch;patch=1 \ + file://tosa/0049-platform-support-for-TMIO-on-tosa.patch;patch=1 \ + file://tosa/0050-tosa-update-for-tc6393xb-gpio.patch;patch=1 \ + file://tosa/0051-fix-sound-soc-pxa-tosa.c-to-new-gpio-api.patch;patch=1 \ + file://tosa/0052-tosa-platform-backlight-support.patch;patch=1 \ + file://tosa/0053-sound-soc-codecs-wm9712.c-28.patch;patch=1 \ + file://tosa/0054-sound-soc-codecs-wm9712.c-2.patch;patch=1 \ + file://tosa/0055-Add-GPIO_POWERON-to-the-list-of-devices-that-we-supp.patch;patch=1 \ + file://tosa/0058-Fix-tosakbd-suspend.patch;patch=1 \ + file://tosa/0059-patch-tosa-wakeup-test.patch;patch=1 \ + file://tosa/0060-Add-support-for-power_supply-on-tosa.patch;patch=1 \ + file://tosa/0061-tosa-bat-unify.patch;patch=1 \ + file://tosa/0062-tosa-bat-fix-charging.patch;patch=1 \ + file://tosa/0063-patch-tosa-bat-jacket-detect.patch;patch=1 \ + file://tosa/0064-Export-modes-via-sysfs.patch;patch=1 \ + file://tosa/0065-wm97xx-core-fixes.patch;patch=1 \ + file://tosa/0066-tmiofb_probe-should-be-__devinit.patch;patch=1 \ + file://tosa/0067-modeswitching.patch;patch=1 \ + file://tosa/0068-Preliminary-tosa-denoiser.patch;patch=1 \ + file://tosa/0019-pxa-remove-periodic-mode-emulation-support.patch;patch=1 \ + file://tosa/0020-Provide-dew-device-clock-backports-from-2.6.24-git.patch;patch=1 \ + file://tosa/0021-Add-an-empty-drivers-gpio-directory-for-gpiolib-infr.patch;patch=1 \ + file://tosa/0022-Provide-new-implementation-infrastructure-that-platf.patch;patch=1 \ + file://tosa/0023-This-adds-gpiolib-support-for-the-PXA-architecture.patch;patch=1 \ + file://tosa/0024-Update-Documentation-gpio.txt-primarily-to-include.patch;patch=1 \ + file://tosa/0025-Signed-off-by-Dmitry-Baryshkov-dbaryshkov-gmail.co.patch;patch=1 \ + file://tosa/0039-Add-generic-framework-for-managing-clocks.patch;patch=1 \ + file://tosa/0040-Clocklib-debugfs-support.patch;patch=1 \ + file://tosa/0041-From-80a359e60c2aec59ccf4fca0a7fd20495f82b1d2-Mon-Se.patch;patch=1 \ + file://tosa/0042-Use-correct-clock-for-IrDA-on-pxa.patch;patch=1 \ + file://tosa/0043-Use-clocklib-for-sa1100-sub-arch.patch;patch=1 \ + file://tosa/0056-Support-resetting-by-asserting-GPIO-pin.patch;patch=1 \ + file://tosa/0057-Clean-up-tosa-resetting.patch;patch=1 \ " -# ${DOSRC}/tosa-asoc-r1.patch;patch=1 " SRC_URI_append_akita = "\ file://mtd-module.patch;patch=1;status=external \ diff --git a/packages/linux/linux.inc b/packages/linux/linux.inc index 835437415f..e0303c272f 100644 --- a/packages/linux/linux.inc +++ b/packages/linux/linux.inc @@ -144,6 +144,5 @@ do_deploy() { do_deploy[dirs] = "${S}" -addtask sizecheck before do_install after do_compile addtask deploy before do_package after do_install diff --git a/packages/linux/linux_2.6.24.bb b/packages/linux/linux_2.6.24.bb index 40ffef7d0b..7fc1aa38ca 100644 --- a/packages/linux/linux_2.6.24.bb +++ b/packages/linux/linux_2.6.24.bb @@ -6,20 +6,21 @@ DEFAULT_PREFERENCE_gesbc-9302 = "1" DEFAULT_PREFERENCE_cm-x270 = "1" DEFAULT_PREFERENCE_mpc8313e-rdb = "1" DEFAULT_PREFERENCE_simpad = "1" +DEFAULT_PREFERENCE_atngw100 = "1" +DEFAULT_PREFERENCE_at32stk1000 = "1" DEPENDS_append_mpc8313e-rdb = " dtc-native" -PR = "r7" +PR = "r9" SRC_URI = "${KERNELORG_MIRROR}/pub/linux/kernel/v2.6/linux-2.6.24.tar.bz2 \ http://kamikaze.waninkoko.info/patches/2.6.24/kamikaze1/broken-out/squashfs-lzma-2.6.24.patch;patch=1 \ - file://powerpc-clockres.patch;patch=1 \ - file://leds-cpu-activity.patch;patch=1 \ - file://leds-cpu-activity-powerpc.patch;patch=1 \ file://defconfig" -# Real-time preemption. This is experimental and requires a different defconfig. -#SRC_URI += " http://www.kernel.org/pub/linux/kernel/projects/rt/patch-2.6.24-rt1.bz2;patch=1" +# Moved away temporarely until committed properly (work in progress). +# file://powerpc-clockres.patch;patch=1 \ +# file://leds-cpu-activity.patch;patch=1 \ +# file://leds-cpu-activity-powerpc.patch;patch=1 \ SRC_URI_append_simpad = "\ file://linux-2.6.24-SIMpad-GPIO-MMC-mod.patch;patch=1 \ @@ -32,6 +33,7 @@ SRC_URI_append_simpad = "\ file://linux-2.6.24-SIMpad-ucb1x00-ts-supend-and-accuracy.patch;patch=1 \ file://linux-2.6.24-SIMpad-hostap_cs-shared-irq.patch;patch=1 \ file://linux-2.6.24-SIMpad-orinoco_cs-shared-irq.patch;patch=1 \ + file://linux-2.6.24-SIMpad-rtc-sa1100.patch;patch=1 \ file://collie-kexec.patch;patch=1 \ file://export_atags-r2.patch;patch=1 \ " @@ -57,6 +59,11 @@ SRC_URI_append_cm-x270 = " \ file://0005-add-display-set-default-16bpp.patch;patch=1 \ " +SRC_URI_avr32 = "http://avr32linux.org/twiki/pub/Main/LinuxPatches/linux-2.6.24.3.atmel.3.tar.bz2 \ + file://defconfig" +S_avr32 = "${WORKDIR}/linux-2.6.24.3.atmel.3" + + CMDLINE_cm-x270 = "console=${CMX270_CONSOLE_SERIAL_PORT},38400 monitor=1 mem=64M mtdparts=physmap-flash.0:256k(boot)ro,0x180000(kernel),-(root);cm-x270-nand:64m(app),-(data) rdinit=/sbin/init root=mtd3 rootfstype=jffs2" FILES_kernel-image_gesbc-9302 = "" |