diff options
Diffstat (limited to 'packages/linux/nas100d-kernel')
33 files changed, 6754 insertions, 0 deletions
diff --git a/packages/linux/nas100d-kernel/.mtn2git_empty b/packages/linux/nas100d-kernel/.mtn2git_empty new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/packages/linux/nas100d-kernel/.mtn2git_empty diff --git a/packages/linux/nas100d-kernel/2.6.14/.mtn2git_empty b/packages/linux/nas100d-kernel/2.6.14/.mtn2git_empty new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/packages/linux/nas100d-kernel/2.6.14/.mtn2git_empty diff --git a/packages/linux/nas100d-kernel/2.6.14/10-ixp4xx-copy-from.patch b/packages/linux/nas100d-kernel/2.6.14/10-ixp4xx-copy-from.patch new file mode 100644 index 0000000000..f3da2e093f --- /dev/null +++ b/packages/linux/nas100d-kernel/2.6.14/10-ixp4xx-copy-from.patch @@ -0,0 +1,73 @@ +--- linux-2.6.14/drivers/mtd/maps/ixp4xx.c 2005-10-27 17:02:08.000000000 -0700 ++++ linux-2.6.14/drivers/mtd/maps/ixp4xx.c 2005-10-29 23:11:24.990820968 -0700 +@@ -38,10 +38,14 @@ + #define BYTE1(h) ((h) & 0xFF) + #endif + ++#define FLASHWORD(a) (*(__u16*)(a)) ++#define FLASHVAL(a) FLASHWORD(a) ++#define FLASHSET(a,v) do { FLASHWORD(a) = (v); } while (0) ++ + static map_word ixp4xx_read16(struct map_info *map, unsigned long ofs) + { + map_word val; +- val.x[0] = *(__u16 *) (map->map_priv_1 + ofs); ++ val.x[0] = FLASHVAL(map->map_priv_1 + ofs); + return val; + } + +@@ -53,19 +57,25 @@ static map_word ixp4xx_read16(struct map + static void ixp4xx_copy_from(struct map_info *map, void *to, + unsigned long from, ssize_t len) + { +- int i; +- u8 *dest = (u8 *) to; +- u16 *src = (u16 *) (map->map_priv_1 + from); +- u16 data; +- +- for (i = 0; i < (len / 2); i++) { +- data = src[i]; +- dest[i * 2] = BYTE0(data); +- dest[i * 2 + 1] = BYTE1(data); ++ u8 *dest, *src; ++ ++ if (len <= 0) ++ return; ++ ++ dest = (u8 *) to; ++ src = (u8 *) (map->map_priv_1 + from); ++ if (from & 1) ++ *dest++ = BYTE1(FLASHVAL(src-1)), ++src, --len; ++ ++ while (len >= 2) { ++ u16 data = FLASHVAL(src); src += 2; ++ *dest++ = BYTE0(data); ++ *dest++ = BYTE1(data); ++ len -= 2; + } + +- if (len & 1) +- dest[len - 1] = BYTE0(src[i]); ++ if (len > 0) ++ *dest++ = BYTE0(FLASHVAL(src)); + } + + /* +@@ -75,7 +85,7 @@ static void ixp4xx_copy_from(struct map_ + static void ixp4xx_probe_write16(struct map_info *map, map_word d, unsigned long adr) + { + if (!(adr & 1)) +- *(__u16 *) (map->map_priv_1 + adr) = d.x[0]; ++ FLASHSET(map->map_priv_1 + adr, d.x[0]); + } + + /* +@@ -83,7 +93,7 @@ static void ixp4xx_probe_write16(struct + */ + static void ixp4xx_write16(struct map_info *map, map_word d, unsigned long adr) + { +- *(__u16 *) (map->map_priv_1 + adr) = d.x[0]; ++ FLASHSET(map->map_priv_1 + adr, d.x[0]); + } + + struct ixp4xx_flash_info { diff --git a/packages/linux/nas100d-kernel/2.6.14/10-ixp4xx-le.patch b/packages/linux/nas100d-kernel/2.6.14/10-ixp4xx-le.patch new file mode 100644 index 0000000000..0b50e4e1a0 --- /dev/null +++ b/packages/linux/nas100d-kernel/2.6.14/10-ixp4xx-le.patch @@ -0,0 +1,54 @@ +--- linux-2.6.14/drivers/mtd/maps/ixp4xx.c 2005-10-27 17:02:08.000000000 -0700 ++++ linux-2.6.14/drivers/mtd/maps/ixp4xx.c 2005-10-29 23:11:24.990820968 -0700 +@@ -22,6 +22,7 @@ + #include <linux/string.h> + #include <linux/mtd/mtd.h> + #include <linux/mtd/map.h> ++#include <linux/mtd/cfi_endian.h> + #include <linux/mtd/partitions.h> + #include <linux/ioport.h> + #include <linux/device.h> +@@ -30,17 +31,40 @@ + + #include <linux/reboot.h> + ++/* On a little-endian IXP4XX system (tested on NSLU2) an LDRH or STRH ++ * will flip the second address bit - i.e. XOR the address with 10b. ++ * This causes the cfi commands (sent to the command address, 0xAA for ++ * 16 bit flash) to fail. This is fixed here by XOR'ing the address ++ * before use with 10b. The cost of this is that the flash layout ends ++ * up with pdp-endiannes (on an LE system), however this is not a problem ++ * as the access code consistently only accesses half words - so the ++ * endianness is not determinable on stuff which is written and read ++ * consistently in the little endian world. ++ * ++ * For flash data from the big-endian world, however, the results are ++ * weird - the pdp-endianness results in the data apparently being ++ * 2-byte swapped (as in dd conv=swab). To work round this the 16 ++ * bit values are written and read using cpu_to_cfi16 and cfi16_to_cpu, ++ * by default these are no-ops, but if the MTD driver is configed with ++ * CONFIG_MTD_CFI_BE_BYTE_SWAP the macros will byte swap the data, ++ * resulting in a consistently BE view of the flash on both BE (no ++ * op) and LE systems. This config setting also causes the command ++ * data from the CFI implementation to get swapped - as is required ++ * so that this code will *unswap* it and give the correct command ++ * data to the flash. ++ */ + #ifndef __ARMEB__ + #define BYTE0(h) ((h) & 0xFF) + #define BYTE1(h) (((h) >> 8) & 0xFF) ++#define FLASHWORD(a) (*(__u16*)((u32)(a) ^ 2)) + #else + #define BYTE0(h) (((h) >> 8) & 0xFF) + #define BYTE1(h) ((h) & 0xFF) ++#define FLASHWORD(a) (*(__u16*)(a)) + #endif + +-#define FLASHWORD(a) (*(__u16*)(a)) +-#define FLASHVAL(a) FLASHWORD(a) +-#define FLASHSET(a,v) do { FLASHWORD(a) = (v); } while (0) ++#define FLASHVAL(a) cfi16_to_cpu(FLASHWORD(a)) ++#define FLASHSET(a,v) (FLASHWORD(a) = cpu_to_cfi16(v)) + + static map_word ixp4xx_read16(struct map_info *map, unsigned long ofs) + { diff --git a/packages/linux/nas100d-kernel/2.6.14/10-mtdpart-redboot-fis-byteswap.patch b/packages/linux/nas100d-kernel/2.6.14/10-mtdpart-redboot-fis-byteswap.patch new file mode 100644 index 0000000000..37d19bd1b0 --- /dev/null +++ b/packages/linux/nas100d-kernel/2.6.14/10-mtdpart-redboot-fis-byteswap.patch @@ -0,0 +1,44 @@ +On IXP4XX systems the FIS directory is big endian even with a little +endian kernel. This patch recognises the FIS directory on such a +system and byte swaps it to obtain a valid table based on the 'size' +field of the FIS directory (the size field is know to always match the +erase block size on such systems, and probably all systems.) + +--- linux-2.6.13/.pc/10-mtdpart-redboot-fis-byteswap.patch/drivers/mtd/redboot.c 2005-08-28 16:41:01.000000000 -0700 ++++ linux-2.6.13/drivers/mtd/redboot.c 2005-10-23 21:44:59.999694674 -0700 +@@ -89,8 +89,34 @@ + i = numslots; + break; + } +- if (!memcmp(buf[i].name, "FIS directory", 14)) ++ if (!memcmp(buf[i].name, "FIS directory", 14)) { ++ /* This is apparently the FIS directory entry for the ++ * FIS directory itself. The FIS directory size is ++ * one erase block, if the buf[i].size field is ++ * swab32(erasesize) then we know we are looking at ++ * a byte swapped FIS directory - swap all the entries! ++ * (NOTE: this is 'size' not 'data_length', size is ++ * the full size of the entry.) ++ */ ++ if (swab32(buf[i].size) == master->erasesize) { ++ int j; ++ for (j = 0; j < numslots && buf[j].name[0] != 0xff; ++j) { ++ /* The unsigned long fields were written with the ++ * wrong byte sex, name and pad have no byte sex. ++ */ ++# define do_swab32(x) (x) = swab32(x) ++ do_swab32(buf[j].flash_base); ++ do_swab32(buf[j].mem_base); ++ do_swab32(buf[j].size); ++ do_swab32(buf[j].entry_point); ++ do_swab32(buf[j].data_length); ++ do_swab32(buf[j].desc_cksum); ++ do_swab32(buf[j].file_cksum); ++# undef do_swab32 ++ } ++ } + break; ++ } + } + if (i == numslots) { + /* Didn't find it */ diff --git a/packages/linux/nas100d-kernel/2.6.14/15-ixp4xx-writesb-l-w.patch b/packages/linux/nas100d-kernel/2.6.14/15-ixp4xx-writesb-l-w.patch new file mode 100644 index 0000000000..6ac0807f1e --- /dev/null +++ b/packages/linux/nas100d-kernel/2.6.14/15-ixp4xx-writesb-l-w.patch @@ -0,0 +1,31 @@ +# The inline caller of these APIs were changed to have +# const vaddr parameters... +--- linux-2.6.13/include/asm-arm/arch-ixp4xx/io.h.orig 2005-09-24 17:06:19.968099976 -0700 ++++ linux-2.6.13/include/asm-arm/arch-ixp4xx/io.h 2005-09-24 17:06:52.542149731 -0700 +@@ -113,7 +113,7 @@ + } + + static inline void +-__ixp4xx_writesb(u32 bus_addr, u8 *vaddr, int count) ++__ixp4xx_writesb(u32 bus_addr, const u8 *vaddr, int count) + { + while (count--) + writeb(*vaddr++, bus_addr); +@@ -136,7 +136,7 @@ + } + + static inline void +-__ixp4xx_writesw(u32 bus_addr, u16 *vaddr, int count) ++__ixp4xx_writesw(u32 bus_addr, const u16 *vaddr, int count) + { + while (count--) + writew(*vaddr++, bus_addr); +@@ -154,7 +154,7 @@ + } + + static inline void +-__ixp4xx_writesl(u32 bus_addr, u32 *vaddr, int count) ++__ixp4xx_writesl(u32 bus_addr, const u32 *vaddr, int count) + { + while (count--) + writel(*vaddr++, bus_addr); diff --git a/packages/linux/nas100d-kernel/2.6.14/18-ixp4xx-io-h-addr.patch b/packages/linux/nas100d-kernel/2.6.14/18-ixp4xx-io-h-addr.patch new file mode 100644 index 0000000000..5813bbb7ac --- /dev/null +++ b/packages/linux/nas100d-kernel/2.6.14/18-ixp4xx-io-h-addr.patch @@ -0,0 +1,287 @@ +--- linux-2.6.14/include/asm-arm/arch-ixp4xx/io.h 2005-10-29 23:33:21.757679882 -0700 ++++ linux-2.6.14/include/asm-arm/arch-ixp4xx/io.h 2005-10-29 23:47:02.581331058 -0700 +@@ -80,9 +80,9 @@ __ixp4xx_iounmap(void __iomem *addr) + #define __arch_ioremap(a, s, f, x) __ixp4xx_ioremap(a, s, f, x) + #define __arch_iounmap(a) __ixp4xx_iounmap(a) + +-#define writeb(p, v) __ixp4xx_writeb(p, v) +-#define writew(p, v) __ixp4xx_writew(p, v) +-#define writel(p, v) __ixp4xx_writel(p, v) ++#define writeb(v, p) __ixp4xx_writeb(v, p) ++#define writew(v, p) __ixp4xx_writew(v, p) ++#define writel(v, p) __ixp4xx_writel(v, p) + + #define writesb(p, v, l) __ixp4xx_writesb(p, v, l) + #define writesw(p, v, l) __ixp4xx_writesw(p, v, l) +@@ -97,8 +97,9 @@ __ixp4xx_iounmap(void __iomem *addr) + #define readsl(p, v, l) __ixp4xx_readsl(p, v, l) + + static inline void +-__ixp4xx_writeb(u8 value, u32 addr) ++__ixp4xx_writeb(u8 value, volatile void __iomem *p) + { ++ u32 addr = (u32)p; + u32 n, byte_enables, data; + + if (addr >= VMALLOC_START) { +@@ -113,15 +114,16 @@ __ixp4xx_writeb(u8 value, u32 addr) + } + + static inline void +-__ixp4xx_writesb(u32 bus_addr, const u8 *vaddr, int count) ++__ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count) + { + while (count--) + writeb(*vaddr++, bus_addr); + } + + static inline void +-__ixp4xx_writew(u16 value, u32 addr) ++__ixp4xx_writew(u16 value, volatile void __iomem *p) + { ++ u32 addr = (u32)p; + u32 n, byte_enables, data; + + if (addr >= VMALLOC_START) { +@@ -136,15 +138,16 @@ __ixp4xx_writew(u16 value, u32 addr) + } + + static inline void +-__ixp4xx_writesw(u32 bus_addr, const u16 *vaddr, int count) ++__ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count) + { + while (count--) + writew(*vaddr++, bus_addr); + } + + static inline void +-__ixp4xx_writel(u32 value, u32 addr) ++__ixp4xx_writel(u32 value, volatile void __iomem *p) + { ++ u32 addr = (u32)p; + if (addr >= VMALLOC_START) { + __raw_writel(value, addr); + return; +@@ -154,15 +157,16 @@ __ixp4xx_writel(u32 value, u32 addr) + } + + static inline void +-__ixp4xx_writesl(u32 bus_addr, const u32 *vaddr, int count) ++__ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count) + { + while (count--) + writel(*vaddr++, bus_addr); + } + + static inline unsigned char +-__ixp4xx_readb(u32 addr) ++__ixp4xx_readb(const volatile void __iomem *p) + { ++ u32 addr = (u32)p; + u32 n, byte_enables, data; + + if (addr >= VMALLOC_START) +@@ -177,15 +181,16 @@ __ixp4xx_readb(u32 addr) + } + + static inline void +-__ixp4xx_readsb(u32 bus_addr, u8 *vaddr, u32 count) ++__ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count) + { + while (count--) + *vaddr++ = readb(bus_addr); + } + + static inline unsigned short +-__ixp4xx_readw(u32 addr) ++__ixp4xx_readw(const volatile void __iomem *p) + { ++ u32 addr = (u32)p; + u32 n, byte_enables, data; + + if (addr >= VMALLOC_START) +@@ -200,15 +205,16 @@ __ixp4xx_readw(u32 addr) + } + + static inline void +-__ixp4xx_readsw(u32 bus_addr, u16 *vaddr, u32 count) ++__ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count) + { + while (count--) + *vaddr++ = readw(bus_addr); + } + + static inline unsigned long +-__ixp4xx_readl(u32 addr) ++__ixp4xx_readl(const volatile void __iomem *p) + { ++ u32 addr = (u32)p; + u32 data; + + if (addr >= VMALLOC_START) +@@ -221,7 +227,7 @@ __ixp4xx_readl(u32 addr) + } + + static inline void +-__ixp4xx_readsl(u32 bus_addr, u32 *vaddr, u32 count) ++__ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count) + { + while (count--) + *vaddr++ = readl(bus_addr); +@@ -239,7 +245,7 @@ __ixp4xx_readsl(u32 bus_addr, u32 *vaddr + eth_copy_and_sum((s),__mem_pci(c),(l),(b)) + + static inline int +-check_signature(unsigned long bus_addr, const unsigned char *signature, ++check_signature(const unsigned char __iomem *bus_addr, const unsigned char *signature, + int length) + { + int retval = 0; +@@ -389,7 +395,7 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u + #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ + ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) + static inline unsigned int +-__ixp4xx_ioread8(void __iomem *addr) ++__ixp4xx_ioread8(const void __iomem *addr) + { + unsigned long port = (unsigned long __force)addr; + if (__is_io_address(port)) +@@ -398,12 +404,12 @@ __ixp4xx_ioread8(void __iomem *addr) + #ifndef CONFIG_IXP4XX_INDIRECT_PCI + return (unsigned int)__raw_readb(port); + #else +- return (unsigned int)__ixp4xx_readb(port); ++ return (unsigned int)__ixp4xx_readb(addr); + #endif + } + + static inline void +-__ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count) ++__ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) + { + unsigned long port = (unsigned long __force)addr; + if (__is_io_address(port)) +@@ -412,12 +418,12 @@ __ixp4xx_ioread8_rep(void __iomem *addr, + #ifndef CONFIG_IXP4XX_INDIRECT_PCI + __raw_readsb(addr, vaddr, count); + #else +- __ixp4xx_readsb(port, vaddr, count); ++ __ixp4xx_readsb(addr, vaddr, count); + #endif + } + + static inline unsigned int +-__ixp4xx_ioread16(void __iomem *addr) ++__ixp4xx_ioread16(const void __iomem *addr) + { + unsigned long port = (unsigned long __force)addr; + if (__is_io_address(port)) +@@ -426,12 +432,12 @@ __ixp4xx_ioread16(void __iomem *addr) + #ifndef CONFIG_IXP4XX_INDIRECT_PCI + return le16_to_cpu(__raw_readw((u32)port)); + #else +- return (unsigned int)__ixp4xx_readw((u32)port); ++ return (unsigned int)__ixp4xx_readw(addr); + #endif + } + + static inline void +-__ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count) ++__ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count) + { + unsigned long port = (unsigned long __force)addr; + if (__is_io_address(port)) +@@ -440,12 +446,12 @@ __ixp4xx_ioread16_rep(void __iomem *addr + #ifndef CONFIG_IXP4XX_INDIRECT_PCI + __raw_readsw(addr, vaddr, count); + #else +- __ixp4xx_readsw(port, vaddr, count); ++ __ixp4xx_readsw(addr, vaddr, count); + #endif + } + + static inline unsigned int +-__ixp4xx_ioread32(void __iomem *addr) ++__ixp4xx_ioread32(const void __iomem *addr) + { + unsigned long port = (unsigned long __force)addr; + if (__is_io_address(port)) +@@ -454,13 +460,13 @@ __ixp4xx_ioread32(void __iomem *addr) + #ifndef CONFIG_IXP4XX_INDIRECT_PCI + return le32_to_cpu(__raw_readl((u32)port)); + #else +- return (unsigned int)__ixp4xx_readl((u32)port); ++ return (unsigned int)__ixp4xx_readl(addr); + #endif + } + } + + static inline void +-__ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count) ++__ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count) + { + unsigned long port = (unsigned long __force)addr; + if (__is_io_address(port)) +@@ -469,7 +475,7 @@ __ixp4xx_ioread32_rep(void __iomem *addr + #ifndef CONFIG_IXP4XX_INDIRECT_PCI + __raw_readsl(addr, vaddr, count); + #else +- __ixp4xx_readsl(port, vaddr, count); ++ __ixp4xx_readsl(addr, vaddr, count); + #endif + } + +@@ -483,7 +489,7 @@ __ixp4xx_iowrite8(u8 value, void __iomem + #ifndef CONFIG_IXP4XX_INDIRECT_PCI + __raw_writeb(value, port); + #else +- __ixp4xx_writeb(value, port); ++ __ixp4xx_writeb(value, addr); + #endif + } + +@@ -497,7 +503,7 @@ __ixp4xx_iowrite8_rep(void __iomem *addr + #ifndef CONFIG_IXP4XX_INDIRECT_PCI + __raw_writesb(addr, vaddr, count); + #else +- __ixp4xx_writesb(port, vaddr, count); ++ __ixp4xx_writesb(addr, vaddr, count); + #endif + } + +@@ -511,7 +517,7 @@ __ixp4xx_iowrite16(u16 value, void __iom + #ifndef CONFIG_IXP4XX_INDIRECT_PCI + __raw_writew(cpu_to_le16(value), addr); + #else +- __ixp4xx_writew(value, port); ++ __ixp4xx_writew(value, addr); + #endif + } + +@@ -525,7 +531,7 @@ __ixp4xx_iowrite16_rep(void __iomem *add + #ifndef CONFIG_IXP4XX_INDIRECT_PCI + __raw_writesw(addr, vaddr, count); + #else +- __ixp4xx_writesw(port, vaddr, count); ++ __ixp4xx_writesw(addr, vaddr, count); + #endif + } + +@@ -539,7 +545,7 @@ __ixp4xx_iowrite32(u32 value, void __iom + #ifndef CONFIG_IXP4XX_INDIRECT_PCI + __raw_writel(cpu_to_le32(value), port); + #else +- __ixp4xx_writel(value, port); ++ __ixp4xx_writel(value, addr); + #endif + } + +@@ -553,7 +559,7 @@ __ixp4xx_iowrite32_rep(void __iomem *add + #ifndef CONFIG_IXP4XX_INDIRECT_PCI + __raw_writesl(addr, vaddr, count); + #else +- __ixp4xx_writesl(port, vaddr, count); ++ __ixp4xx_writesl(addr, vaddr, count); + #endif + } + diff --git a/packages/linux/nas100d-kernel/2.6.14/28-spinlock-up.patch b/packages/linux/nas100d-kernel/2.6.14/28-spinlock-up.patch new file mode 100644 index 0000000000..3ae5178cff --- /dev/null +++ b/packages/linux/nas100d-kernel/2.6.14/28-spinlock-up.patch @@ -0,0 +1,32 @@ +--- linux-2.6.14-rc5/include/linux/spinlock_up.h 2005-10-26 08:37:20.164248408 -0700 ++++ patched/include/linux/spinlock_up.h 2005-10-26 12:15:13.458898975 -0700 +@@ -47,6 +47,14 @@ static inline void __raw_spin_unlock(raw + lock->slock = 1; + } + ++#else /* DEBUG_SPINLOCK */ ++#define __raw_spin_is_locked(lock) ((void)(lock), 0) ++/* for sched.c and kernel_lock.c: */ ++# define __raw_spin_lock(lock) do { (void)(lock); } while (0) ++# define __raw_spin_unlock(lock) do { (void)(lock); } while (0) ++# define __raw_spin_trylock(lock) ({ (void)(lock); 1; }) ++#endif /* DEBUG_SPINLOCK */ ++ + /* + * Read-write spinlocks. No debug version. + */ +@@ -57,14 +65,6 @@ static inline void __raw_spin_unlock(raw + #define __raw_read_unlock(lock) do { (void)(lock); } while (0) + #define __raw_write_unlock(lock) do { (void)(lock); } while (0) + +-#else /* DEBUG_SPINLOCK */ +-#define __raw_spin_is_locked(lock) ((void)(lock), 0) +-/* for sched.c and kernel_lock.c: */ +-# define __raw_spin_lock(lock) do { (void)(lock); } while (0) +-# define __raw_spin_unlock(lock) do { (void)(lock); } while (0) +-# define __raw_spin_trylock(lock) ({ (void)(lock); 1; }) +-#endif /* DEBUG_SPINLOCK */ +- + #define __raw_read_can_lock(lock) (((void)(lock), 1)) + #define __raw_write_can_lock(lock) (((void)(lock), 1)) + diff --git a/packages/linux/nas100d-kernel/2.6.14/29-ipv4-route-c-spinlock.patch b/packages/linux/nas100d-kernel/2.6.14/29-ipv4-route-c-spinlock.patch new file mode 100644 index 0000000000..93e070518c --- /dev/null +++ b/packages/linux/nas100d-kernel/2.6.14/29-ipv4-route-c-spinlock.patch @@ -0,0 +1,11 @@ +--- linux-2.6.14-rc5/net/ipv4/route.c 2005-10-26 08:37:20.752285410 -0700 ++++ patched/net/ipv4/route.c 2005-10-26 12:17:00.761651111 -0700 +@@ -231,7 +231,7 @@ static spinlock_t *rt_hash_locks; + spin_lock_init(&rt_hash_locks[i]); \ + } + #else +-# define rt_hash_lock_addr(slot) NULL ++# define rt_hash_lock_addr(slot) ((spinlock_t*)NULL) + # define rt_hash_lock_init() + #endif + diff --git a/packages/linux/nas100d-kernel/2.6.14/50-nas100d-arch.patch b/packages/linux/nas100d-kernel/2.6.14/50-nas100d-arch.patch new file mode 100644 index 0000000000..51ab586010 --- /dev/null +++ b/packages/linux/nas100d-kernel/2.6.14/50-nas100d-arch.patch @@ -0,0 +1,64 @@ + arch/arm/mach-ixp4xx/Kconfig | 8 ++++++++ + arch/arm/mach-ixp4xx/Makefile | 1 + + arch/arm/tools/mach-types | 1 + + include/asm-arm/arch-ixp4xx/hardware.h | 1 + + include/asm-arm/arch-ixp4xx/irqs.h | 9 +++++++++ + 5 files changed, 20 insertions(+) + +--- linux-2.6.14.orig/arch/arm/mach-ixp4xx/Kconfig 2005-11-09 00:58:58.000000000 +0100 ++++ linux-2.6.14/arch/arm/mach-ixp4xx/Kconfig 2005-11-11 22:23:08.000000000 +0100 +@@ -61,6 +61,14 @@ config ARCH_PRPMC1100 + PrPCM1100 Processor Mezanine Module. For more information on + this platform, see <file:Documentation/arm/IXP4xx>. + ++config MACH_NAS100D ++ bool ++ prompt "NAS100D" ++ help ++ Say 'Y' here if you want your kernel to support Iomega's ++ NAS 100d device. For more information on this platform, ++ see http://www.nslu2-linux.org/wiki/NAS100d/HomePage ++ + # + # Avila and IXDP share the same source for now. Will change in future + # +--- linux-2.6.14.orig/arch/arm/mach-ixp4xx/Makefile 2005-11-09 00:58:58.000000000 +0100 ++++ linux-2.6.14/arch/arm/mach-ixp4xx/Makefile 2005-11-11 22:23:08.000000000 +0100 +@@ -8,4 +8,5 @@ obj-$(CONFIG_ARCH_IXDP4XX) += ixdp425-pc + obj-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o coyote-setup.o + obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o coyote-setup.o + obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o gtwx5715-setup.o ++obj-$(CONFIG_MACH_NAS100D) += nas100d-pci.o nas100d-setup.o nas100d-power.o + +--- linux-2.6.14.orig/include/asm-arm/arch-ixp4xx/hardware.h 2005-11-09 00:59:41.000000000 +0100 ++++ linux-2.6.14/include/asm-arm/arch-ixp4xx/hardware.h 2005-11-11 22:23:08.000000000 +0100 +@@ -44,5 +44,6 @@ extern unsigned int processor_id; + #include "ixdp425.h" + #include "coyote.h" + #include "prpmc1100.h" ++#include "nas100d.h" + + #endif /* _ASM_ARCH_HARDWARE_H */ +--- linux-2.6.14.orig/include/asm-arm/arch-ixp4xx/irqs.h 2005-11-09 00:59:41.000000000 +0100 ++++ linux-2.6.14/include/asm-arm/arch-ixp4xx/irqs.h 2005-11-11 23:01:50.000000000 +0100 +@@ -93,4 +93,13 @@ + #define IRQ_COYOTE_PCI_SLOT1 IRQ_IXP4XX_GPIO11 + #define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5 + ++/* ++ * NAS100D board IRQs ++ */ ++#define IRQ_NAS100D_PCI_INTA IRQ_IXP4XX_GPIO11 ++#define IRQ_NAS100D_PCI_INTB IRQ_IXP4XX_GPIO10 ++#define IRQ_NAS100D_PCI_INTC IRQ_IXP4XX_GPIO9 ++#define IRQ_NAS100D_PCI_INTD IRQ_IXP4XX_GPIO8 ++#define IRQ_NAS100D_PCI_INTE IRQ_IXP4XX_GPIO7 ++ + #endif +--- linux-2.6.14.orig/arch/arm/tools/mach-types 2005-11-09 00:58:59.000000000 +0100 ++++ linux-2.6.14/arch/arm/tools/mach-types 2005-11-11 22:23:08.000000000 +0100 +@@ -869,3 +869,4 @@ davinci_dvdp MACH_DAVINCI_DVDP DAVINCI_ + htcuniversal MACH_HTCUNIVERSAL HTCUNIVERSAL 855 + tpad MACH_TPAD TPAD 856 + roverp3 MACH_ROVERP3 ROVERP3 857 ++nas100d MACH_NAS100D NAS100D 865 diff --git a/packages/linux/nas100d-kernel/2.6.14/60-nas100d-i2c.patch b/packages/linux/nas100d-kernel/2.6.14/60-nas100d-i2c.patch new file mode 100644 index 0000000000..5e180093a4 --- /dev/null +++ b/packages/linux/nas100d-kernel/2.6.14/60-nas100d-i2c.patch @@ -0,0 +1,649 @@ + drivers/i2c/busses/i2c-ixp4xx.c | 9 + drivers/i2c/chips/Kconfig | 9 + drivers/i2c/chips/Makefile | 1 + drivers/i2c/chips/pcf8563.c | 547 ++++++++++++++++++++++++++++++++++++++++ + include/linux/pcf8563.h | 24 + + 5 files changed, 587 insertions(+), 3 deletions(-) + +--- linux-nas100d.orig/drivers/i2c/busses/i2c-ixp4xx.c 2005-11-11 22:22:43.000000000 +0100 ++++ linux-nas100d/drivers/i2c/busses/i2c-ixp4xx.c 2005-11-15 22:06:23.000000000 +0100 +@@ -65,7 +65,6 @@ static int ixp4xx_bit_getscl(void *data) + + gpio_line_config(ixp4xx_scl_pin(data), IXP4XX_GPIO_IN ); + gpio_line_get(ixp4xx_scl_pin(data), &scl); +- + return scl; + } + +@@ -75,7 +74,6 @@ static int ixp4xx_bit_getsda(void *data) + + gpio_line_config(ixp4xx_sda_pin(data), IXP4XX_GPIO_IN ); + gpio_line_get(ixp4xx_sda_pin(data), &sda); +- + return sda; + } + +@@ -127,7 +125,10 @@ static int ixp4xx_i2c_probe(struct devic + drv_data->algo_data.udelay = 10; + drv_data->algo_data.mdelay = 10; + drv_data->algo_data.timeout = 100; +- ++#ifdef CONFIG_MACH_NAS100D ++ drv_data->algo_data.udelay = 100; ++ drv_data->algo_data.mdelay = 100; ++#endif + drv_data->adapter.id = I2C_HW_B_IXP4XX; + drv_data->adapter.algo_data = &drv_data->algo_data; + +@@ -145,6 +146,8 @@ static int ixp4xx_i2c_probe(struct devic + return err; + } + ++ printk(KERN_INFO "i2c: ixp4xx 0.0.4\n"); ++ + dev_set_drvdata(&plat_dev->dev, drv_data); + + return 0; +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-nas100d/drivers/i2c/chips/pcf8563.c 2005-11-16 11:34:15.000000000 +0100 +@@ -0,0 +1,547 @@ ++/* ++ * pcf8563.c - An i2c driver for the Philips PCF8563 RTC ++ * Copyright 2005 Alessandro Zummo ++ * ++ * please send all reports to: ++ * a dot zummo at towertech dot it ++ * ++ * based on the other drivers in this same directory. ++ * ++ * http://www.semiconductors.philips.com/acrobat/datasheets/PCF8563-04.pdf ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include <linux/module.h> ++#include <linux/init.h> ++#include <linux/slab.h> ++#include <linux/i2c.h> ++#include <linux/string.h> ++#include <linux/bcd.h> ++#include <linux/rtc.h> ++#include <linux/list.h> ++ ++#include <linux/pcf8563.h> ++ ++#define DRV_VERSION "0.3.1" ++ ++/* Addresses to scan */ ++static unsigned short normal_i2c[] = { 0x51, I2C_CLIENT_END }; ++ ++/* Module parameters */ ++I2C_CLIENT_INSMOD; ++I2C_CLIENT_MODULE_PARM(hctosys, ++ "Set the system time from the hardware clock upon initialization"); ++ ++#define PCF8563_REG_ST1 0x00 /* status */ ++#define PCF8563_REG_ST2 0x01 ++ ++#define PCF8563_REG_SC 0x02 /* datetime */ ++#define PCF8563_REG_MN 0x03 ++#define PCF8563_REG_HR 0x04 ++#define PCF8563_REG_DM 0x05 ++#define PCF8563_REG_DW 0x06 ++#define PCF8563_REG_MO 0x07 ++#define PCF8563_REG_YR 0x08 ++ ++#define PCF8563_REG_AMN 0x09 /* alarm */ ++#define PCF8563_REG_AHR 0x0A ++#define PCF8563_REG_ADM 0x0B |