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-rw-r--r--packages/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch278
1 files changed, 278 insertions, 0 deletions
diff --git a/packages/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch b/packages/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch
new file mode 100644
index 0000000000..bdf9e293d6
--- /dev/null
+++ b/packages/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch
@@ -0,0 +1,278 @@
+From: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+To: linux-omap@vger.kernel.org
+Cc: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+Subject: [PATCH 2/3] ARM: OMAP: SmartReflex driver: added required register and bit definitions.
+Date: Fri, 6 Jun 2008 12:49:48 +0300
+
+Added new register and bit definitions to enable Smartreflex driver integration.
+Also PRM_VC_SMPS_SA bit definitions' naming was changed to match the naming of
+other similar bit definitions.
+
+Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+---
+ arch/arm/mach-omap2/prm-regbits-34xx.h | 27 ++++++--
+ arch/arm/mach-omap2/smartreflex.h | 124 ++++++++++++++++++++++++++++++-
+ include/asm-arm/arch-omap/control.h | 19 +++++
+ include/asm-arm/arch-omap/omap34xx.h | 2 +
+ 4 files changed, 163 insertions(+), 9 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
+index c6a7940..f82b5a7 100644
+--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
++++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
+@@ -435,10 +435,10 @@
+ /* PM_PWSTST_EMU specific bits */
+
+ /* PRM_VC_SMPS_SA */
+-#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16
+-#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16)
+-#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0
+-#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0)
++#define OMAP3430_SMPS_SA1_SHIFT 16
++#define OMAP3430_SMPS_SA1_MASK (0x7f << 16)
++#define OMAP3430_SMPS_SA0_SHIFT 0
++#define OMAP3430_SMPS_SA0_MASK (0x7f << 0)
+
+ /* PRM_VC_SMPS_VOL_RA */
+ #define OMAP3430_VOLRA1_SHIFT 16
+@@ -452,7 +452,7 @@
+ #define OMAP3430_CMDRA0_SHIFT 0
+ #define OMAP3430_CMDRA0_MASK (0xff << 0)
+
+-/* PRM_VC_CMD_VAL_0 specific bits */
++/* PRM_VC_CMD_VAL */
+ #define OMAP3430_VC_CMD_ON_SHIFT 24
+ #define OMAP3430_VC_CMD_ON_MASK (0xFF << 24)
+ #define OMAP3430_VC_CMD_ONLP_SHIFT 16
+@@ -462,7 +462,17 @@
+ #define OMAP3430_VC_CMD_OFF_SHIFT 0
+ #define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0)
+
++/* PRM_VC_CMD_VAL_0 specific bits */
++#define OMAP3430_VC_CMD_VAL0_ON (0x3 << 4)
++#define OMAP3430_VC_CMD_VAL0_ONLP (0x3 << 3)
++#define OMAP3430_VC_CMD_VAL0_RET (0x3 << 3)
++#define OMAP3430_VC_CMD_VAL0_OFF (0x3 << 3)
++
+ /* PRM_VC_CMD_VAL_1 specific bits */
++#define OMAP3430_VC_CMD_VAL1_ON (0xB << 2)
++#define OMAP3430_VC_CMD_VAL1_ONLP (0x3 << 3)
++#define OMAP3430_VC_CMD_VAL1_RET (0x3 << 3)
++#define OMAP3430_VC_CMD_VAL1_OFF (0x3 << 3)
+
+ /* PRM_VC_CH_CONF */
+ #define OMAP3430_CMD1 (1 << 20)
+@@ -521,6 +531,13 @@
+ #define OMAP3430_AUTO_RET (1 << 1)
+ #define OMAP3430_AUTO_SLEEP (1 << 0)
+
++/* Constants to define setup durations */
++#define OMAP3430_CLKSETUP_DURATION 0xff
++#define OMAP3430_VOLTSETUP_TIME2 0xfff
++#define OMAP3430_VOLTSETUP_TIME1 0xfff
++#define OMAP3430_VOLTOFFSET_DURATION 0xff
++#define OMAP3430_VOLTSETUP2_DURATION 0xff
++
+ /* PRM_SRAM_PCHARGE */
+ #define OMAP3430_PCHARGE_TIME_SHIFT 0
+ #define OMAP3430_PCHARGE_TIME_MASK (0xff << 0)
+diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
+index 62907ef..2091a15 100644
+--- a/arch/arm/mach-omap2/smartreflex.h
++++ b/arch/arm/mach-omap2/smartreflex.h
+@@ -1,5 +1,10 @@
++#ifndef __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H
++#define __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H
+ /*
+- * linux/arch/arm/mach-omap3/smartreflex.h
++ * linux/arch/arm/mach-omap2/smartreflex.h
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Kalle Jokiniemi
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <x0080970@ti.com>
+@@ -9,6 +14,21 @@
+ * published by the Free Software Foundation.
+ */
+
++#define PHY_TO_OFF_PM_MASTER(p) (p - 0x36)
++#define PHY_TO_OFF_PM_RECIEVER(p) (p - 0x5b)
++#define PHY_TO_OFF_PM_INT(p) (p - 0x2e)
++
++/* SMART REFLEX REG ADDRESS OFFSET */
++#define SRCONFIG 0x00
++#define SRSTATUS 0x04
++#define SENVAL 0x08
++#define SENMIN 0x0C
++#define SENMAX 0x10
++#define SENAVG 0x14
++#define AVGWEIGHT 0x18
++#define NVALUERECIPROCAL 0x1C
++#define SENERROR 0x20
++#define ERRCONFIG 0x24
+
+ /* SR Modules */
+ #define SR1 1
+@@ -127,10 +147,106 @@
+ #define SR2_ERRMAXLIMIT (0x02 << 8)
+ #define SR2_ERRMINLIMIT (0xF9 << 0)
+
++/* T2 SMART REFLEX */
++#define R_SRI2C_SLAVE_ADDR 0x12
++#define R_VDD1_SR_CONTROL 0x00
++#define R_VDD2_SR_CONTROL 0x01
++#define T2_SMPS_UPDATE_DELAY 360 /* In uSec */
++
++/* Vmode control */
++#define R_DCDC_GLOBAL_CFG PHY_TO_OFF_PM_RECIEVER(0x61)
++
++#define R_VDD1_VSEL PHY_TO_OFF_PM_RECIEVER(0xb9)
++#define R_VDD1_VMODE_CFG PHY_TO_OFF_PM_RECIEVER(0xba)
++#define R_VDD1_VFLOOR PHY_TO_OFF_PM_RECIEVER(0xbb)
++#define R_VDD1_VROOF PHY_TO_OFF_PM_RECIEVER(0xbc)
++#define R_VDD1_STEP PHY_TO_OFF_PM_RECIEVER(0xbd)
++
++#define R_VDD2_VSEL PHY_TO_OFF_PM_RECIEVER(0xc7)
++#define R_VDD2_VMODE_CFG PHY_TO_OFF_PM_RECIEVER(0xc8)
++#define R_VDD2_VFLOOR PHY_TO_OFF_PM_RECIEVER(0xc9)
++#define R_VDD2_VROOF PHY_TO_OFF_PM_RECIEVER(0xca)
++#define R_VDD2_STEP PHY_TO_OFF_PM_RECIEVER(0xcb)
++
++/* R_DCDC_GLOBAL_CFG register, SMARTREFLEX_ENABLE valuws */
++#define DCDC_GLOBAL_CFG_ENABLE_SRFLX 0x08
++
++/* VDDs*/
++#define PRCM_VDD1 1
++#define PRCM_VDD2 2
++#define PRCM_MAX_SYSC_REGS 30
++
++/* XXX: These should be removed/moved from here once we have a working DVFS
++ implementation in place */
++#define AT_3430 1 /*3430 ES 1.0 */
++#define AT_3430_ES2 2 /*3430 ES 2.0 */
++
++#define ID_OPP 0xE2 /*OPP*/
++
++/* DEVICE ID/DPLL ID/CLOCK ID: bits 28-31 for OMAP type */
++#define OMAP_TYPE_SHIFT 28
++#define OMAP_TYPE_MASK 0xF
++/* OPP ID: bits: 0-4 for OPP number */
++#define OPP_NO_POS 0
++#define OPP_NO_MASK 0x1F
++/* OPP ID: bits: 5-6 for VDD */
++#define VDD_NO_POS 5
++#define VDD_NO_MASK 0x3
++/* Other IDs: bits 20-27 for ID type */
++/* These IDs have bits 25,26,27 as 1 */
++#define OTHER_ID_TYPE_SHIFT 20
++#define OTHER_ID_TYPE_MASK 0xFF
++
++#define OTHER_ID_TYPE(X) ((X & OTHER_ID_TYPE_MASK) << OTHER_ID_TYPE_SHIFT)
++#define ID_OPP_NO(X) ((X & OPP_NO_MASK) << OPP_NO_POS)
++#define ID_VDD(X) ((X & VDD_NO_MASK) << VDD_NO_POS)
++#define OMAP(X) ((X >> OMAP_TYPE_SHIFT) & OMAP_TYPE_MASK)
++#define get_opp_no(X) ((X >> OPP_NO_POS) & OPP_NO_MASK)
++#define get_vdd(X) ((X >> VDD_NO_POS) & VDD_NO_MASK)
++
++/* VDD1 OPPs */
++#define PRCM_VDD1_OPP1 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
++ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x1))
++#define PRCM_VDD1_OPP2 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
++ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x2))
++#define PRCM_VDD1_OPP3 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
++ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x3))
++#define PRCM_VDD1_OPP4 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
++ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x4))
++#define PRCM_VDD1_OPP5 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
++ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x5))
++#define PRCM_NO_VDD1_OPPS 5
++
++
++/* VDD2 OPPs */
++#define PRCM_VDD2_OPP1 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
++ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x1))
++#define PRCM_VDD2_OPP2 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
++ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x2))
++#define PRCM_VDD2_OPP3 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
++ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x3))
++#define PRCM_NO_VDD2_OPPS 3
++/* XXX: end remove/move */
++
++
++/* XXX: find more appropriate place for these once DVFS is in place */
+ extern u32 current_vdd1_opp;
+ extern u32 current_vdd2_opp;
+-extern struct kset power_subsys;
+
+-extern inline int loop_wait(u32 *lcnt, u32 *rcnt, u32 delay);
+-extern void omap_udelay(u32 udelay);
++/*
++ * Smartreflex module enable/disable interface.
++ * NOTE: if smartreflex is not enabled from sysfs, these functions will not
++ * do anything.
++ */
++#if defined(CONFIG_ARCH_OMAP34XX) && defined(CONFIG_TWL4030_CORE)
++void enable_smartreflex(int srid);
++void disable_smartreflex(int srid);
++#else
++static inline void enable_smartreflex(int srid) {}
++static inline void disable_smartreflex(int srid) {}
++#endif
++
++
++#endif
++
+
+diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h
+index 12bc22a..6e64fe7 100644
+--- a/include/asm-arm/arch-omap/control.h
++++ b/include/asm-arm/arch-omap/control.h
+@@ -138,6 +138,15 @@
+ #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4)
+ #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8)
+ #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
++#define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)
++#define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)
++#define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)
++#define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c)
++#define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
++#define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124)
++#define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
++#define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c)
++#define OMAP343X_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130)
+ #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
+ #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
+ #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4)
+@@ -172,6 +181,16 @@
+ #define OMAP2_SYSBOOT_1_MASK (1 << 1)
+ #define OMAP2_SYSBOOT_0_MASK (1 << 0)
+
++/* CONTROL_FUSE_SR bits */
++#define OMAP343X_SR2_SENNENABLE_MASK (0x3 << 10)
++#define OMAP343X_SR2_SENNENABLE_SHIFT 10
++#define OMAP343X_SR2_SENPENABLE_MASK (0x3 << 8)
++#define OMAP343X_SR2_SENPENABLE_SHIFT 8
++#define OMAP343X_SR1_SENNENABLE_MASK (0x3 << 2)
++#define OMAP343X_SR1_SENNENABLE_SHIFT 2
++#define OMAP343X_SR1_SENPENABLE_MASK (0x3 << 0)
++#define OMAP343X_SR1_SENPENABLE_SHIFT 0
++
+ #ifndef __ASSEMBLY__
+ #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+ extern void __iomem *omap_ctrl_base_get(void);
+diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h
+index 6a0459a..3667fd6 100644
+--- a/include/asm-arm/arch-omap/omap34xx.h
++++ b/include/asm-arm/arch-omap/omap34xx.h
+@@ -54,6 +54,8 @@
+ #define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000)
+ #define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
+ #define IRQ_SIR_IRQ 0x0040
++#define OMAP34XX_SR1_BASE 0x480C9000
++#define OMAP34XX_SR2_BASE 0x480CB000
+
+
+ #if defined(CONFIG_ARCH_OMAP3430)
+--
+1.5.4.3