diff options
| -rwxr-xr-x | contrib/mtn-bisect.sh | 26 | ||||
| -rw-r--r-- | packages/dsplink/dsplink_1.50.bb | 2 | ||||
| -rw-r--r-- | packages/linux/linux-omap2-git/beagleboard/00001-mcbsp-transform.patch | 1160 | ||||
| -rw-r--r-- | packages/linux/linux-omap2-git/beagleboard/00002-mcbsp-omap1.patch | 204 | ||||
| -rw-r--r-- | packages/linux/linux-omap2-git/beagleboard/00003-mcbsp-omap3-clock.patch | 123 | ||||
| -rw-r--r-- | packages/linux/linux-omap2-git/beagleboard/00004-omap2-mcbsp.patch | 144 | ||||
| -rw-r--r-- | packages/linux/linux-omap2-git/beagleboard/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch | 55 | ||||
| -rw-r--r-- | packages/linux/linux-omap2-git/beagleboard/defconfig | 195 | ||||
| -rw-r--r-- | packages/linux/linux-omap2_git.bb | 11 | ||||
| -rw-r--r-- | packages/u-boot/files/sffsdr-u-boot.patch | 718 | ||||
| -rw-r--r-- | packages/u-boot/u-boot_git.bb | 4 | ||||
| -rw-r--r-- | packages/vnc/x11vnc_0.9.3.bb | 2 |
12 files changed, 2467 insertions, 177 deletions
diff --git a/contrib/mtn-bisect.sh b/contrib/mtn-bisect.sh new file mode 100755 index 0000000000..e1c970d974 --- /dev/null +++ b/contrib/mtn-bisect.sh @@ -0,0 +1,26 @@ +#!/bin/bash + +# the revision that we noticed does not longer build +LATEST_BAD_REV=$1 + +# an older revision that is known to build +LAST_KNOWN_GOOD_REV=$2 + +# count the number of commits +COUNT=`mtn log --brief --no-merges --no-graph --to p:$LAST_KNOWN_GOOD_REV --from $LATEST_BAD_REV | tee /tmp/candidates.txt | wc -l` + +echo $COUNT commits + +# if COUNT == 1 stop + +# make binary sections +COUNT=$(($(($COUNT + 1)) / 2)) + +CANDIDATE_REV=`cat /tmp/candidates.txt | head -n $COUNT | tail -n 1 | sed -e 's@\([a-f0-9]*\) .*@\1@'` + +echo $CANDIDATE_REV + +echo mtn up -r $CANDIDATE_REV +mtn up -r $CANDIDATE_REV + + diff --git a/packages/dsplink/dsplink_1.50.bb b/packages/dsplink/dsplink_1.50.bb index 7051966ffc..dae3b04999 100644 --- a/packages/dsplink/dsplink_1.50.bb +++ b/packages/dsplink/dsplink_1.50.bb @@ -14,7 +14,7 @@ SRC_URI = "http://install.tarball.in.source.dir/dsplink_1_50.tar.gz \ file://CURRENTCFG.MK \ file://c64xx_5.xx_linux.mk \ file://davinci_mvlpro5.0.mk \ - file://prcs-fix-include.patch;patch=1 \ + file://prcs-fix-include.patch;patch=1;pnum=2 \ " S = "${WORKDIR}/dsplink_1_50/dsplink" diff --git a/packages/linux/linux-omap2-git/beagleboard/00001-mcbsp-transform.patch b/packages/linux/linux-omap2-git/beagleboard/00001-mcbsp-transform.patch new file mode 100644 index 0000000000..452370bf3e --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/00001-mcbsp-transform.patch @@ -0,0 +1,1160 @@ +From: Eduardo Valentin <eduardo.valentin@indt.org.br>
+
+This patch transform mcbsp code into a very initial
+implementation of a platform driver.
+
+It also gets ride of ifdefs on mcbsp.c code.
+To do it, a platform data structure was defined.
+
+Platform devices are located in arch/arm/plat-omap/devices.c
+
+Signed-off-by: Eduardo Valentin <eduardo.valentin@indt.org.br>
+---
+ arch/arm/plat-omap/devices.c | 45 +++
+ arch/arm/plat-omap/mcbsp.c | 660 ++++++++++++++-----------------------
+ include/asm-arm/arch-omap/mcbsp.h | 73 ++++-
+ 3 files changed, 367 insertions(+), 411 deletions(-)
+
+diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
+index 099182b..b3e0147 100644
+--- a/arch/arm/plat-omap/devices.c
++++ b/arch/arm/plat-omap/devices.c
+@@ -27,6 +27,7 @@
+ #include <asm/arch/gpio.h>
+ #include <asm/arch/menelaus.h>
+ #include <asm/arch/dsp_common.h>
++#include <asm/arch/mcbsp.h>
+
+ #if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
+
+@@ -150,6 +151,49 @@ static inline void omap_init_kp(void) {}
+ #endif
+
+ /*-------------------------------------------------------------------------*/
++#if defined(CONFIG_OMAP_MCBSP) || defined(CONFIG_OMAP_MCBSP_MODULE)
++
++static struct platform_device omap_mcbsp_devices[OMAP_MAX_MCBSP_COUNT];
++static int mcbsps_configured;
++
++void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
++ int size)
++{
++ int i;
++
++ if (size > OMAP_MAX_MCBSP_COUNT) {
++ printk(KERN_WARNING "Registered too many McBSPs platform_data."
++ " Using maximum (%d) available.\n",
++ OMAP_MAX_MCBSP_COUNT);
++ size = OMAP_MAX_MCBSP_COUNT;
++ }
++
++ for (i = 0; i < size; i++) {
++ struct platform_device *new_mcbsp = &omap_mcbsp_devices[i];
++ new_mcbsp->name = "omap-mcbsp";
++ new_mcbsp->id = i + 1;
++ new_mcbsp->dev.platform_data = &config[i];
++ }
++ mcbsps_configured = size;
++}
++
++static void __init omap_init_mcbsp(void)
++{
++ int i;
++
++ for (i = 0; i < mcbsps_configured; i++)
++ platform_device_register(&omap_mcbsp_devices[i]);
++}
++#else
++void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
++ int size)
++{ }
++
++static inline void __init omap_init_mcbsp(void)
++{ }
++#endif
++
++/*-------------------------------------------------------------------------*/
+
+ #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) \
+ || defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
+@@ -511,6 +555,7 @@ static int __init omap_init_devices(void)
+ */
+ omap_init_dsp();
+ omap_init_kp();
++ omap_init_mcbsp();
+ omap_init_mmc();
+ omap_init_uwire();
+ omap_init_wdt();
+diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
+index 053de31..5536223 100644
+--- a/arch/arm/plat-omap/mcbsp.c
++++ b/arch/arm/plat-omap/mcbsp.c
+@@ -15,6 +15,7 @@
+ #include <linux/module.h>
+ #include <linux/init.h>
+ #include <linux/device.h>
++#include <linux/platform_device.h>
+ #include <linux/wait.h>
+ #include <linux/completion.h>
+ #include <linux/interrupt.h>
+@@ -25,83 +26,53 @@
+ #include <linux/irq.h>
+
+ #include <asm/arch/dma.h>
+-#include <asm/arch/mux.h>
+-#include <asm/arch/irqs.h>
+-#include <asm/arch/dsp_common.h>
+ #include <asm/arch/mcbsp.h>
+
+-#ifdef CONFIG_MCBSP_DEBUG
+-#define DBG(x...) printk(x)
+-#else
+-#define DBG(x...) do { } while (0)
+-#endif
+-
+-struct omap_mcbsp {
+- u32 io_base;
+- u8 id;
+- u8 free;
+- omap_mcbsp_word_length rx_word_length;
+- omap_mcbsp_word_length tx_word_length;
+-
+- omap_mcbsp_io_type_t io_type; /* IRQ or poll */
+- /* IRQ based TX/RX */
+- int rx_irq;
+- int tx_irq;
+-
+- /* DMA stuff */
+- u8 dma_rx_sync;
+- short dma_rx_lch;
+- u8 dma_tx_sync;
+- short dma_tx_lch;
+-
+- /* Completion queues */
+- struct completion tx_irq_completion;
+- struct completion rx_irq_completion;
+- struct completion tx_dma_completion;
+- struct completion rx_dma_completion;
+-
+- /* Protect the field .free, while checking if the mcbsp is in use */
+- spinlock_t lock;
+-};
+-
+ static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
+-#ifdef CONFIG_ARCH_OMAP1
+-static struct clk *mcbsp_dsp_ck;
+-static struct clk *mcbsp_api_ck;
+-static struct clk *mcbsp_dspxor_ck;
+-#endif
+-#ifdef CONFIG_ARCH_OMAP2
+-static struct clk *mcbsp1_ick;
+-static struct clk *mcbsp1_fck;
+-static struct clk *mcbsp2_ick;
+-static struct clk *mcbsp2_fck;
+-#endif
++
++#define omap_mcbsp_check_valid_id(id) (mcbsp[id].pdata && \
++ mcbsp[id].pdata->ops && \
++ mcbsp[id].pdata->ops->check && \
++ (mcbsp[id].pdata->ops->check(id) == 0))
+
+ static void omap_mcbsp_dump_reg(u8 id)
+ {
+- DBG("**** MCBSP%d regs ****\n", mcbsp[id].id);
+- DBG("DRR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
+- DBG("DRR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
+- DBG("DXR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
+- DBG("DXR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
+- DBG("SPCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
+- DBG("SPCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
+- DBG("RCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
+- DBG("RCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
+- DBG("XCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
+- DBG("XCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
+- DBG("SRGR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
+- DBG("SRGR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
+- DBG("PCR0: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
+- DBG("***********************\n");
++ dev_dbg(mcbsp[id].dev, "**** McBSP%d regs ****\n", mcbsp[id].id);
++ dev_dbg(mcbsp[id].dev, "DRR2: 0x%04x\n",
++ OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
++ dev_dbg(mcbsp[id].dev, "DRR1: 0x%04x\n",
++ OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
++ dev_dbg(mcbsp[id].dev, "DXR2: 0x%04x\n",
++ OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
++ dev_dbg(mcbsp[id].dev, "DXR1: 0x%04x\n",
++ OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
++ dev_dbg(mcbsp[id].dev, "SPCR2: 0x%04x\n",
++ OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
++ dev_dbg(mcbsp[id].dev, "SPCR1: 0x%04x\n",
++ OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
++ dev_dbg(mcbsp[id].dev, "RCR2: 0x%04x\n",
++ OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
++ dev_dbg(mcbsp[id].dev, "RCR1: 0x%04x\n",
++ OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
++ dev_dbg(mcbsp[id].dev, "XCR2: 0x%04x\n",
++ OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
++ dev_dbg(mcbsp[id].dev, "XCR1: 0x%04x\n",
++ OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
++ dev_dbg(mcbsp[id].dev, "SRGR2: 0x%04x\n",
++ OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
++ dev_dbg(mcbsp[id].dev, "SRGR1: 0x%04x\n",
++ OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
++ dev_dbg(mcbsp[id].dev, "PCR0: 0x%04x\n",
++ OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
++ dev_dbg(mcbsp[id].dev, "***********************\n");
+ }
+
+ static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
+ {
+ struct omap_mcbsp *mcbsp_tx = dev_id;
+
+- DBG("TX IRQ callback : 0x%x\n",
+- OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
++ dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n",
++ OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
+
+ complete(&mcbsp_tx->tx_irq_completion);
+
+@@ -112,8 +83,8 @@ static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
+ {
+ struct omap_mcbsp *mcbsp_rx = dev_id;
+
+- DBG("RX IRQ callback : 0x%x\n",
+- OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
++ dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n",
++ OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
+
+ complete(&mcbsp_rx->rx_irq_completion);
+
+@@ -124,8 +95,8 @@ static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
+ {
+ struct omap_mcbsp *mcbsp_dma_tx = data;
+
+- DBG("TX DMA callback : 0x%x\n",
+- OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
++ dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
++ OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
+
+ /* We can free the channels */
+ omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
+@@ -138,8 +109,8 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
+ {
+ struct omap_mcbsp *mcbsp_dma_rx = data;
+
+- DBG("RX DMA callback : 0x%x\n",
+- OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
++ dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
++ OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
+
+ /* We can free the channels */
+ omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
+@@ -156,9 +127,16 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
+ */
+ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
+ {
+- u32 io_base = mcbsp[id].io_base;
++ u32 io_base;
++
++ if (!omap_mcbsp_check_valid_id(id)) {
++ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
++ return;
++ }
+
+- DBG("OMAP-McBSP: McBSP%d io_base: 0x%8x\n", id + 1, io_base);
++ io_base = mcbsp[id].io_base;
++ dev_dbg(mcbsp[id].dev, "Configuring McBSP%d io_base: 0x%8x\n",
++ mcbsp[id].id, io_base);
+
+ /* We write the given config */
+ OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
+@@ -175,97 +153,22 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
+ }
+ EXPORT_SYMBOL(omap_mcbsp_config);
+
+-static int omap_mcbsp_check(unsigned int id)
+-{
+- if (cpu_is_omap730()) {
+- if (id > OMAP_MAX_MCBSP_COUNT - 1) {
+- printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",
+- id + 1);
+- return -1;
+- }
+- return 0;
+- }
+-
+- if (cpu_is_omap15xx() || cpu_is_omap16xx() || cpu_is_omap24xx()) {
+- if (id > OMAP_MAX_MCBSP_COUNT) {
+- printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",
+- id + 1);
+- return -1;
+- }
+- return 0;
+- }
+-
+- return -1;
+-}
+-
+-#ifdef CONFIG_ARCH_OMAP1
+-static void omap_mcbsp_dsp_request(void)
+-{
+- if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
+- int ret;
+-
+- ret = omap_dsp_request_mem();
+- if (ret < 0) {
+- printk(KERN_ERR "Could not get dsp memory: %i\n", ret);
+- return;
+- }
+-
+- clk_enable(mcbsp_dsp_ck);
+- clk_enable(mcbsp_api_ck);
+-
+- /* enable 12MHz clock to mcbsp 1 & 3 */
+- clk_enable(mcbsp_dspxor_ck);
+-
+- /*
+- * DSP external peripheral reset
+- * FIXME: This should be moved to dsp code
+- */
+- __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1,
+- DSP_RSTCT2);
+- }
+-}
+-
+-static void omap_mcbsp_dsp_free(void)
+-{
+- if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
+- omap_dsp_release_mem();
+- clk_disable(mcbsp_dspxor_ck);
+- clk_disable(mcbsp_dsp_ck);
+- clk_disable(mcbsp_api_ck);
+- }
+-}
+-#endif
+-
+-#ifdef CONFIG_ARCH_OMAP2
+-static void omap2_mcbsp2_mux_setup(void)
+-{
+- if (cpu_is_omap2420()) {
+- omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
+- omap_cfg_reg(R14_24XX_MCBSP2_FSX);
+- omap_cfg_reg(W15_24XX_MCBSP2_DR);
+- omap_cfg_reg(V15_24XX_MCBSP2_DX);
+- omap_cfg_reg(V14_24XX_GPIO117);
+- }
+- /*
+- * Need to add MUX settings for OMAP 2430 SDP
+- */
+-}
+-#endif
+-
+ /*
+ * We can choose between IRQ based or polled IO.
+ * This needs to be called before omap_mcbsp_request().
+ */
+ int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
+ {
+- if (omap_mcbsp_check(id) < 0)
+- return -EINVAL;
++ if (!omap_mcbsp_check_valid_id(id)) {
++ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
++ return -ENODEV;
++ }
+
+ spin_lock(&mcbsp[id].lock);
+
+ if (!mcbsp[id].free) {
+- printk(KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n",
+- id + 1);
++ dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n",
++ mcbsp[id].id);
+ spin_unlock(&mcbsp[id].lock);
+ return -EINVAL;
+ }
+@@ -282,34 +185,20 @@ int omap_mcbsp_request(unsigned int id)
+ {
+ int err;
+
+- if (omap_mcbsp_check(id) < 0)
+- return -EINVAL;
+-
+-#ifdef CONFIG_ARCH_OMAP1
+- /*
+- * On 1510, 1610 and 1710, McBSP1 and McBSP3
+- * are DSP public peripherals.
+- */
+- if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
+- omap_mcbsp_dsp_request();
+-#endif
+-
+-#ifdef CONFIG_ARCH_OMAP2
+- if (cpu_is_omap24xx()) {
+- if (id == OMAP_MCBSP1) {
+- clk_enable(mcbsp1_ick);
+- clk_enable(mcbsp1_fck);
+- } else {
+- clk_enable(mcbsp2_ick);
+- clk_enable(mcbsp2_fck);
+- }
++ if (!omap_mcbsp_check_valid_id(id)) {
++ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
++ return -ENODEV;
+ }
+-#endif
++
++ if (mcbsp[id].pdata->ops->request)
++ mcbsp[id].pdata->ops->request(id);
++
++ mcbsp_clk_enable(&mcbsp[id]);
+
+ spin_lock(&mcbsp[id].lock);
+ if (!mcbsp[id].free) {
+- printk(KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n",
+- id + 1);
++ dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n",
++ mcbsp[id].id);
+ spin_unlock(&mcbsp[id].lock);
+ return -1;
+ }
+@@ -322,9 +211,9 @@ int omap_mcbsp_request(unsigned int id)
+ err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler,
+ 0, "McBSP", (void *) (&mcbsp[id]));
+ if (err != 0) {
+- printk(KERN_ERR "OMAP-McBSP: Unable to "
+- "request TX IRQ %d for McBSP%d\n",
+- mcbsp[id].tx_irq, mcbsp[id].id);
++ dev_err(mcbsp[id].dev, "Unable to request TX IRQ %d "
++ "for McBSP%d\n", mcbsp[id].tx_irq,
++ mcbsp[id].id);
+ return err;
+ }
+
+@@ -333,9 +222,9 @@ int omap_mcbsp_request(unsigned int id)
+ err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler,
+ 0, "McBSP", (void *) (&mcbsp[id]));
+ if (err != 0) {
+- printk(KERN_ERR "OMAP-McBSP: Unable to "
+- "request RX IRQ %d for McBSP%d\n",
+- mcbsp[id].rx_irq, mcbsp[id].id);
++ dev_err(mcbsp[id].dev, "Unable to request RX IRQ %d "
++ "for McBSP%d\n", mcbsp[id].rx_irq,
++ mcbsp[id].id);
+ free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
+ return err;
+ }
+@@ -349,32 +238,20 @@ EXPORT_SYMBOL(omap_mcbsp_request);
+
+ void omap_mcbsp_free(unsigned int id)
+ {
+- if (omap_mcbsp_check(id) < 0)
++ if (!omap_mcbsp_check_valid_id(id)) {
++ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+ return;
+-
+-#ifdef CONFIG_ARCH_OMAP1
+- if (cpu_class_is_omap1()) {
+- if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
+- omap_mcbsp_dsp_free();
+ }
+-#endif
+-
+-#ifdef CONFIG_ARCH_OMAP2
+- if (cpu_is_omap24xx()) {
+- if (id == OMAP_MCBSP1) {
+- clk_disable(mcbsp1_ick);
+- clk_disable(mcbsp1_fck);
+- } else {
+- clk_disable(mcbsp2_ick);
+- clk_disable(mcbsp2_fck);
+- }
+- }
+-#endif
++
++ if (mcbsp[id].pdata->ops->free)
++ mcbsp[id].pdata->ops->free(id);
++
++ mcbsp_clk_disable(&mcbsp[id]);
+
+ spin_lock(&mcbsp[id].lock);
+ if (mcbsp[id].free) {
+- printk(KERN_ERR "OMAP-McBSP: McBSP%d was not reserved\n",
+- id + 1);
++ dev_err(mcbsp[id].dev, "McBSP%d was not reserved\n",
++ mcbsp[id].id);
+ spin_unlock(&mcbsp[id].lock);
+ return;
+ }
+@@ -400,8 +277,10 @@ void omap_mcbsp_start(unsigned int id)
+ u32 io_base;
+ u16 w;
+
+- if (omap_mcbsp_check(id) < 0)
++ if (!omap_mcbsp_check_valid_id(id)) {
++ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+ return;
++ }
+
+ io_base = mcbsp[id].io_base;
+
+@@ -435,8 +314,10 @@ void omap_mcbsp_stop(unsigned int id)
+ u32 io_base;
+ u16 w;
+
+- if (omap_mcbsp_check(id) < 0)
++ if (!omap_mcbsp_check_valid_id(id)) {
++ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+ return;
++ }
+
+ io_base = mcbsp[id].io_base;
+
+@@ -457,7 +338,14 @@ EXPORT_SYMBOL(omap_mcbsp_stop);
+ /* polled mcbsp i/o operations */
+ int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
+ {
+- u32 base = mcbsp[id].io_base;
++ u32 base;
++
++ if (!omap_mcbsp_check_valid_id(id)) {
++ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
++ return -ENODEV;
++ }
++
++ base = mcbsp[id].io_base;
+ writew(buf, base + OMAP_MCBSP_REG_DXR1);
+ /* if frame sync error - clear the error */
+ if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
+@@ -479,8 +367,8 @@ int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
+ (XRST),
+ base + OMAP_MCBSP_REG_SPCR2);
+ udelay(10);
+- printk(KERN_ERR
+- " Could not write to McBSP Register\n");
++ dev_err(mcbsp[id].dev, "Could not write to"
++ " McBSP%d Register\n", mcbsp[id].id);
+ return -2;
+ }
+ }
+@@ -492,7 +380,14 @@ EXPORT_SYMBOL(omap_mcbsp_pollwrite);
+
+ int omap_mcbsp_pollread(unsigned int id, u16 *buf)
+ {
+- u32 base = mcbsp[id].io_base;
++ u32 base;
++
++ if (!omap_mcbsp_check_valid_id(id)) {
++ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
++ return -ENODEV;
++ }
++
++ base = mcbsp[id].io_base;
+ /* if frame sync error - clear the error */
+ if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
+ /* clear error */
+@@ -513,8 +408,8 @@ int omap_mcbsp_pollread(unsigned int id, u16 *buf)
+ (RRST),
+ base + OMAP_MCBSP_REG_SPCR1);
+ udelay(10);
+- printk(KERN_ERR
+- " Could not read from McBSP Register\n");
++ dev_err(mcbsp[id].dev, "Could not read from"
++ " McBSP%d Register\n", mcbsp[id].id);
+ return -2;
+ }
+ }
+@@ -531,12 +426,15 @@ EXPORT_SYMBOL(omap_mcbsp_pollread);
+ void omap_mcbsp_xmit_word(unsigned int id, u32 word)
+ {
+ u32 io_base;
+- omap_mcbsp_word_length word_length = mcbsp[id].tx_word_length;
++ omap_mcbsp_word_length word_length;
+
+- if (omap_mcbsp_check(id) < 0)
++ if (!omap_mcbsp_check_valid_id(id)) {
++ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+ return;
++ }
+
+ io_base = mcbsp[id].io_base;
++ word_length = mcbsp[id].tx_word_length;
+
+ wait_for_completion(&(mcbsp[id].tx_irq_completion));
+
+@@ -550,11 +448,14 @@ u32 omap_mcbsp_recv_word(unsigned int id)
+ {
+ u32 io_base;
+ u16 word_lsb, word_msb = 0;
+- omap_mcbsp_word_length word_length = mcbsp[id].rx_word_length;
++ omap_mcbsp_word_length word_length;
+
+- if (omap_mcbsp_check(id) < 0)
+- return -EINVAL;
++ if (!omap_mcbsp_check_valid_id(id)) {
++ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
++ return -ENODEV;
++ }
+
++ word_length = mcbsp[id].rx_word_length;
+ io_base = mcbsp[id].io_base;
+
+ wait_for_completion(&(mcbsp[id].rx_irq_completion));
+@@ -569,11 +470,20 @@ EXPORT_SYMBOL(omap_mcbsp_recv_word);
+
+ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
+ {
+- u32 io_base = mcbsp[id].io_base;
+- omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;
+- omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;
++ u32 io_base;
++ omap_mcbsp_word_length tx_word_length;
++ omap_mcbsp_word_length rx_word_length;
+ u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
+
++ if (!omap_mcbsp_check_valid_id(id)) {
++ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
++ return -ENODEV;
++ }
++
++ io_base = mcbsp[id].io_base;
++ tx_word_length = mcbsp[id].tx_word_length;
++ rx_word_length = mcbsp[id].rx_word_length;
++
+ if (tx_word_length != rx_word_length)
+ return -EINVAL;
+
+@@ -587,7 +497,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
+ udelay(10);
+ OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
+ udelay(10);
+- printk(KERN_ERR "McBSP transmitter not ready\n");
++ dev_err(mcbsp[id].dev, "McBSP%d transmitter not "
++ "ready\n", mcbsp[id].id);
+ return -EAGAIN;
+ }
+ }
+@@ -607,7 +518,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
+ udelay(10);
+ OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
+ udelay(10);
+- printk(KERN_ERR "McBSP receiver not ready\n");
++ dev_err(mcbsp[id].dev, "McBSP%d receiver not "
++ "ready\n", mcbsp[id].id);
+ return -EAGAIN;
+ }
+ }
+@@ -623,11 +535,20 @@ EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
+
+ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
+ {
+- u32 io_base = mcbsp[id].io_base, clock_word = 0;
+- omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;
+- omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;
++ u32 io_base, clock_word = 0;
++ omap_mcbsp_word_length tx_word_length;
++ omap_mcbsp_word_length rx_word_length;
+ u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
+
++ if (!omap_mcbsp_check_valid_id(id)) {
++ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
++ return -ENODEV;
++ }
++
++ io_base = mcbsp[id].io_base;
++ tx_word_length = mcbsp[id].tx_word_length;
++ rx_word_length = mcbsp[id].rx_word_length;
++
+ if (tx_word_length != rx_word_length)
+ return -EINVAL;
+
+@@ -641,7 +562,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
+ udelay(10);
+ OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
+ udelay(10);
+- printk(KERN_ERR "McBSP transmitter not ready\n");
++ dev_err(mcbsp[id].dev, "McBSP%d transmitter not "
++ "ready\n", mcbsp[id].id);
+ return -EAGAIN;
+ }
+ }
+@@ -661,7 +583,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
+ udelay(10);
+ OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
+ udelay(10);
+- printk(KERN_ERR "McBSP receiver not ready\n");
++ dev_err(mcbsp[id].dev, "McBSP%d receiver not "
++ "ready\n", mcbsp[id].id);
+ return -EAGAIN;
+ }
+ }
+@@ -692,20 +615,24 @@ int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
+ int dest_port = 0;
+ int sync_dev = 0;
+
+- if (omap_mcbsp_check(id) < 0)
+- return -EINVAL;
++ if (!omap_mcbsp_check_valid_id(id)) {
++ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
++ return -ENODEV;
++ }
+
+ if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX",
+ omap_mcbsp_tx_dma_callback,
+ &mcbsp[id],
+ &dma_tx_ch)) {
+- printk(KERN_ERR "OMAP-McBSP: Unable to request DMA channel for"
+- " McBSP%d TX. Trying IRQ based TX\n", id + 1);
++ dev_err(mcbsp[id].dev, " Unable to request DMA channel for "
++ "McBSP%d TX. Trying IRQ based TX\n",
++ mcbsp[id].id);
+ return -EAGAIN;
+ }
+ mcbsp[id].dma_tx_lch = dma_tx_ch;
+
+- DBG("TX DMA on channel %d\n", dma_tx_ch);
++ dev_err(mcbsp[id].dev, "McBSP%d TX DMA on channel %d\n", mcbsp[id].id,
++ dma_tx_ch);
+
+ init_completion(&(mcbsp[id].tx_dma_completion));
+
+@@ -713,7 +640,7 @@ int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
+ src_port = OMAP_DMA_PORT_TIPB;
+ dest_port = OMAP_DMA_PORT_EMIFF;
+ }
+- if (cpu_is_omap24xx())
++ if (cpu_class_is_omap2())
+ sync_dev = mcbsp[id].dma_tx_sync;
+
+ omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
+@@ -749,20 +676,24 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
+ int dest_port = 0;
+ int sync_dev = 0;
+
+- if (omap_mcbsp_check(id) < 0)
+- return -EINVAL;
++ if (!omap_mcbsp_check_valid_id(id)) {
++ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
++ return -ENODEV;
++ }
+
+ if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX",
+ omap_mcbsp_rx_dma_callback,
+ &mcbsp[id],
+ &dma_rx_ch)) {
+- printk(KERN_ERR "Unable to request DMA channel for McBSP%d RX."
+- " Trying IRQ based RX\n", id + 1);
++ dev_err(mcbsp[id].dev, "Unable to request DMA channel for "
++ "McBSP%d RX. Trying IRQ based RX\n",
++ mcbsp[id].id);
+ return -EAGAIN;
+ }
+ mcbsp[id].dma_rx_lch = dma_rx_ch;
+
+- DBG("RX DMA on channel %d\n", dma_rx_ch);
++ dev_err(mcbsp[id].dev, "McBSP%d RX DMA on channel %d\n", mcbsp[id].id,
++ dma_rx_ch);
+
+ init_completion(&(mcbsp[id].rx_dma_completion));
+
+@@ -770,7 +701,7 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
+ src_port = OMAP_DMA_PORT_TIPB;
+ dest_port = OMAP_DMA_PORT_EMIFF;
+ }
+- if (cpu_is_omap24xx())
++ if (cpu_class_is_omap2())
+ sync_dev = mcbsp[id].dma_rx_sync;
+
+ omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
+@@ -809,8 +740,10 @@ void omap_mcbsp_set_spi_mode(unsigned int id,
+ {
+ struct omap_mcbsp_reg_cfg mcbsp_cfg;
+
+- if (omap_mcbsp_check(id) < 0)
++ if (!omap_mcbsp_check_valid_id(id)) {
++ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+ return;
++ }
+
+ memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
+
+@@ -871,182 +804,91 @@ EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
+ * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
+ * 730 has only 2 McBSP, and both of them are MPU peripherals.
+ */
+-struct omap_mcbsp_info {
+- u32 virt_base;
+- u8 dma_rx_sync, dma_tx_sync;
+- u16 rx_irq, tx_irq;
+-};
++static int __init omap_mcbsp_probe(struct platform_device *pdev)
++{
++ struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
++ int id = pdev->id - 1;
++ int ret = 0;
++ int i;
+
+-#ifdef CONFIG_ARCH_OMAP730
+-static const struct omap_mcbsp_info mcbsp_730[] = {
+- [0] = { .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
+- .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
+- .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
+- .rx_irq = INT_730_McBSP1RX,
+- .tx_irq = INT_730_McBSP1TX },
+- [1] = { .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
+- .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
+- .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
+- .rx_irq = INT_730_McBSP2RX,
+- .tx_irq = INT_730_McBSP2TX },
+-};
+-#endif
+-
+-#ifdef CONFIG_ARCH_OMAP15XX
+-static const struct omap_mcbsp_info mcbsp_1510[] = {
+- [0] = { .virt_base = OMAP1510_MCBSP1_BASE,
+- .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
+- .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
+- .rx_irq = INT_McBSP1RX,
+- .tx_irq = INT_McBSP1TX },
+- [1] = { .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
+- .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
+- .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
+- .rx_irq = INT_1510_SPI_RX,
+- .tx_irq = INT_1510_SPI_TX },
+- [2] = { .virt_base = OMAP1510_MCBSP3_BASE,
+- .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
+- .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
+- .rx_irq = INT_McBSP3RX,
+- .tx_irq = INT_McBSP3TX },
+-};
+-#endif
+-
+-#if defined(CONFIG_ARCH_OMAP16XX)
+-static const struct omap_mcbsp_info mcbsp_1610[] = {
+- [0] = { .virt_base = OMAP1610_MCBSP1_BASE,
+- .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
+- .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
+- .rx_irq = INT_McBSP1RX,
+- .tx_irq = INT_McBSP1TX },
+- [1] = { .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
+- .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
+- .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
+- .rx_irq = INT_1610_McBSP2_RX,
+- .tx_irq = INT_1610_McBSP2_TX },
+- [2] = { .virt_base = OMAP1610_MCBSP3_BASE,
+- .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
+- .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
+- .rx_irq = INT_McBSP3RX,
+- .tx_irq = INT_McBSP3TX },
+-};
+-#endif
+-
+-#if defined(CONFIG_ARCH_OMAP24XX)
+-static const struct omap_mcbsp_info mcbsp_24xx[] = {
+- [0] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
+- .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
+- .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
+- .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
+- .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
+- },
+- [1] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
+- .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
+- .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
+- .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
+- .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
+- },
+-};
+-#endif
++ if (!pdata) {
++ dev_err(&pdev->dev, "McBSP device initialized without"
++ "platform data\n");
++ ret = -EINVAL;
++ goto exit;
++ }
+
+-static int __init omap_mcbsp_init(void)
++ dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
++
++ if (id >= OMAP_MAX_MCBSP_COUNT) {
++ dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
++ ret = -EINVAL;
++ goto exit;
++ }
++
++ spin_lock_init(&mcbsp[id].lock);
++ mcbsp[id].id = id + 1;
++ mcbsp[id].free = 1;
++ mcbsp[id].dma_tx_lch = -1;
++ mcbsp[id].dma_rx_lch = -1;
++
++ mcbsp[id].io_base = pdata->virt_base;
++ /* Default I/O is IRQ based */
++ mcbsp[id].io_type = OMAP_MCBSP_IRQ_IO;
++ mcbsp[id].tx_irq = pdata->tx_irq;
++ mcbsp[id].rx_irq = pdata->rx_irq;
++ mcbsp[id].dma_rx_sync = pdata->dma_rx_sync;
++ mcbsp[id].dma_tx_sync = pdata->dma_tx_sync;
++
++ mcbsp[id].nr_clocks = ARRAY_SIZE(pdata->clocks);
++ for (i = 0; i < ARRAY_SIZE(pdata->clocks); i++)
++ mcbsp[id].clocks[i] = clk_get(&pdev->dev, pdata->clocks[i]);
++
++ mcbsp[id].pdata = pdata;
++ mcbsp[id].dev = &pdev->dev;
++ platform_set_drvdata(pdev, &mcbsp[id]);
++
++exit:
++ return ret;
++}
++
++static int omap_mcbsp_remove(struct platform_device *pdev)
+ {
+- int mcbsp_count = 0, i;
+- static const struct omap_mcbsp_info *mcbsp_info;
++ struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
+
+- printk(KERN_INFO "Initializing OMAP McBSP system\n");
++ platform_set_drvdata(pdev, NULL);
++ if (mcbsp) {
++ int i;
+
+-#ifdef CONFIG_ARCH_OMAP1
+- mcbsp_dsp_ck = clk_get(0, "dsp_ck");
+- if (IS_ERR(mcbsp_dsp_ck)) {
+- printk(KERN_ERR "mcbsp: could not acquire dsp_ck handle.\n");
+- return PTR_ERR(mcbsp_dsp_ck);
+- }
+- mcbsp_api_ck = clk_get(0, "api_ck");
+- if (IS_ERR(mcbsp_api_ck)) {
+- printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n");
+- return PTR_ERR(mcbsp_api_ck);
+- }
+- mcbsp_dspxor_ck = clk_get(0, "dspxor_ck");
+- if (IS_ERR(mcbsp_dspxor_ck)) {
+- printk(KERN_ERR "mcbsp: could not acquire dspxor_ck handle.\n");
+- return PTR_ERR(mcbsp_dspxor_ck);
+- }
+-#endif
+-#ifdef CONFIG_ARCH_OMAP2
+- mcbsp1_ick = clk_get(0, "mcbsp1_ick");
+- if (IS_ERR(mcbsp1_ick)) {
+- printk(KERN_ERR "mcbsp: could not acquire "
+- "mcbsp1_ick handle.\n");
+- return PTR_ERR(mcbsp1_ick);
+- }
+- mcbsp1_fck = clk_get(0, "mcbsp1_fck");
+- if (IS_ERR(mcbsp1_fck)) {
+- printk(KERN_ERR "mcbsp: could not acquire "
+- "mcbsp1_fck handle.\n");
+- return PTR_ERR(mcbsp1_fck);
+- }
+- mcbsp2_ick = clk_get(0, "mcbsp2_ick");
+- if (IS_ERR(mcbsp2_ick)) {
+- printk(KERN_ERR "mcbsp: could not acquire "
+- "mcbsp2_ick handle.\n");
+- return PTR_ERR(mcbsp2_ick);
+- }
+- mcbsp2_fck = clk_get(0, "mcbsp2_fck");
+- if (IS_ERR(mcbsp2_fck)) {
+- printk(KERN_ERR "mcbsp: could not acquire "
+- "mcbsp2_fck handle.\n");
+- return PTR_ERR(mcbsp2_fck);
+- }
+-#endif
++ if (mcbsp->pdata && mcbsp->pdata->ops &&
++ mcbsp->pdata->ops->free)
++ mcbsp->pdata->ops->free(mcbsp->id);
+
+-#ifdef CONFIG_ARCH_OMAP730
+- if (cpu_is_omap730()) {
+- mcbsp_info = mcbsp_730;
+- mcbsp_count = ARRAY_SIZE(mcbsp_730);
+- }
+-#endif
+-#ifdef CONFIG_ARCH_OMAP15XX
+- if (cpu_is_omap15xx()) {
+- mcbsp_info = mcbsp_1510;
+- mcbsp_count = ARRAY_SIZE(mcbsp_1510);
+- }
+-#endif
+-#if defined(CONFIG_ARCH_OMAP16XX)
+- if (cpu_is_omap16xx()) {
+- mcbsp_info = mcbsp_1610;
+- mcbsp_count = ARRAY_SIZE(mcbsp_1610);
+- }
+-#endif
+-#if defined(CONFIG_ARCH_OMAP24XX)
+- if (cpu_is_omap24xx()) {
+- mcbsp_info = mcbsp_24xx;
+- mcbsp_count = ARRAY_SIZE(mcbsp_24xx);
+- omap2_mcbsp2_mux_setup();
+- }
+-#endif
+- for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {
+- if (i >= mcbsp_count) {
+- mcbsp[i].io_base = 0;
+- mcbsp[i].free = 0;
+- continue;
+- }
+- mcbsp[i].id = i + 1;
+- mcbsp[i].free = 1;
+- mcbsp[i].dma_tx_lch = -1;
+- mcbsp[i].dma_rx_lch = -1;
+-
+- mcbsp[i].io_base = mcbsp_info[i].virt_base;
+- /* Default I/O is IRQ based */
+- mcbsp[i].io_type = OMAP_MCBSP_IRQ_IO;
+- mcbsp[i].tx_irq = mcbsp_info[i].tx_irq;
+- mcbsp[i].rx_irq = mcbsp_info[i].rx_irq;
+- mcbsp[i].dma_rx_sync = mcbsp_info[i].dma_rx_sync;
+- mcbsp[i].dma_tx_sync = mcbsp_info[i].dma_tx_sync;
+- spin_lock_init(&mcbsp[i].lock);
++ mcbsp_clk_disable(mcbsp);
++ mcbsp_clk_put(mcbsp);
++
++ for (i = 0; i < mcbsp->nr_clocks; i++)
++ mcbsp->clocks[i] = NULL;
++
++ mcbsp->free = 0;
++ mcbsp->dev = NULL;
+ }
+
+ return 0;
+ }
+
+-arch_initcall(omap_mcbsp_init);
++static struct platform_driver omap_mcbsp_driver = {
++ .probe = omap_mcbsp_probe,
++ .remove = omap_mcbsp_remove,
++ .driver = {
++ .name = "omap-mcbsp",
++ },
++};
++
++int __init omap_mcbsp_init(void)
++{
++ /* Register the McBSP driver */
++ return platform_driver_register(&omap_mcbsp_driver);
++}
++
++
+diff --git a/include/asm-arm/arch-omap/mcbsp.h b/include/asm-arm/arch-omap/mcbsp.h
+index b53c3b2..aa47421 100644
+--- a/include/asm-arm/arch-omap/mcbsp.h
++++ b/include/asm-arm/arch-omap/mcbsp.h
+@@ -24,7 +24,11 @@
+ #ifndef __ASM_ARCH_OMAP_MCBSP_H
+ #define __ASM_ARCH_OMAP_MCBSP_H
+
++#include <linux/completion.h>
++#include <linux/spinlock.h>
++
+ #include <asm/hardware.h>
++#include <asm/arch/clock.h>
+
+ #define OMAP730_MCBSP1_BASE 0xfffb1000
+ #define OMAP730_MCBSP2_BASE 0xfffb1800
+@@ -40,6 +44,9 @@
+ #define OMAP24XX_MCBSP1_BASE 0x48074000
+ #define OMAP24XX_MCBSP2_BASE 0x48076000
+
++#define OMAP34XX_MCBSP1_BASE 0x48074000
++#define OMAP34XX_MCBSP2_BASE 0x49022000
++
+ #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
+
+ #define OMAP_MCBSP_REG_DRR2 0x00
+@@ -74,7 +81,8 @@
+ #define OMAP_MCBSP_REG_XCERG 0x3A
+ #define OMAP_MCBSP_REG_XCERH 0x3C
+
+-#define OMAP_MAX_MCBSP_COUNT 3
++#define OMAP_MAX_MCBSP_COUNT 3
++#define MAX_MCBSP_CLOCKS 3
+
+ #define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
+ #define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
+@@ -117,7 +125,8 @@
+ #define OMAP_MCBSP_REG_XCERG 0x74
+ #define OMAP_MCBSP_REG_XCERH 0x78
+
+-#define OMAP_MAX_MCBSP_COUNT 2
++#define OMAP_MAX_MCBSP_COUNT 2
++#define MAX_MCBSP_CLOCKS 2
+
+ #define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
+ #define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
+@@ -298,6 +307,66 @@ struct omap_mcbsp_spi_cfg {
+ omap_mcbsp_word_length word_length;
+ };
+
++/* Platform specific configuration */
++struct omap_mcbsp_ops {
++ void (*request)(unsigned int);
++ void (*free)(unsigned int);
++ int (*check)(unsigned int);
++};
++
++struct omap_mcbsp_platform_data {
++ u32 virt_base;
++ u8 dma_rx_sync, dma_tx_sync;
++ u16 rx_irq, tx_irq;
++ struct omap_mcbsp_ops *ops;
++ char const *clocks[MAX_MCBSP_CLOCKS];
++};
++
++struct omap_mcbsp {
++ struct device *dev;
++ u32 io_base;
++ u8 id;
++ u8 free;
++ omap_mcbsp_word_length rx_word_length;
++ omap_mcbsp_word_length tx_word_length;
++
++ omap_mcbsp_io_type_t io_type; /* IRQ or poll */
++ /* IRQ based TX/RX */
++ int rx_irq;
++ int tx_irq;
++
++ /* DMA stuff */
++ u8 dma_rx_sync;
++ short dma_rx_lch;
++ u8 dma_tx_sync;
++ short dma_tx_lch;
++
++ /* Completion queues */
++ struct completion tx_irq_completion;
++ struct completion rx_irq_completion;
++ struct completion tx_dma_completion;
++ struct completion rx_dma_completion;
++
++ /* Protect the field .free, while checking if the mcbsp is in use */
++ spinlock_t lock;
++ struct omap_mcbsp_platform_data *pdata;
++ int nr_clocks;
++ struct clk *clocks[MAX_MCBSP_CLOCKS];
++};
++
++#define __mcbsp_clk_op(mcbsp, op) \
++ do { \
++ int i; \
++ for (i = 0; i < mcbsp->nr_clocks; i++) \
++ clk_##op(mcbsp->clocks[i]); \
++ } while (0)
++#define mcbsp_clk_enable(mcbsp) __mcbsp_clk_op((mcbsp), enable)
++#define mcbsp_clk_disable(mcbsp) __mcbsp_clk_op((mcbsp), disable)
++#define mcbsp_clk_put(mcbsp) __mcbsp_clk_op((mcbsp), put)
++
++int omap_mcbsp_init(void);
++void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
++ int size);
+ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
+ int omap_mcbsp_request(unsigned int id);
+ void omap_mcbsp_free(unsigned int id);
+--
+1.5.5.1.67.gbdb8.dirty
+
+--
+To unsubscribe from this list: send the line "unsubscribe linux-omap" in
+the body of a message to majordomo@vger.kernel.org
+More majordomo info at http://vger.kernel.org/majordomo-info.html
+
diff --git a/packages/linux/linux-omap2-git/beagleboard/00002-mcbsp-omap1.patch b/packages/linux/linux-omap2-git/beagleboard/00002-mcbsp-omap1.patch new file mode 100644 index 0000000000..76246a9fae --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/00002-mcbsp-omap1.patch @@ -0,0 +1,204 @@ +From: Eduardo Valentin <eduardo.valentin@indt.org.br>
+
+This patch adds support for mach-omap1 based on current
+mcbsp platform driver.
+
+Signed-off-by: Eduardo Valentin <eduardo.valentin@indt.org.br>
+---
+ arch/arm/mach-omap1/Makefile | 2 +
+ arch/arm/mach-omap1/mcbsp.c | 165 ++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 167 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/mach-omap1/mcbsp.c
+
+diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
+index 6ebf23b..09246a7 100644
+--- a/arch/arm/mach-omap1/Makefile
++++ b/arch/arm/mach-omap1/Makefile
+@@ -5,6 +5,8 @@
+ # Common support
+ obj-y := io.o id.o clock.o irq.o mux.o serial.o devices.o
+
++obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
++
+ obj-$(CONFIG_OMAP_MPU_TIMER) += time.o
+ obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o
+
+diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
+new file mode 100644
+index 0000000..f30624a
+--- /dev/null
++++ b/arch/arm/mach-omap1/mcbsp.c
+@@ -0,0 +1,165 @@
++/*
++ * linux/arch/arm/mach-omap1/mcbsp.c
++ *
++ * Copyright (C) 2008 Instituto Nokia de Tecnologia
++ * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * Multichannel mode not supported.
++ */
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/io.h>
++
++#include <asm/arch/dma.h>
++#include <asm/arch/mux.h>
++#include <asm/arch/cpu.h>
++#include <asm/arch/mcbsp.h>
++#include <asm/arch/dsp_common.h>
++
++#define DPS_RSTCT2_PER_EN (1 << 0)
++#define DSP_RSTCT2_WD_PER_EN (1 << 1)
++
++static int omap1_mcbsp_check(unsigned int id)
++{
++ /* REVISIT: Check correctly for number of registered McBSPs */
++ if (cpu_is_omap730()) {
++ if (id > OMAP_MAX_MCBSP_COUNT - 2) {
++ printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",
++ id + 1);
++ return -ENODEV;
++ }
++ return 0;
++ }
++
++ if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
++ if (id > OMAP_MAX_MCBSP_COUNT - 1) {
++ printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",
++ id + 1);
++ return -ENODEV;
++ }
++ return 0;
++ }
++
++ return -ENODEV;
++}
++
++static void omap1_mcbsp_request(unsigned int id)
++{
++ /*
++ * On 1510, 1610 and 1710, McBSP1 and McBSP3
++ * are DSP public peripherals.
++ */
++ if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
++ omap_dsp_request_mem();
++ /*
++ * DSP external peripheral reset
++ * FIXME: This should be moved to dsp code
++ */
++ __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN |
++ DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2);
++ }
++}
++
++static void omap1_mcbsp_free(unsigned int id)
++{
++ if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
++ omap_dsp_release_mem();
++}
++
++static struct omap_mcbsp_ops omap1_mcbsp_ops = {
++ .check = omap1_mcbsp_check,
++ .request = omap1_mcbsp_request,
++ .free = omap1_mcbsp_free,
++};
++
++static struct omap_mcbsp_platform_data omap1_mcbsp_pdata[] = {
++#ifdef CONFIG_ARCH_OMAP730
++ {
++ .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
++ .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
++ .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
++ .rx_irq = INT_730_McBSP1RX,
++ .tx_irq = INT_730_McBSP1TX,
++ .ops = &omap1_mcbsp_ops,
++ },
++ {
++ .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
++ .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
++ .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
++ .rx_irq = INT_730_McBSP2RX,
++ .tx_irq = INT_730_McBSP2TX
++ .ops = &omap1_mcbsp_ops,
++ },
++#endif
++#ifdef CONFIG_ARCH_OMAP15XX
++ {
++ .virt_base = OMAP1510_MCBSP1_BASE,
++ .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
++ .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
++ .rx_irq = INT_McBSP1RX,
++ .tx_irq = INT_McBSP1TX,
++ .ops = &omap1_mcbsp_ops,
++ .clocks = { "dsp_ck", "api_ck", "dspxor_ck" },
++ },
++ {
++ .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
++ .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
++ .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
++ .rx_irq = INT_1510_SPI_RX,
++ .tx_irq = INT_1510_SPI_TX,
++ .ops = &omap1_mcbsp_ops,
++ },
++ {
++ .virt_base = OMAP1510_MCBSP3_BASE,
++ .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
++ .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
++ .rx_irq = INT_McBSP3RX,
++ .tx_irq = INT_McBSP3TX,
++ .ops = &omap1_mcbsp_ops,
++ .clocks = { "dsp_ck", "api_ck", "dspxor_ck" },
++ },
++#endif
++#ifdef CONFIG_ARCH_OMAP16XX
++ {
++ .virt_base = OMAP1610_MCBSP1_BASE,
++ .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
++ .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
++ .rx_irq = INT_McBSP1RX,
++ .tx_irq = INT_McBSP1TX,
++ .ops = &omap1_mcbsp_ops,
++ .clocks = { "dsp_ck", "api_ck", "dspxor_ck" },
++ },
++ {
++ .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
++ .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
++ .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
++ .rx_irq = INT_1610_McBSP2_RX,
++ .tx_irq = INT_1610_McBSP2_TX,
++ .ops = &omap1_mcbsp_ops,
++ },
++ {
++ .virt_base = OMAP1610_MCBSP3_BASE,
++ .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
++ .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
++ .rx_irq = INT_McBSP3RX,
++ .tx_irq = INT_McBSP3TX,
++ .ops = &omap1_mcbsp_ops,
++ .clocks = { "dsp_ck", "api_ck", "dspxor_ck" },
++ },
++#endif
++};
++#define mcbsp_count ARRAY_SIZE(omap1_mcbsp_pdata)
++
++int __init omap1_mcbsp_init(void)
++{
++ omap_mcbsp_register_board_cfg(omap1_mcbsp_pdata, mcbsp_count);
++
++ return omap_mcbsp_init();
++}
++arch_initcall(omap1_mcbsp_init);
+--
+1.5.5.1.67.gbdb8.dirty
+
+--
+To unsubscribe from this list: send the line "unsubscribe linux-omap" in
+the body of a message to majordomo@vger.kernel.org
+More majordomo info at http://vger.kernel.org/majordomo-info.html
+
diff --git a/packages/linux/linux-omap2-git/beagleboard/00003-mcbsp-omap3-clock.patch b/packages/linux/linux-omap2-git/beagleboard/00003-mcbsp-omap3-clock.patch new file mode 100644 index 0000000000..6d1e7d3f71 --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/00003-mcbsp-omap3-clock.patch @@ -0,0 +1,123 @@ +From: Eduardo Valentin <eduardo.valentin@indt.org.br>
+
+This patch fix the clock definition for mcbsps on clock34xx.h.
+Device identification must be done using .id field, not
+only name field.
+
+Signed-off-by: Eduardo Valentin <eduardo.valentin@indt.org.br>
+---
+ arch/arm/mach-omap2/clock34xx.h | 30 ++++++++++++++++++++----------
+ 1 files changed, 20 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
+index 85afe1e..3fea82e 100644
+--- a/arch/arm/mach-omap2/clock34xx.h
++++ b/arch/arm/mach-omap2/clock34xx.h
+@@ -1480,7 +1480,8 @@ static const struct clksel mcbsp_15_clksel[] = {
+ };
+
+ static struct clk mcbsp5_fck = {
+- .name = "mcbsp5_fck",
++ .name = "mcbsp_fck",
++ .id = 5,
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
+@@ -1493,7 +1494,8 @@ static struct clk mcbsp5_fck = {
+ };
+
+ static struct clk mcbsp1_fck = {
+- .name = "mcbsp1_fck",
++ .name = "mcbsp_fck",
++ .id = 1,
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+ .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
+@@ -1941,7 +1943,8 @@ static struct clk gpt10_ick = {
+ };
+
+ static struct clk mcbsp5_ick = {
+- .name = "mcbsp5_ick",
++ .name = "mcbsp_ick",
++ .id = 5,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
+@@ -1951,7 +1954,8 @@ static struct clk mcbsp5_ick = {
+ };
+
+ static struct clk mcbsp1_ick = {
+- .name = "mcbsp1_ick",
++ .name = "mcbsp_ick",
++ .id = 1,
+ .parent = &core_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+ .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
+@@ -2754,7 +2758,8 @@ static struct clk gpt2_ick = {
+ };
+
+ static struct clk mcbsp2_ick = {
+- .name = "mcbsp2_ick",
++ .name = "mcbsp_ick",
++ .id = 2,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
+@@ -2764,7 +2769,8 @@ static struct clk mcbsp2_ick = {
+ };
+
+ static struct clk mcbsp3_ick = {
+- .name = "mcbsp3_ick",
++ .name = "mcbsp_ick",
++ .id = 3,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
+@@ -2774,7 +2780,8 @@ static struct clk mcbsp3_ick = {
+ };
+
+ static struct clk mcbsp4_ick = {
+- .name = "mcbsp4_ick",
++ .name = "mcbsp_ick",
++ .id = 4,
+ .parent = &per_l4_ick,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+ .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
+@@ -2790,7 +2797,8 @@ static const struct clksel mcbsp_234_clksel[] = {
+ };
+
+ static struct clk mcbsp2_fck = {
+- .name = "mcbsp2_fck",
++ .name = "mcbsp_fck",
++ .id = 2,
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
+@@ -2803,7 +2811,8 @@ static struct clk mcbsp2_fck = {
+ };
+
+ static struct clk mcbsp3_fck = {
+- .name = "mcbsp3_fck",
++ .name = "mcbsp_fck",
++ .id = 3,
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
+@@ -2816,7 +2825,8 @@ static struct clk mcbsp3_fck = {
+ };
+
+ static struct clk mcbsp4_fck = {
+- .name = "mcbsp4_fck",
++ .name = "mcbsp_fck",
++ .id = 4,
+ .init = &omap2_init_clksel_parent,
+ .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+ .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
+--
+1.5.5.1.67.gbdb8.dirty
+
+--
+To unsubscribe from this list: send the line "unsubscribe linux-omap" in
+the body of a message to majordomo@vger.kernel.org
+More majordomo info at http://vger.kernel.org/majordomo-info.html
+
diff --git a/packages/linux/linux-omap2-git/beagleboard/00004-omap2-mcbsp.patch b/packages/linux/linux-omap2-git/beagleboard/00004-omap2-mcbsp.patch new file mode 100644 index 0000000000..f31604d658 --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/00004-omap2-mcbsp.patch @@ -0,0 +1,144 @@ +From: Eduardo Valentin <eduardo.valentin@indt.org.br>
+
+This patch adds support for mach-omap2 based on current
+mcbsp platform driver.
+
+Signed-off-by: Eduardo Valentin <eduardo.valentin@indt.org.br>
+---
+ arch/arm/mach-omap2/Makefile | 2 +
+ arch/arm/mach-omap2/mcbsp.c | 105 ++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 107 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/mcbsp.c
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index 552664c..84fa698 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -7,6 +7,8 @@ obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \
+ devices.o serial.o gpmc.o timer-gp.o powerdomain.o \
+ clockdomain.o
+
++obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
++
+ # Functions loaded to SRAM
+ obj-$(CONFIG_ARCH_OMAP2) += sram24xx.o
+
+diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
+new file mode 100644
+index 0000000..e2ee8f7
+--- /dev/null
++++ b/arch/arm/mach-omap2/mcbsp.c
+@@ -0,0 +1,105 @@
++/*
++ * linux/arch/arm/mach-omap2/mcbsp.c
++ *
++ * Copyright (C) 2008 Instituto Nokia de Tecnologia
++ * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * Multichannel mode not supported.
++ */
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++
++#include <asm/arch/dma.h>
++#include <asm/arch/mux.h>
++#include <asm/arch/cpu.h>
++#include <asm/arch/mcbsp.h>
++
++static void omap2_mcbsp2_mux_setup(void)
++{
++ omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
++ omap_cfg_reg(R14_24XX_MCBSP2_FSX);
++ omap_cfg_reg(W15_24XX_MCBSP2_DR);
++ omap_cfg_reg(V15_24XX_MCBSP2_DX);
++ omap_cfg_reg(V14_24XX_GPIO117);
++ /*
++ * TODO: Need to add MUX settings for OMAP 2430 SDP
++ */
++}
++
++static void omap2_mcbsp_request(unsigned int id)
++{
++ if (cpu_is_omap2420() && (id == OMAP_MCBSP2))
++ omap2_mcbsp2_mux_setup();
++}
++
++static int omap2_mcbsp_check(unsigned int id)
++{
++ if (id > OMAP_MAX_MCBSP_COUNT - 1) {
++ printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
++ return -ENODEV;
++ }
++ return 0;
++}
++
++static struct omap_mcbsp_ops omap2_mcbsp_ops = {
++ .request = omap2_mcbsp_request,
++ .check = omap2_mcbsp_check,
++};
++
++static struct omap_mcbsp_platform_data omap2_mcbsp_pdata[] = {
++#ifdef CONFIG_ARCH_OMAP24XX
++ {
++ .virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
++ .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
++ .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
++ .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
++ .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
++ .ops = &omap2_mcbsp_ops,
++ .clocks = { "mcbsp_ick", "mcbsp_fck" },
++ },
++ {
++ .virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
++ .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
++ .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
++ .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
++ .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
++ .ops = &omap2_mcbsp_ops,
++ .clocks = { "mcbsp_ick", "mcbsp_fck" },
++ },
++#endif
++#ifdef CONFIG_ARCH_OMAP34XX
++ {
++ .virt_base = IO_ADDRESS(OMAP34XX_MCBSP1_BASE),
++ .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
++ .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
++ .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
++ .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
++ .ops = &omap2_mcbsp_ops,
++ .clocks = { "mcbsp_ick", "mcbsp_fck" },
++ },
++ {
++ .virt_base = IO_ADDRESS(OMAP34XX_MCBSP2_BASE),
++ .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
++ .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
++ .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
++ .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
++ .ops = &omap2_mcbsp_ops,
++ .clocks = { "mcbsp_ick", "mcbsp_fck" },
++ },
++#endif
++};
++#define mcbsp_count ARRAY_SIZE(omap2_mcbsp_pdata)
++
++int __init omap2_mcbsp_init(void)
++{
++ omap_mcbsp_register_board_cfg(omap2_mcbsp_pdata, mcbsp_count);
++
++ return omap_mcbsp_init();
++}
++arch_initcall(omap2_mcbsp_init);
+--
+1.5.5.1.67.gbdb8.dirty
+
+--
+To unsubscribe from this list: send the line "unsubscribe linux-omap" in
+the body of a message to majordomo@vger.kernel.org
+More majordomo info at http://vger.kernel.org/majordomo-info.html
+
diff --git a/packages/linux/linux-omap2-git/beagleboard/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch b/packages/linux/linux-omap2-git/beagleboard/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch new file mode 100644 index 0000000000..6e31ead2bd --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch @@ -0,0 +1,55 @@ +From a1dbb6dd28e9815a307b87b8d96dcf371d6cfd58 Mon Sep 17 00:00:00 2001 +From: Jarkko Nikula <jarkko.nikula@nokia.com> +Date: Mon, 19 May 2008 13:24:41 +0300 +Subject: [PATCH] ASoC: OMAP: Add basic support for OMAP34xx in McBSP DAI driver + +This adds support for OMAP34xx McBSP port 1 and 2. + +Signed-off-by: Jarkko Nikula <jarkko.nikula@nokia.com> +--- + sound/soc/omap/omap-mcbsp.c | 20 +++++++++++++++++++- + 1 files changed, 19 insertions(+), 1 deletions(-) + +diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c +index 40d87e6..8e6ec9d 100644 +--- a/sound/soc/omap/omap-mcbsp.c ++++ b/sound/soc/omap/omap-mcbsp.c +@@ -99,6 +99,21 @@ static const unsigned long omap2420_mcbsp_port[][2] = { + static const int omap2420_dma_reqs[][2] = {}; + static const unsigned long omap2420_mcbsp_port[][2] = {}; + #endif ++#if defined(CONFIG_ARCH_OMAP34XX) ++static const int omap34xx_dma_reqs[][2] = { ++ { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX }, ++ { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX }, ++}; ++static const unsigned long omap34xx_mcbsp_port[][2] = { ++ { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR2, ++ OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR2 }, ++ { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR2, ++ OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR2 }, ++}; ++#else ++static const int omap34xx_dma_reqs[][2] = {}; ++static const unsigned long omap34xx_mcbsp_port[][2] = {}; ++#endif + + static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream) + { +@@ -169,9 +184,12 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, + } else if (cpu_is_omap2420()) { + dma = omap2420_dma_reqs[bus_id][substream->stream]; + port = omap2420_mcbsp_port[bus_id][substream->stream]; ++ } else if (cpu_is_omap343x()) { ++ dma = omap34xx_dma_reqs[bus_id][substream->stream]; ++ port = omap34xx_mcbsp_port[bus_id][substream->stream]; + } else { + /* +- * TODO: Add support for 2430 and 3430 ++ * TODO: Add support for 2430 + */ + return -ENODEV; + } +-- +1.5.5.1 + diff --git a/packages/linux/linux-omap2-git/beagleboard/defconfig b/packages/linux/linux-omap2-git/beagleboard/defconfig index 5c39ea9c6f..5b8f07209f 100644 --- a/packages/linux/linux-omap2-git/beagleboard/defconfig +++ b/packages/linux/linux-omap2-git/beagleboard/defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.26-rc2-omap1 -# Sat May 17 13:43:38 2008 +# Linux kernel version: 2.6.26-rc3-omap1 +# Tue May 20 19:38:20 2008 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -179,7 +179,9 @@ CONFIG_OMAP_BOOT_TAG=y CONFIG_OMAP_BOOT_REASON=y # CONFIG_OMAP_COMPONENT_VERSION is not set # CONFIG_OMAP_GPIO_SWITCH is not set -# CONFIG_OMAP_MUX is not set +CONFIG_OMAP_MUX=y +# CONFIG_OMAP_MUX_DEBUG is not set +CONFIG_OMAP_MUX_WARNINGS=y CONFIG_OMAP_MCBSP=y # CONFIG_OMAP_MMU_FWK is not set # CONFIG_OMAP_MBOX_FWK is not set @@ -190,6 +192,7 @@ CONFIG_OMAP_DM_TIMER=y # CONFIG_OMAP_LL_DEBUG_UART1 is not set # CONFIG_OMAP_LL_DEBUG_UART2 is not set CONFIG_OMAP_LL_DEBUG_UART3=y +CONFIG_OMAP_SERIAL_WAKE=y CONFIG_ARCH_OMAP34XX=y CONFIG_ARCH_OMAP3430=y @@ -948,15 +951,15 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_VIDEO_DEV=y CONFIG_VIDEO_V4L2_COMMON=y -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -CONFIG_DVB_CORE=m +# CONFIG_VIDEO_ALLOW_V4L1 is not set +# CONFIG_VIDEO_V4L1_COMPAT is not set +# CONFIG_DVB_CORE is not set CONFIG_VIDEO_MEDIA=y # # Multimedia drivers # -# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_ATTACH=y CONFIG_MEDIA_TUNER=y # CONFIG_MEDIA_TUNER_CUSTOMIZE is not set CONFIG_MEDIA_TUNER_SIMPLE=y @@ -965,18 +968,11 @@ CONFIG_MEDIA_TUNER_TDA9887=y CONFIG_MEDIA_TUNER_TEA5761=y CONFIG_MEDIA_TUNER_TEA5767=y CONFIG_MEDIA_TUNER_MT20XX=y -CONFIG_MEDIA_TUNER_MT2060=m -CONFIG_MEDIA_TUNER_MT2266=m -CONFIG_MEDIA_TUNER_QT1010=m CONFIG_MEDIA_TUNER_XC2028=y CONFIG_MEDIA_TUNER_XC5000=y CONFIG_VIDEO_V4L2=y -CONFIG_VIDEO_V4L1=y -CONFIG_VIDEOBUF_GEN=m -CONFIG_VIDEOBUF_VMALLOC=m -CONFIG_VIDEO_IR_I2C=m -CONFIG_VIDEO_IR=m CONFIG_VIDEO_TVEEPROM=m +CONFIG_VIDEO_TUNER=m CONFIG_VIDEO_CAPTURE_DRIVERS=y # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set @@ -1006,21 +1002,12 @@ CONFIG_VIDEO_WM8775=m # # Video decoders # -# CONFIG_VIDEO_BT819 is not set -# CONFIG_VIDEO_BT856 is not set -# CONFIG_VIDEO_BT866 is not set -# CONFIG_VIDEO_KS0127 is not set # CONFIG_VIDEO_OV7670 is not set # CONFIG_VIDEO_TCM825X is not set # CONFIG_VIDEO_OV9640 is not set -# CONFIG_VIDEO_SAA7110 is not set -# CONFIG_VIDEO_SAA7111 is not set -# CONFIG_VIDEO_SAA7114 is not set CONFIG_VIDEO_SAA711X=m # CONFIG_VIDEO_SAA717X is not set -# CONFIG_VIDEO_SAA7191 is not set # CONFIG_VIDEO_TVP5150 is not set -# CONFIG_VIDEO_VPX3220 is not set # # Video and audio decoders @@ -1036,162 +1023,29 @@ CONFIG_VIDEO_CX2341X=m # Video encoders # # CONFIG_VIDEO_SAA7127 is not set -# CONFIG_VIDEO_SAA7185 is not set -# CONFIG_VIDEO_ADV7170 is not set -# CONFIG_VIDEO_ADV7175 is not set # # Video improvement chips # # CONFIG_VIDEO_UPD64031A is not set # CONFIG_VIDEO_UPD64083 is not set -CONFIG_VIDEO_VIVI=m -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_CPIA2 is not set -CONFIG_VIDEO_SAA5246A=m -CONFIG_VIDEO_SAA5249=m -# CONFIG_TUNER_3036 is not set -# CONFIG_VIDEO_AU0828 is not set +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set CONFIG_V4L_USB_DRIVERS=y CONFIG_VIDEO_PVRUSB2=m CONFIG_VIDEO_PVRUSB2_SYSFS=y -# CONFIG_VIDEO_PVRUSB2_DVB is not set # CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -CONFIG_VIDEO_EM28XX=m -CONFIG_VIDEO_EM28XX_ALSA=m -# CONFIG_VIDEO_EM28XX_DVB is not set -CONFIG_VIDEO_USBVISION=m -# CONFIG_USB_VICAM is not set -# CONFIG_USB_IBMCAM is not set -# CONFIG_USB_KONICAWC is not set -# CONFIG_USB_QUICKCAM_MESSENGER is not set -CONFIG_USB_ET61X251=m -# CONFIG_VIDEO_OVCAMCHIP is not set -# CONFIG_USB_W9968CF is not set -# CONFIG_USB_OV511 is not set -# CONFIG_USB_SE401 is not set +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_VIDEO_USBVISION is not set +# CONFIG_USB_ET61X251 is not set CONFIG_USB_SN9C102=m -# CONFIG_USB_STV680 is not set -CONFIG_USB_ZC0301=m -# CONFIG_USB_PWC is not set -CONFIG_USB_ZR364XX=m -CONFIG_USB_STKWEBCAM=m +# CONFIG_USB_ZC0301 is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set # CONFIG_SOC_CAMERA is not set # CONFIG_RADIO_ADAPTERS is not set -CONFIG_DVB_CAPTURE_DRIVERS=y -# CONFIG_TTPCI_EEPROM is not set - -# -# Supported USB Adapters -# -CONFIG_DVB_USB=m -# CONFIG_DVB_USB_DEBUG is not set -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_DIBUSB_MB=m -# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_CXUSB=m -CONFIG_DVB_USB_M920X=m -CONFIG_DVB_USB_GL861=m -CONFIG_DVB_USB_AU6610=m -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_VP7045=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_NOVA_T_USB2=m -CONFIG_DVB_USB_TTUSB2=m -CONFIG_DVB_USB_DTT200U=m -CONFIG_DVB_USB_OPERA1=m -CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m -CONFIG_DVB_TTUSB_BUDGET=m -CONFIG_DVB_TTUSB_DEC=m -CONFIG_DVB_CINERGYT2=m -# CONFIG_DVB_CINERGYT2_TUNING is not set - -# -# Supported FlexCopII (B2C2) Adapters -# -# CONFIG_DVB_B2C2_FLEXCOP is not set - -# -# Supported DVB Frontends -# - -# -# Customise DVB Frontends -# -# CONFIG_DVB_FE_CUSTOMISE is not set - -# -# DVB-S (satellite) frontends -# -CONFIG_DVB_CX24110=m -CONFIG_DVB_CX24123=m -CONFIG_DVB_MT312=m -CONFIG_DVB_S5H1420=m -CONFIG_DVB_STV0299=m -CONFIG_DVB_TDA8083=m -CONFIG_DVB_TDA10086=m -CONFIG_DVB_VES1X93=m -# CONFIG_DVB_TUNER_ITD1000 is not set -CONFIG_DVB_TDA826X=m -CONFIG_DVB_TUA6100=m - -# -# DVB-T (terrestrial) frontends -# -CONFIG_DVB_SP8870=m -CONFIG_DVB_SP887X=m -CONFIG_DVB_CX22700=m -CONFIG_DVB_CX22702=m -CONFIG_DVB_L64781=m -CONFIG_DVB_TDA1004X=m -CONFIG_DVB_NXT6000=m -CONFIG_DVB_MT352=m -CONFIG_DVB_ZL10353=m -CONFIG_DVB_DIB3000MB=m -CONFIG_DVB_DIB3000MC=m -CONFIG_DVB_DIB7000M=m -CONFIG_DVB_DIB7000P=m -# CONFIG_DVB_TDA10048 is not set - -# -# DVB-C (cable) frontends -# -CONFIG_DVB_VES1820=m -CONFIG_DVB_TDA10021=m -CONFIG_DVB_TDA10023=m -CONFIG_DVB_STV0297=m - -# -# ATSC (North American/Korean Terrestrial/Cable DTV) frontends -# -CONFIG_DVB_NXT200X=m -CONFIG_DVB_OR51211=m -CONFIG_DVB_OR51132=m -CONFIG_DVB_BCM3510=m -CONFIG_DVB_LGDT330X=m -CONFIG_DVB_S5H1409=m -# CONFIG_DVB_AU8522 is not set -# CONFIG_DVB_S5H1411 is not set - -# -# Digital terrestrial only tuners/PLL -# -CONFIG_DVB_PLL=m -CONFIG_DVB_TUNER_DIB0070=m - -# -# SEC control devices for DVB-S -# -CONFIG_DVB_LNBP21=m -# CONFIG_DVB_ISL6405 is not set -CONFIG_DVB_ISL6421=m -CONFIG_DAB=y -CONFIG_USB_DABUSB=m +# CONFIG_DAB is not set # # Graphics support @@ -1210,7 +1064,6 @@ CONFIG_FB_CFB_IMAGEBLIT=y # CONFIG_FB_SYS_IMAGEBLIT is not set # CONFIG_FB_FOREIGN_ENDIAN is not set # CONFIG_FB_SYS_FOPS is not set -CONFIG_FB_DEFERRED_IO=y # CONFIG_FB_SVGALIB is not set # CONFIG_FB_MACMODES is not set # CONFIG_FB_BACKLIGHT is not set @@ -1248,10 +1101,7 @@ CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y # CONFIG_FONTS is not set CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -CONFIG_LOGO_LINUX_VGA16=y -CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_LOGO is not set # # Sound @@ -1455,6 +1305,7 @@ CONFIG_USB_SERIAL=m # CONFIG_USB_SERIAL_MCT_U232 is not set # CONFIG_USB_SERIAL_MOS7720 is not set # CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set # CONFIG_USB_SERIAL_NAVMAN is not set # CONFIG_USB_SERIAL_PL2303 is not set # CONFIG_USB_SERIAL_OTI6858 is not set diff --git a/packages/linux/linux-omap2_git.bb b/packages/linux/linux-omap2_git.bb index 38f6df204e..f167d3be3e 100644 --- a/packages/linux/linux-omap2_git.bb +++ b/packages/linux/linux-omap2_git.bb @@ -2,13 +2,18 @@ require linux-omap.inc FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/linux-omap2-git/${MACHINE}" -SRCREV = "fe2c08002adea304a13ccb806aa1ab4058607094" +SRCREV = "f4eb51b909144550048b7922ebd1904a54005394" -PV = "2.6.25+2.6.26-rc2+git${SRCREV}" -PR = "r15" +PV = "2.6.25+2.6.26-rc3+git${SRCREV}" +PR = "r16" SRC_URI = "git://source.mvista.com/git/linux-omap-2.6.git;protocol=git \ + file://00001-mcbsp-transform.patch;patch=1 \ + file://00002-mcbsp-omap1.patch;patch=1 \ + file://00003-mcbsp-omap3-clock.patch;patch=1 \ + file://00004-omap2-mcbsp.patch;patch=1 \ + file://0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch;patch=1 \ file://defconfig" SRC_URI_append_beagleboard = " file://no-harry-potter.diff;patch=1 \ diff --git a/packages/u-boot/files/sffsdr-u-boot.patch b/packages/u-boot/files/sffsdr-u-boot.patch new file mode 100644 index 0000000000..cf8415330b --- /dev/null +++ b/packages/u-boot/files/sffsdr-u-boot.patch @@ -0,0 +1,718 @@ +X-Mozilla-Status: 0003 +X-Mozilla-Status2: 00000000 +Return-Path: <owner-sffsdr@LISTSERV.VT.EDU> +Received: from mail6.zoneedit.com (mail6.zoneedit.com [66.240.226.247]) + by www.balister.org (8.13.8/8.13.5) with ESMTP id m4GGYUC2017393 + for <balister@www.balister.org>; Fri, 16 May 2008 12:34:31 -0400 +Received: from listserv.vt.edu (listserv.vt.edu [198.82.161.192]) + by mail6.zoneedit.com (Postfix) with ESMTP id B457D5D5B6 + for <philip@BALISTER.ORG>; Fri, 16 May 2008 12:34:29 -0400 (EDT) +Received: from listserv.vt.edu (listserv.vt.edu [127.0.0.1]) + by listserv.vt.edu (8.13.1/8.13.1/LISTSERV) with ESMTP id m4G7PKLG018387; + Fri, 16 May 2008 12:34:28 -0400 +Received: by LISTSERV.VT.EDU (LISTSERV-TCP/IP release 14.4) with spool id + 29624903 for SFFSDR@LISTSERV.VT.EDU; Fri, 16 May 2008 12:34:28 -0400 +Received: from freya.cc.vt.edu (IDENT:mirapoint@freya.cc.vt.edu + [198.82.161.17]) by listserv.vt.edu (8.13.1/8.13.1/LISTSERV) with + ESMTP id m4GGYSHs005336 for <sffsdr@listserv.vt.edu>; Fri, 16 May + 2008 12:34:28 -0400 +Received: from server.hugovil.com (201-217-static-ppp.3menatwork.com + [64.235.217.201]) by freya.cc.vt.edu (MOS 3.8.6-GA) with ESMTP id + AOF41814; Fri, 16 May 2008 12:34:27 -0400 (EDT) +Received: from localhost.localdomain (mail.lyrtech.com [204.101.172.90]) by + server.hugovil.com (8.13.6/8.13.6) with ESMTP id m4GGYOYT028003 for + <sffsdr@listserv.vt.edu>; Fri, 16 May 2008 12:34:24 -0400 +X-Mailer: git-send-email 1.5.4.5 +X-Greylist: Default is to whitelist mail, + not delayed by milter-greylist-3.0 (server.hugovil.com + [64.235.217.201]); Fri, 16 May 2008 12:34:25 -0400 (EDT) +X-Junkmail-Status: score=10/50, host=freya.cc.vt.edu +X-Junkmail-SD-Raw: score=unknown, + refid=str=0001.0A090205.482DB793.02F2,ss=1,fgs=0, + ip=64.235.217.201, so=2007-10-30 19:00:17, + dmn=5.4.3/2007-10-19 +X-Junkmail-IWF: false +Message-ID: <1210970183-26615-1-git-send-email-hugo.villeneuve@lyrtech.com> +Date: Fri, 16 May 2008 16:36:23 -0400 +Reply-To: sffsdr Discussion List <SFFSDR@LISTSERV.VT.EDU> +Sender: sffsdr Discussion List <SFFSDR@LISTSERV.VT.EDU> +From: Hugo Villeneuve <hugo.villeneuve@LYRTECH.COM> +Subject: [PATCH] Add support for Lyrtech SFF-SDR board (ARM926EJS) +To: SFFSDR@LISTSERV.VT.EDU +Precedence: list + +Philip, +this is the patch I´m planning on sending to the U-Boot +folks so that the SFFSDR is integrated into mainline +U-Boot. + +It is mostly based on the work you have done. + +I added code to make the EEPROM accessible through +the I2C bus. This is needed because we use an I2C +switch on the SFFSDR that is turned OFF by default. +I also added code to read the MAC address from the +EEPROM. + +I also removed unused stuff specific to the +Schmoogie board. + +The network and NAND are both working fine with +that patch. + +I´m looking forward to your comments. + +Hugo V. + +--- + +This patch adds support for the Lyrtech SFF-SDR, based +on the TI DaVinci architecture (ARM926EJS). + +Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com> +--- + + MAKEALL | 1 + + Makefile | 3 + + board/davinci/sffsdr/Makefile | 52 +++++++++ + board/davinci/sffsdr/board_init.S | 29 +++++ + board/davinci/sffsdr/config.mk | 24 ++++ + board/davinci/sffsdr/dv_board.c | 211 +++++++++++++++++++++++++++++++++++++ + board/davinci/sffsdr/u-boot.lds | 52 +++++++++ + include/asm-arm/mach-types.h | 13 +++ + include/configs/davinci_sffsdr.h | 171 ++++++++++++++++++++++++++++++ + 9 files changed, 556 insertions(+), 0 deletions(-) + +diff --git a/MAKEALL b/MAKEALL +index 791eabc..1a0cb37 100755 +--- a/MAKEALL ++++ b/MAKEALL +@@ -495,6 +495,7 @@ LIST_ARM9=" \ + voiceblue \ + davinci_dvevm \ + davinci_schmoogie \ ++ davinci_sffsdr \ + davinci_sonata \ + " + +diff --git a/Makefile b/Makefile +index 167a717..6280a59 100644 +--- a/Makefile ++++ b/Makefile +@@ -2402,6 +2402,9 @@ davinci_dvevm_config : unconfig + davinci_schmoogie_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs schmoogie davinci davinci + ++davinci_sffsdr_config : unconfig ++ @$(MKCONFIG) $(@:_config=) arm arm926ejs sffsdr davinci davinci ++ + davinci_sonata_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci + +diff --git a/board/davinci/sffsdr/Makefile b/board/davinci/sffsdr/Makefile +new file mode 100644 +index 0000000..fa00138 +--- /dev/null ++++ b/board/davinci/sffsdr/Makefile +@@ -0,0 +1,52 @@ ++# ++# (C) Copyright 2000, 2001, 2002 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).a ++ ++COBJS := dv_board.o ++SOBJS := board_init.o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak *~ .depend ++ ++######################################################################### ++# This is for $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff --git a/board/davinci/sffsdr/board_init.S b/board/davinci/sffsdr/board_init.S +new file mode 100644 +index 0000000..22d8adc +--- /dev/null ++++ b/board/davinci/sffsdr/board_init.S +@@ -0,0 +1,29 @@ ++/* ++ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> ++ * ++ * Board-specific low level initialization code. Called at the very end ++ * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no ++ * initialization required. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include <config.h> ++ ++.globl dv_board_init ++dv_board_init: ++ ++ mov pc, lr +diff --git a/board/davinci/sffsdr/config.mk b/board/davinci/sffsdr/config.mk +new file mode 100644 +index 0000000..e8a329c +--- /dev/null ++++ b/board/davinci/sffsdr/config.mk +@@ -0,0 +1,24 @@ ++# ++# (C) Copyright 2002 ++# Gary Jennejohn, DENX Software Engineering, <gj@denx.de> ++# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> ++# ++# Lyrtech SFF SDR board (ARM926EJS) cpu ++# see http://www.lyrtech.com/ for more information on Lyrtech ++# ++# SFF SDR board has 1 bank of 128 MB DDR RAM ++# Physical Address: ++# 8000'0000 to 87FF'FFFF ++# ++# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 ++# (mem base + reserved) ++# ++# Integrity kernel is expected to be at 8000'0000, entry 8000'00D0, ++# up to 81FF'FFFF (uses up to 32 MB of memory for text, heap, etc). ++# ++# we load ourself to 8400'0000 ++# ++# ++ ++# Provide at least 32MB spacing between us and the Integrity kernel image ++TEXT_BASE = 0x84000000 +diff --git a/board/davinci/sffsdr/dv_board.c b/board/davinci/sffsdr/dv_board.c +new file mode 100644 +index 0000000..a3f60cb +--- /dev/null ++++ b/board/davinci/sffsdr/dv_board.c +@@ -0,0 +1,211 @@ ++/* ++ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> ++ * ++ * Parts are shamelessly stolen from various TI sources, original copyright ++ * follows: ++ * ----------------------------------------------------------------- ++ * ++ * Copyright (C) 2004 Texas Instruments. ++ * ++ * ---------------------------------------------------------------------------- ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ---------------------------------------------------------------------------- ++ */ ++ ++#include <common.h> ++#include <i2c.h> ++#include <asm/arch/hardware.h> ++#include <asm/arch/emac_defs.h> ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++extern void i2c_init(int speed, int slaveaddr); ++extern void timer_init(void); ++extern int eth_hw_init(void); ++extern phy_t phy; ++ ++ ++/* Works on Always On power domain only (no PD argument) */ ++void lpsc_on(unsigned int id) ++{ ++ dv_reg_p mdstat, mdctl; ++ ++ if (id >= DAVINCI_LPSC_GEM) ++ return; /* Don't work on DSP Power Domain */ ++ ++ mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); ++ mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); ++ ++ while (REG(PSC_PTSTAT) & 0x01) {;} ++ ++ if ((*mdstat & 0x1f) == 0x03) ++ return; /* Already on and enabled */ ++ ++ *mdctl |= 0x03; ++ ++ /* Special treatment for some modules as for sprue14 p.7.4.2 */ ++ if ( (id == DAVINCI_LPSC_VPSSSLV) || ++ (id == DAVINCI_LPSC_EMAC) || ++ (id == DAVINCI_LPSC_EMAC_WRAPPER) || ++ (id == DAVINCI_LPSC_MDIO) || ++ (id == DAVINCI_LPSC_USB) || ++ (id == DAVINCI_LPSC_ATA) || ++ (id == DAVINCI_LPSC_VLYNQ) || ++ (id == DAVINCI_LPSC_UHPI) || ++ (id == DAVINCI_LPSC_DDR_EMIF) || ++ (id == DAVINCI_LPSC_AEMIF) || ++ (id == DAVINCI_LPSC_MMC_SD) || ++ (id == DAVINCI_LPSC_MEMSTICK) || ++ (id == DAVINCI_LPSC_McBSP) || ++ (id == DAVINCI_LPSC_GPIO) ++ ) ++ *mdctl |= 0x200; ++ ++ REG(PSC_PTCMD) = 0x01; ++ ++ while (REG(PSC_PTSTAT) & 0x03) {;} ++ while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */ ++} ++ ++void dsp_on(void) ++{ ++ int i; ++ ++ if (REG(PSC_PDSTAT1) & 0x1f) ++ return; /* Already on */ ++ ++ REG(PSC_GBLCTL) |= 0x01; ++ REG(PSC_PDCTL1) |= 0x01; ++ REG(PSC_PDCTL1) &= ~0x100; ++ REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; ++ REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; ++ REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; ++ REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; ++ REG(PSC_PTCMD) = 0x02; ++ ++ for (i = 0; i < 100; i++) { ++ if (REG(PSC_EPCPR) & 0x02) ++ break; ++ } ++ ++ REG(PSC_CHP_SHRTSW) = 0x01; ++ REG(PSC_PDCTL1) |= 0x100; ++ REG(PSC_EPCCR) = 0x02; ++ ++ for (i = 0; i < 100; i++) { ++ if (!(REG(PSC_PTSTAT) & 0x02)) ++ break; ++ } ++ ++ REG(PSC_GBLCTL) &= ~0x1f; ++} ++ ++ ++int board_init(void) ++{ ++ /* arch number of the board */ ++ gd->bd->bi_arch_number = MACH_TYPE_SFFSDR; ++ ++ /* address of boot parameters */ ++ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; ++ ++ /* Workaround for TMS320DM6446 errata 1.3.22 */ ++ REG(PSC_SILVER_BULLET) = 0; ++ ++ /* Power on required peripherals */ ++ lpsc_on(DAVINCI_LPSC_EMAC); ++ lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); ++ lpsc_on(DAVINCI_LPSC_MDIO); ++ lpsc_on(DAVINCI_LPSC_I2C); ++ lpsc_on(DAVINCI_LPSC_UART0); ++ lpsc_on(DAVINCI_LPSC_TIMER1); ++ lpsc_on(DAVINCI_LPSC_GPIO); ++ ++ /* Powerup the DSP */ ++ dsp_on(); ++ ++ /* Bringup UART0 out of reset */ ++ REG(UART0_PWREMU_MGMT) = 0x0000e003; ++ ++ /* Enable GIO3.3V cells used for EMAC */ ++ REG(VDD3P3V_PWDN) = 0; ++ ++ /* Enable UART0 MUX lines */ ++ REG(PINMUX1) |= 1; ++ ++ /* Enable EMAC and AEMIF pins */ ++ REG(PINMUX0) = 0x80000c1f; ++ ++ /* Enable I2C pin Mux */ ++ REG(PINMUX1) |= (1 << 7); ++ ++ /* Set the Bus Priority Register to appropriate value */ ++ REG(VBPR) = 0x20; ++ ++ timer_init(); ++ ++ return(0); ++} ++ ++int misc_init_r (void) ++{ ++ u_int8_t tmp[20], buf[10]; ++ int i = 0; ++ int clk = 0; ++ ++ clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); ++ ++ printf ("ARM Clock: %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2); ++ printf ("DDR Clock: %dMHz\n", (clk / 2)); ++ ++ /* Configure I2C switch (PCA9543) to enable channel 0. */ ++ tmp[0] = CFG_I2C_PCA9543_ENABLE_CH0; ++ if (i2c_write(CFG_I2C_PCA9543_ADDR, 0, CFG_I2C_PCA9543_ADDR_LEN, tmp, 1)) { ++ printf ("Write to MUX @ 0x%02x failed\n", CFG_I2C_PCA9543_ADDR); ++ } ++ ++ /* Set Ethernet MAC address from EEPROM. ++ * We must read 8 bytes because data is stored in little-endian. */ ++ if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x05A8, CFG_I2C_EEPROM_ADDR_LEN, buf, 8)) { ++ printf ("Read from EEPROM @ 0x%02x failed\n", CFG_I2C_EEPROM_ADDR); ++ } else { ++ tmp[0] = 0xff; ++ for (i = 0; i < 6; i++) ++ tmp[0] &= buf[i]; ++ ++ if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { ++ sprintf ((char *)&tmp[0], "%02x:%02x:%02x:%02x:%02x:%02x", ++ buf[3], buf[2], buf[1], buf[0], ++ buf[7], buf[6]); ++ setenv ("ethaddr", (char *)&tmp[0]); ++ } ++ } ++ ++ if (!eth_hw_init()) { ++ printf ("Ethernet init failed\n"); ++ } else { ++ printf ("ETH PHY: %s\n", phy.name); ++ } ++ ++ return(0); ++} ++ ++int dram_init(void) ++{ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++ ++ return(0); ++} +diff --git a/board/davinci/sffsdr/u-boot.lds b/board/davinci/sffsdr/u-boot.lds +new file mode 100644 +index 0000000..a4fcd1a +--- /dev/null ++++ b/board/davinci/sffsdr/u-boot.lds +@@ -0,0 +1,52 @@ ++/* ++ * (C) Copyright 2002 ++ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") ++OUTPUT_ARCH(arm) ++ENTRY(_start) ++SECTIONS ++{ ++ . = 0x00000000; ++ . = ALIGN(4); ++ .text : ++ { ++ cpu/arm926ejs/start.o (.text) ++ *(.text) ++ } ++ . = ALIGN(4); ++ .rodata : { *(.rodata) } ++ . = ALIGN(4); ++ .data : { *(.data) } ++ . = ALIGN(4); ++ .got : { *(.got) } ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ . = ALIGN(4); ++ __bss_start = .; ++ .bss (NOLOAD) : { *(.bss) } ++ _end = .; ++} +diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h +index aaf2ea2..b347857 100644 +--- a/include/asm-arm/mach-types.h ++++ b/include/asm-arm/mach-types.h +@@ -1595,6 +1595,7 @@ extern unsigned int __machine_arch_type; + #define MACH_TYPE_P300 1602 + #define MACH_TYPE_XDACOMET 1603 + #define MACH_TYPE_DEXFLEX2 1604 ++#define MACH_TYPE_SFFSDR 1657 + + #ifdef CONFIG_ARCH_EBSA110 + # ifdef machine_arch_type +@@ -16500,6 +16501,18 @@ extern unsigned int __machine_arch_type; + # define machine_is_schmoogie() (0) + #endif + ++#ifdef CONFIG_MACH_SFFSDR ++# ifdef machine_arch_type ++# undef machine_arch_type ++# define machine_arch_type __machine_arch_type ++# else ++# define machine_arch_type MACH_TYPE_SFFSDR ++# endif ++# define machine_is_sffsdr() (machine_arch_type == MACH_TYPE_SFFSDR) ++#else ++# define machine_is_sffsdr() (0) ++#endif ++ + #ifdef CONFIG_MACH_AZTOOL + # ifdef machine_arch_type + # undef machine_arch_type +diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h +new file mode 100644 +index 0000000..a9b480b +--- /dev/null ++++ b/include/configs/davinci_sffsdr.h +@@ -0,0 +1,171 @@ ++/* ++ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++#include <asm/sizes.h> ++ ++/*=======*/ ++/* Board */ ++/*=======*/ ++#define SFFSDR ++#define CFG_NAND_LARGEPAGE ++#define CFG_USE_NAND ++/*===================*/ ++/* SoC Configuration */ ++/*===================*/ ++#define CONFIG_ARM926EJS /* arm926ejs CPU core */ ++#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ ++#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ ++#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ ++#define CFG_HZ 1000 ++/*==================================================*/ ++/* EEPROM definitions for Atmel 24LC64 EEPROM chip */ ++/*==================================================*/ ++#define CFG_I2C_EEPROM_ADDR_LEN 2 ++#define CFG_I2C_EEPROM_ADDR 0x50 ++#define CFG_EEPROM_PAGE_WRITE_BITS 5 ++#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 ++/*=============*/ ++/* Memory Info */ ++/*=============*/ ++#define CFG_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ ++#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ ++#define CFG_MEMTEST_START 0x80000000 /* memtest start address */ ++#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */ ++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ ++#define CONFIG_STACKSIZE (256*1024) /* regular stack */ ++#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ ++#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ ++#define DDR_4BANKS /* 4-bank DDR2 (128MB) */ ++/*====================*/ ++/* Serial Driver info */ ++/*====================*/ ++#define CFG_NS16550 ++#define CFG_NS16550_SERIAL ++#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ ++#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */ ++#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */ ++#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ ++#define CONFIG_BAUDRATE 115200 /* Default baud rate */ ++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } ++/*===================*/ ++/* I2C Configuration */ ++/*===================*/ ++#define CONFIG_HARD_I2C ++#define CONFIG_DRIVER_DAVINCI_I2C ++#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ ++#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ ++/*==================================*/ ++/* Network & Ethernet Configuration */ ++/*==================================*/ ++#define CONFIG_DRIVER_TI_EMAC ++#define CONFIG_MII ++#define CONFIG_BOOTP_DEFAULT ++#define CONFIG_BOOTP_DNS ++#define CONFIG_BOOTP_DNS2 ++#define CONFIG_BOOTP_SEND_HOSTNAME ++#define CONFIG_NET_RETRY_COUNT 10 ++#define CONFIG_OVERWRITE_ETHADDR_ONCE ++/*=====================*/ ++/* Flash & Environment */ ++/*=====================*/ ++#undef CFG_ENV_IS_IN_FLASH ++#define CFG_NO_FLASH ++#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ ++#define CFG_ENV_SECT_SIZE 2048 /* Env sector Size */ ++#define CFG_ENV_SIZE SZ_128K ++#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ ++#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ ++#define CFG_NAND_BASE 0x02000000 ++#define CFG_NAND_HW_ECC ++#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ ++#define NAND_MAX_CHIPS 1 ++#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ ++/*=====================*/ ++/* Board related stuff */ ++/*=====================*/ ++/*==========================================*/ ++/* I2C switch definitions for PCA9543 chip */ ++/* on Lyrtech SFF SDR board. */ ++/*==========================================*/ ++#define CFG_I2C_PCA9543_ADDR 0x70 ++#define CFG_I2C_PCA9543_ADDR_LEN 0 /* This chip has a single register. */ ++#define CFG_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */ ++/*==============================*/ ++/* U-Boot general configuration */ ++/*==============================*/ ++#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ ++#define CONFIG_MISC_INIT_R ++#undef CONFIG_BOOTDELAY ++#define CONFIG_BOOTFILE "uImage" /* Boot file name */ ++#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ ++#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ ++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buffer sz */ ++#define CFG_MAXARGS 16 /* max number of command args */ ++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ ++#define CFG_LOAD_ADDR 0x80700000 /* default Linux kernel load address */ ++#define CONFIG_VERSION_VARIABLE ++#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */ ++#define CFG_HUSH_PARSER ++#define CFG_PROMPT_HUSH_PS2 "> " ++#define CONFIG_CMDLINE_EDITING ++#define CFG_LONGHELP ++#define CONFIG_CRC32_VERIFY ++#define CONFIG_MX_CYCLIC ++/* ++ * Define this to load an Integrity kernel. ++ * ++#define CONFIG_CMD_ELF ++ */ ++ ++/*===================*/ ++/* Linux Information */ ++/*===================*/ ++#define LINUX_BOOT_PARAM_ADDR 0x80000100 ++#define CONFIG_CMDLINE_TAG ++#define CONFIG_SETUP_MEMORY_TAGS ++#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" ++#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot" ++/*=================*/ ++/* U-Boot commands */ ++/*=================*/ ++#include <config_cmd_default.h> ++#define CONFIG_CMD_ASKENV ++#define CONFIG_CMD_DHCP ++#define CONFIG_CMD_DIAG ++#define CONFIG_CMD_I2C ++#define CONFIG_CMD_MII ++#define CONFIG_CMD_PING ++#define CONFIG_CMD_SAVES ++#define CONFIG_CMD_NAND ++#define CONFIG_CMD_EEPROM ++#undef CONFIG_CMD_BDI ++#undef CONFIG_CMD_FPGA ++#undef CONFIG_CMD_SETGETDCR ++#undef CONFIG_CMD_FLASH ++#undef CONFIG_CMD_IMLS ++/*=======================*/ ++/* KGDB support (if any) */ ++/*=======================*/ ++#ifdef CONFIG_CMD_KGDB ++#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ ++#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ ++#endif ++#endif /* __CONFIG_H */ + diff --git a/packages/u-boot/u-boot_git.bb b/packages/u-boot/u-boot_git.bb index 60ab0ab3f6..a05422ef50 100644 --- a/packages/u-boot/u-boot_git.bb +++ b/packages/u-boot/u-boot_git.bb @@ -2,9 +2,13 @@ require u-boot.inc PR="r1" DEFAULT_PREFERENCE = "-1" +SRCREV_davinci-sffsdr = "4ce1e23b5e12283579828b3d23e8fd6e1328a7aa" + SRC_URI = "git://www.denx.de/git/u-boot.git;protocol=git " SRC_URI_sequoia = "git://www.denx.de/git/u-boot.git;protocol=git;tag=cf3b41e0c1111dbb865b6e34e9f3c3d3145a6093 " +SRC_URI_append_davinci-sffsdr = " file://sffsdr-u-boot.patch;patch=1 " + S = "${WORKDIR}/git" PACKAGE_ARCH = "${MACHINE_ARCH}" diff --git a/packages/vnc/x11vnc_0.9.3.bb b/packages/vnc/x11vnc_0.9.3.bb index 04ac87b444..7714a4fffa 100644 --- a/packages/vnc/x11vnc_0.9.3.bb +++ b/packages/vnc/x11vnc_0.9.3.bb @@ -3,7 +3,7 @@ SECTION = "x11/utils" HOMEPAGE = "http://www.karlrunge.com/x11vnc/" AUTHOR = "Karl Runge" LICENSE = "GPL" -DEPENDS = "openssl virtual/libx11 libxext avahi jpeg zlib" +DEPENDS = "openssl virtual/libx11 libxtst libxext avahi jpeg zlib" SRC_URI = "http://www.karlrunge.com/x11vnc/x11vnc-0.9.3.tar.gz" |