Merge branch 'org.openembedded.dev' of git@git.openembedded.net:openembedded into org.openembedded.dev

49 files changed, 1677 insertions, 80 deletions

diff --git a/recipes/angstrom/e-wm-config-angstrom.bb b/recipes/angstrom/e-wm-config-angstrom.bb
index 139a23138f..04c35be2b5 100644
--- a/recipes/angstrom/e-wm-config-angstrom.bb
+++ b/recipes/angstrom/e-wm-config-angstrom.bb
@@ -4,7 +4,7 @@ DEPENDS = "edje-native eet-native"
 RDEPENDS = "e-wm"
 RRECOMMENDS_${PN} = "places"
 
-PR = "r7"
+PR = "r8"
 
 SRC_URI = " \
           file://e.src \
diff --git a/recipes/angstrom/e-wm-config-angstrom/profile.desktop b/recipes/angstrom/e-wm-config-angstrom/profile.desktop
index f85ac869d6..2a8ad2ff8c 100644
--- a/recipes/angstrom/e-wm-config-angstrom/profile.desktop
+++ b/recipes/angstrom/e-wm-config-angstrom/profile.desktop
@@ -2,4 +2,4 @@
 Type=Link
 Name=Angstrom
 Icon=icon.png
-Comment=This is the Angstrom<br>profile that is<br>universal for most<br>systems. Choose this<br>if you are not<br>sure what to choose.
+Comment=This is the Angstrom profile that is universal for most systems. Choose this if you are not sure what to choose.
diff --git a/recipes/binutils/binutils_2.18.bb b/recipes/binutils/binutils_2.18.bb
index 0155fb1151..3b650c679b 100644
--- a/recipes/binutils/binutils_2.18.bb
+++ b/recipes/binutils/binutils_2.18.bb
@@ -1,4 +1,4 @@
-PR = "r5"
+PR = "r6"
 
 require binutils.inc
 LICENSE = "GPLv3"
@@ -18,3 +18,6 @@ SRC_URI = "\
 
 # powerpc patches
 SRC_URI += "file://binutils-2.16.1-e300c2c3.patch;patch=1"
+
+# ep93xx crunch patches
+SRC_URI_append_ep9312 = " file://binutils-crunch.patch;patch=1"
diff --git a/recipes/binutils/files/binutils-crunch.patch b/recipes/binutils/files/binutils-crunch.patch
new file mode 100644
index 0000000000..79771aad2c
--- /dev/null
+++ b/recipes/binutils/files/binutils-crunch.patch
@@ -0,0 +1,163 @@
+--- binutils-2.18-original/gas/config/tc-arm.c	2007-05-18 13:45:49.000000000 +1000
++++ binutils-2.18/gas/config/tc-arm.c	2008-04-03 12:38:28.000000000 +1000
+@@ -3573,6 +3575,140 @@
+   ignore_rest_of_line ();
+ }
+ 
++/* Parse a directive saving Maverick Crunch double registers.  */
++
++static void
++s_arm_unwind_save_mvd (void)
++{
++  int reg;
++  int hi_reg;
++  int i;
++  unsigned mask = 0;
++  valueT op;
++
++  if (*input_line_pointer == '{')
++    input_line_pointer++;
++
++  do
++    {
++      reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MVD);
++
++      if (reg == FAIL)
++	{
++	  as_bad (_(reg_expected_msgs[REG_TYPE_MVD]));
++	  goto error;
++	}
++
++      if (mask >> reg)
++        as_tsktsk (_("register list not in ascending order"));
++      mask |= 1 << reg;
++
++      if (*input_line_pointer == '-')
++	{
++	  input_line_pointer++;
++	  hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MVD);
++	  if (hi_reg == FAIL)
++	    {
++	      as_bad (_(reg_expected_msgs[REG_TYPE_MVD]));
++	      goto error;
++	    }
++	  else if (reg >= hi_reg)
++	    {
++	      as_bad (_("bad register range"));
++	      goto error;
++	    }
++	  for (; reg < hi_reg; reg++)
++	    mask |= 1 << reg;
++	}
++    }
++  while (skip_past_comma (&input_line_pointer) != FAIL);
++
++  if (*input_line_pointer == '}')
++    input_line_pointer++;
++
++  demand_empty_rest_of_line ();
++
++  /* Generate any deferred opcodes because we're going to be looking at
++     the list.	*/
++  flush_pending_unwind ();
++
++  for (i = 0; i < 16; i++)
++    {
++      if (mask & (1 << i))
++	unwind.frame_size += 8;
++    }
++
++  /* Attempt to combine with a previous opcode.	 We do this because gcc
++     likes to output separate unwind directives for a single block of
++     registers.	 */
++  if (unwind.opcode_count > 0)
++    {
++      i = unwind.opcodes[unwind.opcode_count - 1];
++      if ((i & 0xf8) == 0xd8)
++        {
++          i &= 7;
++          /* Only merge if the blocks are contiguous.  */
++          if (i < 6)
++	         {
++               if ((mask & 0xfe00) == (1 << 9))
++		        {
++                 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
++                 unwind.opcode_count--;
++               }
++	         }
++          else if (i == 6 && unwind.opcode_count >= 2)
++	         {
++	      i = unwind.opcodes[unwind.opcode_count - 2];
++	      reg = i >> 4;
++	      i &= 0xf;
++
++	      op = 0xffff << (reg - 1);
++         if (reg > 0
++		     && ((mask & op) == (1u << (reg - 1))))
++		   {
++		     op = (1 << (reg + i + 1)) - 1;
++		     op &= ~((1 << reg) - 1);
++		     mask |= op;
++		     unwind.opcode_count -= 2;
++		   }
++        }
++      }
++    }
++
++  hi_reg = 15;
++  /* We want to generate opcodes in the order the registers have been
++     saved, ie. descending order.  */
++  for (reg = 15; reg >= -1; reg--)
++    {
++      /* Save registers in blocks.  */
++      if (reg < 0
++	  || !(mask & (1 << reg)))
++	{
++	  /* We found an unsaved reg.  Generate opcodes to save the
++	     preceeding block.	*/
++	  if (reg != hi_reg)
++	    {
++	      if (reg == 9)
++		{
++		  /* Short form.  */
++		  op = 0xd8 | (hi_reg - 10);
++		  add_unwind_opcode (op, 1);
++		}
++	      else
++		{
++		  /* Long form.	 */
++		  op = 0xde00 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
++		  add_unwind_opcode (op, 2);
++		}
++	    }
++	  hi_reg = reg - 1;
++	}
++    }
++
++  return;
++error:
++  ignore_rest_of_line ();
++}
+ 
+ /* Parse an unwind_save directive.
+    If the argument is non-zero, this is a .vsave directive.  */
+@@ -3624,6 +3760,8 @@
+     case REG_TYPE_MMXWR:  s_arm_unwind_save_mmxwr ();  return;
+     case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
+ 
++    case REG_TYPE_MVD:    s_arm_unwind_save_mvd (); return;    
++
+     default:
+       as_bad (_(".unwind_save does not support this kind of register"));
+       ignore_rest_of_line ();
+@@ -14256,8 +14394,8 @@
+   REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
+ 
+   /* Maverick DSP coprocessor registers.  */
+-  REGSET(mvf,MVF),  REGSET(mvd,MVD),  REGSET(mvfx,MVFX),  REGSET(mvdx,MVDX),
+-  REGSET(MVF,MVF),  REGSET(MVD,MVD),  REGSET(MVFX,MVFX),  REGSET(MVDX,MVDX),
++  REGSET(mv,MVD),  REGSET(mvf,MVF),  REGSET(mvd,MVD),  REGSET(mvfx,MVFX),  REGSET(mvdx,MVDX),
++  REGSET(MV,MVD),  REGSET(MVF,MVF),  REGSET(MVD,MVD),  REGSET(MVFX,MVFX),  REGSET(MVDX,MVDX),
+ 
+   REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
+   REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
diff --git a/recipes/chromium/chromium_svn.bb b/recipes/chromium/chromium_svn.bb
index 98f4f10881..ffeae9f15a 100644
--- a/recipes/chromium/chromium_svn.bb
+++ b/recipes/chromium/chromium_svn.bb
@@ -5,7 +5,7 @@ DEPENDS = "perl-native python-native flex-native gperf-native"
 
 PV = "0.0+svnr${SRCREV}"
 
-SRCREV = "1665"
+SRCREV = "17935"
 SRC_URI = "svn://src.chromium.org/svn/trunk/;module=src;proto=http"
 
 S = "${WORKDIR}/src/chrome"
diff --git a/recipes/dsplink/gstreamer-ti_svn.bb b/recipes/dsplink/gstreamer-ti_svn.bb
index bf52c63ba3..493e4fb59a 100644
--- a/recipes/dsplink/gstreamer-ti_svn.bb
+++ b/recipes/dsplink/gstreamer-ti_svn.bb
@@ -2,7 +2,7 @@ DEPENDS = "ti-codec-engine ti-dmai gstreamer gst-plugins-base gst-plugins-good g
 
 SRC_URI = "svn://gforge.ti.com/svn/gstreamer_ti/trunk;module=gstreamer_ti;proto=https;user=anonymous;pswd='' \
           "
-SRCREV = "225"
+SRCREV = "239"
 
 PR = "${MACHINE_KERNEL_PR}"
 
diff --git a/recipes/e17/expedite_svn.bb b/recipes/e17/expedite_svn.bb
index 1337487623..c4dfa5afed 100644
--- a/recipes/e17/expedite_svn.bb
+++ b/recipes/e17/expedite_svn.bb
@@ -1,9 +1,9 @@
 DESCRIPTION = "Expedite is a comprehensive benchmarking suite for Evas"
 DEPENDS = "eet evas"
-RDEPENDS = "libevas-engine-buffer libevas-engine-fb libevas-engine-software-generic libevas-engine-software-x11 libevas-loader-png"
+RDEPENDS = "evas-engine-buffer evas-engine-fb evas-engine-software-generic evas-engine-software-x11 evas-loader-png"
 LICENSE = "MIT BSD"
 PV = "0.6.0+svnr${SRCREV}"
-PR = "r0"
+PR = "r1"
 
 inherit e
 
diff --git a/recipes/e2fsprogs/e2fsprogs-native_1.38.bb b/recipes/e2fsprogs/e2fsprogs-native_1.38.bb
index 13fd2beb0c..cef0aa41e8 100644
--- a/recipes/e2fsprogs/e2fsprogs-native_1.38.bb
+++ b/recipes/e2fsprogs/e2fsprogs-native_1.38.bb
@@ -16,4 +16,5 @@ DEPENDS = ""
 
 do_stage () {
         oe_runmake install
+        install ${S}/lib/et/compile_et ${STAGING_BINDIR_NATIVE}
 }
diff --git a/recipes/geda/geda-docs_1.4.1.bb b/recipes/geda/geda-docs_1.4.3.bb
index a35d41514b..a35d41514b 100644
--- a/recipes/geda/geda-docs_1.4.1.bb
+++ b/recipes/geda/geda-docs_1.4.3.bb
diff --git a/recipes/geda/geda-examples_1.4.1.bb b/recipes/geda/geda-examples_1.4.3.bb
index a35d41514b..a35d41514b 100644
--- a/recipes/geda/geda-examples_1.4.1.bb
+++ b/recipes/geda/geda-examples_1.4.3.bb
diff --git a/recipes/geda/geda-gattrib_1.4.1.bb b/recipes/geda/geda-gattrib_1.4.3.bb
index af4ea94153..af4ea94153 100644
--- a/recipes/geda/geda-gattrib_1.4.1.bb
+++ b/recipes/geda/geda-gattrib_1.4.3.bb
diff --git a/recipes/geda/geda-gnetlist_1.4.1.bb b/recipes/geda/geda-gnetlist_1.4.3.bb
index 4f560d3d37..4f560d3d37 100644
--- a/recipes/geda/geda-gnetlist_1.4.1.bb
+++ b/recipes/geda/geda-gnetlist_1.4.3.bb
diff --git a/recipes/geda/geda-gschem_1.4.1.bb b/recipes/geda/geda-gschem_1.4.3.bb
index 7613f3c6a5..7613f3c6a5 100644
--- a/recipes/geda/geda-gschem_1.4.1.bb
+++ b/recipes/geda/geda-gschem_1.4.3.bb
diff --git a/recipes/geda/geda-gsymcheck_1.4.1.bb b/recipes/geda/geda-gsymcheck_1.4.3.bb
index 463da2de99..463da2de99 100644
--- a/recipes/geda/geda-gsymcheck_1.4.1.bb
+++ b/recipes/geda/geda-gsymcheck_1.4.3.bb
diff --git a/recipes/geda/geda-symbols_1.4.1.bb b/recipes/geda/geda-symbols_1.4.3.bb
index 4f560d3d37..4f560d3d37 100644
--- a/recipes/geda/geda-symbols_1.4.1.bb
+++ b/recipes/geda/geda-symbols_1.4.3.bb
diff --git a/recipes/geda/geda-utils_1.4.1.bb b/recipes/geda/geda-utils_1.4.3.bb
index ea61665d9d..ea61665d9d 100644
--- a/recipes/geda/geda-utils_1.4.1.bb
+++ b/recipes/geda/geda-utils_1.4.3.bb
diff --git a/recipes/geda/geda_1.4.1.bb b/recipes/geda/geda_1.4.3.bb
index ee9394d9f2..ee9394d9f2 100644
--- a/recipes/geda/geda_1.4.1.bb
+++ b/recipes/geda/geda_1.4.3.bb
diff --git a/recipes/geda/libgeda_1.4.1.bb b/recipes/geda/libgeda_1.4.3.bb
index a00a1d5cde..a00a1d5cde 100644
--- a/recipes/geda/libgeda_1.4.1.bb
+++ b/recipes/geda/libgeda_1.4.3.bb
diff --git a/recipes/glibc/glibc-2.4/glibc-crunch-eabi-force.patch b/recipes/glibc/glibc-2.4/glibc-crunch-eabi-force.patch
new file mode 100644
index 0000000000..b509b133c7
--- /dev/null
+++ b/recipes/glibc/glibc-2.4/glibc-crunch-eabi-force.patch
@@ -0,0 +1,133 @@
+diff -urN glibc-2.6.1/ports/sysdeps/arm/eabi/bits/fenv.h glibc-2.6.1/ports/sysdeps/arm/eabi/bits/fenv.h
+--- glibc-2.6.1/ports/sysdeps/arm/eabi/bits/fenv.h	2008-04-04 18:32:58.000000000 +1000
++++ glibc-2.6.1/ports/sysdeps/arm/eabi/bits/fenv.h	2008-04-07 10:40:28.000000000 +1000
+@@ -20,6 +20,8 @@
+ # error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
+ #endif
+ 
++#if 0
++
+ /* Define bits representing exceptions in the VFP FPU status word.  */
+ enum
+   {
+@@ -55,37 +57,50 @@
+ #define FE_TOWARDZERO FE_TOWARDZERO
+   };
+ 
++#endif
++
+ /* Define bits representing exceptions in the CRUNCH FPU status word.  */
+ enum
+   {
+     FE_CRUNCH_INVALID = (1),
+ #define FE_CRUNCH_INVALID FE_CRUNCH_INVALID
++#define FE_INVALID FE_CRUNCH_INVALID
++#define FE_DIVBYZERO 0
+     FE_CRUNCH_OVERFLOW = (4),
+ #define FE_CRUNCH_OVERFLOW FE_CRUNCH_OVERFLOW
++#define FE_OVERFLOW FE_CRUNCH_OVERFLOW
+     FE_CRUNCH_UNDERFLOW = (8),
+ #define FE_CRUNCH_UNDERFLOW FE_CRUNCH_UNDERFLOW
++#define FE_UNDERFLOW FE_CRUNCH_UNDERFLOW
+     FE_CRUNCH_INEXACT = (16),
+ #define FE_CRUNCH_INEXACT FE_CRUNCH_INEXACT
++#define FE_INEXACT FE_CRUNCH_INEXACT
+   };
+ 
+ /* Amount to shift by to convert an exception to a mask bit.  */
+ #define FE_CRUNCH_EXCEPT_SHIFT	5
++#define FE_EXCEPT_SHIFT FE_CRUNCH_EXCEPT_SHIFT
+ 
+ /* All supported exceptions, except DIVBYZERO.  */
+ #define FE_CRUNCH_ALL_EXCEPT	\
+ 	(FE_CRUNCH_INVALID | FE_CRUNCH_OVERFLOW | FE_CRUNCH_UNDERFLOW | FE_CRUNCH_INEXACT)
++#define FE_ALL_EXCEPT FE_CRUNCH_ALL_EXCEPT
+ 
+ /* CRUNCH supports all of the four defined rounding modes.  */
+ enum
+   {
+     FE_CRUNCH_TONEAREST = 0,
+ #define FE_CRUNCH_TONEAREST FE_CRUNCH_TONEAREST
++#define FE_TONEAREST FE_CRUNCH_TONEAREST
+     FE_CRUNCH_TOWARDZERO = 0x400,
+ #define FE_CRUNCH_TOWARDZERO FE_CRUNCH_TOWARDZERO
++#define FE_TOWARDZERO FE_CRUNCH_TOWARDZERO
+     FE_CRUNCH_DOWNWARD = 0x800,
+ #define FE_CRUNCH_DOWNWARD FE_CRUNCH_DOWNWARD
++#define FE_DOWNWARD FE_CRUNCH_DOWNWARD
+     FE_CRUNCH_UPWARD = 0xc00
+ #define FE_CRUNCH_UPWARD FE_CRUNCH_UPWARD
++#define FE_UPWARD FE_CRUNCH_UPWARD
+   };
+ 
+ 
+diff -urN glibc-2.6.1/ports/sysdeps/arm/eabi/fpu_control.h glibc-2.6.1/ports/sysdeps/arm/eabi/fpu_control.h
+--- glibc-2.6.1/ports/sysdeps/arm/eabi/fpu_control.h	2008-04-04 18:32:58.000000000 +1000
++++ glibc-2.6.1/ports/sysdeps/arm/eabi/fpu_control.h	2008-04-07 11:02:13.000000000 +1000
+@@ -20,6 +20,8 @@
+ #ifndef _FPU_CONTROL_H
+ #define _FPU_CONTROL_H
+ 
++#if 0
++
+ /* masking of interrupts */
+ #define _FPU_MASK_IM	0x00000100	/* invalid operation */
+ #define _FPU_MASK_ZM	0x00000200	/* divide by zero */
+@@ -45,6 +47,11 @@
+ #define _FPU_SETCW(cw) \
+   __asm__ __volatile__ ("mcr p10, 7, %0, cr1, cr0, 0" : : "r" (cw))
+ 
++#endif
++
+ /* CRUNCH SECTION */
+
++/* Type of the control word.  */
++typedef unsigned int fpu_control_t;
++ 
+ /* DSPSC register: (from EP9312 User's Guide)
+@@ -69,19 +73,27 @@
+ 
+ /* masking of interrupts */
+ #define _FPU_CRUNCH_MASK_IM	(1 << 5)	/* invalid operation */
++#define _FPU_MASK_IM _FPU_CRUNCH_MASK_IM
+ #define _FPU_CRUNCH_MASK_ZM	0       	/* divide by zero */ 
++#define _FPU_MASK_ZM _FPU_CRUNCH_MASK_ZM
+ #define _FPU_CRUNCH_MASK_OM	(1 << 7)    /* overflow */
++#define _FPU_MASK_OM _FPU_CRUNCH_MASK_OM
+ #define _FPU_CRUNCH_MASK_UM    (1 << 8)	/* underflow */
++#define _FPU_MASK_UM _FPU_CRUNCH_MASK_UM
+ #define _FPU_CRUNCH_MASK_PM	(1 << 9)	/* inexact */
++#define _FPU_MASK_PM _FPU_CRUNCH_MASK_PM
+ #define _FPU_CRUNCH_MASK_DM    0           /* denormalized operation */
++#undef _FPU_MASK_DM
+ 
+ /* Some bits in the FPSCR are not yet defined.  They must be preserved when
+    modifying the contents.  */
+ #define _FPU_CRUNCH_RESERVED	0x03000042
++#define _FPU_RESERVED _FPU_CRUNCH_RESERVED
+ #define _FPU_CRUNCH_DEFAULT    0x00b00000
++#define _FPU_DEFAULT _FPU_CRUNCH_DEFAULT
+ /* Default + exceptions enabled. */
+ #define _FPU_CRUNCH_IEEE	(_FPU_CRUNCH_DEFAULT | 0x000003a0)
+-
++#define _FPU_IEEE _FPU_CRUNCH_IEEE
+ 
+ /* Macros for accessing the hardware control word.  */
+ /*	cfmvr64l	%1, mvdx0    */
+@@ -103,6 +115,7 @@
+ 	: "=r" (cw), "=r" (__t1), "=r" (__t2)	\
+ 	);					\
+ })
++#define _FPU_GETCW(cw) _FPU_CRUNCH_GETCW(cw)
+ 
+ /* cfmvr64l	%1, mvdx0    */
+ /* cfmvr64h	%2, mvdx0    */
+@@ -123,7 +136,7 @@
+ 	: "=r" (__t1), "=r" (__t2) : "r" (cw)	\
+ 	);					\
+ })
+-
++#define _FPU_SETCW(cw) _FPU_CRUNCH_SETCW(cw)
+ 
+ /* Default control word set at startup.  */
+ extern fpu_control_t __fpu_control;
diff --git a/recipes/glibc/glibc-2.4/glibc-crunch-eabi-fraiseexcpt.patch b/recipes/glibc/glibc-2.4/glibc-crunch-eabi-fraiseexcpt.patch
new file mode 100644
index 0000000000..dcee3fad0a
--- /dev/null
+++ b/recipes/glibc/glibc-2.4/glibc-crunch-eabi-fraiseexcpt.patch
@@ -0,0 +1,88 @@
+diff -urN glibc-2.5/ports/sysdeps/arm/eabi/fraiseexcpt.c glibc-2.5/ports/sysdeps/arm/eabi-new/fraiseexcpt.c
+--- glibc-2.5/ports/sysdeps/arm/eabi/fraiseexcpt.c	2005-10-11 01:29:32.000000000 +1000
++++ glibc-2.5/ports/sysdeps/arm/eabi-new/fraiseexcpt.c	2008-04-14 17:21:09.000000000 +1000
+@@ -25,6 +25,7 @@
+ #include <ldsodefs.h>
+ #include <dl-procinfo.h>
+ #include <sysdep.h>
++#include <math.h>
+ 
+ int
+ feraiseexcept (int excepts)
+@@ -105,8 +105,74 @@
+ 
+   if (GLRO (dl_hwcap) & HWCAP_ARM_CRUNCH)
+     {
+-      /* Unsupported, for now.  */
+-      return 1;
++      unsigned int dspsc;
++      const float fp_zero = 0.0, fp_one = 1.0, fp_max = FLT_MAX,
++                  fp_min = FLT_MIN, fp_1e32 = 1.0e32f, fp_two = 2.0,
++		  fp_three = 3.0, fp_inf = HUGE_VALF;
++
++      /* Raise exceptions represented by EXPECTS.  But we must raise only
++	 one signal at a time.  It is important that if the overflow/underflow
++	 exception and the inexact exception are given at the same time,
++	 the overflow/underflow exception follows the inexact exception.  After
++	 each exception we read from the dspsc, to force the exception to be
++	 raised immediately.  */
++
++      /* There are additional complications because this file may be compiled
++         without CRUNCH support enabled, and we also can't assume that the
++	 assembler has CRUNCH instructions enabled. To get around this we use the
++	 generic coprocessor mnemonics and avoid asking GCC to put float values
++	 in CRUNCH registers.  */
++
++      /* First: invalid exception.  */
++      if (FE_CRUNCH_INVALID & excepts)
++	/* (ZERO * INFINITY) */
++	__asm__ __volatile__ (
++	  "ldc p4, cr0, %1\n\t"                        /* cflds mvf0, %1  */
++	  "ldc p4, cr1, %2\n\t"                        /* cflds mvf1, %2  */
++	  "cdp p4, 1, cr0, cr0, cr1, 0\n\t"            /* cfmuls mvf0, mvf0, mvf1  */
++	  "cdp p4, 0, cr0, cr0, cr0, 7\n\t"            /* cfmv32sc mvdx0, dspsc */
++      "mrc p5, 0, %0, cr0, cr0, 0" : "=r" (dspsc) /* cfmvr64l dspsc, mvdx0 */
++			                : "m" (fp_zero), "m" (fp_inf)
++					: "s0", "s1");
++
++      /* Next: overflow.  */
++      if (FE_CRUNCH_OVERFLOW & excepts)
++	/* There's no way to raise overflow without also raising inexact.  */
++	__asm__ __volatile__ (
++	  "ldc p4, cr0, %1\n\t"                        /* cflds mvf0, %1  */
++	  "ldc p4, cr1, %2\n\t"                        /* cflds mvf1, %2  */
++	  "cdp p4, 3, cr0, cr0, cr1, 4\n\t"            /* cfadds mvf0, mvf0, mvf1  */
++	  "cdp p4, 0, cr0, cr0, cr0, 7\n\t"            /* cfmv32sc mvdx0, dspsc */
++      "mrc p5, 0, %0, cr0, cr0, 0" : "=r" (dspsc) /* cfmvr64l dspsc, mvdx0  */
++			                : "m" (fp_max), "m" (fp_1e32)
++					: "s0", "s1");
++
++      /* Next: underflow.  */
++      if (FE_CRUNCH_UNDERFLOW & excepts)
++	/* (FLT_MIN * FLT_MIN) */
++	__asm__ __volatile__ (
++	  "ldc p4, cr0, %1\n\t"                        /* cflds mvf0, %1  */
++	  "ldc p4, cr1, %2\n\t"                        /* cflds mvf1, %2  */
++	  "cdp p4, 1, cr0, cr0, cr1, 0\n\t"            /* cfmul mvf0, mvf0, mvf1  */
++	  "cdp p4, 0, cr0, cr0, cr0, 7\n\t"            /* cfmv32sc mvdx0, dspsc */
++      "mrc p5, 0, %0, cr0, cr0, 0" : "=r" (dspsc) /* cfmvr64l dspsc, mvdx0 */
++			                : "m" (fp_min), "m" (fp_min)
++					: "s0", "s1");
++
++      /* Last: inexact.  */
++      if (FE_CRUNCH_INEXACT & excepts)
++	/* There's no way to raise inexact without also raising overflow.  */
++	__asm__ __volatile__ (
++	  "ldc p4, cr0, %1\n\t"                        /* cflds mvf0, %1  */
++	  "ldc p4, cr1, %2\n\t"                        /* cflds mvf1, %2  */
++	  "cdp p4, 3, cr0, cr0, cr1, 4\n\t"            /* cfadds mvf0, mvf0, mvf1  */
++	  "cdp p4, 0, cr0, cr0, cr0, 7\n\t"            /* cfmv32sc mvdx0, dspsc */
++      "mrc p5, 0, %0, cr0, cr0, 0" : "=r" (dspsc) /* cfmvr64l dspsc, mvdx0 */
++			                : "m" (fp_max), "m" (fp_1e32)
++					: "s0", "s1");
++
++      /* Success.  */
++      return 0;
+     }
+ 
+   /* Unsupported, so fail.  */
diff --git a/recipes/glibc/glibc-2.4/glibc-crunch-eabi-setjmp_longjmp.patch b/recipes/glibc/glibc-2.4/glibc-crunch-eabi-setjmp_longjmp.patch
new file mode 100644
index 0000000000..cf4ed6060b
--- /dev/null
+++ b/recipes/glibc/glibc-2.4/glibc-crunch-eabi-setjmp_longjmp.patch
@@ -0,0 +1,112 @@
+--- glibc-2.5/ports/sysdeps/arm/eabi/setjmp.S	2006-09-22 04:39:51.000000000 +1000
++++ glibc-2.5/ports/sysdeps/arm/eabi/setjmp.S	2007-05-24 13:31:20.000000000 +1000
+@@ -74,6 +74,34 @@
+ 	stcl	p1, cr15, [r12], #8
+ Lno_iwmmxt:
+ 
++	tst	a3, #HWCAP_ARM_CRUNCH
++	beq	Lno_crunch
++
++	/* Save the call-preserved crunch registers.  */
++	/* Following instructions are cfstrd cr10, [ip], #8 (etc.)  */
++	/* stcl	p4, cr4,  [r12], #8 */
++	/* stcl	p4, cr5,  [r12], #8 */
++	/* stcl	p4, cr6,  [r12], #8 */
++	/* stcl	p4, cr7,  [r12], #8 */
++	stcl	p4, cr8,  [r12], #8
++	stcl	p4, cr9,  [r12], #8
++	stcl	p4, cr10, [r12], #8
++	stcl	p4, cr11, [r12], #8