linux 2.6.27: add support for ts72xx and make it default kernel

Signed-off-by: Petr Štetiar <ynezz@true.cz>
Acked-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>

32 files changed, 8077 insertions, 1 deletions

diff --git a/recipes/linux/linux-2.6.27/ts72xx/0001-TS72xx-update-memory-map-comments.patch b/recipes/linux/linux-2.6.27/ts72xx/0001-TS72xx-update-memory-map-comments.patch
new file mode 100644
index 0000000000..3eab1ca0d7
--- /dev/null
+++ b/recipes/linux/linux-2.6.27/ts72xx/0001-TS72xx-update-memory-map-comments.patch
@@ -0,0 +1,45 @@
+From dd631acb622a6c7c6355945c446bd07085ade99f Mon Sep 17 00:00:00 2001
+From: Matthieu Crapet <mcrapet@gmail.com>
+Date: Sun, 4 Jan 2009 14:02:33 +0100
+Subject: [PATCH] TS72xx update memory map comments
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Petr Štetiar <ynezz@true.cz>
+---
+ arch/arm/mach-ep93xx/include/mach/ts72xx.h |   13 ++++++++++++-
+ 1 files changed, 12 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/mach-ep93xx/include/mach/ts72xx.h b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
+index 30b318a..99c4e48 100644
+--- a/arch/arm/mach-ep93xx/include/mach/ts72xx.h
++++ b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
+@@ -8,12 +8,23 @@
+  * virt		phys		size
+  * febff000	22000000	4K	model number register
+  * febfe000	22400000	4K	options register
+- * febfd000	22800000	4K	options register #2
++ * febfd000	22800000	4K	options register #2 (JP6 and TS-9420 flags)
+  * febfc000	[67]0000000	4K	NAND data register
+  * febfb000	[67]0400000	4K	NAND control register
+  * febfa000	[67]0800000	4K	NAND busy register
+  * febf9000	10800000	4K	TS-5620 RTC index register
+  * febf8000	11700000	4K	TS-5620 RTC data register
++ * febf7000	23800000	4K	CPLD watchdog (control register)
++ * febf6000	23c00000	4K	CPLD watchdog (feed register)
++ * febf5000	23400000	4K	PLD version (3 bits)
++ * febf4000	22c00000	4K	RS-485 control register
++ * febf3000	23000000	4K	RS-485 mode register
++ * febf2000	10800000	4K	jumpers/max197 busy bit/COM1 dcd register (8-bit, read only)
++ * febf1000	10f00000	4K	max197 sample/control register (16-bit read/8-bit write)
++ * febf0000	11e00000	4K	PC/104 8-bit I/O
++ * febef000	21e00000	4K	PC/104 16-bit I/O
++ * fea00000	11a00000	1MB	PC/104 8-bit memory
++ * fe900000	21a00000	1MB	PC/104 16-bit memory
+  */
+ 
+ #define TS72XX_MODEL_PHYS_BASE		0x22000000
+-- 
+1.6.0.4
+
diff --git a/recipes/linux/linux-2.6.27/ts72xx/0002-GPIO-fix.patch b/recipes/linux/linux-2.6.27/ts72xx/0002-GPIO-fix.patch
new file mode 100644
index 0000000000..006321efd5
--- /dev/null
+++ b/recipes/linux/linux-2.6.27/ts72xx/0002-GPIO-fix.patch
@@ -0,0 +1,47 @@
+From 9c7b38ef5e6843521c71eadefdba8cfa0aa607b4 Mon Sep 17 00:00:00 2001
+From: Matthieu Crapet <mcrapet@gmail.com>
+Date: Sun, 4 Jan 2009 00:41:38 +0100
+Subject: [PATCH] GPIO fix
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Petr Štetiar <ynezz@true.cz>
+---
+ arch/arm/mach-ep93xx/core.c |    2 +-
+ arch/arm/mach-ep93xx/gpio.c |    4 ++--
+ 2 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
+index f99f436..d6967de 100644
+--- a/arch/arm/mach-ep93xx/core.c
++++ b/arch/arm/mach-ep93xx/core.c
+@@ -157,7 +157,7 @@ static unsigned char gpio_int_type2[3];
+ static const u8 int_type1_register_offset[3]	= { 0x90, 0xac, 0x4c };
+ static const u8 int_type2_register_offset[3]	= { 0x94, 0xb0, 0x50 };
+ static const u8 eoi_register_offset[3]		= { 0x98, 0xb4, 0x54 };
+-static const u8 int_en_register_offset[3]	= { 0x9c, 0xb8, 0x5c };
++static const u8 int_en_register_offset[3]	= { 0x9c, 0xb8, 0x58 };
+ 
+ void ep93xx_gpio_update_int_params(unsigned port)
+ {
+diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
+index 0f3fb87..468d523 100644
+--- a/arch/arm/mach-ep93xx/gpio.c
++++ b/arch/arm/mach-ep93xx/gpio.c
+@@ -141,10 +141,10 @@ static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
+ static struct ep93xx_gpio_chip ep93xx_gpio_banks[] = {
+ 	EP93XX_GPIO_BANK("A", 0x00, 0x10, 0),
+ 	EP93XX_GPIO_BANK("B", 0x04, 0x14, 8),
+-	EP93XX_GPIO_BANK("C", 0x30, 0x34, 40),
++	EP93XX_GPIO_BANK("C", 0x08, 0x18, 40),
+ 	EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24),
+ 	EP93XX_GPIO_BANK("E", 0x20, 0x24, 32),
+-	EP93XX_GPIO_BANK("F", 0x08, 0x18, 16),
++	EP93XX_GPIO_BANK("F", 0x30, 0x34, 16),
+ 	EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48),
+ 	EP93XX_GPIO_BANK("H", 0x40, 0x44, 56),
+ };
+-- 
+1.6.0.4
+
diff --git a/recipes/linux/linux-2.6.27/ts72xx/0003-Debounce-IRQ.patch b/recipes/linux/linux-2.6.27/ts72xx/0003-Debounce-IRQ.patch
new file mode 100644
index 0000000000..21410ab7f0
--- /dev/null
+++ b/recipes/linux/linux-2.6.27/ts72xx/0003-Debounce-IRQ.patch
@@ -0,0 +1,97 @@
+From 51bba77f0953f87a88a8fce9fb8827bdba57a2c5 Mon Sep 17 00:00:00 2001
+From: Matthieu Crapet <mcrapet@gmail.com>
+Date: Sun, 4 Jan 2009 00:42:43 +0100
+Subject: [PATCH] Debounce IRQ
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Petr Štetiar <ynezz@true.cz>
+---
+ arch/arm/mach-ep93xx/core.c                     |   18 ++++++++++++++++++
+ arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |    3 +++
+ arch/arm/mach-ep93xx/include/mach/gpio.h        |    2 ++
+ 3 files changed, 23 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
+index d6967de..1928c93 100644
+--- a/arch/arm/mach-ep93xx/core.c
++++ b/arch/arm/mach-ep93xx/core.c
+@@ -152,12 +152,14 @@ static unsigned char gpio_int_unmasked[3];
+ static unsigned char gpio_int_enabled[3];
+ static unsigned char gpio_int_type1[3];
+ static unsigned char gpio_int_type2[3];
++static unsigned char gpio_int_debouce[3];
+ 
+ /* Port ordering is: A B F */
+ static const u8 int_type1_register_offset[3]	= { 0x90, 0xac, 0x4c };
+ static const u8 int_type2_register_offset[3]	= { 0x94, 0xb0, 0x50 };
+ static const u8 eoi_register_offset[3]		= { 0x98, 0xb4, 0x54 };
+ static const u8 int_en_register_offset[3]	= { 0x9c, 0xb8, 0x58 };
++static const u8 int_debounce_register_offset[3]	= { 0xa8, 0xc4, 0x64 };
+ 
+ void ep93xx_gpio_update_int_params(unsigned port)
+ {
+@@ -180,6 +182,22 @@ void ep93xx_gpio_int_mask(unsigned line)
+ 	gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
+ }
+ 
++void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
++{
++	int line = irq_to_gpio(irq);
++	int port = line >> 3;
++	int port_mask = 1 << (line & 7);
++
++	if (enable)
++		gpio_int_debouce[port] |= port_mask;
++	else
++		gpio_int_debouce[port] &= ~port_mask;
++
++	__raw_writeb(gpio_int_debouce[port],
++		EP93XX_GPIO_REG(int_debounce_register_offset[port]));
++}
++EXPORT_SYMBOL(ep93xx_gpio_int_debounce);
++
+ /*************************************************************************
+  * EP93xx IRQ handling
+  *************************************************************************/
+diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+index 9f4458c..5582138 100644
+--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
++++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+@@ -78,16 +78,19 @@
+ #define EP93XX_GPIO_F_INT_ACK		EP93XX_GPIO_REG(0x54)
+ #define EP93XX_GPIO_F_INT_ENABLE	EP93XX_GPIO_REG(0x58)
+ #define EP93XX_GPIO_F_INT_STATUS	EP93XX_GPIO_REG(0x5c)
++#define EP93XX_GPIO_F_INT_DEBOUNCE	EP93XX_GPIO_REG(0x64)
+ #define EP93XX_GPIO_A_INT_TYPE1		EP93XX_GPIO_REG(0x90)
+ #define EP93XX_GPIO_A_INT_TYPE2		EP93XX_GPIO_REG(0x94)
+ #define EP93XX_GPIO_A_INT_ACK		EP93XX_GPIO_REG(0x98)
+ #define EP93XX_GPIO_A_INT_ENABLE	EP93XX_GPIO_REG(0x9c)
+ #define EP93XX_GPIO_A_INT_STATUS	EP93XX_GPIO_REG(0xa0)
++#define EP93XX_GPIO_A_INT_DEBOUNCE	EP93XX_GPIO_REG(0xa8)
+ #define EP93XX_GPIO_B_INT_TYPE1		EP93XX_GPIO_REG(0xac)
+ #define EP93XX_GPIO_B_INT_TYPE2		EP93XX_GPIO_REG(0xb0)
+ #define EP93XX_GPIO_B_INT_ACK		EP93XX_GPIO_REG(0xb4)
+ #define EP93XX_GPIO_B_INT_ENABLE	EP93XX_GPIO_REG(0xb8)
+ #define EP93XX_GPIO_B_INT_STATUS	EP93XX_GPIO_REG(0xbc)
++#define EP93XX_GPIO_B_INT_DEBOUNCE	EP93XX_GPIO_REG(0xc4)
+ 
+ #define EP93XX_AAC_BASE			(EP93XX_APB_VIRT_BASE + 0x00080000)
+ 
+diff --git a/arch/arm/mach-ep93xx/include/mach/gpio.h b/arch/arm/mach-ep93xx/include/mach/gpio.h
+index f702041..0a1498a 100644
+--- a/arch/arm/mach-ep93xx/include/mach/gpio.h
++++ b/arch/arm/mach-ep93xx/include/mach/gpio.h
+@@ -99,6 +99,8 @@
+ /* maximum value for irq capable line identifiers */
+ #define EP93XX_GPIO_LINE_MAX_IRQ	EP93XX_GPIO_LINE_F(7)
+ 
++extern void ep93xx_gpio_int_debounce(unsigned int irq, int enable);
++
+ /* new generic GPIO API - see Documentation/gpio.txt */
+ 
+ #include <asm-generic/gpio.h>
+-- 
+1.6.0.4
+
diff --git a/recipes/linux/linux-2.6.27/ts72xx/0004-OHCI-fix.patch b/recipes/linux/linux-2.6.27/ts72xx/0004-OHCI-fix.patch
new file mode 100644
index 0000000000..1482e2dddf
--- /dev/null
+++ b/recipes/linux/linux-2.6.27/ts72xx/0004-OHCI-fix.patch
@@ -0,0 +1,39 @@
+From 06e0fdf41288a6d54b821671593195ea27deba8b Mon Sep 17 00:00:00 2001
+From: Matthieu Crapet <mcrapet@gmail.com>
+Date: Sun, 4 Jan 2009 00:54:35 +0100
+Subject: [PATCH] OHCI fix
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Petr Štetiar <ynezz@true.cz>
+---
+ arch/arm/mach-ep93xx/core.c |    5 +++--
+ 1 files changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
+index 1928c93..24b24c7 100644
+--- a/arch/arm/mach-ep93xx/core.c
++++ b/arch/arm/mach-ep93xx/core.c
+@@ -32,6 +32,7 @@
+ #include <linux/termios.h>
+ #include <linux/amba/bus.h>
+ #include <linux/amba/serial.h>
++#include <linux/dma-mapping.h>
+ 
+ #include <asm/types.h>
+ #include <asm/setup.h>
+@@ -472,8 +473,8 @@ static struct platform_device ep93xx_ohci_device = {
+ 	.name		= "ep93xx-ohci",
+ 	.id		= -1,
+ 	.dev		= {
+-		.dma_mask		= (void *)0xffffffff,
+-		.coherent_dma_mask	= 0xffffffff,
++		.dma_mask = &ep93xx_ohci_device.dev.coherent_dma_mask,
++		.coherent_dma_mask = DMA_BIT_MASK(32),
+ 	},
+ 	.num_resources	= ARRAY_SIZE(ep93xx_ohci_resources),
+ 	.resource	= ep93xx_ohci_resources,
+-- 
+1.6.0.4
+
diff --git a/recipes/linux/linux-2.6.27/ts72xx/0005-Fix-wrong-machine-ID-passed-from-RedBoot.patch b/recipes/linux/linux-2.6.27/ts72xx/0005-Fix-wrong-machine-ID-passed-from-RedBoot.patch
new file mode 100644
index 0000000000..e17f945ef6
--- /dev/null
+++ b/recipes/linux/linux-2.6.27/ts72xx/0005-Fix-wrong-machine-ID-passed-from-RedBoot.patch
@@ -0,0 +1,28 @@
+From 22ce7d90cb3c58be44ebb0fcb3f1f5ca8af83d59 Mon Sep 17 00:00:00 2001
+From: =?utf-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz>
+Date: Sat, 3 Jan 2009 21:33:53 +0100
+Subject: [PATCH] Fix wrong machine ID passed from RedBoot
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Petr Štetiar <ynezz@true.cz>
+---
+ arch/arm/kernel/head.S |    1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
+index bff4c6e..bda4eb4 100644
+--- a/arch/arm/kernel/head.S
++++ b/arch/arm/kernel/head.S
+@@ -83,6 +83,7 @@ ENTRY(stext)
+ 	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
+ 	movs	r10, r5				@ invalid processor (r5=0)?
+ 	beq	__error_p			@ yes, error 'p'
++	ldr	r1, =0x000002a1			@ mach-type = TS-7250
+ 	bl	__lookup_machine_type		@ r5=machinfo
+ 	movs	r8, r5				@ invalid machine (r5=0)?
+ 	beq	__error_a			@ yes, error 'a'
+-- 
+1.6.0.4
+
diff --git a/recipes/linux/linux-2.6.27/ts72xx/0006-Force-the-nF-bit-on.patch b/recipes/linux/linux-2.6.27/ts72xx/0006-Force-the-nF-bit-on.patch
new file mode 100644
index 0000000000..db96acc060
--- /dev/null
+++ b/recipes/linux/linux-2.6.27/ts72xx/0006-Force-the-nF-bit-on.patch
@@ -0,0 +1,33 @@
+From 9852d9654b25b396cf5f31de376a2c211805db8b Mon Sep 17 00:00:00 2001
+From: =?utf-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz>
+Date: Sat, 3 Jan 2009 21:35:03 +0100
+Subject: [PATCH] Force the nF bit on
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+Usually this is set by the bootrom.  If it is not set, then the CPU core will
+run from HCLK instead of FCLK, and performance will suffer. If you see
+BogoMIPS of about 1/4 of your CPU clock, try turning this on; your performance
+should double.
+
+Signed-off-by: Petr Štetiar <ynezz@true.cz>
+---
+ arch/arm/mm/proc-arm920.S |    1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
+index 28cdb06..12f59db 100644
+--- a/arch/arm/mm/proc-arm920.S
++++ b/arch/arm/mm/proc-arm920.S
+@@ -395,6 +395,7 @@ __arm920_setup:
+ 	mrc	p15, 0, r0, c1, c0		@ get control register v4
+ 	bic	r0, r0, r5
+ 	orr	r0, r0, r6
++	orr     r0, r0, #0x40000000
+ 	mov	pc, lr
+ 	.size	__arm920_setup, . - __arm920_setup
+ 
+-- 
+1.6.0.4
+
diff --git a/recipes/linux/linux-2.6.27/ts72xx/0007-Use-CPLD-watchdog-to-reset.patch b/recipes/linux/linux-2.6.27/ts72xx/0007-Use-CPLD-watchdog-to-reset.patch
new file mode 100644
index 0000000000..c2fbd5c407
--- /dev/null
+++ b/recipes/linux/linux-2.6.27/ts72xx/0007-Use-CPLD-watchdog-to-reset.patch
@@ -0,0 +1,54 @@
+From fca24d7cd93b7282d139cb91c0f4d62b1a95a985 Mon Sep 17 00:00:00 2001
+From: =?utf-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz>
+Date: Sat, 3 Jan 2009 21:36:36 +0100
+Subject: [PATCH] Use CPLD watchdog to reset
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+Use CPLD watchdog to reset the machine instead of buggy ep93xx one, which
+sometimes get stuck...
+
+Signed-off-by: Petr Štetiar <ynezz@true.cz>
+---
+ arch/arm/mach-ep93xx/include/mach/system.h |   17 ++++++++++++-----
+ 1 files changed, 12 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/mach-ep93xx/include/mach/system.h b/arch/arm/mach-ep93xx/include/mach/system.h
+index 67789d0..5d85094 100644
+--- a/arch/arm/mach-ep93xx/include/mach/system.h
++++ b/arch/arm/mach-ep93xx/include/mach/system.h
+@@ -3,6 +3,7 @@
+  */
+ 
+ #include <mach/hardware.h>
++#include <asm/mach-types.h>
+ 
+ static inline void arch_idle(void)
+ {
+@@ -15,11 +16,17 @@ static inline void arch_reset(char mode)
+ 
+ 	local_irq_disable();
+ 
+-	devicecfg = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
+-	__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
+-	__raw_writel(devicecfg | 0x80000000, EP93XX_SYSCON_DEVICE_CONFIG);
+-	__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
+-	__raw_writel(devicecfg & ~0x80000000, EP93XX_SYSCON_DEVICE_CONFIG);
++	if (machine_is_ts72xx()) {
++		__raw_writeb(0x5, TS72XX_WATCHDOG_FEED_PHYS_BASE);
++		__raw_writeb(0x1, TS72XX_WATCHDOG_CONTROL_PHYS_BASE);
++	} else {
++		devicecfg = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
++		__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
++		__raw_writel(devicecfg | 0x80000000, EP93XX_SYSCON_DEVICE_CONFIG);
++		__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
++		__raw_writel(devicecfg & ~0x80000000, EP93XX_SYSCON_DEVICE_CONFIG);
++	}
++
+ 
+ 	while (1)
+ 		;
+-- 
+1.6.0.4
+
diff --git a/recipes/linux/linux-2.6.27/ts72xx/0008-Fix-UART-clocks.patch b/recipes/linux/linux-2.6.27/ts72xx/0008-Fix-UART-clocks.patch
new file mode 100644
index 0000000000..43848478f8
--- /dev/null
+++ b/recipes/linux/linux-2.6.27/ts72xx/0008-Fix-UART-clocks.patch
@@ -0,0 +1,99 @@
+From 1a86fa006baad26dcb70645e9d2a965f956a7189 Mon Sep 17 00:00:00 2001
+From: Lennert Buytenhek <buytenh@wantstofly.org>
+Date: Sat, 3 Jan 2009 21:51:11 +0100
+Subject: [PATCH] Fix UART clocks
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+Hackishly enable all UART clocks before uncompressing the kernel,
+so that using ttyAM1 or ttyAM2 as console can work. Force UARTBAUD
+on before uncompressing.
+
+Signed-off-by: Petr Štetiar <ynezz@true.cz>
+---
+ arch/arm/mach-ep93xx/include/mach/uncompress.h |   65 ++++++++++++++++++++++++
+ 1 files changed, 65 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/mach-ep93xx/include/mach/uncompress.h
+index 1fd2f17..ecdfd64 100644
+--- a/arch/arm/mach-ep93xx/include/mach/uncompress.h
++++ b/arch/arm/mach-ep93xx/include/mach/uncompress.h
+@@ -77,9 +77,74 @@ static void ethernet_reset(void)
+ }
+ 
+ 
++/*
++ * We don't have clock management for the UARTs (amba-pl010)
++ * yet, so hackily enable all UART clocks here for now.
++ */
++#define PHYS_SYSCON_DEVICE_CONFIG	0x80930080
++#define PHYS_SYSCON_SWLOCK		0x809300c0
++
++static void enable_all_uart_clocks(void)
++{
++	unsigned int v;
++
++	v = __raw_readl(PHYS_SYSCON_DEVICE_CONFIG);
++	__raw_writel(0xaa, PHYS_SYSCON_SWLOCK);
++	__raw_writel(v | 0x01140000, PHYS_SYSCON_DEVICE_CONFIG);
++}
++
++
++/*
++ * Some bootloaders don't turn on the UARTBAUD bit, which means that
++ * the UARTs will be running off a divided 7.3728 MHz clock instead of
++ * the 14.7456 MHz peripheral clock when linux boots.
++ *
++ * We detect that condition here and fix it by turning on UARTBAUD, and
++ * then reprogramming the divisors on all enabled UARTs to twice what
++ * they were before we turned UARTBAUD on, to preserve the programmed
++ * baud rate.
++ */
++#define PHYS_SYSCON_CLOCK_CONTROL	0x80930004
++#define SYSCON_CLOCK_UARTBAUD		0x20000000
++#define PHYS_UART1_BASE			0x808c0000
++#define PHYS_UART2_BASE			0x808d0000
++#define PHYS_UART3_BASE			0x808e0000
++
++static void uart_divisor_times_two(unsigned int base)
++{
++	u16 divisor;
++
++	divisor = __raw_readb(base + 0x0c) << 8;
++	divisor |= __raw_readb(base + 0x10);
++	if (divisor) {
++		divisor = (2 * (divisor + 1)) - 1;
++		__raw_writeb(divisor >> 8, base + 0x0c);
++		__raw_writeb(divisor & 0xff, base + 0x10);
++		__raw_writeb(__raw_readb(base + 0x08), base + 0x08);
++	}
++}
++
++static void fix_uart_base(void)
++{
++	unsigned int v;
++
++	v = __raw_readl(PHYS_SYSCON_CLOCK_CONTROL);
++	if ((v & SYSCON_CLOCK_UARTBAUD) == 0) {
++		v |= SYSCON_CLOCK_UARTBAUD;
++		__raw_writel(v, PHYS_SYSCON_CLOCK_CONTROL);
++
++		uart_divisor_times_two(PHYS_UART1_BASE);
++		uart_divisor_times_two(PHYS_UART2_BASE);
++		uart_divisor_times_two(PHYS_UART3_BASE);
++	}
++}
++
++
+ static void arch_decomp_setup(void)
+ {
+ 	ethernet_reset();
++	enable_all_uart_clocks();
++	fix_uart_base();
+ }
+ 
+ #define arch_decomp_wdog()
+-- 
+1.6.0.4
+
diff --git a/recipes/linux/linux-2.6.27/ts72xx/0009-CPU-info-and-board-revision.patch b/recipes/linux/linux-2.6.27/ts72xx/0009-CPU-info-and-board-revision.patch
new file mode 100644
index 0000000000..5dd360a796
--- /dev/null
+++ b/recipes/linux/linux-2.6.27/ts72xx/0009-CPU-info-and-board-revision.patch
@@ -0,0 +1,64 @@
+From 3f48e4dc8affb4ddfe7b1ca8f209003cfb8ac314 Mon Sep 17 00:00:00 2001
+From: Matthieu Crapet <mcrapet@gmail.com>
+Date: Sat, 3 Jan 2009 22:19:21 +0100
+Subject: [PATCH] CPU info and board revision
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+Adds support for SoC's unique ID (Maverick Key) in /proc/cpuinfo and
+information about board revision.
+
+Signed-off-by: Petr Štetiar <ynezz@true.cz>
+---
+ arch/arm/kernel/setup.c                         |    9 +++++++++
+ arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |    3 +++
+ 2 files changed, 12 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
+index 2ca7038..891fcf3 100644
+--- a/arch/arm/kernel/setup.c
++++ b/arch/arm/kernel/setup.c
+@@ -994,9 +994,18 @@ static int c_show(struct seq_file *m, void *v)
+ 	seq_puts(m, "\n");
+ 
+ 	seq_printf(m, "Hardware\t: %s\n", machine_name);
++
++#if defined(CONFIG_ARCH_EP93XX)
++#include <mach/ep93xx-regs.h>
++	seq_printf(m, "Revision\t: %04x\n",
++		   *((unsigned int *)EP93XX_SYSCON_CHIPID) >> 28);
++	seq_printf(m, "Serial\t\t: %016x\n",
++		   *((unsigned int *)EP93XX_SECURITY_UNIQID));
++#else
+ 	seq_printf(m, "Revision\t: %04x\n", system_rev);
+ 	seq_printf(m, "Serial\t\t: %08x%08x\n",
+ 		   system_serial_high, system_serial_low);
++#endif
+ 
+ 	return 0;
+ }
+diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+index 5582138..e26b41b 100644
+--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
++++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+@@ -70,6 +70,8 @@
+ #define EP93XX_I2S_BASE			(EP93XX_APB_VIRT_BASE + 0x00020000)
+ 
+ #define EP93XX_SECURITY_BASE		(EP93XX_APB_VIRT_BASE + 0x00030000)
++#define EP93XX_SECURITY_REG(x)		(EP93XX_SECURITY_BASE + (x))
++#define EP93XX_SECURITY_UNIQID		EP93XX_SECURITY_REG(0x2440)
+ 
+ #define EP93XX_GPIO_BASE		(EP93XX_APB_VIRT_BASE + 0x00040000)
+ #define EP93XX_GPIO_REG(x)		(EP93XX_GPIO_BASE + (x))
+@@ -129,6 +131,7 @@
+ #define EP93XX_SYSCON_DEVICE_CONFIG	EP93XX_SYSCON_REG(0x80)
+ #define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE	0x00800000
+ #define EP93XX_SYSCON_SWLOCK		EP93XX_SYSCON_REG(0xc0)
++#define EP93XX_SYSCON_CHIPID		EP93XX_SYSCON_REG(0x94)
+ 
+ #define EP93XX_WATCHDOG_BASE		(EP93XX_APB_VIRT_BASE + 0x00140000)
+ 
+-- 
+1.6.0.4
+
diff --git a/recipes/linux/linux-2.6.27/ts72xx/0010-GPIO-leds.patch b/recipes/linux/linux-2.6.27/ts72xx/0010-GPIO-leds.patch
new file mode 100644
index 0000000000..74c4490666
--- /dev/null
+++ b/recipes/linux/linux-2.6.27/ts72xx/0010-GPIO-leds.patch
@@ -0,0 +1,72 @@
+From 11158bb59b2d848f1827d4ed59d4ca20d1f91d11 Mon Sep 17 00:00:00 2001
+From: Matthieu Crapet <mcrapet@gmail.com>
+Date: Sun, 4 Jan 2009 00:58:03 +0100
+Subject: [PATCH] GPIO leds
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Petr Štetiar <ynezz@true.cz>
+---
+ arch/arm/mach-ep93xx/core.c |   31 +++++++++++++++++++++++++++++++
+ 1 files changed, 31 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
+index 24b24c7..88afbe6 100644
+--- a/arch/arm/mach-ep93xx/core.c
++++ b/arch/arm/mach-ep93xx/core.c
+@@ -33,6 +33,7 @@
+ #include <linux/amba/bus.h>
+ #include <linux/amba/serial.h>
+ #include <linux/dma-mapping.h>
++#include <linux/leds.h>
+ 
+ #include <asm/types.h>
+ #include <asm/setup.h>
+@@ -480,6 +481,35 @@ static struct platform_device ep93xx_ohci_device = {
+ 	.resource	= ep93xx_ohci_resources,
+ };
+ 
++
++static const struct gpio_led ep93xx_led_pins[] = {
++  {
++    .name = "green",
++    .gpio = EP93XX_GPIO_LINE_GRLED,
++    .active_low = 0,
++    .default_trigger = "heartbeat",
++  },
++  {
++    .name = "red",
++    .gpio = EP93XX_GPIO_LINE_RDLED,
++    .active_low = 0,
++  }
++};
++
++static const struct gpio_led_platform_data ep93xx_led_data = {
++  .num_leds = ARRAY_SIZE(ep93xx_led_pins),
++  .leds = (void *)ep93xx_led_pins,
++};
++
++static struct platform_device ep93xx_gpio_leds = {
++  .name = "leds-gpio",
++  .id = -1,
++  .dev = {
++    .platform_data = (void *)&ep93xx_led_data,
++  }
++};
++
++
+ extern void ep93xx_gpio_init(void);
+ 
+ void __init ep93xx_init_devices(void)
+@@ -500,6 +530,7 @@ void __init ep93xx_init_devices(void)
+ 	amba_device_register(&uart2_device, &iomem_resource);
+ 	amba_device_register(&uart3_device, &iomem_resource);
+ 
++	platform_device_register(&ep93xx_gpio_leds);
+ 	platform_device_register(&ep93xx_rtc_device);
+ 	platform_device_register(&ep93xx_ohci_device);
+ }
+-- 
+1.6.0.4
+
diff --git a/recipes/linux/linux-2.6.27/ts72xx/0011-EP93xx-Ethernet-support.patch b/recipes/linux/linux-2.6.27/ts72xx/0011-EP93xx-Ethernet-support.patch
new file mode 100644
index 0000000000..dc520def5c
--- /dev/null
+++ b/recipes/linux/linux-2.6.27/ts72xx/0011-EP93xx-Ethernet-support.patch
@@ -0,0 +1,548 @@
+From d4b6abf167207531bad915bf8931b0757d8bc01e Mon Sep 17 00:00:00 2001
+From: Matthieu Crapet <mcrapet@gmail.com>
+Date: Sun, 4 Jan 2009 01:03:58 +0100
+Subject: [PATCH] EP93xx Ethernet support
+MIME-Version: 1.0
+Content-Type: text/plain; charset=utf-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Petr Štetiar <ynezz@true.cz>
+---
+ drivers/net/arm/Kconfig      |    1 +
+ drivers/net/arm/ep93xx_eth.c |  354 +++++++++++++++++++++++++++++++++---------
+ 2 files changed, 282 insertions(+), 73 deletions(-)
+
+diff --git a/drivers/net/arm/Kconfig b/drivers/net/arm/Kconfig
+index 8eda6ee..84e6068 100644
+--- a/drivers/net/arm/Kconfig
++++ b/drivers/net/arm/Kconfig
+@@ -44,6 +44,7 @@ config EP93XX_ETH
+ 	tristate "EP93xx Ethernet support"
+ 	depends on ARM && ARCH_EP93XX
+ 	select MII
++	select PHYLIB
+ 	help
+ 	  This is a driver for the ethernet hardware included in EP93xx CPUs.
+ 	  Say Y if you are building a kernel for EP93xx based devices.
+diff --git a/drivers/net/arm/ep93xx_eth.c b/drivers/net/arm/ep93xx_eth.c
+index 1267444..c3f011f 100644
+--- a/drivers/net/arm/ep93xx_eth.c
++++ b/drivers/net/arm/ep93xx_eth.c
+@@ -2,6 +2,7 @@
+  * EP93xx ethernet network device driver
+  * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
+  * Dedicated to Marija Kulikova.
++ * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+@@ -14,6 +15,7 @@
+ #include <linux/kernel.h>
+ #include <linux/netdevice.h>
+ #include <linux/mii.h>
++#include <linux/phy.h>
+ #include <linux/etherdevice.h>
+ #include <linux/ethtool.h>
+ #include <linux/init.h>
+@@ -37,6 +39,8 @@
+ #define  REG_RXCTL_DEFAULT	0x00073800
+ #define REG_TXCTL		0x0004
+ #define  REG_TXCTL_ENABLE	0x00000001
++#define REG_TESTCTL    0x0008
++#define  REG_TESTCTL_MFDX  0x00000040
+ #define REG_MIICMD		0x0010
+ #define  REG_MIICMD_READ	0x00008000
+ #define  REG_MIICMD_WRITE	0x00004000
+@@ -45,6 +49,9 @@
+ #define  REG_MIISTS_BUSY	0x00000001
+ #define REG_SELFCTL		0x0020
+ #define  REG_SELFCTL_RESET	0x00000001
++#define  REG_SELFCTL_MDCDIV_MSK 0x00007e00
++#define  REG_SELFCTL_MDCDIV_OFS 9
++#define  REG_SELFCTL_PSPRS 0x00000100
+ #define REG_INTEN		0x0024
+ #define  REG_INTEN_TX		0x00000008
+ #define  REG_INTEN_RX		0x00000007
+@@ -174,8 +181,14 @@ struct ep93xx_priv
+ 
+ 	struct net_device_stats	stats;
+ 
+-	struct mii_if_info	mii;
+ 	u8			mdc_divisor;
++  int     phy_supports_mfps:1;
++
++  struct mii_bus    mii_bus;
++  struct phy_device *phy_dev;
++  int     speed;