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authorDenys Dmytriyenko <denis@denix.org>2009-03-17 14:32:59 -0400
committerDenys Dmytriyenko <denis@denix.org>2009-03-17 14:32:59 -0400
commit709c4d66e0b107ca606941b988bad717c0b45d9b (patch)
tree37ee08b1eb308f3b2b6426d5793545c38396b838 /recipes/u-boot/u-boot-1.1.4
parentfa6cd5a3b993f16c27de4ff82b42684516d433ba (diff)
rename packages/ to recipes/ per earlier agreement
See links below for more details: http://thread.gmane.org/gmane.comp.handhelds.openembedded/21326 http://thread.gmane.org/gmane.comp.handhelds.openembedded/21816 Signed-off-by: Denys Dmytriyenko <denis@denix.org> Acked-by: Mike Westerhof <mwester@dls.net> Acked-by: Philip Balister <philip@balister.org> Acked-by: Khem Raj <raj.khem@gmail.com> Acked-by: Marcin Juszkiewicz <hrw@openembedded.org> Acked-by: Koen Kooi <koen@openembedded.org> Acked-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
Diffstat (limited to 'recipes/u-boot/u-boot-1.1.4')
-rw-r--r--recipes/u-boot/u-boot-1.1.4/at32stk1000/ap7000-add-spi-device-and-lcdc-base-address.patch112
-rw-r--r--recipes/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-define-for-sdram-test.patch117
-rw-r--r--recipes/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-framebuffer-address.patch11
-rw-r--r--recipes/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-spi-initcalls.patch16
-rw-r--r--recipes/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-system-manager-header-file.patch252
-rw-r--r--recipes/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-add-lcd-and-spi-to-config.patch124
-rw-r--r--recipes/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-ltv350qv-display-support.patch163
-rw-r--r--recipes/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-spi-support.patch98
-rw-r--r--recipes/u-boot/u-boot-1.1.4/at32stk1000/avr32-boards-fix-flash-read.patch120
-rw-r--r--recipes/u-boot/u-boot-1.1.4/at32stk1000/cmd-bmp-add-gzip-compressed-bmp.patch90
-rw-r--r--recipes/u-boot/u-boot-1.1.4/at32stk1000/fix-mmc-data-timeout.patch101
-rw-r--r--recipes/u-boot/u-boot-1.1.4/at32stk1000/lcd-add-24-bpp-support-and-atmel-lcdc-support.patch670
-rw-r--r--recipes/u-boot/u-boot-1.1.4/at32stk1000/lcdc-driver-for-avr32.patch755
-rw-r--r--recipes/u-boot/u-boot-1.1.4/at32stk1000/libavr32-add-spi-and-lcd-board-support.patch61
-rw-r--r--recipes/u-boot/u-boot-1.1.4/at32stk1000/spi-driver-for-avr32.patch1026
-rw-r--r--recipes/u-boot/u-boot-1.1.4/u-boot-autoscript.patch12
-rw-r--r--recipes/u-boot/u-boot-1.1.4/u-boot-base.patch913
-rw-r--r--recipes/u-boot/u-boot-1.1.4/u-boot-crc-warning-not-so-scary.patch11
-rw-r--r--recipes/u-boot/u-boot-1.1.4/u-boot-dht-walnut-df2.patch186
-rw-r--r--recipes/u-boot/u-boot-1.1.4/u-boot-flash-protect-fixup.patch11
-rw-r--r--recipes/u-boot/u-boot-1.1.4/u-boot-fw_printenv.patch139
-rw-r--r--recipes/u-boot/u-boot-1.1.4/u-boot-install.patch102
-rw-r--r--recipes/u-boot/u-boot-1.1.4/u-boot-jerase-cmd.patch107
-rw-r--r--recipes/u-boot/u-boot-1.1.4/u-boot-jffs2-new-nodetypes.patch25
-rw-r--r--recipes/u-boot/u-boot-1.1.4/u-boot-loadb-safe.patch16
-rw-r--r--recipes/u-boot/u-boot-1.1.4/u-boot-make381-fix.patch15
-rw-r--r--recipes/u-boot/u-boot-1.1.4/u-boot-mmc-init.patch24
-rw-r--r--recipes/u-boot/u-boot-1.1.4/u-boot-mmcclk-alternate.patch14
-rw-r--r--recipes/u-boot/u-boot-1.1.4/u-boot-smc91x-multi.patch125
-rw-r--r--recipes/u-boot/u-boot-1.1.4/u-boot-zzz-osx.patch41
30 files changed, 5457 insertions, 0 deletions
diff --git a/recipes/u-boot/u-boot-1.1.4/at32stk1000/ap7000-add-spi-device-and-lcdc-base-address.patch b/recipes/u-boot/u-boot-1.1.4/at32stk1000/ap7000-add-spi-device-and-lcdc-base-address.patch
new file mode 100644
index 0000000000..fa8c8f701f
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/at32stk1000/ap7000-add-spi-device-and-lcdc-base-address.patch
@@ -0,0 +1,112 @@
+diff -uprN u-boot-orig/cpu/at32ap7xxx/ap7000/devices.c u-boot/cpu/at32ap7xxx/ap7000/devices.c
+--- u-boot-orig/cpu/at32ap7xxx/ap7000/devices.c 2007-01-01 19:26:46.000000000 +0100
++++ u-boot/cpu/at32ap7xxx/ap7000/devices.c 2006-12-22 14:51:26.000000000 +0100
+@@ -223,6 +223,46 @@ static const struct resource macb1_resou
+ },
+ };
+ #endif
++#if defined(CFG_SPI0)
++static const struct resource spi0_resource[] = {
++ {
++ .type = RESOURCE_CLOCK,
++ .u = {
++ .clock = { CLOCK_APBA, 0 },
++ },
++ }, {
++ .type = RESOURCE_GPIO,
++ .u = {
++ .gpio = { 6, DEVICE_PIOA, GPIO_FUNC_A, 0 },
++ },
++ }, {
++ .type = RESOURCE_GPIO,
++ .u = {
++ .gpio = { 1, DEVICE_PIOA, GPIO_FUNC_B, 20 },
++ },
++ },
++};
++#endif
++#if defined(CFG_SPI1)
++static const struct resource spi1_resource[] = {
++ {
++ .type = RESOURCE_CLOCK,
++ .u = {
++ .clock = { CLOCK_APBA, 1 },
++ },
++ }, {
++ .type = RESOURCE_GPIO,
++ .u = {
++ .gpio = { 6, DEVICE_PIOB, GPIO_FUNC_B, 0 },
++ },
++ }, {
++ .type = RESOURCE_GPIO,
++ .u = {
++ .gpio = { 1, DEVICE_PIOA, GPIO_FUNC_A, 27 },
++ },
++ },
++};
++#endif
+ #if defined(CFG_LCDC)
+ static const struct resource lcdc_resource[] = {
+ {
+@@ -230,6 +270,16 @@ static const struct resource lcdc_resour
+ .u = {
+ .clock = { CLOCK_AHB, 7 },
+ },
++ }, {
++ .type = RESOURCE_GPIO,
++ .u = {
++ .gpio = { 13, DEVICE_PIOC, GPIO_FUNC_A, 19 },
++ },
++ }, {
++ .type = RESOURCE_GPIO,
++ .u = {
++ .gpio = { 18, DEVICE_PIOD, GPIO_FUNC_A, 0 },
++ },
+ },
+ };
+ #endif
+@@ -390,6 +440,20 @@ const struct device chip_device[] = {
+ .resource = macb0_resource,
+ },
+ #endif
++#if defined(CFG_SPI0)
++ [DEVICE_SPI0] = {
++ .regs = (void *)SPI0_BASE,
++ .nr_resources = ARRAY_SIZE(spi0_resource),
++ .resource = spi0_resource,
++ },
++#endif
++#if defined(CFG_SPI1)
++ [DEVICE_SPI1] = {
++ .regs = (void *)SPI1_BASE,
++ .nr_resources = ARRAY_SIZE(spi1_resource),
++ .resource = spi1_resource,
++ },
++#endif
+ #if defined(CFG_MACB1)
+ [DEVICE_MACB1] = {
+ .regs = (void *)MACB1_BASE,
+@@ -399,6 +463,7 @@ const struct device chip_device[] = {
+ #endif
+ #if defined(CFG_LCDC)
+ [DEVICE_LCDC] = {
++ .regs = (void *)LCDC_BASE,
+ .nr_resources = ARRAY_SIZE(lcdc_resource),
+ .resource = lcdc_resource,
+ },
+diff -uprN u-boot-orig/include/asm-avr32/arch-ap7000/platform.h u-boot/include/asm-avr32/arch-ap7000/platform.h
+--- u-boot-orig/include/asm-avr32/arch-ap7000/platform.h 2007-01-01 19:26:46.000000000 +0100
++++ u-boot/include/asm-avr32/arch-ap7000/platform.h 2006-12-22 14:20:39.000000000 +0100
+@@ -66,6 +66,12 @@ enum device_id {
+ #if defined(CFG_MACB1)
+ DEVICE_MACB1,
+ #endif
++#if defined(CFG_SPI0)
++ DEVICE_SPI0,
++#endif
++#if defined(CFG_SPI1)
++ DEVICE_SPI1,
++#endif
+ #if defined(CFG_LCDC)
+ DEVICE_LCDC,
+ #endif
diff --git a/recipes/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-define-for-sdram-test.patch b/recipes/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-define-for-sdram-test.patch
new file mode 100644
index 0000000000..33c5eb9b7c
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-define-for-sdram-test.patch
@@ -0,0 +1,117 @@
+Index: u-boot-1.1.4/cpu/at32ap7xxx/hsdramc.c
+===================================================================
+--- u-boot-1.1.4.orig/cpu/at32ap7xxx/hsdramc.c 2007-01-11 15:28:40.000000000 +0100
++++ u-boot-1.1.4/cpu/at32ap7xxx/hsdramc.c 2007-01-11 15:29:36.000000000 +0100
+@@ -133,6 +133,7 @@
+ printf("SDRAM: %u MB at address 0x%08lx\n",
+ sdram_size >> 20, info->phys_addr);
+
++#ifdef CONFIG_SDRAM_TEST
+ printf("Testing SDRAM...");
+ for (i = 0; i < sdram_size / 4; i++)
+ sdram[i] = i;
+@@ -148,6 +149,7 @@
+ }
+
+ puts("OK\n");
++#endif
+
+ return sdram_size;
+ }
+Index: u-boot-1.1.4/include/configs/atngw.h
+===================================================================
+--- u-boot-1.1.4.orig/include/configs/atngw.h 2007-01-11 15:28:40.000000000 +0100
++++ u-boot-1.1.4/include/configs/atngw.h 2007-01-30 16:41:23.000000000 +0100
+@@ -31,6 +31,10 @@
+
+ #define CONFIG_NGW_EXT_FLASH 1
+
++/* Handy macros for making strings */
++#define xstringify(x) #x
++#define stringify(x) xstringify(x)
++
+ /*
+ * Timer clock frequency. We're using the CPU-internal COUNT register
+ * for this, so this is equivalent to the CPU core clock frequency
+@@ -80,9 +84,9 @@
+
+ #define CONFIG_BAUDRATE 115200
+ #define CONFIG_BOOTARGS \
+- "console=ttyS0 root=/dev/mmcblk0p1"
++ "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2"
+ #define CONFIG_BOOTCOMMAND \
+- "mmcinit; ext2load mmc 0:1 0x90400000 /uImage; bootm 0x90400000"
++ "fsload 0x90250000 /uImage; bootm 0x90250000"
+
+ #define CONFIG_BOOTDELAY 2
+ #define CONFIG_AUTOBOOT 1
+@@ -105,8 +109,8 @@
+ * generated and assigned to the environment variables "ethaddr" and
+ * "eth1addr".
+ */
+-#define CONFIG_ETHADDR "6a:87:71:14:cd:cb"
+-#define CONFIG_ETH1ADDR "ca:f8:15:e6:3e:e6"
++#define CONFIG_ETHADDR "42:b2:13:36:50:94"
++#define CONFIG_ETH1ADDR "4e:29:49:7e:5c:b9"
+ #define CONFIG_OVERWRITE_ETHADDR_ONCE 1
+ #define CONFIG_NET_MULTI 1
+
+@@ -183,6 +187,7 @@
+
+ #define CFG_SDRAM_BASE 0x10000000
+ #define CFG_SDRAM_16BIT 1
++#define CONFIG_SDRAM_TEST 1
+
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_SIZE 65536
+@@ -202,7 +207,7 @@
+ #define CFG_DMA_ALLOC_END (CFG_MALLOC_START)
+ #define CFG_DMA_ALLOC_START (CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN)
+ /* Allow 2MB for the kernel run-time image */
+-#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000)
++#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00250000)
+ #define CFG_BOOTPARAMS_LEN (16 * 1024)
+
+ /* Other configuration settings that shouldn't have to change all that often */
+Index: u-boot-1.1.4/include/configs/atstk1002.h
+===================================================================
+--- u-boot-1.1.4.orig/include/configs/atstk1002.h 2007-01-11 15:29:36.000000000 +0100
++++ u-boot-1.1.4/include/configs/atstk1002.h 2007-01-30 16:41:25.000000000 +0100
+@@ -98,7 +98,7 @@
+ #define CFG_CONSOLE_UART_DEV DEVICE_USART1
+
+ /* Define to force consol on serial */
+-/* #define CFG_CONSOLE_ALLWAYS_UART 1 */
++#define CFG_CONSOLE_ALLWAYS_UART 1
+ #ifdef CFG_CONSOLE_ALLWAYS_UART
+ #define CFG_CONSOLE_IS_IN_ENV 1
+ #define CFG_CONSOLE_OVERWRITE_ROUTINE 1
+@@ -123,7 +123,7 @@
+ #endif
+
+ #define CONFIG_BOOTCOMMAND \
+- "mmcinit; ext2load mmc 0:1 /uImage; bootm"
++ "mmcinit; ext2load mmc 0:1 0x90250000 /uImage; bootm 0x90250000"
+ #define CONFIG_BOOTDELAY 2
+ #define CONFIG_AUTOBOOT 1
+
+@@ -145,8 +145,8 @@
+ * generated and assigned to the environment variables "ethaddr" and
+ * "eth1addr".
+ */
+-#define CONFIG_ETHADDR "6a:87:71:14:cd:cb"
+-#define CONFIG_ETH1ADDR "ca:f8:15:e6:3e:e6"
++#define CONFIG_ETHADDR "42:b2:13:36:50:94"
++#define CONFIG_ETH1ADDR "4e:29:49:7e:5c:b9"
+ #define CONFIG_OVERWRITE_ETHADDR_ONCE 1
+ #define CONFIG_NET_MULTI 1
+
+@@ -233,6 +233,8 @@
+ #define CFG_INTRAM_SIZE 0x8000
+
+ #define CFG_SDRAM_BASE 0x10000000
++/* Will do SDRAM test if defined */
++#define CONFIG_SDRAM_TEST 1
+
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_SIZE 65536
diff --git a/recipes/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-framebuffer-address.patch b/recipes/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-framebuffer-address.patch
new file mode 100644
index 0000000000..cac9be5d55
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-framebuffer-address.patch
@@ -0,0 +1,11 @@
+diff -uprN u-boot-orig/include/asm-avr32/global_data.h u-boot/include/asm-avr32/global_data.h
+--- u-boot-orig/include/asm-avr32/global_data.h 2007-01-01 19:26:46.000000000 +0100
++++ u-boot/include/asm-avr32/global_data.h 2006-12-19 11:08:14.000000000 +0100
+@@ -44,6 +44,7 @@ typedef struct global_data {
+ unsigned long env_addr; /* Address of env struct */
+ unsigned long env_valid; /* Checksum of env valid? */
+ unsigned long cpu_hz; /* TODO: remove */
++ unsigned long fb_base; /* Address to framebuffer */
+ void **jt;
+ } gd_t;
+
diff --git a/recipes/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-spi-initcalls.patch b/recipes/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-spi-initcalls.patch
new file mode 100644
index 0000000000..397d6b00aa
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-spi-initcalls.patch
@@ -0,0 +1,16 @@
+diff -uprN u-boot-orig/include/asm-avr32/initcalls.h u-boot/include/asm-avr32/initcalls.h
+--- u-boot-orig/include/asm-avr32/initcalls.h 2007-01-01 19:26:46.000000000 +0100
++++ u-boot/include/asm-avr32/initcalls.h 2007-01-05 13:29:16.000000000 +0100
+@@ -30,6 +30,12 @@ extern void board_init_memories(void);
+ extern void board_init_pio(void);
+ extern void board_init_info(void);
+
++#if CONFIG_SPI
++extern void board_init_spi(void);
++#else
++static inline void board_init_spi(void) { }
++#endif
++
+ #if (CONFIG_COMMANDS & CFG_CMD_NET)
+ extern void net_init(void);
+ #else
diff --git a/recipes/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-system-manager-header-file.patch b/recipes/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-system-manager-header-file.patch
new file mode 100644
index 0000000000..221333c4bc
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/at32stk1000/at32ap-add-system-manager-header-file.patch
@@ -0,0 +1,252 @@
+diff -uprN u-boot-orig/include/asm-avr32/arch-ap7000/sm.h u-boot/include/asm-avr32/arch-ap7000/sm.h
+--- u-boot-orig/include/asm-avr32/arch-ap7000/sm.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/include/asm-avr32/arch-ap7000/sm.h 2006-12-21 16:28:04.000000000 +0100
+@@ -0,0 +1,248 @@
++/*
++ * Register definitions for SM
++ *
++ * System Manager
++ */
++#ifndef __ASM_AVR32_SM_H__
++#define __ASM_AVR32_SM_H__
++
++/* SM register offsets */
++#define SM_PM_MCCTRL 0x0000
++#define SM_PM_CKSEL 0x0004
++#define SM_PM_CPU_MASK 0x0008
++#define SM_PM_AHB_MASK 0x000c
++#define SM_PM_APBA_MASK 0x0010
++#define SM_PM_APBB_MASK 0x0014
++#define SM_PM_PLL0 0x0020
++#define SM_PM_PLL1 0x0024
++#define SM_PM_VCTRL 0x0030
++#define SM_PM_VMREF 0x0034
++#define SM_PM_VMV 0x0038
++#define SM_PM_IER 0x0040
++#define SM_PM_IDR 0x0044
++#define SM_PM_IMR 0x0048
++#define SM_PM_ISR 0x004c
++#define SM_PM_ICR 0x0050
++#define SM_PM_GCCTRL 0x0060
++#define SM_PM_GCCTRL0 0x0060
++#define SM_PM_GCCTRL1 0x0064
++#define SM_PM_GCCTRL2 0x0068
++#define SM_PM_GCCTRL3 0x006c
++#define SM_PM_GCCTRL4 0x0070
++#define SM_PM_GCCTRL5 0x0074
++#define SM_PM_GCCTRL6 0x0078
++#define SM_PM_GCCTRL7 0x007c
++#define SM_RTC_CTRL 0x0080
++#define SM_RTC_VAL 0x0084
++#define SM_RTC_TOP 0x0088
++#define SM_RTC_IER 0x0090
++#define SM_RTC_IDR 0x0094
++#define SM_RTC_IMR 0x0098
++#define SM_RTC_ISR 0x009c
++#define SM_RTC_ICR 0x00a0
++#define SM_WDT_CTRL 0x00b0
++#define SM_WDT_CLR 0x00b4
++#define SM_WDT_EXT 0x00b8
++#define SM_RC_RCAUSE 0x00c0
++#define SM_EIM_IER 0x0100
++#define SM_EIM_IDR 0x0104
++#define SM_EIM_IMR 0x0108
++#define SM_EIM_ISR 0x010c
++#define SM_EIM_ICR 0x0110
++#define SM_EIM_MODE 0x0114
++#define SM_EIM_EDGE 0x0118
++#define SM_EIM_LEVEL 0x011c
++#define SM_EIM_TEST 0x0120
++#define SM_EIM_NMIC 0x0124
++
++/* Bitfields in PM_MCCTRL */
++
++/* Bitfields in PM_CKSEL */
++#define SM_CPUSEL_OFFSET 0
++#define SM_CPUSEL_SIZE 3
++#define SM_CPUDIV_OFFSET 7
++#define SM_CPUDIV_SIZE 1
++#define SM_AHBSEL_OFFSET 8
++#define SM_AHBSEL_SIZE 3
++#define SM_AHBDIV_OFFSET 15
++#define SM_AHBDIV_SIZE 1
++#define SM_APBASEL_OFFSET 16
++#define SM_APBASEL_SIZE 3
++#define SM_APBADIV_OFFSET 23
++#define SM_APBADIV_SIZE 1
++#define SM_APBBSEL_OFFSET 24
++#define SM_APBBSEL_SIZE 3
++#define SM_APBBDIV_OFFSET 31
++#define SM_APBBDIV_SIZE 1
++
++/* Bitfields in PM_CPU_MASK */
++
++/* Bitfields in PM_AHB_MASK */
++
++/* Bitfields in PM_APBA_MASK */
++
++/* Bitfields in PM_APBB_MASK */
++
++/* Bitfields in PM_PLL0 */
++#define SM_PLLEN_OFFSET 0
++#define SM_PLLEN_SIZE 1
++#define SM_PLLOSC_OFFSET 1
++#define SM_PLLOSC_SIZE 1
++#define SM_PLLOPT_OFFSET 2
++#define SM_PLLOPT_SIZE 3
++#define SM_PLLDIV_OFFSET 8
++#define SM_PLLDIV_SIZE 8
++#define SM_PLLMUL_OFFSET 16
++#define SM_PLLMUL_SIZE 8
++#define SM_PLLCOUNT_OFFSET 24
++#define SM_PLLCOUNT_SIZE 6
++#define SM_PLLTEST_OFFSET 31
++#define SM_PLLTEST_SIZE 1
++
++/* Bitfields in PM_PLL1 */
++
++/* Bitfields in PM_VCTRL */
++#define SM_VAUTO_OFFSET 0
++#define SM_VAUTO_SIZE 1
++#define SM_PM_VCTRL_VAL_OFFSET 8
++#define SM_PM_VCTRL_VAL_SIZE 7
++
++/* Bitfields in PM_VMREF */
++#define SM_REFSEL_OFFSET 0
++#define SM_REFSEL_SIZE 4
++
++/* Bitfields in PM_VMV */
++#define SM_PM_VMV_VAL_OFFSET 0
++#define SM_PM_VMV_VAL_SIZE 8
++
++/* Bitfields in PM_IER */
++
++/* Bitfields in PM_IDR */
++
++/* Bitfields in PM_IMR */
++
++/* Bitfields in PM_ISR */
++
++/* Bitfields in PM_ICR */
++#define SM_LOCK0_OFFSET 0
++#define SM_LOCK0_SIZE 1
++#define SM_LOCK1_OFFSET 1
++#define SM_LOCK1_SIZE 1
++#define SM_WAKE_OFFSET 2
++#define SM_WAKE_SIZE 1
++#define SM_VOK_OFFSET 3
++#define SM_VOK_SIZE 1
++#define SM_VMRDY_OFFSET 4
++#define SM_VMRDY_SIZE 1
++#define SM_CKRDY_OFFSET 5
++#define SM_CKRDY_SIZE 1
++
++/* Bitfields in PM_GCCTRL */
++#define SM_OSCSEL_OFFSET 0
++#define SM_OSCSEL_SIZE 1
++#define SM_PLLSEL_OFFSET 1
++#define SM_PLLSEL_SIZE 1
++#define SM_CEN_OFFSET 2
++#define SM_CEN_SIZE 1
++#define SM_CPC_OFFSET 3
++#define SM_CPC_SIZE 1
++#define SM_DIVEN_OFFSET 4
++#define SM_DIVEN_SIZE 1
++#define SM_DIV_OFFSET 8
++#define SM_DIV_SIZE 8
++
++/* Bitfields in RTC_CTRL */
++#define SM_PCLR_OFFSET 1
++#define SM_PCLR_SIZE 1
++#define SM_TOPEN_OFFSET 2
++#define SM_TOPEN_SIZE 1
++#define SM_CLKEN_OFFSET 3
++#define SM_CLKEN_SIZE 1
++#define SM_PSEL_OFFSET 8
++#define SM_PSEL_SIZE 16
++
++/* Bitfields in RTC_VAL */
++#define SM_RTC_VAL_VAL_OFFSET 0
++#define SM_RTC_VAL_VAL_SIZE 31
++
++/* Bitfields in RTC_TOP */
++#define SM_RTC_TOP_VAL_OFFSET 0
++#define SM_RTC_TOP_VAL_SIZE 32
++
++/* Bitfields in RTC_IER */
++
++/* Bitfields in RTC_IDR */
++
++/* Bitfields in RTC_IMR */
++
++/* Bitfields in RTC_ISR */
++
++/* Bitfields in RTC_ICR */
++#define SM_TOPI_OFFSET 0
++#define SM_TOPI_SIZE 1
++
++/* Bitfields in WDT_CTRL */
++#define SM_KEY_OFFSET 24
++#define SM_KEY_SIZE 8
++
++/* Bitfields in WDT_CLR */
++
++/* Bitfields in WDT_EXT */
++
++/* Bitfields in RC_RCAUSE */
++#define SM_POR_OFFSET 0
++#define SM_POR_SIZE 1
++#define SM_BOD_OFFSET 1
++#define SM_BOD_SIZE 1
++#define SM_EXT_OFFSET 2
++#define SM_EXT_SIZE 1
++#define SM_WDT_OFFSET 3
++#define SM_WDT_SIZE 1
++#define SM_NTAE_OFFSET 4
++#define SM_NTAE_SIZE 1
++#define SM_SERP_OFFSET 5
++#define SM_SERP_SIZE 1
++
++/* Bitfields in EIM_IER */
++
++/* Bitfields in EIM_IDR */
++
++/* Bitfields in EIM_IMR */
++
++/* Bitfields in EIM_ISR */
++
++/* Bitfields in EIM_ICR */
++
++/* Bitfields in EIM_MODE */
++
++/* Bitfields in EIM_EDGE */
++#define SM_INT0_OFFSET 0
++#define SM_INT0_SIZE 1
++#define SM_INT1_OFFSET 1
++#define SM_INT1_SIZE 1
++#define SM_INT2_OFFSET 2
++#define SM_INT2_SIZE 1
++#define SM_INT3_OFFSET 3
++#define SM_INT3_SIZE 1
++
++/* Bitfields in EIM_LEVEL */
++
++/* Bitfields in EIM_TEST */
++#define SM_TESTEN_OFFSET 31
++#define SM_TESTEN_SIZE 1
++
++/* Bitfields in EIM_NMIC */
++#define SM_EN_OFFSET 0
++#define SM_EN_SIZE 1
++
++/* Bit manipulation macros */
++#define SM_BIT(name) (1 << SM_##name##_OFFSET)
++#define SM_BF(name,value) (((value) & ((1 << SM_##name##_SIZE) - 1)) << SM_##name##_OFFSET)
++#define SM_BFEXT(name,value) (((value) >> SM_##name##_OFFSET) & ((1 << SM_##name##_SIZE) - 1))
++#define SM_BFINS(name,value,old) (((old) & ~(((1 << SM_##name##_SIZE) - 1) << SM_##name##_OFFSET)) | SM_BF(name,value))
++
++/* Register access macros */
++#define sm_readl(port,reg) readl((port)->regs + SM_##reg)
++#define sm_writel(port,reg,value) writel((value), (port)->regs + SM_##reg)
++
++#endif /* __ASM_AVR32_SM_H__ */
diff --git a/recipes/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-add-lcd-and-spi-to-config.patch b/recipes/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-add-lcd-and-spi-to-config.patch
new file mode 100644
index 0000000000..4deb284564
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-add-lcd-and-spi-to-config.patch
@@ -0,0 +1,124 @@
+Index: u-boot-orig/include/configs/atstk1002.h
+===================================================================
+--- u-boot-orig.orig/include/configs/atstk1002.h 2007-01-05 15:58:53.000000000 +0100
++++ u-boot-orig/include/configs/atstk1002.h 2007-01-05 16:04:50.000000000 +0100
+@@ -32,6 +32,10 @@
+
+ #define CONFIG_ATSTK1000_EXT_FLASH 1
+
++/* Handy macros for making strings */
++#define xstringify(x) #x
++#define stringify(x) xstringify(x)
++
+ /*
+ * Timer clock frequency. We're using the CPU-internal COUNT register
+ * for this, so this is equivalent to the CPU core clock frequency
+@@ -68,10 +72,39 @@
+ #define CFG_USART1 1
+ #define CFG_MMCI 1
+ #define CFG_MACB0 1
+-#define CFG_MACB1 1
++/* #define CFG_MACB1 1 */
++
++/* Enable SPI support */
++#define CONFIG_SPI 1
++#define CONFIG_ATMEL_SPI 1
++#define CFG_SPI0 1
++
++/* Enable LCD support */
++#define CFG_DMAC 1
++#define CFG_LCDC 1
++#define CONFIG_LCD 1
++#define CONFIG_ATMEL_LCDC 1
++#define CONFIG_DISPLAY_LTV350QV 1
++
++/* Setup LCD */
++#define LCD_BPP LCD_COLOR24
++/* CFG_SDRAM_BASE + 0x00500000 */
++#define CFG_LCD_BASE 0x10500000
++#define CFG_WHITE_ON_BLACK 1
++#define CONFIG_VIDEO_BMP_GZIP 1
++#define CFG_VIDEO_LOGO_MAX_SIZE 262144 /* > 320 * 240 * 3 */
++/* #define CONFIG_SPLASH_SCREEN 1 */
+
+ #define CFG_CONSOLE_UART_DEV DEVICE_USART1
+
++/* Define to force consol on serial */
++/* #define CFG_CONSOLE_ALLWAYS_UART 1 */
++#ifdef CFG_CONSOLE_ALLWAYS_UART
++#define CFG_CONSOLE_IS_IN_ENV 1
++#define CFG_CONSOLE_OVERWRITE_ROUTINE 1
++#define CFG_CONSOLE_ENV_OVERWRITE 1
++#endif
++
+ /* User serviceable stuff */
+ #define CONFIG_CMDLINE_TAG 1
+ #define CONFIG_SETUP_MEMORY_TAGS 1
+@@ -80,11 +113,17 @@
+ #define CONFIG_STACKSIZE (2048)
+
+ #define CONFIG_BAUDRATE 115200
++
++#ifdef CFG_LCD_BASE
+ #define CONFIG_BOOTARGS \
+- "console=ttyUS0 root=/dev/mmcblk0p1 fbmem=600k"
+-#define CONFIG_BOOTCOMMAND \
+- "mmcinit; ext2load mmc 0:1 0x90400000 /uImage; bootm 0x90400000"
++ "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k@" stringify(CFG_LCD_BASE)
++#else
++#define CONFIG_BOOTARGS \
++ "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k"
++#endif
+
++#define CONFIG_BOOTCOMMAND \
++ "mmcinit; ext2load mmc 0:1 /uImage; bootm"
+ #define CONFIG_BOOTDELAY 2
+ #define CONFIG_AUTOBOOT 1
+
+@@ -144,7 +183,7 @@
+ /* | CFG_CMD_DIAG */ \
+ /* | CFG_CMD_HWFLOW */ \
+ /* | CFG_CMD_SAVES */ \
+- /* | CFG_CMD_SPI */ \
++ | CFG_CMD_SPI \
+ /* | CFG_CMD_PING */ \
+ | CFG_CMD_MMC \
+ /* | CFG_CMD_FAT */ \
+@@ -152,6 +191,7 @@
+ /* | CFG_CMD_ITEST */ \
+ | CFG_CMD_EXT2 \
+ | CFG_CMD_JFFS2 \
++ | CFG_CMD_BMP \
+ )
+
+ #include <cmd_confdefs.h>
+@@ -201,7 +241,7 @@
+ #define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+
+ #ifdef CONFIG_ATSTK1000
+-# define CFG_MALLOC_LEN (256*1024)
++# define CFG_MALLOC_LEN (512*1024)
+ # define CFG_MALLOC_END \
+ ({ \
+ DECLARE_GLOBAL_DATA_PTR; \
+@@ -213,7 +253,7 @@
+ # define CFG_DMA_ALLOC_END (CFG_MALLOC_START)
+ # define CFG_DMA_ALLOC_START (CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN)
+ /* Allow 2MB for the kernel run-time image */
+-# define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000)
++# define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00250000)
+ # define CFG_BOOTPARAMS_LEN (16 * 1024)
+ #else
+ # define CFG_MALLOC_LEN (8*1024)
+Index: u-boot-orig/board/atstk1000/atstk1000.c
+===================================================================
+--- u-boot-orig.orig/board/atstk1000/atstk1000.c 2007-01-05 16:02:33.000000000 +0100
++++ u-boot-orig/board/atstk1000/atstk1000.c 2007-01-05 16:04:00.000000000 +0100
+@@ -52,3 +52,7 @@
+ gd->bd->bi_phy_id[0] = 0x10;
+ gd->bd->bi_phy_id[1] = 0x11;
+ }
++
++#ifdef CFG_CONSOLE_ALLWAYS_UART
++int overwrite_console(void) { return 1; }
++#endif
diff --git a/recipes/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-ltv350qv-display-support.patch b/recipes/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-ltv350qv-display-support.patch
new file mode 100644
index 0000000000..57c0fae127
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-ltv350qv-display-support.patch
@@ -0,0 +1,163 @@
+diff -uprN u-boot-orig/board/atstk1000/ltv350qv.c u-boot/board/atstk1000/ltv350qv.c
+--- u-boot-orig/board/atstk1000/ltv350qv.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/board/atstk1000/ltv350qv.c 2007-01-02 15:17:32.000000000 +0100
+@@ -0,0 +1,147 @@
++/*
++ * Copyright (C) 2005-2006 Atmel Corporation
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#include <common.h>
++
++#ifdef CONFIG_LCD
++#ifndef CONFIG_SPI
++#error No SPI controller for LCD setup, enable CFG_SPI
++#endif
++
++#include <spi.h>
++
++#ifdef CONFIG_ATMEL_SPI
++#include <atmel_spi.h>
++#endif
++
++static int ltv350qv_write_reg(u8 reg, u16 val)
++{
++ int ret;
++ u8 buffer[3];
++
++ buffer[0] = 0x74;
++ buffer[1] = 0x00;
++ buffer[2] = reg & 0x7f;
++
++ ret = spi_write(&buffer[0], 1, &buffer[1], 2);
++ if (ret != 3) {
++ printf("spi_write returned %d\n", ret);
++ return -1;
++ }
++
++ buffer[0] = 0x76;
++ buffer[1] = val >> 8;
++ buffer[2] = val;
++
++ ret = spi_write(&buffer[0], 1, &buffer[1], 2);
++ if (ret != 3) {
++ printf("spi_write returned %d\n", ret);
++ return -1;
++ }
++
++ return 0;
++}
++
++#define write_reg(reg, val) \
++ do { \
++ ret = ltv350qv_write_reg(reg, val); \
++ if (ret) \
++ goto out; \
++ } while (0)
++
++void ltv350qv_power_on(void)
++{
++ int ret;
++
++#ifdef CONFIG_ATMEL_SPI
++ spi_select_chip(1);
++#endif
++
++ debug ("ltv350qv: do power on sequence\n");
++
++ /* write startup procedure */
++ write_reg(9, 0x0000);
++ udelay(15000);
++ write_reg(9, 0x4000);
++ write_reg(10, 0x2000);
++ write_reg(9, 0x4055);
++ udelay(55000);
++ write_reg(1, 0x409d);
++ write_reg(2, 0x0204);
++ write_reg(3, 0x0100);
++ write_reg(4, 0x3000);
++ write_reg(5, 0x4003);
++ write_reg(6, 0x000a);
++ write_reg(7, 0x0021);
++ write_reg(8, 0x0c00);
++ write_reg(10, 0x0103);
++ write_reg(11, 0x0301);
++ write_reg(12, 0x1f0f);
++ write_reg(13, 0x1f0f);
++ write_reg(14, 0x0707);
++ write_reg(15, 0x0307);
++ write_reg(16, 0x0707);
++ write_reg(17, 0x0000);
++ write_reg(18, 0x0004);
++ write_reg(19, 0x0000);
++
++ udelay(20000);
++ write_reg(9, 0x4a55);
++ write_reg(5, 0x5003);
++
++ debug ("ltv350qv: power on sequence done\n");
++out:
++ return;
++}
++
++void ltv350qv_power_off(void)
++{
++ int ret;
++
++#ifdef CONFIG_ATMEL_SPI
++ spi_select_chip(1);
++#endif
++
++ debug ("ltv350qv: do power off sequence\n");
++ /* GON -> 0, POC -> 0 */
++ write_reg(9, 0x4055);
++ /* DSC -> 0 */
++ write_reg(5, 0x4003);
++ /* VCOMG -> 0 */
++ write_reg(10, 0x2103);
++
++ udelay(1000000);
++
++ /* AP[2:0] -> 000 */
++ write_reg(9, 0x4050);
++
++ debug ("ltv350qv: power off sequence done\n");
++out:
++ return;
++}
++
++void ltv350qv_init(void)
++{
++ debug ("ltv350qv: initializing LTV350QV panel\n");
++ ltv350qv_power_on();
++}
++
++#endif
+diff -uprN u-boot-orig/board/atstk1000/Makefile u-boot/board/atstk1000/Makefile
+--- u-boot-orig/board/atstk1000/Makefile 2007-01-01 19:26:46.000000000 +0100
++++ u-boot/board/atstk1000/Makefile 2007-01-01 16:23:12.000000000 +0100
+@@ -30,7 +30,7 @@ endif
+
+ LIB := lib$(BOARD).a
+
+-SRC := $(BOARD).c $(DAUGHTERBOARD).c eth.c flash.c
++SRC := $(BOARD).c $(DAUGHTERBOARD).c eth.c flash.c ltv350qv.c
+ SRC += spi.c
+ OBJS := $(addsuffix .o,$(basename $(SRC)))
+
diff --git a/recipes/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-spi-support.patch b/recipes/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-spi-support.patch
new file mode 100644
index 0000000000..b9cdba16ff
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/at32stk1000/atstk1000-spi-support.patch
@@ -0,0 +1,98 @@
+diff -uprN u-boot-orig/board/atstk1000/spi.c u-boot/board/atstk1000/spi.c
+--- u-boot-orig/board/atstk1000/spi.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/board/atstk1000/spi.c 2007-01-03 08:46:36.000000000 +0100
+@@ -0,0 +1,83 @@
++/*
++ * Copyright (C) 2006 Atmel Corporation
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#include <common.h>
++
++#include <spi.h>
++#include <asm/io.h>
++#include <atmel_spi.h>
++
++extern void ltv350qv_init(void);
++
++static struct spi_options_t cs0 = {
++ .reg = 0,
++ .baudrate = 200000,
++ .bits = 8,
++ .spck_delay = 0,
++ .trans_delay = 0,
++ .stay_act = 1,
++ .spi_mode = 3,
++};
++static struct spi_options_t cs1 = {
++ .reg = 1,
++ .baudrate = 1500000,
++ .bits = 8,
++ .spck_delay = 0,
++ .trans_delay = 0,
++ .stay_act = 1,
++ .spi_mode = 3,
++};
++
++void spi_chipsel_dac(int cs)
++{
++ if (cs) spi_select_chip(0);
++ else spi_unselect_chip(0);
++}
++
++void spi_chipsel_lcd(int cs)
++{
++ if (cs) spi_select_chip(1);
++ else spi_unselect_chip(1);
++}
++
++spi_chipsel_type spi_chipsel[] = {
++ spi_chipsel_dac,
++ spi_chipsel_lcd,
++};
++int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
++
++void board_init_spi(void)
++{
++ int ret;
++
++ spi_init();
++
++ ret = spi_setup_chip_reg(&cs0, 45000000); /* TODO: get APBA speed */
++ if (ret)
++ return;
++ ret = spi_setup_chip_reg(&cs1, 45000000); /* TODO: get APBA speed */
++ if (ret)
++ return;
++
++ spi_enable();
++
++ ltv350qv_init();
++}
+diff -uprN u-boot-orig/board/atstk1000/Makefile u-boot/board/atstk1000/Makefile
+--- u-boot-orig/board/atstk1000/Makefile 2007-01-01 19:26:46.000000000 +0100
++++ u-boot/board/atstk1000/Makefile 2007-01-01 16:23:12.000000000 +0100
+@@ -31,6 +31,7 @@ endif
+ LIB := lib$(BOARD).a
+
+ SRC := $(BOARD).c $(DAUGHTERBOARD).c eth.c flash.c
++SRC += spi.c
+ OBJS := $(addsuffix .o,$(basename $(SRC)))
+
+ .PHONY: all
diff --git a/recipes/u-boot/u-boot-1.1.4/at32stk1000/avr32-boards-fix-flash-read.patch b/recipes/u-boot/u-boot-1.1.4/at32stk1000/avr32-boards-fix-flash-read.patch
new file mode 100644
index 0000000000..a1e9fe89e5
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/at32stk1000/avr32-boards-fix-flash-read.patch
@@ -0,0 +1,120 @@
+Index: u-boot-orig/board/atmel/ngw/flash.c
+===================================================================
+--- u-boot-orig.orig/board/atmel/ngw/flash.c 2007-01-03 11:31:44.000000000 +0100
++++ u-boot-orig/board/atmel/ngw/flash.c 2007-01-03 11:33:13.000000000 +0100
+@@ -161,7 +161,7 @@
+ {
+ unsigned long flags;
+ uint16_t *base, *p, *s, *end;
+- uint16_t word, status;
++ uint16_t word, status,status1;
+ int ret = ERR_OK;
+
+ if (addr < info->start[0]
+@@ -196,20 +196,36 @@
+ sync_write_buffer();
+
+ /* Wait for completion */
+- do {
++ status1 = readw(p);
++ do {
+ /* TODO: Timeout */
+- status = readw(p);
+- } while ((status != word) && !(status & 0x28));
+-
++ status = status1;
++ status1=readw(p);
++ } while ( ((status ^ status1) & 0x40) && // toggle bit has toggled
++ !(status1 & 0x28) // status is "working"
++ );
++
++ // We'll need to check once again for toggle bit because the toggle bit
++ // may stop toggling as I/O5 changes to "1" (ref at49bv642.pdf p9)
++ status1=readw(p);
++ status=readw(p);
++ if ((status ^ status1) & 0x40)
++ {
++ printf("Flash write error at address 0x%p: 0x%02x != 0x%02x\n",
++ p, status,word);
++ ret = ERR_PROG_ERROR;
++ writew(0xf0, base);
++ readw(base);
++ break;
++ }
++ // we can now verify status==word if we want to.
++
++ // is this Product ID Exit command really required??
++ // --If configuration is 00 (the default) the device is allready in read mode,
++ // and the instruction is not required!
+ writew(0xf0, base);
+ readw(base);
+
+- if (status != word) {
+- printf("Flash write error at address 0x%p: 0x%02x\n",
+- p, status);
+- ret = ERR_PROG_ERROR;
+- break;
+- }
+ }
+
+ local_irq_restore(flags);
+Index: u-boot-orig/board/atstk1000/flash.c
+===================================================================
+--- u-boot-orig.orig/board/atstk1000/flash.c 2007-01-03 11:31:44.000000000 +0100
++++ u-boot-orig/board/atstk1000/flash.c 2007-01-03 11:33:13.000000000 +0100
+@@ -160,7 +160,7 @@
+ {
+ unsigned long flags;
+ uint16_t *base, *p, *s, *end;
+- uint16_t word, status;
++ uint16_t word, status,status1;
+ int ret = ERR_OK;
+
+ if (addr < info->start[0]
+@@ -195,20 +195,36 @@
+ sync_write_buffer();
+
+ /* Wait for completion */
+- do {
++ status1 = readw(p);
++ do {
+ /* TODO: Timeout */
+- status = readw(p);
+- } while ((status != word) && !(status & 0x28));
+-
++ status = status1;
++ status1=readw(p);
++ } while ( ((status ^ status1) & 0x40) && // toggle bit has toggled
++ !(status1 & 0x28) // status is "working"
++ );
++
++ // We'll need to check once again for toggle bit because the toggle bit
++ // may stop toggling as I/O5 changes to "1" (ref at49bv642.pdf p9)
++ status1=readw(p);
++ status=readw(p);
++ if ((status ^ status1) & 0x40)
++ {
++ printf("Flash write error at address 0x%p: 0x%02x != 0x%02x\n",
++ p, status,word);
++ ret = ERR_PROG_ERROR;
++ writew(0xf0, base);
++ readw(base);
++ break;
++ }
++ // we can now verify status==word if we want to.
++
++ // is this Product ID Exit command really required??
++ // --If configuration is 00 (the default) the device is allready in read mode,
++ // and the instruction is not required!
+ writew(0xf0, base);
+ readw(base);
+
+- if (status != word) {
+- printf("Flash write error at address 0x%p: 0x%02x\n",
+- p, status);
+- ret = ERR_PROG_ERROR;
+- break;
+- }
+ }
+
+ local_irq_restore(flags);
diff --git a/recipes/u-boot/u-boot-1.1.4/at32stk1000/cmd-bmp-add-gzip-compressed-bmp.patch b/recipes/u-boot/u-boot-1.1.4/at32stk1000/cmd-bmp-add-gzip-compressed-bmp.patch
new file mode 100644
index 0000000000..47da73ef5e
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/at32stk1000/cmd-bmp-add-gzip-compressed-bmp.patch
@@ -0,0 +1,90 @@
+Index: u-boot-orig/common/cmd_bmp.c
+===================================================================
+--- u-boot-orig.orig/common/cmd_bmp.c 2007-01-05 14:50:55.000000000 +0100
++++ u-boot-orig/common/cmd_bmp.c 2007-01-05 15:59:21.000000000 +0100
+@@ -176,13 +176,83 @@
+ */
+ static int bmp_display(ulong addr, int x, int y)
+ {
++ int ret;
++#ifdef CONFIG_VIDEO_BMP_GZIP
++ bmp_image_t *bmp = (bmp_image_t *)addr;
++ unsigned char *dst = NULL;
++ ulong len;
++
++ if (!((bmp->header.signature[0]=='B') &&
++ (bmp->header.signature[1]=='M'))) {
++
++ /*
++ * Decompress bmp image
++ */
++ len = CFG_VIDEO_LOGO_MAX_SIZE;
++ dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE);
++ if (dst == NULL) {
++ printf("Error: malloc in gunzip failed!\n");
++ return(1);
++ }
++ if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)addr, &len) != 0) {
++ free(dst);
++ printf("There is no valid bmp file at the given address\n");
++ return(1);
++ }
++ if (len == CFG_VIDEO_LOGO_MAX_SIZE) {
++ printf("Image could be truncated "
++ "(increase CFG_VIDEO_LOGO_MAX_SIZE)!\n");
++ }
++
++ /*
++ * Set addr to decompressed image
++ */
++ bmp = (bmp_image_t *)dst;
++
++ /*
++ * Check for bmp mark 'BM'
++ */
++ if (!((bmp->header.signature[0] == 'B') &&
++ (bmp->header.signature[1] == 'M'))) {
++ printf("There is no valid bmp file at the given address\n");
++ free(dst);
++ return(1);
++ }
++ }
++
++ if (dst) {
++ addr = (ulong)dst;
++ }
++#endif /* CONFIG_VIDEO_BMP_GZIP */
++
+ #if defined(CONFIG_LCD)
+ extern int lcd_display_bitmap (ulong, int, int);
+
+- return (lcd_display_bitmap (addr, x, y));
++ ret = lcd_display_bitmap (addr, x, y);
++ if (ret) {
++#ifdef CONFIG_VIDEO_BMP_GZIP
++ free(dst);
++#endif
++ return ret;
++ }
++#ifdef CONFIG_VIDEO_BMP_GZIP
++ free(dst);
++#endif
++ return 0;
++
+ #elif defined(CONFIG_VIDEO)
+ extern int video_display_bitmap (ulong, int, int);
+- return (video_display_bitmap (addr, x, y));
++ ret = video_display_bitmap (addr, x, y);
++ if (ret) {
++#ifdef CONFIG_VIDEO_BMP_GZIP
++ free(dst);
++#endif
++ return ret;
++ }
++#ifdef CONFIG_VIDEO_BMP_GZIP
++ free(dst);
++#endif
++ return 0;
+ #else
+ # error bmp_display() requires CONFIG_LCD or CONFIG_VIDEO
+ #endif
diff --git a/recipes/u-boot/u-boot-1.1.4/at32stk1000/fix-mmc-data-timeout.patch b/recipes/u-boot/u-boot-1.1.4/at32stk1000/fix-mmc-data-timeout.patch
new file mode 100644
index 0000000000..d78cbcaaaa
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/at32stk1000/fix-mmc-data-timeout.patch
@@ -0,0 +1,101 @@
+---
+ cpu/at32ap7xxx/mmc.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 58 insertions(+)
+
+Index: u-boot-1.1.4-avr32/cpu/at32ap7xxx/mmc.c
+===================================================================
+--- u-boot-1.1.4-avr32.orig/cpu/at32ap7xxx/mmc.c 2007-01-30 14:53:33.000000000 +0100
++++ u-boot-1.1.4-avr32/cpu/at32ap7xxx/mmc.c 2007-01-30 15:45:37.000000000 +0100
+@@ -67,6 +67,7 @@ struct mmci {
+ unsigned int rca;
+ block_dev_desc_t blkdev;
+ const struct device *dev;
++ int card_is_sd;
+ };
+
+ struct mmci mmci = {
+@@ -391,6 +392,8 @@ static int sd_init_card(struct mmci *mmc
+ mmc->rca = resp[0] >> 16;
+ if (verbose)
+ printf("SD Card detected (RCA %u)\n", mmc->rca);
++ mmc->card_is_sd = 1;
++
+ return 0;
+ }
+
+@@ -425,6 +428,57 @@ static int mmc_init_card(struct mmci *mm
+ return ret;
+ }
+
++static void mci_set_data_timeout(struct mmci *mmc, struct mmc_csd *csd)
++{
++ static const unsigned int dtomul_to_shift[] = {
++ 0, 4, 7, 8, 10, 12, 16, 20,
++ };
++ static const unsigned int taac_exp[] = {
++ 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000,
++ };
++ static const unsigned int taac_mant[] = {
++ 0, 10, 12, 13, 15, 60, 25, 30,
++ 35, 40, 45, 50, 55, 60, 70, 80,
++ };
++ unsigned int timeout_ns, timeout_clks;
++ unsigned int e, m;
++ unsigned int dtocyc, dtomul;
++ u32 dtor;
++
++ e = csd->taac & 0x07;
++ m = (csd->taac >> 3) & 0x0f;
++
++ timeout_ns = (taac_exp[e] * taac_mant[m] + 9) / 10;
++ timeout_clks = csd->nsac * 100;
++
++ timeout_clks += (((timeout_ns + 9) / 10)
++ * ((CFG_MMC_CLK_PP + 99999) / 100000) + 9999) / 10000;
++ if (!mmc->card_is_sd)
++ timeout_clks *= 10;
++ else
++ timeout_clks *= 100;
++
++ dtocyc = timeout_clks;
++ dtomul = 0;
++ while (dtocyc > 15 && dtomul < 8) {
++ dtomul++;
++ dtocyc = timeout_clks >> dtomul_to_shift[dtomul];
++ }
++
++ if (dtomul >= 8) {
++ dtomul = 7;
++ dtocyc = 15;
++ puts("Warning: Using maximum data timeout\n");
++ }
++
++ dtor = (MMCI_MKBF(MCI_DTOR_DTOMUL, dtomul)
++ | MMCI_MKBF(MCI_DTOR_DTOCYC, dtocyc));
++ mmci_writel(&mmci, MCI_DTOR, dtor);
++
++ printf("mmc: Using %u cycles data timeout (DTOR=0x%x)\n",
++ dtocyc << dtomul_to_shift[dtomul], dtor);
++}
++
+ int mmc_init(int verbose)
+ {
+ struct mmc_cid cid;
+@@ -443,6 +497,8 @@ int mmc_init(int verbose)
+ mmci_writel(&mmci, MCI_IDR, ~0UL);
+ mci_set_mode(CFG_MMC_CLK_OD, CFG_MMC_BLKLEN);
+
++ mmci.card_is_sd = 0;
++
+ ret = sd_init_card(&mmci, &cid, verbose);
+ if (ret) {
+ mmci.rca = MMC_DEFAULT_RCA;
+@@ -458,6 +514,8 @@ int mmc_init(int verbose)
+ if (verbose)
+ mmc_dump_csd(&csd);
+
++ mci_set_data_timeout(&mmci, &csd);
++
+ /* Initialize the blockdev structure */
+ sprintf(mmci.blkdev.vendor,
+ "Man %02x%04x Snr %08x",
diff --git a/recipes/u-boot/u-boot-1.1.4/at32stk1000/lcd-add-24-bpp-support-and-atmel-lcdc-support.patch b/recipes/u-boot/u-boot-1.1.4/at32stk1000/lcd-add-24-bpp-support-and-atmel-lcdc-support.patch
new file mode 100644
index 0000000000..126178b286
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/at32stk1000/lcd-add-24-bpp-support-and-atmel-lcdc-support.patch
@@ -0,0 +1,670 @@
+Index: u-boot-1.1.4/common/lcd.c
+===================================================================
+--- u-boot-1.1.4.orig/common/lcd.c 2007-01-11 15:25:03.000000000 +0100
++++ u-boot-1.1.4/common/lcd.c 2007-01-11 15:28:54.000000000 +0100
+@@ -34,6 +34,7 @@
+ #include <command.h>
+ #include <version.h>
+ #include <stdarg.h>
++#include <malloc.h>
+ #include <linux/types.h>
+ #include <devices.h>
+ #if defined(CONFIG_POST)
+@@ -81,6 +82,9 @@
+ extern void lcd_enable (void);
+ static void *lcd_logo (void);
+
++#ifdef CONFIG_VIDEO_BMP_GZIP
++extern int gunzip(void *, int, unsigned char *, unsigned long *);
++#endif
+
+ #if LCD_BPP == LCD_COLOR8
+ extern void lcd_setcolreg (ushort regno,
+@@ -112,9 +116,12 @@
+ #if 1
+ /* Copy up rows ignoring the first one */
+ memcpy (CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, CONSOLE_SCROLL_SIZE);
+-
+ /* Clear the last one */
+ memset (CONSOLE_ROW_LAST, COLOR_MASK(lcd_color_bg), CONSOLE_ROW_SIZE);
++#ifdef CONFIG_AVR32
++ /* flush cache */
++ dcache_clean_range(CONSOLE_ROW_FIRST, CONSOLE_SIZE);
++#endif
+ #else
+ /*
+ * Poor attempt to optimize speed by moving "long"s.
+@@ -228,10 +235,23 @@
+ static void lcd_drawchars (ushort x, ushort y, uchar *str, int count)
+ {
+ uchar *dest;
+- ushort off, row;
++ ushort off, row, bpp, bytespp;
++#ifdef CONFIG_AVR32
++ uchar *dest_start;
++#endif
+
+- dest = (uchar *)(lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) / 8);
+- off = x * (1 << LCD_BPP) % 8;
++#if (LCD_BPP > LCD_COLOR32)
++ bpp = LCD_BPP;
++#else
++ bpp = 1<<LCD_BPP;
++#endif
++ bytespp = (bpp + 7) / 8;
++
++ dest = (uchar *)(lcd_base + y * lcd_line_length + x * bytespp);
++ off = x * bytespp * 8 % 8;
++#ifdef CONFIG_AVR32
++ dest_start = dest;
++#endif
+
+ for (row=0; row < VIDEO_FONT_HEIGHT; ++row, dest += lcd_line_length) {
+ uchar *s = str;
+@@ -261,7 +281,17 @@
+ bits <<= 1;
+ }
+ #elif LCD_BPP == LCD_COLOR16
+- for (c=0; c<16; ++c) {
++ for (c=0; c<8; ++c) {
++ *d++ = (bits & 0x80) ?
++ lcd_color_fg : lcd_color_bg;
++ bits <<= 1;
++ }
++#elif LCD_BPP == LCD_COLOR24
++ for (c=0; c<8; ++c) {
++ *d++ = (bits & 0x80) ?
++ lcd_color_fg : lcd_color_bg;
++ *d++ = (bits & 0x80) ?
++ lcd_color_fg : lcd_color_bg;
+ *d++ = (bits & 0x80) ?
+ lcd_color_fg : lcd_color_bg;
+ bits <<= 1;
+@@ -271,6 +301,10 @@
+ #if LCD_BPP == LCD_MONOCHROME
+ *d = rest | (*d & ((1 << (8-off)) - 1));
+ #endif
++#ifdef CONFIG_AVR32
++ /* flush cache */
++ dcache_clean_range(dest_start, (int)(d - dest_start));
++#endif
+ }
+ }
+
+@@ -346,7 +380,11 @@
+
+ lcd_base = (void *)(gd->fb_base);
+
+- lcd_line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
++ if (panel_info.vl_bpix > LCD_COLOR32)
++ lcd_line_length = (panel_info.vl_col * panel_info.vl_bpix) / 8;
++ else
++ lcd_line_length = (panel_info.vl_col
++ * NBITS (panel_info.vl_bpix)) / 8;
+
+ lcd_init (lcd_base); /* LCD initialization */
+
+@@ -407,6 +445,11 @@
+ console_col = 0;
+ console_row = 0;
+
++#ifdef CONFIG_AVR32
++ /* flush cache */
++ dcache_clean_range(CONSOLE_ROW_FIRST, CONSOLE_SIZE);
++#endif
++
+ return (0);
+ }
+
+@@ -453,10 +496,17 @@
+ ulong lcd_setmem (ulong addr)
+ {
+ ulong size;
+- int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
++ int bpp;
++ int line_length;
++ if (panel_info.vl_bpix > LCD_COLOR32)
++ bpp = panel_info.vl_bpix;
++ else
++ bpp = NBITS (panel_info.vl_bpix);
++
++ line_length = (panel_info.vl_col * bpp) / 8;
+
+ debug ("LCD panel info: %d x %d, %d bit/pix\n",
+- panel_info.vl_col, panel_info.vl_row, NBITS (panel_info.vl_bpix) );
++ panel_info.vl_col, panel_info.vl_row, bpp);
+
+ size = line_length * panel_info.vl_row;
+
+@@ -475,14 +525,22 @@
+
+ static void lcd_setfgcolor (int color)
+ {
++#if LCD_BPP <= LCD_COLOR8
+ lcd_color_fg = color & 0x0F;
++#else
++ lcd_color_fg = color;
++#endif
+ }
+
+ /*----------------------------------------------------------------------*/
+
+ static void lcd_setbgcolor (int color)
+ {
++#if LCD_BPP <= LCD_COLOR8
+ lcd_color_bg = color & 0x0F;
++#else
++ lcd_color_bg = color;
++#endif
+ }
+
+ /*----------------------------------------------------------------------*/
+@@ -509,7 +567,11 @@
+ #ifdef CONFIG_LCD_LOGO
+ void bitmap_plot (int x, int y)
+ {
++#if !defined(CONFIG_ATMEL_LCDC)
+ ushort *cmap;
++#else
++ ulong *cmap;
++#endif
+ ushort i, j;
+ uchar *bmap;
+ uchar *fb;
+@@ -519,6 +581,8 @@
+ #elif defined(CONFIG_MPC823)
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile cpm8xx_t *cp = &(immr->im_cpm);
++#elif defined(CONFIG_ATMEL_LCDC)
++ struct lcdc_info *cinfo = panel_info.lcdc;
+ #endif
+
+ debug ("Logo: width %d height %d colors %d cmap %d\n",
+@@ -534,6 +598,8 @@
+ cmap = (ushort *)fbi->palette;
+ #elif defined(CONFIG_MPC823)
+ cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]);
++#elif defined(CONFIG_ATMEL_LCDC)
++ cmap = (ulong *)(cinfo->palette) + BMP_LOGO_OFFSET;
+ #endif
+
+ WATCHDOG_RESET();
+@@ -541,10 +607,19 @@
+ /* Set color map */
+ for (i=0; i<(sizeof(bmp_logo_palette)/(sizeof(ushort))); ++i) {
+ ushort colreg = bmp_logo_palette[i];
++#if defined(CONFIG_ATMEL_LCDC)
++ /* convert to match palette registers */
++ uchar red = (colreg >> 8) & 0x0f;
++ uchar green = (colreg >> 4) & 0x0f;
++ uchar blue = (colreg >> 0) & 0x0f;
++ colreg = (blue << 11);
++ colreg |= (green << 6);
++ colreg |= (red << 1);
++#endif
+ #ifdef CFG_INVERT_COLORS
+- *cmap++ = 0xffff - colreg;
++ *(cmap++) = 0xffff - colreg;
+ #else
+- *cmap++ = colreg;
++ *(cmap++) = colreg;
+ #endif
+ }
+
+@@ -579,14 +654,16 @@
+ */
+ int lcd_display_bitmap(ulong bmp_image, int x, int y)
+ {
++#if !defined(CONFIG_ATMEL_LCDC)
+ ushort *cmap;
++#endif
+ ushort i, j;
+ uchar *fb;
+ bmp_image_t *bmp=(bmp_image_t *)bmp_image;
+ uchar *bmap;
+ ushort padded_line;
+ unsigned long width, height;
+- unsigned colors,bpix;
++ unsigned colors,bpix,bpp,bytespp;
+ unsigned long compression;
+ #if defined(CONFIG_PXA250)
+ struct pxafb_info *fbi = &panel_info.pxa;
+@@ -597,82 +674,126 @@
+
+ if (!((bmp->header.signature[0]=='B') &&
+ (bmp->header.signature[1]=='M'))) {
+- printf ("Error: no valid bmp image at %lx\n", bmp_image);
++ printf ("[LCD] No valid BMP image at 0x%08lx\n", bmp_image);
+ return 1;
+-}
++ }
+
+ width = le32_to_cpu (bmp->header.width);
+ height = le32_to_cpu (bmp->header.height);
++ bpp = le16_to_cpu (bmp->header.bit_count);
+ colors = 1<<le16_to_cpu (bmp->header.bit_count);
+ compression = le32_to_cpu (bmp->header.compression);
++ bytespp = (panel_info.vl_bpix + 7) / 8;
+
+- bpix = NBITS(panel_info.vl_bpix);
++ if (panel_info.vl_bpix > LCD_COLOR32)
++ bpix = panel_info.vl_bpix;
++ else
++ bpix = NBITS(panel_info.vl_bpix);
+
+- if ((bpix != 1) && (bpix != 8)) {
++ if ((bpix != 1) && (bpix != 8) && (bpix != 24)) {
+ printf ("Error: %d bit/pixel mode not supported by U-Boot\n",
+ bpix);
+ return 1;
+ }
+
+- if (bpix != le16_to_cpu(bmp->header.bit_count)) {
++ if (bpix != bpp) {
+ printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
+- bpix,
+- le16_to_cpu(bmp->header.bit_count));
++ bpix, bpp);
+ return 1;
+ }
+
+- debug ("Display-bmp: %d x %d with %d colors\n",
+- (int)width, (int)height, (int)colors);
++ debug ("Display-bmp: %d x %d with %d colors (%d bpp)\n",
++ (int)width, (int)height, (int)colors, (int)bpp);
+
+- if (bpix==8) {
++ if (bpix == 8) {
+ #if defined(CONFIG_PXA250)
+ cmap = (ushort *)fbi->palette;
+ #elif defined(CONFIG_MPC823)
+ cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
++#elif defined(CONFIG_ATMEL_LCDC)
++ /* no need to have a palette link, we use lcd_setcolreg */
+ #else
+ # error "Don't know location of color map"
+ #endif
+
+ /* Set color map */
+ for (i=0; i<colors; ++i) {
++#if LCP_BPP <= LCD_COLOR8 /* palette only for 8 bpp and less */
+ bmp_color_table_entry_t cte = bmp->color_table[i];
++#endif
++#if !defined(CONFIG_ATMEL_LCDC)
+ ushort colreg =
+ ( ((cte.red) << 8) & 0xf800) |
+ ( ((cte.green) << 3) & 0x07e0) |
+ ( ((cte.blue) >> 3) & 0x001f) ;
+ #ifdef CFG_INVERT_COLORS
+- *cmap = 0xffff - colreg;
+-#else
+- *cmap = colreg;
++ colreg = 0xffff - colreg;
+ #endif
+ #if defined(CONFIG_PXA250)
+- cmap++;
++ cmap[i] = colreg;
+ #elif defined(CONFIG_MPC823)
+- cmap--;
++ cmap[colors-i] = colreg;
++#endif
++#else /* CONFIG_ATMEL_LCDC */
++#if LCD_BPP <= LCD_COLOR8
++ lcd_setcolreg(i, cte.red, cte.green, cte.blue);
++#endif
+ #endif
+ }
+ }
+
+- padded_line = (width&0x3) ? ((width&~0x3)+4) : (width);
+- if ((x + width)>panel_info.vl_col)
++ padded_line = (((width * bpp + 7) / 8) + 3) & ~0x3;
++ if ((x + width) > panel_info.vl_col)
+ width = panel_info.vl_col - x;
+- if ((y + height)>panel_info.vl_row)
++ if ((y + height) > panel_info.vl_row)
+ height = panel_info.vl_row - y;
+
+ bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset);
+- fb = (uchar *) (lcd_base +
+- (y + height - 1) * lcd_line_length + x);
+- for (i = 0; i < height; ++i) {
+- WATCHDOG_RESET();
+- for (j = 0; j < width ; j++)
++ fb = (uchar *) (lcd_base + (y + height - 1) * lcd_line_length + x);
++
++ switch (bpp) {
++ case 24:
++ for (i = 0; i < height; ++i) {
++ WATCHDOG_RESET();
++ for (j = 0; j < width; j++) {
+ #if defined(CONFIG_PXA250)
+- *(fb++)=*(bmap++);
++#error 24 bpp support not added for PXA250
++#elif defined(CONFIG_ATMEL_LCDC)
++ fb[0] = bmap[0];
++ fb[1] = bmap[1];
++ fb[2] = bmap[2];
++ fb += 3;
++ bmap += 3;
+ #elif defined(CONFIG_MPC823)
+- *(fb++)=255-*(bmap++);
++#error 24 bpp support not added for MPC823
+ #endif
+- bmap += (width - padded_line);
+- fb -= (width + lcd_line_length);
+- }
++ }
++ bmap += (width * bytespp - padded_line);
++ fb -= (width * bytespp + lcd_line_length);
++ }
++ break;
++ case 1: /* pass through */
++ case 8:
++ for (i = 0; i < height; ++i) {
++ WATCHDOG_RESET();
++ for (j = 0; j < width; j++) {
++#if defined(CONFIG_PXA250)
++ *(fb++)=*(bmap++);
++#elif defined(CONFIG_ATMEL_LCDC)
++ *(fb++)=*(bmap++);
++#elif defined(CONFIG_MPC823)
++ *(fb++)=255-*(bmap++);
++#endif
++ }
++ bmap += (width * bytespp - padded_line);
++ fb -= (width * bytespp + lcd_line_length);
++ }
++ break;
++ default:
++ break;
++ };
++
++ /* TODO: flush fb */
+
+ return (0);
+ }
+@@ -694,12 +815,68 @@
+ static int do_splash = 1;
+
+ if (do_splash && (s = getenv("splashimage")) != NULL) {
++#ifdef CONFIG_VIDEO_BMP_GZIP
++ bmp_image_t *bmp;
++ unsigned char *dst = NULL;
++ ulong len;
++#endif
+ addr = simple_strtoul(s, NULL, 16);
+ do_splash = 0;
+
++#ifdef CONFIG_VIDEO_BMP_GZIP
++ bmp = (bmp_image_t *)addr;
++
++ if (!((bmp->header.signature[0]=='B') &&
++ (bmp->header.signature[1]=='M'))) {
++ len = CFG_VIDEO_LOGO_MAX_SIZE;
++ dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE);
++ if (dst == NULL) {
++ printf("[LCD] Malloc for gunzip failed!\n");
++ return ((void *)lcd_base);
++ }
++ if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE,
++ (uchar *)addr, &len) != 0) {
++ free(dst);
++ printf("[LCD] No valid BMP image at 0x%08lx\n",
++ addr);
++ return ((void *)lcd_base);
++ }
++ if (len == CFG_VIDEO_LOGO_MAX_SIZE) {
++ printf("[LCD] Image could be truncated (increase "
++ "CFG_VIDEO_LOGO_MAX_SIZE)!\n");
++ }
++
++ /*
++ * Set addr to decompressed image
++ */
++ bmp = (bmp_image_t *)dst;
++
++ /*
++ * Check for bmp mark 'BM'
++ */
++ if (!((bmp->header.signature[0] == 'B') &&
++ (bmp->header.signature[1] == 'M'))) {
++ printf("[LCD] No valid BMP image at 0x%08lx\n",
++ addr);
++ free(dst);
++ return ((void *)lcd_base);
++ }
++
++ addr = (ulong)dst;
++ }
++#endif
+ if (lcd_display_bitmap (addr, 0, 0) == 0) {
++#ifdef CONFIG_VIDEO_BMP_GZIP
++ if (dst)
++ free(dst);
++#endif
+ return ((void *)lcd_base);
+ }
++
++#ifdef CONFIG_VIDEO_BMP_GZIP
++ if (dst)
++ free(dst);
++#endif
+ }
+ #endif /* CONFIG_SPLASH_SCREEN */
+
+Index: u-boot-1.1.4/include/lcd.h
+===================================================================
+--- u-boot-1.1.4.orig/include/lcd.h 2007-01-11 15:25:03.000000000 +0100
++++ u-boot-1.1.4/include/lcd.h 2007-01-11 15:25:38.000000000 +0100
+@@ -148,7 +148,159 @@
+
+ extern vidinfo_t panel_info;
+
+-#endif /* CONFIG_MPC823 or CONFIG_PXA250 */
++#elif defined CONFIG_ATMEL_LCDC
++struct lcdc_bitfield {
++ u32 offset; /* beginning of bitfield */
++ u32 length; /* length of bitfield */
++ u32 msb_right; /* != 0 : Most significant bit is right */
++};
++
++struct lcdc_var_screeninfo {
++ u32 xres; /* visible resolution */
++ u32 yres;
++ u32 xres_virtual; /* virtual resolution */
++ u32 yres_virtual;
++ u32 xoffset; /* offset from virtual to visible */
++ u32 yoffset; /* resolution */
++
++ u32 bits_per_pixel; /* guess what */
++ u32 grayscale; /* != 0 Graylevels instead of colors */
++
++ struct lcdc_bitfield red; /* bitfield in fb mem if true color, */
++ struct lcdc_bitfield green; /* else only length is significant */
++ struct lcdc_bitfield blue;
++ struct lcdc_bitfield transp; /* transparency */
++
++ u32 nonstd; /* != 0 Non standard pixel format */
++
++ u32 activate; /* see FB_ACTIVATE_* */
++
++ u32 height; /* height of picture in mm */
++ u32 width; /* width of picture in mm */
++
++ u32 accel_flags; /* (OBSOLETE) see fb_info.flags */
++
++ /* Timing: All values in pixclocks, except pixclock (of course) */
++ u32 pixclock; /* pixel clock in ps (pico seconds) */
++ u32 left_margin; /* time from sync to picture */
++ u32 right_margin; /* time from picture to sync */
++ u32 upper_margin; /* time from sync to picture */
++ u32 lower_margin;
++ u32 hsync_len; /* length of horizontal sync */
++ u32 vsync_len; /* length of vertical sync */
++ u32 sync; /* see FB_SYNC_* */
++ u32 vmode; /* see FB_VMODE_* */
++ u32 rotate; /* angle we rotate counter clockwise */
++ u32 reserved[5]; /* Reserved for future compatibility */
++};
++
++/*
++ * Atmel LCDC DMA descriptor
++ */
++struct lcdc_dma_descriptor {
++ u_long fdadr; /* Frame descriptor address register */
++ u_long fsadr; /* Frame source address register */
++ u_long fidr; /* Frame ID register */
++ u_long ldcmd; /* Command register */
++};
++
++/*
++ * Atmel LCDC info
++ */
++struct lcdc_info {
++ u_long reg_lccr3;
++ u_long reg_lccr2;
++ u_long reg_lccr1;
++ u_long reg_lccr0;
++ u_long fdadr0;
++ u_long fdadr1;
++
++ void *regs;
++
++ u_long guard_time;
++ u_long xres;
++ u_long yres;
++ u_long xres_virtual;
++ u_long yres_virtual;
++ u_long bits_per_pixel;
++ u_long smem_start;
++ u_long line_length;
++ u_long visual;
++
++ u_long pixclock;
++ u_long left_margin;
++ u_long right_margin;
++ u_long upper_margin;
++ u_long lower_margin;
++ u_long hsync_len;
++ u_long vsync_len;
++ u_long sync;
++ u_long yoffset;
++ u_long xoffset;
++
++ struct lcdc_var_screeninfo var;
++
++ /* DMA descriptors */
++ struct lcdc_dma_descriptor *dmadesc_fblow;
++ struct lcdc_dma_descriptor *dmadesc_fbhigh;
++ struct lcdc_dma_descriptor *dmadesc_palette;
++
++ u_long screen; /* physical address of frame buffer */
++ u_long palette; /* physical address of palette memory */
++ u_int palette_size;
++
++ /* Device resource */
++ const struct device *dev;
++};
++
++/*
++ * LCD controller stucture for AVR32 CPU
++ */
++typedef struct vidinfo {
++ ushort vl_col; /* Number of columns (i.e. 640) */
++ ushort vl_row; /* Number of rows (i.e. 480) */
++ ushort vl_width; /* Width of display area in millimeters */
++ ushort vl_height; /* Height of display area in millimeters */
++
++ /* LCD configuration register */
++ u_char vl_clkp; /* Clock polarity */
++ u_char vl_oep; /* Output Enable polarity */
++ u_char vl_hsp; /* Horizontal Sync polarity */
++ u_char vl_vsp; /* Vertical Sync polarity */
++ u_char vl_dp; /* Data polarity */
++ u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
++ u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */
++ u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */
++ u_char vl_clor; /* Color, 0 = mono, 1 = color */
++ u_char vl_tft; /* 0 = passive, 1 = TFT */
++
++ /* Horizontal control register. Timing from data sheet */
++ ushort vl_hpw; /* Horz sync pulse width */
++ u_char vl_blw; /* Wait before of line */
++ u_char vl_elw; /* Wait end of line */
++
++ /* Vertical control register. */
++ u_char vl_vpw; /* Vertical sync pulse width */
++ u_char vl_bfw; /* Wait before of frame */
++ u_char vl_efw; /* Wait end of frame */
++
++ /* Atmel LCDC controller params */
++ struct lcdc_info *lcdc;
++ u_long pixclock;
++ u_long left_margin;
++ u_long right_margin;
++ u_long upper_margin;
++ u_long lower_margin;
++ u_long hsync_len;
++ u_long vsync_len;
++ u_long sync;
++ u_long yoffset;
++ u_long xoffset;
++} vidinfo_t;
++
++extern vidinfo_t panel_info;
++
++#endif /* CONFIG_MPC823 or CONFIG_PXA250 or CONFIG_ATMEL_LCDC */
+
+ /* Video functions */
+
+@@ -184,6 +336,16 @@
+ #define LCD_COLOR4 2
+ #define LCD_COLOR8 3
+ #define LCD_COLOR16 4
++#define LCD_COLOR32 5
++#define LCD_COLOR15 15
++#define LCD_COLOR24 24
++
++#define FB_VISUAL_MONO01 0 /* Monochr. 1=Black 0=White */
++#define FB_VISUAL_MONO10 1 /* Monochr. 1=White 0=Black */
++#define FB_VISUAL_TRUECOLOR 2 /* True color */
++#define FB_VISUAL_PSEUDOCOLOR 3 /* Pseudo color (like atari) */
++#define FB_VISUAL_DIRECTCOLOR 4 /* Direct color */
++#define FB_VISUAL_STATIC_PSEUDOCOLOR 5 /* Pseudo color readonly */
+
+ /*----------------------------------------------------------------------*/
+ #if defined(CONFIG_LCD_INFO_BELOW_LOGO)
+@@ -235,7 +397,7 @@
+ # define CONSOLE_COLOR_GREY 14
+ # define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */
+
+-#else
++#elif LCD_BPP == LCD_COLOR16
+
+ /*
+ * 16bpp color definitions
+@@ -243,6 +405,14 @@
+ # define CONSOLE_COLOR_BLACK 0x0000
+ # define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */
+
++#else
++
++/*
++ * 24bpp color definitions
++ */
++# define CONSOLE_COLOR_BLACK 0x000000
++# define CONSOLE_COLOR_WHITE 0xffffff /* Must remain last / highest */
++
+ #endif /* color definitions */
+
+ /************************************************************************/
+@@ -274,6 +444,8 @@
+ (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7)
+ #elif LCD_BPP == LCD_COLOR8
+ # define COLOR_MASK(c) (c)
++#elif LCD_BPP == LCD_COLOR24
++# define COLOR_MASK(c) (c)
+ #else
+ # error Unsupported LCD BPP.
+ #endif
diff --git a/recipes/u-boot/u-boot-1.1.4/at32stk1000/lcdc-driver-for-avr32.patch b/recipes/u-boot/u-boot-1.1.4/at32stk1000/lcdc-driver-for-avr32.patch
new file mode 100644
index 0000000000..e838360992
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/at32stk1000/lcdc-driver-for-avr32.patch
@@ -0,0 +1,755 @@
+diff -uprN u-boot-orig/include/atmel_lcdc.h u-boot/include/atmel_lcdc.h
+--- u-boot-orig/include/atmel_lcdc.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/include/atmel_lcdc.h 2006-12-21 16:26:10.000000000 +0100
+@@ -0,0 +1,269 @@
++/*
++ * Register definitions for Atmel/SIDSA LCD Controller
++ *
++ * Copyright (C) 2004-2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#ifndef __ATMEL_LCDC_H__
++#define __ATMEL_LCDC_H__
++
++#define LCDC_CONTRAST_CTR 0x00000840
++# define LCDC_CONTRAST_CTR_ENA_OFFSET 3
++# define LCDC_CONTRAST_CTR_ENA_SIZE 1
++# define LCDC_CONTRAST_CTR_POL_OFFSET 2
++# define LCDC_CONTRAST_CTR_POL_SIZE 1
++# define LCDC_CONTRAST_CTR_PS_OFFSET 0
++# define LCDC_CONTRAST_CTR_PS_SIZE 2
++#define LCDC_CONTRAST_VAL 0x00000844
++# define LCDC_CONTRAST_VAL_CVAL_OFFSET 0
++# define LCDC_CONTRAST_VAL_CVAL_SIZE 8
++#define LCDC_DMABADDR1 0x00000000
++# define LCDC_DMABADDR1_BADDR_U_OFFSET 0
++# define LCDC_DMABADDR1_BADDR_U_SIZE 32
++#define LCDC_DMABADDR2 0x00000004
++# define LCDC_DMABADDR2_BADDR_L_OFFSET 0
++# define LCDC_DMABADDR2_BADDR_L_SIZE 32
++#define LCDC_DMACON 0x0000001C
++# define LCDC_DMACON_DMABUSY_OFFSET 2
++# define LCDC_DMACON_DMABUSY_SIZE 1
++# define LCDC_DMACON_DMAEN_OFFSET 0
++# define LCDC_DMACON_DMAEN_SIZE 1
++# define LCDC_DMACON_DMARST_OFFSET 1
++# define LCDC_DMACON_DMARST_SIZE 1
++# define LCDC_DMACON_DMAUPDT_OFFSET 3
++# define LCDC_DMACON_DMAUPDT_SIZE 1
++# define LCDC_DMACON_DMA2DEN_OFFSET 4
++# define LCDC_DMACON_DMA2DEN_SIZE 1
++#define LCDC_DMAFRMADD1 0x00000010
++# define LCDC_DMAFRMADD1_FRMADD_U_OFFSET 0
++# define LCDC_DMAFRMADD1_FRMADD_U_SIZE 32
++#define LCDC_DMAFRMADD2 0x00000014
++# define LCDC_DMAFRMADD2_FRMADD_L_OFFSET 0
++# define LCDC_DMAFRMADD2_FRMADD_L_SIZE 32
++#define LCDC_DMAFRMCFG 0x00000018
++# define LCDC_DMAFRMCFG_BRSTLEN_OFFSET 24
++# define LCDC_DMAFRMCFG_BRSTLEN_SIZE 7
++# define LCDC_DMAFRMCFG_FRMSIZE_OFFSET 0
++# define LCDC_DMAFRMCFG_FRMSIZE_SIZE 23
++#define LCDC_DMAFRMPT1 0x00000008
++# define LCDC_DMAFRMPT1_FRMPT_U_OFFSET 0
++# define LCDC_DMAFRMPT1_FRMPT_U_SIZE 23
++#define LCDC_DMAFRMPT2 0x0000000C
++# define LCDC_DMAFRMPT2_FRMPT_L_OFFSET 0
++# define LCDC_DMAFRMPT2_FRMPT_L_SIZE 23
++#define LCDC_DMA2DCFG 0x00000020
++# define LCDC_DMA2DCFG_ADDRINC_OFFSET 0
++# define LCDC_DMA2DCFG_ADDRINC_SIZE 16
++# define LCDC_DMA2DCFG_PIXELOFF_OFFSET 24
++# define LCDC_DMA2DCFG_PIXELOFF_SIZE 5
++#define LCDC_DP1_2 0x0000081C
++# define LCDC_DP1_2_DP1_2_OFFSET 0
++# define LCDC_DP1_2_DP1_2_SIZE 8
++#define LCDC_DP2_3 0x00000828
++# define LCDC_DP2_3_DP2_3_OFFSET 0
++# define LCDC_DP2_3_DP2_3_SIZE 12
++#define LCDC_DP3_4 0x00000830
++# define LCDC_DP3_4_DP3_4_OFFSET 0
++# define LCDC_DP3_4_DP3_4_SIZE 16
++#define LCDC_DP3_5 0x00000824
++# define LCDC_DP3_5_DP3_5_OFFSET 0
++# define LCDC_DP3_5_DP3_5_SIZE 20
++#define LCDC_DP4_5 0x00000834
++# define LCDC_DP4_5_DP4_5_OFFSET 0
++# define LCDC_DP4_5_DP4_5_SIZE 20
++#define LCDC_DP4_7 0x00000820
++# define LCDC_DP4_7_DP4_7_OFFSET 0
++# define LCDC_DP4_7_DP4_7_SIZE 28
++#define LCDC_DP5_7 0x0000082C
++# define LCDC_DP5_7_DP5_7_OFFSET 0
++# define LCDC_DP5_7_DP5_7_SIZE 28
++#define LCDC_DP6_7 0x00000838
++# define LCDC_DP6_7_DP6_7_OFFSET 0
++# define LCDC_DP6_7_DP6_7_SIZE 28
++#define LCDC_LCDCON1 0x00000800
++# define LCDC_LCDCON1_BYPASS_OFFSET 0
++# define LCDC_LCDCON1_BYPASS_SIZE 1
++# define LCDC_LCDCON1_CLKVAL_OFFSET 12
++# define LCDC_LCDCON1_CLKVAL_SIZE 9
++# define LCDC_LCDCON1_LINECNT_OFFSET 21
++# define LCDC_LCDCON1_LINECNT_SIZE 11
++#define LCDC_LCDCON2 0x00000804
++# define LCDC_LCDCON2_CLKMOD_OFFSET 15
++# define LCDC_LCDCON2_CLKMOD_SIZE 1
++# define LCDC_LCDCON2_DISTYPE_OFFSET 0
++# define LCDC_LCDCON2_DISTYPE_SIZE 2
++# define LCDC_LCDCON2_IFWIDTH_OFFSET 3
++# define LCDC_LCDCON2_IFWIDTH_SIZE 2
++# define LCDC_LCDCON2_INVCLK_OFFSET 11
++# define LCDC_LCDCON2_INVCLK_SIZE 1
++# define LCDC_LCDCON2_INVDVAL_OFFSET 12
++# define LCDC_LCDCON2_INVDVAL_SIZE 1
++# define LCDC_LCDCON2_INVFRAME_OFFSET 9
++# define LCDC_LCDCON2_INVFRAME_SIZE 1
++# define LCDC_LCDCON2_INVLINE_OFFSET 10
++# define LCDC_LCDCON2_INVLINE_SIZE 1
++# define LCDC_LCDCON2_INVVD_OFFSET 8
++# define LCDC_LCDCON2_INVVD_SIZE 1
++# define LCDC_LCDCON2_MEMOR_OFFSET 30
++# define LCDC_LCDCON2_MEMOR_SIZE 2
++# define LCDC_LCDCON2_PIXELSIZE_OFFSET 5
++# define LCDC_LCDCON2_PIXELSIZE_SIZE 3
++# define LCDC_LCDCON2_SCANMOD_OFFSET 2
++# define LCDC_LCDCON2_SCANMOD_SIZE 1
++#define LCDC_LCDFIFO 0x00000814
++# define LCDC_LCDFIFO_FIFOTH_OFFSET 0
++# define LCDC_LCDFIFO_FIFOTH_SIZE 16
++#define LCDC_LCDFRMCFG 0x00000810
++# define LCDC_LCDFRMCFG_LINESIZE_OFFSET 21
++# define LCDC_LCDFRMCFG_LINESIZE_SIZE 11
++# define LCDC_LCDFRMCFG_LINEVAL_OFFSET 0
++# define LCDC_LCDFRMCFG_LINEVAL_SIZE 11
++#define LCDC_LCDMVAL 0x00000818
++# define LCDC_LCDMVAL_MMODE_OFFSET 31
++# define LCDC_LCDMVAL_MMODE_SIZE 1
++# define LCDC_LCDMVAL_MVAL_OFFSET 0
++# define LCDC_LCDMVAL_MVAL_SIZE 8
++#define LCDC_LCDTIM1 0x00000808
++# define LCDC_LCDTIM1_VBP_OFFSET 8
++# define LCDC_LCDTIM1_VBP_SIZE 8
++# define LCDC_LCDTIM1_VFP_OFFSET 0
++# define LCDC_LCDTIM1_VFP_SIZE 8
++# define LCDC_LCDTIM1_VHDLY_OFFSET 24
++# define LCDC_LCDTIM1_VHDLY_SIZE 4
++# define LCDC_LCDTIM1_VPW_OFFSET 16
++# define LCDC_LCDTIM1_VPW_SIZE 6
++#define LCDC_LCDTIM2 0x0000080C
++# define LCDC_LCDTIM2_HBP_OFFSET 0
++# define LCDC_LCDTIM2_HBP_SIZE 8
++# define LCDC_LCDTIM2_HFP_OFFSET 21
++# define LCDC_LCDTIM2_HFP_SIZE 11
++# define LCDC_LCDTIM2_HPW_OFFSET 8
++# define LCDC_LCDTIM2_HPW_SIZE 6
++#define LCDC_LCD_GPR 0x0000085C
++# define LCDC_LCD_GPR_GPRB0_OFFSET 0
++# define LCDC_LCD_GPR_GPRB0_SIZE 1
++# define LCDC_LCD_GPR_GPRB1_OFFSET 1
++# define LCDC_LCD_GPR_GPRB1_SIZE 1
++# define LCDC_LCD_GPR_GPRB2_OFFSET 2
++# define LCDC_LCD_GPR_GPRB2_SIZE 1
++# define LCDC_LCD_GPR_GPRB3_OFFSET 3
++# define LCDC_LCD_GPR_GPRB3_SIZE 1
++# define LCDC_LCD_GPR_GPRB4_OFFSET 4
++# define LCDC_LCD_GPR_GPRB4_SIZE 1
++# define LCDC_LCD_GPR_GPRB5_OFFSET 5
++# define LCDC_LCD_GPR_GPRB5_SIZE 1
++# define LCDC_LCD_GPR_GPRB6_OFFSET 6
++# define LCDC_LCD_GPR_GPRB6_SIZE 1
++# define LCDC_LCD_GPR_GPRB7_OFFSET 7
++# define LCDC_LCD_GPR_GPRB7_SIZE 1
++#define LCDC_LCD_ICR 0x00000858
++# define LCDC_LCD_ICR_EOFIC_OFFSET 2
++# define LCDC_LCD_ICR_EOFIC_SIZE 1
++# define LCDC_LCD_ICR_LNIC_OFFSET 0
++# define LCDC_LCD_ICR_LNIC_SIZE 1
++# define LCDC_LCD_ICR_LSTLNIC_OFFSET 1
++# define LCDC_LCD_ICR_LSTLNIC_SIZE 1
++# define LCDC_LCD_ICR_MERIC_OFFSET 6
++# define LCDC_LCD_ICR_MERIC_SIZE 1
++# define LCDC_LCD_ICR_OWRIC_OFFSET 5
++# define LCDC_LCD_ICR_OWRIC_SIZE 1
++# define LCDC_LCD_ICR_UFLWIC_OFFSET 4
++# define LCDC_LCD_ICR_UFLWIC_SIZE 1
++#define LCDC_LCD_IDR 0x0000084C
++# define LCDC_LCD_IDR_EOFID_OFFSET 2
++# define LCDC_LCD_IDR_EOFID_SIZE 1
++# define LCDC_LCD_IDR_LNID_OFFSET 0
++# define LCDC_LCD_IDR_LNID_SIZE 1
++# define LCDC_LCD_IDR_LSTLNID_OFFSET 1
++# define LCDC_LCD_IDR_LSTLNID_SIZE 1
++# define LCDC_LCD_IDR_MERID_OFFSET 6
++# define LCDC_LCD_IDR_MERID_SIZE 1
++# define LCDC_LCD_IDR_OWRID_OFFSET 5
++# define LCDC_LCD_IDR_OWRID_SIZE 1
++# define LCDC_LCD_IDR_UFLWID_OFFSET 4
++# define LCDC_LCD_IDR_UFLWID_SIZE 1
++#define LCDC_LCD_IER 0x00000848
++# define LCDC_LCD_IER_EOFIE_OFFSET 2
++# define LCDC_LCD_IER_EOFIE_SIZE 1
++# define LCDC_LCD_IER_LNIE_OFFSET 0
++# define LCDC_LCD_IER_LNIE_SIZE 1
++# define LCDC_LCD_IER_LSTLNIE_OFFSET 1
++# define LCDC_LCD_IER_LSTLNIE_SIZE 1
++# define LCDC_LCD_IER_MERIE_OFFSET 6
++# define LCDC_LCD_IER_MERIE_SIZE 1
++# define LCDC_LCD_IER_OWRIE_OFFSET 5
++# define LCDC_LCD_IER_OWRIE_SIZE 1
++# define LCDC_LCD_IER_UFLWIE_OFFSET 4
++# define LCDC_LCD_IER_UFLWIE_SIZE 1
++#define LCDC_LCD_IMR 0x00000850
++# define LCDC_LCD_IMR_EOFIM_OFFSET 2
++# define LCDC_LCD_IMR_EOFIM_SIZE 1
++# define LCDC_LCD_IMR_LNIM_OFFSET 0
++# define LCDC_LCD_IMR_LNIM_SIZE 1
++# define LCDC_LCD_IMR_LSTLNIM_OFFSET 1
++# define LCDC_LCD_IMR_LSTLNIM_SIZE 1
++# define LCDC_LCD_IMR_MERIM_OFFSET 6
++# define LCDC_LCD_IMR_MERIM_SIZE 1
++# define LCDC_LCD_IMR_OWRIM_OFFSET 5
++# define LCDC_LCD_IMR_OWRIM_SIZE 1
++# define LCDC_LCD_IMR_UFLWIM_OFFSET 4
++# define LCDC_LCD_IMR_UFLWIM_SIZE 1
++#define LCDC_LCD_IRR 0x00000864
++# define LCDC_LCD_IRR_EOFIR_OFFSET 2
++# define LCDC_LCD_IRR_EOFIR_SIZE 1
++# define LCDC_LCD_IRR_LNIR_OFFSET 0
++# define LCDC_LCD_IRR_LNIR_SIZE 1
++# define LCDC_LCD_IRR_LSTLNIR_OFFSET 1
++# define LCDC_LCD_IRR_LSTLNIR_SIZE 1
++# define LCDC_LCD_IRR_MERIR_OFFSET 6
++# define LCDC_LCD_IRR_MERIR_SIZE 1
++# define LCDC_LCD_IRR_OWRIR_OFFSET 5
++# define LCDC_LCD_IRR_OWRIR_SIZE 1
++# define LCDC_LCD_IRR_UFLWIR_OFFSET 4
++# define LCDC_LCD_IRR_UFLWIR_SIZE 1
++#define LCDC_LCD_ISR 0x00000854
++# define LCDC_LCD_ISR_EOFIS_OFFSET 2
++# define LCDC_LCD_ISR_EOFIS_SIZE 1
++# define LCDC_LCD_ISR_LNIS_OFFSET 0
++# define LCDC_LCD_ISR_LNIS_SIZE 1
++# define LCDC_LCD_ISR_LSTLNIS_OFFSET 1
++# define LCDC_LCD_ISR_LSTLNIS_SIZE 1
++# define LCDC_LCD_ISR_MERIS_OFFSET 6
++# define LCDC_LCD_ISR_MERIS_SIZE 1
++# define LCDC_LCD_ISR_OWRIS_OFFSET 5
++# define LCDC_LCD_ISR_OWRIS_SIZE 1
++# define LCDC_LCD_ISR_UFLWIS_OFFSET 4
++# define LCDC_LCD_ISR_UFLWIS_SIZE 1
++#define LCDC_LCD_ITR 0x00000860
++# define LCDC_LCD_ITR_EOFIT_OFFSET 2
++# define LCDC_LCD_ITR_EOFIT_SIZE 1
++# define LCDC_LCD_ITR_LNIT_OFFSET 0
++# define LCDC_LCD_ITR_LNIT_SIZE 1
++# define LCDC_LCD_ITR_LSTLNIT_OFFSET 1
++# define LCDC_LCD_ITR_LSTLNIT_SIZE 1
++# define LCDC_LCD_ITR_MERIT_OFFSET 6
++# define LCDC_LCD_ITR_MERIT_SIZE 1
++# define LCDC_LCD_ITR_OWRIT_OFFSET 5
++# define LCDC_LCD_ITR_OWRIT_SIZE 1
++# define LCDC_LCD_ITR_UFLWIT_OFFSET 4
++# define LCDC_LCD_ITR_UFLWIT_SIZE 1
++#define LCDC_PWRCON 0x0000083C
++# define LCDC_PWRCON_GUARD_TIME_OFFSET 1
++# define LCDC_PWRCON_GUARD_TIME_SIZE 7
++# define LCDC_PWRCON_LCD_BUSY_OFFSET 31
++# define LCDC_PWRCON_LCD_BUSY_SIZE 1
++# define LCDC_PWRCON_LCD_PWR_OFFSET 0
++# define LCDC_PWRCON_LCD_PWR_SIZE 1
++
++#define LCDC_BIT(name) (1 << LCDC_##name##_OFFSET)
++#define LCDC_MKBF(name,value) (((value) & ((1 << LCDC_##name##_SIZE) - 1)) << LCDC_##name##_OFFSET)
++#define LCDC_GETBF(name,value) (((value) >> LCDC_##name##_OFFSET) & ((1 << LCDC_##name##_SIZE) - 1))
++#define LCDC_INSBF(name,value,old) (((old) & ~(((1 << LCDC_##name##_SIZE) - 1) << LCDC_##name##_OFFSET)) | LCDC_MKBF(name, value))
++
++#define lcdc_readl(port,reg) readl((port)->regs + LCDC_##reg)
++#define lcdc_writel(port,reg,value) writel((value), (port)->regs + LCDC_##reg)
++
++#endif /* __ASM_AVR32_PERIPH_LCDC_H__ */
+diff -uprN u-boot-orig/drivers/atmel_lcdc.c u-boot/drivers/atmel_lcdc.c
+--- u-boot-orig/drivers/atmel_lcdc.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/drivers/atmel_lcdc.c 2007-01-05 12:29:24.000000000 +0100
+@@ -0,0 +1,465 @@
++/*
++ * Framebuffer Driver for Atmel/SIDSA LCD Controller
++ *
++ * Copyright (C) 2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <common.h>
++
++#if defined(CONFIG_ATMEL_LCDC)
++
++#ifndef LCD_BPP
++# define LCD_BPP LCD_COLOR24
++#endif
++
++#include <lcd.h>
++#include <malloc.h>
++#include <video_fb.h>
++
++#include <atmel_lcdc.h>
++
++#include <asm/io.h>
++#include <asm/arch/sm.h>
++#include <asm/arch/platform.h>
++
++/* Sync defines */
++#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */
++#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
++#define FB_SYNC_EXT 4 /* external sync */
++#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
++#define FB_SYNC_BROADCAST 16 /* broadcast video timings */
++/* vtotal = 144d/288n/576i => PAL */
++/* vtotal = 121d/242n/484i => NTSC */
++#define FB_SYNC_ON_GREEN 32 /* sync on green */
++#define FB_SYNC_PCLK_RISING 64 /* pixel data sampled on rising pclk */
++
++/* More or less configurable parameters */
++#define LCDC_FIFO_SIZE 512
++#define LCDC_DMA_BURST_LEN 8
++
++/* TODO: These should be autogenerated from part description file */
++#define LCDC_DISTYPE_STN_MONO 0
++#define LCDC_DISTYPE_STN_COLOR 1
++#define LCDC_DISTYPE_TFT 2
++#define LCDC_LUT 0xc00
++
++#ifdef CONFIG_DISPLAY_LTV350QV
++/* 320x240x24 @ 75 Hz */
++vidinfo_t panel_info = {
++ vl_col: 320, /* Number of columns */
++ vl_row: 240, /* Number of rows */
++ vl_width: 320, /* Width in mm */
++ vl_height: 240, /* Height in mm */
++ vl_clkp: CFG_HIGH, /* Clock polarity */
++ vl_oep: CFG_HIGH, /* Output enable polarity */
++ vl_hsp: CFG_HIGH, /* Horizontal sync polarity */
++ vl_vsp: CFG_HIGH, /* Vertical sync polarity */
++ vl_dp: CFG_HIGH, /* Data polarity */
++ vl_bpix: LCD_BPP, /* Bits per pixel */
++ vl_lbw: 1, /* LCD bus width */
++ vl_splt: 0, /* Split display? 0=single, 1=dual */
++ vl_clor: 1, /* Color? 0 = mono, 1 = color */
++ vl_tft: 1, /* TFT? 0 = passive, 1 = TFT */
++ vl_hpw: 16, /* Horizontal sync pulse width */
++ vl_blw: 17, /* Wait before of line */
++ vl_elw: 33, /* Wait end of line */
++ vl_vpw: 1, /* Vertical sync pulse width */
++ vl_bfw: 10, /* Wait before of frame */
++ vl_efw: 10, /* Wait end of frame */
++
++ pixclock: 145111,
++ left_margin: 17,
++ right_margin: 33,
++ upper_margin: 10,
++ lower_margin: 10,
++ hsync_len: 16,
++ vsync_len: 1,
++ sync: FB_SYNC_PCLK_RISING,
++ yoffset: 0,
++ xoffset: 0,
++};
++#else
++#error A display must be defined for the LCD controller
++#endif
++
++void lcd_ctrl_init (void *lcdbase);
++void lcd_enable (void);
++
++int lcd_line_length;
++int lcd_color_fg;
++int lcd_color_bg;
++
++void *lcd_base; /* Start of framebuffer memory */
++void *lcd_console_address; /* Start of console buffer */
++
++short console_col;
++short console_row;
++
++static int lcdc_init_mem(void *lcdbase);
++void lcdc_init(void *lcdbase);
++
++static inline u_int chan_to_field(u_int chan, const struct lcdc_bitfield *bf)
++{
++ chan &= 0xffff;
++ chan >>= 16 - bf->length;
++ return chan << bf->offset;
++}
++
++/*
++ * ************************************************************************* *
++ * Das U-Boot LCD functions *
++ * ************************************************************************* *
++ */
++void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
++{
++ struct lcdc_info *cinfo = panel_info.lcdc;
++ u_int *palette = (u_int *)cinfo->palette;
++ u_int val;
++
++ if (cinfo->var.grayscale)
++ red = green = blue = (19595 * red + 38470 * green
++ + 7471 * blue) >> 16;
++
++ switch (cinfo->visual) {
++ case FB_VISUAL_TRUECOLOR:
++ if (regno < 16) {
++ /* TODO: I do not get why we need a palette here
++ palette = cinfo->pseudo_palette;
++ */
++
++ val = chan_to_field(red, &cinfo->var.red);
++ val |= chan_to_field(green, &cinfo->var.green);
++ val |= chan_to_field(blue, &cinfo->var.blue);
++
++ palette[regno] = val;
++ }
++ break;
++
++ case FB_VISUAL_PSEUDOCOLOR:
++ if (regno < 256) {
++ val = ((blue << 7) & 0x7c00);
++ val |= ((green << 2) & 0x03e0);
++ val |= ((red >> 3) & 0x001f);
++
++ /*
++ * TODO: intensity bit. Maybe something like
++ * ~(red[10] ^ green[10] ^ blue[10]) & 1
++ */
++ palette[regno] = val;
++ }
++ break;
++ }
++}
++
++void lcd_ctrl_init (void *lcdbase)
++{
++ lcdc_init_mem(lcdbase);
++ lcdc_init(lcdbase);
++}
++
++
++
++void lcd_enable (void)
++{
++ return;
++}
++
++ulong calc_fbsize (void)
++{
++ ulong size;
++ int line_length;
++ if (panel_info.vl_bpix > LCD_COLOR32)
++ line_length = panel_info.vl_col * panel_info.vl_bpix / 8;
++ else
++ line_length = panel_info.vl_col * NBITS(panel_info.vl_bpix) / 8;
++
++ size = line_length * panel_info.vl_row;
++ size += PAGE_SIZE;
++
++ return size;
++}
++
++/* ************************************************************************* *
++ * Architecture specific functions *
++ * ************************************************************************* *
++ */
++static int lcdc_init_mem(void *lcdbase)
++{
++ struct lcdc_info *cinfo;
++ const struct device *dev;
++
++ cinfo = malloc(sizeof(struct lcdc_info));
++ if (!cinfo) {
++ printf("lcdc: could not allocate RAM for lcdc_info\n");
++ return -1;
++ }
++
++ dev = get_device(DEVICE_LCDC);
++ if (!dev)
++ printf("lcdc: could not get LCDC\n");
++
++ cinfo->dev = dev;
++ cinfo->regs = dev->regs;
++
++ cinfo->screen = (u_long)lcdbase;
++ cinfo->palette_size = NBITS(panel_info.vl_bpix) == 8 ? 256 : 16;
++ /* palette is stored in LCD controller IO memory */
++ cinfo->palette = (u_long)cinfo->regs + LCDC_LUT;
++
++ panel_info.lcdc = cinfo;
++
++ return 0;
++}
++
++static void lcdc_update_dma()
++{
++ unsigned long dma_addr;
++ unsigned long pixeloff;
++ unsigned long dma2dcfg;
++ struct lcdc_info *cinfo = panel_info.lcdc;
++
++ dma_addr = (cinfo->smem_start + cinfo->yoffset * cinfo->line_length
++ + cinfo->xoffset * cinfo->bits_per_pixel / 8);
++
++ dma_addr &= ~3UL;
++ pixeloff = LCDC_MKBF(DMA2DCFG_PIXELOFF, cinfo->xoffset * cinfo->bits_per_pixel);
++
++ /* Set framebuffer DMA base address and pixel offset */
++ lcdc_writel(cinfo, DMABADDR1, dma_addr);
++ dma2dcfg = lcdc_readl(cinfo, DMA2DCFG);
++ dma2dcfg = LCDC_INSBF(DMA2DCFG_PIXELOFF, pixeloff, dma2dcfg);
++ lcdc_writel(cinfo, DMA2DCFG, dma2dcfg);
++
++ /* Update configuration */
++ lcdc_writel(cinfo, DMACON, (lcdc_readl(cinfo, DMACON)
++ | LCDC_BIT(DMACON_DMAUPDT)));
++}
++
++static int lcdc_set_var(struct lcdc_info *info)
++{
++ info->var.red.msb_right = info->var.green.msb_right
++ = info->var.blue.msb_right = 0;
++ info->var.transp.offset = info->var.transp.length = 0;
++
++ switch (info->bits_per_pixel) {
++ case 2:
++ case 4:
++ case 8:
++ info->var.red.offset = info->var.green.offset
++ = info->var.blue.offset = 0;
++ info->var.red.length = info->var.green.length
++ = info->var.blue.length = info->var.bits_per_pixel;
++ break;
++ case 15:
++ case 16:
++ /*
++ * Bit 16 is the "intensity" bit, I think. Not sure
++ * what we're going to use that for...
++ */
++ info->var.red.offset = 0;
++ info->var.green.offset = 5;
++ info->var.blue.offset = 10;
++ info->var.red.length = 5;
++ info->var.green.length = 5;
++ info->var.blue.length = 5;
++ break;
++ case 32:
++ info->var.transp.offset = 24;
++ info->var.transp.length = 8;
++ /* fall through */
++ case 24:
++ info->var.red.offset = 16;
++ info->var.green.offset = 8;
++ info->var.blue.offset = 0;
++ info->var.red.length = info->var.green.length
++ = info->var.blue.length = 8;
++ break;
++ default:
++ printf("lcdc: color depth %d not supported\n",
++ info->var.bits_per_pixel);
++ return -1;
++ }
++
++ info->var.xoffset = info->var.yoffset = 0;
++ info->var.red.msb_right = info->var.green.msb_right
++ = info->var.blue.msb_right = info->var.transp.msb_right = 0;
++
++ return 0;
++}
++
++void lcdc_init(void *lcdbase)
++{
++ unsigned int value;
++ const struct device *sm;
++ struct lcdc_info *cinfo = panel_info.lcdc;
++
++ sm = get_device(DEVICE_SM);
++ if (!sm)
++ printf("lcdc: could not get SM\n");
++
++ cinfo->xres = panel_info.vl_col;
++ cinfo->yres = panel_info.vl_row;
++ cinfo->xres_virtual = panel_info.vl_col;
++ cinfo->yres_virtual = panel_info.vl_row;
++ if (panel_info.vl_bpix > LCD_COLOR32) {
++ cinfo->bits_per_pixel = panel_info.vl_bpix;
++ } else {
++ cinfo->bits_per_pixel = (1<<panel_info.vl_bpix);
++ }
++ /* INFO: if you see weird offset errors when displaying data
++ * increase the guard_time */
++ cinfo->guard_time = 2;
++
++ cinfo->pixclock = panel_info.pixclock;
++
++ cinfo->left_margin = panel_info.left_margin;
++ cinfo->right_margin = panel_info.right_margin;
++ cinfo->upper_margin = panel_info.upper_margin;
++ cinfo->lower_margin = panel_info.lower_margin;
++
++ cinfo->hsync_len = panel_info.hsync_len;
++ cinfo->vsync_len = panel_info.vsync_len;
++
++ cinfo->sync = panel_info.sync;
++
++ cinfo->smem_start = (u_long)lcdbase;
++ cinfo->yoffset = panel_info.yoffset;
++ cinfo->xoffset = panel_info.xoffset;
++ cinfo->line_length = cinfo->xres;
++
++ panel_info.lcdc = cinfo;
++
++ if (cinfo->bits_per_pixel <= 8) {
++ cinfo->visual = FB_VISUAL_PSEUDOCOLOR;
++ } else {
++ cinfo->visual = FB_VISUAL_TRUECOLOR;
++ }
++
++ /* setup var information */
++ if (lcdc_set_var(cinfo) != 0) {
++ printf("lcdc: could not set var information\n");
++ return;
++ }
++
++ sm_writel(sm, PM_GCCTRL7, SM_BIT(PLLSEL)|SM_BIT(CEN));
++
++ debug("lcdc: resolution: %ux%u %dbpp (%ux%u virtual)\n",
++ cinfo->xres, cinfo->yres, cinfo->bits_per_pixel,
++ cinfo->xres_virtual, cinfo->yres_virtual);
++
++ /* Turn off the LCD controller and the DMA controller */
++ lcdc_writel(cinfo, PWRCON,
++ LCDC_MKBF(PWRCON_GUARD_TIME, cinfo->guard_time));
++ lcdc_writel(cinfo, DMACON, 0);
++
++ cinfo->line_length = (cinfo->xres_virtual
++ * (cinfo->bits_per_pixel / 8));
++
++ /* Re-initialize the DMA engine... */
++ lcdc_update_dma();
++
++ /* ...set frame size and burst length = 8 words (?) */
++ value = LCDC_MKBF(DMAFRMCFG_FRMSIZE,
++ (cinfo->yres * cinfo->line_length + 3) / 4);
++ value |= LCDC_MKBF(DMAFRMCFG_BRSTLEN, (LCDC_DMA_BURST_LEN - 1));
++ lcdc_writel(cinfo, DMAFRMCFG, value);
++
++ /* ...set 2D configuration (necessary for xres_virtual != xres) */
++ value = LCDC_MKBF(DMA2DCFG_ADDRINC,
++ cinfo->xres_virtual - cinfo->xres);
++ lcdc_writel(cinfo, DMA2DCFG, value);
++
++ /* ...wait for DMA engine to become idle... */
++ while (lcdc_readl(cinfo, DMACON) & LCDC_BIT(DMACON_DMABUSY));
++
++ /* ...and enable it with updated configuration */
++ lcdc_writel(cinfo, DMACON, (LCDC_BIT(DMACON_DMAEN)
++ | LCDC_BIT(DMACON_DMAUPDT)
++ | LCDC_BIT(DMACON_DMA2DEN)));
++
++ /* Now, the LCD core... */
++
++ /* Set pixel clock. */
++ value = 140000000 / 100000 * cinfo->pixclock;
++ value /= 10000000;
++ value = (value + 1) / 2;
++ if (value == 0) {
++ lcdc_writel(cinfo, LCDCON1, LCDC_BIT(LCDCON1_BYPASS));
++ } else {
++ lcdc_writel(cinfo, LCDCON1, LCDC_MKBF(LCDCON1_CLKVAL, value - 1));
++ }
++
++ /* Initialize control register 2 */
++ value = (LCDC_BIT(LCDCON2_CLKMOD)
++ | LCDC_MKBF(LCDCON2_DISTYPE, LCDC_DISTYPE_TFT));
++ if (!(cinfo->sync & FB_SYNC_HOR_HIGH_ACT))
++ value |= LCDC_BIT(LCDCON2_INVLINE);
++ if (!(cinfo->sync & FB_SYNC_VERT_HIGH_ACT))
++ value |= LCDC_BIT(LCDCON2_INVFRAME);
++ if (cinfo->sync & FB_SYNC_PCLK_RISING)
++ value |= LCDC_BIT(LCDCON2_INVCLK);
++
++ switch (cinfo->bits_per_pixel) {
++ case 1: value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 0); break;
++ case 2: value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 1); break;
++ case 4: value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 2); break;
++ case 8: value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 3); break;
++ case 15: /* fall through */
++ case 16: value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 4); break;
++ case 24: value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 5); break;
++ case 32: value |= LCDC_MKBF(LCDCON2_PIXELSIZE, 6); break;
++ default:
++ printf("lcdc: %d bits per pixel not supported\n",
++ cinfo->bits_per_pixel);
++ return;
++ break;
++ }
++ lcdc_writel(cinfo, LCDCON2, value);
++
++ /* Vertical timing */
++ value = LCDC_MKBF(LCDTIM1_VPW, cinfo->vsync_len - 1);
++ value |= LCDC_MKBF(LCDTIM1_VBP, cinfo->upper_margin);
++ value |= LCDC_MKBF(LCDTIM1_VFP, cinfo->lower_margin);
++ lcdc_writel(cinfo, LCDTIM1, value);
++
++ /* Horizontal timing */
++ value = LCDC_MKBF(LCDTIM2_HFP, cinfo->right_margin - 1);
++ value |= LCDC_MKBF(LCDTIM2_HPW, cinfo->hsync_len - 1);
++ value |= LCDC_MKBF(LCDTIM2_HBP, cinfo->left_margin - 1);
++ lcdc_writel(cinfo, LCDTIM2, value);
++
++ /* Display size */
++ value = LCDC_MKBF(LCDFRMCFG_LINESIZE, cinfo->xres - 1);
++ value |= LCDC_MKBF(LCDFRMCFG_LINEVAL, cinfo->yres - 1);
++ lcdc_writel(cinfo, LCDFRMCFG, value);
++
++ /* FIFO Threshold: Use formula from data sheet */
++ value = LCDC_FIFO_SIZE - (2 * LCDC_DMA_BURST_LEN + 3);
++ lcdc_writel(cinfo, LCDFIFO, value);
++
++ /* Toggle LCD_MODE every frame */
++ lcdc_writel(cinfo, LCDMVAL, 0);
++
++ /* Disable all interrupts */
++ lcdc_writel(cinfo, LCD_IDR, ~0UL);
++
++ /* Wait for the LCDC core to become idle and enable it */
++ while (lcdc_readl(cinfo, PWRCON) & LCDC_BIT(PWRCON_LCD_BUSY));
++
++ lcdc_writel(cinfo, PWRCON,
++ LCDC_MKBF(PWRCON_GUARD_TIME, cinfo->guard_time)
++ | LCDC_BIT(PWRCON_LCD_PWR));
++
++ debug("lcdc: controller at 0x%08x, framebuffer at 0x%08x\n",
++ cinfo->regs, cinfo->smem_start);
++
++ /* clear 320 x 240 x 24bpp area in framebuffer */
++ memset((void *)cinfo->smem_start, 0, cinfo->xres * cinfo->yres * 3);
++
++ return;
++}
++#endif
+diff -uprN u-boot-orig/drivers/Makefile u-boot/drivers/Makefile
+--- u-boot-orig/drivers/Makefile 2007-01-01 19:26:46.000000000 +0100
++++ u-boot/drivers/Makefile 2007-01-01 16:10:49.000000000 +0100
+@@ -27,7 +27,8 @@ include $(TOPDIR)/config.mk
+
+ LIB = libdrivers.a
+
+-OBJS = 3c589.o 5701rls.o ali512x.o atmel_usart.o \
++OBJS = 3c589.o 5701rls.o ali512x.o \
++ atmel_usart.o atmel_lcdc.o \
+ bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
+ cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
+ e1000.o eepro100.o \
diff --git a/recipes/u-boot/u-boot-1.1.4/at32stk1000/libavr32-add-spi-and-lcd-board-support.patch b/recipes/u-boot/u-boot-1.1.4/at32stk1000/libavr32-add-spi-and-lcd-board-support.patch
new file mode 100644
index 0000000000..5212766115
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/at32stk1000/libavr32-add-spi-and-lcd-board-support.patch
@@ -0,0 +1,61 @@
+diff -uprN u-boot-orig/lib_avr32/board.c u-boot/lib_avr32/board.c
+--- u-boot-orig/lib_avr32/board.c 2007-01-01 19:26:46.000000000 +0100
++++ u-boot/lib_avr32/board.c 2007-01-05 13:29:34.000000000 +0100
+@@ -28,6 +28,7 @@
+
+ #include <asm/initcalls.h>
+ #include <asm/sections.h>
++#include <asm/page.h>
+
+ #ifndef CONFIG_IDENT_STRING
+ #define CONFIG_IDENT_STRING ""
+@@ -128,6 +129,10 @@ void start_u_boot (void)
+ {
+ DECLARE_GLOBAL_DATA_PTR;
+ gd_t gd_data;
++#if defined(CONFIG_VFD) || defined(CONFIG_LCD)
++ unsigned long size;
++ unsigned long addr;
++#endif
+
+ /* Initialize the global data pointer */
+ memset(&gd_data, 0, sizeof(gd_data));
+@@ -172,9 +177,38 @@ void start_u_boot (void)
+ if (!gd->bd->bi_boot_params)
+ puts("WARNING: Cannot allocate space for boot parameters\n");
+
++#if CONFIG_SPI
++ board_init_spi();
++#endif
++
++#ifdef CONFIG_VFD
++ /*
++ * reserve memory for VFD display (always full pages)
++ */
++ /* bss_end is defined in the board-specific linker script */
++ addr = CFG_LCD_BASE;
++ size = vfd_setmem(addr);
++ gd->fb_base = addr;
++#endif /* CONFIG_VFD */
++
++#ifdef CONFIG_LCD
++ /*
++ * reserve memory for LCD display (always full pages)
++ */
++ /* bss_end is defined in the board-specific linker script */
++ addr = CFG_LCD_BASE;
++ size = lcd_setmem(addr);
++ gd->fb_base = addr;
++#endif /* CONFIG_LCD */
++
+ /* initialize environment */
+ env_relocate();
+
++#ifdef CONFIG_VFD
++ /* must do this after the framebuffer is allocated */
++ drv_vfd_init();
++#endif /* CONFIG_VFD */
++
+ devices_init();
+ jumptable_init();
+ console_init_r();
diff --git a/recipes/u-boot/u-boot-1.1.4/at32stk1000/spi-driver-for-avr32.patch b/recipes/u-boot/u-boot-1.1.4/at32stk1000/spi-driver-for-avr32.patch
new file mode 100644
index 0000000000..82c3fbc3c9
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/at32stk1000/spi-driver-for-avr32.patch
@@ -0,0 +1,1026 @@
+diff -uprN u-boot-orig/include/atmel_spi.h u-boot/include/atmel_spi.h
+--- u-boot-orig/include/atmel_spi.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/include/atmel_spi.h 2007-01-01 18:45:27.000000000 +0100
+@@ -0,0 +1,676 @@
++#ifndef __SPI_H_
++#define __SPI_H_
++
++/*! \brief Timeout for spi read and write blocking functions */
++#define SPI_TIMEOUT 10000
++/*! \brief Enable PDC functions for SPI */
++#define SPI_ENABLE_PDC
++
++#define SPI_10_BPT 0x00000002
++#define SPI_11_BPT 0x00000003
++#define SPI_12_BPT 0x00000004
++#define SPI_13_BPT 0x00000005
++#define SPI_14_BPT 0x00000006
++#define SPI_15_BPT 0x00000007
++#define SPI_16_BPT 0x00000008
++#define SPI_8_BPT 0x00000000
++#define SPI_9_BPT 0x00000001
++#define SPI_BITS 4
++#define SPI_BITS_10_BPT 0x00000002
++#define SPI_BITS_11_BPT 0x00000003
++#define SPI_BITS_12_BPT 0x00000004
++#define SPI_BITS_13_BPT 0x00000005
++#define SPI_BITS_14_BPT 0x00000006
++#define SPI_BITS_15_BPT 0x00000007
++#define SPI_BITS_16_BPT 0x00000008
++#define SPI_BITS_8_BPT 0x00000000
++#define SPI_BITS_9_BPT 0x00000001
++#define SPI_BITS_MASK 0x000000f0
++#define SPI_BITS_OFFSET 4
++#define SPI_BITS_SIZE 4
++#define SPI_CPOL 0
++#define SPI_CPOL_MASK 0x00000001
++#define SPI_CPOL_OFFSET 0
++#define SPI_CPOL_SIZE 1
++#define SPI_CR 0x00000000
++#define SPI_CR_LASTXFER 24
++#define SPI_CR_LASTXFER_MASK 0x01000000
++#define SPI_CR_LASTXFER_OFFSET 24
++#define SPI_CR_LASTXFER_SIZE 1
++#define SPI_CR_SPIDIS 1
++#define SPI_CR_SPIDIS_MASK 0x00000002
++#define SPI_CR_SPIDIS_OFFSET 1
++#define SPI_CR_SPIDIS_SIZE 1
++#define SPI_CR_SPIEN 0
++#define SPI_CR_SPIEN_MASK 0x00000001
++#define SPI_CR_SPIEN_OFFSET 0
++#define SPI_CR_SPIEN_SIZE 1
++#define SPI_CR_SWRST 7
++#define SPI_CR_SWRST_MASK 0x00000080
++#define SPI_CR_SWRST_OFFSET 7
++#define SPI_CR_SWRST_SIZE 1
++#define SPI_CSAAT 3
++#define SPI_CSAAT_MASK 0x00000008
++#define SPI_CSAAT_OFFSET 3
++#define SPI_CSAAT_SIZE 1
++#define SPI_CSR0 0x00000030
++#define SPI_CSR0_BITS 4
++#define SPI_CSR0_BITS_10_BPT 0x00000002
++#define SPI_CSR0_BITS_11_BPT 0x00000003
++#define SPI_CSR0_BITS_12_BPT 0x00000004
++#define SPI_CSR0_BITS_13_BPT 0x00000005
++#define SPI_CSR0_BITS_14_BPT 0x00000006
++#define SPI_CSR0_BITS_15_BPT 0x00000007
++#define SPI_CSR0_BITS_16_BPT 0x00000008
++#define SPI_CSR0_BITS_8_BPT 0x00000000
++#define SPI_CSR0_BITS_9_BPT 0x00000001
++#define SPI_CSR0_BITS_MASK 0x000000f0
++#define SPI_CSR0_BITS_OFFSET 4
++#define SPI_CSR0_BITS_SIZE 4
++#define SPI_CSR0_CPOL 0
++#define SPI_CSR0_CPOL_MASK 0x00000001
++#define SPI_CSR0_CPOL_OFFSET 0
++#define SPI_CSR0_CPOL_SIZE 1
++#define SPI_CSR0_CSAAT 3
++#define SPI_CSR0_CSAAT_MASK 0x00000008
++#define SPI_CSR0_CSAAT_OFFSET 3
++#define SPI_CSR0_CSAAT_SIZE 1
++#define SPI_CSR0_DLYBCT 24
++#define SPI_CSR0_DLYBCT_MASK 0xff000000
++#define SPI_CSR0_DLYBCT_OFFSET 24
++#define SPI_CSR0_DLYBCT_SIZE 8
++#define SPI_CSR0_DLYBS 16
++#define SPI_CSR0_DLYBS_MASK 0x00ff0000
++#define SPI_CSR0_DLYBS_OFFSET 16
++#define SPI_CSR0_DLYBS_SIZE 8
++#define SPI_CSR0_NCPHA 1
++#define SPI_CSR0_NCPHA_MASK 0x00000002
++#define SPI_CSR0_NCPHA_OFFSET 1
++#define SPI_CSR0_NCPHA_SIZE 1
++#define SPI_CSR0_SCBR 8
++#define SPI_CSR0_SCBR_MASK 0x0000ff00
++#define SPI_CSR0_SCBR_OFFSET 8
++#define SPI_CSR0_SCBR_SIZE 8
++#define SPI_CSR1 0x00000034
++#define SPI_CSR1_BITS 4
++#define SPI_CSR1_BITS_10_BPT 0x00000002
++#define SPI_CSR1_BITS_11_BPT 0x00000003
++#define SPI_CSR1_BITS_12_BPT 0x00000004
++#define SPI_CSR1_BITS_13_BPT 0x00000005
++#define SPI_CSR1_BITS_14_BPT 0x00000006
++#define SPI_CSR1_BITS_15_BPT 0x00000007
++#define SPI_CSR1_BITS_16_BPT 0x00000008
++#define SPI_CSR1_BITS_8_BPT 0x00000000
++#define SPI_CSR1_BITS_9_BPT 0x00000001
++#define SPI_CSR1_BITS_MASK 0x000000f0
++#define SPI_CSR1_BITS_OFFSET 4
++#define SPI_CSR1_BITS_SIZE 4
++#define SPI_CSR1_CPOL 0
++#define SPI_CSR1_CPOL_MASK 0x00000001
++#define SPI_CSR1_CPOL_OFFSET 0
++#define SPI_CSR1_CPOL_SIZE 1
++#define SPI_CSR1_CSAAT 3
++#define SPI_CSR1_CSAAT_MASK 0x00000008
++#define SPI_CSR1_CSAAT_OFFSET 3
++#define SPI_CSR1_CSAAT_SIZE 1
++#define SPI_CSR1_DLYBCT 24
++#define SPI_CSR1_DLYBCT_MASK 0xff000000
++#define SPI_CSR1_DLYBCT_OFFSET 24
++#define SPI_CSR1_DLYBCT_SIZE 8
++#define SPI_CSR1_DLYBS 16
++#define SPI_CSR1_DLYBS_MASK 0x00ff0000
++#define SPI_CSR1_DLYBS_OFFSET 16
++#define SPI_CSR1_DLYBS_SIZE 8
++#define SPI_CSR1_NCPHA 1
++#define SPI_CSR1_NCPHA_MASK 0x00000002
++#define SPI_CSR1_NCPHA_OFFSET 1
++#define SPI_CSR1_NCPHA_SIZE 1
++#define SPI_CSR1_SCBR 8
++#define SPI_CSR1_SCBR_MASK 0x0000ff00
++#define SPI_CSR1_SCBR_OFFSET 8
++#define SPI_CSR1_SCBR_SIZE 8
++#define SPI_CSR2 0x00000038
++#define SPI_CSR2_BITS 4
++#define SPI_CSR2_BITS_10_BPT 0x00000002
++#define SPI_CSR2_BITS_11_BPT 0x00000003
++#define SPI_CSR2_BITS_12_BPT 0x00000004
++#define SPI_CSR2_BITS_13_BPT 0x00000005
++#define SPI_CSR2_BITS_14_BPT 0x00000006
++#define SPI_CSR2_BITS_15_BPT 0x00000007
++#define SPI_CSR2_BITS_16_BPT 0x00000008
++#define SPI_CSR2_BITS_8_BPT 0x00000000
++#define SPI_CSR2_BITS_9_BPT 0x00000001
++#define SPI_CSR2_BITS_MASK 0x000000f0
++#define SPI_CSR2_BITS_OFFSET 4
++#define SPI_CSR2_BITS_SIZE 4
++#define SPI_CSR2_CPOL 0
++#define SPI_CSR2_CPOL_MASK 0x00000001
++#define SPI_CSR2_CPOL_OFFSET 0
++#define SPI_CSR2_CPOL_SIZE 1
++#define SPI_CSR2_CSAAT 3
++#define SPI_CSR2_CSAAT_MASK 0x00000008
++#define SPI_CSR2_CSAAT_OFFSET 3
++#define SPI_CSR2_CSAAT_SIZE 1
++#define SPI_CSR2_DLYBCT 24
++#define SPI_CSR2_DLYBCT_MASK 0xff000000
++#define SPI_CSR2_DLYBCT_OFFSET 24
++#define SPI_CSR2_DLYBCT_SIZE 8
++#define SPI_CSR2_DLYBS 16
++#define SPI_CSR2_DLYBS_MASK 0x00ff0000
++#define SPI_CSR2_DLYBS_OFFSET 16
++#define SPI_CSR2_DLYBS_SIZE 8
++#define SPI_CSR2_NCPHA 1
++#define SPI_CSR2_NCPHA_MASK 0x00000002
++#define SPI_CSR2_NCPHA_OFFSET 1
++#define SPI_CSR2_NCPHA_SIZE 1
++#define SPI_CSR2_SCBR 8
++#define SPI_CSR2_SCBR_MASK 0x0000ff00
++#define SPI_CSR2_SCBR_OFFSET 8
++#define SPI_CSR2_SCBR_SIZE 8
++#define SPI_CSR3 0x0000003c
++#define SPI_CSR3_BITS 4
++#define SPI_CSR3_BITS_10_BPT 0x00000002
++#define SPI_CSR3_BITS_11_BPT 0x00000003
++#define SPI_CSR3_BITS_12_BPT 0x00000004
++#define SPI_CSR3_BITS_13_BPT 0x00000005
++#define SPI_CSR3_BITS_14_BPT 0x00000006
++#define SPI_CSR3_BITS_15_BPT 0x00000007
++#define SPI_CSR3_BITS_16_BPT 0x00000008
++#define SPI_CSR3_BITS_8_BPT 0x00000000
++#define SPI_CSR3_BITS_9_BPT 0x00000001
++#define SPI_CSR3_BITS_MASK 0x000000f0
++#define SPI_CSR3_BITS_OFFSET 4
++#define SPI_CSR3_BITS_SIZE 4
++#define SPI_CSR3_CPOL 0
++#define SPI_CSR3_CPOL_MASK 0x00000001
++#define SPI_CSR3_CPOL_OFFSET 0
++#define SPI_CSR3_CPOL_SIZE 1
++#define SPI_CSR3_CSAAT 3
++#define SPI_CSR3_CSAAT_MASK 0x00000008
++#define SPI_CSR3_CSAAT_OFFSET 3
++#define SPI_CSR3_CSAAT_SIZE 1
++#define SPI_CSR3_DLYBCT 24
++#define SPI_CSR3_DLYBCT_MASK 0xff000000
++#define SPI_CSR3_DLYBCT_OFFSET 24
++#define SPI_CSR3_DLYBCT_SIZE 8
++#define SPI_CSR3_DLYBS 16
++#define SPI_CSR3_DLYBS_MASK 0x00ff0000
++#define SPI_CSR3_DLYBS_OFFSET 16
++#define SPI_CSR3_DLYBS_SIZE 8
++#define SPI_CSR3_NCPHA 1
++#define SPI_CSR3_NCPHA_MASK 0x00000002
++#define SPI_CSR3_NCPHA_OFFSET 1
++#define SPI_CSR3_NCPHA_SIZE 1
++#define SPI_CSR3_SCBR 8
++#define SPI_CSR3_SCBR_MASK 0x0000ff00
++#define SPI_CSR3_SCBR_OFFSET 8
++#define SPI_CSR3_SCBR_SIZE 8
++#define SPI_DLYBCS 24
++#define SPI_DLYBCS_MASK 0xff000000
++#define SPI_DLYBCS_OFFSET 24
++#define SPI_DLYBCS_SIZE 8
++#define SPI_DLYBCT 24
++#define SPI_DLYBCT_MASK 0xff000000
++#define SPI_DLYBCT_OFFSET 24
++#define SPI_DLYBCT_SIZE 8
++#define SPI_DLYBS 16
++#define SPI_DLYBS_MASK 0x00ff0000
++#define SPI_DLYBS_OFFSET 16
++#define SPI_DLYBS_SIZE 8
++#define SPI_ENDRX 4
++#define SPI_ENDRX_MASK 0x00000010
++#define SPI_ENDRX_OFFSET 4
++#define SPI_ENDRX_SIZE 1
++#define SPI_ENDTX 5
++#define SPI_ENDTX_MASK 0x00000020
++#define SPI_ENDTX_OFFSET 5
++#define SPI_ENDTX_SIZE 1
++#define SPI_FDIV 3
++#define SPI_FDIV_MASK 0x00000008
++#define SPI_FDIV_OFFSET 3
++#define SPI_FDIV_SIZE 1
++#define SPI_IDR 0x00000018
++#define SPI_IDR_ENDRX 4
++#define SPI_IDR_ENDRX_MASK 0x00000010
++#define SPI_IDR_ENDRX_OFFSET 4
++#define SPI_IDR_ENDRX_SIZE 1
++#define SPI_IDR_ENDTX 5
++#define SPI_IDR_ENDTX_MASK 0x00000020
++#define SPI_IDR_ENDTX_OFFSET 5
++#define SPI_IDR_ENDTX_SIZE 1
++#define SPI_IDR_MODF 2
++#define SPI_IDR_MODF_MASK 0x00000004
++#define SPI_IDR_MODF_OFFSET 2
++#define SPI_IDR_MODF_SIZE 1
++#define SPI_IDR_NSSR 8
++#define SPI_IDR_NSSR_MASK 0x00000100
++#define SPI_IDR_NSSR_OFFSET 8
++#define SPI_IDR_NSSR_SIZE 1
++#define SPI_IDR_OVRES 3
++#define SPI_IDR_OVRES_MASK 0x00000008
++#define SPI_IDR_OVRES_OFFSET 3
++#define SPI_IDR_OVRES_SIZE 1
++#define SPI_IDR_RDRF 0
++#define SPI_IDR_RDRF_MASK 0x00000001
++#define SPI_IDR_RDRF_OFFSET 0
++#define SPI_IDR_RDRF_SIZE 1
++#define SPI_IDR_RXBUFF 6
++#define SPI_IDR_RXBUFF_MASK 0x00000040
++#define SPI_IDR_RXBUFF_OFFSET 6
++#define SPI_IDR_RXBUFF_SIZE 1
++#define SPI_IDR_TDRE 1
++#define SPI_IDR_TDRE_MASK 0x00000002
++#define SPI_IDR_TDRE_OFFSET 1
++#define SPI_IDR_TDRE_SIZE 1
++#define SPI_IDR_TXBUFE 7
++#define SPI_IDR_TXBUFE_MASK 0x00000080
++#define SPI_IDR_TXBUFE_OFFSET 7
++#define SPI_IDR_TXBUFE_SIZE 1
++#define SPI_IDR_TXEMPTY 9
++#define SPI_IDR_TXEMPTY_MASK 0x00000200
++#define SPI_IDR_TXEMPTY_OFFSET 9
++#define SPI_IDR_TXEMPTY_SIZE 1
++#define SPI_IER 0x00000014
++#define SPI_IER_ENDRX 4
++#define SPI_IER_ENDRX_MASK 0x00000010
++#define SPI_IER_ENDRX_OFFSET 4
++#define SPI_IER_ENDRX_SIZE 1
++#define SPI_IER_ENDTX 5
++#define SPI_IER_ENDTX_MASK 0x00000020
++#define SPI_IER_ENDTX_OFFSET 5
++#define SPI_IER_ENDTX_SIZE 1
++#define SPI_IER_MODF 2
++#define SPI_IER_MODF_MASK 0x00000004
++#define SPI_IER_MODF_OFFSET 2
++#define SPI_IER_MODF_SIZE 1
++#define SPI_IER_NSSR 8
++#define SPI_IER_NSSR_MASK 0x00000100
++#define SPI_IER_NSSR_OFFSET 8
++#define SPI_IER_NSSR_SIZE 1
++#define SPI_IER_OVRES 3
++#define SPI_IER_OVRES_MASK 0x00000008
++#define SPI_IER_OVRES_OFFSET 3
++#define SPI_IER_OVRES_SIZE 1
++#define SPI_IER_RDRF 0
++#define SPI_IER_RDRF_MASK 0x00000001
++#define SPI_IER_RDRF_OFFSET 0
++#define SPI_IER_RDRF_SIZE 1
++#define SPI_IER_RXBUFF 6
++#define SPI_IER_RXBUFF_MASK 0x00000040
++#define SPI_IER_RXBUFF_OFFSET 6
++#define SPI_IER_RXBUFF_SIZE 1
++#define SPI_IER_TDRE 1
++#define SPI_IER_TDRE_MASK 0x00000002
++#define SPI_IER_TDRE_OFFSET 1
++#define SPI_IER_TDRE_SIZE 1
++#define SPI_IER_TXBUFE 7
++#define SPI_IER_TXBUFE_MASK 0x00000080
++#define SPI_IER_TXBUFE_OFFSET 7
++#define SPI_IER_TXBUFE_SIZE 1
++#define SPI_IER_TXEMPTY 9
++#define SPI_IER_TXEMPTY_MASK 0x00000200
++#define SPI_IER_TXEMPTY_OFFSET 9
++#define SPI_IER_TXEMPTY_SIZE 1
++#define SPI_IMR 0x0000001c
++#define SPI_IMR_ENDRX 4
++#define SPI_IMR_ENDRX_MASK 0x00000010
++#define SPI_IMR_ENDRX_OFFSET 4
++#define SPI_IMR_ENDRX_SIZE 1
++#define SPI_IMR_ENDTX 5
++#define SPI_IMR_ENDTX_MASK 0x00000020
++#define SPI_IMR_ENDTX_OFFSET 5
++#define SPI_IMR_ENDTX_SIZE 1
++#define SPI_IMR_MODF 2
++#define SPI_IMR_MODF_MASK 0x00000004
++#define SPI_IMR_MODF_OFFSET 2
++#define SPI_IMR_MODF_SIZE 1
++#define SPI_IMR_NSSR 8
++#define SPI_IMR_NSSR_MASK 0x00000100
++#define SPI_IMR_NSSR_OFFSET 8
++#define SPI_IMR_NSSR_SIZE 1
++#define SPI_IMR_OVRES 3
++#define SPI_IMR_OVRES_MASK 0x00000008
++#define SPI_IMR_OVRES_OFFSET 3
++#define SPI_IMR_OVRES_SIZE 1
++#define SPI_IMR_RDRF 0
++#define SPI_IMR_RDRF_MASK 0x00000001
++#define SPI_IMR_RDRF_OFFSET 0
++#define SPI_IMR_RDRF_SIZE 1
++#define SPI_IMR_RXBUFF 6
++#define SPI_IMR_RXBUFF_MASK 0x00000040
++#define SPI_IMR_RXBUFF_OFFSET 6
++#define SPI_IMR_RXBUFF_SIZE 1
++#define SPI_IMR_TDRE 1
++#define SPI_IMR_TDRE_MASK 0x00000002
++#define SPI_IMR_TDRE_OFFSET 1
++#define SPI_IMR_TDRE_SIZE 1
++#define SPI_IMR_TXBUFE 7
++#define SPI_IMR_TXBUFE_MASK 0x00000080
++#define SPI_IMR_TXBUFE_OFFSET 7
++#define SPI_IMR_TXBUFE_SIZE 1
++#define SPI_IMR_TXEMPTY 9
++#define SPI_IMR_TXEMPTY_MASK 0x00000200
++#define SPI_IMR_TXEMPTY_OFFSET 9
++#define SPI_IMR_TXEMPTY_SIZE 1
++#define SPI_LASTXFER 24
++#define SPI_LASTXFER_MASK 0x01000000
++#define SPI_LASTXFER_OFFSET 24
++#define SPI_LASTXFER_SIZE 1
++#define SPI_LLB 7
++#define SPI_LLB_MASK 0x00000080
++#define SPI_LLB_OFFSET 7
++#define SPI_LLB_SIZE 1
++#define SPI_MODF 2
++#define SPI_MODFDIS 4
++#define SPI_MODFDIS_MASK 0x00000010
++#define SPI_MODFDIS_OFFSET 4
++#define SPI_MODFDIS_SIZE 1
++#define SPI_MODF_MASK 0x00000004
++#define SPI_MODF_OFFSET 2
++#define SPI_MODF_SIZE 1
++#define SPI_MR 0x00000004
++#define SPI_MR_DLYBCS 24
++#define SPI_MR_DLYBCS_MASK 0xff000000
++#define SPI_MR_DLYBCS_OFFSET 24
++#define SPI_MR_DLYBCS_SIZE 8
++#define SPI_MR_FDIV 3
++#define SPI_MR_FDIV_MASK 0x00000008
++#define SPI_MR_FDIV_OFFSET 3
++#define SPI_MR_FDIV_SIZE 1
++#define SPI_MR_LLB 7
++#define SPI_MR_LLB_MASK 0x00000080
++#define SPI_MR_LLB_OFFSET 7
++#define SPI_MR_LLB_SIZE 1
++#define SPI_MR_MODFDIS 4
++#define SPI_MR_MODFDIS_MASK 0x00000010
++#define SPI_MR_MODFDIS_OFFSET 4
++#define SPI_MR_MODFDIS_SIZE 1
++#define SPI_MR_MSTR 0
++#define SPI_MR_MSTR_MASK 0x00000001
++#define SPI_MR_MSTR_OFFSET 0
++#define SPI_MR_MSTR_SIZE 1
++#define SPI_MR_PCS 16
++#define SPI_MR_PCSDEC 2
++#define SPI_MR_PCSDEC_MASK 0x00000004
++#define SPI_MR_PCSDEC_OFFSET 2
++#define SPI_MR_PCSDEC_SIZE 1
++#define SPI_MR_PCS_MASK 0x000f0000
++#define SPI_MR_PCS_OFFSET 16
++#define SPI_MR_PCS_SIZE 4
++#define SPI_MR_PS 1
++#define SPI_MR_PS_MASK 0x00000002
++#define SPI_MR_PS_OFFSET 1
++#define SPI_MR_PS_SIZE 1
++#define SPI_MSTR 0
++#define SPI_MSTR_MASK 0x00000001
++#define SPI_MSTR_OFFSET 0
++#define SPI_MSTR_SIZE 1
++#define SPI_NCPHA 1
++#define SPI_NCPHA_MASK 0x00000002
++#define SPI_NCPHA_OFFSET 1
++#define SPI_NCPHA_SIZE 1
++#define SPI_NSSR 8
++#define SPI_NSSR_MASK 0x00000100
++#define SPI_NSSR_OFFSET 8
++#define SPI_NSSR_SIZE 1
++#define SPI_OVRES 3
++#define SPI_OVRES_MASK 0x00000008
++#define SPI_OVRES_OFFSET 3
++#define SPI_OVRES_SIZE 1
++#define SPI_PCS 16
++#define SPI_PCSDEC 2
++#define SPI_PCSDEC_MASK 0x00000004
++#define SPI_PCSDEC_OFFSET 2
++#define SPI_PCSDEC_SIZE 1
++#define SPI_PCS_MASK 0x000f0000
++#define SPI_PCS_OFFSET 16
++#define SPI_PCS_SIZE 4
++#define SPI_PS 1
++#define SPI_PS_MASK 0x00000002
++#define SPI_PS_OFFSET 1
++#define SPI_PS_SIZE 1
++#define SPI_PTCR 0x00000120
++#define SPI_PTCR_RXTDIS 1
++#define SPI_PTCR_RXTDIS_MASK 0x00000002
++#define SPI_PTCR_RXTDIS_OFFSET 1
++#define SPI_PTCR_RXTDIS_SIZE 1
++#define SPI_PTCR_RXTEN 0
++#define SPI_PTCR_RXTEN_MASK 0x00000001
++#define SPI_PTCR_RXTEN_OFFSET 0
++#define SPI_PTCR_RXTEN_SIZE 1
++#define SPI_PTCR_TXTDIS 9
++#define SPI_PTCR_TXTDIS_MASK 0x00000200
++#define SPI_PTCR_TXTDIS_OFFSET 9
++#define SPI_PTCR_TXTDIS_SIZE 1
++#define SPI_PTCR_TXTEN 8
++#define SPI_PTCR_TXTEN_MASK 0x00000100
++#define SPI_PTCR_TXTEN_OFFSET 8
++#define SPI_PTCR_TXTEN_SIZE 1
++#define SPI_PTSR 0x00000124
++#define SPI_PTSR_RXTEN 0
++#define SPI_PTSR_RXTEN_MASK 0x00000001
++#define SPI_PTSR_RXTEN_OFFSET 0
++#define SPI_PTSR_RXTEN_SIZE 1
++#define SPI_PTSR_TXTEN 8
++#define SPI_PTSR_TXTEN_MASK 0x00000100
++#define SPI_PTSR_TXTEN_OFFSET 8
++#define SPI_PTSR_TXTEN_SIZE 1
++#define SPI_RCR 0x00000104
++#define SPI_RCR_RXCTR 0
++#define SPI_RCR_RXCTR_MASK 0x0000ffff
++#define SPI_RCR_RXCTR_OFFSET 0
++#define SPI_RCR_RXCTR_SIZE 16
++#define SPI_RD 0
++#define SPI_RDR 0x00000008
++#define SPI_RDRF 0
++#define SPI_RDRF_MASK 0x00000001
++#define SPI_RDRF_OFFSET 0
++#define SPI_RDRF_SIZE 1
++#define SPI_RDR_PCS 16
++#define SPI_RDR_PCS_MASK 0x000f0000
++#define SPI_RDR_PCS_OFFSET 16
++#define SPI_RDR_PCS_SIZE 4
++#define SPI_RDR_RD 0
++#define SPI_RDR_RD_MASK 0x0000ffff
++#define SPI_RDR_RD_OFFSET 0
++#define SPI_RDR_RD_SIZE 16
++#define SPI_RD_MASK 0x0000ffff
++#define SPI_RD_OFFSET 0
++#define SPI_RD_SIZE 16
++#define SPI_RNCR 0x00000114
++#define SPI_RNCR_RXNCR 0
++#define SPI_RNCR_RXNCR_MASK 0x0000ffff
++#define SPI_RNCR_RXNCR_OFFSET 0
++#define SPI_RNCR_RXNCR_SIZE 16
++#define SPI_RNPR 0x00000110
++#define SPI_RPR 0x00000100
++#define SPI_RXBUFF 6
++#define SPI_RXBUFF_MASK 0x00000040
++#define SPI_RXBUFF_OFFSET 6
++#define SPI_RXBUFF_SIZE 1
++#define SPI_RXCTR 0
++#define SPI_RXCTR_MASK 0x0000ffff
++#define SPI_RXCTR_OFFSET 0
++#define SPI_RXCTR_SIZE 16
++#define SPI_RXNCR 0
++#define SPI_RXNCR_MASK 0x0000ffff
++#define SPI_RXNCR_OFFSET 0
++#define SPI_RXNCR_SIZE 16
++#define SPI_RXTDIS 1
++#define SPI_RXTDIS_MASK 0x00000002
++#define SPI_RXTDIS_OFFSET 1
++#define SPI_RXTDIS_SIZE 1
++#define SPI_RXTEN 0
++#define SPI_RXTEN_MASK 0x00000001
++#define SPI_RXTEN_OFFSET 0
++#define SPI_RXTEN_SIZE 1
++#define SPI_SCBR 8
++#define SPI_SCBR_MASK 0x0000ff00
++#define SPI_SCBR_OFFSET 8
++#define SPI_SCBR_SIZE 8
++#define SPI_SPIDIS 1
++#define SPI_SPIDIS_MASK 0x00000002
++#define SPI_SPIDIS_OFFSET 1
++#define SPI_SPIDIS_SIZE 1
++#define SPI_SPIEN 0
++#define SPI_SPIENS 16
++#define SPI_SPIENS_MASK 0x00010000
++#define SPI_SPIENS_OFFSET 16
++#define SPI_SPIENS_SIZE 1
++#define SPI_SPIEN_MASK 0x00000001
++#define SPI_SPIEN_OFFSET 0
++#define SPI_SPIEN_SIZE 1
++#define SPI_SR 0x00000010
++#define SPI_SR_ENDRX 4
++#define SPI_SR_ENDRX_MASK 0x00000010
++#define SPI_SR_ENDRX_OFFSET 4
++#define SPI_SR_ENDRX_SIZE 1
++#define SPI_SR_ENDTX 5
++#define SPI_SR_ENDTX_MASK 0x00000020
++#define SPI_SR_ENDTX_OFFSET 5
++#define SPI_SR_ENDTX_SIZE 1
++#define SPI_SR_MODF 2
++#define SPI_SR_MODF_MASK 0x00000004
++#define SPI_SR_MODF_OFFSET 2
++#define SPI_SR_MODF_SIZE 1
++#define SPI_SR_NSSR 8
++#define SPI_SR_NSSR_MASK 0x00000100
++#define SPI_SR_NSSR_OFFSET 8
++#define SPI_SR_NSSR_SIZE 1
++#define SPI_SR_OVRES 3
++#define SPI_SR_OVRES_MASK 0x00000008
++#define SPI_SR_OVRES_OFFSET 3
++#define SPI_SR_OVRES_SIZE 1
++#define SPI_SR_RDRF 0
++#define SPI_SR_RDRF_MASK 0x00000001
++#define SPI_SR_RDRF_OFFSET 0
++#define SPI_SR_RDRF_SIZE 1
++#define SPI_SR_RXBUFF 6
++#define SPI_SR_RXBUFF_MASK 0x00000040
++#define SPI_SR_RXBUFF_OFFSET 6
++#define SPI_SR_RXBUFF_SIZE 1
++#define SPI_SR_SPIENS 16
++#define SPI_SR_SPIENS_MASK 0x00010000
++#define SPI_SR_SPIENS_OFFSET 16
++#define SPI_SR_SPIENS_SIZE 1
++#define SPI_SR_TDRE 1
++#define SPI_SR_TDRE_MASK 0x00000002
++#define SPI_SR_TDRE_OFFSET 1
++#define SPI_SR_TDRE_SIZE 1
++#define SPI_SR_TXBUFE 7
++#define SPI_SR_TXBUFE_MASK 0x00000080
++#define SPI_SR_TXBUFE_OFFSET 7
++#define SPI_SR_TXBUFE_SIZE 1
++#define SPI_SR_TXEMPTY 9
++#define SPI_SR_TXEMPTY_MASK 0x00000200
++#define SPI_SR_TXEMPTY_OFFSET 9
++#define SPI_SR_TXEMPTY_SIZE 1
++#define SPI_SWRST 7
++#define SPI_SWRST_MASK 0x00000080
++#define SPI_SWRST_OFFSET 7
++#define SPI_SWRST_SIZE 1
++#define SPI_TCR 0x0000010c
++#define SPI_TCR_TXCTR 0
++#define SPI_TCR_TXCTR_MASK 0x0000ffff
++#define SPI_TCR_TXCTR_OFFSET 0
++#define SPI_TCR_TXCTR_SIZE 16
++#define SPI_TD 0
++#define SPI_TDR 0x0000000c
++#define SPI_TDRE 1
++#define SPI_TDRE_MASK 0x00000002
++#define SPI_TDRE_OFFSET 1
++#define SPI_TDRE_SIZE 1
++#define SPI_TDR_LASTXFER 24
++#define SPI_TDR_LASTXFER_MASK 0x01000000
++#define SPI_TDR_LASTXFER_OFFSET 24
++#define SPI_TDR_LASTXFER_SIZE 1
++#define SPI_TDR_PCS 16
++#define SPI_TDR_PCS_MASK 0x000f0000
++#define SPI_TDR_PCS_OFFSET 16
++#define SPI_TDR_PCS_SIZE 4
++#define SPI_TDR_TD 0
++#define SPI_TDR_TD_MASK 0x0000ffff
++#define SPI_TDR_TD_OFFSET 0
++#define SPI_TDR_TD_SIZE 16
++#define SPI_TD_MASK 0x0000ffff
++#define SPI_TD_OFFSET 0
++#define SPI_TD_SIZE 16
++#define SPI_TNCR 0x0000011c
++#define SPI_TNCR_TXNCR 0
++#define SPI_TNCR_TXNCR_MASK 0x0000ffff
++#define SPI_TNCR_TXNCR_OFFSET 0
++#define SPI_TNCR_TXNCR_SIZE 16
++#define SPI_TNPR 0x00000118
++#define SPI_TPR 0x00000108
++#define SPI_TXBUFE 7
++#define SPI_TXBUFE_MASK 0x00000080
++#define SPI_TXBUFE_OFFSET 7
++#define SPI_TXBUFE_SIZE 1
++#define SPI_TXCTR 0
++#define SPI_TXCTR_MASK 0x0000ffff
++#define SPI_TXCTR_OFFSET 0
++#define SPI_TXCTR_SIZE 16
++#define SPI_TXEMPTY 9
++#define SPI_TXEMPTY_MASK 0x00000200
++#define SPI_TXEMPTY_OFFSET 9
++#define SPI_TXEMPTY_SIZE 1
++#define SPI_TXNCR 0
++#define SPI_TXNCR_MASK 0x0000ffff
++#define SPI_TXNCR_OFFSET 0
++#define SPI_TXNCR_SIZE 16
++#define SPI_TXTDIS 9
++#define SPI_TXTDIS_MASK 0x00000200
++#define SPI_TXTDIS_OFFSET 9
++#define SPI_TXTDIS_SIZE 1
++#define SPI_TXTEN 8
++#define SPI_TXTEN_MASK 0x00000100
++#define SPI_TXTEN_OFFSET 8
++#define SPI_TXTEN_SIZE 1
++
++enum {
++ SPI_ERROR = -1,
++ SPI_OK = 0,
++ SPI_ERROR_TIMEOUT = 1,
++ SPI_ERROR_ARGUMENT,
++ SPI_ERROR_OVERRUN,
++ SPI_ERROR_MODE_FAULT,
++ SPI_ERROR_OVERRUN_AND_MODE_FAULT
++};
++
++struct spi_options_t {
++ unsigned char reg;
++ unsigned int baudrate;
++ unsigned char bits;
++ unsigned char spck_delay;
++ unsigned char trans_delay;
++ unsigned char stay_act;
++ unsigned char spi_mode;
++};
++
++struct spi_info {
++ void *regs;
++};
++
++int spi_select_chip(unsigned char chip);
++
++int spi_unselect_chip(unsigned char chip);
++
++int spi_setup_chip_reg(struct spi_options_t *options, unsigned int cpuHz);
++
++void spi_enable(void);
++
++void spi_disable(void);
++
++int spi_write(uchar *addr, int alen, uchar *buffer, int len);
++
++int spi_read(uchar *addr, int alen, uchar *buffer, int len);
++
++#define SPI_BIT(name) (1 << SPI_##name##_OFFSET)
++#define SPI_MKBF(name,value) (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
++#define SPI_GETBF(name,value) (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
++#define SPI_INSBF(name,value,old) (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) | SPI_MKBF(name, value))
++
++#define spi_readl(port,reg) readl((port)->regs + SPI_##reg)
++#define spi_writel(port,reg,value) writel((value), (port)->regs + SPI_##reg)
++
++#endif /* #ifndef __SPI_H_ */
+diff -uprN u-boot-orig/drivers/atmel_spi.c u-boot/drivers/atmel_spi.c
+--- u-boot-orig/drivers/atmel_spi.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot/drivers/atmel_spi.c 2007-01-03 10:01:26.000000000 +0100
+@@ -0,0 +1,330 @@
++/*
++ * Copyright (C) 2004-2006 Atmel Corporation
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#include <common.h>
++
++#ifdef CONFIG_ATMEL_SPI
++
++#include <part.h>
++#include <malloc.h>
++#include <spi.h>
++#include <atmel_spi.h>
++
++#include <asm/io.h>
++#include <asm/errno.h>
++#include <asm/byteorder.h>
++
++#include <asm/arch/memory-map.h>
++#include <asm/arch/platform.h>
++
++
++struct spi_info *spi;
++
++void spi_reset(struct spi_info *spi);
++
++int get_baud_div(struct spi_options_t * options, int busHz);
++
++int spi_selection_mode(unsigned char variable_ps,
++ unsigned char pcs_decode,
++ unsigned char delay);
++
++void spi_reset(struct spi_info *spi)
++{
++ spi_writel(spi, CR, SPI_BIT(CR_SWRST));
++}
++
++void spi_init()
++{
++ const struct device *dev;
++
++#ifdef CFG_SPI0
++ dev = get_device(DEVICE_SPI0);
++#elif CFG_SPI1
++ dev = get_device(DEVICE_SPI1);
++#else
++#error No SPI device available
++#endif
++ if (!dev)
++ return;
++
++ spi = malloc(sizeof(struct spi_info));
++ if (!spi)
++ return;
++
++ spi->regs = dev->regs;
++
++ /* Reset */
++ spi_reset(spi);
++
++ /* Master Mode */
++ spi_writel(spi, MR, SPI_BIT(MR_MSTR)
++ |SPI_MR_PCS_MASK
++ |(0<<SPI_MR_FDIV_OFFSET)
++ |(0<<SPI_MR_MODFDIS_OFFSET));
++
++ /* Selection mode:
++ * no variable peripheral select
++ * no peripheral chip select decode
++ * 0 delay cycles after a chip select
++ */
++ if (!spi_selection_mode(0, 0, 0))
++ return;
++
++ debug("spi: controller at 0x%08x\n", spi->regs);
++}
++
++int spi_selection_mode(unsigned char variable_ps,
++ unsigned char pcs_decode,
++ unsigned char delay)
++{
++ if (variable_ps > 1 || pcs_decode > 1) {
++ return SPI_ERROR_ARGUMENT;
++ }
++
++ /* Unset bitfields */
++ spi_writel(spi, MR, spi_readl(spi, MR) &
++ ~(SPI_MR_PS_MASK|SPI_MR_PCSDEC_MASK
++ |SPI_MR_DLYBCS_MASK));
++ /* Set selction bits */
++ spi_writel(spi, MR, spi_readl(spi, MR)
++ |SPI_MKBF(MR_PS, variable_ps)
++ |SPI_MKBF(MR_PCSDEC, pcs_decode)
++ |SPI_MKBF(MR_DLYBCS, delay));
++
++ return SPI_OK;
++}
++
++int spi_select_chip(unsigned char chip)
++{
++ /* Assert all lines; no peripheral is selected */
++ spi_writel(spi, MR_PCS, spi_readl(spi, MR)|SPI_MR_PCS_MASK);
++
++ if (spi_readl(spi, MR) & SPI_MR_PCSDEC_MASK) {
++ ulong status;
++
++ /* The signal is decoded; allow up to 15 chips */
++ if (chip > 14) {
++ return SPI_ERROR_ARGUMENT;
++ }
++
++ status = spi_readl(spi, MR);
++ status &= ~SPI_MR_PCS_MASK;
++ status |= SPI_MKBF(MR_PCS, chip);
++ spi_writel(spi, MR, status);
++ } else {
++ if (chip > 3) {
++ return SPI_ERROR_ARGUMENT;
++ }
++
++ spi_writel(spi, MR, spi_readl(spi, MR) &
++ ~(1<<(SPI_MR_PCS_OFFSET + chip)));
++ }
++
++ debug("spi: chip select %d activated\n", chip);
++
++ return SPI_OK;
++}
++
++int spi_unselect_chip(unsigned char chip)
++{
++ /* Assert all lines; no peripheral is selected */
++ spi_writel(spi, MR, spi_readl(spi, MR)|SPI_MR_PCS_MASK);
++
++ /* Last transfer, so deassert the current NPCS if CSAAT is set */
++ spi_writel(spi, CR, spi_readl(spi, MR)|SPI_CR_LASTXFER_MASK);
++
++ debug("spi: chip select %d deactivated\n", chip);
++
++ return SPI_OK;
++}
++
++int spi_setup_chip_reg(struct spi_options_t *options,
++ unsigned int busHz)
++{
++ int baudDiv = -1;
++ unsigned long csr = 0;
++
++ if (options->bits > 16 || options->bits < 8 || options->stay_act > 1) {
++ return SPI_ERROR_ARGUMENT;
++ }
++
++ baudDiv = get_baud_div(options, busHz);
++
++ if (baudDiv < 0) {
++ return -baudDiv;
++ }
++
++ /* Will use CSR0 offsets; these are the same for CSR0 - CSR3 */
++ csr = ((options->bits - 8)<<SPI_CSR0_BITS_OFFSET)|
++ (baudDiv<<SPI_CSR0_SCBR_OFFSET)|
++ (options->spck_delay<<SPI_CSR0_DLYBS_OFFSET)|
++ (options->trans_delay<<SPI_CSR0_DLYBCT_OFFSET)|
++ (options->stay_act<<SPI_CSR0_CSAAT_OFFSET);
++
++ switch (options->spi_mode) {
++ case 0:
++ csr |= (1<<SPI_CSR0_NCPHA_OFFSET); /* pass through */
++ case 1:
++ break;
++ case 2:
++ csr |= (1<<SPI_CSR0_NCPHA_OFFSET); /* pass through */
++ case 3:
++ csr |= (1<<SPI_CSR0_CPOL_OFFSET);
++ break;
++ default: /* Not in legal range */
++ return SPI_ERROR_ARGUMENT;
++ }
++
++ switch (options->reg) {
++ case 0:
++ spi_writel(spi, CSR0, csr);
++ break;
++ case 1:
++ spi_writel(spi, CSR1, csr);
++ break;
++ case 2:
++ spi_writel(spi, CSR2, csr);
++ break;
++ case 3:
++ spi_writel(spi, CSR3, csr);
++ break;
++ default:
++ return SPI_ERROR_ARGUMENT;
++ }
++
++ debug("spi: chip select %d registered\n", options->reg);
++
++ return SPI_OK;
++}
++
++void spi_enable()
++{
++ spi_writel(spi, CR, SPI_BIT(CR_SPIEN));
++}
++
++void spi_disable()
++{
++ spi_writel(spi, CR, SPI_BIT(CR_SPIDIS));
++}
++
++int spi_write(uchar *addr, int alen, uchar *buffer, int len)
++{
++ int sent = 0;
++ uchar *addr_p = addr;
++ uchar *buffer_p = buffer;
++ unsigned int timeout = SPI_TIMEOUT;
++
++ if ((alen + len) <= 0)
++ return -SPI_ERROR_ARGUMENT;
++
++ do {
++ while (!(spi_readl(spi, SR) & SPI_BIT(SR_TXEMPTY)) && --timeout);
++ if (!timeout)
++ return -SPI_ERROR_TIMEOUT;
++ if (len > 0 || alen > 1)
++ spi_writel(spi, TDR, *addr_p++ & 0x0000FFFF);
++ else
++ spi_writel(spi, TDR, (*addr_p++ & 0x0000FFFF)
++ | SPI_BIT(TDR_LASTXFER));
++ sent++;
++ } while (--alen > 0);
++
++ timeout = SPI_TIMEOUT;
++
++ do {
++ while (!(spi_readl(spi, SR) & SPI_BIT(SR_TXEMPTY)) && --timeout);
++ if (!timeout)
++ return -SPI_ERROR_TIMEOUT;
++ if (len > 1)
++ spi_writel(spi, TDR, *buffer_p++ & 0x0000FFFF);
++ else
++ spi_writel(spi, TDR, (*buffer_p++ & 0x0000FFFF)
++ | SPI_BIT(TDR_LASTXFER));
++ sent++;
++ } while (--len > 0);
++
++ return sent;
++}
++
++int spi_read(uchar *addr, int alen, uchar *buffer, int len)
++{
++ int received = 0;
++ uchar *addr_p = addr;
++ uchar *buffer_p = buffer;
++ unsigned int timeout = SPI_TIMEOUT;
++
++ if ((alen + len) <= 0)
++ return SPI_ERROR_ARGUMENT;
++
++ do {
++ while (!(spi_readl(spi, SR) & SPI_BIT(SR_RDRF)) && --timeout);
++ if (!timeout)
++ return -SPI_ERROR_TIMEOUT;
++ *addr_p++ = spi_readl(spi, RDR) & 0x000000FF;
++ --alen;
++ received++;
++ } while (alen > 0);
++
++ timeout = SPI_TIMEOUT;
++
++ do {
++ while (!(spi_readl(spi, SR) & SPI_BIT(SR_RDRF)) && --timeout);
++ if (!timeout)
++ return -SPI_ERROR_TIMEOUT;
++ *buffer_p++ = spi_readl(spi, RDR) & 0x000000FF;
++ --len;
++ received++;
++ } while (len > 0);
++
++ return received;
++}
++
++int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din)
++{
++ int len = 0;
++ uchar *dout_p = dout;
++ uchar *din_p = din;
++
++ while (--bitlen) {
++ if (spi_write(dout_p++, 1, 0, 0) != 1)
++ break;
++ if (spi_read(din_p++, 1, 0, 0) != 1)
++ break;
++ len++;
++ }
++
++ return len;
++}
++
++int get_baud_div(struct spi_options_t *options, int busHz) {
++ int baudDiv = 0;
++
++ baudDiv = busHz / options->baudrate;
++
++ if (baudDiv > (SPI_CSR0_SCBR_MASK<<SPI_CSR0_SCBR_OFFSET)
++ || baudDiv <= 0) {
++ return -SPI_ERROR_ARGUMENT;
++ }
++
++ return baudDiv;
++}
++
++#endif /* CONFIG_ATMEL_SPI */
+diff -uprN u-boot-orig/drivers/Makefile u-boot/drivers/Makefile
+--- u-boot-orig/drivers/Makefile 2007-01-01 19:26:46.000000000 +0100
++++ u-boot/drivers/Makefile 2007-01-01 16:10:49.000000000 +0100
+@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
+ LIB = libdrivers.a
+
+ OBJS = 3c589.o 5701rls.o ali512x.o \
+- atmel_usart.o atmel_lcdc.o \
++ atmel_usart.o atmel_lcdc.o atmel_spi.o \
+ bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
+ cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
+ e1000.o eepro100.o \
diff --git a/recipes/u-boot/u-boot-1.1.4/u-boot-autoscript.patch b/recipes/u-boot/u-boot-1.1.4/u-boot-autoscript.patch
new file mode 100644
index 0000000000..1864b4494e
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/u-boot-autoscript.patch
@@ -0,0 +1,12 @@
+--- u-boot-1.1.2/common/cmd_autoscript.c
++++ u-boot-1.1.2/common/cmd_autoscript.c
+@@ -110,8 +110,8 @@
+ return 1;
+ }
+
+- while (*len_ptr++);
++ do { len_ptr++; } while (!(*len_ptr));
+
+ /* make sure cmd is null terminated */
+ memmove (cmd, (char *)len_ptr, len);
+ *(cmd + len) = 0;
diff --git a/recipes/u-boot/u-boot-1.1.4/u-boot-base.patch b/recipes/u-boot/u-boot-1.1.4/u-boot-base.patch
new file mode 100644
index 0000000000..d866c1c26e
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/u-boot-base.patch
@@ -0,0 +1,913 @@
+--- a/MAKEALL
++++ a/MAKEALL
+@@ -146,8 +146,8 @@
+
+ LIST_pxa=" \
+ adsvix cerf250 cradle csb226 \
+- innokom lubbock pxa255_idp wepep250 \
+- xaeniax xm250 xsengine \
++ gumstix innokom lubbock pxa255_idp \
++ wepep250 xaeniax xm250 xsengine \
+ "
+
+ LIST_ixp="ixdp425"
+--- a/Makefile
++++ a/Makefile
+@@ -121,7 +121,6 @@
+ # The "tools" are needed early, so put this first
+ # Don't include stuff already done in $(LIBS)
+ SUBDIRS = tools \
+- examples \
+ post \
+ post/cpu
+ .PHONY : $(SUBDIRS)
+@@ -1078,6 +1077,9 @@
+ csb226_config : unconfig
+ @./mkconfig $(@:_config=) arm pxa csb226
+
++gumstix_config : unconfig
++ @./mkconfig $(@:_config=) arm pxa gumstix
++
+ innokom_config : unconfig
+ @./mkconfig $(@:_config=) arm pxa innokom
+
+--- a/board/gumstix/Makefile
++++ a/board/gumstix/Makefile
+@@ -0,0 +1,47 @@
++#
++# (C) Copyright 2004
++# Craig Hughes, Gumstix Inc, <craig@gumstix.com>
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = lib$(BOARD).a
++
++OBJS := gumstix.o
++SOBJS := memsetup.o
++
++$(LIB): $(OBJS) $(SOBJS)
++ $(AR) crv $@ $^
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
++
++-include .depend
++
++#########################################################################
+--- a/board/gumstix/config.mk
++++ a/board/gumstix/config.mk
+@@ -0,0 +1,13 @@
++#
++# This is config used for compilation of Gumstix sources
++#
++# You might change location of U-Boot in memory by setting right TEXT_BASE.
++# This allows for example having one copy located at the end of ram and stored
++# in flash device and later on while developing use other location to test
++# the code in RAM device only.
++#
++
++TEXT_BASE = 0xA3F00000
++ifeq ($(GUMSTIX_400MHZ),y)
++ PLATFORM_CPPFLAGS += -DCONFIG_GUMSTIX_CPUSPEED_400
++endif
+--- a/board/gumstix/early_refresh.S
++++ a/board/gumstix/early_refresh.S
+@@ -0,0 +1,50 @@
++#define COTULLA_CP15_B1_VAL 0x69052903
++ /* Workaround for early termination of SDRAM autorefresh on exit from
++ processor's sleep state in B1 stepping of XPA250/210. (sighting 27004)
++ Need first forced refresh within 8 usec.
++
++ - Code snippet received from validation team, slightly modified
++
++ Notes: - MMU assumed to be inactive at this time, so use physical addresses
++ - Eboot didn't boot on A1 stepping without the leading exclusion,
++ so the core code must be restricted to B1 only.
++ */
++
++ mrc p15, 0, r9, c0, c0, 0 @ Grab CPU ID
++ ldr r3, =COTULLA_CP15_B1_VAL @ Load the B1 CPU ID value
++ cmp r9, r3
++ bne EARLY_REFRESH_DONE
++
++ @ Eboot loads BIN image into RAM,
++ @ turns off the MMU and then jumps here.
++ @ If we're already executing from RAM, don't mess with it
++
++ mov r0, #0x400000 @ Just at the end of boot device addressing space
++ cmp r0, pc @ Are we executing from boot flash space?
++ bls EARLY_REFRESH_DONE @ if outside that space, skip this.
++
++
++ /*
++ Need to set MDREFR:DRI field to 0 for this to work. Side effect is
++ picking the MEMCLK:SDCLK ratio. The specified value (0x038FF000)
++ sets that ratio as 2:1.
++ This corresponds to the defaults after reset, including sleep reset.
++ 0x038ff000 == MDREFR_K2FREE | MDREFR_K1FREE | MDREFR_K0FREE |
++ MDREFR_K2DB2 | MDREFR_K2RUN |
++ MDREFR_K1DB2 | MDREFR_K1RUN | MDREFR_E1PIN |
++ MDREFR_K0DB2 | MDREFR_K0RUN | MDREFR_E0PIN
++ */
++
++ ldr r0, =0X48000004 @ Memory controller base physical addr+ REFR Offset.
++ mov r1, #0x03800000
++ orr r1, r1, #0x000FF000
++ str r1, [r0]
++
++ mov r0, #CFG_DRAM_BASE
++ ldr r1, [r0] @ CAUSES the 1st row refresh to all partitions
++ mov r2, #0x2000 @ 8k loo
++1:
++ ldr r1, [r0] @ CAUSES a row refresh to all partitions
++ subs r2, r2, #0x1
++ bpl 1b @ while >= 0
++EARLY_REFRESH_DONE:
+--- a/board/gumstix/gumstix.c
++++ a/board/gumstix/gumstix.c
+@@ -0,0 +1,134 @@
++/*
++ * Copyright (C) 2004 Gumstix, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ * Written by Craig Hughes <craig@gumstix.com>
++ *
++ */
++
++#include <common.h>
++#include <asm/arch/pxa-regs.h>
++
++int board_init( void ){
++ DECLARE_GLOBAL_DATA_PTR;
++
++ gd->bd->bi_arch_number = 373;
++ gd->bd->bi_boot_params = 0xa0000100;
++
++ PSSR = 0x20;
++
++ GPDR1 = CFG_GPDR1_VAL;
++ GAFR1_L = CFG_GAFR1_L_VAL;
++
++ return 0;
++}
++
++int dram_init( void ){
++ DECLARE_GLOBAL_DATA_PTR;
++
++#if ( CONFIG_NR_DRAM_BANKS > 0 )
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++#endif
++#if ( CONFIG_NR_DRAM_BANKS > 1 )
++ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
++ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
++#endif
++#if ( CONFIG_NR_DRAM_BANKS > 2 )
++ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
++ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
++#endif
++#if ( CONFIG_NR_DRAM_BANKS > 3 )
++ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
++ gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
++#endif
++
++ return 0;
++}
++
++extern flash_info_t flash_info[]; /* info for FLASH chips */
++
++static u8 system_serial[8];
++
++void get_board_serial(struct tag_serialnr *serialnr)
++{
++ serialnr->high = (system_serial[0]<<24) + (system_serial[1]<<16) + (system_serial[2]<<8) + system_serial[3];
++ serialnr->low = (system_serial[4]<<24) + (system_serial[5]<<16) + (system_serial[6]<<8) + system_serial[7];
++}
++
++/*
++ * This hash function converts a structured 64-bit number to an unstructured, more bit-random 64-bit number.
++ * The purpose is to provide more randomness for each bit of the system serial number, since we're going to
++ * be using some of its bits (by extraction) as the varying part of an ethernet MAC. So more random bits =
++ * less chance of collision
++ *
++ * The has algorithm is basically going to work by looping through each bit in the incoming number. If that bit
++ * is set, then we'll XOR our result with a bitmask; if not, then we leave the result and continue the loop.
++ * Each time through the loop, we rotate the bitmask by one bit position, so that each bit of the incoming number
++ * will affect half of the bits of the result, but which bits it modifies are unique to that incoming bit position
++ */
++void gumstix_serial_hash(u8 *buf)
++{
++ unsigned int bit_number,byte;
++ // Starting bitmask is 0b0101001100001111000000001111111100000000000000001111111111111111
++ u8 xor_mask[] = { 0x53, 0x0F, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0xFF };
++
++ u8 result[8];
++
++ // Loop through all 64 bits
++ for(bit_number=0; bit_number<64; bit_number++)
++ {
++ // If the given bit is set in the incoming buffer
++ if(buf[bit_number/8] & (1 << (bit_number % 8)))
++ {
++ // XOR the masked bits of the result
++ for(byte=0;byte<8;byte++) result[byte] ^= xor_mask[byte];
++ }
++
++ // Now rotate the bitmask
++ for(byte=0;byte<8;byte++)
++ {
++ // Shift the byte up by one bit
++ xor_mask[byte] = xor_mask[byte]<<1;
++ // Take the most significant bit of the previous byte and tack that on the bottom
++ // Special case for byte==0 when we take the MSB of the top byte instead
++ xor_mask[byte] |= xor_mask[(byte == 0 ? 7 : byte-1)]>>7;
++ }
++ }
++
++ // Copy result out
++ for(byte=0;byte<8;byte++) buf[byte]=result[byte];
++}
++
++int misc_init_r(void)
++{
++ unsigned char serial[17];
++
++ flash_read_user_serial(flash_info, (void *)system_serial, 0, 8);
++ if(0xff == (system_serial[0] & system_serial[1] & system_serial[2] & system_serial[3] &
++ system_serial[4] & system_serial[5] & system_serial[6] & system_serial[7]))
++ {
++ // User serial number is all ones, so use the factory serial number
++ flash_read_factory_serial(flash_info, (void *)system_serial, 0, 8);
++ gumstix_serial_hash(system_serial);
++ }
++
++ sprintf(serial,"%02lX%02lX%02lX%02lX%02lX%02lX%02lX%02lX",system_serial[0],system_serial[1],system_serial[2],system_serial[3],
++ system_serial[4],system_serial[5],system_serial[6],system_serial[7]);
++
++ setenv("serial#",serial);
++}
+--- a/board/gumstix/memsetup.S
++++ a/board/gumstix/memsetup.S
+@@ -0,0 +1,229 @@
++#include <config.h>
++#include <version.h>
++#include <asm/arch/pxa-regs.h>
++
++
++.macro CPWAIT
++ mrc p15,0,r0,c2,c0,0
++ mov r0,r0
++ sub pc,pc,#4
++.endm
++
++
++.globl lowlevel_init
++lowlevel_init:
++
++
++ cmp pc, #0xa0000000 /** test if we're in SDRAM **/
++ bhi end_of_memsetup /** if we are, then jump **/
++
++ /* First, setup GPIOs */
++
++ ldr r0, =GPSR0
++ ldr r1, =CFG_GPSR0_VAL
++ str r1, [r0]
++
++ ldr r0, =GPSR1
++ ldr r1, =CFG_GPSR1_VAL
++ str r1, [r0]
++
++ ldr r0, =GPSR2
++ ldr r1, =CFG_GPSR2_VAL
++ str r1, [r0]
++
++ ldr r0, =GPCR0
++ ldr r1, =CFG_GPCR0_VAL
++ str r1, [r0]
++
++ ldr r0, =GPCR1
++ ldr r1, =CFG_GPCR1_VAL
++ str r1, [r0]
++
++ ldr r0, =GPCR2
++ ldr r1, =CFG_GPCR2_VAL
++ str r1, [r0]
++
++ ldr r0, =GPDR0
++ ldr r1, =CFG_GPDR0_VAL
++ str r1, [r0]
++
++ ldr r0, =GPDR1
++ ldr r1, =CFG_GPDR1_VAL
++ str r1, [r0]
++
++ ldr r0, =GPDR2
++ ldr r1, =CFG_GPDR2_VAL
++ str r1, [r0]
++
++ ldr r0, =GAFR0_L
++ ldr r1, =CFG_GAFR0_L_VAL
++ str r1, [r0]
++
++ ldr r0, =GAFR0_U
++ ldr r1, =CFG_GAFR0_U_VAL
++ str r1, [r0]
++
++ ldr r0, =GAFR1_L
++ ldr r1, =CFG_GAFR1_L_VAL
++ str r1, [r0]
++
++ ldr r0, =GAFR1_U
++ ldr r1, =CFG_GAFR1_U_VAL
++ str r1, [r0]
++
++ ldr r0, =GAFR2_L
++ ldr r1, =CFG_GAFR2_L_VAL
++ str r1, [r0]
++
++ ldr r0, =GAFR2_U
++ ldr r1, =CFG_GAFR2_U_VAL
++ str r1, [r0]
++
++ ldr r0, =PSSR
++ ldr r1, =CFG_PSSR_VAL
++ str r1, [r0]
++
++
++ /* The procedure below uses sample code generated by the Intel PXA250 Memory
++ * Configuration Tool [http://appzone.intel.com/pcg/pxa250/memory/] which has
++ * then been modified manually while following the documentation in
++ * "Intel PXA255 Process Developer's Manual" [order #278693-002]
++ * Chapter 6.11 - Hardware, Watchdog, or Sleep Reset Operation */
++
++ /* Step 1: After hardware reset, complete a power-on wait of 200us to allow clocks to stabilize */
++
++ ldr r3, =OSCR /* reset the OS Timer Count to zero */
++ mov r2, #0
++ str r2, [r3]
++ ldr r4, =0x300 /* really 0x2E1 is about 200usec, so 0x300 should be plenty */
++10:
++ ldr r2, [r3]
++ cmp r4, r2
++ bgt 10b
++
++ /* Step 1a: Write MSC0, MSC1, MSC2 */
++ ldr r3, =MSC0 /* Configures /CS0 and /CS1 */
++ ldr r2, =0x128C26AB /* Generated value */
++ str r2, [r3]
++ ldr r2, [r3] /* the MSC register should be read after it is written with */
++ /* a new value before an access to the memory is attempted. */
++ /* (see MSC section of manual) */
++ ldr r3, =MSC1 /* /CS2 and /CS3 */
++ ldr r2, =0x0000128C /* Generated value */
++ str r2, [r3]
++ ldr r2, [r3]
++
++ /* Step 1b: Write MECR, MCMEM0, MCMEM1, MCATT0, MCATT1, MCIO0, MCIO1 (Skip on gumstix) */
++ /* Step 1c: Write MDREFR:K0RUN and MDREFR:E0PIN. Configure MDREFR:K0DB2. Retain
++ * the current values of MDREFR:APD and MDREFR:SLFRSH. MDREFR:DRI must
++ * contain a valid value. Deassert MDREFR:KxFREE. (Skip on gumstix) */
++
++ ldr r3, =MDREFR
++ ldr r2, [r3] /* read MDREFR value */
++
++ ldr r1, =0xfff
++ bic r2, r2, r1 /* Clear DRI -- INTEL TOOL LEAVES THIS STEP OUT!! */
++ orr r2, r2, #0x018 /* configure a valid SDRAM Refresh Interval (DRI) */
++ str r2, [r3]
++
++ /* Step 2: Configure Synchronous Static memory (Skip on gumstix) */
++
++ /* Step 4: In systems that contain SDRAM, transition the SDRAM controller through the following state sequence:
++ * a. self-refresh
++ * b. power-down
++ * c. PWRDNX
++ * d. NOP */
++
++ orr r2, r2, #0x00010000 /* assert K1RUN for SDCLK1 */
++ bic r2, r2, #0x000A4000 /* clear K0DB2, K1DB2 and K2DB2 */
++ str r2, [r3] /* change from "self-refresh and clock-stop" to "self-refresh" state */
++
++ bic r2, r2, #0x00400000 /* clear SLFRSH bit field */
++ str r2, [r3] /* change from "self-refresh" to "Power-down" state */
++
++ orr r2, r2, #0x00008000 /* set the E1PIN bit field */
++ str r2, [r3] /* change from "Power-down" to "PWRDNX" state */
++
++ nop /* no action is required to change from "PWRDNX" to "NOP" state */
++
++ /* Step 4f: Write MDCNFG (with enable bits deasserted), MDCNFG:DE3:2,1:0 set to 0. */
++
++ ldr r3, =MDCNFG /* Load the SDRAM Configuration register. Must not be enabled yet. */
++ ldr r2, =0x000019C8 /* Value from Intel tool */
++ str r2, [r3] /* Write to MDCNFG register */
++
++ /* Step 5: For systems that contain SDRAM, wait a specified NOP power-up waiting period required by
++ * the SDRAMs to ensure the SDRAMs receive a stable clock with a NOP condition */
++
++ ldr r3, =OSCR /* reset the OS Timer Count to zero */
++ mov r2, #0
++ str r2, [r3]
++ ldr r4, =0x300 /* really 0x2E1 is about 200usec, so 0x300 should be plenty */
++20:
++ ldr r2, [r3]
++ cmp r4, r2
++ bgt 20b
++
++ /* Step 6: Ensure the data cache is disabled -- should not be needed out of reset, but best to be safe*/
++
++ mov r0, #0x78 /* turn everything off */
++ mcr p15, 0, r0, c1, c0, 0 /* caches off, MMU off, etc. */
++
++ CPWAIT /* wait for co-processor */
++
++ /* Step 7: On a hardware reset in systems that contain SDRAM, trigger the specified number (typically
++ eight) of refresh cycles by attempting non-burst read or write accesses to any disabled
++ SDRAM bank. Each such access causes a simultaneous CBR refresh cycles for all four banks,
++ which causes a pass through the CBR state and back to NOP. On the first pass, the PALL state
++ occurs before the CBR state. */
++
++ ldr r3, =PHYS_SDRAM_1
++ mov r2, #9 /* now must do 9 (!) refresh or CBR commands before the first access */
++CBR_refresh1:
++ str r2, [r3]
++ subs r2, r2, #1
++ bne CBR_refresh1
++
++ /* Step 8: Can re-enable DCACHE if it was disabled above (Skip on gumstix) */
++
++ /* Step 9: Enable SDRAM partitions */
++
++ ldr r3, =MDCNFG /* sdram config -- sdram enable */
++ ldr r2, [r3]
++ orr r2, r2, #0x00000001 /* enable partition 0 only */
++ str r2, [r3] /* write to MDCNFG */
++
++ /* Step 10: In systems containing SDRAM, write the MDMRS register to trigger an MRS command to all
++ * enabled banks of SDRAM. For each SDRAM partition pair that has one or both partitions
++ * enabled, this forces a pass through the MRS state and back to NOP. The CAS latency must be
++ * the only variable option and is derived from the value programmed in the
++ * MDCNFG:MDTC0,2 fields. The burst type is programmed to sequential and the length is set
++ * to four. */
++
++ ldr r3, =MDMRS /* write the MDMRS */
++ ldr r2, =0x00020022 /* the writable bits will be written as a 0 */
++ str r2, [r3]
++
++ /* Step 11: (optional) Enable auto-power-down */
++
++ ldr r3, =MDREFR /* enable auto-power-down */
++ ldr r2, [r3]
++ orr r2, r2, #0x00100000 /* set the APD bit */
++ str r2, [r3] /* write to MDREFR */
++
++ /* enable the 32Khz oscillator for RTC and PowerManager */
++
++ ldr r1, =OSCC
++ mov r2, #OSCC_OON
++ str r2, [r1]
++
++ /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
++ /* has settled. */
++/*60:
++ ldr r2, [r1]
++ ands r2, r2, #1
++ beq 60b */
++
++end_of_memsetup:
++ mov pc, lr
++
+--- a/board/gumstix/u-boot.lds
++++ a/board/gumstix/u-boot.lds
+@@ -0,0 +1,55 @@
++/*
++ * (C) Copyright 2004
++ * Craig Hughes, Gumstix Inc, <craig@gumstix.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++ . = 0x00000000;
++
++ . = ALIGN(4);
++ .text :
++ {
++ cpu/pxa/start.o (.text)
++ board/gumstix/memsetup.o (.text)
++ *(.text)
++ }
++ . = ALIGN(4);
++ .rodata : { *(.rodata) }
++
++ . = ALIGN(4);
++ .data : { *(.data) }
++
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
+--- a/cpu/pxa/start.S
++++ a/cpu/pxa/start.S
+@@ -91,6 +91,7 @@
+ .word 0x0badc0de
+ #endif
+
++.space 0x800 /* JTAG install interrupt vectors over low memory in instruction cache */
+
+ /****************************************************************************/
+ /* */
+@@ -104,6 +105,37 @@
+ orr r0,r0,#0x13
+ msr cpsr,r0
+
++/* This special code just unprotects all of flash, then erases it */
++// mov r0, #0x1f /* Loop over all blocks 0x1f-0x00*/
++//flash_wipe_main_loop:
++// mov r1, r0, LSL #0x11 /* Convert bank number to start address */
++// mov r2, #0x60 /* Clear lock bit setup */
++// strh r2, [r1]
++// nop
++// mov r2, #0xd0 /* Clear lock bits confirm */
++// strh r2, [r1]
++// nop
++//flash_clear_wait_loop:
++// ldrh r2, [r1]
++// tst r2, #0x80 /* Check SR.7 */
++// bne flash_clear_wait_loop
++//
++// mov r2, #0x20 /* Block erase command */
++// strh r2, [r1]
++// nop
++// mov r2, #0xd0 /* Block erase confirm */
++// strh r2, [r1]
++// nop
++//flash_erase_wait_loop:
++// ldrh r2, [r1]
++// tst r2, #0x80
++// bne flash_clear_wait_loop
++//
++// teq r0, #0
++// subne r0, r0, #1
++// bne flash_wipe_main_loop
++/* End of flash-nuking code */
++
+ /*
+ * we do sys-critical inits only at reboot,
+ * not when booting from ram!
+@@ -113,7 +145,7 @@
+ #endif
+
+ relocate: /* relocate U-Boot to RAM */
+- adr r0, _start /* r0 <- current position of code */
++ adrl r0, _start /* r0 <- current position of code */
+ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
+ cmp r0, r1 /* don't reloc during debug */
+ beq stack_setup
+--- a/include/configs/gumstix.h
++++ a/include/configs/gumstix.h
+@@ -0,0 +1,259 @@
++/*
++ * Copyright (C) 2004 Gumstix, Inc.
++**
++** Gumstix u-boot 1.1.1
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ * Written by Craig Hughes <craig@gumstix.com> 2004
++ *
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#define CONFIG_PXA250 /* this is an PXA250 CPU */
++#define CONFIG_GUMSTIX /* config for gumstix board */
++#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */
++#ifndef __LITTLE_ENDIAN
++#define __LITTLE_ENDIAN 1234 /* For some reason this is not defined */
++#endif
++
++/*
++ * Select serial console configuration FFUART is default on G dev board
++ */
++
++#define CONFIG_FFUART
++#define CONFIG_BAUDRATE 115200
++#define CONFIG_SILENT_CONSOLE
++
++/*
++ * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
++ * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
++ * functionality or size of u-boot code.
++ */
++
++#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \
++ & ~CFG_CMD_CDP \
++ & ~CFG_CMD_IDE \
++ & ~CFG_CMD_IMLS \
++ & ~CFG_CMD_IRQ \
++ & ~CFG_CMD_PCMCIA \
++ & ~CFG_CMD_SETGETDCR \
++ | CFG_CMD_AUTOSCRIPT \
++ | CFG_CMD_BDI \
++ | CFG_CMD_BOOTD \
++ | CFG_CMD_CACHE \
++ | CFG_CMD_CONSOLE \
++ | CFG_CMD_DHCP \
++ | CFG_CMD_DIAG \
++ | CFG_CMD_ECHO \
++ | CFG_CMD_ELF \
++ | CFG_CMD_ENV \
++ | CFG_CMD_FAT \
++ | CFG_CMD_FLASH \
++ | CFG_CMD_IMI \
++ | CFG_CMD_ITEST \
++ | CFG_CMD_JFFS2 \
++ | CFG_CMD_LOADB \
++ | CFG_CMD_LOADS \
++ | CFG_CMD_MEMORY \
++ | CFG_CMD_MISC \
++ | CFG_CMD_MMC \
++ | CFG_CMD_NET \
++ | CFG_CMD_NFS \
++ | CFG_CMD_PING \
++ | CFG_CMD_REGINFO \
++ | CFG_CMD_RUN \
++ | CFG_CMD_SAVES \
++ | CFG_CMD_SDRAM \
++ )
++
++
++#define CONFIG_NETCONSOLE
++#define CONFIG_NET_MULTI
++
++#define CFG_DEVICE_NULLDEV
++
++#include <cmd_confdefs.h>
++
++/*
++ * Boot options. Setting delay to -1 stops autostart count down.
++ * NOTE: Sending parameters to kernel depends on kernel version and
++ * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
++ * parameters at all! Do not get confused by them so.
++*/
++
++#define CONFIG_IDENT_STRING "\n\n*** Welcome to Gumstix ***"
++#define CONFIG_MISC_INIT_R /* misc_init_r function in gumstix sets board serial number */
++
++#define CONFIG_BOOTFILE boot/uImage
++#define CONFIG_BOOTARGS "console=ttyS0,115200n8 root=1f01 rootfstype=jffs2 reboot=cold,hard"
++#define CONFIG_BOOTCOMMAND "icache on;setenv stderr nulldev; setenv stdout nulldev; if mmcinit && fatload mmc 0 a2000000 gumstix-factory.script; then setenv stdout serial; setenv stderr serial; echo Found gumstix-factory script...; autoscr; else setenv stdout serial;setenv stderr serial;fsload && bootm; fi"
++#define CONFIG_BOOTDELAY 2 /* in seconds */
++#define CONFIG_EXTRA_ENV_SETTINGS "verify=no"
++#define CFG_HUSH_PARSER
++#define CFG_AUTO_COMPLETE
++#define CFG_PROMPT_HUSH_PS2 "> "
++
++/*
++ * General options for u-boot. Modify to save memory foot print
++ */
++
++#define CFG_LONGHELP /* undef saves memory */
++#define CFG_PROMPT "GUM> " /* prompt string */
++#define CFG_CBSIZE 512 /* console I/O buffer */
++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */
++#define CFG_MAXARGS 16 /* max command args */
++#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */
++
++#define CONFIG_CRC32_VERIFY
++#define CONFIG_LOOPW
++#define CONFIG_MX_CYCLIC
++
++/*
++ * * SMSC91C111 Network Card
++ * */
++#define CONFIG_DRIVER_SMC91111 1
++#define CONFIG_SMC91111_BASE 0x04000300 /* chip select 1 */
++#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
++#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
++#undef CONFIG_SHOW_ACTIVITY
++#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
++#define CONFIG_ETHPRIME "SMC91C1111-0"
++#define CONFIG_ETHADDR 00:0A:95:A5:47:3A
++
++
++#define CFG_MEMTEST_START 0xa1000000 /* memtest test area */
++#define CFG_MEMTEST_END 0xa2000000
++
++
++#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */
++#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
++#ifdef CONFIG_GUMSTIX_CPUSPEED_400
++#define CFG_CPUSPEED 0x161 /* 0x161 == 400MHz, 0x141 ==200MHz */
++#else
++#define CFG_CPUSPEED 0x141
++#endif
++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
++
++#define CFG_CONSOLE_INFO_QUIET
++
++/*
++ * Definitions related to passing arguments to kernel.
++ */
++#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
++#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
++#define CONFIG_INITRD_TAG /* send initrd params */
++#define CONFIG_SERIAL_TAG /* send serialnr from flash */
++#undef CONFIG_VFD /* do not send framebuffer setup */
++
++/*
++ * SDRAM Memory Map
++ */
++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
++#define PHYS_SDRAM_1 0xa0000000 /* SDRAM bank #1 */
++#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB ( 2 chip ) */
++
++#define CFG_DRAM_BASE PHYS_SDRAM_1
++#define CFG_DRAM_SIZE PHYS_SDRAM_1_SIZE
++
++/*
++ * Configuration for FLASH memory
++ */
++#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
++#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors */
++
++#define CFG_FLASH_BASE PHYS_FLASH_1
++#define CFG_FLASH_CFI /* flash is CFI conformant */
++#define CFG_FLASH_CFI_DRIVER /* use common cfi driver */
++#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
++#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
++#define CFG_MAX_FLASH_SECT 256 /* max # of sectors on one chip */
++#define CFG_FLASH_PROTECTION /* use hardware flash protection */
++
++#define CFG_ENV_IS_IN_FLASH
++#define CFG_ENV_SIZE 0x1000 /* 4kB */
++#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
++#define CFG_ENV_ADDR ((CFG_FLASH_BASE + CFG_ENV_SECT_SIZE*2) - CFG_ENV_SIZE)
++
++/*
++ * Malloc pool need to host env + 128 Kb reserve for other allocations.
++ */
++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) )
++#define CONFIG_STACKSIZE (120<<10) /* stack size */
++#define CFG_GBL_DATA_SIZE 512 /* num bytes initial data */
++
++/*
++ * This is setting for JFFS2 support in u-boot.
++ * Right now there is no gain for user, but later on booting kernel might be
++ * possible. Consider using XIP kernel running from flash to save RAM
++ * footprint.
++ * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
++ */
++
++#define CFG_JFFS2_FIRST_BANK 0
++#define CFG_JFFS2_FIRST_SECTOR 2
++#define CFG_JFFS2_NUM_BANKS 1
++
++#define CONFIG_MMC 1
++#define CFG_MMC_BASE 0xF0000000
++#define CONFIG_DOS_PARTITION
++
++/*
++ * Environment setup. Definitions of monitor location and size with
++ * definition of environment setup ends up in 2 possibilities.
++ * 1. Embedded environment - in u-boot code is space for environment
++ * 2. Environment is read from predefined sector of flash
++ * Right now we support 2. possiblity, but expecting no env placed
++ * on mentioned address right now. This also needs to provide whole
++ * sector for it - for us 256Kb is really waste of memory. U-boot uses
++ * default env. and until kernel parameters could be sent to kernel
++ * env. has no sense to us.
++ */
++
++#define CFG_MONITOR_BASE CFG_FLASH_BASE
++#define CFG_MONITOR_LEN (PHYS_FLASH_SECT_SIZE*2 - CFG_ENV_SIZE)
++
++#define CFG_GPSR0_VAL 0xFFFFFFFF
++#define CFG_GPSR1_VAL 0xFFEFFFFF
++#define CFG_GPSR2_VAL 0xFFFEFFFF
++
++#define CFG_GPCR0_VAL 0x08022080
++#define CFG_GPCR1_VAL 0x00100000
++#define CFG_GPCR2_VAL 0x00010000
++
++#define CFG_GPDR0_VAL 0xC182B9F8
++#define CFG_GPDR1_VAL 0x0012AA80
++#define CFG_GPDR2_VAL 0x0001FFFF
++
++#define CFG_GAFR0_L_VAL 0x81011000
++#define CFG_GAFR0_U_VAL 0xA5254010
++#define CFG_GAFR1_L_VAL 0x69908010
++#define CFG_GAFR1_U_VAL 0xAAA5A8AA
++#define CFG_GAFR2_L_VAL 0xAAAAAAAA
++#define CFG_GAFR2_U_VAL 0x00000000
++
++#define CFG_PSSR_VAL 0x20
++
++/*
++ * Well this has to be defined, but on the other hand it is used differently
++ * one may expect. For instance loadb command do not cares :-)
++ * So advice is - do not rely on this...
++ */
++
++#define CFG_LOAD_ADDR 0xA2000000
++#endif /* __CONFIG_H */
+--- a/lib_arm/board.c
++++ a/lib_arm/board.c
+@@ -200,10 +200,10 @@
+ NULL,
+ };
+
++DECLARE_GLOBAL_DATA_PTR;
++
+ void start_armboot (void)
+ {
+- DECLARE_GLOBAL_DATA_PTR;
+-
+ ulong size;
+ init_fnc_t **init_fnc_ptr;
+ char *s;
diff --git a/recipes/u-boot/u-boot-1.1.4/u-boot-crc-warning-not-so-scary.patch b/recipes/u-boot/u-boot-1.1.4/u-boot-crc-warning-not-so-scary.patch
new file mode 100644
index 0000000000..b5736894c6
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/u-boot-crc-warning-not-so-scary.patch
@@ -0,0 +1,11 @@
+--- u-boot-1.1.2/common/env_common.c 2005-06-15 12:38:53.632219409 -0700
++++ u-boot-1.1.2/common/env_common.c 2005-06-15 12:39:41.469052324 -0700
+@@ -237,7 +237,7 @@
+ #if defined(CONFIG_GTH) || defined(CFG_ENV_IS_NOWHERE) /* Environment not changable */
+ puts ("Using default environment\n\n");
+ #else
++ puts ("Using default environment\n\n");
+- puts ("*** Warning - bad CRC, using default environment\n\n");
+ SHOW_BOOT_PROGRESS (-1);
+ #endif
+
diff --git a/recipes/u-boot/u-boot-1.1.4/u-boot-dht-walnut-df2.patch b/recipes/u-boot/u-boot-1.1.4/u-boot-dht-walnut-df2.patch
new file mode 100644
index 0000000000..d919ea504e
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/u-boot-dht-walnut-df2.patch
@@ -0,0 +1,186 @@
+diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c
+index f1a96a6..86bcc65 100644
+--- a/board/amcc/walnut/walnut.c
++++ b/board/amcc/walnut/walnut.c
+@@ -73,7 +73,11 @@ int checkboard(void)
+ if (pvr == PVR_405GPR_RB) {
+ puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board");
+ } else {
++#ifdef CONFIG_DHT_WALNUT
++ puts("Board: DHT Walnut");
++#else
+ puts("Board: Walnut - AMCC PPC405GP Evaluation Board");
++#endif
+ }
+
+ if (s != NULL) {
+diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c
+index ebd5f39..1c4c4b1 100644
+--- a/cpu/ppc4xx/spd_sdram.c
++++ b/cpu/ppc4xx/spd_sdram.c
+@@ -398,19 +398,24 @@ long int spd_sdram(int(read_spd)(uint ad
+
+ tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
+ sdram0_b0cr = (bank_size * 0) | tmp;
+-#ifndef CONFIG_405EP /* not on PPC405EP */
++#if defined(CONFIG_405EP)
++ /* PPC405EP chip only supports two SDRAM banks */
++ if (bank_cnt > 1)
++ sdram0_b1cr = (bank_size * 1) | tmp;
++ if (bank_cnt > 2)
++ total_size = 2 * bank_size;
++#elif defined(CONFIG_DHT_WALNUT)
++ if (bank_cnt > 1) {
++ sdram0_b2cr = (bank_size * 1) | tmp;
++ total_size = 2 * bank_size;
++ }
++#else
+ if (bank_cnt > 1)
+ sdram0_b2cr = (bank_size * 1) | tmp;
+ if (bank_cnt > 2)
+ sdram0_b1cr = (bank_size * 2) | tmp;
+ if (bank_cnt > 3)
+ sdram0_b3cr = (bank_size * 3) | tmp;
+-#else
+- /* PPC405EP chip only supports two SDRAM banks */
+- if (bank_cnt > 1)
+- sdram0_b1cr = (bank_size * 1) | tmp;
+- if (bank_cnt > 2)
+- total_size = 2 * bank_size;
+ #endif
+
+ /*
+diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c
+index 3302457..7f6d33a 100644
+--- a/drivers/pci_auto.c
++++ b/drivers/pci_auto.c
+@@ -296,10 +296,12 @@ int pciauto_config_device(struct pci_con
+
+ case PCI_CLASS_STORAGE_IDE:
+ pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
++#ifndef CONFIG_DHT_WALNUT
+ if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
+ DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
+ return sub_bus;
+ }
++#endif
+
+ pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
+ break;
+diff --git a/include/configs/walnut.h b/include/configs/walnut.h
+index 1171ee5..df9e8ac 100644
+--- a/include/configs/walnut.h
++++ b/include/configs/walnut.h
+@@ -37,6 +37,7 @@
+ #define CONFIG_4xx 1 /* ...member of PPC4xx family */
+ #define CONFIG_WALNUT 1 /* ...on a WALNUT board */
+ /* ...and on a SYCAMORE board */
++#define CONFIG_DHT_WALNUT 1 /* Just like a walnut, but .... */
+
+ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
+
+@@ -88,10 +89,36 @@
+ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+ #define CONFIG_MII 1 /* MII PHY management */
++#ifdef CONFIG_DHT_WALNUT
++#define CONFIG_ETHADDR de:ad:be:ef:00:00
++#define CONFIG_ENV_OVERWRITE 1
++#define CONFIG_PHY_ADDR 9 /* PHY address */
++#else
+ #define CONFIG_PHY_ADDR 1 /* PHY address */
++#endif
+
+ #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */
+
++#ifdef CONFIG_DHT_WALNUT
++#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
++ CFG_CMD_ASKENV | \
++ CFG_CMD_DATE | \
++ CFG_CMD_DHCP | \
++ CFG_CMD_DIAG | \
++ CFG_CMD_ELF | \
++ CFG_CMD_I2C | \
++ CFG_CMD_IRQ | \
++ CFG_CMD_MII | \
++ CFG_CMD_NET | \
++ CFG_CMD_NFS | \
++ CFG_CMD_PCI | \
++ CFG_CMD_PING | \
++ CFG_CMD_REGINFO | \
++ CFG_CMD_SDRAM | \
++ CFG_CMD_IDE | \
++ CFG_CMD_BEDBUG | \
++ CFG_CMD_SNTP )
++#else
+ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DATE | \
+@@ -108,6 +135,7 @@
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SDRAM | \
+ CFG_CMD_SNTP )
++#endif
+
+ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+ #include <cmd_confdefs.h>
+@@ -151,7 +179,7 @@
+ #define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+-#define CFG_LOAD_ADDR 0x100000 /* default load address */
++#define CFG_LOAD_ADDR 0x200000 /* default load address */
+ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
+
+ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+@@ -198,6 +226,50 @@
+ #define CFG_PCI_PTM2MS 0x00000000 /* disabled */
+ #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
+
++#ifdef CONFIG_DHT_WALNUT
++/***********************************************************************
++ * External peripheral base address
++ ***********************************************************************/
++#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
++
++/************************************************************
++ * IDE/ATA stuff
++ ************************************************************/
++#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */
++#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 per IDE bus */
++
++#define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */
++#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offset */
++#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
++#define CFG_ATA_REG_OFFSET 0 /* reg offset */
++#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
++
++#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
++#undef CONFIG_IDE_LED /* no led for ide supported */
++#undef CONFIG_IDE_RESET /* no reset for ide supported */
++
++#define CONFIG_LBA48 1
++#define CONFIG_MAC_PARTITION 1
++#define CONFIG_DOS_PARTITION 1
++#define CONFIG_ISO_PARTITION 1
++
++#define CONFIG_SUPPORT_VFAT
++
++/************************************************************
++ * ATAPI support (experimental)
++ ************************************************************/
++#define CONFIG_ATAPI /* enable ATAPI Support */
++
++/************************************************************
++ * SCSI support (experimental) only SYM53C8xx supported
++ ************************************************************/
++#define CONFIG_SCSI_SYM53C8XX
++#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
++#define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
++#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
++#define CFG_SCSI_SPIN_UP_TIME 2
++#endif
++
+ /*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
diff --git a/recipes/u-boot/u-boot-1.1.4/u-boot-flash-protect-fixup.patch b/recipes/u-boot/u-boot-1.1.4/u-boot-flash-protect-fixup.patch
new file mode 100644
index 0000000000..1bbbbcb32d
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/u-boot-flash-protect-fixup.patch
@@ -0,0 +1,11 @@
+--- a/drivers/cfi_flash.c
++++ a/drivers/cfi_flash.c
+@@ -345,7 +345,7 @@
+ #endif
+
+ /* Environment protection ON by default */
+-#ifdef CFG_ENV_IS_IN_FLASH
++#if defined(CFG_ENV_IS_IN_FLASH) && (CFG_MONITOR_BASE + CFG_MONITOR_LEN < CFG_ENV_ADDR)
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
diff --git a/recipes/u-boot/u-boot-1.1.4/u-boot-fw_printenv.patch b/recipes/u-boot/u-boot-1.1.4/u-boot-fw_printenv.patch
new file mode 100644
index 0000000000..5e33452d11
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/u-boot-fw_printenv.patch
@@ -0,0 +1,139 @@
+--- u-boot/tools/env/fw_env.c 2006-03-17 17:21:00.000000000 -0800
++++ u-boot/tools/env/fw_env.c 2006-03-17 17:53:41.000000000 -0800
+@@ -31,8 +31,9 @@
+ #include <sys/ioctl.h>
+ #include <sys/stat.h>
+ #include <unistd.h>
+-#include <linux/mtd/mtd.h>
++#include <mtd/mtd-user.h>
+ #include "fw_env.h"
++#include "config.h"
+
+ typedef unsigned char uchar;
+
+@@ -54,8 +55,6 @@
+ #define ENVSIZE(i) envdevices[(i)].env_size
+ #define DEVESIZE(i) envdevices[(i)].erase_size
+
+-#define CFG_ENV_SIZE ENVSIZE(curdev)
+-
+ #define ENV_SIZE getenvsize()
+
+ typedef struct environment_s {
+@@ -418,8 +417,8 @@
+ fdr = fd;
+ }
+ printf ("Unlocking flash...\n");
+- erase.length = DEVESIZE (otherdev);
+- erase.start = DEVOFFSET (otherdev);
++ erase.length = DEVESIZE (otherdev)*2;
++ erase.start = 0;
+ ioctl (fdr, MEMUNLOCK, &erase);
+
+ if (HaveRedundEnv) {
+@@ -439,7 +438,7 @@
+ strerror (errno));
+ return (-1);
+ }
+- if (lseek (fdr, DEVOFFSET (otherdev) + CFG_ENV_SIZE, SEEK_SET)
++ if (lseek (fdr, DEVESIZE(otherdev), SEEK_SET)
+ == -1) {
+ fprintf (stderr, "seek error on %s: %s\n",
+ DEVNAME (otherdev),
+@@ -458,7 +457,7 @@
+ printf ("Erasing old environment...\n");
+
+ erase.length = DEVESIZE (otherdev);
+- erase.start = DEVOFFSET (otherdev);
++ erase.start = DEVESIZE (otherdev);
+ if (ioctl (fdr, MEMERASE, &erase) != 0) {
+ fprintf (stderr, "MTD erase error on %s: %s\n",
+ DEVNAME (otherdev),
+@@ -469,6 +468,22 @@
+ printf ("Done\n");
+
+ printf ("Writing environment to %s...\n", DEVNAME (otherdev));
++ if (resid) {
++ if (lseek(fdr, DEVESIZE(otherdev), SEEK_SET)
++ == -1) {
++ fprintf(stderr, "seek error on %s: %s\n",
++ DEVNAME(otherdev),
++ strerror(errno));
++ return -1;
++ }
++ if (write (fdr, data, resid) != resid) {
++ fprintf (stderr,
++ "write error on %s: %s\n",
++ DEVNAME (curdev), strerror (errno));
++ return (-1);
++ }
++ free (data);
++ }
+ if (lseek (fdr, DEVOFFSET (otherdev), SEEK_SET) == -1) {
+ fprintf (stderr,
+ "seek error on %s: %s\n",
+@@ -487,15 +502,6 @@
+ DEVNAME (otherdev), strerror (errno));
+ return (-1);
+ }
+- if (resid) {
+- if (write (fdr, data, resid) != resid) {
+- fprintf (stderr,
+- "write error on %s: %s\n",
+- DEVNAME (curdev), strerror (errno));
+- return (-1);
+- }
+- free (data);
+- }
+ if (HaveRedundEnv) {
+ /* change flag on current active env partition */
+ if (lseek (fd, DEVOFFSET (curdev) + sizeof (ulong), SEEK_SET)
+@@ -514,8 +520,8 @@
+ }
+ printf ("Done\n");
+ printf ("Locking ...\n");
+- erase.length = DEVESIZE (otherdev);
+- erase.start = DEVOFFSET (otherdev);
++ erase.length = DEVESIZE (otherdev)*2;
++ erase.start = 0;
+ ioctl (fdr, MEMLOCK, &erase);
+ if (HaveRedundEnv) {
+ erase.length = DEVESIZE (curdev);
+--- u-boot/tools/env/fw_env.h 2006-03-17 17:16:37.000000000 -0800
++++ u-boot/tools/env/fw_env.h 2006-03-17 17:53:41.000000000 -0800
+@@ -27,25 +27,17 @@
+ * See included "fw_env.config" sample file (TRAB board)
+ * for notes on configuration.
+ */
+-#define CONFIG_FILE "/etc/fw_env.config"
++//#define CONFIG_FILE "/etc/fw_env.config"
+
+-#define HAVE_REDUND /* For systems with 2 env sectors */
+-#define DEVICE1_NAME "/dev/mtd1"
+-#define DEVICE2_NAME "/dev/mtd2"
+-#define DEVICE1_OFFSET 0x0000
+-#define ENV1_SIZE 0x4000
+-#define DEVICE1_ESIZE 0x4000
+-#define DEVICE2_OFFSET 0x0000
+-#define ENV2_SIZE 0x4000
+-#define DEVICE2_ESIZE 0x4000
+-
+-#define CONFIG_BAUDRATE 115200
+-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+-#define CONFIG_BOOTCOMMAND \
+- "bootp; " \
+- "setenv bootargs root=/dev/nfs nfsroot=${serverip}:${rootpath} " \
+- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+- "bootm"
++//#define HAVE_REDUND /* For systems with 2 env sectors */
++#define DEVICE1_NAME "/dev/mtd0"
++//#define DEVICE2_NAME "/dev/mtd2"
++#define DEVICE1_OFFSET CFG_ENV_ADDR
++#define ENV1_SIZE CFG_ENV_SIZE
++#define DEVICE1_ESIZE CFG_ENV_SECT_SIZE
++//#define DEVICE2_OFFSET 0x0000
++//#define ENV2_SIZE 0x4000
++//#define DEVICE2_ESIZE 0x4000
+
+ extern void fw_printenv(int argc, char *argv[]);
+ extern unsigned char *fw_getenv (unsigned char *name);
diff --git a/recipes/u-boot/u-boot-1.1.4/u-boot-install.patch b/recipes/u-boot/u-boot-1.1.4/u-boot-install.patch
new file mode 100644
index 0000000000..50c149c0a1
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/u-boot-install.patch
@@ -0,0 +1,102 @@
+--- u-boot-1.1.2/common/Makefile 2004-12-16 09:35:57.000000000 -0800
++++ u-boot-install/common/Makefile 2005-04-12 07:00:25.000000000 -0700
+@@ -34,7 +34,7 @@
+ cmd_date.o cmd_dcr.o cmd_diag.o cmd_doc.o cmd_dtt.o \
+ cmd_eeprom.o cmd_elf.o cmd_ext2.o \
+ cmd_fat.o cmd_fdc.o cmd_fdos.o cmd_flash.o cmd_fpga.o \
+- cmd_i2c.o cmd_ide.o cmd_immap.o cmd_itest.o cmd_jffs2.o \
++ cmd_i2c.o cmd_ide.o cmd_immap.o cmd_install.o cmd_itest.o cmd_jffs2.o \
+ cmd_load.o cmd_log.o \
+ cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
+ cmd_nand.o cmd_net.o cmd_nvedit.o \
+--- u-boot-1.1.2/common/cmd_install.c 1969-12-31 16:00:00.000000000 -0800
++++ u-boot-install/common/cmd_install.c 2005-04-12 07:43:10.000000000 -0700
+@@ -0,0 +1,70 @@
++/*
++ * (C) Copyright 2005
++ * Craig Hughes, Gumstix Inc. <craig@gumstix.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++/*
++ * Install command to copy compiled-in binary to flash
++ *
++ */
++
++#include <common.h>
++#include <command.h>
++#if (CONFIG_COMMANDS & CFG_CMD_INSTALL)
++
++#ifdef CONFIG_GUMSTIX_CPUSPEED_400
++#include <u-boot-400.h>
++#else
++#include <u-boot-200.h>
++#endif
++
++int do_install ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
++{
++ int rc;
++ size_t sect_top;
++
++ if (argc != 1) {
++ printf ("Usage:\n%s\n", cmdtp->usage);
++ return 1;
++ }
++
++ for(sect_top=0; sect_top<sizeof(u_boot_bin_data); sect_top+=PHYS_FLASH_SECT_SIZE) continue;
++ sect_top--;
++ flash_sect_protect(0, CFG_FLASH_BASE, sect_top);
++ flash_sect_erase(CFG_FLASH_BASE, sect_top);
++
++ puts ("Copying to Flash... ");
++
++ rc = flash_write ((uchar *)u_boot_bin_data, CFG_FLASH_BASE, sizeof(u_boot_bin_data));
++ if (rc != 0) {
++ flash_perror (rc);
++ return (1);
++ }
++ puts ("done\n");
++ return 0;
++}
++
++
++/**************************************************/
++U_BOOT_CMD(
++ install, 1, 1, do_install,
++ "install - install u-boot to flash\n",
++ "copies a u-boot image to begining of flash\n"
++);
++
++#endif /* CFG_CMD_INSTALL */
+--- u-boot-1.1.2/include/cmd_confdefs.h 2004-12-16 09:59:53.000000000 -0800
++++ u-boot-install/include/cmd_confdefs.h 2005-04-12 07:02:59.000000000 -0700
+@@ -94,6 +94,7 @@
+ #define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */
+ #define CFG_CMD_SNTP 0x2000000000000000ULL /* SNTP support */
+ #define CFG_CMD_DISPLAY 0x4000000000000000ULL /* Display support */
++#define CFG_CMD_INSTALL 0x2000000000000000ULL /* Install u-boot binary */
+
+ #define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFULL /* ALL commands */
+
+@@ -121,6 +121,7 @@
+ CFG_CMD_I2C | \
+ CFG_CMD_IDE | \
+ CFG_CMD_IMMAP | \
++ CFG_CMD_INSTALL | \
+ CFG_CMD_IRQ | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_KGDB | \
diff --git a/recipes/u-boot/u-boot-1.1.4/u-boot-jerase-cmd.patch b/recipes/u-boot/u-boot-1.1.4/u-boot-jerase-cmd.patch
new file mode 100644
index 0000000000..698f7a2d78
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/u-boot-jerase-cmd.patch
@@ -0,0 +1,107 @@
+--- u-boot-orig/common/cmd_flash.c 2004-12-31 01:32:50.000000000 -0800
++++ u-boot-1.1.2/common/cmd_flash.c 2005-09-13 23:00:14.000000000 -0700
+@@ -36,6 +36,11 @@
+
+ extern flash_info_t flash_info[]; /* info for FLASH chips */
+
++static const unsigned int JFFS2_CLEAN_HEADER[] = { 0x20031985,
++ 0x0000000c,
++ 0xe41eb0b1
++ };
++
+ /*
+ * The user interface starts numbering for Flash banks with 1
+ * for historical reasons.
+@@ -206,29 +211,46 @@
+ flash_print_info (&flash_info[bank-1]);
+ return 0;
+ }
+
++void jffs2_write_header(flash_info_t *info, unsigned int first, unsigned int last)
++{
++ unsigned int i;
++ for(i=first; i<=last; i++)
++ {
++ flash_write(JFFS2_CLEAN_HEADER, info->start[i], 12);
++ }
++}
++
+ int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ {
+ flash_info_t *info;
+ ulong bank, addr_first, addr_last;
+ int n, sect_first, sect_last;
+ #if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE)
+ struct mtd_device *dev;
+ struct part_info *part;
+ u8 dev_type, dev_num, pnum;
+ #endif
+ int rcode = 0;
++ int jffs2erase = 0;
+
+ if (argc < 2) {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
++ // Special JFFS2 erase which will write a JFFS2 "clean" header after the erase
++ if('j' == argv[0][0])
++ {
++ jffs2erase = 1;
++ }
++
+ if (strcmp(argv[1], "all") == 0) {
+ for (bank=1; bank<=CFG_MAX_FLASH_BANKS; ++bank) {
+ printf ("Erase Flash Bank # %ld ", bank);
+ info = &flash_info[bank-1];
+ rcode = flash_erase (info, 0, info->sector_count-1);
++ if(jffs2erase) jffs2_write_header(info, 0, info->sector_count-1);
+ }
+ return rcode;
+ }
+@@ -235,6 +257,7 @@
+ printf ("Erase Flash Sectors %d-%d in Bank # %d ",
+ sect_first, sect_last, (info-flash_info)+1);
+ rcode = flash_erase(info, sect_first, sect_last);
++ if(jffs2erase) jffs2_write_header(info, sect_first, sect_last);
+ return rcode;
+ }
+
+@@ -253,6 +276,7 @@
+ printf ("Erase Flash Bank # %ld ", bank);
+ info = &flash_info[bank-1];
+ rcode = flash_erase (info, 0, info->sector_count-1);
++ if(jffs2erase) jffs2_write_header(info, 0, info->sector_count-1);
+ return rcode;
+ }
+
+@@ -264,6 +288,12 @@
+ return 1;
+ }
+
++ if (jffs2erase)
++ {
++ printf ("Usage:\n%s\n", cmdtp->usage);
++ return 1;
++ }
++
+ rcode = flash_sect_erase(addr_first, addr_last);
+ return rcode;
+ }
+@@ -517,6 +547,16 @@
+ );
+
+ U_BOOT_CMD(
++ jerase, 3, 1, do_flerase,
++ "jerase - erase FLASH memory for JFFS2\n",
++ "jerase N:SF[-SL]\n - erase sectors SF-SL in FLASH bank # N\n"
++ "jerase bank N\n - erase FLASH bank # N\n"
++ "jerase all\n - erase all FLASH banks\n"
++ " in each case, after erasing a flash sector, that sector\n"
++ " has a JFFS2 'clean' marker written to it\n"
++);
++
++U_BOOT_CMD(
+ protect, 4, 1, do_protect,
+ "protect - enable or disable FLASH write protection\n",
+ "on start end\n"
diff --git a/recipes/u-boot/u-boot-1.1.4/u-boot-jffs2-new-nodetypes.patch b/recipes/u-boot/u-boot-1.1.4/u-boot-jffs2-new-nodetypes.patch
new file mode 100644
index 0000000000..cce41aca18
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/u-boot-jffs2-new-nodetypes.patch
@@ -0,0 +1,25 @@
+--- u-boot-1.1.4/fs/jffs2/jffs2_1pass.c-orig 2006-03-17 07:46:53.000000000 -0800
++++ u-boot-1.1.4/fs/jffs2/jffs2_1pass.c 2006-03-17 07:59:37.000000000 -0800
+@@ -1194,6 +1194,10 @@
+ printf("OOPS Padding has bad size "
+ "%d < %d\n", node->totlen,
+ sizeof(struct jffs2_unknown_node));
++ } else if (node->nodetype == JFFS2_NODETYPE_ERASEBLOCK_HEADER) {
++ // Could check offset here to ensure we're at start of erase block
++ } else if (node->nodetype == JFFS2_NODETYPE_SUMMARY) {
++ // Ignore summary blocks for now
+ } else {
+ printf("Unknown node type: %x len %d "
+ "offset 0x%x\n", node->nodetype,
+--- u-boot-1.1.4/include/jffs2/jffs2.h-orig 2006-03-17 08:20:01.000000000 -0800
++++ u-boot-1.1.4/include/jffs2/jffs2.h 2006-03-17 08:20:20.000000000 -0800
+@@ -90,6 +90,9 @@
+ #define JFFS2_NODETYPE_CLEANMARKER (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3)
+ #define JFFS2_NODETYPE_PADDING (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 4)
+
++#define JFFS2_NODETYPE_ERASEBLOCK_HEADER (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 5)
++#define JFFS2_NODETYPE_SUMMARY (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 6)
++
+ /* Maybe later... */
+ /*#define JFFS2_NODETYPE_CHECKPOINT (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3) */
+ /*#define JFFS2_NODETYPE_OPTIONS (JFFS2_FEATURE_RWCOMPAT_COPY | JFFS2_NODE_ACCURATE | 4) */
diff --git a/recipes/u-boot/u-boot-1.1.4/u-boot-loadb-safe.patch b/recipes/u-boot/u-boot-1.1.4/u-boot-loadb-safe.patch
new file mode 100644
index 0000000000..d4b8ef3935
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/u-boot-loadb-safe.patch
@@ -0,0 +1,16 @@
+diff -bBdurNP u-boot-1.1.1/common/cmd_load.c u-boot/common/cmd_load.c
+--- u-boot-1.1.1/common/cmd_load.c 2004-03-11 16:14:10.000000000 -0800
++++ u-boot/common/cmd_load.c 2004-09-30 00:19:43.656640004 -0700
+@@ -454,6 +454,12 @@
+ if (argc >= 2) {
+ offset = simple_strtoul(argv[1], NULL, 16);
+ }
++
++ if(offset < CFG_DRAM_BASE || offset > (CFG_DRAM_BASE+CFG_DRAM_SIZE)) {
++ printf("Cannot load to 0x%08lX -- address not in RAM\n",offset);
++ return 1;
++ }
++
+ if (argc == 3) {
+ load_baudrate = (int)simple_strtoul(argv[2], NULL, 10);
+
diff --git a/recipes/u-boot/u-boot-1.1.4/u-boot-make381-fix.patch b/recipes/u-boot/u-boot-1.1.4/u-boot-make381-fix.patch
new file mode 100644
index 0000000000..89555ac027
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/u-boot-make381-fix.patch
@@ -0,0 +1,15 @@
+--- /examples/orig-Makefile 2005-12-16 18:39:27.000000000 +0200
++++ /examples/Makefile 2006-12-02 14:58:59.000000000 +0200
+@@ -123,10 +123,10 @@
+ $(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \
+ -o $@ -e $(<:.o=) $< $(LIB) \
+ -L$(gcclibdir) -lgcc
+-%.srec: %
++%.srec: %.o
+ $(OBJCOPY) -O srec $< $@ 2>/dev/null
+
+-%.bin: %
++%.bin: %.o
+ $(OBJCOPY) -O binary $< $@ 2>/dev/null
+
+ #########################################################################
diff --git a/recipes/u-boot/u-boot-1.1.4/u-boot-mmc-init.patch b/recipes/u-boot/u-boot-1.1.4/u-boot-mmc-init.patch
new file mode 100644
index 0000000000..a18d4d3609
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/u-boot-mmc-init.patch
@@ -0,0 +1,24 @@
+--- a/cpu/pxa/mmc.c
++++ a/cpu/pxa/mmc.c
+@@ -401,16 +401,17 @@
+
+ /* reset */
+ retries = 10;
+- resp = mmc_cmd(0, 0, 0, 0);
+- resp = mmc_cmd(1, 0x00ff, 0xc000, MMC_CMDAT_INIT|MMC_CMDAT_BUSY|MMC_CMDAT_R3);
++ resp = mmc_cmd(0, 0, 0, MMC_CMDAT_INIT|MMC_CMDAT_BUSY|MMC_CMDAT_R1);
++ udelay(200000);
++ resp = mmc_cmd(1, 0x00ff, 0x8000, MMC_CMDAT_BUSY|MMC_CMDAT_R3);
+ while (retries-- && resp && !(resp[4] & 0x80)) {
+ debug("resp %x %x\n", resp[0], resp[1]);
+ #ifdef CONFIG_PXA27X
+ udelay(10000);
+ #else
+- udelay(50);
++ udelay(200000);
+ #endif
+- resp = mmc_cmd(1, 0x00ff, 0xff00, MMC_CMDAT_BUSY|MMC_CMDAT_R3);
++ resp = mmc_cmd(1, 0x00ff, 0x8000, MMC_CMDAT_BUSY|MMC_CMDAT_R3);
+ }
+
+ /* try to get card id */
diff --git a/recipes/u-boot/u-boot-1.1.4/u-boot-mmcclk-alternate.patch b/recipes/u-boot/u-boot-1.1.4/u-boot-mmcclk-alternate.patch
new file mode 100644
index 0000000000..5eb8324630
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/u-boot-mmcclk-alternate.patch
@@ -0,0 +1,14 @@
+--- a/cpu/pxa/mmc.c 2005-05-31 14:58:43.090949787 -0700
++++ a/cpu/pxa/mmc.c 2005-04-14 16:02:22.000000000 -0700
+@@ -546,9 +546,10 @@
+ int retries, rc = -ENODEV;
+ uchar *resp;
+
+-#ifdef CONFIG_LUBBOCK
++#if defined(CONFIG_LUBBOCK) || defined(CONFIG_GUMSTIX)
+ set_GPIO_mode( GPIO6_MMCCLK_MD );
+ set_GPIO_mode( GPIO8_MMCCS0_MD );
++ set_GPIO_mode( GPIO53_MMCCLK_MD );
+ #endif
+ CKEN |= CKEN12_MMC; /* enable MMC unit clock */
+ #if defined(CONFIG_ADSVIX)
diff --git a/recipes/u-boot/u-boot-1.1.4/u-boot-smc91x-multi.patch b/recipes/u-boot/u-boot-1.1.4/u-boot-smc91x-multi.patch
new file mode 100644
index 0000000000..3f285e34dc
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/u-boot-smc91x-multi.patch
@@ -0,0 +1,125 @@
+diff -u a/drivers/smc91111.c a/drivers/smc91111.c
+--- a/drivers/smc91111.c 2005-03-31 15:43:10.000000000 -0800
++++ a/drivers/smc91111.c 2005-04-13 13:48:41.000000000 -0700
+@@ -155,10 +155,14 @@
+ .
+ .------------------------------------------------------------------ */
+
++#ifndef CONFIG_NET_MULTI
+ extern int eth_init(bd_t *bd);
+ extern void eth_halt(void);
+ extern int eth_rx(void);
+ extern int eth_send(volatile void *packet, int length);
++#else
++extern int smc_initialize(bd_t *);
++#endif
+
+
+ /*
+@@ -797,6 +801,56 @@
+ }
+
+
++#ifdef CONFIG_NET_MULTI
++static int smc_multi_init(struct eth_device *, bd_t *);
++static void smc_multi_halt(struct eth_device *);
++static int smc_multi_send(struct eth_device *,volatile void *,int);
++static int smc_multi_recv(struct eth_device *);
++
++extern int smc_initialize(bd_t *bd)
++{
++ struct eth_device *dev;
++
++ dev = (struct eth_device *)malloc(sizeof(struct eth_device));
++ sprintf(dev->name, "SMC91C1111-%d",0);
++ dev->priv = NULL;
++ dev->iobase = SMC_BASE_ADDRESS;
++ dev->init = smc_multi_init;
++ dev->halt = smc_multi_halt;
++ dev->send = smc_multi_send;
++ dev->recv = smc_multi_recv;
++ eth_register(dev);
++
++ return 1; // number of cards detected
++}
++
++static int smc_multi_init(struct eth_device *dev, bd_t *bis)
++{
++ if(dev->priv == NULL)
++ {
++ smc_open(bis);
++ dev->priv = (void *)1;
++ }
++ return 1;
++}
++
++static void smc_multi_halt(struct eth_device *dev)
++{
++ // Not sure when we should actually close...
++ //smc_close();
++}
++
++static int smc_multi_send(struct eth_device *dev, volatile void *packet, int length)
++{
++ return smc_send_packet(packet, length);
++}
++
++static int smc_multi_recv(struct eth_device *dev)
++{
++ return smc_rcv();
++}
++#endif
++
+ /*
+ * Open and Initialize the board
+ *
+@@ -1505,6 +1559,7 @@
+ }
+ #endif
+
++#ifndef CONFIG_NET_MULTI
+ int eth_init(bd_t *bd) {
+ return (smc_open(bd));
+ }
+@@ -1520,6 +1575,7 @@
+ int eth_send(volatile void *packet, int length) {
+ return smc_send_packet(packet, length);
+ }
++#endif //CONFIG_NET_MULTI
+
+ int smc_get_ethaddr (bd_t * bd)
+ {
+--- a/lib_arm/board.c 2005-03-30 16:39:47.000000000 -0800
++++ a/lib_arm/board.c 2005-03-30 14:26:08.000000000 -0800
+@@ -278,6 +278,11 @@
+ /* initialize environment */
+ env_relocate ();
+
++#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
++ /* must do after the environment variables are set up */
++ eth_initialize (NULL);
++#endif
++
+ #ifdef CONFIG_VFD
+ /* must do this after the framebuffer is allocated */
+ drv_vfd_init();
+--- a/net/eth.c 2004-12-16 09:49:38.000000000 -0800
++++ a/net/eth.c 2005-03-30 17:06:49.000000000 -0800
+@@ -53,6 +53,7 @@
+ extern int scc_initialize(bd_t*);
+ extern int skge_initialize(bd_t*);
+ extern int tsec_initialize(bd_t*, int, char *);
++extern int smc_initialize(bd_t*);
+
+ static struct eth_device *eth_devices, *eth_current;
+
+@@ -196,6 +197,9 @@
+ #if defined(CONFIG_RTL8169)
+ rtl8169_initialize(bis);
+ #endif
++#if defined(CONFIG_DRIVER_SMC91111)
++ smc_initialize(bis);
++#endif
+
+ if (!eth_devices) {
+ puts ("No ethernet found.\n");
diff --git a/recipes/u-boot/u-boot-1.1.4/u-boot-zzz-osx.patch b/recipes/u-boot/u-boot-1.1.4/u-boot-zzz-osx.patch
new file mode 100644
index 0000000000..f9d52c7dfe
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.4/u-boot-zzz-osx.patch
@@ -0,0 +1,41 @@
+--- u-boot-1.1.1/tools/Makefile Mon Sep 27 03:34:12 2004
++++ u-boot-1.1.1/tools/Makefile Mon Sep 27 03:34:52 2004
+@@ -70,26 +70,26 @@
+ # multiple symbol definitions are treated as errors, hence the
+ # -multiply_defined suppress option to turn off this error.
+ #
+-ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc)
+-HOST_CFLAGS = -traditional-cpp -Wall
+-HOST_LDFLAGS =-multiply_defined suppress
+-HOST_ENVIRO_CFLAGS = -traditional-cpp
++#ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc)
++#HOST_CFLAGS = -traditional-cpp -Wall
++#HOST_LDFLAGS =-multiply_defined suppress
++#HOST_ENVIRO_CFLAGS = -traditional-cpp
+
+-else
+-ifeq ($(HOSTOS)-$(HOSTARCH),netbsd-ppc)
+-HOST_CFLAGS = -Wall -pedantic
+-HOST_LDFLAGS =
+-HOST_ENVIRO_CFLAGS =
++#else
++#ifeq ($(HOSTOS)-$(HOSTARCH),netbsd-ppc)
++#HOST_CFLAGS = -Wall -pedantic
++#HOST_LDFLAGS =
++#HOST_ENVIRO_CFLAGS =
+
+ #
+ # Everyone else
+ #
+-else
++#else
+ HOST_CFLAGS = -Wall -pedantic
+ HOST_LDFLAGS =
+ HOST_ENVIRO_CFLAGS =
+-endif
+-endif
++#endif
++#endif
+
+ #
+ # Cygwin needs .exe files :-(