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authorDenys Dmytriyenko <denis@denix.org>2009-03-17 14:32:59 -0400
committerDenys Dmytriyenko <denis@denix.org>2009-03-17 14:32:59 -0400
commit709c4d66e0b107ca606941b988bad717c0b45d9b (patch)
tree37ee08b1eb308f3b2b6426d5793545c38396b838 /recipes/u-boot/u-boot-1.1.2
parentfa6cd5a3b993f16c27de4ff82b42684516d433ba (diff)
rename packages/ to recipes/ per earlier agreement
See links below for more details: http://thread.gmane.org/gmane.comp.handhelds.openembedded/21326 http://thread.gmane.org/gmane.comp.handhelds.openembedded/21816 Signed-off-by: Denys Dmytriyenko <denis@denix.org> Acked-by: Mike Westerhof <mwester@dls.net> Acked-by: Philip Balister <philip@balister.org> Acked-by: Khem Raj <raj.khem@gmail.com> Acked-by: Marcin Juszkiewicz <hrw@openembedded.org> Acked-by: Koen Kooi <koen@openembedded.org> Acked-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
Diffstat (limited to 'recipes/u-boot/u-boot-1.1.2')
-rw-r--r--recipes/u-boot/u-boot-1.1.2/arm_flags.patch15
-rw-r--r--recipes/u-boot/u-boot-1.1.2/cmd-arm-linux.patch122
-rw-r--r--recipes/u-boot/u-boot-1.1.2/command-names.patch340
-rw-r--r--recipes/u-boot/u-boot-1.1.2/mnci-jffs2.patch16
-rw-r--r--recipes/u-boot/u-boot-1.1.2/mnci.patch1007
-rw-r--r--recipes/u-boot/u-boot-1.1.2/oxnas.patch7257
-rw-r--r--recipes/u-boot/u-boot-1.1.2/u-boot-1.1.2-neon.patch19155
-rw-r--r--recipes/u-boot/u-boot-1.1.2/u-boot-emetec.patch2170
8 files changed, 30082 insertions, 0 deletions
diff --git a/recipes/u-boot/u-boot-1.1.2/arm_flags.patch b/recipes/u-boot/u-boot-1.1.2/arm_flags.patch
new file mode 100644
index 0000000000..48c7b78043
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.2/arm_flags.patch
@@ -0,0 +1,15 @@
+
+#
+# Patch managed by http://www.holgerschurig.de/patcher.html
+#
+
+--- u-boot-1.1.2/cpu/pxa/config.mk~armflags
++++ u-boot-1.1.2/cpu/pxa/config.mk
+@@ -23,6 +23,6 @@
+ #
+
+ PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
+- -mshort-load-bytes -msoft-float
++ -msoft-float
+
+ PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100
diff --git a/recipes/u-boot/u-boot-1.1.2/cmd-arm-linux.patch b/recipes/u-boot/u-boot-1.1.2/cmd-arm-linux.patch
new file mode 100644
index 0000000000..e7ef37e061
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.2/cmd-arm-linux.patch
@@ -0,0 +1,122 @@
+
+#
+# Patch managed by http://www.holgerschurig.de/patcher.html
+#
+
+--- u-boot-1.1.2/include/cmd_confdefs.h~cmd-arm-linux
++++ u-boot-1.1.2/include/cmd_confdefs.h
+@@ -92,6 +92,7 @@
+ #define CFG_CMD_XIMG 0x0400000000000000ULL /* Load part of Multi Image */
+ #define CFG_CMD_UNIVERSE 0x0800000000000000ULL /* Tundra Universe Support */
+ #define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */
++#define CFG_CMD_LINUX 0x2000000000000000ULL /* boot zImage directly */
+
+ #define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFULL /* ALL commands */
+
+--- u-boot-1.1.2/lib_arm/armlinux.c~cmd-arm-linux
++++ u-boot-1.1.2/lib_arm/armlinux.c
+@@ -271,6 +271,104 @@
+ }
+
+
++#if (CONFIG_COMMANDS & CFG_CMD_LINUX)
++void do_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ ulong initrd_start = 0;
++ ulong initrd_end = 0;
++ ulong data;
++ void (*theKernel)(int zero, int arch, uint params);
++ bd_t *bd = gd->bd;
++
++
++#ifdef CONFIG_CMDLINE_TAG
++ char cmdline[128];
++ char *s;
++#endif
++
++#ifdef CONFIG_CMDLINE_TAG
++ if (argc > 1) {
++ ulong len;
++ int i;
++
++ for (i=1, len=0 ; i<argc ; i+=1) {
++ if (i > 1)
++ cmdline[len++] = ' ';
++ strcpy (&cmdline[len], argv[i]);
++ len += strlen(argv[i]);
++ }
++ } else
++ if ((s = getenv("bootargs")) != NULL) {
++ strcpy(cmdline, s);
++ } else {
++ strcpy(cmdline, "");
++ }
++#endif
++
++ theKernel = (void (*)(int, int, uint))load_addr;
++
++ SHOW_BOOT_PROGRESS (14);
++
++#ifdef DEBUG
++ printf ("## Transferring control to Linux (at address %08lx) ...\n",
++ (ulong)theKernel);
++#endif
++
++#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
++ defined (CONFIG_CMDLINE_TAG) || \
++ defined (CONFIG_INITRD_TAG) || \
++ defined (CONFIG_SERIAL_TAG) || \
++ defined (CONFIG_REVISION_TAG) || \
++ defined (CONFIG_LCD) || \
++ defined (CONFIG_VFD)
++ setup_start_tag(bd);
++#ifdef CONFIG_SERIAL_TAG
++ setup_serial_tag(&params);
++#endif
++#ifdef CONFIG_REVISION_TAG
++ setup_revision_tag(&params);
++#endif
++#ifdef CONFIG_SETUP_MEMORY_TAGS
++ setup_memory_tags(bd);
++#endif
++#ifdef CONFIG_CMDLINE_TAG
++ setup_commandline_tag(bd, cmdline);
++#endif
++#ifdef CONFIG_INITRD_TAG
++ setup_initrd_tag(bd, initrd_start, initrd_end);
++#endif
++#if defined (CONFIG_VFD) || defined (CONFIG_LCD)
++ setup_videolfb_tag ((gd_t *) gd);
++#endif
++ setup_end_tag(bd);
++#endif
++
++ /* we assume that the kernel is in place */
++ printf("\nStarting kernel ...\n");
++
++#ifdef CONFIG_USB_DEVICE
++ {
++ extern void udc_disconnect (void);
++ udc_disconnect ();
++ }
++#endif
++ cleanup_before_linux();
++
++ //TODO: CONFIG_TAG_ADDR is now bd->bi_boot_params ?
++ theKernel(0, bd->bi_arch_number, bd->bi_boot_params);
++}
++
++
++U_BOOT_CMD(
++ linux, CFG_MAXARGS, 0, do_linux,
++ "linux - boot Linux zImage directly\n",
++ "[arg ...]\n - boot Linux zImage, passing arguments 'arg ...'\n"
++);
++#endif
++
++
+ #if defined (CONFIG_SETUP_MEMORY_TAGS) || \
+ defined (CONFIG_CMDLINE_TAG) || \
+ defined (CONFIG_INITRD_TAG) || \
diff --git a/recipes/u-boot/u-boot-1.1.2/command-names.patch b/recipes/u-boot/u-boot-1.1.2/command-names.patch
new file mode 100644
index 0000000000..dd9a7fab44
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.2/command-names.patch
@@ -0,0 +1,340 @@
+
+#
+# Patch managed by http://www.holgerschurig.de/patcher.html
+#
+
+--- u-boot-1.1.2/common/cmd_mem.c~command-names
++++ u-boot-1.1.2/common/cmd_mem.c
+@@ -1188,56 +1188,56 @@
+ /**************************************************/
+ #if (CONFIG_COMMANDS & CFG_CMD_MEMORY)
+ U_BOOT_CMD(
+- md, 3, 1, do_mem_md,
+- "md - memory display\n",
++ memdump, 3, 1, do_mem_md,
++ "memdump - memory display\n",
+ "[.b, .w, .l] address [# of objects]\n - memory display\n"
+ );
+
+
+ U_BOOT_CMD(
+- mm, 2, 1, do_mem_mm,
+- "mm - memory modify (auto-incrementing)\n",
++ memmod, 2, 1, do_mem_mm,
++ "memmod - memory modify (auto-incrementing)\n",
+ "[.b, .w, .l] address\n" " - memory modify, auto increment address\n"
+ );
+
+
+ U_BOOT_CMD(
+- nm, 2, 1, do_mem_nm,
+- "nm - memory modify (constant address)\n",
++ memchg, 2, 1, do_mem_nm,
++ "memchg - memory modify (constant address)\n",
+ "[.b, .w, .l] address\n - memory modify, read and keep address\n"
+ );
+
+ U_BOOT_CMD(
+- mw, 4, 1, do_mem_mw,
+- "mw - memory write (fill)\n",
++ memfill, 4, 1, do_mem_mw,
++ "memfill - fill write\n",
+ "[.b, .w, .l] address value [count]\n - write memory\n"
+ );
+
+ U_BOOT_CMD(
+- cp, 4, 1, do_mem_cp,
+- "cp - memory copy\n",
++ memcp, 4, 1, do_mem_cp,
++ "memcp - copy memory\n",
+ "[.b, .w, .l] source target count\n - copy memory\n"
+ );
+
+ U_BOOT_CMD(
+- cmp, 4, 1, do_mem_cmp,
+- "cmp - memory compare\n",
++ memcmp, 4, 1, do_mem_cmp,
++ "memcmp - compary memory\n",
+ "[.b, .w, .l] addr1 addr2 count\n - compare memory\n"
+ );
+
+ #ifndef CONFIG_CRC32_VERIFY
+
+ U_BOOT_CMD(
+- crc32, 4, 1, do_mem_crc,
+- "crc32 - checksum calculation\n",
++ memcrc, 4, 1, do_mem_crc,
++ "memcrc - checksum memory\n",
+ "address count [addr]\n - compute CRC32 checksum [save at addr]\n"
+ );
+
+ #else /* CONFIG_CRC32_VERIFY */
+
+ U_BOOT_CMD(
+- crc32, 5, 1, do_mem_crc,
+- "crc32 - checksum calculation\n",
++ memcrc, 5, 1, do_mem_crc,
++ "memcrc - checksum memory\n",
+ "address count [addr]\n - compute CRC32 checksum [save at addr]\n"
+ "-v address count crc\n - verify crc of memory area\n"
+ );
+@@ -1245,31 +1245,31 @@
+ #endif /* CONFIG_CRC32_VERIFY */
+
+ U_BOOT_CMD(
+- base, 2, 1, do_mem_base,
+- "base - print or set address offset\n",
++ membase, 2, 1, do_mem_base,
++ "membase - print/set memory offset\n",
+ "\n - print address offset for memory commands\n"
+- "base off\n - set address offset for memory commands to 'off'\n"
++ "[offset]\n - set address offset for memory commands to 'offset'\n"
+ );
+
+ U_BOOT_CMD(
+- loop, 3, 1, do_mem_loop,
+- "loop - infinite loop on address range\n",
++ memloop, 3, 1, do_mem_loop,
++ "memloop - infinite loop on address range\n",
+ "[.b, .w, .l] address number_of_objects\n"
+ " - loop on a set of addresses\n"
+ );
+
+ #ifdef CONFIG_LOOPW
+ U_BOOT_CMD(
+- loopw, 4, 1, do_mem_loopw,
+- "loopw - infinite write loop on address range\n",
++ memloopw, 4, 1, do_mem_loopw,
++ "memloopw- infinite write loop on address range\n",
+ "[.b, .w, .l] address number_of_objects data_to_write\n"
+ " - loop on a set of addresses\n"
+ );
+ #endif /* CONFIG_LOOPW */
+
+ U_BOOT_CMD(
+- mtest, 4, 1, do_mem_mtest,
+- "mtest - simple RAM test\n",
++ memtest, 4, 1, do_mem_mtest,
++ "memtest - simple RAM test\n",
+ "[start [end [pattern]]]\n"
+ " - simple RAM read/write test\n"
+ );
+--- u-boot-1.1.2/common/cmd_flash.c~command-names
++++ u-boot-1.1.2/common/cmd_flash.c
+@@ -507,30 +507,30 @@
+ );
+
+ U_BOOT_CMD(
+- erase, 3, 1, do_flerase,
+- "erase - erase FLASH memory\n",
++ flerase, 3, 1, do_flerase,
++ "flerase - erase FLASH memory\n",
+ "start end\n"
+ " - erase FLASH from addr 'start' to addr 'end'\n"
+- "erase N:SF[-SL]\n - erase sectors SF-SL in FLASH bank # N\n"
+- "erase bank N\n - erase FLASH bank # N\n"
+- "erase all\n - erase all FLASH banks\n"
++ "flerase N:SF[-SL]\n - erase sectors SF-SL in FLASH bank # N\n"
++ "flerase bank N\n - erase FLASH bank # N\n"
++ "flerase all\n - erase all FLASH banks\n"
+ );
+
+ U_BOOT_CMD(
+- protect, 4, 1, do_protect,
+- "protect - enable or disable FLASH write protection\n",
++ flprot, 4, 1, do_protect,
++ "flprot - enable or disable FLASH write protection\n",
+ "on start end\n"
+ " - protect FLASH from addr 'start' to addr 'end'\n"
+- "protect on N:SF[-SL]\n"
++ "flprot on N:SF[-SL]\n"
+ " - protect sectors SF-SL in FLASH bank # N\n"
+- "protect on bank N\n - protect FLASH bank # N\n"
+- "protect on all\n - protect all FLASH banks\n"
+- "protect off start end\n"
++ "flprot on bank N\n - protect FLASH bank # N\n"
++ "flprot on all\n - protect all FLASH banks\n"
++ "flprot off start end\n"
+ " - make FLASH from addr 'start' to addr 'end' writable\n"
+- "protect off N:SF[-SL]\n"
++ "flprot off N:SF[-SL]\n"
+ " - make sectors SF-SL writable in FLASH bank # N\n"
+- "protect off bank N\n - make FLASH bank # N writable\n"
+- "protect off all\n - make all FLASH banks writable\n"
++ "flprot off bank N\n - make FLASH bank # N writable\n"
++ "flprot off all\n - make all FLASH banks writable\n"
+ );
+
+ #endif /* CFG_CMD_FLASH */
+--- u-boot-1.1.2/common/cmd_bootm.c~command-names
++++ u-boot-1.1.2/common/cmd_bootm.c
+@@ -446,8 +446,8 @@
+ }
+
+ U_BOOT_CMD(
+- bootm, CFG_MAXARGS, 1, do_bootm,
+- "bootm - boot application image from memory\n",
++ imgboot, CFG_MAXARGS, 1, do_bootm,
++ "imgboot - boot application image from memory\n",
+ "[addr [arg ...]]\n - boot application image stored in memory\n"
+ "\tpassing arguments 'arg ...'; when booting a Linux kernel,\n"
+ "\t'arg' can be the address of an initrd image\n"
+@@ -1056,8 +1056,8 @@
+ }
+
+ U_BOOT_CMD(
+- iminfo, CFG_MAXARGS, 1, do_iminfo,
+- "iminfo - print header information for application image\n",
++ imginfo, CFG_MAXARGS, 1, do_iminfo,
++ "imginfo - print header information for application image\n",
+ "addr [addr ...]\n"
+ " - print header information for application image starting at\n"
+ " address 'addr' in memory; this includes verification of the\n"
+@@ -1116,8 +1116,8 @@
+ }
+
+ U_BOOT_CMD(
+- imls, 1, 1, do_imls,
+- "imls - list all images found in flash\n",
++ imgls, 1, 1, do_imls,
++ "imgls - list all images found in flash\n",
+ "\n"
+ " - Prints information about all images found at sector\n"
+ " boundaries in flash.\n"
+--- u-boot-1.1.2/common/cmd_jffs2.c~command-names
++++ u-boot-1.1.2/common/cmd_jffs2.c
+@@ -259,8 +259,8 @@
+ }
+
+ U_BOOT_CMD(
+- chpart, 2, 0, do_jffs2_chpart,
+- "chpart\t- change active partition\n",
++ jffspart, 2, 0, do_jffs2_chpart,
++ "jffspart\t- change active partition\n",
+ " - change active partition\n"
+ );
+ #endif /* CFG_JFFS_SINGLE_PART */
+@@ -268,22 +268,22 @@
+ /***************************************************/
+
+ U_BOOT_CMD(
+- fsload, 3, 0, do_jffs2_fsload,
+- "fsload\t- load binary file from a filesystem image\n",
++ jffsload, 3, 0, do_jffs2_fsload,
++ "jffsload- load binary file from a filesystem image\n",
+ "[ off ] [ filename ]\n"
+ " - load binary file from flash bank\n"
+ " with offset 'off'\n"
+ );
+
+ U_BOOT_CMD(
+- fsinfo, 1, 1, do_jffs2_fsinfo,
+- "fsinfo\t- print information about filesystems\n",
++ jffsinfo, 1, 1, do_jffs2_fsinfo,
++ "jffsinfo- print information about filesystems\n",
+ " - print information about filesystems\n"
+ );
+
+ U_BOOT_CMD(
+- ls, 2, 1, do_jffs2_ls,
+- "ls\t- list files in a directory (default /)\n",
++ jffsls, 2, 1, do_jffs2_ls,
++ "jffsls\t- list files in a directory (default /)\n",
+ "[ directory ]\n"
+ " - list files in a directory.\n"
+ );
+--- u-boot-1.1.2/common/cmd_nvedit.c~command-names
++++ u-boot-1.1.2/common/cmd_nvedit.c
+@@ -570,19 +570,19 @@
+ /**************************************************/
+
+ U_BOOT_CMD(
+- printenv, CFG_MAXARGS, 1, do_printenv,
+- "printenv- print environment variables\n",
++ env, CFG_MAXARGS, 1, do_printenv,
++ "env - print environment variables\n",
+ "\n - print values of all environment variables\n"
+- "printenv name ...\n"
++ "env name ...\n"
+ " - print value of environment variable 'name'\n"
+ );
+
+ U_BOOT_CMD(
+- setenv, CFG_MAXARGS, 0, do_setenv,
+- "setenv - set environment variables\n",
++ envset, CFG_MAXARGS, 0, do_setenv,
++ "envset - set environment variables\n",
+ "name value ...\n"
+ " - set environment variable 'name' to 'value ...'\n"
+- "setenv name\n"
++ "envset name\n"
+ " - delete environment variable 'name'\n"
+ );
+
+@@ -590,8 +590,8 @@
+ ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == \
+ (CFG_CMD_ENV|CFG_CMD_FLASH))
+ U_BOOT_CMD(
+- saveenv, 1, 0, do_saveenv,
+- "saveenv - save environment variables to persistent storage\n",
++ envsave, 1, 0, do_saveenv,
++ "envsave - save environment variables to persistent storage\n",
+ NULL
+ );
+
+@@ -600,16 +600,16 @@
+ #if (CONFIG_COMMANDS & CFG_CMD_ASKENV)
+
+ U_BOOT_CMD(
+- askenv, CFG_MAXARGS, 1, do_askenv,
+- "askenv - get environment variables from stdin\n",
++ envask, CFG_MAXARGS, 1, do_askenv,
++ "envask - get environment variables from stdin\n",
+ "name [message] [size]\n"
+ " - get environment variable 'name' from stdin (max 'size' chars)\n"
+- "askenv name\n"
++ "envask name\n"
+ " - get environment variable 'name' from stdin\n"
+- "askenv name size\n"
++ "envask name size\n"
+ " - get environment variable 'name' from stdin (max 'size' chars)\n"
+- "askenv name [message] size\n"
+- " - display 'message' string and get environment variable 'name'"
++ "envask name [message] size\n"
++ " - display 'message' string and get environment variable 'name' "
+ "from stdin (max 'size' chars)\n"
+ );
+ #endif /* CFG_CMD_ASKENV */
+@@ -617,8 +617,8 @@
+ #if (CONFIG_COMMANDS & CFG_CMD_RUN)
+ int do_run (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+ U_BOOT_CMD(
+- run, CFG_MAXARGS, 1, do_run,
+- "run - run commands in an environment variable\n",
++ envrun, CFG_MAXARGS, 1, do_run,
++ "envrun - run commands in an environment variable\n",
+ "var [...]\n"
+ " - run the commands in the environment variable(s) 'var'\n"
+ );
+--- u-boot-1.1.2/common/cmd_cache.c~command-names
++++ u-boot-1.1.2/common/cmd_cache.c
+@@ -96,15 +96,15 @@
+
+
+ U_BOOT_CMD(
+- icache, 2, 1, do_icache,
+- "icache - enable or disable instruction cache\n",
++ cachei, 2, 1, do_icache,
++ "cachei - enable or disable instruction cache\n",
+ "[on, off]\n"
+ " - enable or disable instruction cache\n"
+ );
+
+ U_BOOT_CMD(
+- dcache, 2, 1, do_dcache,
+- "dcache - enable or disable data cache\n",
++ cached, 2, 1, do_dcache,
++ "cached - enable or disable data cache\n",
+ "[on, off]\n"
+ " - enable or disable data (writethrough) cache\n"
+ );
diff --git a/recipes/u-boot/u-boot-1.1.2/mnci-jffs2.patch b/recipes/u-boot/u-boot-1.1.2/mnci-jffs2.patch
new file mode 100644
index 0000000000..8b2571ad99
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.2/mnci-jffs2.patch
@@ -0,0 +1,16 @@
+
+#
+# Patch managed by http://www.holgerschurig.de/patcher.html
+#
+
+--- u-boot-1.1.2/common/cmd_jffs2.c~mnci-jffs2
++++ u-boot-1.1.2/common/cmd_jffs2.c
+@@ -43,7 +43,7 @@
+ extern int cramfs_ls (struct part_info *info, char *filename);
+ extern int cramfs_info (struct part_info *info);
+
+-static int part_num=0;
++static int part_num=3;
+
+ #ifndef CFG_JFFS_CUSTOM_PART
+
diff --git a/recipes/u-boot/u-boot-1.1.2/mnci.patch b/recipes/u-boot/u-boot-1.1.2/mnci.patch
new file mode 100644
index 0000000000..d69cf8eb72
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.2/mnci.patch
@@ -0,0 +1,1007 @@
+
+#
+# Patch managed by http://www.holgerschurig.de/patcher.html
+#
+
+--- u-boot-1.1.2/CREDITS~mnci
++++ u-boot-1.1.2/CREDITS
+@@ -360,6 +360,9 @@
+ E: r.schwebel@pengutronix.de
+ D: Support for csb226, logodl and innokom boards (PXA2xx)
+
++N: Holger Schurig
++D: Support for MNCI-RX "Ramses"
++
+ N: Yasushi Shoji
+ E: yashi@atmark-techno.com
+ D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board
+--- u-boot-1.1.2/MAINTAINERS~mnci
++++ u-boot-1.1.2/MAINTAINERS
+@@ -396,6 +396,10 @@
+ csb226 xscale
+ innokom xscale
+
++Holger Schurig
++
++ mnci xscale
++
+ Andrea Scian <andrea.scian@dave-tech.it>
+
+ B2 ARM7TDMI (S3C44B0X)
+--- u-boot-1.1.2/Makefile~mnci
++++ u-boot-1.1.2/Makefile
+@@ -1388,6 +1388,9 @@
+ wepep250_config : unconfig
+ @./mkconfig $(@:_config=) arm pxa wepep250
+
++mnci_config : unconfig
++ @./mkconfig $(@:_config=) arm pxa mnci
++
+ xaeniax_config : unconfig
+ @./mkconfig $(@:_config=) arm pxa xaeniax
+
+--- /dev/null
++++ u-boot-1.1.2/board/mnci/Makefile
+@@ -0,0 +1,49 @@
++#
++# (C) Copyright 2000
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++# (C) Copyright 2005
++# M&N Solutions GmbH, Rosbach, Germany, Holger Schurig
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = lib$(BOARD).a
++
++OBJS := mnci.o
++SOBJS := memsetup.o
++
++$(LIB): $(OBJS) $(SOBJS)
++ $(AR) crv $@ $(OBJS) $(SOBJS)
++
++clean:
++ rm -f $(SOBJS) $(OBJS
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
++
++-include .depend
++
++#########################################################################
+--- /dev/null
++++ u-boot-1.1.2/board/mnci/config.mk
+@@ -0,0 +1 @@
++TEXT_BASE = 0xa1fe0000
+--- /dev/null
++++ u-boot-1.1.2/board/mnci/u-boot.lds
+@@ -0,0 +1,55 @@
++/*
++ * (C) Copyright 2000
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++ . = 0x00000000;
++
++ . = ALIGN(4);
++ .text :
++ {
++ cpu/pxa/start.o (.text)
++ *(.text)
++ }
++
++ . = ALIGN(4);
++ .rodata : { *(.rodata) }
++
++ . = ALIGN(4);
++ .data : { *(.data) }
++
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
+--- /dev/null
++++ u-boot-1.1.2/board/mnci/mnci.c
+@@ -0,0 +1,174 @@
++/*
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/arch/pxa-regs.h>
++#include <asm/mach-types.h>
++
++/**
++ * board_init: - setup some data structures
++ *
++ * @return: 0 in case of success
++ */
++
++int board_init (void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ /* memory and cpu-speed are setup before relocation */
++ /* so we do _nothing_ here */
++
++ gd->bd->bi_arch_number = MACH_TYPE_RAMSES;
++ gd->bd->bi_boot_params = 0xa0000100;
++#if 0
++ gd->bd->bi_baudrate = 115200;
++#endif
++
++#if 0
++ CKEN |= CKEN2_AC97;
++ GCR = GCR_COLD_RST;
++#endif
++
++ return 0;
++}
++
++
++int board_late_init(void)
++{
++ setenv("stdout", "serial");
++ setenv("stderr", "serial");
++ return 0;
++}
++
++
++/**
++ * dram_init: - setup dynamic RAM
++ *
++ * @return: 0 in case of success
++ */
++
++int dram_init (void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++
++ return 0;
++}
++
++
++
++#ifdef CFG_JFFS_CUSTOM_PART
++
++#include <jffs2/jffs2.h>
++
++#define FLASH_DEBUG 1
++
++/* Some debug macros */
++#if (FLASH_DEBUG > 2 )
++#define PRINTK3(args...) printf(args)
++#else
++#define PRINTK3(args...)
++#endif
++
++#if FLASH_DEBUG > 1
++#define PRINTK2(args...) printf(args)
++#else
++#define PRINTK2(args...)
++#endif
++
++#ifdef FLASH_DEBUG
++#define PRINTK(args...) printf(args)
++#else
++#define PRINTK(args...)
++#endif
++
++
++#define FLASH_BANK_SIZE 0x02000000 /* 32 MB (during development) */
++#define MAIN_SECT_SIZE 0x00040000 /* 256k per sector */
++
++#ifndef CFG_FLASH_CFI
++flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
++#endif
++
++static struct part_info part;
++static int current_part = -1;
++
++struct part_info* jffs2_part_info(int part_num) {
++ void *jffs2_priv_saved = part.jffs2_priv;
++
++ PRINTK2("jffs2_part_info: part_num=%i\n",part_num);
++
++ if (current_part == part_num)
++ return &part;
++
++ /* u-boot partition */
++ if(part_num==0){
++ memset(&part, 0, sizeof(part));
++
++ part.offset=(char*)0x00000000;
++ part.size=0x00040000;
++
++ /* Mark the struct as ready */
++ current_part = part_num;
++
++ PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
++ PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
++ }
++
++ /* primary Kernel partition */
++ if(part_num==1){
++ memset(&part, 0, sizeof(part));
++
++ part.offset=(char*)0x00040000;
++ part.size=0x00040000*4;
++
++ /* Mark the struct as ready */
++ current_part = part_num;
++
++ PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
++ PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
++ }
++
++ /* data partition */
++ if(part_num==3){
++ memset(&part, 0, sizeof(part));
++
++ part.offset=(char*)0x00140000;
++ part.size=FLASH_BANK_SIZE-0x00140000;
++
++ /* Mark the struct as ready */
++ current_part = part_num;
++
++ PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset);
++ PRINTK("part.size = 0x%08x\n",(unsigned int)part.size);
++ }
++
++ if (current_part == part_num) {
++ part.usr_priv = &current_part;
++ part.jffs2_priv = jffs2_priv_saved;
++ return &part;
++ }
++
++ PRINTK("jffs2_part_info: end of partition table\n");
++ return 0;
++}
++#endif
+--- /dev/null
++++ u-boot-1.1.2/include/configs/mnci.h
+@@ -0,0 +1,309 @@
++/*
++ * (C) Copyright 2005
++ * Holger Schurig, M&N Solutions GmbH, Rosbach, Germany
++ *
++ * Configuration for the Auerswald Innokom CPU board.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#include <asm/arch/pxa-regs.h>
++
++/*
++ * If we are developing, we might want to start armboot from ram
++ * so we MUST NOT initialize critical regs like mem-timing ...
++ */
++#define CONFIG_INIT_CRITICAL /* undef for developing */
++
++/*
++ * define the following to enable debug blinks. A debug blink function
++ * must be defined in memsetup.S
++ */
++#undef DEBUG_BLINK_ENABLE
++#undef DEBUG_BLINKC_ENABLE
++
++/*
++ * High Level Configuration Options
++ * (easy to change)
++ */
++#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
++
++#undef CONFIG_LCD
++#ifdef CONFIG_LCD
++#define CONFIG_SHARP_LM8V31
++#endif
++
++#define CONFIG_MMC 1
++#define BOARD_LATE_INIT 1
++
++#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
++
++/*
++ * Size of malloc() pool
++ */
++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
++
++/*
++ * MNCI memory map information
++ */
++
++#define MNCI_CS5_ETH_OFFSET 0x03400000
++
++
++/*
++ * Hardware drivers
++ */
++#if 0
++#define CONFIG_DRIVER_SMC91111
++#define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + MNCI_CS5_ETH_OFFSET + 0x300)
++#define CONFIG_SMC_USE_32_BIT 1
++//#define CONFIG_SMC_USE_IOFUNCS
++#endif
++
++/* the following has to be set high -- suspect something is wrong with
++ * with the tftp timeout routines. FIXME!!!
++ */
++#define CONFIG_NET_RETRY_COUNT 100
++
++/*
++ * select serial console configuration
++ */
++#define CONFIG_FFUART 1 /* we use FFUART on MNCI */
++
++/* allow to overwrite serial and ethaddr */
++//#define CONFIG_ENV_OVERWRITE
++
++#define CONFIG_BAUDRATE 115200
++
++#define CONFIG_COMMANDS ( 0 \
++ | CFG_CMD_ENV \
++ | CFG_CMD_FLASH \
++ | CFG_CMD_LINUX \
++ | CFG_CMD_JFFS2 \
++ | CFG_CMD_LOADB \
++ | CFG_CMD_MEMORY \
++ | CFG_CMD_MISC \
++ | CFG_CMD_RUN \
++ )
++
++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
++#include <cmd_confdefs.h>
++
++#define CONFIG_BOOTDELAY 0
++#define CONFIG_BOOTCOMMAND "linux"
++#define CONFIG_BOOTARGS "console=ttyS0,115200 rootfstype=jffs2 root=/dev/mtdblock2"
++//#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfsroot ip=192.168.233.14:192.168.233.1:192.168.233.1:255.255.255.0:ramses2:eth0:off"
++#define CONFIG_CMDLINE_TAG 1
++#define CONFIG_SETUP_MEMORY_TAGS 1
++#define CFG_CONSOLE_INFO_QUIET 1
++#define CFG_JFFS_SINGLE_PART 1
++
++/*
++ * Current memory map for MNCI supplied Linux images:
++ *
++ * Flash:
++ * 0x00000 - 0x003ffff: bootloader
++ * 0x040000 - 0x013ffff: kernel
++ * 0x140000 - 0x1ffffff: file system
++ *
++ * RAM:
++ * 0xa0008000 - kernel is loaded
++ * 0xa1fe0000 - Uboot runs (48MB into RAM)
++ *
++ */
++
++#define MY_CONFIG_EXTRA_ENV_SETTINGS \
++ "prog_boot_mmc=" \
++ "mw.b 0xa0000000 0xff 0x40000; " \
++ "if mmcinit && " \
++ "fatload mmc 0 0xa0000000 u-boot.bin; " \
++ "then " \
++ "protect off 0x0 0x3ffff; " \
++ "erase 0x0 0x3ffff; " \
++ "cp.b 0xa0000000 0x0 0x40000; " \
++ "reset;" \
++ "fi\0" \
++ "prog_uImage_mmc=" \
++ "mw.b 0xa0000000 0xff 0x1C0000; " \
++ "if mmcinit && " \
++ "fatload mmc 0 0xa0000000 uImage; " \
++ "then " \
++ "protect off 0x40000 0x13ffff; " \
++ "erase 0x40000 0x13ffff; " \
++ "cp.b 0xa0000000 0x40000 0x1C0000; " \
++ "fi\0" \
++ "prog_jffs_mmc=" \
++ "mw.b 0xa0000000 0xff 0x1e00000; " \
++ "if mmcinit && " \
++ "fatload mmc 0 0xa0000000 root.jffs; " \
++ "then " \
++ "protect off 0x200000 0x13fffff; " \
++ "erase 0x200000 0x13fffff; " \
++ "cp.b 0xa0000000 0x200000 0x1e00000; " \
++ "fi\0" \
++ "boot_mmc=" \
++ "if mmcinit && " \
++ "fatload mmc 0 0xa1000000 uImage && " \
++ "then " \
++ "bootm 0xa1000000; " \
++ "fi\0" \
++ "prog_boot_net=" \
++ "mw.b 0xa0000000 0xff 0x100000; " \
++ "if bootp 0xa0000000 u-boot.bin; " \
++ "then " \
++ "protect off 0x0 0x3ffff; " \
++ "erase 0x0 0x3ffff; " \
++ "cp.b 0xa0000000 0x0 0x40000; " \
++ "reset; " \
++ "fi\0" \
++ "prog_uImage_net=" \
++ "mw.b 0xa0000000 0xff 0x1C0000; " \
++ "if bootp 0xa0000000 uImage; " \
++ "then " \
++ "protect off 0x40000 0x13ffff; " \
++ "erase 0x40000 0x13ffff; " \
++ "cp.b 0xa0000000 0x40000 0x1C0000; " \
++ "fi\0" \
++ "boot_uImage_net=" \
++ "mw.b 0xa0000000 0xff 0x1C0000; " \
++ "if bootp 0xa0000000 uImage; " \
++ "then " \
++ "bootm 0xa0000000; " \
++ "fi\0" \
++ "prog_jffs_net=" \
++ "mw.b 0xa0000000 0xff 0x1e00000; " \
++ "if bootp 0xa0000000 root.jffs; " \
++ "then " \
++ "protect off 0x200000 0x13fffff; " \
++ "erase 0x200000 0x13fffff; " \
++ "cp.b 0xa0000000 0x200000 0x1e00000; " \
++ "fi\0"
++
++#define CONFIG_EXTRA_ENV_SETTINGS \
++ "bootargsnfs=console=ttyS0,115200 root=/dev/nfsroot ip=192.168.233.14:192.168.233.1:192.168.233.1:255.255.255.0:ramses2:eth0:off;\0" \
++ "boot_nfs=" \
++ "set bootargs $bootargsnfs; " \
++ "linux\0"
++
++
++#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
++#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
++#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
++#endif
++
++/*
++ * Miscellaneous configurable options
++ */
++//#define CFG_HUSH_PARSER 1
++//#define CFG_PROMPT_HUSH_PS2 "> "
++
++#define CFG_LONGHELP /* undef to save memory */
++#define CFG_PROMPT "mnci> " /* Monitor Command Prompt */
++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
++#define CFG_MAXARGS 16 /* max number of command args */
++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
++#define CFG_DEVICE_NULLDEV 1
++
++#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
++#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
++
++#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
++
++#define CFG_LOAD_ADDR 0x40000 /* default load address */
++
++#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
++#define CFG_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */
++
++//#define RTC 1 /* enable 32KHz osc */
++
++ /* valid baudrates */
++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
++
++#define CFG_MMC_BASE 0xF0000000
++
++/*
++ * Stack sizes
++ *
++ * The stack sizes are set up in start.S using the settings below
++ */
++#define CONFIG_STACKSIZE (256*1024) /* regular stack */
++#ifdef CONFIG_USE_IRQ
++#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
++#endif
++
++
++/*
++ * Environment
++ */
++#define CFG_MONITOR_BASE 0
++#define CFG_MONITOR_LEN 0x40000
++
++#define CFG_ENV_IS_IN_FLASH 1
++#define CFG_ENV_ADDR 0x20000
++#define CFG_ENV_SIZE 0x4000
++#define CFG_ENV_SECT_SIZE 0x40000
++
++/*
++ * Physical Memory Map
++ */
++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */
++#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
++#define PHYS_SDRAM_1_SIZE 0x08000000 /* 64 MB */
++
++#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
++#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */
++#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
++//#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
++//#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
++
++#define CFG_DRAM_BASE PHYS_SDRAM_1
++#define CFG_DRAM_SIZE PHYS_SDRAM_1_SIZE
++
++#define CFG_FLASH_BASE PHYS_FLASH_1
++
++
++/*
++ * JFFS2 Partitions
++ */
++#define CFG_JFFS_CUSTOM_PART 1 /* see board/innokom/flash.c */
++
++
++/*
++ * FLASH organization
++ */
++#define CFG_FLASH_CFI
++#define CFG_FLASH_CFI_DRIVER 1
++
++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
++#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
++
++#define CFG_FLASH_USE_BUFFER_WRITE 1
++
++/* timeout values are in ticks */
++#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
++#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
++
++
++#endif /* __CONFIG_H */
+--- /dev/null
++++ u-boot-1.1.2/board/mnci/memsetup.S
+@@ -0,0 +1,359 @@
++/*
++ * Memory & peripheral setup of the XScale PXA250
++ *
++ * Written October 2002 by H.Schurig for M&N Logistik-Lösungen Online GmbH
++ * http://www.mn-logistik.de/unsupported/pxa250/
++ *
++ * Number in Parentheses like (3-29) refer to pages in the
++ *
++ * Intel PXA250 and PXA210
++ * Application Processor
++ * Developer's Manual
++ * February 2002
++ *
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <config.h>
++#include <version.h>
++#include <asm/arch/pxa-regs.h>
++
++
++/**********************************************************************
++ *
++ * reginit
++ *
++ * PURPOSE: initialize stuff using a addr/data pair table
++ * PARAMS: r0 - address the the table
++ * REGISTERS: r0, r1, r2, r3
++ * CALLS: Nothing
++ * RETURNS: Nothing
++ **********************************************************************/
++reginit:
++1: ldmia r0!, {r1,r2} @ load reg/value from regtable
++ cmp r1, #0 @ at end?
++ strne r2, [r1] @ if not, store value into reg
++ ldrne r3, [r1] @ if not, read it back (see PXA errata)
++ bne 1b @ if not, branch back
++ mov pc, lr
++
++
++/**********************************************************************
++ *
++ * memsetup
++ *
++ * PURPOSE:
++ * PARAMS:
++ * REGISTERS:
++ * CALLS:
++ * RETURNS: Nothing
++ **********************************************************************/
++
++.globl memsetup
++memsetup:
++ mov r11, lr
++
++ adr r0, SystemUnitTable
++ bl reginit
++
++ @ Steps 2a..4d
++ adr r0,MemTable1
++ bl reginit
++
++ @ Step 4e wait 200 usec
++ ldr r0, oscr_addr
++ ldr r1, [r0]
++ add r1,r1,#0x300 @ Current OSCR+0x300
++1:
++ ldr r2, [r0]
++ cmp r1, r2
++ bgt 1b
++
++ @ TODO: data cache must be off, see Developers Manual, Section 6.12,
++ @ page 6-77, point 6.
++
++ @ Step 4f attempt read access to trigger a number of refresh cycles
++ ldr r2, =CFG_DRAM_BASE
++.rept 8
++ str r2, [r2]
++.endr
++
++ @ TODO: re-enable data cache
++
++ @ Steps 4g..4h
++ adr r0,MemTable2
++ bl reginit
++ @ Done with memory setup
++
++
++ @ Check if we return from Sleep Mode via RCSR (3-33)
++ ldr r0, rcsr_addr
++ ldr r1, [r0]
++ and r1,r1,#0xf @ mask RCSR_HWR|RCSR_WDR|RCSR_SMR|RCSR_GPR
++ str r1, [r0] @ clear Reset Controll State Register
++ teq r1, #4 @ RCSR_SMR (Sleep Mode)
++ beq WakeUp
++
++ @ Issue Frequency Change Sequence
++freqchange:
++ mov r0, #3
++ mcr p14, 0, r0, c6, c0, 0
++ mov pc, r11
++
++WakeUp:
++ @ retrieve the scratchpad value and jump to that address
++ ldr r0, pspr_addr
++ ldr pc, [r0]
++
++
++@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
++@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
++@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
++
++
++SystemUnitTable:
++ @ (4-22) Mask all interrupts
++ .long ICMR, 0x00000000 @ PM
++ @ (4-22) Interrupts are IRQs, not FIQs
++ .long ICLR, 0x00000000
++ @ (4-23) Only enabled and unmasked interrupts bring the CPU out of idle mode
++ .long ICCR, 0x00000001
++ @ (4-41) Clear OS Timer Match bits
++ .long OSSR, 0x0000000f @ NO PM
++ @ (3-34) Set clock register (we change CP14,6 at the end of this function)
++ .long CCCR, 0x00000161 @ NO PM, 121 is slow, 241 is medium, 161 is fast
++ @ (3-38) Enable 32 kHz Oszillator
++ .long OSCC, 0x00000002
++
++ @ (3-36) Enable needed clocks
++ .long CKEN, 0x00000043 @ PM: FFUART, PWM0, PWM1
++
++ .long 0x17c00004,8 @ CPLD: PER_PWR_EN
++
++// Bit GPIO Level Function Direct Altern Function
++// --------------------------------------------------
++// 00000001 0 1 nc Input 0 normal GPIO
++// 00000002 1 1 nPFI Input 0 normal GPIO
++// 00000004 2 1 BAT_DATA Input 0 normal GPIO
++// 00000008 3 1 IRQ_KEY Input 0 normal GPIO
++// 00000010 4 0 IRQ_ETH Input 0 normal GPIO
++// 00000020 5 1 nc Input 0 normal GPIO
++// 00000040 6 0 MMC_CLK Output 1 MMC_CLK
++// 00000080 7 1 IRQ_GSM Input 0 normal GPIO
++// 00000100 8 1 nPCC_S1_CD Input 0 normal GPIO
++// 00000200 9 1 nMMC_CD Input 0 normal GPIO
++// 00000400 10 1 IRQ_RTC Input 0 normal GPIO
++// 00000800 11 0 nc 3M6 Output 1 3.6 MHz
++// 00001000 12 1 nc Input 0 normal GPIO
++// 00002000 13 1 IRQ_DOCK Input 0 normal GPIO
++// 00004000 14 1 nc Input 0 normal GPIO
++// 00008000 15 1 nc nCS1 Output 2 nCS1
++
++// 00010000 16 1 PWM0 Output 2 PWM0
++// 00020000 17 1 PWM1 Output 2 PWM1
++// 00040000 18 1 RDY Input 1 RDY
++// 00080000 19 1 nPCC_S0_IRQ Input 0 normal GPIO
++// 00100000 20 1 nc Input 0 normal GPIO
++// 00200000 21 1 AC97_IRQ Input 0 normal GPIO
++// 00400000 22 1 nPCC_S1_IRQ Input 0 normal GPIO
++// 00800000 23 1 nc IRQ_GSM Input 0 normal GPIO
++// 01000000 24 0 UART_INTB Input 0 normal GPIO
++// 02000000 25 0 UART_INTC Input 0 normal GPIO
++// 04000000 26 1 UART_INTD Input 0 normal GPIO
++// 08000000 27 0 nc cpldfree Input 0 normal GPIO
++// 10000000 28 1 AUD_BITCLK Input 1 97_BITCLK
++// 20000000 29 0 AUD_SDIN0 Input 1 97_SDATAIN0
++// 40000000 30 0 AUD_SDOUT Output 2 97_SDATAOUT
++// 80000000 31 0 AUD_SYNC Output 2 97_SYNC
++
++ .long GPSR0, 0x00008000 @ set nCS1
++ .long GPDR0, 0xd0038840 @ out MMC_CLK, 3M6, nCS1, PWM0, PWM1
++ .long GAFR0_L,0x80401000 @ MMC_CLK:1, 3M6:1, nCS1:2
++ .long GAFR0_U,0xA500001a @ PWM0:2, PWM1:2, RDY:1
++ @ 97_BITCLK:1, 97_SDATAIN0:1, 97_SDATAOUT:2, 97_SYNC:2
++ .long PGSR0, 0x00028000 @ sleep set: nCS1, PWM1
++ .long GRER0, 0x00000000 @ rising edge detect: none
++ .long GFER0, 0x00000000 @ falling edge detect: none
++
++
++// 00000001 32 0 USB_INT Input 0 normal GPIO
++// 00000002 33 1 nCS5 Output 2 nCS5
++// 00000004 34 1 FF_RXD Input 1 FF_RXD
++// 00000008 35 1 FF_CTS Input 1 FF_CTS
++// 00000010 36 1 FF_DCD Input 1 FF_DCD
++// 00000020 37 1 FF_DSR Input 1 FF_DSR
++// 00000040 38 1 FF_RI Input 1 FF_RI
++// 00000080 39 0 FF_TXD Output 2 FF_TXD
++// 00000100 40 0 FF_DTR Output 2 FF_DTR
++// 00000200 41 0 FF_RTS Output 2 FF_RTS
++// 00000400 42 1 BT_RXD Input 1 BT_RXD
++// 00000800 43 1 BT_TXD Output 2 BT_TXD
++// 00001000 44 0 BT_CTS Input 1 BT_CTS
++// 00002000 45 1 BT_RTS Output 2 BT_RTS
++// 00004000 46 1 IR_RXD Input 1 ICP_RXD
++// 00008000 47 0 IR_TXD Output 2 ICP_TXD
++// 00010000 48 1 nPOE Output 2 nPOE
++// 00020000 49 1 nPWE Output 2 nPWE
++// 00040000 50 1 nPIOR Output 2 nPIOR
++// 00080000 51 1 nPIOW Output 2 nPIOW
++// 00100000 52 1 nPCE1 Output 2 nPCE1
++// 00200000 53 1 nPCE2 Output 2 nPCE2
++// 00400000 54 0 nPKTSEL Output 2 nPKTSEL
++// 00800000 55 1 nPREG Output 2 nPREG
++// 01000000 56 1 nPWAIT Input 1 nPWAIT
++// 02000000 57 1 nIOIS16 Input 1 nIOI16
++// 04000000 58 0 LDD0 Output 2 LDD0
++// 08000000 59 1 LDD1 Output 2 LDD1
++// 10000000 60 0 LDD2 Output 2 LDD2
++// 20000000 61 1 LDD3 Output 2 LDD3
++// 40000000 62 0 LDD4 Output 2 LDD4
++// 80000000 63 0 LDD5 Output 2 LDD5
++
++ .long GPSR1, 0x00020302 @ set nCS5, FF_RTS, FF_DTR, nPWE
++ .long GPCR1, 0x00000080 @ clear FF_TXD
++ .long GPDR1, 0xfcffab82 @ out: nCS5, FF_TXD, FF_DTR, FF_RTS, BT_TXD,
++ @ BT_RTS, IR_TXD, nPOE...nPREG, LDD0..LDD5
++ .long GAFR1_L,0x999a9558 @
++ .long GAFR1_U,0xaaa5aaaa @
++ .long PGSR1, 0x00020002 @ sleep set: nCS5, nPWE
++ .long GRER1, 0x00000000 @
++ .long GFER1, 0x00000000 @
++
++
++
++// 00000001 64 0 LDD6 Output 2 LDD6
++// 00000002 65 1 LDD7 Output 2 LDD7
++// 00000004 66 1 LDD8 Output 2 LDD8
++// 00000008 67 0 LDD9 Output 2 LDD9
++// 00000010 68 1 LDD10 Output 2 LDD10
++// 00000020 69 0 LDD11 Output 2 LDD11
++// 00000040 70 0 LDD12 Output 2 LDD12
++// 00000080 71 1 LDD13 Output 2 LDD13
++// 00000100 72 0 LDD14 Output 2 LDD14
++// 00000200 73 0 LDD15 Output 2 LDD15
++// 00000400 74 1 FCLK Output 2 FCLK
++// 00000800 75 1 LCLK Output 2 LCLK
++// 00001000 76 1 PCLK Output 2 PCLK
++// 00002000 77 0 BIAS Output 2 ACBIAS
++// 00004000 78 1 nCS2 Output 2 nCS2
++// 00008000 79 1 nCS3 Output 2 nCS3
++// 00010000 80 1 nCS4 Output 2 nCS4
++// 00020000 81 1 nc Input 0 normal GPIO
++// 00040000 82 1 nc Input 0 normal GPIO
++// 00080000 83 1 nc Input 0 normal GPIO
++// 00100000 84 1 nc Input 0 normal GPIO
++
++ .long GPSR2, 0x0001c000 @ set nCS2..4
++ .long GPDR2, 0x0001FFFF @ out: LDD6..nCS4
++ .long GAFR2_L,0xaaaaaaaa @
++ .long GAFR2_U,0x00000002 @
++ .long PGSR2, 0x0001c000 @ sleep set: nCS2..4
++ .long GRER2, 0x00000000 @
++ .long GFER2, 0x00000000 @
++
++ @ (3-25) Power Wakeup Registers
++ .long PWER, 0x00000008 @ wake up on IRQ_KEY
++ .long PRER, 0x00000008 @ detect rising edge on IRQ_KEY
++ .long PFER, 0x00000000 @ dont detect falling edges
++
++ @ (3-28) Power Manager Edge Detect Status Register
++ .long PEDR, 0x00000008 @ clear edge detect status for IRQ_KEY
++
++ @ (3-29) Sleep State Register
++ .long PSSR, 0x00000030 @ clear PH and RDH
++
++ .long PWM_CTRL0, 0
++ .long PWM_CTRL0, 0
++ .long PWM_PERVAL0, 512
++ .long PWM_PERVAL1, 512
++ .long PWM_PWDUTY0, 440
++ .long PWM_PWDUTY1, 450
++
++ @ End
++ .long 0,0
++
++
++
++
++MemTable1:
++ @ Info on this sequence is in the OS Developers Guide, Section 10.0 on page 13
++ @ also see Developers Manual, Section 6.12 on page 6-76
++
++ @ write MSC0, MSC1, MSC2 (6-44)
++ .long MSC0, 0x7ff0fdc3 @ f4c0
++ .long MSC1, 0x29842981
++ .long MSC2, 0x29842984
++
++ @ no synchronous static stuff here
++ .long SXCNFG, 0x00000000 @ (6-31)
++
++ @ write MECR (6-60), MCMEMx (6-57), MCATTx (6-58), MCIOx (6-58)
++ .long MECR, 0x00000003
++ .long MCMEM0, 0x00020418
++ .long MCMEM1, 0x00020418
++ .long MCATT0, 0x0002449D
++ .long MCATT1, 0x0002449D
++ .long MCIO0, 0x00014290
++ .long MCIO1, 0x00014290
++
++ @ write FLYCNFG (that register is now undocumented)
++
++ @ OS Developers Manual: write MDREFR (6-15), K0RUN and K0PIN are
++ @ set for synchronous static memory. The desired value of
++ @ K0DB2 can be programmed. KxFREE can be deasserted. APD must
++ @ remain deasserted and SLFRSH must remain asserted.
++ @ Developers Manual: write K0RUN and E0PIN. Configure K0DB2. Retain
++ @ the current values of APD and SLFRSH. DRI must contain a
++ @ valid value. Deassert KxFREE.
++ .long MDREFR, 0x00400016 @ 2d KxFREE & APD deasserted, SLFRSH asserted
++
++ @ Developers Manual: in systems containing Synchronous Static Memory, write
++ @ to SXCNFG, including the enable bits.
++ @.long SXCNFG, 0x00000000 @ no Synchronous Static Memory
++
++ @ Assert K1RUN and K2RUN and configure K1DB2 and K2DB2
++ .long MDREFR, 0x00450016 @ 4a
++ .long MDREFR, 0x00050016 @ 4b deassert SLFRFH
++ .long MDREFR, 0x00058016 @ 4c assert E1PIN
++ .long MDCNFG, 0x0A000AC8 @ 4d without DE0/DE1 (6-10)
++ .long 0,0
++
++oscr_addr:
++ .long OSCR
++rcsr_addr:
++ .long RCSR
++pspr_addr:
++ .long PSPR
++
++
++@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
++
++
++MemTable2:
++ .long MDCNFG, 0x0A000ACB @ 4d with DE0/DE1
++ .long MDMRS, 0x00000000 @ 4h
++ .long MDREFR, 0x00118016 @ 5 (optional) turn APD on
++ .long 0x17C0002C, 0x00000011 @ MNCI: enable FFUART driver
++ .long 0x17c00034, 0x00000000 @ MNCI: enable flash write
++ .long 0x17c00028, 0x00000000 @ MNCI: turn off CF-Card enable
++ .long 0x17c00014, 0x00000000 @ MNCI: turn off CF-Card power
++ .long 0x10000000, 0x0000d803 @ MNCI: disable all LEDs, SCANNER_WAKE & SCANNER_TRIG on
++@ .long 0x10000000, 0x0000d80b @ MNCI: disable all LEDs, SCANNER_WAKE, SCANNER_TRIG & UARTB on
++ .long 0,0
diff --git a/recipes/u-boot/u-boot-1.1.2/oxnas.patch b/recipes/u-boot/u-boot-1.1.2/oxnas.patch
new file mode 100644
index 0000000000..f1fff14822
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.2/oxnas.patch
@@ -0,0 +1,7257 @@
+diff -Nurd u-boot-1.1.2/board/oxnas/config.mk u-boot-1.1.2-oxe810/board/oxnas/config.mk
+--- u-boot-1.1.2/board/oxnas/config.mk 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-oxe810/board/oxnas/config.mk 2008-06-11 17:55:18.000000000 +0200
+@@ -0,0 +1,26 @@
++TEXT_BASE = 0x48d00000
++CROSS_COMPILE = arm-linux-
++
++PLL400 ?= 733333333
++RPSCLK ?= 25000000
++
++NAS_VERSION ?= 810
++FPGA ?= 0
++FPGA_ARM_CLK ?= 25000000
++
++PROBE_MEM_SIZE ?= 1
++MEM_SIZE ?= 64 # Memory size in megabytes if probing is not enabled
++MEM_ODT ?= 150
++
++USE_SATA ?= 1
++USE_SATA_ENV ?= 1
++USE_FLASH ?= 1
++
++LINUX_ROOT_RAIDED ?= 1
++
++USE_EXTERNAL_UART ?= 0
++INTERNAL_UART ?= 2
++
++TEST_BRD ?= 0 # Only significant for OX800
++
++PLATFORM_CPPFLAGS += -DLINUX_ROOT_RAIDED=$(LINUX_ROOT_RAIDED) -DMEM_ODT=$(MEM_ODT) -DPROBE_MEM_SIZE=$(PROBE_MEM_SIZE) -DNAS_VERSION=$(NAS_VERSION) -DFPGA=$(FPGA) -DFPGA_ARM_CLK=$(FPGA_ARM_CLK) -DINTERNAL_UART=$(INTERNAL_UART) -DUSE_EXTERNAL_UART=$(USE_EXTERNAL_UART) -DMEM_SIZE=$(MEM_SIZE) -DPLL400=$(PLL400) -DRPSCLK=$(RPSCLK) -DTEST_BRD=$(TEST_BRD) -DUSE_SATA=$(USE_SATA) -DUSE_SATA_ENV=$(USE_SATA_ENV) -DUSE_FLASH=$(USE_FLASH)
+diff -Nurd u-boot-1.1.2/board/oxnas/eth.c u-boot-1.1.2-oxe810/board/oxnas/eth.c
+--- u-boot-1.1.2/board/oxnas/eth.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-oxe810/board/oxnas/eth.c 2008-06-11 17:55:18.000000000 +0200
+@@ -0,0 +1,1666 @@
++/*
++ * (C) Copyright 2005
++ * Oxford Semiconductor Ltd
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <malloc.h>
++#include <net.h>
++#include <asm/barrier.h>
++
++//#define DEBUG_GMAC_INIT
++
++// The number of bytes wasted at the start of a received packet buffer in order
++// to ensure the IP header will be aligned to a 32-bit boundary
++static const int ETHER_FRAME_ALIGN_WASTAGE = 2;
++static const int EXTRA_RX_SKB_SPACE = 32; // Otherwise GMAC spans over >1 skb
++static const int ETHER_MTU = 1500;
++
++static const u32 MAC_BASE_OFFSET = 0x0000;
++static const u32 DMA_BASE_OFFSET = 0x1000;
++
++static const int NUM_TX_DMA_DESCRIPTORS = 1;
++static const int NUM_RX_DMA_DESCRIPTORS = 32;
++
++/* Generic MII registers. */
++#define MII_BMCR 0x00 /* Basic mode control register */
++#define MII_BMSR 0x01 /* Basic mode status register */
++#define MII_PHYSID1 0x02 /* PHYS ID 1 */
++#define MII_PHYSID2 0x03 /* PHYS ID 2 */
++#define MII_ADVERTISE 0x04 /* Advertisement control reg */
++#define MII_LPA 0x05 /* Link partner ability reg */
++#define MII_EXPANSION 0x06 /* Expansion register */
++#define MII_CTRL1000 0x09 /* 1000BASE-T control */
++#define MII_STAT1000 0x0a /* 1000BASE-T status */
++#define MII_ESTATUS 0x0f /* Extended Status */
++
++/* Basic mode control register. */
++#define BMCR_RESV 0x003f /* Unused... */
++#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
++#define BMCR_CTST 0x0080 /* Collision test */
++#define BMCR_FULLDPLX 0x0100 /* Full duplex */
++#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
++#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
++#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
++#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
++#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
++#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
++#define BMCR_RESET 0x8000 /* Reset the DP83840 */
++
++/* Basic mode status register. */
++#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
++#define BMSR_JCD 0x0002 /* Jabber detected */
++#define BMSR_LSTATUS 0x0004 /* Link status */
++#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
++#define BMSR_RFAULT 0x0010 /* Remote fault detected */
++#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
++#define BMSR_RESV 0x00c0 /* Unused... */
++#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
++#define BMSR_100FULL2 0x0200 /* Can do 100BASE-T2 HDX */
++#define BMSR_100HALF2 0x0400 /* Can do 100BASE-T2 FDX */
++#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
++#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
++#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
++#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
++#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
++
++/* 1000BASE-T Status register */
++#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
++#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
++#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
++#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
++#define PHY_TYPE_NONE 0
++#define PHY_TYPE_MICREL_KS8721BL 0x00221619
++#define PHY_TYPE_VITESSE_VSC8201XVZ 0x000fc413
++#define PHY_TYPE_REALTEK_RTL8211BGR 0x001cc912
++#define PHY_TYPE_LSI_ET1011C 0x0282f013
++
++/* Specific PHY values */
++#define VSC8201_MII_ACSR 0x1c // Vitesse VCS8201 gigabit PHY Auxillary Control and Status register
++#define VSC8201_MII_ACSR_MDPPS_BIT 2 // Mode/Duplex Pin Priority Select
++
++#define ET1011C_MII_CONFIG 0x16
++#define ET1011C_MII_CONFIG_IFMODESEL 0
++#define ET1011C_MII_CONFIG_IFMODESEL_NUM_BITS 3
++#define ET1011C_MII_CONFIG_SYSCLKEN 4
++#define ET1011C_MII_CONFIG_TXCLKEN 5
++#define ET1011C_MII_CONFIG_TBI_RATESEL 8
++#define ET1011C_MII_CONFIG_CRS_TX_EN 15
++
++#define ET1011C_MII_CONFIG_IFMODESEL_GMII_MII 0
++#define ET1011C_MII_CONFIG_IFMODESEL_TBI 1
++#define ET1011C_MII_CONFIG_IFMODESEL_GMII_MII_GTX 2
++
++#define ET1011C_MII_LED2 0x1c
++#define ET1011C_MII_LED2_LED_TXRX 12
++#define ET1011C_MII_LED2_LED_NUM_BITS 4
++
++#define ET1011C_MII_LED2_LED_TXRX_ON 0xe
++#define ET1011C_MII_LED2_LED_TXRX_ACTIVITY 0x7
++
++// Some typedefs to cope with std Linux types
++typedef void sk_buff_t;
++
++// The in-memory descriptor structures
++typedef struct gmac_dma_desc
++{
++ /** The encoded status field of the GMAC descriptor */
++ u32 status;
++ /** The encoded length field of GMAC descriptor */
++ u32 length;
++ /** Buffer 1 pointer field of GMAC descriptor */
++ u32 buffer1;
++ /** Buffer 2 pointer or next descriptor pointer field of GMAC descriptor */
++ u32 buffer2;
++ /** Not used for U-Boot */
++ u32 skb;
++} __attribute ((packed)) gmac_dma_desc_t;
++
++typedef struct gmac_desc_list_info
++{
++ gmac_dma_desc_t* base_ptr;
++ int num_descriptors;
++ int empty_count;
++ int full_count;
++ int r_index;
++ int w_index;
++} gmac_desc_list_info_t;
++
++// Private data structure for the GMAC driver
++typedef struct gmac_priv
++{
++ /** Base address of GMAC MAC registers */
++ u32 macBase;
++ /** Base address of GMAC DMA registers */
++ u32 dmaBase;
++
++ /** The number of descriptors in the gmac_dma_desc_t array holding both the
++ * TX and RX descriptors. The TX descriptors reside at the start of the
++ * array */
++ unsigned total_num_descriptors;
++
++ /** The address of the start of the descriptor array */
++ gmac_dma_desc_t *desc_base_addr;
++
++ /** Descriptor list management */
++ gmac_desc_list_info_t tx_gmac_desc_list_info;
++ gmac_desc_list_info_t rx_gmac_desc_list_info;
++
++ /** PHY info */
++ u32 phy_type;
++ u32 phy_addr;
++ int phy_id;
++ int link_is_1000M;
++} gmac_priv_t;
++
++/**
++ * MAC register indices
++ */
++typedef enum gmac_mac_regs {
++ MAC_CONFIG_REG = 0,
++ MAC_FRAME_FILTER_REG = 1,
++ MAC_HASH_HIGH_REG = 2,
++ MAC_HASH_LOW_REG = 3,
++ MAC_GMII_ADR_REG = 4,
++ MAC_GMII_DATA_REG = 5,
++ MAC_FLOW_CNTL_REG = 6,
++ MAC_VLAN_TAG_REG = 7,
++ MAC_VERSION_REG = 8,
++ MAC_ADR0_HIGH_REG = 16,
++ MAC_ADR0_LOW_REG = 17,
++ MAC_ADR1_HIGH_REG = 18,
++ MAC_ADR1_LOW_REG = 19,
++ MAC_ADR2_HIGH_REG = 20,
++ MAC_ADR2_LOW_REG = 21,
++ MAC_ADR3_HIGH_REG = 22,
++ MAC_ADR3_LOW_REG = 23,
++ MAC_ADR4_HIGH_REG = 24,
++ MAC_ADR4_LOW_REG = 25,
++ MAC_ADR5_HIGH_REG = 26,
++ MAC_ADR5_LOW_REG = 27,
++ MAC_ADR6_HIGH_REG = 28,
++ MAC_ADR6_LOW_REG = 29,
++ MAC_ADR7_HIGH_REG = 30,
++ MAC_ADR7_LOW_REG = 31,
++ MAC_ADR8_HIGH_REG = 32,
++ MAC_ADR8_LOW_REG = 33,
++ MAC_ADR9_HIGH_REG = 34,
++ MAC_ADR9_LOW_REG = 35,
++ MAC_ADR10_HIGH_REG = 36,
++ MAC_ADR10_LOW_REG = 37,
++ MAC_ADR11_HIGH_REG = 38,
++ MAC_ADR11_LOW_REG = 39,
++ MAC_ADR12_HIGH_REG = 40,
++ MAC_ADR12_LOW_REG = 41,
++ MAC_ADR13_HIGH_REG = 42,
++ MAC_ADR13_LOW_REG = 43,
++ MAC_ADR14_HIGH_REG = 44,
++ MAC_ADR14_LOW_REG = 45,
++ MAC_ADR15_HIGH_REG = 46,
++ MAC_ADR15_LOW_REG = 47
++} gmac_mac_regs_t;
++
++
++/**
++ * MAC register field definitions
++ */
++typedef enum gmac_config_reg {
++ MAC_CONFIG_WD_BIT = 23,
++ MAC_CONFIG_JD_BIT = 22,
++ MAC_CONFIG_BE_BIT = 21,
++ MAC_CONFIG_JE_BIT = 20,
++ MAC_CONFIG_IFG_BIT = 17,
++ MAC_CONFIG_PS_BIT = 15,
++ MAC_CONFIG_DO_BIT = 13,
++ MAC_CONFIG_LM_BIT = 12,
++ MAC_CONFIG_DM_BIT = 11,
++ MAC_CONFIG_IPC_BIT = 10,
++ MAC_CONFIG_DR_BIT = 9,
++ MAC_CONFIG_ACS_BIT = 7,
++ MAC_CONFIG_BL_BIT = 5,
++ MAC_CONFIG_DC_BIT = 4,
++ MAC_CONFIG_TE_BIT = 3,
++ MAC_CONFIG_RE_BIT = 2
++} gmac_config_reg_t;
++
++#define MAC_CONFIG_IFG_NUM_BITS 3
++#define MAC_CONFIG_BL_NUM_BITS 2
++
++typedef enum gmac_frame_filter_reg {
++ MAC_FRAME_FILTER_RA_BIT = 31,
++ MAC_FRAME_FILTER_SAF_BIT = 9,
++ MAC_FRAME_FILTER_SAIF_BIT = 8,
++ MAC_FRAME_FILTER_PCF_BIT = 6,
++ MAC_FRAME_FILTER_DBF_BIT = 5,
++ MAC_FRAME_FILTER_PM_BIT = 4,
++ MAC_FRAME_FILTER_DAIF_BIT = 3,
++ MAC_FRAME_FILTER_HMC_BIT = 2,
++ MAC_FRAME_FILTER_HUC_BIT = 1,
++ MAC_FRAME_FILTER_PR_BIT = 0
++} gmac_frame_filter_reg_t;
++
++#define MAC_FRAME_FILTER_PCF_NUM_BITS 2
++
++typedef enum gmac_hash_table_high_reg {
++ MAC_HASH_HIGH_HTH_BIT = 0
++} gmac_hash_table_high_reg_t;
++
++typedef enum gmac_hash_table_low_reg {
++ MAC_HASH_LOW_HTL_BIT = 0
++} gmac_hash_table_low_reg_t;
++
++typedef enum gmac_gmii_address_reg {
++ MAC_GMII_ADR_PA_BIT = 11,
++ MAC_GMII_ADR_GR_BIT = 6,
++ MAC_GMII_ADR_CR_BIT = 2,
++ MAC_GMII_ADR_GW_BIT = 1,
++ MAC_GMII_ADR_GB_BIT = 0
++} gmac_gmii_address_reg_t;
++
++#define MAC_GMII_ADR_PA_NUM_BITS 5
++#define MAC_GMII_ADR_GR_NUM_BITS 5
++#define MAC_GMII_ADR_CR_NUM_BITS 3
++
++typedef enum gmac_gmii_data_reg {
++ MAC_GMII_DATA_GD_BIT = 0
++} gmac_gmii_data_reg_t;
++
++#define MAC_GMII_DATA_GD_NUM_BITS 16
++
++typedef enum gmac_flow_control_reg {
++ MAC_FLOW_CNTL_PT_BIT = 16,
++ MAC_FLOW_CNTL_PLT_BIT = 4,
++ MAC_FLOW_CNTL_UP_BIT = 3,
++ MAC_FLOW_CNTL_RFE_BIT = 2,
++ MAC_FLOW_CNTL_TFE_BIT = 1,
++ MAC_FLOW_CNTL_FCB_BPA_BIT = 0
++} gmac_flow_control_reg_t;
++
++#define MAC_FLOW_CNTL_PT_NUM_BITS 16
++#define MAC_FLOW_CNTL_PLT_NUM_BITS 2
++
++typedef enum gmac_vlan_tag_reg {
++ MAC_VLAN_TAG_LV_BIT = 0
++} gmac_vlan_tag_reg_t;
++
++#define MAC_VLAN_TAG_LV_NUM_BITS 16
++
++typedef enum gmac_version_reg {
++ MAC_VERSION_UD_BIT = 8,
++ MAC_VERSION_SD_BIT = 0
++} gmac_version_reg_t;
++
++#define MAC_VERSION_UD_NUM_BITS 8
++#define MAC_VERSION_SD_NUM_BITS 8
++
++typedef enum gmac_mac_adr_0_high_reg {
++ MAC_ADR0_HIGH_MO_BIT = 31,
++ MAC_ADR0_HIGH_A_BIT = 0
++} gmac_mac_adr_0_high_reg_t;
++
++#define MAC_ADR0_HIGH_A_NUM_BITS 16
++
++typedef enum gmac_mac_adr_0_low_reg {
++ MAC_ADR0_LOW_A_BIT = 0
++} gmac_mac_adr_0_low_reg_t;
++
++typedef enum gmac_mac_adr_1_high_reg {
++ MAC_ADR1_HIGH_AE_BIT = 31,
++ MAC_ADR1_HIGH_SA_BIT = 30,
++ MAC_ADR1_HIGH_MBC_BIT = 24,
++ MAC_ADR1_HIGH_A_BIT = 0
++} gmac_mac_adr_1_high_reg_t;
++
++#define MAC_ADR1_HIGH_MBC_NUM_BITS 6
++#define MAC_ADR1_HIGH_A_NUM_BITS 16
++
++typedef enum gmac_mac_adr_1_low_reg {
++ MAC_ADR1_LOW_A_BIT = 0
++} gmac_mac_adr_1_low_reg_t;
++
++
++/**
++ * MMC register indices - registers accessed via the MAC accessor functions
++ */
++typedef enum gmac_mmc_regs {
++ MMC_CONTROL_REG = 64,
++ MMC_RX_INT_REG = 65,
++ MMC_TX_INT_REG = 66,
++ MMC_RX_MASK_REG = 67,
++ MMC_TX_MASK_REG = 68
++} gmac_mmc_regs_t;
++
++/**
++ * DMA register indices
++ */
++typedef enum gmac_dma_regs {
++ DMA_BUS_MODE_REG = 0,
++ DMA_TX_POLL_REG = 1,
++ DMA_RX_POLL_REG = 2,
++ DMA_RX_DESC_ADR_REG = 3,
++ DMA_TX_DESC_ADR_REG = 4,
++ DMA_STATUS_REG = 5,
++ DMA_OP_MODE_REG = 6,
++ DMA_INT_ENABLE_REG = 7,
++ DMA_MISSED_OVERFLOW_REG = 8,
++ DMA_CUR_TX_DESC_REG = 18,
++ DMA_CUR_RX_DESC_REG = 19,
++ DMA_CUR_TX_ADR_REG = 20,
++ DMA_CUR_RX_ADR_REG = 21
++} gmac_dma_regs_t;
++
++/**
++ * DMA register field definitions
++ */
++
++typedef enum gmac_dma_bus_mode_reg {
++ DMA_BUS_MODE_FB_BIT = 16,
++ DMA_BUS_MODE_PR_BIT = 14,
++ DMA_BUS_MODE_PBL_BIT = 8,
++ DMA_BUS_MODE_DSL_BIT = 2,
++ DMA_BUS_MODE_DA_BIT = 1,
++ DMA_BUS_MODE_SWR_BIT = 0
++} gmac_dma_bus_mode_reg_t;
++
++#define DMA_BUS_MODE_PR_NUM_BITS 2
++#define DMA_BUS_MODE_PBL_NUM_BITS 6
++#define DMA_BUS_MODE_DSL_NUM_BITS 5
++
++typedef enum gmac_dma_tx_poll_demand_reg {
++ DMA_TX_POLL_TPD_BIT = 0
++} gmac_dma_tx_poll_demand_reg_t;
++
++typedef enum gmac_dma_rx_poll_demand_reg {
++ DMA_RX_POLL_RPD_BIT = 0
++} gmac_dma_rx_poll_demand_reg_t;
++
++typedef enum gmac_dma_rx_desc_list_adr_reg {
++ DMA_RX_DESC_ADR_SRL_BIT = 0
++} gmac_dma_rx_desc_list_adr_reg_t;
++
++typedef enum gmac_dma_tx_desc_list_adr_reg {
++ DMA_TX_DESC_ADR_STL_BIT = 0
++} gmac_dma_tx_desc_list_adr_reg_t;
++
++typedef enum gmac_dma_status_reg {
++ DMA_STATUS_GPI_BIT = 28,
++ DMA_STATUS_GMI_BIT = 27,
++ DMA_STATUS_GLI_BIT = 26,
++ DMA_STATUS_EB_BIT = 23,
++ DMA_STATUS_TS_BIT = 20,
++ DMA_STATUS_RS_BIT = 17,
++ DMA_STATUS_NIS_BIT = 16,
++ DMA_STATUS_AIS_BIT = 15,
++ DMA_STATUS_ERI_BIT = 14,
++ DMA_STATUS_FBE_BIT = 13,
++ DMA_STATUS_ETI_BIT = 10,
++ DMA_STATUS_RWT_BIT = 9,
++ DMA_STATUS_RPS_BIT = 8,
++ DMA_STATUS_RU_BIT = 7,
++ DMA_STATUS_RI_BIT = 6,
++ DMA_STATUS_UNF_BIT = 5,
++ DMA_STATUS_OVF_BIT = 4,
++ DMA_STATUS_TJT_BIT = 3,
++ DMA_STATUS_TU_BIT = 2,
++ DMA_STATUS_TPS_BIT = 1,
++ DMA_STATUS_TI_BIT = 0
++} gmac_dma_status_reg_t;
++
++#define DMA_STATUS_EB_NUM_BITS 3
++#define DMA_STATUS_TS_NUM_BITS 3
++#define DMA_STATUS_RS_NUM_BITS 3
++
++typedef enum gmac_dma_op_mode_reg {
++ DMA_OP_MODE_SF_BIT = 21,
++ DMA_OP_MODE_FTF_BIT = 20,
++ DMA_OP_MODE_TTC_BIT = 14,
++ DMA_OP_MODE_ST_BIT = 13,
++ DMA_OP_MODE_RFD_BIT = 11,
++ DMA_OP_MODE_RFA_BIT = 9,
++ DMA_OP_MODE_EFC_BIT = 8,
++ DMA_OP_MODE_FEF_BIT = 7,
++ DMA_OP_MODE_FUF_BIT = 6,
++ DMA_OP_MODE_RTC_BIT = 3,
++ DMA_OP_MODE_OSF_BIT = 2,
++ DMA_OP_MODE_SR_BIT = 1
++} gmac_dma_op_mode_reg_t;
++
++#define DMA_OP_MODE_TTC_NUM_BITS 3
++#define DMA_OP_MODE_RFD_NUM_BITS 2
++#define DMA_OP_MODE_RFA_NUM_BITS 2
++#define DMA_OP_MODE_RTC_NUM_BITS 2
++
++typedef enum gmac_dma_intr_enable_reg {
++ DMA_INT_ENABLE_NI_BIT = 16,
++ DMA_INT_ENABLE_AI_BIT = 15,
++ DMA_INT_ENABLE_ERE_BIT = 14,
++ DMA_INT_ENABLE_FBE_BIT = 13,
++ DMA_INT_ENABLE_ETE_BIT = 10,
++ DMA_INT_ENABLE_RW_BIT = 9,
++ DMA_INT_ENABLE_RS_BIT = 8,
++ DMA_INT_ENABLE_RU_BIT = 7,
++ DMA_INT_ENABLE_RI_BIT = 6,
++ DMA_INT_ENABLE_UN_BIT = 5,
++ DMA_INT_ENABLE_OV_BIT = 4,
++ DMA_INT_ENABLE_TJ_BIT = 3,
++ DMA_INT_ENABLE_TU_BIT = 2,
++ DMA_INT_ENABLE_TS_BIT = 1,
++ DMA_INT_ENABLE_TI_BIT = 0
++} gmac_dma_intr_enable_reg_t;
++
++typedef enum gmac_dma_missed_overflow_reg {
++ DMA_MISSED_OVERFLOW_OFOC_BIT = 28, // Overflow bit for FIFO Overflow Counter
++ DMA_MISSED_OVERFLOW_AMFC_BIT = 17, // Application Missed Frames Count
++ DMA_MISSED_OVERFLOW_OAMFO_BIT = 16, // Overflow bit for Application Missed Frames Count
++ DMA_MISSED_OVERFLOW_CMFC_BIT = 0 // Controller Missed Frames Count
++} gmac_dma_missed_overflow_reg_t;
++
++#define DMA_MISSED_OVERFLOW_OAMFO_NUM_BITS 11
++#define DMA_MISSED_OVERFLOW_CMFC_NUM_BITS 16
++
++typedef enum gmac_dma_current_tx_desc_reg {
++ DMA_CUR_TX_DESC_A_BIT = 0
++} gmac_dma_current_tx_desc_reg_t;
++
++typedef enum gmac_dma_current_rx_desc_reg {
++ DMA_CUR_RX_DESC_A_BIT = 0
++} gmac_dma_current_rx_desc_reg_t;
++
++typedef enum gmac_dma_current_tx_adr_reg {
++ DMA_CUR_TX_ADR_A_BIT = 0
++} gmac_dma_current_tx_adr_reg_t;
++
++typedef enum gmac_dma_current_rx_adr_reg {
++ DMA_CUR_RX_ADR_A_BIT = 0
++} gmac_dma_current_rx_adr_reg_t;
++
++/**
++ * Descriptor support
++ */
++/** Descriptor status word field definitions */
++typedef enum desc_status {
++ descOwnByDma = 0x80000000, /* descriptor is owned by DMA engine */
++
++ descFrameLengthMask = 0x3FFF0000, /* Receive descriptor frame length */
++ descFrameLengthShift = 16,
++
++ descError = 0x00008000, /* Error summary bit - OR of the following bits: v */
++
++ descRxTruncated = 0x00004000, /* Rx - no more descriptors for receive frame E */
++
++ descRxLengthError = 0x00001000, /* Rx - frame size not matching with length field */
++ descRxDamaged = 0x00000800, /* Rx - frame was damaged due to buffer overflow E */
++ descRxFirst = 0x00000200, /* Rx - first descriptor of the frame */
++ descRxLast = 0x00000100, /* Rx - last descriptor of the frame */
++ descRxLongFrame = 0x00000080, /* Rx - frame is longer than 1518 bytes E */
++ descRxCollision = 0x00000040, /* Rx - late collision occurred during reception E */
++ descRxFrameEther = 0x00000020, /* Rx - Frame type - Ethernet, otherwise 802.3 */
++ descRxWatchdog = 0x00000010, /* Rx - watchdog timer expired during reception E */
++ descRxMiiError = 0x00000008, /* Rx - error reported by MII interface E */
++ descRxDribbling = 0x00000004, /* Rx - frame contains noninteger multiple of 8 bits */
++ descRxCrc = 0x00000002, /* Rx - CRC error E */
++
++ descTxTimeout = 0x00004000, /* Tx - Transmit jabber timeout E */
++ descTxLostCarrier = 0x00000800, /* Tx - carrier lost during tramsmission E */
++ descTxNoCarrier = 0x00000400, /* Tx - no carrier signal from the tranceiver E */
++ descTxLateCollision = 0x00000200, /* Tx - transmission aborted due to collision E */
++ descTxExcCollisions = 0x00000100, /* Tx - transmission aborted after 16 collisions E */
++ descTxVLANFrame = 0x00000080, /* Tx - VLAN-type frame */
++ descTxCollMask = 0x00000078, /* Tx - Collision count */
++ descTxCollShift = 3,
++ descTxExcDeferral = 0x00000004, /* Tx - excessive deferral E */
++ descTxUnderflow = 0x00000002, /* Tx - late data arrival from the memory E */
++ descTxDeferred = 0x00000001, /* Tx - frame transmision deferred */
++} desc_status_t;
++
++/** Descriptor length word field definitions */
++typedef enum desc_length {
++ descTxIntEnable = 0x80000000, /* Tx - interrupt on completion */
++ descTxLast = 0x40000000, /* Tx - Last segment of the frame */
++ descTxFirst = 0x20000000, /* Tx - First segment of the frame */
++ descTxDisableCrc = 0x04000000, /* Tx - Add CRC disabled (first segment only) */
++
++ descEndOfRing = 0x02000000, /* End of descriptors ring */
++ descChain = 0x01000000, /* Second buffer address is chain address */
++ descTxDisablePadd = 0x00800000, /* disable padding, added by - reyaz */
++
++ descSize2Mask = 0x003FF800, /* Buffer 2 size */
++ descSize2Shift = 11,
++ descSize1Mask = 0x000007FF, /* Buffer 1 size */
++ descSize1Shift = 0,
++} desc_length_t;
++
++typedef enum rx_desc_status {
++ RX_DESC_STATUS_OWN_BIT = 31,
++ RX_DESC_STATUS_AFM_BIT = 30,
++ RX_DESC_STATUS_FL_BIT = 16,
++ RX_DESC_STATUS_ES_BIT = 15,
++ RX_DESC_STATUS_DE_BIT = 14,
++ RX_DESC_STATUS_SAF_BIT = 13,
++ RX_DESC_STATUS_LE_BIT = 12,
++ RX_DESC_STATUS_OE_BIT = 11,
++ RX_DESC_STATUS_IPC_BIT = 10,
++ RX_DESC_STATUS_FS_BIT = 9,
++ RX_DESC_STATUS_LS_BIT = 8,
++ RX_DESC_STATUS_VLAN_BIT = 7,
++ RX_DESC_STATUS_LC_BIT = 6,
++ RX_DESC_STATUS_FT_BIT = 5,
++ RX_DESC_STATUS_RWT_BIT = 4,
++ RX_DESC_STATUS_RE_BIT = 3,
++ RX_DESC_STATUS_DRE_BIT = 2,
++ RX_DESC_STATUS_CE_BIT = 1,
++ RX_DESC_STATUS_MAC_BIT = 0
++} rx_desc_status_t;
++
++#define RX_DESC_STATUS_FL_NUM_BITS 14
++
++typedef enum rx_desc_length {
++ RX_DESC_LENGTH_DIC_BIT = 31,
++ RX_DESC_LENGTH_RER_BIT = 25,
++ RX_DESC_LENGTH_RCH_BIT = 24,
++ RX_DESC_LENGTH_RBS2_BIT = 11,
++ RX_DESC_LENGTH_RBS1_BIT = 0,
++} rx_desc_length_t;
++
++#define RX_DESC_LENGTH_RBS2_NUM_BITS 11
++#define RX_DESC_LENGTH_RBS1_NUM_BITS 11
++
++typedef enum tx_desc_status {
++ TX_DESC_STATUS_OWN_BIT = 31,
++ TX_DESC_STATUS_ES_BIT = 15,
++ TX_DESC_STATUS_JT_BIT = 14,
++ TX_DESC_STATUS_FF_BIT = 13,
++ TX_DESC_STATUS_LOC_BIT = 11,
++ TX_DESC_STATUS_NC_BIT = 10,
++ TX_DESC_STATUS_LC_BIT = 9,
++ TX_DESC_STATUS_EC_BIT = 8,
++ TX_DESC_STATUS_VF_BIT = 7,
++ TX_DESC_STATUS_CC_BIT = 3,
++ TX_DESC_STATUS_ED_BIT = 2,
++ TX_DESC_STATUS_UF_BIT = 1,
++ TX_DESC_STATUS_DB_BIT = 0
++} tx_desc_status_t;
++
++#define TX_DESC_STATUS_CC_NUM_BITS 4
++
++typedef enum tx_desc_length {
++ TX_DESC_LENGTH_IC_BIT = 31,
++ TX_DESC_LENGTH_LS_BIT = 30,
++ TX_DESC_LENGTH_FS_BIT = 29,
++ TX_DESC_LENGTH_DC_BIT = 26,
++ TX_DESC_LENGTH_TER_BIT = 25,
++ TX_DESC_LENGTH_TCH_BIT = 24,
++ TX_DESC_LENGTH_DP_BIT = 23,
++ TX_DESC_LENGTH_TBS2_BIT = 11,
++ TX_DESC_LENGTH_TBS1_BIT = 0
++} tx_desc_length_t;
++
++#define TX_DESC_LENGTH_TBS2_NUM_BITS 11
++#define TX_DESC_LENGTH_TBS1_NUM_BITS 11
++
++/** Return the number of descriptors available for the CPU to fill with new
++ * packet info */
++static inline int available_for_write(gmac_desc_list_info_t* desc_list)
++{
++ return desc_list->empty_count;
++}
++
++/** Return non-zero if there is a descriptor available with a packet with which
++ * the GMAC DMA has finished */
++static inline int tx_available_for_read(gmac_desc_list_info_t* desc_list)
++{
++ return desc_list->full_count &&
++ !((desc_list->base_ptr + desc_list->r_index)->status & (1UL << TX_DESC_STATUS_OWN_BIT));
++}
++
++/** Return non-zero if there is a descriptor available with a packet with which
++ * the GMAC DMA has finished */
++static inline int rx_available_for_read(gmac_desc_list_info_t* desc_list)
++{
++ return desc_list->full_count &&
++ !((desc_list->base_ptr + desc_list->r_index)->status & (1UL << RX_DESC_STATUS_OWN_BIT));
++}
++
++/**
++ * @param A u32 containing the status from a received frame's DMA descriptor
++ * @return An int which is non-zero if a valid received frame is fully contained
++ * within the descriptor from whence the status came
++ */
++static inline int is_rx_valid(u32 status)
++{
++ return !(status & descError) &&
++ (status & descRxFirst) &&
++ (status & descRxLast);
++}
++
++static inline int is_rx_dribbling(u32 status)
++{
++ return status & descRxDribbling;
++}
++
++static inline u32 get_rx_length(u32 status)
++{
++ return (status & descFrameLengthMask) >> descFrameLengthShift;
++}
++
++static inline int is_rx_collision_error(u32 status)
++{
++ return status & (descRxDamaged | descRxCollision);
++}
++
++static inline int is_rx_crc_error(u32 status)
++{
++ return status & descRxCrc;
++}
++
++static inline int is_rx_frame_error(u32 status)
++{
++ return status & descRxDribbling;
++}
++
++static inline int is_rx_length_error(u32 status)
++{
++ return status & descRxLengthError;
++}
++
++static inline int is_rx_long_frame(u32 status)
++{
++ return status & descRxLongFrame;
++}
++
++static inline int is_tx_valid(u32 status)
++{
++ return !(status & descError);
++}
++
++static inline int is_tx_collision_error(u32 status)
++{
++ return (status & descTxCollMask) >> descTxCollShift;
++}
++
++static inline int is_tx_aborted(u32 status)
++{
++ return status & (descTxLateCollision | descTxExcCollisions);
++}
++
++static inline int is_tx_carrier_error(u32 status)
++{
++ return status & (descTxLostCarrier | descTxNoCarrier);
++}
++
++/**
++ * GMAC private metadata
++ */
++static gmac_priv_t priv_data;
++static gmac_priv_t* priv = &priv_data;
++
++/**
++ * Descriptor list management
++ */
++
++static void init_rx_descriptor(
++ gmac_dma_desc_t* desc,
++ int end_of_ring,
++ int disable_ioc)
++{
++ desc->status = 0;
++ desc->length = 0;
++ if (disable_ioc) {
++ desc->length |= (1UL << RX_DESC_LENGTH_DIC_BIT);
++ }
++ if (end_of_ring) {
++ desc->length |= (1UL << RX_DESC_LENGTH_RER_BIT);
++ }
++ desc->buffer1 = 0;
++ desc->buffer2 = 0;
++ desc->skb = 0;
++}
++
++static void init_tx_descriptor(
++ gmac_dma_desc_t* desc,
++ int end_of_ring,
++ int enable_ioc,
++ int disable_crc,
++ int disable_padding)
++{
++ desc->status = 0;
++ desc->length = 0;
++ if (enable_ioc) {
++ desc->length |= (1UL << TX_DESC_LENGTH_IC_BIT);
++ }
++ if (disable_crc) {
++ desc->length |= (1UL << TX_DESC_LENGTH_DC_BIT);
++ }
++ if (disable_padding) {
++ desc->length |= (1UL << TX_DESC_LENGTH_DP_BIT);
++ }
++ if (end_of_ring) {
++ desc->length |= (1UL << TX_DESC_LENGTH_TER_BIT);
++ }
++ desc->buffer1 = 0;
++ desc->buffer2 = 0;
++ desc->skb = 0;
++}
++
++static void init_rx_desc_list(
++ gmac_desc_list_info_t* desc_list,
++ gmac_dma_desc_t* base_ptr,
++ int num_descriptors)
++{
++ int i;
++
++ desc_list->base_ptr = base_ptr;
++ desc_list->num_descriptors = num_descriptors;
++ desc_list->empty_count = num_descriptors;
++ desc_list->full_count = 0;
++ desc_list->r_index = 0;
++ desc_list->w_index = 0;
++
++ for (i=0; i < (num_descriptors - 1); i++) {
++ init_rx_descriptor(base_ptr + i, 0, 0);
++ }
++ init_rx_descriptor(base_ptr + i, 1, 0);
++}
++
++static void init_tx_desc_list(
++ gmac_desc_list_info_t* desc_list,
++ gmac_dma_desc_t* base_ptr,
++ int num_descriptors)
++{
++ int i;
++
++ desc_list->base_ptr = base_ptr;
++ desc_list->num_descriptors = num_descriptors;
++ desc_list->empty_count = num_descriptors;
++ desc_list->full_count = 0;
++ desc_list->r_index = 0;
++ desc_list->w_index = 0;
++
++ for (i=0; i < (num_descriptors - 1); i++) {
++ init_tx_descriptor(base_ptr + i, 0, 1, 0, 0);
++ }
++ init_tx_descriptor(base_ptr + i, 1, 1, 0, 0);
++}
++
++static void rx_take_ownership(gmac_desc_list_info_t* desc_list)
++{
++ int i;
++ for (i=0; i < desc_list->num_descriptors; i++) {
++ (desc_list->base_ptr + i)->status &= ~(1UL << RX_DESC_STATUS_OWN_BIT);
++ }
++}
++
++static void tx_take_ownership(gmac_desc_list_info_t* desc_list)
++{
++ int i;
++ for (i=0; i < desc_list->num_descriptors; i++) {
++ (desc_list->base_ptr + i)->status &= ~(1UL << TX_DESC_STATUS_OWN_BIT);
++ }
++}
++
++static int set_tx_descriptor(
++ gmac_priv_t* priv,
++ dma_addr_t dma_address,
++ u32 length,
++ sk_buff_t* skb)
++{
++ int index;
++ gmac_dma_desc_t* tx;
++
++ // Are sufficicent descriptors available for writing by the CPU?
++ if (!available_for_write(&priv->tx_gmac_desc_list_info)) {
++ return -1;
++ }
++
++ // Get the index of the next TX descriptor available for writing by the CPU
++ index = priv->tx_gmac_desc_list_info.w_index;
++
++ // Get a pointer to the next TX descriptor available for writing by the CPU
++ tx = priv->tx_gmac_desc_list_info.base_ptr + index;
++
++ // Initialise the TX descriptor length field for the passed single buffer,
++ // without destroying any fields we wish to be persistent
++
++ // No chained second buffer
++ tx->length &= ~(1UL << TX_DESC_LENGTH_TCH_BIT);
++ // Single descriptor holds entire packet
++ tx->length |= ((1UL << TX_DESC_LENGTH_LS_BIT) | (1UL << TX_DESC_LENGTH_FS_BIT));
++ // Zero the second buffer length field
++ tx->length &= ~(((1UL << TX_DESC_LENGTH_TBS2_NUM_BITS) - 1) << TX_DESC_LENGTH_TBS2_BIT);
++ // Zero the first buffer length field
++ tx->length &= ~(((1UL << TX_DESC_LENGTH_TBS1_NUM_BITS) - 1) << TX_DESC_LENGTH_TBS1_BIT);
++ // Fill in the first buffer length
++ tx->length |= (length << TX_DESC_LENGTH_TBS1_BIT);
++
++ // Initialise the first buffer pointer to the single passed buffer
++ tx->buffer1 = dma_address;
++
++ // Remember the socket buffer associated with the single passed buffer
++ tx->skb = (u32)skb;
++
++ // Update the index of the next descriptor available for writing by the CPU
++ priv->tx_gmac_desc_list_info.w_index = (tx->length & (1UL << TX_DESC_LENGTH_TER_BIT)) ? 0 : index + 1;
++
++ // make sure all memory updates are complete before releasing the GMAC on the data.
++ wmb();
++
++ // Hand TX descriptor to the GMAC DMA by setting the status bit.
++ tx->status = (1UL << TX_DESC_STATUS_OWN_BIT);
++
++ // Account for the number of descriptors used to hold the new packet
++ --priv->tx_gmac_desc_list_info.empty_count;
++ ++priv->tx_gmac_desc_list_info.full_count;
++
++ return index;
++}
++
++static int get_tx_descriptor(
++ gmac_priv_t* priv,
++ u32* status,
++ dma_addr_t* dma_address,
++ u32* length,
++ sk_buff_t** skb)
++{
++ int index;
++ gmac_dma_desc_t *tx;
++
++ // Is there at least one descriptor with which the GMAC DMA has finished?
++ if (!tx_available_for_read(&priv->tx_gmac_desc_list_info)) {
++ return -1;
++ }
++
++ // Get the index of the descriptor released the longest time ago by the
++ // GMAC DMA
++ index = priv->tx_gmac_desc_list_info.r_index;
++
++ // Get a pointer to the descriptor released the longest time ago by the
++ // GMAC DMA
++ tx = priv->tx_gmac_desc_list_info.base_ptr + index;
++
++ // Extract the status field
++ if (status) {
++ *status = tx->status;
++ }
++
++ // Extract the length field - only cope with the first buffer associated
++ // with the descriptor
++ if (length) {
++ *length = (tx->length >> TX_DESC_LENGTH_TBS1_BIT) &
++ ((1UL << TX_DESC_LENGTH_TBS1_NUM_BITS) - 1);
++ }
++
++ // Extract the pointer to the buffer containing the packet - only cope with
++ // the first buffer associated with the descriptor
++ if (dma_address) {
++ *dma_address = tx->buffer1;
++ }
++
++ // Extract the pointer to the socket buffer associated with the packet
++ if (skb) {
++ *skb = (sk_buff_t*)(tx->skb);
++ }
++
++ // Update the index of the next descriptor with which the GMAC DMA may have
++ // finished
++ priv->tx_gmac_desc_list_info.r_index = (tx->length & (1UL << TX_DESC_LENGTH_TER_BIT)) ? 0 : index + 1;
++
++ // Account for the number of descriptors freed to hold new packets
++ ++priv->tx_gmac_desc_list_info.empty_count;
++ --priv->tx_gmac_desc_list_info.full_count;
++
++ return index;
++}
++
++int set_rx_descriptor(
++ gmac_priv_t* priv,
++ dma_addr_t dma_address,
++ u32 length,
++ sk_buff_t* skb)
++{
++ int index;
++ gmac_dma_desc_t* rx;
++ int num_descriptors_required;
++
++ // Currently only support using a single descriptor to describe each packet
++ // queued with the GMAc DMA
++ num_descriptors_required = 1;
++
++ // Are sufficicent descriptors available for writing by the CPU?
++ if (available_for_write(&priv->rx_gmac_desc_list_info) < num_descriptors_required) {
++ index = -1;
++ } else {
++ // Get the index of the next RX descriptor available for writing by the CPU
++ index = priv->rx_gmac_desc_list_info.w_index;
++
++ // Get a pointer to the next RX descriptor available for writing by the CPU
++ rx = priv->rx_gmac_desc_list_info.base_ptr + index;
++
++ // Initialise the RX descriptor length field for the passed single buffer,
++ // without destroying any fields we wish to be persistent
++
++ // No chained second buffer
++ rx->length &= ~(1UL << RX_DESC_LENGTH_RCH_BIT);
++ // Zero the second buffer length field
++ rx->length &= ~(((1UL << RX_DESC_LENGTH_RBS2_NUM_BITS) - 1) << RX_DESC_LENGTH_RBS2_BIT);
++ // Zero the first buffer length field
++ rx->length &= ~(((1UL << RX_DESC_LENGTH_RBS1_NUM_BITS) - 1) << RX_DESC_LENGTH_RBS1_BIT);
++ // Fill in the first buffer length
++ rx->length |= (length << RX_DESC_LENGTH_RBS1_BIT);
++
++ // Initialise the first buffer pointer to the single passed buffer
++ rx->buffer1 = dma_address;
++
++ // Remember the socket buffer associated with the single passed buffer
++ rx->skb = (u32)skb;
++
++ wmb();
++
++ // Initialise RX descriptor status to be owned by the GMAC DMA
++ rx->status = (1UL << RX_DESC_STATUS_OWN_BIT);
++
++ // Update the index of the next descriptor available for writing by the CPU
++ priv->rx_gmac_desc_list_info.w_index = (rx->length & (1UL << RX_DESC_LENGTH_RER_BIT)) ? 0 : index + 1;
++
++ // Account for the number of descriptors used to hold the new packet
++ priv->rx_gmac_desc_list_info.empty_count -= num_descriptors_required;
++ priv->rx_gmac_desc_list_info.full_count += num_descriptors_required;
++ }
++
++ return index;
++}
++
++int get_rx_descriptor(
++ gmac_priv_t* priv,
++ u32* status,
++ dma_addr_t* dma_address,
++ u32* length,
++ sk_buff_t** skb)
++{
++ int index;
++ gmac_dma_desc_t *rx;
++ int num_descriptors_required;
++
++ // Is there at least one descriptor with which the GMAC DMA has finished?
++ if (!rx_available_for_read(&priv->rx_gmac_desc_list_info)) {
++ return -1;
++ }
++
++ // Currently can only cope with packets entirely contained within a single
++ // descriptor
++ num_descriptors_required = 1;
++
++ // Get the index of the descriptor released the longest time ago by the
++ // GMAC DMA
++ index = priv->rx_gmac_desc_list_info.r_index;
++
++ // Get a pointer to the descriptor released the longest time ago by the
++ // GMAC DMA
++ rx = priv->rx_gmac_desc_list_info.base_ptr + index;
++
++ // Extract the status field
++ if (status) {
++ *status = rx->status;
++ }
++
++ // Extract the length field - only cope with the first buffer associated
++ // with the descriptor
++ if (length) {
++ *length = (rx->length >> RX_DESC_LENGTH_RBS1_BIT) &
++ ((1UL << RX_DESC_LENGTH_RBS1_NUM_BITS) - 1);
++ }
++
++ // Extract the pointer to the buffer containing the packet - only cope with
++ // the first buffer associated with the descriptor
++ if (dma_address) {
++ *dma_address = rx->buffer1;
++ }
++
++ // Extract the pointer to the socket buffer associated with the packet
++ if (skb) {
++ *skb = (sk_buff_t*)(rx->skb);
++ }
++
++ wmb();
++ // Update the index of the next descriptor with which the GMAC DMA may have
++ // finished
++ priv->rx_gmac_desc_list_info.r_index = (rx->length & (1UL << RX_DESC_LENGTH_RER_BIT)) ? 0 : index + 1;
++
++ // Account for the number of descriptors freed to hold new packets
++ priv->rx_gmac_desc_list_info.empty_count += num_descriptors_required;
++ priv->rx_gmac_desc_list_info.full_count -= num_descriptors_required;
++
++ return index;
++}
++
++/**
++ * GMAC register access functions
++ */
++
++/**
++ * MAC register access functions
++ */
++
++/**
++ * @param priv A gmac_priv_t* pointing to private device data
++ * @param reg_num An int specifying the index of the MAC register to access
++ */
++static inline u32 mac_reg_read(gmac_priv_t* priv, int reg_num)
++{
++ return *(volatile u32*)(priv->macBase + (reg_num << 2));
++}
++
++/**
++ * @param priv A gmac_priv_t* pointing to private device data
++ * @param reg_num An int specifying the index of the MAC register to access
++ */
++static inline void mac_reg_write(gmac_priv_t* priv, int reg_num, u32 value)
++{
++ *(volatile u32*)(priv->macBase + (reg_num << 2)) = value;
++
++}
++
++/**
++ * @param priv A gmac_priv_t* pointing to private device data
++ * @param reg_num An int specifying the index of the MAC register to access
++ * @param bits_to_clear A u32 specifying which bits of the specified register to
++ * clear. A set bit in this parameter will cause the matching bit in the
++ * register to be cleared
++ */
++static inline void mac_reg_clear_mask(gmac_priv_t* priv, int reg_num, u32 bits_to_clear)
++{
++ mac_reg_write(priv, reg_num, mac_reg_read(priv, reg_num) & ~bits_to_clear);
++}
++
++/**
++ * @param priv A gmac_priv_t* pointing to private device data
++ * @param reg_num An int specifying the index of the MAC register to access
++ * @param bits_to_set A u32 specifying which bits of the specified register to
++ * set. A set bit in this parameter will cause the matching bit in the register
++ * to be set
++ */
++static inline void mac_reg_set_mask(gmac_priv_t* priv, int reg_num, u32 bits_to_set)
++{
++ mac_reg_write(priv, reg_num, mac_reg_read(priv, reg_num) | bits_to_set);
++}
++
++
++/**
++ * DMA register access functions
++ */
++
++/**
++ * @param priv A gmac_priv_t* pointing to private device data
++ * @param reg_num An int specifying the index of the DMA register to access
++ */
++static inline u32 dma_reg_read(gmac_priv_t* priv, int reg_num)
++{
++ return *(volatile u32*)(priv->dmaBase + (reg_num << 2));
++}
++
++/**
++ * @param priv A gmac_priv_t* pointing to private device data
++ * @param reg_num An int specifying the index of the DMA register to access
++ */
++static inline void dma_reg_write(gmac_priv_t* priv, int reg_num, u32 value)
++{
++ *(volatile u32*)(priv->dmaBase + (reg_num << 2)) = value;
++ wmb();
++}
++
++/**
++ * @param priv A gmac_priv_t* pointing to private device data
++ * @param reg_num An int specifying the index of the DMA register to access
++ * @param bits_to_clear A u32 specifying which bits of the specified register to
++ * clear. A set bit in this parameter will cause the matching bit in the
++ * register to be cleared
++ * @return An u32 containing the new value written to the register
++ */
++static inline u32 dma_reg_clear_mask(gmac_priv_t* priv, int reg_num, u32 bits_to_clear)
++{
++ u32 new_value = dma_reg_read(priv, reg_num) & ~bits_to_clear;
++ dma_reg_write(priv, reg_num, new_value);
++ return new_value;
++}
++
++/**
++ * @param priv A gmac_priv_t* pointing to private device data
++ * @param reg_num An int specifying the index of the DMA register to access
++ * @param bits_to_set A u32 specifying which bits of the specified register to
++ * set. A set bit in this parameter will cause the matching bit in the register
++ * to be set
++ * @return An u32 containing the new value written to the register
++ */
++static inline u32 dma_reg_set_mask(gmac_priv_t* priv, int reg_num, u32 bits_to_set)
++{
++ u32 new_value = dma_reg_read(priv, reg_num) | bits_to_set;
++ dma_reg_write(priv, reg_num, new_value);
++ return new_value;
++}
++
++static void eth_down(void)
++{
++ // Stop transmitter, take ownership of all tx descriptors
++ dma_reg_clear_mask(priv, DMA_OP_MODE_REG, DMA_OP_MODE_ST_BIT);
++ if (priv->desc_base_addr) {
++ tx_take_ownership(&priv->tx_gmac_desc_list_info);
++ }
++
++ // Stop receiver, take ownership of all rx descriptors
++ dma_reg_clear_mask(priv, DMA_OP_MODE_REG, DMA_OP_MODE_SR_BIT);
++ if (priv->desc_base_addr) {
++ rx_take_ownership(&priv->rx_gmac_desc_list_info);
++ }
++
++ // Free descriptor resources. The TX descriptor will not have a packet
++ // buffer attached, as this is provided by the stack when transmission is
++ // required and ownership is not retained by the descriptor, as the stack
++ // waits for transmission to complete via polling
++ if (priv->desc_base_addr) {
++ // Free receive descriptors, accounting for buffer offset used to
++ // ensure IP header alignment
++ while (1) {
++ dma_addr_t dma_address;
++ if (get_rx_descriptor(priv, 0, &dma_address, 0, 0) < 0) {
++ break;
++ }
++ free((void*)(dma_address - ETHER_FRAME_ALIGN_WASTAGE));
++ }
++
++ // Free DMA descriptors' storage
++ free(priv->desc_base_addr);
++
++ // Remember that we've freed the descriptors memory
++ priv->desc_base_addr = 0;
++ }
++}
++
++/*
++ * Reads a register from the MII Management serial interface
++ */
++int phy_read(int phyaddr, int phyreg)
++{
++ int data = 0;
++ u32 addr = (phyaddr << MAC_GMII_ADR_PA_BIT) |
++ (phyreg << MAC_GMII_ADR_GR_BIT) |
++ (5 << MAC_GMII_ADR_CR_BIT) |
++ (1UL << MAC_GMII_ADR_GB_BIT);
++
++ mac_reg_write(priv, MAC_GMII_ADR_REG, addr);
++
++ for (;;) {
++ if (!(mac_reg_read(priv, MAC_GMII_ADR_REG) & (1UL << MAC_GMII_ADR_GB_BIT))) {
++ // Successfully read from PHY
++ data = mac_reg_read(priv, MAC_GMII_DATA_REG) & 0xFFFF;
++ break;
++ }
++ }
++
++#ifdef DEBUG_GMAC_INIT
++ printf("phy_read() phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", phyaddr, phyreg, data);
++#endif // DEBUG_GMAC_INIT
++
++ return data;
++}
++
++/*
++ * Writes a register to the MII Management serial interface
++ */
++void phy_write(int phyaddr, int phyreg, int phydata)
++{
++ u32 addr = (phyaddr << MAC_GMII_ADR_PA_BIT) |
++ (phyreg << MAC_GMII_ADR_GR_BIT) |
++ (5 << MAC_GMII_ADR_CR_BIT) |
++ (1UL << MAC_GMII_ADR_GW_BIT) |
++ (1UL << MAC_GMII_ADR_GB_BIT);
++
++ mac_reg_write(priv, MAC_GMII_DATA_REG, phydata);
++ mac_reg_write(priv, MAC_GMII_ADR_REG, addr);
++
++ for (;;) {
++ if (!(mac_reg_read(priv, MAC_GMII_ADR_REG) & (1UL << MAC_GMII_ADR_GB_BIT))) {
++ break;
++ }
++ }
++
++#ifdef DEBUG_GMAC_INIT
++ printf("phy_write() phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", phyaddr, phyreg, phydata);
++#endif // DEBUG_GMAC_INIT
++}
++
++/*
++ * Finds and reports the PHY address
++ */
++int phy_detect(void)
++{
++ int found = 0;
++ int phyaddr;
++
++ // Scan all 32 PHY addresses if necessary
++ priv->phy_type = 0;
++ for (phyaddr = 1; phyaddr < 33; ++phyaddr) {
++ unsigned int id1, id2;
++
++ // Read the PHY identifiers
++ id1 = phy_read(phyaddr & 31, MII_PHYSID1);
++ id2 = phy_read(phyaddr & 31, MII_PHYSID2);
++
++#ifdef DEBUG_GMAC_INIT
++ printf("phy_detect() PHY adr = %u -> phy_id1=0x%x, phy_id2=0x%x\n", phyaddr, id1, id2);
++#endif // DEBUG_GMAC_INIT
++
++ // Make sure it is a valid identifier
++ if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 &&
++ id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) {
++#ifdef DEBUG_GMAC_INIT
++ printf("phy_detect() Found PHY at address = %u\n", phyaddr);
++#endif // DEBUG_GMAC_INIT
++
++ priv->phy_id = phyaddr & 31;
++ priv->phy_type = id1 << 16 | id2;
++ priv->phy_addr = phyaddr;
++
++ found = 1;
++ break;
++ }
++ }
++
++ return found;
++}
++
++void start_phy_reset(void)
++{
++ // Ask the PHY to reset
++ phy_write(priv->phy_addr, MII_BMCR, BMCR_RESET);
++}
++
++int is_phy_reset_complete(void)
++{
++ int complete = 0;
++ int bmcr;
++
++ // Read back the status until it indicates reset, or we timeout
++ bmcr = phy_read(priv->phy_addr, MII_BMCR);
++ if (!(bmcr & BMCR_RESET)) {
++ complete = 1;
++ }
++
++ return complete;
++}
++
++void set_phy_type_rgmii(void)
++{
++ // Use sysctrl to switch MAC link lines into either (G)MII or RGMII mode
++ *(volatile u32*)SYS_CTRL_GMAC_CTRL |= (1UL << SYS_CTRL_GMAC_RGMII);
++}
++
++void phy_initialise(void)
++{
++ switch (priv->phy_type) {
++ case PHY_TYPE_VITESSE_VSC8201XVZ:
++ {
++ // Allow s/w to override mode/duplex pin settings
++ u32 acsr = phy_read(priv->phy_id, VSC8201_MII_ACSR);
++
++ printf("PHY is Vitesse VSC8201XVZ\n");
++ acsr |= (1UL << VSC8201_MII_ACSR_MDPPS_BIT);
++ phy_write(priv->phy_id, VSC8201_MII_ACSR, acsr);
++ }
++ break;
++ case PHY_TYPE_REALTEK_RTL8211BGR:
++ printf("PHY is Realtek RTL8211BGR\n");
++ set_phy_type_rgmii();
++ break;
++ case PHY_TYPE_LSI_ET1011C:
++ {
++ u32 phy_reg;
++
++ printf("PHY is LSI ET1011C\n");
++
++ // Configure clocks
++ phy_reg = phy_read(priv->phy_id, ET1011C_MII_CONFIG);
++ phy_reg &= ~(((1UL << ET1011C_MII_CONFIG_IFMODESEL_NUM_BITS) - 1) << ET1011C_MII_CONFIG_IFMODESEL);
++ phy_reg |= (ET1011C_MII_CONFIG_IFMODESEL_GMII_MII << ET1011C_MII_CONFIG_IFMODESEL);
++ phy_reg |= ((1UL << ET1011C_MII_CONFIG_SYSCLKEN) |
++ (1UL << ET1011C_MII_CONFIG_TXCLKEN) |
++ (1UL << ET1011C_MII_CONFIG_TBI_RATESEL) |
++ (1UL << ET1011C_MII_CONFIG_CRS_TX_EN));
++ phy_write(priv->phy_id, ET1011C_MII_CONFIG, phy_reg);
++
++ // Enable Tx/Rx LED
++ phy_reg = phy_read(priv->phy_id, ET1011C_MII_LED2);
++ phy_reg &= ~(((1UL << ET1011C_MII_LED2_LED_NUM_BITS) - 1) << ET1011C_MII_LED2_LED_TXRX);
++ phy_reg |= (ET1011C_MII_LED2_LED_TXRX_ACTIVITY << ET1011C_MII_LED2_LED_TXRX);
++ phy_write(priv->phy_id, ET1011C_MII_LED2, phy_reg);
++ }
++ break;
++ }
++}
++
++int detect_link_speed(void)
++{
++ u32 lpa2 = phy_read(priv->phy_id, MII_STAT1000);
++
++ if (((lpa2 & LPA_1000FULL)) ||
++ ((lpa2 & LPA_1000HALF))) {
++ priv->link_is_1000M = 1;
++ } else {
++ priv->link_is_1000M = 0;
++ }
++
++ return 0;
++}
++
++int is_autoneg_complete(void)
++{
++ return phy_read(priv->phy_addr, MII_BMSR) & BMSR_ANEGCOMPLETE;
++}
++
++int is_link_ok(void)
++{
++ return phy_read(priv->phy_id, MII_BMSR) & BMSR_LSTATUS;
++}
++
++int eth_init(bd_t *bd)
++{
++ u32 version;
++ u32 reg_contents;
++ u8 *mac_addr;
++ int desc;
++
++ // Set hardware device base addresses
++ priv->macBase = (MAC_BASE_PA + MAC_BASE_OFFSET);
++ priv->dmaBase = (MAC_BASE_PA + DMA_BASE_OFFSET);
++
++#ifdef DEBUG_GMAC_INIT
++ printf("eth_init(): About to reset MAC core\n");
++#endif // DEBUG_GMAC_INIT
++ // Ensure the MAC block is properly reset
++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL = (1UL << SYS_CTRL_RSTEN_MAC_BIT);
++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_MAC_BIT);
++
++ // Enable the clock to the MAC block
++ *(volatile u32*)SYS_CTRL_CKEN_SET_CTRL = (1UL << SYS_CTRL_CKEN_MAC_BIT);
++
++ version = mac_reg_read(priv, MAC_VERSION_REG);
++#ifdef DEBUG_GMAC_INIT
++ printf("eth_init(): GMAC Synopsis version = 0x%x, vendor version = 0x%x\n", version & 0xff, (version >> 8) & 0xff);
++#endif // DEBUG_GMAC_INIT
++
++ // Use simple mux for 25/125 Mhz clock switching
++ *(volatile u32*)SYS_CTRL_GMAC_CTRL |= (1UL << SYS_CTRL_GMAC_SIMPLE_MAX);
++
++ // Enable GMII_GTXCLK to follow GMII_REFCLK - required for gigabit PHY
++ *(volatile u32*)SYS_CTRL_GMAC_CTRL |= (1UL << SYS_CTRL_GMAC_CKEN_GTX);
++
++ // Disable all GMAC interrupts
++ dma_reg_write(priv, DMA_INT_ENABLE_REG, 0);
++
++ // Reset the entire GMAC
++ dma_reg_write(priv, DMA_BUS_MODE_REG, 1UL << DMA_BUS_MODE_SWR_BIT);
++
++ // Wait for the reset operation to complete
++ printf("Wait GMAC to reset");
++ while (dma_reg_read(priv, DMA_BUS_MODE_REG) & (1UL << DMA_BUS_MODE_SWR_BIT)) {
++ udelay(250000);
++ printf(".");
++ }
++ printf("\n");
++
++ // Attempt to discover link speed from the PHY
++ if (!phy_detect()) {
++ printf("No PHY found\n");
++ } else {
++ // Ensure the PHY is in a sensible state by resetting it
++ start_phy_reset();
++
++ // Read back the status until it indicates reset, or we timeout
++ printf("Wait for PHY reset");
++ while (!is_phy_reset_complete()) {
++ udelay(250000);
++ printf(".");
++ }
++ printf("\n");
++
++ // Setup the PHY based on its type
++ phy_initialise();
++
++ printf("Wait for link to come up");
++ while (!is_link_ok()) {
++ udelay(250000);
++ printf(".");
++ }
++ printf("Link up\n");
++
++ // Wait for PHY to have completed autonegotiation
++ printf("Wait for auto-negotiation to complete");
++ while (!is_autoneg_complete()) {
++ udelay(250000);
++ printf(".");
++ }
++ printf("\n");
++
++ // Interrogate the PHY for the link speed
++ if (detect_link_speed()) {
++ printf("Failed to detect link speed\n");
++ } else {
++ printf("Link is %s\n", priv->link_is_1000M ? "1000M" : "10M/100M");
++ }
++ }
++
++ // Form the MAC config register contents
++ reg_contents = 0;
++ if (!priv->link_is_1000M) {
++ reg_contents |= (1UL << MAC_CONFIG_PS_BIT); // Gigabit
++ }
++ reg_contents |= (1UL << MAC_CONFIG_DM_BIT); // Full duplex
++ reg_contents |= ((1UL << MAC_CONFIG_TE_BIT) |
++ (1UL << MAC_CONFIG_RE_BIT));
++ mac_reg_write(priv, MAC_CONFIG_REG, reg_contents);
++
++ // Form the MAC frame filter register contents
++ reg_contents = 0;
++ mac_reg_write(priv, MAC_FRAME_FILTER_REG, reg_contents);
++
++ // Form the hash table registers contents
++ mac_reg_write(priv, MAC_HASH_HIGH_REG, 0);
++ mac_reg_write(priv, MAC_HASH_LOW_REG, 0);
++
++ // Form the MAC flow control register contents
++ reg_contents = 0;
++ reg_contents |= ((1UL << MAC_FLOW_CNTL_RFE_BIT) |
++ (1UL << MAC_FLOW_CNTL_TFE_BIT));
++ mac_reg_write(priv, MAC_FLOW_CNTL_REG, reg_contents);
++
++ // Form the MAC VLAN tag register contents
++ reg_contents = 0;
++ mac_reg_write(priv, MAC_VLAN_TAG_REG, reg_contents);
++
++ // Form the MAC addr0 high and low registers contents from the character
++ // string representation from the environment
++ mac_addr = getenv("ethaddr");
++#ifdef DEBUG_GMAC_INIT
++ printf("eth_init(): Mac addr = %s\n", mac_addr);
++#endif // DEBUG_GMAC_INIT
++ reg_contents = simple_strtoul(mac_addr+0, 0, 16);
++ reg_contents |= (simple_strtoul(mac_addr+3, 0, 16) << 8);
++ reg_contents |= (simple_strtoul(mac_addr+6, 0, 16) << 16);
++ reg_contents |= (simple_strtoul(mac_addr+9, 0, 16) << 24);
++ mac_reg_write(priv, MAC_ADR0_LOW_REG, reg_contents);
++ reg_contents = simple_strtoul(mac_addr+12, 0, 16);
++ reg_contents |= (simple_strtoul(mac_addr+15, 0, 16) << 8);
++ mac_reg_write(priv, MAC_ADR0_HIGH_REG, reg_contents);
++
++ // Disable all MMC interrupt sources
++ mac_reg_write(priv, MMC_RX_MASK_REG, ~0UL);
++ mac_reg_write(priv, MMC_TX_MASK_REG, ~0UL);
++
++ // Remember how large the unified descriptor array is to be
++ priv->total_num_descriptors = NUM_RX_DMA_DESCRIPTORS + NUM_TX_DMA_DESCRIPTORS;
++
++ // Need a consistent DMA mapping covering all the memory occupied by DMA
++ // unified descriptor array, as both CPU and DMA engine will be reading and
++ // writing descriptor fields.
++ priv->desc_base_addr = (gmac_dma_desc_t*)malloc(sizeof(gmac_dma_desc_t) * priv->total_num_descriptors);
++ if (!priv->desc_base_addr) {
++ printf("eth_init(): Failed to allocate memory for DMA descriptors\n");
++ goto err_out;
++ }
++
++ // Initialise the structures managing the TX descriptor list
++ init_tx_desc_list(&priv->tx_gmac_desc_list_info,
++ priv->desc_base_addr,
++ NUM_TX_DMA_DESCRIPTORS);
++
++ // Initialise the structures managing the RX descriptor list
++ init_rx_desc_list(&priv->rx_gmac_desc_list_info,
++ priv->desc_base_addr + NUM_TX_DMA_DESCRIPTORS,
++ priv->total_num_descriptors - NUM_TX_DMA_DESCRIPTORS);
++
++ // Prepare receive descriptors
++ desc = 0;
++ while (available_for_write(&priv->rx_gmac_desc_list_info)) {
++ // Allocate a new buffer for the descriptor which is large enough for
++ // any packet received from the link
++ dma_addr_t dma_address = (dma_addr_t)malloc(ETHER_MTU + ETHER_FRAME_ALIGN_WASTAGE + EXTRA_RX_SKB_SPACE);
++ if (!dma_address) {
++ printf("eth_init(): No memory for socket buffer\n");
++ break;
++ }
++
++ desc = set_rx_descriptor(priv,
++ dma_address + ETHER_FRAME_ALIGN_WASTAGE,
++ ETHER_MTU + EXTRA_RX_SKB_SPACE,
++ 0);
++
++ if (desc < 0) {
++ // Release the buffer
++ free((void*)dma_address);
++
++ printf("eth_init(): Error, no RX descriptor available\n");
++ goto err_out;
++ }
++ }
++
++ // Initialise the GMAC DMA bus mode register
++ dma_reg_write(priv, DMA_BUS_MODE_REG, ((0UL << DMA_BUS_MODE_FB_BIT) |
++ (0UL << DMA_BUS_MODE_PR_BIT) |
++ (32UL << DMA_BUS_MODE_PBL_BIT) | // AHB burst size
++ (1UL << DMA_BUS_MODE_DSL_BIT) |
++ (0UL << DMA_BUS_MODE_DA_BIT)));
++
++ // Write the address of the start of the tx descriptor array
++ dma_reg_write(priv, DMA_TX_DESC_ADR_REG, (u32)priv->desc_base_addr);
++
++ // Write the address of the start of the rx descriptor array
++ dma_reg_write(priv, DMA_RX_DESC_ADR_REG,
++ (u32)(priv->desc_base_addr + priv->tx_gmac_desc_list_info.num_descriptors));
++
++ // Clear any pending interrupt requests
++ dma_reg_write(priv, DMA_STATUS_REG, dma_reg_read(priv, DMA_STATUS_REG));
++
++ // Initialise the GMAC DMA operation mode register, starting both the
++ // transmitter and receiver
++ dma_reg_write(priv, DMA_OP_MODE_REG, ((1UL << DMA_OP_MODE_SF_BIT) | // Store and forward
++ (0UL << DMA_OP_MODE_TTC_BIT) | // Tx threshold
++ (1UL << DMA_OP_MODE_ST_BIT) | // Enable transmitter
++ (0UL << DMA_OP_MODE_RTC_BIT) | // Rx threshold
++ (1UL << DMA_OP_MODE_SR_BIT))); // Enable receiver
++
++ // Success
++ return 1;
++
++err_out:
++ eth_down();
++
++ return 0;
++}
++
++void eth_halt(void)
++{
++ eth_down();
++
++ // Disable the clock to the MAC block
++ *(volatile u32*)(SYS_CTRL_CKEN_CLR_CTRL) = (1UL << SYS_CTRL_CKEN_MAC_BIT);
++}
++
++int eth_rx(void)
++{
++ static const int MAX_LOOPS = 2000; // 2 seconds
++
++ int length = 0;
++ dma_addr_t dma_address;
++ u32 desc_status;
++ int loops = 0;
++
++ // Look for the first available received packet
++ while (loops++ < MAX_LOOPS) {
++ if (get_rx_descriptor(priv, &desc_status, &dma_address, 0, 0) >= 0) {
++ if (is_rx_valid(desc_status)) {
++ // Get the length of the packet within the buffer
++ length = get_rx_length(desc_status);
++
++ // Pass packet up the network stack - will block until processing is
++ // completed
++ NetReceive((uchar*)dma_address, length);
++ } else {
++ printf("eth_rx() Received packet has bad desc_status = 0x%08x\n", desc_status);
++ }
++
++ // Re-initialise the RX descriptor with its buffer - relies on always
++ // setting an RX descriptor directly after getting it
++ if (set_rx_descriptor(priv, dma_address, ETHER_MTU + EXTRA_RX_SKB_SPACE, 0) < 0) {
++ printf("eth_rx(): Failed to set RX descriptor\n");
++ }
++
++ break;
++ }
++
++ // Wait a bit before trying again to get a descriptor
++ udelay(1000); // 1mS
++ }
++
++ return length;
++}
++
++int eth_send(volatile void *packet, int length)
++{
++ // Transmit the new packet
++ while (1) {
++ // Get the TX descriptor
++ if (set_tx_descriptor(priv, (dma_addr_t)packet, length, 0) >= 0) {
++ // Tell the GMAC to poll for the updated descriptor
++ dma_reg_write(priv, DMA_TX_POLL_REG, 0);
++ break;
++ }
++
++ // Wait a bit before trying again to get a descriptor
++ udelay(1000); // 1mS
++ }
++
++ // Wait for the packet buffer to be finished with
++ while (get_tx_descriptor(priv, 0, 0, 0, 0) < 0) {
++ // Wait a bit before examining the descriptor again
++ udelay(1000); // 1mS
++ }
++
++ return length;
++}
++
+diff -Nurd u-boot-1.1.2/board/oxnas/ide-810.c u-boot-1.1.2-oxe810/board/oxnas/ide-810.c
+--- u-boot-1.1.2/board/oxnas/ide-810.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-oxe810/board/oxnas/ide-810.c 2008-06-11 17:55:18.000000000 +0200
+@@ -0,0 +1,892 @@
++/*
++ * (C) Copyright 2005
++ * Oxford Semiconductor Ltd
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,`
++ * MA 02111-1307 USA
++ */
++#include <common.h>
++
++#define SATA_DMA_CHANNEL 0
++
++#define DMA_CTRL_STATUS (0x0)
++#define DMA_BASE_SRC_ADR (0x4)
++#define DMA_BASE_DST_ADR (0x8)
++#define DMA_BYTE_CNT (0xC)
++#define DMA_CURRENT_SRC_ADR (0x10)
++#define DMA_CURRENT_DST_ADR (0x14)
++#define DMA_CURRENT_BYTE_CNT (0x18)
++#define DMA_INTR_ID (0x1C)
++#define DMA_INTR_CLEAR_REG (DMA_CURRENT_SRC_ADR)
++
++#define DMA_CALC_REG_ADR(channel, register) ((volatile u32*)(DMA_BASE_PA + ((channel) << 5) + (register)))
++
++#define DMA_CTRL_STATUS_FAIR_SHARE_ARB (1 << 0)
++#define DMA_CTRL_STATUS_IN_PROGRESS (1 << 1)
++#define DMA_CTRL_STATUS_SRC_DREQ_MASK (0x0000003C)
++#define DMA_CTRL_STATUS_SRC_DREQ_SHIFT (2)
++#define DMA_CTRL_STATUS_DEST_DREQ_MASK (0x000003C0)
++#define DMA_CTRL_STATUS_DEST_DREQ_SHIFT (6)
++#define DMA_CTRL_STATUS_INTR (1 << 10)
++#define DMA_CTRL_STATUS_NXT_FREE (1 << 11)
++#define DMA_CTRL_STATUS_RESET (1 << 12)
++#define DMA_CTRL_STATUS_DIR_MASK (0x00006000)
++#define DMA_CTRL_STATUS_DIR_SHIFT (13)
++#define DMA_CTRL_STATUS_SRC_ADR_MODE (1 << 15)
++#define DMA_CTRL_STATUS_DEST_ADR_MODE (1 << 16)
++#define DMA_CTRL_STATUS_TRANSFER_MODE_A (1 << 17)
++#define DMA_CTRL_STATUS_TRANSFER_MODE_B (1 << 18)
++#define DMA_CTRL_STATUS_SRC_WIDTH_MASK (0x00380000)
++#define DMA_CTRL_STATUS_SRC_WIDTH_SHIFT (19)
++#define DMA_CTRL_STATUS_DEST_WIDTH_MASK (0x01C00000)
++#define DMA_CTRL_STATUS_DEST_WIDTH_SHIFT (22)
++#define DMA_CTRL_STATUS_PAUSE (1 << 25)
++#define DMA_CTRL_STATUS_INTERRUPT_ENABLE (1 << 26)
++#define DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED (1 << 27)
++#define DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED (1 << 28)
++#define DMA_CTRL_STATUS_STARVE_LOW_PRIORITY (1 << 29)
++#define DMA_CTRL_STATUS_INTR_CLEAR_ENABLE (1 << 30)
++
++#define DMA_BYTE_CNT_MASK ((1 << 21) - 1)
++#define DMA_BYTE_CNT_WR_EOT_MASK (1 << 30)
++#define DMA_BYTE_CNT_RD_EOT_MASK (1 << 31)
++
++#define MAKE_FIELD(value, num_bits, bit_num) (((value) & ((1 << (num_bits)) - 1)) << (bit_num))
++
++typedef enum oxnas_dma_mode {
++ OXNAS_DMA_MODE_FIXED,
++ OXNAS_DMA_MODE_INC
++} oxnas_dma_mode_t;
++
++typedef enum oxnas_dma_direction {
++ OXNAS_DMA_TO_DEVICE,
++ OXNAS_DMA_FROM_DEVICE
++} oxnas_dma_direction_t;
++
++/* The available buses to which the DMA controller is attached */
++typedef enum oxnas_dma_transfer_bus
++{
++ OXNAS_DMA_SIDE_A,
++ OXNAS_DMA_SIDE_B
++} oxnas_dma_transfer_bus_t;
++
++/* Direction of data flow between the DMA controller's pair of interfaces */
++typedef enum oxnas_dma_transfer_direction
++{
++ OXNAS_DMA_A_TO_A,
++ OXNAS_DMA_B_TO_A,
++ OXNAS_DMA_A_TO_B,
++ OXNAS_DMA_B_TO_B
++} oxnas_dma_transfer_direction_t;
++
++/* The available data widths */
++typedef enum oxnas_dma_transfer_width
++{
++ OXNAS_DMA_TRANSFER_WIDTH_8BITS,
++ OXNAS_DMA_TRANSFER_WIDTH_16BITS,
++ OXNAS_DMA_TRANSFER_WIDTH_32BITS
++} oxnas_dma_transfer_width_t;
++
++/* The mode of the DMA transfer */
++typedef enum oxnas_dma_transfer_mode
++{
++ OXNAS_DMA_TRANSFER_MODE_SINGLE,
++ OXNAS_DMA_TRANSFER_MODE_BURST
++} oxnas_dma_transfer_mode_t;
++
++/* The available transfer targets */
++typedef enum oxnas_dma_dreq
++{
++ OXNAS_DMA_DREQ_SATA = 0,
++ OXNAS_DMA_DREQ_MEMORY = 15
++} oxnas_dma_dreq_t;
++
++typedef struct oxnas_dma_device_settings {
++ unsigned long address_;
++ unsigned fifo_size_; // Chained transfers must take account of FIFO offset at end of previous transfer
++ unsigned char dreq_;
++ unsigned read_eot_:1;
++ unsigned read_final_eot_:1;
++ unsigned write_eot_:1;
++ unsigned write_final_eot_:1;
++ unsigned bus_:1;
++ unsigned width_:2;
++ unsigned transfer_mode_:1;
++ unsigned address_mode_:1;
++ unsigned address_really_fixed_:1;
++} oxnas_dma_device_settings_t;
++
++static const int MAX_NO_ERROR_LOOPS = 100000; /* 1 second in units of 10uS */
++static const int MAX_DMA_XFER_LOOPS = 300000; /* 30 seconds in units of 100uS */
++static const int MAX_DMA_ABORT_LOOPS = 10000; /* 0.1 second in units of 10uS */
++static const int MAX_SRC_READ_LOOPS = 10000; /* 0.1 second in units of 10uS */
++static const int MAX_SRC_WRITE_LOOPS = 10000; /* 0.1 second in units of 10uS */
++static const int MAX_NOT_BUSY_LOOPS = 10000; /* 1 second in units of 100uS */
++
++/* The internal SATA drive on which we should attempt to find partitions */
++static volatile u32* sata_regs_base[2] =
++{
++ (volatile u32*)SATA_0_REGS_BASE,
++ (volatile u32*)SATA_1_REGS_BASE,
++
++};
++static u32 wr_sata_orb1[2] = { 0, 0 };
++static u32 wr_sata_orb2[2] = { 0, 0 };
++static u32 wr_sata_orb3[2] = { 0, 0 };
++static u32 wr_sata_orb4[2] = { 0, 0 };
++
++static oxnas_dma_device_settings_t oxnas_sata_dma_settings = {
++ .address_ = SATA_DATA_BASE_PA,
++ .fifo_size_ = 16,
++ .dreq_ = OXNAS_DMA_DREQ_SATA,
++ .read_eot_ = 0,
++ .read_final_eot_ = 1,
++ .write_eot_ = 0,
++ .write_final_eot_ = 1,
++ .bus_ = OXNAS_DMA_SIDE_A,
++ .width_ = OXNAS_DMA_TRANSFER_WIDTH_32BITS,
++ .transfer_mode_ = OXNAS_DMA_TRANSFER_MODE_BURST,
++ .address_mode_ = OXNAS_DMA_MODE_FIXED,
++ .address_really_fixed_ = 0
++};
++
++oxnas_dma_device_settings_t oxnas_ram_dma_settings = {
++ .address_ = 0,
++ .fifo_size_ = 0,
++ .dreq_ = OXNAS_DMA_DREQ_MEMORY,
++ .read_eot_ = 1,
++ .read_final_eot_ = 1,
++ .write_eot_ = 1,
++ .write_final_eot_ = 1,
++ .bus_ = OXNAS_DMA_SIDE_B,
++ .width_ = OXNAS_DMA_TRANSFER_WIDTH_32BITS,
++ .transfer_mode_ = OXNAS_DMA_TRANSFER_MODE_BURST,
++ .address_mode_ = OXNAS_DMA_MODE_FIXED,
++ .address_really_fixed_ = 1
++};
++
++static void xfer_wr_shadow_to_orbs(int device)
++{
++ *(sata_regs_base[device] + SATA_ORB1_OFF) = wr_sata_orb1[device];
++ *(sata_regs_base[device] + SATA_ORB2_OFF) = wr_sata_orb2[device];
++ *(sata_regs_base[device] + SATA_ORB3_OFF) = wr_sata_orb3[device];
++ *(sata_regs_base[device] + SATA_ORB4_OFF) = wr_sata_orb4[device];
++}
++
++static inline void device_select(int device)
++{
++ /* master/slave has no meaning to SATA core */
++}
++
++static int disk_present[CFG_IDE_MAXDEVICE];
++
++#include <ata.h>
++
++unsigned char oxnas_sata_inb(int device, int port)
++{
++ unsigned char val = 0;
++
++ /* Only permit accesses to disks found to be present during ide_preinit() */
++ if (!disk_present[device]) {
++ return ATA_STAT_FAULT;
++ }
++
++ device_select(device);
++
++ switch (port) {
++ case ATA_PORT_CTL:
++ val = (*(sata_regs_base[device] + SATA_ORB4_OFF) & (0xFFUL << SATA_CTL_BIT)) >> SATA_CTL_BIT;
++ break;
++ case ATA_PORT_FEATURE:
++ val = (*(sata_regs_base[device] + SATA_ORB2_OFF) & (0xFFUL << SATA_FEATURE_BIT)) >> SATA_FEATURE_BIT;
++ break;
++ case ATA_PORT_NSECT:
++ val = (*(sata_regs_base[device] + SATA_ORB2_OFF) & (0xFFUL << SATA_NSECT_BIT)) >> SATA_NSECT_BIT;
++ break;
++ case ATA_PORT_LBAL:
++ val = (*(sata_regs_base[device] + SATA_ORB3_OFF) & (0xFFUL << SATA_LBAL_BIT)) >> SATA_LBAL_BIT;
++ break;
++ case ATA_PORT_LBAM:
++ val = (*(sata_regs_base[device] + SATA_ORB3_OFF) & (0xFFUL << SATA_LBAM_BIT)) >> SATA_LBAM_BIT;
++ break;
++ case ATA_PORT_LBAH:
++ val = (*(sata_regs_base[device] + SATA_ORB3_OFF) & (0xFFUL << SATA_LBAH_BIT)) >> SATA_LBAH_BIT;
++ break;
++ case ATA_PORT_DEVICE:
++ val = (*(sata_regs_base[device] + SATA_ORB3_OFF) & (0xFFUL << SATA_HOB_LBAH_BIT)) >> SATA_HOB_LBAH_BIT;
++ val |= (*(sata_regs_base[device] + SATA_ORB1_OFF) & (0xFFUL << SATA_DEVICE_BIT)) >> SATA_DEVICE_BIT;
++ break;
++ case ATA_PORT_COMMAND:
++ val = (*(sata_regs_base[device] + SATA_ORB2_OFF) & (0xFFUL << SATA_COMMAND_BIT)) >> SATA_COMMAND_BIT;
++ val |= ATA_STAT_DRQ ;
++ break;
++ default:
++ printf("ide_inb() Unknown port = %d\n", port);
++ break;
++ }
++
++// printf("inb: %d:%01x => %02x\n", device, port, val);
++
++ return val;
++}
++
++/**
++ * Possible that ATA status will not become no-error, so must have timeout
++ * @returns An int which is zero on error
++ */
++static inline int wait_no_error(int device)
++{
++ int status = 0;
++
++ /* Check for ATA core error */
++ if (*(sata_regs_base[device] + SATA_INT_STATUS_OFF) & (1 << SATA_INT_STATUS_ERROR_BIT)) {
++ printf("wait_no_error() SATA core flagged error\n");
++ } else {
++ int loops = MAX_NO_ERROR_LOOPS;
++ do {
++ /* Check for ATA device error */
++ if (!(oxnas_sata_inb(device, ATA_PORT_COMMAND) & (1 << ATA_STATUS_ERR_BIT))) {
++ status = 1;
++ break;
++ }
++ udelay(10);
++ } while (--loops);
++
++ if (!loops) {
++ printf("wait_no_error() Timed out of wait for SATA no-error condition\n");
++ }
++ }
++
++ return status;
++}
++
++/**
++ * Expect SATA command to always finish, perhaps with error
++ * @returns An int which is zero on error
++ */
++static inline int wait_sata_command_not_busy(int device)
++{
++ /* Wait for data to be available */
++ int status = 0;
++ int loops = MAX_NOT_BUSY_LOOPS;
++ do {
++ if (!(*(sata_regs_base[device] + SATA_COMMAND_OFF) & (1 << SATA_CMD_BUSY_BIT) )) {
++ status = 1;
++ break;
++ }
++ udelay(100);
++ } while (--loops);
++
++ if (!loops) {
++ printf("wait_sata_command_not_busy() Timed out of wait for SATA command to finish\n");
++ }
++
++ return status;
++}
++
++void oxnas_sata_outb(int device, int port, unsigned char val)
++{
++ typedef enum send_method {
++ SEND_NONE,
++ SEND_SIMPLE,
++ SEND_CMD,
++ SEND_CTL,
++ } send_method_t;
++
++ /* Only permit accesses to disks found to be present during ide_preinit() */
++ if (!disk_present[device]) {
++ return;
++ }
++
++// printf("outb: %d:%01x <= %02x\n", device, port, val);
++
++ device_select(device);
++
++ send_method_t send_regs = SEND_NONE;
++ switch (port) {
++ case ATA_PORT_CTL:
++ wr_sata_orb4[device] &= ~(0xFFUL << SATA_CTL_BIT);
++ wr_sata_orb4[device] |= (val << SATA_CTL_BIT);
++ send_regs = SEND_CTL;
++ break;
++ case ATA_PORT_FEATURE:
++ wr_sata_orb2[device] &= ~(0xFFUL << SATA_FEATURE_BIT);
++ wr_sata_orb2[device] |= (val << SATA_FEATURE_BIT);
++ send_regs = SEND_SIMPLE;
++ break;
++ case ATA_PORT_NSECT:
++ wr_sata_orb2[device] &= ~(0xFFUL << SATA_NSECT_BIT);
++ wr_sata_orb2[device] |= (val << SATA_NSECT_BIT);
++ send_regs = SEND_SIMPLE;
++ break;
++ case ATA_PORT_LBAL:
++ wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAL_BIT);
++ wr_sata_orb3[device] |= (val << SATA_LBAL_BIT);
++ send_regs = SEND_SIMPLE;
++ break;
++ case ATA_PORT_LBAM:
++ wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAM_BIT);
++ wr_sata_orb3[device] |= (val << SATA_LBAM_BIT);
++ send_regs = SEND_SIMPLE;
++ break;
++ case ATA_PORT_LBAH:
++ wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAH_BIT);
++ wr_sata_orb3[device] |= (val << SATA_LBAH_BIT);
++ send_regs = SEND_SIMPLE;
++ break;
++ case ATA_PORT_DEVICE:
++ wr_sata_orb1[device] &= ~(0xFFUL << SATA_DEVICE_BIT);
++ wr_sata_orb1[device] |= ((val & 0xf0) << SATA_DEVICE_BIT);
++ wr_sata_orb3[device] &= ~(0xFFUL << SATA_HOB_LBAH_BIT);
++ wr_sata_orb3[device] |= ((val & 0x0f) << SATA_HOB_LBAH_BIT);
++ send_regs = SEND_SIMPLE;
++ break;
++ case ATA_PORT_COMMAND:
++ wr_sata_orb2[device] &= ~(0xFFUL << SATA_COMMAND_BIT);
++ wr_sata_orb2[device] |= (val << SATA_COMMAND_BIT);
++ send_regs = SEND_CMD;
++ break;
++ default:
++ printf("ide_outb() Unknown port = %d\n", port);
++ }
++
++ u32 command;
++ switch (send_regs) {
++ case SEND_CMD:
++ wait_sata_command_not_busy(device);
++ command = *(sata_regs_base[device] + SATA_COMMAND_OFF);
++ command &= ~SATA_OPCODE_MASK;
++ command |= SATA_CMD_WRITE_TO_ORB_REGS;
++ xfer_wr_shadow_to_orbs(device);
++ wait_sata_command_not_busy(device);
++ *(sata_regs_base[device] + SATA_COMMAND_OFF) = command;
++ if (!wait_no_error(device)) {
++ printf("oxnas_sata_outb() Wait for ATA no-error timed-out\n");
++ }
++ break;
++ case SEND_CTL:
++ wait_sata_command_not_busy(device);
++ command = *(sata_regs_base[device] + SATA_COMMAND_OFF);
++ command &= ~SATA_OPCODE_MASK;
++ command |= SATA_CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
++ xfer_wr_shadow_to_orbs(device);
++ wait_sata_command_not_busy(device);
++ *(sata_regs_base[device] + SATA_COMMAND_OFF) = command;
++ if (!wait_no_error(device)) {
++ printf("oxnas_sata_outb() Wait for ATA no-error timed-out\n");
++ }
++ break;
++ default:
++ break;
++ }
++}
++
++static u32 encode_start(u32 ctrl_status)
++{
++ return ctrl_status & ~DMA_CTRL_STATUS_PAUSE;
++}
++
++static void dma_start(void)
++{
++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS) =
++ encode_start(*(DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS)));
++}
++
++static unsigned long encode_control_status(
++ oxnas_dma_device_settings_t* src_settings,
++ oxnas_dma_device_settings_t* dst_settings)
++{
++ unsigned long ctrl_status;
++ oxnas_dma_transfer_direction_t direction;
++
++ ctrl_status = DMA_CTRL_STATUS_PAUSE; // Paused
++ ctrl_status |= DMA_CTRL_STATUS_FAIR_SHARE_ARB; // High priority
++ ctrl_status |= (src_settings->dreq_ << DMA_CTRL_STATUS_SRC_DREQ_SHIFT); // Dreq
++ ctrl_status |= (dst_settings->dreq_ << DMA_CTRL_STATUS_DEST_DREQ_SHIFT); // Dreq
++ ctrl_status &= ~DMA_CTRL_STATUS_RESET; // !RESET
++
++ // Use new interrupt clearing register
++ ctrl_status |= DMA_CTRL_STATUS_INTR_CLEAR_ENABLE;
++
++ // Setup the transfer direction and burst/single mode for the two DMA busses
++ if (src_settings->bus_ == OXNAS_DMA_SIDE_A) {
++ // Set the burst/single mode for bus A based on src device's settings
++ if (src_settings->transfer_mode_ == OXNAS_DMA_TRANSFER_MODE_BURST) {
++ ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_A;
++ } else {
++ ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_A;
++ }
++
++ if (dst_settings->bus_ == OXNAS_DMA_SIDE_A) {
++ direction = OXNAS_DMA_A_TO_A;
++ } else {
++ direction = OXNAS_DMA_A_TO_B;
++
++ // Set the burst/single mode for bus B based on dst device's settings
++ if (dst_settings->transfer_mode_ == OXNAS_DMA_TRANSFER_MODE_BURST) {
++ ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_B;
++ } else {
++ ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_B;
++ }
++ }
++ } else {
++ // Set the burst/single mode for bus B based on src device's settings
++ if (src_settings->transfer_mode_ == OXNAS_DMA_TRANSFER_MODE_BURST) {
++ ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_B;
++ } else {
++ ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_B;
++ }
++
++ if (dst_settings->bus_ == OXNAS_DMA_SIDE_A) {
++ direction = OXNAS_DMA_B_TO_A;
++
++ // Set the burst/single mode for bus A based on dst device's settings
++ if (dst_settings->transfer_mode_ == OXNAS_DMA_TRANSFER_MODE_BURST) {
++ ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_A;
++ } else {
++ ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_A;
++ }
++ } else {
++ direction = OXNAS_DMA_B_TO_B;
++ }
++ }
++ ctrl_status |= (direction << DMA_CTRL_STATUS_DIR_SHIFT);
++
++ // Setup source address mode fixed or increment
++ if (src_settings->address_mode_ == OXNAS_DMA_MODE_FIXED) {
++ // Fixed address
++ ctrl_status &= ~(DMA_CTRL_STATUS_SRC_ADR_MODE);
++
++ // Set up whether fixed address is _really_ fixed
++ if (src_settings->address_really_fixed_) {
++ ctrl_status |= DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED;
++ } else {
++ ctrl_status &= ~DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED;
++ }
++ } else {
++ // Incrementing address
++ ctrl_status |= DMA_CTRL_STATUS_SRC_ADR_MODE;
++ ctrl_status &= ~DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED;
++ }
++
++ // Setup destination address mode fixed or increment
++ if (dst_settings->address_mode_ == OXNAS_DMA_MODE_FIXED) {
++ // Fixed address
++ ctrl_status &= ~(DMA_CTRL_STATUS_DEST_ADR_MODE);
++
++ // Set up whether fixed address is _really_ fixed
++ if (dst_settings->address_really_fixed_) {
++ ctrl_status |= DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED;
++ } else {
++ ctrl_status &= ~DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED;
++ }
++ } else {
++ // Incrementing address
++ ctrl_status |= DMA_CTRL_STATUS_DEST_ADR_MODE;
++ ctrl_status &= ~DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED;
++ }
++
++ // Set up the width of the transfers on the DMA buses
++ ctrl_status |= (src_settings->width_ << DMA_CTRL_STATUS_SRC_WIDTH_SHIFT);
++ ctrl_status |= (dst_settings->width_ << DMA_CTRL_STATUS_DEST_WIDTH_SHIFT);
++
++ // Setup the priority arbitration scheme
++ ctrl_status &= ~DMA_CTRL_STATUS_STARVE_LOW_PRIORITY; // !Starve low priority
++
++ return ctrl_status;
++}
++
++static u32 encode_final_eot(
++ oxnas_dma_device_settings_t* src_settings,
++ oxnas_dma_device_settings_t* dst_settings,
++ unsigned long length)
++{
++ // Write the length, with EOT configuration for a final transfer
++ unsigned long encoded = length;
++ if (dst_settings->write_final_eot_) {
++ encoded |= DMA_BYTE_CNT_WR_EOT_MASK;
++ } else {
++ encoded &= ~DMA_BYTE_CNT_WR_EOT_MASK;
++ }
++ if (src_settings->read_final_eot_) {
++ encoded |= DMA_BYTE_CNT_RD_EOT_MASK;
++ } else {
++ encoded &= ~DMA_BYTE_CNT_RD_EOT_MASK;
++ }
++ return encoded;
++}
++
++static void dma_start_write(ulong* buffer, int num_bytes)
++{
++ // Assemble complete memory settings
++ oxnas_dma_device_settings_t mem_settings = oxnas_ram_dma_settings;
++ mem_settings.address_ = (unsigned long)buffer;
++ mem_settings.address_mode_ = OXNAS_DMA_MODE_INC;
++
++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS) = encode_control_status(&mem_settings, &oxnas_sata_dma_settings);
++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_BASE_SRC_ADR) = mem_settings.address_;
++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_BASE_DST_ADR) = oxnas_sata_dma_settings.address_;
++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_BYTE_CNT) = encode_final_eot(&mem_settings, &oxnas_sata_dma_settings, num_bytes);
++
++ dma_start();
++}
++
++static void dma_start_read(ulong* buffer, int num_bytes)
++{
++ // Assemble complete memory settings
++ oxnas_dma_device_settings_t mem_settings = oxnas_ram_dma_settings;
++ mem_settings.address_ = (unsigned long)buffer;
++ mem_settings.address_mode_ = OXNAS_DMA_MODE_INC;
++
++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS) = encode_control_status(&oxnas_sata_dma_settings, &mem_settings);
++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_BASE_SRC_ADR) = oxnas_sata_dma_settings.address_;
++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_BASE_DST_ADR) = mem_settings.address_;
++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_BYTE_CNT) = encode_final_eot(&oxnas_sata_dma_settings, &mem_settings, num_bytes);
++
++ dma_start();
++}
++
++static inline int dma_busy(void)
++{
++ return (*DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS)) & DMA_CTRL_STATUS_IN_PROGRESS;
++}
++
++static int wait_dma_not_busy(int device)
++{
++ unsigned int cleanup_required = 0;
++
++ /* Poll for DMA completion */
++ int loops = MAX_DMA_XFER_LOOPS;
++ do {
++ if (!dma_busy()) {
++ break;
++ }
++ udelay(100);
++ } while (--loops);
++
++ if (!loops) {
++ printf("wait_dma_not_busy() Timed out of wait for DMA not busy\n");
++ cleanup_required = 1;
++ }
++
++ if (cleanup_required) {
++ /* Abort DMA to make sure it has finished. */
++ unsigned long ctrl_status = *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS);
++ ctrl_status |= DMA_CTRL_STATUS_RESET;
++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS) = ctrl_status;
++
++ // Wait for the channel to become idle - should be quick as should
++ // finish after the next AHB single or burst transfer
++ loops = MAX_DMA_ABORT_LOOPS;
++ do {
++ if (!(*DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS) & DMA_CTRL_STATUS_IN_PROGRESS)) {
++ break;
++ }
++ udelay(10);
++ } while (--loops);
++
++ if (!loops) {
++ printf("wait_dma_not_busy() Timed out of wait for DMA channel abort\n");
++ } else {
++ /* Successfully cleanup the DMA channel */
++ cleanup_required = 0;
++ }
++
++ // Deassert reset for the channel
++ ctrl_status = *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS);
++ ctrl_status &= ~DMA_CTRL_STATUS_RESET;
++ *DMA_CALC_REG_ADR(SATA_DMA_CHANNEL, DMA_CTRL_STATUS) = ctrl_status;
++ }
++
++ return !cleanup_required;
++}
++
++/**
++ * Possible that ATA status will not become not-busy, so must have timeout
++ */
++static unsigned int wait_not_busy(int device, unsigned long timeout_secs)
++{
++ int busy = 1;
++ unsigned long loops = (timeout_secs * 1000) / 50;
++ do {
++ // Test the ATA status register BUSY flag
++ if (!((*(sata_regs_base[device] + SATA_ORB2_OFF) >> SATA_COMMAND_BIT) & (1UL << ATA_STATUS_BSY_BIT))) {
++ /* Not busy, so stop polling */
++ busy = 0;
++ break;
++ }
++
++ // Wait for 50mS before sampling ATA status register again
++ udelay(50000);
++ } while (--loops);
++
++ return busy;
++}
++
++void oxnas_sata_output_data(int device, ulong *sect_buf, int words)
++{
++ /* Only permit accesses to disks found to be present during ide_preinit() */
++ if (!disk_present[device]) {
++ return;
++ }
++
++ /* Select the required internal SATA drive */
++ device_select(device);
++
++ /* Start the DMA channel sending data from the passed buffer to the SATA core */
++ dma_start_write(sect_buf, words << 2);
++
++ /* Don't know why we need this delay, but without it the wait for DMA not
++ busy times soemtimes out, e.g. when saving environment to second disk */
++ udelay(1000);
++
++ /* Wait for DMA to finish */
++ if (!wait_dma_not_busy(device)) {
++ printf("Timed out of wait for DMA channel for SATA device %d to have in-progress clear\n", device);
++ }
++
++ /* Sata core should finish after DMA */
++ if (wait_not_busy(device, 30)) {
++ printf("Timed out of wait for SATA device %d to have BUSY clear\n", device);
++ }
++ if (!wait_no_error(device)) {
++ printf("oxnas_sata_output_data() Wait for ATA no-error timed-out\n");
++ }
++}
++
++void oxnas_sata_input_data(int device, ulong *sect_buf, int words)
++{
++ /* Only permit accesses to disks found to be present during ide_preinit() */
++ if (!disk_present[device]) {
++ return;
++ }
++
++ /* Select the required internal SATA drive */
++ device_select(device);
++
++ /* Start the DMA channel receiving data from the SATA core into the passed buffer */
++ dma_start_read(sect_buf, words << 2);
++
++ /* Sata core should finish before DMA */
++ if (wait_not_busy(device, 30)) {
++ printf("Timed out of wait for SATA device %d to have BUSY clear\n", device);
++ }
++ if (!wait_no_error(device)) {
++ printf("oxnas_sata_output_data() Wait for ATA no-error timed-out\n");
++ }
++
++ /* Wait for DMA to finish */
++ if (!wait_dma_not_busy(device)) {
++ printf("Timed out of wait for DMA channel for SATA device %d to have in-progress clear\n", device);
++ }
++}
++
++static u32 scr_read(int device, unsigned int sc_reg)
++{
++ /* Setup adr of required register. std regs start eight into async region */
++ *(sata_regs_base[device] + SATA_LINK_RD_ADDR) = sc_reg*4 + SATA_STD_ASYNC_REGS_OFF;
++
++ /* Wait for data to be available */
++ int loops = MAX_SRC_READ_LOOPS;
++ do {
++ if (*(sata_regs_base[device] + SATA_LINK_CONTROL) & 1UL) {
++ break;
++ }
++ udelay(10);
++ } while (--loops);
++
++ if (!loops) {
++ printf("scr_read() Timed out of wait for read completion\n");
++ }
++
++ /* Read the data from the async register */
++ return *(sata_regs_base[device] + SATA_LINK_DATA);
++}
++
++static void scr_write(int device, unsigned int sc_reg, u32 val)
++{
++ /* Setup the data for the write */
++ *(sata_regs_base[device] + SATA_LINK_DATA) = val;
++
++ /* Setup adr of required register. std regs start eight into async region */
++ *(sata_regs_base[device] + SATA_LINK_WR_ADDR) = sc_reg*4 + SATA_STD_ASYNC_REGS_OFF;
++
++ /* Wait for data to be written */
++ int loops = MAX_SRC_WRITE_LOOPS;
++ do {
++ if (*(sata_regs_base[device] + SATA_LINK_CONTROL) & 1UL) {
++ break;
++ }
++ udelay(10);
++ } while (--loops);
++
++ if (!loops) {
++ printf("scr_write() Timed out of wait for write completion\n");
++ }
++}
++
++#define PHY_LOOP_COUNT 25 /* Wait for upto 5 seconds for PHY to be found */
++static int phy_reset(int device)
++{
++#ifdef FPGA
++ /* The FPGA thinks it can do 3G when infact only 1.5G is possible, so limit
++ it to Gen-1 SATA (1.5G) */
++ scr_write(device, SATA_SCR_CONTROL, 0x311); /* Issue phy wake & core reset */
++ scr_read(device, SATA_SCR_STATUS); /* Dummy read; flush */
++ udelay(1000);
++ scr_write(device, SATA_SCR_CONTROL, 0x310); /* Issue phy wake & clear core reset */
++#else
++ scr_write(device, SATA_SCR_CONTROL, 0x301); /* Issue phy wake & core reset */
++ scr_read(device, SATA_SCR_STATUS); /* Dummy read; flush */
++ udelay(1000);
++ scr_write(device, SATA_SCR_CONTROL, 0x300); /* Issue phy wake & clear core reset */
++#endif
++ /* Wait for upto 5 seconds for PHY to become ready */
++ int phy_status = 0;
++ int loops = 0;
++ do {
++ udelay(200000);
++ if ((scr_read(device, SATA_SCR_STATUS) & 0xf) != 1) {
++ phy_status = 1;
++ break;
++ }
++ printf("No SATA PHY found\n");
++ } while (++loops < PHY_LOOP_COUNT);
++
++ if (phy_status) {
++ udelay(500000); /* wait half a second */
++ }
++ return phy_status;
++}
++
++#define FIS_LOOP_COUNT 25 /* Wait for upto 5 seconds for FIS to be received */
++static int wait_FIS(int device)
++{
++ int status = 0;
++ int loops = 0;
++
++ do {
++ udelay(200000);
++ if (oxnas_sata_inb(device, ATA_PORT_NSECT) > 0) {
++ status = 1;
++ break;
++ }
++ } while (++loops < FIS_LOOP_COUNT);
++
++ return status;
++}
++
++int ide_preinit(void)
++{
++ int num_disks_found = 0;
++
++ /* Initialise records of which disks are present to all present */
++ int i;
++ for (i=0; i < CFG_IDE_MAXDEVICE; i++) {
++ disk_present[i] = 1;
++ }
++
++//udelay(1000000);
++ /* Enable clocks to SATA and DMA cores */
++ *(volatile u32*)SYS_CTRL_CKEN_SET_CTRL = (1UL << SYS_CTRL_CKEN_SATA_BIT);
++ *(volatile u32*)SYS_CTRL_CKEN_SET_CTRL = (1UL << SYS_CTRL_CKEN_DMA_BIT);
++
++ /* Block reset SATA and DMA cores */
++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL = (1UL << SYS_CTRL_RSTEN_SATA_BIT) |
++ (1UL << SYS_CTRL_RSTEN_SATA_LINK_BIT) |
++ (1UL << SYS_CTRL_RSTEN_SATA_PHY_BIT) |
++ (1UL << SYS_CTRL_RSTEN_DMA_BIT);
++ udelay(50);
++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_SATA_PHY_BIT);
++ udelay(50);
++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_SATA_LINK_BIT) |
++ (1UL << SYS_CTRL_RSTEN_SATA_BIT);
++ udelay(50);
++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_DMA_BIT);
++ udelay(50);
++//udelay(1000000);
++
++ /* disable and clear core interrupts */
++ *((unsigned long*)SATA_HOST_REGS_BASE + SATA_INT_ENABLE_CLR_OFF) = ~0UL;
++ *((unsigned long*)SATA_HOST_REGS_BASE + SATA_INT_CLR_OFF) = ~0UL;
++
++ int device;
++ for (device = 0; device < CFG_IDE_MAXDEVICE; device++) {
++ int found = 0;
++ int retries = 1;
++
++ /* Disable SATA interrupts */
++ *(sata_regs_base[device] + SATA_INT_ENABLE_CLR_OFF) = ~0UL;
++
++ /* Clear any pending SATA interrupts */
++ *(sata_regs_base[device] + SATA_INT_CLR_OFF) = ~0UL;
++
++ do {
++ /* clear sector count register for FIS detection */
++ oxnas_sata_outb(device, ATA_PORT_NSECT, 0);
++
++ /* Get the PHY working */
++ if (!phy_reset(device)) {
++ printf("SATA PHY not ready for device %d\n", device);
++ break;
++ }
++
++ if (!wait_FIS(device)) {
++ printf("No FIS received from device %d\n", device);
++ } else {
++ if ((scr_read(device, SATA_SCR_STATUS) & 0xf) == 0x3) {
++ if (wait_not_busy(device, 30)) {
++ printf("Timed out of wait for SATA device %d to have BUSY clear\n", device);
++ } else {
++ ++num_disks_found;
++ found = 1;
++ }
++ } else {
++ printf("No SATA device %d found, PHY status = 0x%08x\n",
++ device, scr_read(device, SATA_SCR_STATUS));
++ }
++ break;
++ }
++ } while (retries--) ;
++
++ /* Record whether disk is present, so won't attempt to access it later */
++ disk_present[device] = found;
++ }
++
++ /* post disk detection clean-up */
++ for (device = 0; device < CFG_IDE_MAXDEVICE; device++) {
++ if ( disk_present[device] ) {
++ /* set as ata-5 (28-bit) */
++ *(sata_regs_base[device] + SATA_DRIVE_CONTROL_OFF) = 0UL;
++
++ /* clear phy/link errors */
++ scr_write(device, SATA_SCR_ERROR, ~0);
++
++ /* clear host errors */
++ *(sata_regs_base[device] + SATA_CONTROL_OFF) |= SATA_SCTL_CLR_ERR;
++
++ /* clear interrupt register as this clears the error bit in the IDE
++ status register */
++ *(sata_regs_base[device] + SATA_INT_CLR_OFF) = ~0UL;
++ }
++ }
++
++
++ return !num_disks_found;
++}
++
+diff -Nurd u-boot-1.1.2/board/oxnas/Makefile u-boot-1.1.2-oxe810/board/oxnas/Makefile
+--- u-boot-1.1.2/board/oxnas/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-oxe810/board/oxnas/Makefile 2008-06-11 17:55:18.000000000 +0200
+@@ -0,0 +1,51 @@
++#
++# (C) Copyright 2000-2004
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# (C) Copyright 2004
++# ARM Ltd.
++# Philippe Robin, <philippe.robin@arm.com>
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = lib$(BOARD).a
++
++OBJS := oxnas.o eth.o ide-$(NAS_VERSION).o
++SOBJS := platform-$(NAS_VERSION).o
++
++$(LIB): $(OBJS) $(SOBJS)
++ $(AR) crv $@ $^
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
++
++-include .depend
++
++#########################################################################
+diff -Nurd u-boot-1.1.2/board/oxnas/oxnas.c u-boot-1.1.2-oxe810/board/oxnas/oxnas.c
+--- u-boot-1.1.2/board/oxnas/oxnas.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-oxe810/board/oxnas/oxnas.c 2008-06-11 17:55:18.000000000 +0200
+@@ -0,0 +1,280 @@
++/*
++ * (C) Copyright 2005
++ * Oxford Semiconductor Ltd
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++
++#if defined(CONFIG_SHOW_BOOT_PROGRESS)
++void show_boot_progress(int progress)
++{
++ printf("Boot reached stage %d\n", progress);
++}
++#endif
++
++static inline void delay(unsigned long loops)
++{
++ __asm__ volatile ("1:\n"
++ "subs %0, %1, #1\n"
++ "bne 1b":"=r" (loops):"0" (loops));
++}
++
++/*
++ * Miscellaneous platform dependent initialisations
++ */
++
++/** Expected Intel 28F320B3T CFI info */
++// mfr_id: MANUFACTURER_INTEL, -> 0x0089
++// dev_id: I28F320B3T, -> 0x8896
++// name: "Intel 28F320B3T",
++// DevSize: SIZE_4MiB, -> 22
++// CmdSet: P_ID_INTEL_STD, -> 0x0003
++// NumEraseRegions: 2,
++// regions: { -> #define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
++// ERASEINFO(0x10000, 63),
++// ERASEINFO(0x02000, 8),
++// }
++
++#define FLASH_WORD_SIZE unsigned short
++
++int board_init(void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ gd->bd->bi_arch_number = MACH_TYPE_OXNAS;
++ gd->bd->bi_boot_params = PHYS_SDRAM_1_PA + 0x100;
++ gd->flags = 0;
++
++ icache_enable();
++
++ /* Block reset Static core */
++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL = (1UL << SYS_CTRL_RSTEN_STATIC_BIT);
++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_STATIC_BIT);
++
++ /* Enable clock to Static core */
++ *(volatile u32*)SYS_CTRL_CKEN_SET_CTRL = (1UL << SYS_CTRL_CKEN_STATIC_BIT);
++
++#ifdef CONFIG_OXNAS_ENABLE_PCI
++ /* Block reset PCI core */
++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL = (1UL << SYS_CTRL_RSTEN_PCI_BIT);
++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_PCI_BIT);
++
++ /* Enable clock to PCI core */
++ *(volatile u32*)SYS_CTRL_CKEN_SET_CTRL = (1UL << SYS_CTRL_CKEN_PCI_BIT);
++#endif // CONFIG_OXNAS_ENABLE_PCI
++
++#ifdef CONFIG_OXNAS_MANUAL_STATIC_ARBITRATION
++ /* Assert manual static bus PCI arbitration request */
++ *(volatile u32*)SYS_CTRL_PCI_CTRL1 |= (1UL << SYS_CTRL_PCI_CTRL1_PCI_STATIC_RQ_BIT);
++#endif // CONFIG_OXNAS_MANUAL_STATIC_ARBITRATION
++
++#ifdef CONFIG_OXNAS_FEEDBACK_PCI_CLKS
++ /* Set PCI feedback clk GPIO pin as an output */
++ *(volatile u32*)GPIO_1_SET_OE |= 0x800;
++
++ /* Enable PCI feedback clk onto GPIO pin */
++ *(volatile u32*)SYS_CTRL_GPIO_PRIMSEL_CTRL_0 |= 0x00000800;
++#endif // CONFIG_OXNAS_FEEDBACK_PCI_CLKS
++
++#ifndef CFG_NO_FLASH
++ /* Enable static bus onto GPIOs, only CS0 as CS1 conflicts with UART2 */
++ *(volatile u32*)SYS_CTRL_GPIO_PRIMSEL_CTRL_0 |= 0x002FF000;
++
++ /* Setup the static bus CS0 to access FLASH */
++ *(volatile u32*)STATIC_CONTROL_BANK0 = STATIC_BUS_FLASH_CONFIG;
++#endif // !CFG_NO_FLASH
++
++ /* Set 33MHz PCI clock */
++ *(volatile u32*)SYS_CTRL_CKCTRL_CTRL_ADDR = 5;
++ /* Enable full speed RPS clock */
++ *(volatile u32*)SYS_CTRL_CKCTRL_CTRL_ADDR &= ~(1UL << SYS_CTRL_CKCTRL_SLOW_BIT);
++
++#if (USE_EXTERNAL_UART == 0)
++#ifdef CONFIG_OXNAS_UART1
++ /* Block reset UART1 */
++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL = (1UL << SYS_CTRL_RSTEN_UART1_BIT);
++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_UART1_BIT);
++
++ /* Setup pin mux'ing for first internal UART */
++ *(volatile u32*)SYS_CTRL_GPIO_PRIMSEL_CTRL_0 &= ~0x80000000;
++ *(volatile u32*)SYS_CTRL_GPIO_SECSEL_CTRL_0 &= ~0x80000000;
++ *(volatile u32*)SYS_CTRL_GPIO_TERTSEL_CTRL_0 |= 0x80000000; // Route UART1 SOUT onto external pins
++
++ *(volatile u32*)SYS_CTRL_GPIO_PRIMSEL_CTRL_1 &= ~0x00000001;
++ *(volatile u32*)SYS_CTRL_GPIO_SECSEL_CTRL_1 &= ~0x00000001;
++ *(volatile u32*)SYS_CTRL_GPIO_TERTSEL_CTRL_1 |= 0x00000001; // Route UART1 SIN onto external pins
++
++ *(volatile u32*)GPIO_1_SET_OE |= 0x80000000; // Make UART1 SOUT an o/p
++ *(volatile u32*)GPIO_2_CLR_OE |= 0x00000001; // Make UART1 SIN an i/p
++#endif // CONFIG_OXNAS_UART1
++
++#ifdef CONFIG_OXNAS_UART2
++ // Block reset UART2
++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL = (1UL << SYS_CTRL_RSTEN_UART2_BIT);
++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_UART2_BIT);
++
++ /* Setup pin mux'ing for second internal UART */
++ *(volatile u32*)SYS_CTRL_GPIO_PRIMSEL_CTRL_0 &= ~0x00500000;
++ *(volatile u32*)SYS_CTRL_GPIO_SECSEL_CTRL_0 &= ~0x00500000;
++ *(volatile u32*)SYS_CTRL_GPIO_TERTSEL_CTRL_0 |= 0x00500000; // Route UART2 SOUT and SIN onto external pins
++
++ *(volatile u32*)GPIO_1_SET_OE |= 0x00100000; // Make UART2 SOUT an o/p
++ *(volatile u32*)GPIO_1_CLR_OE |= 0x00400000; // Make UART2 SIN an i/p
++#endif // CONFIG_OXNAS_UART2
++
++#ifdef CONFIG_OXNAS_UART3
++ // Block reset UART3
++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL = (1UL << SYS_CTRL_RSTEN_UART3_BIT);
++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_UART3_BIT);
++
++ // Route UART3 SIN/SOUT onto external pin
++ *(volatile u32*)SYS_CTRL_GPIO_PRIMSEL_CTRL_0 &= ~0x000000C0;
++ *(volatile u32*)SYS_CTRL_GPIO_SECSEL_CTRL_0 &= ~0x000000C0;
++ *(volatile u32*)SYS_CTRL_GPIO_TERTSEL_CTRL_0 |= 0x000000C0;
++
++ // Setup GPIO line directions for UART3 SIN/SOUT
++ *(volatile u32*)GPIO_1_SET_OE |= 0x00000080;
++ *(volatile u32*)GPIO_1_CLR_OE |= 0x00000040;
++#endif // CONFIG_ARCH_OXNAS_UART3
++
++#ifdef CONFIG_OXNAS_UART4
++ // Block reset UART4
++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL = (1UL << SYS_CTRL_RSTEN_UART4_BIT);
++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_UART4_BIT);
++
++ // Enable UART4 to override PCI functions onto GPIOs
++ *(volatile u32*)SYS_CTRL_UART_CTRL |= (1UL << SYS_CTRL_UART4_NOT_PCI_MODE);
++#endif // CONFIG_OXNAS_UART4
++#endif // !USE_EXTERNAL_UART
++
++ return 0;
++}
++
++int board_late_init()
++{
++ return 0;
++}
++
++int misc_init_r(void)
++{
++ return 0;
++}
++
++int dram_init(void)
++{
++#ifdef PROBE_MEM_SIZE
++ /* Determine the amount of SDRAM the DDR controller is configured for */
++ volatile unsigned long * const ddr_config_reg_adr = (volatile unsigned long *)(0x45800000);
++ static const int DDR_SIZE_BIT = 17;
++ static const int DDR_SIZE_NUM_BITS = 4;
++ static const unsigned long DDR_SIZE_MASK = (((1UL << DDR_SIZE_NUM_BITS) - 1) << DDR_SIZE_BIT);
++
++ unsigned long ddr_config_reg = *ddr_config_reg_adr;
++ int ddr_size_pow2 = (ddr_config_reg & DDR_SIZE_MASK) >> DDR_SIZE_BIT;
++
++ DECLARE_GLOBAL_DATA_PTR;
++
++ gd->bd->bi_dram[0].size = (1 << ddr_size_pow2) * 1024 * 1024;
++
++ if ((gd->bd->bi_dram[0].size >> 20) == 256) {
++ /* Do we really have 256M, or are we working around the DDR controller's
++ * problem with 128M size? */
++ volatile unsigned long * const PROBE_ADR_1 = (volatile unsigned long * const)PHYS_SDRAM_1_PA;
++ volatile unsigned long * const PROBE_ADR_2 = (volatile unsigned long * const)(PHYS_SDRAM_1_PA + (128*1024*1024));
++ static const unsigned long PROBE_VAL_1 = 0xdeadbeef;
++ static const unsigned long PROBE_VAL_2 = 0x12345678;
++
++ *PROBE_ADR_1 = PROBE_VAL_1;
++ *PROBE_ADR_2 = PROBE_VAL_2;
++ if (*PROBE_ADR_1 != PROBE_VAL_1) {
++ gd->bd->bi_dram[0].size = 128*1024*1024;
++ }
++ }
++#else // PROBE_MEM_SIZE
++ gd->bd->bi_dram[0].size = MEM_SIZE;
++#endif // PROBE_MEM_SIZE
++
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1_PA;
++
++ gd->bd->bi_sramstart = CFG_SRAM_BASE;
++ gd->bd->bi_sramsize = CFG_SRAM_SIZE;
++
++ return 0;
++}
++
++int reset_cpu(void)
++{
++ printf("Resetting Oxsemi NAS...");
++
++ // Assert reset to cores as per power on defaults
++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL =
++ (1UL << SYS_CTRL_RSTEN_COPRO_BIT) |
++ (1UL << SYS_CTRL_RSTEN_USBHS_BIT) |
++ (1UL << SYS_CTRL_RSTEN_USBHSPHY_BIT) |
++ (1UL << SYS_CTRL_RSTEN_MAC_BIT) |
++ (1UL << SYS_CTRL_RSTEN_PCI_BIT) |
++ (1UL << SYS_CTRL_RSTEN_DMA_BIT) |
++ (1UL << SYS_CTRL_RSTEN_DPE_BIT) |
++ (1UL << SYS_CTRL_RSTEN_SATA_BIT) |
++ (1UL << SYS_CTRL_RSTEN_SATA_LINK_BIT) |
++ (1UL << SYS_CTRL_RSTEN_SATA_PHY_BIT) |
++ (1UL << SYS_CTRL_RSTEN_STATIC_BIT) |
++ (1UL << SYS_CTRL_RSTEN_UART1_BIT) |
++ (1UL << SYS_CTRL_RSTEN_UART2_BIT) |
++ (1UL << SYS_CTRL_RSTEN_MISC_BIT) |
++ (1UL << SYS_CTRL_RSTEN_I2S_BIT) |
++ (1UL << SYS_CTRL_RSTEN_AHB_MON_BIT) |
++ (1UL << SYS_CTRL_RSTEN_UART3_BIT) |
++ (1UL << SYS_CTRL_RSTEN_UART4_BIT) |
++ (1UL << SYS_CTRL_RSTEN_SGDMA_BIT);
++
++ // Release reset to cores as per power on defaults
++ *(volatile u32*)SYS_CTRL_RSTEN_CLR_CTRL = (1UL << SYS_CTRL_RSTEN_GPIO_BIT);
++
++ // Disable clocks to cores as per power-on defaults
++ *(volatile u32*)SYS_CTRL_CKEN_CLR_CTRL =
++ (1UL << SYS_CTRL_CKEN_COPRO_BIT) |
++ (1UL << SYS_CTRL_CKEN_DMA_BIT) |
++ (1UL << SYS_CTRL_CKEN_DPE_BIT) |
++ (1UL << SYS_CTRL_CKEN_SATA_BIT) |
++ (1UL << SYS_CTRL_CKEN_I2S_BIT) |
++ (1UL << SYS_CTRL_CKEN_USBHS_BIT) |
++ (1UL << SYS_CTRL_CKEN_MAC_BIT) |
++ (1UL << SYS_CTRL_CKEN_STATIC_BIT);
++
++ // Enable clocks to cores as per power-on defaults
++ *(volatile u32*)SYS_CTRL_CKEN_SET_CTRL = (1UL << SYS_CTRL_CKEN_PCI_BIT);
++
++ // Set sys-control pin mux'ing as per power-on defaults
++ *(volatile u32*)SYS_CTRL_GPIO_PRIMSEL_CTRL_0 = 0x800UL;
++ *(volatile u32*)SYS_CTRL_GPIO_PRIMSEL_CTRL_1 = 0x0UL;
++ *(volatile u32*)SYS_CTRL_GPIO_SECSEL_CTRL_0 = 0x0UL;
++ *(volatile u32*)SYS_CTRL_GPIO_SECSEL_CTRL_1 = 0x0UL;
++ *(volatile u32*)SYS_CTRL_GPIO_TERTSEL_CTRL_0 = 0x0UL;
++ *(volatile u32*)SYS_CTRL_GPIO_TERTSEL_CTRL_1 = 0x0UL;
++
++ // No need to save any state, as the ROM loader can determine whether reset
++ // is due to power cycling or programatic action, just hit the (self-
++ // clearing) CPU reset bit of the block reset register
++ *(volatile u32*)SYS_CTRL_RSTEN_SET_CTRL = (1UL << SYS_CTRL_RSTEN_ARM_BIT);
++
++ return 0;
++}
+diff -Nurd u-boot-1.1.2/board/oxnas/platform-800.S u-boot-1.1.2-oxe810/board/oxnas/platform-800.S
+--- u-boot-1.1.2/board/oxnas/platform-800.S 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-oxe810/board/oxnas/platform-800.S 2008-06-11 17:55:18.000000000 +0200
+@@ -0,0 +1,254 @@
++/*
++ * Board specific setup info
++ *
++ * (C) Copyright 2005
++ * Oxford Semiconductor Ltd
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <config.h>
++#include <version.h>
++
++/* use estimate of processor speed to calculate number of cycles delay */
++/* delay count is nominal (PLL200 frequency x delay time) / loop count
++ * expressing 200us as 200/1000000 and re-arranging gives the expression below
++ */
++
++#define DELAY_200US ((NOMINAL_ARMCLK / (5 * 1000000)) * 200)
++/* this is 8 cycles of ? so choose 8 resulting in 40 cycles */
++#define DELAY_1S ((DELAY_200US) * 5000)
++#define DELAY_8 8
++#define DELAY_200 200
++
++.globl platformsetup
++platformsetup:
++/* register allocations
++ * r0 - delay counter and scratch
++ * r1 - address register
++ * r2 - data register
++ * r3 - index to table pointer
++ * r4 - iteration counter.
++ *
++ * r5 - hold return address.
++ * lr - (R14) link register
++ * pc - (R15) program counter.
++ */
++
++#ifdef INITIALISE_SDRAM
++/*
++ * Check that not in SDRAM execution. Suicide if re-initialise DRAM.
++ * Controller function is linked to execute in SDRAM must be in ROM if not
++ * there. Check for wrong place.
++ */
++ adrl r0, platformsetup /* Relative location of function start.*/
++ ldr r1, _platformsetup
++ cmp r0, r1
++ moveq pc, lr
++#else
++ mov pc, lr
++#endif
++
++ /* Establish a working setup for the SDRAM */
++ mov r6, lr
++
++#ifdef OXNAS_OVERCLOCK
++ /* Delay so the broken JTAG can get control */
++ ldr r0, =DELAY_1S
++ bl delay
++
++ /* Configure the PLL to run faster */
++ ldr r1, =SYS_CTRL_PLLSYS_CTRL
++ ldr r2, =SYS_CTRL_PLLSYS_KEY_CTRL
++
++ /* 0xBEADFACE -> PLL_KEY */
++ /* Bypass PLL */
++ ldr r3, [r1]
++ ldr r5, =0x20000
++ orr r3, r3, r5
++ ldr r4, =0xbeadface
++ str r4, [r2]
++ str r3, [r1]
++
++ /* 0xBEADFACE -> PLL_KEY */
++ /* Set m,p and s for PLL at 400MHz */
++ ldr r5, =0xffff0000
++ and r3, r3, r5
++ ldr r5, =OXNAS_OVERCLOCK
++ orr r3, r3, r5
++ str r4, [r2]
++ str r3, [r1]
++
++ /* Wait at least 300uS */
++ ldr r0, =DELAY_200US
++ bl delay
++ ldr r0, =DELAY_200US
++ bl delay
++
++ /* 0xBEADFACE -> PLL_KEY */
++ /* Disable PLL bypass */
++ ldr r5, =0xfffdffff
++ and r3, r3, r5
++ str r4, [r2]
++ str r3, [r1]
++#endif // OXNAS_OVERCLOCK
++
++ /* Assert reset to the DDR core */
++ ldr r0, =SYS_CTRL_RSTEN_SET_CTRL
++ ldr r1, =1
++ ldr r2, =SYS_CTRL_RSTEN_DDR_BIT
++ mov r1, r1, LSL r2
++ str r1, [r0]
++
++ /* Deassert reset to the DDR core */
++ ldr r0, =SYS_CTRL_RSTEN_CLR_CTRL
++ str r1, [r0]
++
++ /* Turn on the DDR core clock */
++ ldr r0, =SYS_CTRL_CKEN_SET_CTRL
++ ldr r1, =1
++ ldr r2, =SYS_CTRL_CKEN_DDR_BIT
++ mov r1, r1, LSL r2
++ str r1, [r0]
++
++ /* Start using the initialisation value list */
++ adrl r3, init_table
++
++ /* Copy next 6 entries from DDR init table*/
++ ldr r4, =6
++loop0:
++ ldmia r3!, {r1, r2}
++ str r2, [r1]
++ subs r4, r4, #1
++ bne loop0
++
++ /* Delay for 200uS while DRAM controller stabilises. */
++ ldr r0, =DELAY_200US
++ bl delay
++
++#if !TEST_BRD
++ /* Copy next entry */
++ ldr r4, =1
++loopx:
++ ldmia r3!, {r1, r2}
++ str r2, [r1]
++ subs r4, r4, #1
++ bne loopx
++
++ /* Delay for 200uS while DRAM controller stabilises. */
++ ldr r0, =DELAY_200US
++ bl delay
++#endif // TEST_BRD
++
++ /* Copy next entry */
++ ldr r4, =1
++loop1:
++ ldmia r3!, {r1, r2}
++ str r2, [r1]
++ subs r4, r4, #1
++ bne loop1
++
++ /* Delay for 200uS while DRAM controller stabilises. */
++ ldr r0, =DELAY_200US
++ bl delay
++
++ /* Copy next entry */
++ ldr r4, =1
++loop2:
++ ldmia r3!, {r1, r2}
++ str r2, [r1]
++ subs r4, r4, #1
++ bne loop2
++
++ /* Delay for 200uS while DRAM controller stabilises. */
++ ldr r0, =DELAY_200US
++ bl delay
++
++ /* Copy next entry */
++ ldr r4, =1
++loop3:
++ ldmia r3!, {r1, r2}
++ str r2, [r1]
++ subs r4, r4, #1
++ bne loop3
++
++ /* Delay for 200uS while DRAM controller stabilises. */
++ ldr r0, =DELAY_200US
++ bl delay
++
++ /* Copy next 5 entries */
++ ldr r4, =5
++loop4:
++ ldmia r3!, {r1, r2}
++ str r2, [r1]
++ subs r4, r4, #1
++ bne loop4
++
++ /* SDRAM initialised so now exit. */
++ mov lr, r6
++ mov pc, lr
++
++/*
++ * delay()
++ *
++ * uses 1 + r0 * 5 cycles
++ */
++delay:
++ nop
++ nop
++ nop
++ subs r0, r0, #1
++ bne delay
++ mov pc, lr
++
++_platformsetup:
++ .word platformsetup
++
++init_table:
++ /* Table of address, data for loading into the DRAM controller */
++ /* Configure for a single DDR device */
++ .word 0x4500002C, 0x08
++ .word 0x45000038, 0x400
++ .word 0x45800000, 0x80100000
++ .word 0x45800004, 0x8000ffff // Enable DDR core and all clients
++ .word 0x45800024, 0x1e4
++ .word 0x45800014, 0xe0000001 // DLL to automatic with starting value=1
++/* 200uS delay */
++#if !TEST_BRD
++ .word 0x45800014, 0xa0000003 // DLL to automatic with offset value=3
++/* 200uS delay */
++#endif // TEST_BRD
++#if (MEM_SIZE == 32)
++ .word 0x45800000, 0x801B030C
++#else
++ .word 0x45800000, 0x801D030C
++#endif // MEM_SIZE
++/* 200uS delay */
++ .word 0x4580000c, 0x80280400
++/* 200uS delay */
++ .word 0x4580000c, 0x80210000
++/* 200uS delay */
++ .word 0x4580000c, 0x80200063
++ .word 0x45800028, 0x0000001f // Enable all arbiter features
++ .word 0x45800018, 0x00000000 // Disable all monitoring
++ .word 0x45800010, 0xffffffff // Disable all read buffering, due to h/w bug
++ .word 0x4580002C, 0x00000000 // Do NOT disable HPROT, ie want write coherency
++
++.ltorg
++
+diff -Nurd u-boot-1.1.2/board/oxnas/platform-810.S u-boot-1.1.2-oxe810/board/oxnas/platform-810.S
+--- u-boot-1.1.2/board/oxnas/platform-810.S 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-oxe810/board/oxnas/platform-810.S 2008-06-11 17:55:18.000000000 +0200
+@@ -0,0 +1,477 @@
++/*
++ * Board specific setup info
++ *
++ * (C) Copyright 2005
++ * Oxford Semiconductor Ltd
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <config.h>
++#include <version.h>
++
++/* use estimate of processor speed to calculate number of cycles delay */
++/* delay count is nominal (PLL200 frequency x delay time) / loop count
++ * expressing 200us as 200/1000000 and re-arranging gives the expression below
++ */
++
++#define DELAY_200US ((NOMINAL_ARMCLK / (5 * 1000000)) * 200)
++#define DELAY_300US ((NOMINAL_ARMCLK / (5 * 1000000)) * 300)
++/* this is 8 cycles of ? so choose 8 resulting in 40 cycles */
++#define DELAY_1S ((DELAY_200US) * 5000)
++#define DELAY_8 8
++#define DELAY_200 200
++
++
++.globl platformsetup
++platformsetup:
++/* register allocations
++ * r0 - delay counter and scratch
++ * r1 - address register
++ * r2 - data register
++ * r3 - index to table pointer
++ * r4 - iteration counter.
++ *
++ * r5 - hold return address.
++ * lr - (R14) link register
++ * pc - (R15) program counter.
++ */
++
++#ifdef INITIALISE_SDRAM
++/*
++ * Check that not in SDRAM execution. Suicide if re-initialise DRAM.
++ * Controller function is linked to execute in SDRAM must be in ROM if not
++ * there. Check for wrong place.
++ */
++ adrl r0, platformsetup /* Relative location of function start.*/
++ ldr r1, _platformsetup
++ cmp r0, r1
++ moveq pc, lr
++#else
++ mov pc, lr
++#endif
++
++#if (FPGA == 1)
++ /* Establish a working setup for the SDRAM */
++ mov r6, lr
++
++ /* Assert reset to the DDR core */
++ ldr r0, =SYS_CTRL_RSTEN_SET_CTRL
++ ldr r1, =1
++ ldr r2, =SYS_CTRL_RSTEN_DDR_BIT
++ mov r1, r1, LSL r2
++ str r1, [r0]
++
++ /* Deassert reset to the DDR core */
++ ldr r0, =SYS_CTRL_RSTEN_CLR_CTRL
++ str r1, [r0]
++
++ /* Turn on the DDR core clock */
++ ldr r0, =SYS_CTRL_CKEN_SET_CTRL
++ ldr r1, =1
++ ldr r2, =SYS_CTRL_CKEN_DDR_BIT
++ mov r1, r1, LSL r2
++ str r1, [r0]
++
++ /* Start using the initialisation value list */
++ adrl r3, init_table
++
++ /* Copy first 6 entries */
++ ldr r4, =6
++loop0:
++ ldmia r3!, {r1, r2}
++ str r2, [r1]
++ subs r4, r4, #1
++ bne loop0
++
++ /* Delay for 200uS while DRAM controller stabilises. */
++ ldr r0, =DELAY_200US
++ bl delay
++
++ /* Copy next 4 entries */
++ ldr r4, =4
++loop1:
++ ldmia r3!, {r1, r2}
++ str r2, [r1]
++ subs r4, r4, #1
++ bne loop1
++
++ /* Wait at least 200 clock cycles. */
++ ldr r0, =DELAY_200
++ bl delay
++
++ /* Copy next 2 entries */
++ ldr r4, =2
++loop2:
++ ldmia r3!, {r1, r2}
++ str r2, [r1]
++ subs r4, r4, #1
++ bne loop2
++
++ /* Wait at least 8 clock cycles. */
++ ldr r0, =DELAY_8
++ bl delay
++
++ /* Copy next 9 entries */
++ ldr r4, =9
++loop3:
++ ldmia r3!, {r1, r2}
++ str r2, [r1]
++ subs r4, r4, #1
++ bne loop3
++
++ /* SDRAM initialised so now exit. */
++ mov lr, r6
++ mov pc, lr
++
++/*
++ * delay()
++ *
++ * uses 1 + r0 * 5 cycles
++ */
++delay:
++ nop
++ nop
++ nop
++ subs r0, r0, #1
++ bne delay
++ mov pc, lr
++
++_platformsetup:
++ .word platformsetup
++#else // ASIC, (DDR-2)
++/*
++ * Check that not in SDRAM execution. Suicide if re-initialise DRAM.
++ * Controller function is linked to execute in SDRAM must be in ROM if not
++ * there. Check for wrong place.
++ */
++ /* Establish a working setup for the SDRAM */
++ mov r6, lr
++
++#ifdef OVERCLOCK
++ /*
++ change clock speed on chip
++ */
++
++ /* read SYS_CTRL_PLLSYS_CTRL into r3*/
++ mov r5, #0x45000000
++ ldr r3, [r5, #72]
++
++ /* load the value at dllkey (0xbeadface) into r7 */
++ adrl r7, dllkey
++ ldr r7, [r7]
++
++ /* pll_sys |= 0x20000; */
++ orr r3, r3, #131072 /* 0x20000 */
++
++ /* write 0xbeadface into SYS_CTRL_PLLSYS_KEY_CTRL */
++ str r7, [r5, #108]
++
++ /* write pll_sys (bypass pll)*/
++ str r3, [r5, #72]
++
++ /* pll_sys &= 0xff000000; */
++ mov r4, r3, lsr #16
++ mov r4, r4, lsl #16
++
++ /* pll_sys |= 0x00F00061 */
++ orr r4, r4, #15728640 /* 0xf00000 */
++ orr r4, r4, #97 /* 0x61 */
++#if 0
++ orr r4, r4, #7864320 /* 0x780000 */
++ orr r4, r4, #96 /* 0x60 */
++#endif
++
++ /* write 0xbeadface into SYS_CTRL_PLLSYS_KEY_CTRL */
++ str r7, [r5, #108]
++
++ /* write pll_sys (with new pll speeds) */
++ str r4, [r5, #72]
++
++ /* delay 300us */
++ ldr r0, =DELAY_300US
++ bl delay
++
++ /* clear bypass pll bit */
++ bic r4, r4, #131072 /* 0x20000 */
++
++ /* write 0xbeadface into SYS_CTRL_PLLSYS_KEY_CTRL */
++ str r7, [r5, #108]
++
++ /* write pll_sys (with new pll speeds and pll un-bypassed) */
++ str r4, [r5, #72]
++#endif /* OVERCLOCK */
++
++ /* Turn on the DDR core and phy clocks */
++ ldr r0, =SYS_CTRL_CKEN_SET_CTRL
++ ldr r1, =1
++ ldr r2, =SYS_CTRL_CKEN_DDR_BIT
++ mov r1, r1, LSL r2
++ str r1, [r0]
++ ldr r1, =1
++ ldr r2, =SYS_CTRL_CKEN_DDR_PHY_BIT
++ mov r1, r1, LSL r2
++ str r1, [r0]
++
++ /* Assert reset to the DDR core and phy */
++ ldr r0, =SYS_CTRL_RSTEN_SET_CTRL
++ ldr r1, =1
++ ldr r2, =SYS_CTRL_RSTEN_DDR_PHY_BIT
++ mov r1, r1, LSL r2
++ str r1, [r0]
++ ldr r1, =1
++ ldr r2, =SYS_CTRL_RSTEN_DDR_BIT
++ mov r1, r1, LSL r2
++ str r1, [r0]
++
++ /* Deassert reset to the DDR core and phy*/
++ ldr r0, =SYS_CTRL_RSTEN_CLR_CTRL
++ ldr r1, =1
++ ldr r2, =SYS_CTRL_RSTEN_DDR_PHY_BIT
++ mov r1, r1, LSL r2
++ str r1, [r0]
++ ldr r1, =1
++ ldr r2, =SYS_CTRL_RSTEN_DDR_BIT
++ mov r1, r1, LSL r2
++ str r1, [r0]
++
++ /* Start using the initialisation value list */
++ adrl r3, init_table
++
++ /* Copy first 14 entries of DDR core setup (section A)*/
++ ldr r4, =14
++loop0:
++ ldmia r3!, {r1, r2}
++ str r2, [r1]
++ subs r4, r4, #1
++ bne loop0
++
++ /* Delay for 200uS while DDR controller stabilises. */
++ ldr r0, =DELAY_200US
++ bl delay
++
++ /* Copy next 13 entries of DDR device commands (section B)*/
++ ldr r4, =13
++loop1:
++ ldmia r3!, {r1, r2}
++ str r2, [r1]
++
++ /* Wait at least 200 clock cycles between ram chip command writes */
++ ldr r0, =DELAY_200
++ bl delay
++
++ subs r4, r4, #1
++ bne loop1
++
++ /* Copy final DDR controller setup to set memory size/banks (section C)*/
++ ldmia r3!, {r1, r2}
++ str r2, [r1]
++
++#if (PROBE_MEM_SIZE == 1)
++ /* Load the probe values into SDRAM */
++ adrl r3, probe_table
++ mov r4, #4
++.globl pl1
++pl1:
++ ldmia r3!, {r1, r2}
++ str r2, [r1]
++ subs r4, r4, #1
++ bne pl1
++
++ /* Get the current contents of the DDR controller core's config register */
++ adrl r1, ddr_config_reg
++ ldr r1, [r1]
++ ldr r1, [r1]
++
++ /* Zero the number of banks field - bit 23*/
++ mov r2, #1
++ bic r1, r1, r2, lsl #23
++
++ /* Zero the size field - bits 17-20 inclusive */
++ mov r2, #15
++ bic r1, r1, r2, lsl #17
++
++ /* First probe location tells us the SDRAM size */
++ adrl r3, probe_table
++ ldr r0, [r3]
++ ldr r0, [r0]
++
++ /* Is size 64MB? */
++ ldr r2, [r3, #28] /* Get probe value 4 */
++ cmp r0, r2
++ moveq r4, #6
++ orreq r1, r1, r4, lsl #17
++ beq pl2
++
++ /* Is 128M or 256M so set banks to 8 */
++ mov r4, #1
++ orr r1, r1, r4, lsl #23
++
++ /* Is size 128MB? */
++ ldr r2, [r3, #20] /* Get probe value 3 */
++ cmp r0, r2
++// moveq r4, #7
++ moveq r4, #8 /* DDR controller does not work at 128M, use 256M instead
++ orreq r1, r1, r4, lsl #17
++ beq pl2
++
++ /* Must be 256MB, or something is very wrong */
++ mov r4, #8
++ orr r1, r1, r4, lsl #17
++
++pl2:
++ /* Write the revised contents to the DDR controller core's config register */
++ adrl r2, ddr_config_reg
++ ldr r2, [r2]
++ str r1, [r2]
++#endif
++
++ /* SDRAM setup complete */
++ mov lr, r6
++ mov pc, lr
++
++/*
++ * delay()
++ *
++ * uses 1 + r0 * 5 cycles
++ */
++delay:
++ nop
++ nop
++ nop
++ subs r0, r0, #1
++ bne delay
++ mov pc, lr
++
++_platformsetup:
++ .word platformsetup
++#endif
++
++
++init_table:
++#if (FPGA == 1)
++ /* Table of address, data for loading into the DRAM controller on FPGA */
++ .word 0x45800000, 0x000d0000 // Enable the DDR in SDR mode and width 32 bits
++ .word 0x45800034, 0x04442032 // SDR mode timings - #0
++ .word 0x45800038, 0x570A0907 // SDR mode timings - #1
++ .word 0x4580003C, 0x00000002 // SDR mode timings - #2
++ .word 0x45800004, 0x80000000 // Enable DDR core, but not clients yet
++ .word 0x45800014, 0x80000001 // Enable CK and set DLL mode to manual
++/* 200uS delay */
++ .word 0x4580000c, 0x80200000 // Assert CKE for all further commands
++ .word 0x4580000c, 0x80280400 // Issue precharge to all banks
++ .word 0x4580000c, 0x80200000 // NOP, as only DDR has real command here
++ .word 0x4580000c, 0x80200022 // Set burst length 4, sequential CAS 2
++/* 200uS delay */
++ .word 0x4580000c, 0x80280400 // Issue precharge to all banks
++ .word 0x4580000c, 0x80240000 // Issue auto-refresh command, CKE not asserted
++/* 200uS delay */
++ .word 0x4580000c, 0x80240000 // Issue auto-refresh command, CKE not asserted
++ .word 0x4580000c, 0x80200000 // Assert CKE for all further commands
++ .word 0x4580000c, 0x80200022 // Set burst length 4, sequential CAS 2
++ .word 0x45800000, 0x000d0186 // SDR, size and width and refresh rate, assuming
++ // 25Mhz clk to SDR, divide down to get 15.625uS
++ // refresh rate
++ .word 0x45800024, 0x00000124 // Set I/O drive strengths
++ .word 0x45800028, 0x0000001f // Enable all arbiter features
++ .word 0x45800018, 0x00000000 // Disable all monitoring
++ .word 0x45800010, 0xFFFFFFFF // Disable all read buffering
++ .word 0x45800004, 0x800000ff // Enable all client interfaces
++#else // ASIC DDR-2
++ // SECTION A - DDR controller core configuration
++ .word 0x45800000, 0x802d0591 // enable in ddr-2 mode 16 bit wide
++ .word 0x45800034, 0x04442032 // ddr-2 mode timings
++ .word 0x45800038, 0x870f0b25 // ddr-2 mode timings
++ .word 0x4580003c, 0x00000a23 // ddr-2 mode timings
++ .word 0x45800054, 0x00072000 // phy-3 settings
++ .word 0x45800050, 0x00022828 // phy-2 settings, start
++ .word 0x45800050, 0x00032828 // phy-2 settings, on
++ .word 0x45800028, 0x0000001f // Enable all arbiter features
++ .word 0x45800018, 0x00000000 // Disable all monitoring
++ .word 0x45800010, 0xffff0000 // Enable all read buffering
++ .word 0x4580002c, 0x00ff00fd // no burst accl, no hprot on arm data
++ .word 0x45800040, 0x00000000 // enable burst and read cache
++ .word 0x45800044, 0xffff0000 // enable write behind prot, disable timeout
++ .word 0x45800004, 0x8000ffff // Enable all client interfaces
++/* 200uS delay after configuring DDR controller core */
++
++ // SECTION B - Memory device configuration
++ .word 0x4580000c, 0x807c0000 // exit something or other
++ .word 0x4580000c, 0x803c0000 // nop - wake up
++ .word 0x4580000c, 0x80280400 // precharge all
++ .word 0x4580000c, 0x80220000 // emr2
++ .word 0x4580000c, 0x80230000 // emr3
++
++#if (MEM_ODT == 150)
++ .word 0x4580000c, 0x80210042 // enable dll, odt to 150
++#elif (MEM_ODT == 75)
++ .word 0x4580000c, 0x80210006 // enable dll, odt to 75
++#elif (MEM_ODT == 50)
++ .word 0x4580000c, 0x80210046 // enable dll, odt to 50
++#else
++#error Unsupported memory on-die termination, set MEM_ODT to 50, 75, or 150
++#endif
++
++ .word 0x4580000c, 0x80200733 // set WR CL BL and reset dll
++ .word 0x4580000c, 0x80280400 // precharge all
++ .word 0x4580000c, 0x80240000 // auto refresh
++ .word 0x4580000c, 0x80240000 // auto refresh
++ .word 0x4580000c, 0x80200733 // set WR CL BL and reset dll
++
++#if (MEM_ODT == 150)
++ .word 0x4580000c, 0x802103c2 // enable OCD
++ .word 0x4580000c, 0x80210042 // disable OCD
++#elif (MEM_ODT == 75)
++ .word 0x4580000c, 0x80210386 // enable OCD
++ .word 0x4580000c, 0x80210006 // disable OCD
++#elif (MEM_ODT == 50)
++ .word 0x4580000c, 0x802103c6 // enable OCD
++ .word 0x4580000c, 0x80210046 // disable OCD
++#else
++#error Unsupported memory on-die termination, set MEM_ODT to 50, 75, or 150
++#endif
++
++ // SECTION C - Final memory size/bank configuration
++#if (PROBE_MEM_SIZE == 1)
++ .word 0x45800000, 0x80b10591 // 256M, 8 banks, 1425 clocks for 7.8us refresh.
++#elif (MEM_SIZE == 64)
++ .word 0x45800000, 0x802d0591 // 64M, 4 banks, 1425 clocks for 7.8us refresh.
++#elif (MEM_SIZE == 128)
++ .word 0x45800000, 0x80af0591 // 128M, 8 banks, 1425 clocks for 7.8us refresh.
++#elif (MEM_SIZE == 256)
++ .word 0x45800000, 0x80b10591 // 256M, 8 banks, 1425 clocks for 7.8us refresh.
++#else
++#error Unsupported memory size, set MEM_SIZE to 64, 128 or 256
++#endif
++
++#endif // FPGA or ASIC
++dllkey:
++ .word 0xbeadface
++
++ddr_config_reg:
++ .word 0x45800000
++
++probe_table:
++ .word 0x48000000, 0x12345678
++ .word 0x48000040, 0xdeadbeef
++ .word 0x50000000, 0xfafafafa
++ .word 0x50000040, 0xabcdef01
++
++.ltorg
++
+diff -Nurd u-boot-1.1.2/board/oxnas/u-boot.lds u-boot-1.1.2-oxe810/board/oxnas/u-boot.lds
+--- u-boot-1.1.2/board/oxnas/u-boot.lds 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-oxe810/board/oxnas/u-boot.lds 2008-06-11 17:55:18.000000000 +0200
+@@ -0,0 +1,50 @@
++/*
++ * (C) Copyright 2002
++ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++ . = 0x00000000;
++ . = ALIGN(4);
++ .text :
++ {
++ cpu/arm926ejs/start.o (.text)
++ *(.text)
++ }
++ .rodata : { *(.rodata) }
++ . = ALIGN(4);
++ .data : { *(.data) }
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
+diff -Nurd u-boot-1.1.2/common/cmd_ext2.c u-boot-1.1.2-oxe810/common/cmd_ext2.c
+--- u-boot-1.1.2/common/cmd_ext2.c 2004-12-16 18:34:53.000000000 +0100
++++ u-boot-1.1.2-oxe810/common/cmd_ext2.c 2008-06-11 17:55:30.000000000 +0200
+@@ -223,7 +223,7 @@
+ PRINTF("Using device %s%d, partition %d\n", argv[1], dev, part);
+
+ if (part != 0) {
+- if (get_partition_info (&dev_desc[dev], part, &info)) {
++ if (get_partition_info (dev_desc, part, &info)) {
+ printf ("** Bad partition %d **\n", part);
+ return(1);
+ }
+diff -Nurd u-boot-1.1.2/common/cmd_ide.c u-boot-1.1.2-oxe810/common/cmd_ide.c
+--- u-boot-1.1.2/common/cmd_ide.c 2004-12-31 10:32:50.000000000 +0100
++++ u-boot-1.1.2-oxe810/common/cmd_ide.c 2008-06-11 17:55:30.000000000 +0200
+@@ -193,6 +193,13 @@
+ static void set_pcmcia_timing (int pmode);
+ #endif
+
++#ifdef CONFIG_OXNAS
++extern unsigned char oxnas_sata_inb(int dev, int port);
++extern void oxnas_sata_outb(int dev, int port, unsigned char val);
++extern void oxnas_sata_output_data(int dev, ulong *sect_buf, int words);
++extern void oxnas_sata_input_data(int dev, ulong *sect_buf, int words);
++#endif // CONFIG_OXNAS
++
+ /* ------------------------------------------------------------------------- */
+
+ int do_ide (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+@@ -491,175 +498,103 @@
+ return rcode;
+ }
+
+-/* ------------------------------------------------------------------------- */
+
+-void ide_init (void)
++static int ide_probe(int device)
+ {
++ int found = 0;
++
++ /* Select device */
++ udelay(100000); /* 100 ms */
++ ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device));
++ udelay(100000); /* 100 ms */
+
+-#ifdef CONFIG_IDE_8xx_DIRECT
+- DECLARE_GLOBAL_DATA_PTR;
+- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+- volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia);
+-#endif
+ unsigned char c;
+- int i, bus;
+-#ifdef CONFIG_AMIGAONEG3SE
+- unsigned int max_bus_scan;
+- unsigned int ata_reset_time;
+- char *s;
++ int i = 0;
++ do {
++ udelay(10000); /* 10 ms */
++
++ c = ide_inb(device, ATA_STATUS);
++ if (++i > (ATA_RESET_TIME * 100)) {
++ PRINTF("ide_probe() timeout\n");
++ ide_led((LED_IDE1 | LED_IDE2), 0); /* LED's off */
++ return found;
++ }
++ if ((i >= 100) && ((i%100) == 0)) {
++ putc ('.');
++ }
++ } while (c & ATA_STAT_BUSY);
++
++ if (c & (ATA_STAT_BUSY | ATA_STAT_FAULT)) {
++ PRINTF("ide_probe() status = 0x%02X ", c);
++#ifndef CONFIG_ATAPI /* ATAPI Devices do not set DRDY */
++ } else if ((c & ATA_STAT_READY) == 0) {
++ PRINTF("ide_probe() status = 0x%02X ", c);
+ #endif
+-#ifdef CONFIG_IDE_8xx_PCCARD
+- extern int pcmcia_on (void);
+- extern int ide_devices_found; /* Initialized in check_ide_device() */
+-#endif /* CONFIG_IDE_8xx_PCCARD */
++ } else {
++ found = 1;
++ }
+
+-#ifdef CONFIG_IDE_PREINIT
+- extern int ide_preinit (void);
+- WATCHDOG_RESET();
++ return found;
++}
+
+- if (ide_preinit ()) {
+- puts ("ide_preinit failed\n");
++void ide_init(void)
++{
++ static int ide_init_called = 0;
++ int i, bus;
++
++ if (ide_init_called) {
+ return;
+ }
+-#endif /* CONFIG_IDE_PREINIT */
+-
+-#ifdef CONFIG_IDE_8xx_PCCARD
+- extern int pcmcia_on (void);
+- extern int ide_devices_found; /* Initialized in check_ide_device() */
++ ide_init_called = 1;
+
++#ifdef CONFIG_IDE_PREINIT
++ extern int ide_preinit(void);
+ WATCHDOG_RESET();
+
+- ide_devices_found = 0;
+- /* initialize the PCMCIA IDE adapter card */
+- pcmcia_on();
+- if (!ide_devices_found)
++ printf("Initialising disks\n");
++ if (ide_preinit()) {
++ puts ("ide_preinit failed\n");
+ return;
+- udelay (1000000); /* 1 s */
+-#endif /* CONFIG_IDE_8xx_PCCARD */
++ }
++#endif /* CONFIG_IDE_PREINIT */
+
+ WATCHDOG_RESET();
+
+-#ifdef CONFIG_IDE_8xx_DIRECT
+- /* Initialize PIO timing tables */
+- for (i=0; i <= IDE_MAX_PIO_MODE; ++i) {
+- pio_config_clk[i].t_setup = PCMCIA_MK_CLKS(pio_config_ns[i].t_setup,
+- gd->bus_clk);
+- pio_config_clk[i].t_length = PCMCIA_MK_CLKS(pio_config_ns[i].t_length,
+- gd->bus_clk);
+- pio_config_clk[i].t_hold = PCMCIA_MK_CLKS(pio_config_ns[i].t_hold,
+- gd->bus_clk);
+- PRINTF ("PIO Mode %d: setup=%2d ns/%d clk"
+- " len=%3d ns/%d clk"
+- " hold=%2d ns/%d clk\n",
+- i,
+- pio_config_ns[i].t_setup, pio_config_clk[i].t_setup,
+- pio_config_ns[i].t_length, pio_config_clk[i].t_length,
+- pio_config_ns[i].t_hold, pio_config_clk[i].t_hold);
+- }
+-#endif /* CONFIG_IDE_8xx_DIRECT */
+-
+ /* Reset the IDE just to be sure.
+ * Light LED's to show
+ */
+- ide_led ((LED_IDE1 | LED_IDE2), 1); /* LED's on */
+- ide_reset (); /* ATAPI Drives seems to need a proper IDE Reset */
+-
+-#ifdef CONFIG_IDE_8xx_DIRECT
+- /* PCMCIA / IDE initialization for common mem space */
+- pcmp->pcmc_pgcrb = 0;
+-
+- /* start in PIO mode 0 - most relaxed timings */
+- pio_mode = 0;
+- set_pcmcia_timing (pio_mode);
+-#endif /* CONFIG_IDE_8xx_DIRECT */
++ ide_led((LED_IDE1 | LED_IDE2), 1); /* LED's on */
++ ide_reset(); /* ATAPI Drives seems to need a proper IDE Reset */
+
+ /*
+ * Wait for IDE to get ready.
+ * According to spec, this can take up to 31 seconds!
+ */
+-#ifndef CONFIG_AMIGAONEG3SE
+- for (bus=0; bus<CFG_IDE_MAXBUS; ++bus) {
+- int dev = bus * (CFG_IDE_MAXDEVICE / CFG_IDE_MAXBUS);
+-#else
+- s = getenv("ide_maxbus");
+- if (s)
+- max_bus_scan = simple_strtol(s, NULL, 10);
+- else
+- max_bus_scan = CFG_IDE_MAXBUS;
+-
+- for (bus=0; bus<max_bus_scan; ++bus) {
+- int dev = bus * (CFG_IDE_MAXDEVICE / max_bus_scan);
+-#endif
+-
+-#ifdef CONFIG_IDE_8xx_PCCARD
+- /* Skip non-ide devices from probing */
+- if ((ide_devices_found & (1 << bus)) == 0) {
+- ide_led ((LED_IDE1 | LED_IDE2), 0); /* LED's off */
+- continue;
+- }
+-#endif
+- printf ("Bus %d: ", bus);
+-
+- ide_bus_ok[bus] = 0;
+-
+- /* Select device
+- */
+- udelay (100000); /* 100 ms */
+- ide_outb (dev, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(dev));
+- udelay (100000); /* 100 ms */
+-#ifdef CONFIG_AMIGAONEG3SE
+- ata_reset_time = ATA_RESET_TIME;
+- s = getenv("ide_reset_timeout");
+- if (s) ata_reset_time = 2*simple_strtol(s, NULL, 10);
+-#endif
+- i = 0;
+- do {
+- udelay (10000); /* 10 ms */
+-
+- c = ide_inb (dev, ATA_STATUS);
+- i++;
+-#ifdef CONFIG_AMIGAONEG3SE
+- if (i > (ata_reset_time * 100)) {
+-#else
+- if (i > (ATA_RESET_TIME * 100)) {
+-#endif
+- puts ("** Timeout **\n");
+- ide_led ((LED_IDE1 | LED_IDE2), 0); /* LED's off */
+-#ifdef CONFIG_AMIGAONEG3SE
+- /* If this is the second bus, the first one was OK */
+- if (bus != 0) {
+- ide_bus_ok[bus] = 0;
+- goto skip_bus;
+- }
+-#endif
+- return;
+- }
+- if ((i >= 100) && ((i%100)==0)) {
+- putc ('.');
+- }
+- } while (c & ATA_STAT_BUSY);
++ printf("Detecting SATA busses:\n");
++ for (bus=0; bus < CFG_IDE_MAXBUS; ++bus) {
++ printf("Bus %d: ", bus);
+
+- if (c & (ATA_STAT_BUSY | ATA_STAT_FAULT)) {
+- puts ("not available ");
+- PRINTF ("Status = 0x%02X ", c);
+-#ifndef CONFIG_ATAPI /* ATAPI Devices do not set DRDY */
+- } else if ((c & ATA_STAT_READY) == 0) {
+- puts ("not available ");
+- PRINTF ("Status = 0x%02X ", c);
+-#endif
+- } else {
+- puts ("OK ");
+- ide_bus_ok[bus] = 1;
+- }
+- WATCHDOG_RESET();
+- }
++ /* Try to discover if bus is present by probing first device on bus */
++ int device = bus * (CFG_IDE_MAXDEVICE / CFG_IDE_MAXBUS);
++ ide_bus_ok[bus] = ide_probe(device);
++ if (ide_bus_ok[bus]) {
++ puts("Found first device OK\n");
++ } else {
++ WATCHDOG_RESET();
++
++ /* Try second device on bus */
++ ide_bus_ok[bus] = ide_probe(++device);
++ if (ide_bus_ok[bus]) {
++ puts("Found second device OK\n");
++ } else {
++ puts("No devices found\n");
++ }
++ }
+
+-#ifdef CONFIG_AMIGAONEG3SE
+- skip_bus:
+-#endif
+- putc ('\n');
++ WATCHDOG_RESET();
++ }
+
+- ide_led ((LED_IDE1 | LED_IDE2), 0); /* LED's off */
++ ide_led((LED_IDE1 | LED_IDE2), 0); /* LED's off */
+
+ curr_device = -1;
+ for (i=0; i<CFG_IDE_MAXDEVICE; ++i) {
+@@ -675,13 +610,12 @@
+ ide_dev_desc[i].block_read=ide_read;
+ if (!ide_bus_ok[IDE_BUS(i)])
+ continue;
+- ide_led (led, 1); /* LED on */
++ ide_led(led, 1); /* LED on */
+ ide_ident(&ide_dev_desc[i]);
+- ide_led (led, 0); /* LED off */
++ ide_led(led, 0); /* LED off */
+ dev_print(&ide_dev_desc[i]);
+-/* ide_print (i); */
+ if ((ide_dev_desc[i].lba > 0) && (ide_dev_desc[i].blksz > 0)) {
+- init_part (&ide_dev_desc[i]); /* initialize partition type */
++ init_part(&ide_dev_desc[i]); /* initialize partition type */
+ if (curr_device < 0)
+ curr_device = i;
+ }
+@@ -689,6 +623,11 @@
+ WATCHDOG_RESET();
+ }
+
++int is_device_present(int device_number)
++{
++ return ide_dev_desc[device_number].part_type != PART_TYPE_UNKNOWN;
++}
++
+ /* ------------------------------------------------------------------------- */
+
+ block_dev_desc_t * ide_get_dev(int dev)
+@@ -798,6 +737,11 @@
+ EIEIO;
+ *((uchar *)(ATA_CURR_BASE(dev)+port)) = val;
+ }
++#elif defined(CONFIG_OXNAS)
++static void __inline__ ide_outb(int dev, int port, unsigned char val)
++{
++ oxnas_sata_outb(dev, port, val);
++}
+ #else /* ! __PPC__ */
+ static void __inline__
+ ide_outb(int dev, int port, unsigned char val)
+@@ -819,6 +763,11 @@
+ dev, port, (ATA_CURR_BASE(dev)+port), val);
+ return (val);
+ }
++#elif defined(CONFIG_OXNAS)
++static unsigned char __inline__ ide_inb(int dev, int port)
++{
++ return oxnas_sata_inb(dev, port);
++}
+ #else /* ! __PPC__ */
+ static unsigned char __inline__
+ ide_inb(int dev, int port)
+@@ -921,6 +870,11 @@
+ }
+ #endif /* CONFIG_HMI10 */
+ }
++#elif defined(CONFIG_OXNAS)
++static void output_data(int dev, ulong *sect_buf, int words)
++{
++ oxnas_sata_output_data(dev, sect_buf, words);
++}
+ #else /* ! __PPC__ */
+ static void
+ output_data(int dev, ulong *sect_buf, int words)
+@@ -968,6 +922,11 @@
+ }
+ #endif /* CONFIG_HMI10 */
+ }
++#elif defined(CONFIG_OXNAS)
++static void input_data(int dev, ulong *sect_buf, int words)
++{
++ oxnas_sata_input_data(dev, sect_buf, words);
++}
+ #else /* ! __PPC__ */
+ static void
+ input_data(int dev, ulong *sect_buf, int words)
+@@ -1001,10 +960,36 @@
+
+ /* -------------------------------------------------------------------------
+ */
++#ifdef CONFIG_OXNAS
++static void byte_swap_and_trim(char* buf)
++{
++ char *src = buf;
++
++ // Swap bytes in 16-bit words
++ while ((*src != '\0') && (*(src+1) != '\0')) {
++ char tmp = *(src+1);
++ *(src+1) = *src;
++ *src = tmp;
++ src += 2;
++ }
++
++ // Trim leading spaces
++ src = buf;
++ while (*src == ' ') {
++ ++src;
++ }
++ if (src != buf) {
++ memcpy(buf, src, strlen(src));
++ buf[strlen(buf) - (src-buf)] = '\0';
++ }
++}
++#endif // CONFIG_OXNAS
++
+ static void ide_ident (block_dev_desc_t *dev_desc)
+ {
+ ulong iobuf[ATA_SECTORWORDS];
+ unsigned char c;
++ unsigned int i;
+ hd_driveid_t *iop = (hd_driveid_t *)iobuf;
+
+ #ifdef CONFIG_AMIGAONEG3SE
+@@ -1023,6 +1008,10 @@
+ device=dev_desc->dev;
+ printf (" Device %d: ", device);
+
++ for ( i=0; i < ATA_SECTORWORDS; ++i) {
++ iobuf[i] = 0;
++ }
++
+ #ifdef CONFIG_AMIGAONEG3SE
+ s = getenv("ide_maxbus");
+ if (s) {
+@@ -1110,20 +1099,22 @@
+
+ input_swap_data (device, iobuf, ATA_SECTORWORDS);
+
+- ident_cpy (dev_desc->revision, iop->fw_rev, sizeof(dev_desc->revision));
+- ident_cpy (dev_desc->vendor, iop->model, sizeof(dev_desc->vendor));
+- ident_cpy (dev_desc->product, iop->serial_no, sizeof(dev_desc->product));
++ ident_cpy(dev_desc->revision, iop->fw_rev, sizeof(dev_desc->revision));
++ ident_cpy(dev_desc->vendor, iop->model, sizeof(dev_desc->vendor));
++ ident_cpy(dev_desc->product, iop->serial_no, sizeof(dev_desc->product));
++
+ #ifdef __LITTLE_ENDIAN
+ /*
+- * firmware revision and model number have Big Endian Byte
++ * firmware revision, model number and product have Big Endian Byte
+ * order in Word. Convert both to little endian.
+ *
+ * See CF+ and CompactFlash Specification Revision 2.0:
+ * 6.2.1.6: Identfy Drive, Table 39 for more details
+ */
+
+- strswab (dev_desc->revision);
+- strswab (dev_desc->vendor);
++ byte_swap_and_trim(dev_desc->revision);
++ byte_swap_and_trim(dev_desc->vendor);
++ byte_swap_and_trim(dev_desc->product);
+ #endif /* __LITTLE_ENDIAN */
+
+ if ((iop->config & 0x0080)==0x0080)
+diff -Nurd u-boot-1.1.2/common/cmd_ledfail.c u-boot-1.1.2-oxe810/common/cmd_ledfail.c
+--- u-boot-1.1.2/common/cmd_ledfail.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-oxe810/common/cmd_ledfail.c 2008-06-11 17:55:30.000000000 +0200
+@@ -0,0 +1,58 @@
++
++#include <common.h>
++#include <command.h>
++
++#if (CONFIG_COMMANDS & CFG_CMD_LEDFAIL)
++#define FAILURE_LED (1 << (34-32))
++
++#define GPIO_B 0x44100000
++#define WARN_GPIO_OUT_REG (GPIO_B + 0x10)
++#define WARN_GPIO_OUT_ENABLE_SET (GPIO_B + 0x1C)
++#define WARN_GPIO_OUT_ENABLE_CLR (GPIO_B + 0x20)
++
++static void ledfail_light(void)
++{
++ printf("Light LED\n");
++ /* Light the failure LED - assumes active low drive */
++ u_int32_t led_state = *((volatile u_int32_t *)WARN_GPIO_OUT_REG);
++ led_state = led_state & ~FAILURE_LED;
++ *((volatile u_int32_t *)WARN_GPIO_OUT_REG) = led_state;
++
++ /* Enable GPIO for output */
++ *((volatile u_int32_t *)WARN_GPIO_OUT_ENABLE_SET) = FAILURE_LED;
++}
++
++static void ledfail_extinguish(void)
++{
++ printf("Extinguish LED\n");
++ /* Extinguish the failure LED - assumes active low drive */
++ u_int32_t led_state = *((volatile u_int32_t *)WARN_GPIO_OUT_REG);
++ led_state = led_state | FAILURE_LED;
++ *((volatile u_int32_t *)WARN_GPIO_OUT_REG) = led_state;
++
++ /* Clear the failure bit output enable in GPIO's */
++ *((volatile u_int32_t *)WARN_GPIO_OUT_ENABLE_CLR) = FAILURE_LED;
++}
++
++int do_ledfail(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
++{
++ if (argc != 2) {
++ printf ("Usage:\n%s\n", cmdtp->usage);
++ return 1;
++ }
++
++ ulong arg = simple_strtoul(argv[1], NULL, 10);
++ switch (arg) {
++ case 0:
++ ledfail_extinguish();
++ break;
++ case 1:
++ ledfail_light();
++ break;
++ }
++
++ return 0;
++}
++
++U_BOOT_CMD(ledfail, 2, 2, do_ledfail, "ledfail - Extinguish (0) or light (1) failure LED\n", NULL);
++#endif /* CFG_CMD_LEDFAIL */
+diff -Nurd u-boot-1.1.2/common/cmd_mem.c u-boot-1.1.2-oxe810/common/cmd_mem.c
+--- u-boot-1.1.2/common/cmd_mem.c 2004-12-16 18:42:39.000000000 +0100
++++ u-boot-1.1.2-oxe810/common/cmd_mem.c 2008-06-11 17:55:30.000000000 +0200
+@@ -731,13 +731,17 @@
+ if (argc > 1) {
+ start = (ulong *)simple_strtoul(argv[1], NULL, 16);
+ } else {
+- start = (ulong *)CFG_MEMTEST_START;
++ DECLARE_GLOBAL_DATA_PTR;
++
++ start = (ulong *)(gd->bd->bi_dram[0].start);
+ }
+
+ if (argc > 2) {
+ end = (ulong *)simple_strtoul(argv[2], NULL, 16);
+ } else {
+- end = (ulong *)(CFG_MEMTEST_END);
++ DECLARE_GLOBAL_DATA_PTR;
++
++ end = (ulong *)(start + gd->bd->bi_dram[0].size);
+ }
+
+ if (argc > 3) {
+diff -Nurd u-boot-1.1.2/common/cmd_nvedit.c u-boot-1.1.2-oxe810/common/cmd_nvedit.c
+--- u-boot-1.1.2/common/cmd_nvedit.c 2004-09-30 00:55:14.000000000 +0200
++++ u-boot-1.1.2-oxe810/common/cmd_nvedit.c 2008-06-11 17:55:30.000000000 +0200
+@@ -55,8 +55,9 @@
+ !defined(CFG_ENV_IS_IN_FLASH) && \
+ !defined(CFG_ENV_IS_IN_DATAFLASH) && \
+ !defined(CFG_ENV_IS_IN_NAND) && \
++ !defined(CFG_ENV_IS_IN_DISK) && \
+ !defined(CFG_ENV_IS_NOWHERE)
+-# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|NOWHERE}
++# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|DISK|NOWHERE}
+ #endif
+
+ #define XMK_STR(x) #x
+@@ -483,7 +484,7 @@
+ * or NULL if not found
+ */
+
+-char *getenv (uchar *name)
++char *getenv (const uchar *name)
+ {
+ int i, nxt;
+
+@@ -530,7 +531,9 @@
+ return (-1);
+ }
+
+-#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) || \
++#if defined(CFG_ENV_IS_IN_NVRAM) || \
++ defined(CFG_ENV_IS_IN_EEPROM) || \
++ defined(CFG_ENV_IS_IN_DISK) || \
+ ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == \
+ (CFG_CMD_ENV|CFG_CMD_FLASH))
+ int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+@@ -586,7 +589,9 @@
+ " - delete environment variable 'name'\n"
+ );
+
+-#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) || \
++#if defined(CFG_ENV_IS_IN_NVRAM) || \
++ defined(CFG_ENV_IS_IN_EEPROM) || \
++ defined(CFG_ENV_IS_IN_DISK) || \
+ ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == \
+ (CFG_CMD_ENV|CFG_CMD_FLASH))
+ U_BOOT_CMD(
+diff -Nurd u-boot-1.1.2/common/env_common.c u-boot-1.1.2-oxe810/common/env_common.c
+--- u-boot-1.1.2/common/env_common.c 2004-06-09 16:58:14.000000000 +0200
++++ u-boot-1.1.2-oxe810/common/env_common.c 2008-06-11 17:55:30.000000000 +0200
+@@ -42,7 +42,7 @@
+ extern void disable_nvram(void);
+ #endif
+
+-#undef DEBUG_ENV
++//#undef DEBUG_ENV
+ #ifdef DEBUG_ENV
+ #define DEBUGF(fmt,args...) printf(fmt ,##args)
+ #else
+diff -Nurd u-boot-1.1.2/common/env_disk.c u-boot-1.1.2-oxe810/common/env_disk.c
+--- u-boot-1.1.2/common/env_disk.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-oxe810/common/env_disk.c 2008-06-11 17:55:30.000000000 +0200
+@@ -0,0 +1,152 @@
++/*
++ * (C) Copyright 2006
++ * Oxford Semiconductor Ltd
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#include <common.h>
++
++#if defined(CFG_ENV_IS_IN_DISK)
++
++#include <command.h>
++#include <environment.h>
++#include <ide.h>
++
++extern int is_device_present(int device_number);
++
++/* Point to the environment as held in SRAM */
++env_t *env_ptr = NULL;
++
++char *env_name_spec = "Disk";
++
++/* The default environment compiled into U-Boot */
++extern uchar default_environment[];
++
++uchar env_get_char_spec(int index)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ return *((uchar *)(gd->env_addr + index));
++}
++
++#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
++
++void env_relocate_spec(void)
++{
++ /* Compute the CRC of the environment in SRAM, copied from disk at boot */
++ env_t *sram_env = (env_t*)CFG_ENV_ADDR;
++ ulong crc = crc32(0, sram_env->data, CFG_ENV_SIZE - offsetof(env_t, data));
++
++ /* Copy the SRAM environment and CRC to the working environment */
++ memcpy(env_ptr->data, sram_env->data, CFG_ENV_SIZE - offsetof(env_t, data));
++ env_ptr->crc = crc;
++}
++
++int saveenv(void)
++{
++ /* Compute the CRC of the working environment */
++ env_ptr->crc = crc32(0, env_ptr->data, CFG_ENV_SIZE - offsetof(env_t, data));
++
++ /* Copy the working environment to the reserved area on each disk device */
++ int status = 1;
++ int i;
++ for (i=0; i < CFG_IDE_MAXDEVICE; ++i) {
++ if (!is_device_present(i)) {
++ continue;
++ }
++
++ /* Write environment to the main environment area on disk */
++ unsigned long written = ide_write(i, CFG_ENV_DISK_SECTOR, CFG_ENV_SIZE/512, (ulong*)env_ptr);
++ if (written != CFG_ENV_SIZE/512) {
++ printf("Saving environment to disk %d primary image failed\n", i);
++ status = 0;
++ } else {
++ /* Write environment to the redundant environment area on disk */
++ written = ide_write(i, CFG_ENV_DISK_REDUNDANT_SECTOR, CFG_ENV_SIZE/512, (ulong*)env_ptr);
++ if (written != CFG_ENV_SIZE/512) {
++ printf("Saving environment to disk %d secondary image failed\n", i);
++ status = 0;
++ }
++ }
++ }
++
++ return status;
++}
++
++static int check_sram_env_integrity(void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ env_t *sram_env = (env_t*)CFG_ENV_ADDR;
++ ulong crc = crc32(0, sram_env->data, CFG_ENV_SIZE - offsetof(env_t, data));
++
++ if (crc == sram_env->crc) {
++ gd->env_addr = (ulong)sram_env->data;
++ gd->env_valid = 1;
++ }
++
++ return gd->env_valid;
++}
++
++int env_init(void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ /* Have not yet found a valid environment */
++ gd->env_valid = 0;
++
++ /* Need SATA available to load environment from alternate disk locations */
++ ide_init();
++
++ int i;
++ for (i=0; i < CFG_IDE_MAXDEVICE; ++i) {
++ if (!is_device_present(i)) {
++ continue;
++ }
++
++ /* Read environment from the primary environment area on disk */
++ unsigned long read = ide_read(i, CFG_ENV_DISK_SECTOR, CFG_ENV_SIZE/512, (ulong*)CFG_ENV_ADDR);
++ if (read == CFG_ENV_SIZE/512) {
++ /* Check integrity of primary environment data */
++ if (check_sram_env_integrity()) {
++ printf("Environment successfully read from disk %d primary image\n", i);
++ break;
++ }
++ }
++
++ /* Read environment from the secondary environment area on disk */
++ read = ide_read(i, CFG_ENV_DISK_REDUNDANT_SECTOR, CFG_ENV_SIZE/512, (ulong*)CFG_ENV_ADDR);
++ if (read == CFG_ENV_SIZE/512) {
++ /* Check integrity of secondary environment data */
++ if (check_sram_env_integrity()) {
++ printf("Environment successfully read from disk %d secondary image\n", i);
++ break;
++ }
++ }
++ }
++
++ if (!gd->env_valid) {
++ printf("Failed to read valid environment from disk, using built-in default\n");
++ gd->env_addr = (ulong)default_environment;
++ gd->env_valid = 0;
++ }
++
++ return 0;
++}
++#endif // CFG_ENV_IS_IN_DISK
+diff -Nurd u-boot-1.1.2/common/main.c u-boot-1.1.2-oxe810/common/main.c
+--- u-boot-1.1.2/common/main.c 2004-04-23 22:32:06.000000000 +0200
++++ u-boot-1.1.2-oxe810/common/main.c 2008-06-11 17:55:30.000000000 +0200
+@@ -182,7 +182,7 @@
+ else {
+ for (i = 0; i < presskey_max - 1; i ++)
+ presskey [i] = presskey [i + 1];
+-
++do_recovery
+ presskey [i] = getc();
+ }
+ }
+@@ -369,6 +369,149 @@
+ install_auto_complete();
+ #endif
+
++
++#if defined(CONFIG_OXNAS)
++ /* Set the memory size given to Linux */
++ {
++ DECLARE_GLOBAL_DATA_PTR;
++
++ /* Get a copy of the bootargs string from the runtime environment */
++ char tempBuf[1024];
++ char* cmd_string = strcpy(&tempBuf[0], getenv("bootargs"));
++
++ /* Find the extent of memory token in the bootargs string */
++ char* mem_token = strstr(cmd_string, "mem=");
++ char* mem_token_end = mem_token;
++ while ((*mem_token_end != ' ') &&
++ (*mem_token_end != '\0')) {
++ ++mem_token_end;
++ }
++
++ if ((*mem_token_end == '\0') && (mem_token != mem_token_end)) {
++ /* Memory token is last in bootargs string */
++ if (mem_token != cmd_string) {
++ /* Is not the only token, so erase token and previous space" */
++ *(mem_token-1) = '\0';
++ } else {
++ /* Is the only token, so no previous space to erase */
++ *mem_token = '\0';
++ }
++ } else {
++ /* Memory token is at intermediate location in bootargs string */
++ if (*mem_token_end == ' ') {
++ ++mem_token_end;
++ }
++
++ /* Form the bootargs string without the memory token present */
++ strcpy(mem_token, mem_token_end);
++ }
++
++ /* How many MB of SDRAM are present */
++ int megabytes = gd->bd->bi_dram[0].size >> 20;
++
++ /* Append the memory token to the bootargs string */
++ switch (megabytes) {
++ case 64:
++ cmd_string = strcat(cmd_string, " mem=64M");
++ break;
++ case 128:
++ cmd_string = strcat(cmd_string, " mem=128M");
++ break;
++ case 256:
++ cmd_string = strcat(cmd_string, " mem=256M");
++ break;
++ default:
++ printf("Unsupported memory size, defaulting to 64M\n");
++ cmd_string = strcat(cmd_string, " mem=64M");
++ }
++
++ /* Save the revised bootargs string to the runtime environment */
++ setenv("bootargs", cmd_string);
++ }
++
++/* Upgrade, recovery and power button monitor code
++*/
++ int do_recovery = 0; /* default no recovery */
++
++ /* Read the upgrade flag from disk into memory */
++ ide_init();
++ run_command("ide read 48700000 ff 1", 0);
++
++ char upgrade_mode = *(volatile char*)0x48700000;
++ char recovery_mode = *(volatile char*)0x48700001;
++ char controlled_pd_mode = *(volatile char*)0x48700002;
++
++ if (recovery_mode == RECOVERY_MAGIC) {
++ do_recovery = 1; /* perform recovery */
++ }
++
++ if (controlled_pd_mode == CONTROLLED_POWER_DOWN_MAGIC) {
++ /* System in controlled pwer down mode */
++
++ /* Read the SRAM location for normal boot flag */
++ char sram_data = *(volatile char*)(CFG_SRAM_BASE + CFG_SRAM_SIZE - POWER_ON_FLAG_SRAM_OFFSET);
++ char tempBuf[1024];
++ char* cmd_string = strcpy(&tempBuf[0], getenv("bootargs"));
++
++ if (sram_data == CONTROLLED_POWER_UP_MAGIC) {
++ /* The system has to remain in power down state */
++
++ /* Set appropriate boot args */
++ cmd_string = strcat(cmd_string, " powermode=controlledpup");
++ printf("Controlled Power UP requested\n");
++ } else {
++ /* The system is moving to power up state from power down state */
++ cmd_string = strcat(cmd_string, " powermode=controlledpdown");
++ printf("Controlled Power DOWN requested\n");
++ }
++ setenv("bootargs", cmd_string);
++ }
++
++ /* branch off inot recovery or upadate */
++ if (upgrade_mode == UPGRADE_MAGIC) {
++ /* Script to select first disk */
++ parse_string_outer("set select0 ide dev 0", FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
++
++ /* Script to select second disk */
++ parse_string_outer("set select1 ide dev 1", FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
++
++ /* Script for loading 256KB of upgrade rootfs image from hidden sectors */
++ parse_string_outer("set loadf ide read 48700000 1770 200", FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
++
++ /* Script for loading 2MB of upgrade kernel image from hidden sectors */
++ parse_string_outer("set loadk ide read 48800000 1970 1000", FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
++
++ /* Script to light failure LED */
++ parse_string_outer("set lightled ledfail 1", FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
++
++ /* Script to extinguish failure LED */
++ parse_string_outer("set extinguishled ledfail 0", FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
++
++ /* Script for booting Linux kernel image with mkimage-wrapped initrd */
++ parse_string_outer("set boot bootm 48800000 48700000", FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
++
++ /* Set Linux bootargs to use rootfs in initial ramdisk */
++ parse_string_outer("set bootargs mem=32M console=ttyS0,115200 root=/dev/ram0", FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
++
++ /* Validate, load and boot the first validate set of initrd and kernel
++ Theres alot of combos here due to disk/backup/fk arrangments, it'll
++ no doubt work on the first or second one though. */
++ parse_string_outer("run select0 loadf loadk boot || "
++ "run lightled select1 loadf loadk extinguishled boot || "
++ "run lightled select0 loadf select1 loadk extinguishled boot || "
++ "run lightled select1 loadf select0 loadk extinguishled boot || "
++ "run lightled ", FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
++ } else if (do_recovery) {
++ printf ("\nRecovery mode selected\n");
++
++ char tempBuf[1024];
++ char* cmd_string = strcpy(&tempBuf[0], getenv("bootargs"));
++ cmd_string = strcat(cmd_string, " adminmode=recovery");
++ setenv("bootargs", cmd_string);
++ }
++
++#endif // CONFIG_OXNAS
++
+ #ifdef CONFIG_PREBOOT
+ if ((p = getenv ("preboot")) != NULL) {
+ # ifdef CONFIG_AUTOBOOT_KEYED
+diff -Nurd u-boot-1.1.2/common/Makefile u-boot-1.1.2-oxe810/common/Makefile
+--- u-boot-1.1.2/common/Makefile 2004-12-16 18:35:57.000000000 +0100
++++ u-boot-1.1.2-oxe810/common/Makefile 2008-06-11 17:55:30.000000000 +0200
+@@ -40,9 +40,10 @@
+ cmd_nand.o cmd_net.o cmd_nvedit.o \
+ cmd_pci.o cmd_pcmcia.o cmd_portio.o \
+ cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o cmd_usb.o cmd_vfd.o \
++ cmd_ledfail.o \
+ command.o console.o devices.o dlmalloc.o docecc.o \
+ environment.o env_common.o \
+- env_nand.o env_dataflash.o env_flash.o env_eeprom.o env_nvram.o env_nowhere.o exports.o \
++ env_nand.o env_dataflash.o env_flash.o env_eeprom.o env_nvram.o env_nowhere.o env_disk.o exports.o \
+ flash.o fpga.o \
+ hush.o kgdb.o lcd.o lists.o lynxkdi.o \
+ memsize.o miiphybb.o miiphyutil.o \
+diff -Nurd u-boot-1.1.2/cpu/arm926ejs/config.mk u-boot-1.1.2-oxe810/cpu/arm926ejs/config.mk
+--- u-boot-1.1.2/cpu/arm926ejs/config.mk 2003-08-30 00:00:47.000000000 +0200
++++ u-boot-1.1.2-oxe810/cpu/arm926ejs/config.mk 2008-06-11 17:55:03.000000000 +0200
+@@ -21,7 +21,6 @@
+ # MA 02111-1307 USA
+ #
+
+-PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
+- -mshort-load-bytes -msoft-float
++PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8
+
+-PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4
++PLATFORM_CPPFLAGS += -march=armv5te
+diff -Nurd u-boot-1.1.2/cpu/arm926ejs/interrupts.c u-boot-1.1.2-oxe810/cpu/arm926ejs/interrupts.c
+--- u-boot-1.1.2/cpu/arm926ejs/interrupts.c 2004-03-23 22:43:08.000000000 +0100
++++ u-boot-1.1.2-oxe810/cpu/arm926ejs/interrupts.c 2008-06-11 17:55:03.000000000 +0200
+@@ -41,7 +41,12 @@
+ #include <asm/proc-armv/ptrace.h>
+
+ extern void reset_cpu(ulong addr);
++
++#ifdef CONFIG_OXNAS
++#define TIMER_LOAD_VAL 0xffffUL
++#else // CONFIG_OXNAS
+ #define TIMER_LOAD_VAL 0xffffffff
++#endif // CONFIG_OXNAS
+
+ /* macro to read the 32 bit timer */
+ #ifdef CONFIG_OMAP
+@@ -53,6 +58,9 @@
+ #ifdef CONFIG_VERSATILE
+ #define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4))
+ #endif
++#ifdef CONFIG_OXNAS
++#define READ_TIMER ((*(volatile ushort *)(CFG_TIMERBASE+4)) & 0xFFFFUL) /* RPS timer value register has only 16 defined bits */
++#endif
+
+ #ifdef CONFIG_USE_IRQ
+ /* enable IRQ interrupts */
+@@ -212,6 +220,16 @@
+ *(volatile ulong *)(CFG_TIMERBASE + 4) = CFG_TIMER_RELOAD; /* TimerValue */
+ *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x8C;
+ #endif /* CONFIG_VERSATILE */
++#ifdef CONFIG_OXNAS
++ // Setup timer 1 load value
++ *(volatile ulong*)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL;
++
++ // Setup timer 1 prescaler, periodic operation and start it
++ *(volatile ulong*)(CFG_TIMERBASE + 8) =
++ (TIMER_PRESCALE_ENUM << TIMER_PRESCALE_BIT) |
++ (TIMER_MODE_PERIODIC << TIMER_MODE_BIT) |
++ (TIMER_ENABLE_ENABLE << TIMER_ENABLE_BIT);
++#endif /* CONFIG_OXNAS */
+
+ /* init the timestamp and lastdec value */
+ reset_timer_masked();
+diff -Nurd u-boot-1.1.2/cpu/arm926ejs/start.S u-boot-1.1.2-oxe810/cpu/arm926ejs/start.S
+--- u-boot-1.1.2/cpu/arm926ejs/start.S 2004-06-09 02:11:01.000000000 +0200
++++ u-boot-1.1.2-oxe810/cpu/arm926ejs/start.S 2008-06-11 17:55:03.000000000 +0200
+@@ -94,6 +94,11 @@
+ _TEXT_BASE:
+ .word TEXT_BASE
+
++#ifdef CONFIG_OXNAS
++_EXCEPTION_BASE:
++ .word EXCEPTION_BASE
++#endif
++
+ .globl _armboot_start
+ _armboot_start:
+ .word _start
+@@ -135,6 +140,18 @@
+ orr r0,r0,#0xd3
+ msr cpsr,r0
+
++#ifdef CONFIG_OXNAS
++ /*
++ * Copy exception table to relocated address in internal SRAM
++ */
++ adr r0, _start /* Address of exception table in flash */
++ ldr r1, _EXCEPTION_BASE /* Relocated address of exception table */
++ ldmia r0!, {r3-r10} /* Copy exception table and jump values from */
++ stmia r1!, {r3-r10} /* FLASH to relocated address */
++ ldmia r0!, {r3-r10}
++ stmia r1!, {r3-r10}
++#endif
++
+ /*
+ * we do sys-critical inits only at reboot,
+ * not when booting from ram!
+@@ -143,21 +160,21 @@
+ bl cpu_init_crit
+ #endif
+
+-relocate: /* relocate U-Boot to RAM */
+- adr r0, _start /* r0 <- current position of code */
+- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
+- cmp r0, r1 /* don't reloc during debug */
+- beq stack_setup
++relocate: /* relocate U-Boot to RAM */
++ adr r0, _start /* current position of code */
++ ldr r1, _TEXT_BASE /* relocated position of code */
++ cmp r0, r1
++ beq stack_setup
+
+ ldr r2, _armboot_start
+ ldr r3, _bss_start
+- sub r2, r3, r2 /* r2 <- size of armboot */
+- add r2, r0, r2 /* r2 <- source end address */
++ sub r2, r3, r2 /* r2 <- size of armboot */
++ add r2, r0, r2 /* r2 <- source end address */
+
+ copy_loop:
+- ldmia r0!, {r3-r10} /* copy from source address [r0] */
+- stmia r1!, {r3-r10} /* copy to target address [r1] */
+- cmp r0, r2 /* until source end addreee [r2] */
++ ldmia r0!, {r3-r10} /* copy from source address [r0] */
++ stmia r1!, {r3-r10} /* copy to target address [r1] */
++ cmp r0, r2 /* until source end addreee [r2] */
+ ble copy_loop
+
+ /* Set up the stack */
+@@ -212,7 +229,7 @@
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
+ bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
+- orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
++ orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
+ orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
+ mcr p15, 0, r0, c1, c0, 0
+
+@@ -391,6 +408,7 @@
+
+ #endif
+
++#ifndef CONFIG_OXNAS
+ .align 5
+ .globl reset_cpu
+ reset_cpu:
+@@ -405,3 +423,4 @@
+
+ rstctl1:
+ .word 0xfffece10
++#endif // !CONFIG_OXNAS
+diff -Nurd u-boot-1.1.2/drivers/cfi_flash.c u-boot-1.1.2-oxe810/drivers/cfi_flash.c
+--- u-boot-1.1.2/drivers/cfi_flash.c 2004-12-18 23:35:45.000000000 +0100
++++ u-boot-1.1.2-oxe810/drivers/cfi_flash.c 2008-06-11 17:55:31.000000000 +0200
+@@ -1056,7 +1056,11 @@
+ }
+ tmp = flash_read_long (info, 0,
+ FLASH_OFFSET_ERASE_REGIONS +
++#ifdef FORCE_TOP_BOOT_FLASH
++ (num_erase_regions - 1 - i) * 4);
++#else
+ i * 4);
++#endif
+ erase_region_size =
+ (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
+ tmp >>= 16;
+@@ -1104,6 +1108,7 @@
+ cfiptr_t ctladdr;
+ cfiptr_t cptr;
+ int flag;
++ ulong start;
+
+ ctladdr.cp = flash_make_addr (info, 0, 0);
+ cptr.cp = (uchar *) dest;
+@@ -1151,6 +1156,15 @@
+ break;
+ case FLASH_CFI_16BIT:
+ cptr.wp[0] = cword.w;
++ /* Wait for write to complete */
++ start = get_timer (0);
++ while (cptr.wp[0] != cword.w) {
++ printf(".");
++ if (get_timer (start) > info->erase_blk_tout * CFG_HZ) {
++ printf ("Flash write timeout!");;
++ }
++ }
++ printf("\n");
+ break;
+ case FLASH_CFI_32BIT:
+ cptr.lp[0] = cword.l;
+diff -Nurd u-boot-1.1.2/drivers/ns16550.c u-boot-1.1.2-oxe810/drivers/ns16550.c
+--- u-boot-1.1.2/drivers/ns16550.c 2004-06-07 01:13:57.000000000 +0200
++++ u-boot-1.1.2-oxe810/drivers/ns16550.c 2008-06-11 17:55:31.000000000 +0200
+@@ -14,8 +14,25 @@
+ #define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */
+ #define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs */
+
++#ifdef USE_UART_FRACTIONAL_DIVIDER
++static int oxnas_fractional_divider(NS16550_t com_port, int baud_divisor)
++{
++ // Baud rate is passed around x16
++ int real_divisor = baud_divisor >> 4;
++ // Top three bits of 8-bit dlf register hold the number of eigths
++ // for the fractional part of the divide ratio
++ com_port->dlf = (unsigned char)(((baud_divisor - (real_divisor << 4)) << 4) & 0xFF);
++ // Return the x1 divider for the normal divider register
++ return real_divisor;
++}
++#endif // USE_UART_FRACTIONAL_DIVIDER
++
+ void NS16550_init (NS16550_t com_port, int baud_divisor)
+ {
++#ifdef USE_UART_FRACTIONAL_DIVIDER
++ baud_divisor = oxnas_fractional_divider(com_port, baud_divisor);
++#endif // USE_UART_FRACTIONAL_DIVIDER
++
+ com_port->ier = 0x00;
+ #ifdef CONFIG_OMAP1510
+ com_port->mdr1 = 0x7; /* mode select reset TL16C750*/
+@@ -33,6 +50,10 @@
+
+ void NS16550_reinit (NS16550_t com_port, int baud_divisor)
+ {
++#ifdef USE_UART_FRACTIONAL_DIVIDER
++ baud_divisor = oxnas_fractional_divider(com_port, baud_divisor);
++#endif // USE_UART_FRACTIONAL_DIVIDER
++
+ com_port->ier = 0x00;
+ com_port->lcr = LCR_BKSE;
+ com_port->dll = baud_divisor & 0xff;
+diff -Nurd u-boot-1.1.2/drivers/serial.c u-boot-1.1.2-oxe810/drivers/serial.c
+--- u-boot-1.1.2/drivers/serial.c 2003-08-30 00:00:47.000000000 +0200
++++ u-boot-1.1.2-oxe810/drivers/serial.c 2008-06-11 17:55:31.000000000 +0200
+@@ -59,7 +59,13 @@
+ return (26); /* return 26 for base divisor */
+ }
+ #endif
+- return (CFG_NS16550_CLK / 16 / gd->baudrate);
++
++#ifdef USE_UART_FRACTIONAL_DIVIDER
++ return (((CFG_NS16550_CLK << 4) / gd->baudrate) + 8) >> 4;
++#endif // USE_UART_FRACTIONAL_DIVIDER
++
++ // Round to nearest integer
++ return (((CFG_NS16550_CLK / gd->baudrate) + 8 ) / 16);
+ }
+
+ int serial_init (void)
+diff -Nurd u-boot-1.1.2/examples/Makefile u-boot-1.1.2-oxe810/examples/Makefile
+--- u-boot-1.1.2/examples/Makefile 2004-10-10 23:27:33.000000000 +0200
++++ u-boot-1.1.2-oxe810/examples/Makefile 2008-06-11 17:55:30.000000000 +0200
+@@ -30,7 +30,8 @@
+ endif
+
+ ifeq ($(ARCH),arm)
+-LOAD_ADDR = 0xc100000
++#LOAD_ADDR = 0xc100000
++LOAD_ADDR = 0x4C004000
+ endif
+
+ ifeq ($(ARCH),mips)
+@@ -58,6 +59,11 @@
+ SREC = hello_world.srec
+ BIN = hello_world.bin hello_world
+
++ifeq ($(ARCH),arm)
++SREC += mem_test.srec
++BIN += mem_test.bin mem_test
++endif
++
+ ifeq ($(ARCH),i386)
+ SREC += 82559_eeprom.srec
+ BIN += 82559_eeprom.bin 82559_eeprom
+@@ -115,10 +121,10 @@
+ $(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \
+ -o $@ -e $(<:.o=) $< $(LIB) \
+ -L$(gcclibdir) -lgcc
+-%.srec: %
++%.srec: %.o
+ $(OBJCOPY) -O srec $< $@ 2>/dev/null
+
+-%.bin: %
++%.bin: %.o
+ $(OBJCOPY) -O binary $< $@ 2>/dev/null
+
+ #########################################################################
+diff -Nurd u-boot-1.1.2/examples/mem_test.c u-boot-1.1.2-oxe810/examples/mem_test.c
+--- u-boot-1.1.2/examples/mem_test.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-oxe810/examples/mem_test.c 2008-06-11 17:55:30.000000000 +0200
+@@ -0,0 +1,1322 @@
++/*
++ * (C) Copyright 2006
++ * Oxford Semiconductor Ltd, www.oxsemi.com
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++/********************* OPTIONS ********************************************************/
++
++#define ARM
++/*
++#define QUIET
++#define SHORT
++*/
++
++/********************* TEST DEFINITIONS ********************************************************/
++
++
++#define NUM_PATTYPES 5
++#define PATTYPE_A5 0
++#define PATTYPE_5A 1
++#define PATTYPE_NO_FF 2
++#define PATTYPE_INCR 3
++#define PATTYPE_DECR 4
++
++/* Number of words in a block (to ensure that neither data not ~data is 0xFFxx) */
++
++#ifdef SHORT
++ #define BLOCKWORDS (254*4)
++ #define BLOCKSIZE (256*4)
++#else
++ #define BLOCKWORDS (254*256*4)
++ #define BLOCKSIZE (256*256*4)
++#endif
++
++#ifdef ARM
++ #include <common.h>
++ #include <exports.h>
++
++ #define SDRAM_BASE 0x48000000
++ #define SDRAM_TOP 0x49000000
++ #define SDRAM_BLOCK 0x10000
++// #define SDRAM_WRITE(ADDR, DATA) printf("Write 0x%08x to 0x%08x\n", (DATA), (ADDR));
++// #define SDRAM_READ(ADDR, VAR) printf("Read from 0x%08x\n", (ADDR));
++// #define SDRAM_WRITE(ADDR, DATA) printf("Write 0x%08x to 0x%08x\n", (DATA), (ADDR)); (*((volatile unsigned int *)(ADDR)) = (DATA))
++// #define SDRAM_READ(ADDR, VAR) printf("Read from 0x%08x\n", (ADDR)); (*(VAR) = *((volatile unsigned int *)(ADDR)))
++ #define SDRAM_WRITE(ADDR, DATA) (*((volatile unsigned int *)(ADDR)) = (DATA))
++ #define SDRAM_READ(ADDR, VAR) (*(VAR) = *((volatile unsigned int *)(ADDR)))
++#else
++ #include <stdio.h>
++ #include <stdlib.h>
++ /* Not so much space - just 2 blocks from addr 0... */
++ #define SDRAM_BASE 0
++ #define SDRAM_TOP (2 * BLOCKSIZE)
++ #define SDRAM_BLOCK 0x10000
++ #ifdef QUIET
++ #define SDRAM_WRITE(ADDR, DATA) array[ADDR] = (DATA)
++ #define SDRAM_READ(ADDR, VAR) *((volatile unsigned int *)(VAR)) = array[ADDR]
++ #else
++ #define SDRAM_WRITE(ADDR, DATA) printf("WRITE(%08x)=%08x\n", ADDR, DATA); array[ADDR] = (DATA)
++ #define SDRAM_READ(ADDR, VAR) printf("READ (%08x)=%08x\n", ADDR, array[ADDR]); *((volatile unsigned int *)(VAR)) = array[ADDR]
++ #endif
++ unsigned volatile int array[SDRAM_TOP];
++#endif
++
++
++#define SYSCTRL_PRIMSEL_LO 0x4500000C
++#define SYSCTRL_SECSEL_LO 0x45000014
++#define SYSCTRL_TERSEL_LO 0x4500008C
++#define SYSCTRL_PRIMSEL_HI 0x45000010
++#define SYSCTRL_SECSEL_HI 0x45000018
++#define SYSCTRL_TERSEL_HI 0x45000090
++
++/* GPIO */
++#define GPIOB_IO_VAL 0x44100000
++#define GPIOB_OE_VAL 0x44100004
++#define GPIOB_SET_OE 0x4410001C
++#define GPIOB_CLEAR_OE 0x44100020
++#define GPIOB_OUTPUT_VAL 0x44100010
++#define GPIOB_SET_OUTPUT 0x44100014
++#define GPIOB_CLEAR_OUTPUT 0x44100018
++#define GPIOB_BIT_34 0x00000004
++
++void configure_caches(void);
++void report_err(unsigned int address, unsigned int bad_data, unsigned int correct_data, unsigned int iteration);
++
++/********************* TYPES.H ********************************************************/
++
++typedef unsigned int UINT, *PUINT;
++/*
++#ifndef __MY_BASIC_TYPES_H
++#define __MY_BASIC_TYPES_H
++
++typedef signed char CHAR, *PCHAR;
++typedef unsigned char BYTE, UCHAR, *PBYTE, *PUCHAR;
++typedef signed short SHORT, *PSHORT;
++typedef unsigned short WORD, USHORT, *PWORD, *PUSHORT;
++typedef signed long LONG, *PLONG;
++typedef unsigned long DWORD, *PDWORD;
++typedef int BOOL, *PBOOL;
++typedef unsigned int UINT, *PUINT;
++typedef void VOID, *PVOID;
++
++typedef float SINGLE,*PSINGLE;
++typedef double DOUBLE,*PDOUBLE;
++
++
++#define FALSE 0
++#define TRUE 1
++
++#endif
++*/
++
++/********************* CHIP.H ********************************************************/
++
++// Address Map
++#define BOOT_ROM_BASE 0x00000000
++#define USBHS_BASE 0x00200000
++#define GMAC_BASE 0x00400000
++#define PCI_BASE 0x00600000
++#define PCI_DATA_BASE 0x00800000
++#define STATIC0_BASE 0x01000000
++#define STATIC1_BASE 0x01400000
++#define STATIC2_BASE 0x01800000
++#define STATIC_BASE 0x01C00000
++#define SATA_DATA_BASE 0x02000000
++#define DPE_DATA_BASE 0x03000000
++#define GPIOA_BASE 0x04000000
++#define GPIOB_BASE 0x04100000
++#define UARTA_BASE 0x04200000
++#define UARTB_BASE 0x04300000
++#define I2C_MASTER_BASE 0x04400000
++#define AUDIO_BASE 0x04500000
++#define FAN_BASE 0x04600000
++#define PWM_BASE 0x04700000
++#define IR_RX_BASE 0x04800000
++#define UARTC_BASE 0x04900000
++#define UARTD_BASE 0x04A00000
++#define SYS_CTRL_BASE 0x05000000
++#define RPSA_BASE 0x05300000
++#define ARM_RPS_BASE RPSA_BASE
++#define RPSC_BASE 0x05400000
++#define AHB_MON_BASE 0x05500000
++#define DMA_BASE 0x05600000
++#define DPE_BASE 0x05700000
++#define IBIW_BASE 0x05780000
++#define DDR_BASE 0x05800000
++#define SATA0_BASE 0x05900000
++#define SATA1_BASE 0x05980000
++#define DMA_CHKSUM_BASE 0x05A00000
++#define COPRO_BASE 0x05B00000
++#define SGDMA_BASE 0x05C00000
++#define DDR_DATA_BASE 0x08000000
++#define SRAM_BASE 0x0C000000
++#define SRAM0_BASE 0x0C000000
++#define SRAM1_BASE 0x0C002000
++#define SRAM2_BASE 0x0C004000
++#define SRAM3_BASE 0x0C006000
++
++// Virtual peripheral for TB sync
++#define TB_SYNC_BASE 0x05F00100
++
++
++/********************* DMA.H ********************************************************/
++
++
++// DMA Control register settings
++
++#define DMA_FAIR_SHARE (1<<0)
++#define DMA_IN_PROGRESS (1<<1)
++
++#define DMA_SDREQ_SATA (0<<2)
++#define DMA_SDREQ_DPE_OUT (2<<2)
++#define DMA_SDREQ_UARTA_RX (4<<2)
++#define DMA_SDREQ_AUDIO_RX (6<<2)
++#define DMA_SDREQ_MEM (0xF<<2)
++
++#define DMA_DDREQ_SATA (0<<6)
++#define DMA_DDREQ_DPE_IN (1<<6)
++#define DMA_DDREQ_UARTA_TX (3<<6)
++#define DMA_DDREQ_AUDIO_TX (5<<6)
++#define DMA_DDREQ_MEM (0xF<<6)
++
++#define DMA_INTERRUPT (1 << 10)
++#define DMA_NEXT_FREE (1 << 11)
++#define DMA_CH_RESET (1 << 12)
++
++#define DMA_DIR_ATOA (0 << 13)
++#define DMA_DIR_BTOA (1 << 13)
++#define DMA_DIR_ATOB (2 << 13)
++#define DMA_DIR_BTOB (3 << 13)
++
++#define DMA_BURST_A (1 << 17)
++#define DMA_BURST_B (1 << 18)
++
++#define DMA_SWIDTH_8 (0 << 19)
++#define DMA_SWIDTH_16 (1 << 19)
++#define DMA_SWIDTH_32 (2 << 19)
++
++#define DMA_DWIDTH_8 (0 << 22)
++#define DMA_DWIDTH_16 (1 << 22)
++#define DMA_DWIDTH_32 (2 << 22)
++
++#define DMA_PAUSE (1 << 25)
++#define DMA_INT_ENABLE (1 << 26)
++#define DMA_STARVE_LO_PRIORITY (1 << 29)
++#define DMA_NEW_INT_CLEAR (1 << 30)
++
++#define DMA_FIXED_SADDR ((0 << 15) | (1 << 27))
++#define DMA_INCR_SADDR ((1 << 15) | (0 << 27))
++#define DMA_SEMI_FIXED_SADDR ((0 << 15) | (0 << 27))
++
++#define DMA_FIXED_DADDR ((0 << 16) | (1 << 28))
++#define DMA_INCR_DADDR ((1 << 16) | (0 << 28))
++#define DMA_SEMI_FIXED_DADDR ((0 << 16) | (0 << 28))
++
++#define DMA_BASE_CTRL (DMA_BURST_A | DMA_BURST_B | DMA_INT_ENABLE | DMA_NEW_INT_CLEAR)
++
++// Common base setups
++
++#define DMA_CTRL_A32TOA32 ( DMA_BASE_CTRL | DMA_DIR_ATOA | DMA_SWIDTH_32 | DMA_DWIDTH_32 )
++#define DMA_CTRL_B32TOA32 ( DMA_BASE_CTRL | DMA_DIR_BTOA | DMA_SWIDTH_32 | DMA_DWIDTH_32 )
++#define DMA_CTRL_A32TOB32 ( DMA_BASE_CTRL | DMA_DIR_ATOB | DMA_SWIDTH_32 | DMA_DWIDTH_32 )
++#define DMA_CTRL_B32TOB32 ( DMA_BASE_CTRL | DMA_DIR_BTOB | DMA_SWIDTH_32 | DMA_DWIDTH_32 )
++
++#define DMA_CTRL_A8TOB32 ( DMA_BASE_CTRL | DMA_DIR_ATOB | DMA_SWIDTH_8 | DMA_DWIDTH_32 )
++#define DMA_CTRL_B32TOA8 ( DMA_BASE_CTRL | DMA_DIR_BTOA | DMA_SWIDTH_32 | DMA_DWIDTH_8 )
++#define DMA_CTRL_A32TOB8 ( DMA_BASE_CTRL | DMA_DIR_ATOB | DMA_SWIDTH_32 | DMA_DWIDTH_8 )
++
++// Most likely transactions
++
++#define DMA_CTRL_MEM_TO_MEM_AA ( DMA_CTRL_A32TOA32 | DMA_SDREQ_MEM | DMA_DDREQ_MEM | DMA_INCR_SADDR | DMA_INCR_DADDR )
++#define DMA_CTRL_MEM_TO_MEM_AB ( DMA_CTRL_A32TOB32 | DMA_SDREQ_MEM | DMA_DDREQ_MEM | DMA_INCR_SADDR | DMA_INCR_DADDR )
++#define DMA_CTRL_MEM_TO_MEM_BB ( DMA_CTRL_B32TOB32 | DMA_SDREQ_MEM | DMA_DDREQ_MEM | DMA_INCR_SADDR | DMA_INCR_DADDR )
++#define DMA_CTRL_MEM_TO_MEM_BA ( DMA_CTRL_B32TOA32 | DMA_SDREQ_MEM | DMA_DDREQ_MEM | DMA_INCR_SADDR | DMA_INCR_DADDR )
++#define DMA_CTRL_MEM_TO_MEM ( DMA_CTRL_MEM_TO_MEM_AB )
++
++//DMA A-A
++#define DMA_CTRL_SATA_TO_MEM_AA ( DMA_CTRL_A32TOA32 | DMA_SDREQ_SATA | DMA_DDREQ_MEM | DMA_INCR_SADDR | DMA_INCR_DADDR )
++#define DMA_CTRL_MEM_TO_SATA_AA ( DMA_CTRL_A32TOA32 | DMA_SDREQ_MEM | DMA_DDREQ_SATA | DMA_INCR_SADDR | DMA_INCR_DADDR )
++
++#define DMA_CTRL_SATA_TO_MEM ( DMA_CTRL_A32TOB32 | DMA_SDREQ_SATA | DMA_DDREQ_MEM | DMA_INCR_SADDR | DMA_INCR_DADDR )
++#define DMA_CTRL_MEM_TO_SATA ( DMA_CTRL_B32TOA32 | DMA_SDREQ_MEM | DMA_DDREQ_SATA | DMA_INCR_SADDR | DMA_INCR_DADDR )
++#define DMA_CTRL_SATA_TO_DPE ( DMA_CTRL_A32TOA32 | DMA_SDREQ_SATA | DMA_DDREQ_DPE_IN | DMA_INCR_SADDR | DMA_INCR_DADDR )
++#define DMA_CTRL_DPE_TO_SATA ( DMA_CTRL_A32TOA32 | DMA_SDREQ_DPE_OUT | DMA_DDREQ_SATA | DMA_INCR_SADDR | DMA_INCR_DADDR )
++#define DMA_CTRL_MEM_TO_DPE ( DMA_CTRL_B32TOA32 | DMA_SDREQ_MEM | DMA_DDREQ_DPE_IN | DMA_INCR_SADDR | DMA_INCR_DADDR )
++#define DMA_CTRL_DPE_TO_MEM ( DMA_CTRL_A32TOB32 | DMA_SDREQ_DPE_OUT | DMA_DDREQ_MEM | DMA_INCR_SADDR | DMA_INCR_DADDR )
++#define DMA_CTRL_PCI_TO_MEM ( DMA_CTRL_A32TOB32 | DMA_SDREQ_MEM | DMA_DDREQ_MEM | DMA_INCR_SADDR | DMA_INCR_DADDR )
++
++#define DMA_CTRL_MEM_TO_PCI ( DMA_CTRL_B32TOA32 | DMA_SDREQ_MEM | DMA_DDREQ_MEM | DMA_INCR_SADDR | DMA_INCR_DADDR )
++#define DMA_CTRL_MEM_TO_AUDIO ( DMA_CTRL_B32TOA32 | DMA_SDREQ_MEM | DMA_DDREQ_AUDIO_TX | DMA_INCR_SADDR | DMA_FIXED_DADDR )
++#define DMA_CTRL_AUDIO_TO_MEM ( DMA_CTRL_A32TOB32 | DMA_SDREQ_AUDIO_RX | DMA_DDREQ_MEM | DMA_FIXED_SADDR | DMA_INCR_DADDR )
++#define DMA_CTRL_MEM_TO_UART ( DMA_CTRL_B32TOA8 | DMA_SDREQ_MEM | DMA_DDREQ_UARTA_TX | DMA_INCR_SADDR | DMA_FIXED_DADDR )
++#define DMA_CTRL_UART_TO_MEM ( DMA_CTRL_A8TOB32 | DMA_SDREQ_UARTA_RX | DMA_DDREQ_MEM | DMA_FIXED_SADDR | DMA_INCR_DADDR )
++
++// Byte count register flags
++
++#define DMA_HBURST_EN (1<<28)
++#define DMA_WR_BUFFERABLE (1<<29)
++#define DMA_WR_EOT (1<<30)
++#define DMA_RD_EOT (1<<31)
++
++
++// Pause the DMA channel specified
++void PauseDMA( UINT channel );
++
++// UnPause the DMA channel specified
++void UnPauseDMA( UINT channel );
++
++// Configure a DMA
++void SetupDMA( UINT channel,
++ UINT src_addr,
++ UINT dest_addr,
++ UINT byte_count,
++ UINT control,
++ UINT flags );
++
++// Wait while the given DMA channel is busy
++void WaitWhileDMABusy( UINT channel );
++
++// Perform a memory to memory copy
++void DMAMemCopy ( UINT channel,
++ UINT src_addr,
++ UINT dest_addr,
++ UINT byte_count );
++
++
++/****************************** MAIN ***********************************************/
++#ifdef ARM
++int mem_test(int argc, char* argv[])
++#else
++int main(int argc, char* argv[])
++#endif
++{
++ unsigned int i;
++ unsigned int iteration;
++ unsigned int block_base;
++ unsigned int datapattern;
++ unsigned int correct_data;
++ unsigned volatile int read_data;
++ unsigned int pattype, starting_pattype;
++ unsigned int end_addr;
++ unsigned int row, col, bank;
++
++#ifdef ARM
++ /* Print the ABI version */
++ app_startup(argv);
++ printf ("Example expects ABI version %d\n", XF_VERSION);
++ printf ("Actual U-Boot ABI version %d\n", (int)get_version());
++
++ printf("GPIO34 is output, low\n");
++ * (volatile unsigned int *) GPIOB_CLEAR_OUTPUT = GPIOB_BIT_34;
++ * (volatile unsigned int *) GPIOB_SET_OE = GPIOB_BIT_34;
++#endif
++
++// configure_caches();
++//printf("Caches enabled\n");
++
++ /* ******************************************************************* */
++ printf("DMA TEST.\n" );
++ /* ******************************************************************* */
++
++
++ #define DMA0_CTRL_STAT 0x45A00000
++ #define DMA0_SRC_BASE 0x45A00004
++ #define DMA0_DEST_BASE 0x45A00008
++ #define DMA0_BYTE_COUNT 0x45A0000C
++ #define DMA0_CURRENT_BYTE 0x45A00018
++
++ printf("Test to top of 1st SDRAM" );
++ #define BLOCK_BYTES 0x20000
++ #define SDRAM_STOP SDRAM_TOP
++
++ for (iteration=0; 1; iteration++) {
++
++ if ((iteration % 5)==0)
++ printf("Iteration %d\n", iteration );
++
++// printf("Write pattern into first block.\n" );
++ end_addr = SDRAM_BASE + BLOCK_BYTES;
++ for (i=SDRAM_BASE; i < end_addr; i=i+4) {
++ SDRAM_WRITE( i, i);
++ }
++
++// printf("Clear last block and a few blocks more - easy to see on LA.\n" );
++ end_addr = SDRAM_BASE + (BLOCK_BYTES << 3);
++ for (i=SDRAM_STOP - BLOCK_BYTES; i < end_addr; i=i+4) {
++ SDRAM_WRITE( i, 0);
++ }
++
++ end_addr = SDRAM_STOP - BLOCK_BYTES;
++ for (i=SDRAM_BASE; i < end_addr; i=i+BLOCK_BYTES) {
++
++// printf("DMA transfer from %08x to %08x.\n", i, i + BLOCK_BYTES );
++#ifdef ARM
++ DMAMemCopy ( 0, i, i + BLOCK_BYTES, BLOCK_BYTES );
++#endif
++// printf("...pending.\n" );
++#ifdef ARM
++ WaitWhileDMABusy( 0 );
++#endif
++// printf("...complete.\n" );
++ }
++
++// printf("Verify pattern in last block.\n" );
++ end_addr = SDRAM_STOP;
++ correct_data = SDRAM_BASE;
++ for (i=SDRAM_STOP - BLOCK_BYTES; i < end_addr; i=i+4) {
++ SDRAM_READ( i, &read_data);
++ if (read_data != correct_data)
++ {
++ /* Expand out the report_err function to avoid the stack operations. */
++ #ifdef ARM
++ /* ASSERT GPIO */
++ * (volatile unsigned int *) GPIOB_SET_OUTPUT = GPIOB_BIT_34;
++ #endif
++
++ /* REPORT ERROR */
++ printf("Wrong on [%08x]= %08x should be %08x on iteration %d\n", i, read_data, correct_data, iteration );
++
++ /* WRITE TO ANOTHER LOCATION */
++ SDRAM_WRITE(SDRAM_BASE, 0xFFFFFFFF);
++
++ /* READ AGAIN */
++ SDRAM_READ(i, &read_data);
++ if (read_data != correct_data)
++ printf("Again 1 [%08x]= %08x should be %08x\n", i, read_data, correct_data );
++
++ /* WRITE TO ANOTHER LOCATION */
++ SDRAM_WRITE(SDRAM_BASE, 0xFFFFFFFF);
++
++ /* READ AGAIN */
++ SDRAM_READ(i, &read_data);
++ if (read_data != correct_data)
++ printf("Again 2 [%08x]= %08x should be %08x\n", i, read_data, correct_data );
++
++ /* WRITE TO ANOTHER LOCATION */
++ SDRAM_WRITE(SDRAM_BASE, 0xFFFFFFFF);
++
++ /* READ AGAIN */
++ SDRAM_READ(i, &read_data);
++ if (read_data != correct_data)
++ printf("Again 3 [%08x]= %08x should be %08x\n", i, read_data, correct_data );
++
++ row = (((i >> 26) & 0x1) << 13) | (((i >> 23) & 0x3) << 11) | ((i >> 10) & 0x7FF); /* [26], [24:23], [20:10]*/
++ col = (((i >> 27) & 0x1) << 10) | (((i >> 25) & 0x1) << 9) | (((i >> 22) & 0x1) << 8); /* [27], [25], [22]... */
++ col |= (((i >> 6) & 0xF) << 4) | (((i >> 21) & 0x1) << 3) | (((i >> 1) & 0x3) << 1); /* ...[9:8], [21], [3:2], '0' */
++ col |= 0x800; /* bit 11 set for auto-precharge */
++ bank = (i >> 4) & 0x3; /* [5:4] */
++ printf("Bank %08x\n", bank );
++ printf("Row %08x\n", row );
++ printf("Column %08x\n", col );
++ #ifdef ARM
++ /* DEASSERT GPIO */
++ * (volatile unsigned int *) GPIOB_CLEAR_OUTPUT = GPIOB_BIT_34;
++ #endif
++ }
++
++
++ correct_data += 4;
++ }
++ }
++
++
++ /* ******************************************************************* */
++ printf("MEM_TEST2\n");
++ /* ******************************************************************* */
++
++
++ pattype=0;
++ iteration=0;
++
++ for (;;) {
++ /* FOR EACH 64Kword==256KB BLOCK IN 16Mword=64MB (2 OFF 16M16) MEMORY... */
++
++#ifdef SHORT
++ if ((iteration % 5)==0)
++ printf("Iteration %d\n", iteration );
++#else
++ if ((iteration % 1000)==0)
++ printf("Iteration %d\n", iteration );
++#endif
++
++ /* WRITE DATA BLOCKS */
++ starting_pattype = pattype; /* Record for later */
++
++ for (block_base=SDRAM_BASE; block_base < SDRAM_TOP; block_base=block_base + BLOCKSIZE) {
++ switch (pattype) {
++ case PATTYPE_A5 :
++ /* Write alternating 1s and 0s... */
++ end_addr = block_base + BLOCKWORDS;
++ for (i=block_base; i < end_addr; i=i+4) {
++ SDRAM_WRITE( i, 0xaa55aa55);
++ }
++ break;
++ case PATTYPE_5A :
++ /* Write alternating 1s and 0s (inverse of above)... */
++ end_addr = block_base + BLOCKWORDS;
++ for (i=block_base; i < end_addr; i=i+4) {
++ SDRAM_WRITE( i, 0x55aa55aa);
++ }
++ break;
++ case PATTYPE_NO_FF :
++ /* Write data=address with bit[n+16]=~bit[n]... */
++ datapattern = 0x0100FEFF;
++ /* In range 0x0100...0xFEFF so that
++ a. temp[15:8] is never 0xFF
++ b. Inverse of temp[15:8] is never 0xFF
++ */
++ end_addr = block_base + BLOCKWORDS;
++ for (i=block_base; i < end_addr; i=i+4) {
++ SDRAM_WRITE( i, datapattern);
++ datapattern = datapattern + 0xFFFF;
++ }
++ break;
++ case PATTYPE_INCR :
++ /* Write data=address... */
++ end_addr = block_base + BLOCKSIZE;
++ for (i=block_base; i < end_addr; i=i+4) {
++ SDRAM_WRITE( i, i);
++ }
++ break;
++ case PATTYPE_DECR :
++ /* Write data=~address... */
++ end_addr = block_base + BLOCKSIZE;
++ for (i=block_base; i < end_addr; i=i+4) {
++ SDRAM_WRITE( i, ~i);
++ }
++ break;
++ }
++ }
++
++ /* VERIFY DATA BLOCKS */
++ pattype = starting_pattype; /* Reset to same as for writes */
++
++ for (block_base=SDRAM_BASE; block_base < SDRAM_TOP; block_base=block_base + BLOCKSIZE) {
++ switch (pattype) {
++ case PATTYPE_A5 :
++ correct_data = 0xaa55aa55;
++ end_addr = block_base + BLOCKWORDS;
++ for (i=block_base; i < end_addr; i=i+4) {
++ SDRAM_READ( i, &read_data);
++ if (read_data != correct_data)
++ report_err(i, read_data, correct_data, iteration);
++ }
++ break;
++ case PATTYPE_5A :
++ correct_data = 0x55aa55aa;
++ end_addr = block_base + BLOCKWORDS;
++ for (i=block_base; i < end_addr; i=i+4) {
++ SDRAM_READ( i, &read_data);
++ if (read_data != correct_data)
++ report_err(i, read_data, correct_data, iteration);
++ }
++ break;
++ case PATTYPE_NO_FF :
++ correct_data = 0x0100FEFF;
++ end_addr = block_base + BLOCKWORDS;
++ for (i=block_base; i < end_addr; i=i+4) {
++ SDRAM_READ( i, &read_data);
++ if (read_data != correct_data)
++ report_err(i, read_data, correct_data, iteration);
++ correct_data = correct_data + 0xFFFF;
++ }
++ break;
++ case PATTYPE_INCR :
++ end_addr = block_base + BLOCKSIZE;
++ for (i=block_base; i < end_addr; i=i+4) {
++ SDRAM_READ( i, &read_data);
++ if (read_data != i)
++ report_err(i, read_data, i, iteration);
++ }
++ break;
++ case PATTYPE_DECR :
++ end_addr = block_base + BLOCKSIZE;
++ for (i=block_base; i < end_addr; i=i+4) {
++ SDRAM_READ( i, &read_data);
++ if (read_data != ~i)
++ report_err(i, read_data, ~i, iteration);
++ }
++ break;
++ }
++ }
++
++ pattype = pattype + 1;
++ if (pattype >= NUM_PATTYPES) { pattype = 0; }
++ ++iteration;
++ }
++
++ return 0;
++}
++
++/********************* REPORT ERROR FUNC ********************************************************/
++
++void report_err(unsigned int address, unsigned int bad_data, unsigned int correct_data, unsigned int iteration)
++{
++ volatile unsigned int readvalue;
++
++#ifdef ARM
++ /* ASSERT GPIO */
++ * (volatile unsigned int *) GPIOB_SET_OUTPUT = GPIOB_BIT_34;
++#endif
++
++ /* REPORT ERROR */
++ printf("Wrong on [%08x]= %08x should be %08x on iteration %d\n", address, bad_data, correct_data, iteration );
++
++ /* WRITE TO ANOTHER LOCATION */
++ SDRAM_WRITE(SDRAM_BASE, 0xFFFFFFFF);
++
++ /* READ AGAIN */
++ SDRAM_READ(address, &readvalue);
++ if (readvalue != correct_data)
++ printf("Again 1 [%08x]= %08x should be %08x\n", address, readvalue, correct_data );
++
++ /* WRITE TO ANOTHER LOCATION */
++ SDRAM_WRITE(SDRAM_BASE, 0xFFFFFFFF);
++
++ /* READ AGAIN */
++ SDRAM_READ(address, &readvalue);
++ if (readvalue != correct_data)
++ printf("Again 2 [%08x]= %08x should be %08x\n", address, readvalue, correct_data );
++
++ /* WRITE TO ANOTHER LOCATION */
++ SDRAM_WRITE(SDRAM_BASE, 0xFFFFFFFF);
++
++ /* READ AGAIN */
++ SDRAM_READ(address, &readvalue);
++ if (readvalue != correct_data)
++ printf("Again 3 [%08x]= %08x should be %08x\n", address, readvalue, correct_data );
++
++#ifdef ARM
++ /* DEASSERT GPIO */
++ * (volatile unsigned int *) GPIOB_CLEAR_OUTPUT = GPIOB_BIT_34;
++#endif
++
++} /* end of report_err */
++
++
++
++
++/********************* DMA.C FUNCTIONS ********************************************************/
++
++void ResetDMA( UINT channel ) {
++
++ // Clear and abort the dma channel
++
++ volatile PUINT dma = (PUINT) (DMA_BASE + (channel << 5));
++ dma[0] = (1 << 12);
++ dma[0] &= ~(1 << 12);
++}
++
++
++
++
++void PauseDMA( UINT channel ) {
++
++ // Pause the DMA channel specified
++
++ volatile PUINT dma = (PUINT) (DMA_BASE + (channel << 5));
++ UINT rd;
++
++ rd = dma[0];
++
++ rd |= DMA_PAUSE;
++
++ dma[0] = rd;
++}
++
++
++
++
++void UnPauseDMA( UINT channel ) {
++
++ // UnPause the DMA channel specified
++
++ volatile PUINT dma = (PUINT) (DMA_BASE + (channel << 5));
++ UINT rd;
++
++ rd = dma[0];
++
++ rd &= ~DMA_PAUSE;
++
++ dma[0] = rd;
++}
++
++
++
++
++void SetupDMA( UINT channel,
++ UINT src_addr,
++ UINT dest_addr,
++ UINT byte_count,
++ UINT control,
++ UINT flags ) {
++
++ // Configure a DMA
++
++ volatile PUINT dma = (PUINT) (DMA_BASE + (channel << 5));
++
++ dma[0] = control;
++ dma[1] = src_addr;
++ dma[2] = dest_addr;
++ dma[3] = byte_count | (flags & 0xF0000000);
++}
++
++// EXAMPLE:
++//
++// DMA 2kB from SRAM to SATA core with a write EOT set, and HBURST enabled, using DMA channel 2
++// Then wait for the DMA to complete
++//
++// SetupDMA ( 2 , 0x4C001100, BASE_SATA, 2048, DMA_CTRL_MEM_TO_SATA, WR_EOT | DMA_HBURST_EN );
++// WaitWhileDMABusy( 2 );
++
++int DMABusy(UINT channel)
++{
++ volatile PUINT dma = (PUINT) (DMA_BASE + (channel << 5));
++ return (dma[0] & DMA_IN_PROGRESS ? 1 : 0);
++}
++
++
++void WaitWhileDMABusy( UINT channel ) // Wait while the given DMA channel is busy
++{
++ volatile PUINT dma = (PUINT) (DMA_BASE + (channel << 5));
++ while (dma[0] & DMA_IN_PROGRESS) ; // Do Nothing
++}
++
++void DMAClearIRQ(UINT channel)
++{
++ volatile PUINT dma = (PUINT) (DMA_BASE + (channel << 5));
++ dma[4] = 1; // write any value to offset 0x10 (16 / 4 => 4)
++
++}
++
++void DMAMemCopy ( UINT channel,
++ UINT src_addr,
++ UINT dest_addr,
++ UINT byte_count ) {
++
++ // Perform a memory to memory copy
++
++ volatile PUINT dma = (PUINT) (DMA_BASE + (channel << 5));
++
++ // Choose fastest configuration possible for required transfer
++
++ if (src_addr < SRAM_BASE) {
++ if (dest_addr < SRAM_BASE) {
++ dma[0] = DMA_CTRL_MEM_TO_MEM_AA; // Src and Dest must use A
++ } else {
++ dma[0] = DMA_CTRL_MEM_TO_MEM_AB; // Src must use A
++ }
++ } else {
++ if (dest_addr < SRAM_BASE) {
++ dma[0] = DMA_CTRL_MEM_TO_MEM_BA; // Dest must use A
++ } else {
++ dma[0] = DMA_CTRL_MEM_TO_MEM_AB; // No restriction
++ }
++ }
++
++ dma[1] = src_addr;
++ dma[2] = dest_addr;
++ dma[3] = byte_count | DMA_WR_BUFFERABLE | DMA_HBURST_EN;
++
++ WaitWhileDMABusy( channel );
++}
++
++
++
++
++
++
++
++#define CP15R1_M_ENABLE 0x0001 // MMU Enable
++#define CP15R1_A_ENABLE 0x0002 // Address alignment fault enable
++#define CP15R1_C_ENABLE 0x0004 // (data) cache enable
++#define CP15R1_W_ENABLE 0x0008 // write buffer enable
++#define CP15R1_PROG32 0x0010 // PROG32
++#define CP15R1_DATA32 0x0020 // DATA32
++#define CP15R1_L_ENABLE 0x0040 // Late abort on earlier CPUs
++#define CP15R1_BIGEND 0x0080 // Big-endian (=1), little-endian (=0)
++#define CP15R1_SYSTEM 0x0100 // System bit, modifies MMU protections
++#define CP15R1_ROM 0x0200 // ROM bit, modifies MMU protections
++#define CP15R1_F 0x0400 // Should Be Zero
++#define CP15R1_Z_ENABLE 0x0800 // Branch prediction enable on 810
++#define CP15R1_I_ENABLE 0x1000 // Instruction cache enable
++#define CP15R1_RESERVED 0x00000078
++#define CP15R2_RESERVED 0xFFFFC000
++
++#define NUM_DOMAINS 16
++
++#define DAV_NO_ACCESS 0
++#define DAV_CLIENT 1
++#define DAV_RESERVED 2
++#define DAV_MANAGER 3
++#define NUM_DOMAIN_ACCESS_VALUES 4
++
++#define AP_LEVEL_0 0
++#define AP_LEVEL_1 0
++#define AP_LEVEL_2 0
++#define AP_LEVEL_3 0
++#define NUM_ACCESS_PERMISSIONS 4
++
++#define FAULT_ID 0
++
++#define FLD_COURSE_ID 1
++#define FLD_SECTION_ID 2
++#define FLD_FINE_ID 3
++
++#define FD_USER_DATA_BIT 2
++
++#define FD_USER_DATA_NUM_BITS 30
++
++#define SD_BUFFERABLE_BIT 2
++#define SD_CACHEABLE_BIT 3
++#define SD_IMP_BIT 4
++#define SD_DOMAIN_BIT 5
++#define SD_AP_BIT 10
++#define SD_ADDRESS_BIT 20
++
++#define SD_DOMAIN_NUM_BITS 4
++#define SD_AP_NUM_BITS 2
++
++void CoPro15Regs_SetCP15Reg1(const unsigned long mask) {
++ asm volatile(
++ "MOV r0, %0;"
++ "MRC p15, 0, r1, c1, c0, 0;"
++ "ORR r1,r1,r0;"
++ "MCR p15, 0, r1, c1, c0, 0;"
++ :
++ : "r" (mask | CP15R1_RESERVED)
++ : "r0","r1");
++}
++
++void CoPro15Regs_ClearCP15Reg1(const unsigned long mask) {
++ asm volatile(
++ "MOV r0, %0;"
++ "MRC p15, 0, r1, c1, c0, 0;"
++ "BIC r1,r1,r0;"
++ "MCR p15, 0, r1, c1, c0, 0;"
++ :
++ : "r" (mask)
++ : "r0","r1");
++}
++
++unsigned long CoPro15Regs_GetCP15Reg1(const unsigned long mask) {
++ unsigned long value;
++ asm volatile(
++ "MRC p15, 0, r1, c1, c0, 0;"
++ "MOV r0, %1;"
++ "BIC %0,r1,r0; "
++ : "=r" (value)
++ : "r" (mask)
++ : "r0","r1");
++ return value;
++}
++
++unsigned long CoPro15Regs_GetCP15Reg2(void) {
++ unsigned long value;
++ asm volatile(
++ "MRC p15, 0, r0, c2, c0, 0;"
++ "MOV %0, r0;"
++ : "=r" (value)
++ :
++ : "r0");
++ return value & CP15R2_RESERVED;
++}
++
++unsigned long CoPro15Regs_GetCP15Reg3(void) {
++ unsigned long value;
++ asm volatile(
++ "MRC p15, 0, r0, c3, c0, 0;"
++ "MOV %0, r0;"
++ : "=r" (value)
++ :
++ : "r0");
++ return value;
++}
++
++void CoPro15Regs_SetCP15Reg3(unsigned long value) {
++ asm volatile(
++ "MOV r0, %0;"
++ "MCR p15, 0, r0, c3, c0, 0;"
++ :
++ : "r" (value)
++ : "r0");
++}
++
++void CoPro15Regs_SetCP15Reg2(unsigned long value) {
++ asm volatile(
++ "MOV r0, %0;"
++ "MCR p15, 0, r0, c2, c0, 0;"
++ :
++ : "r" (value & CP15R2_RESERVED)
++ : "r0");
++}
++
++void Cache_CleanDataCache(void)
++{
++ // Clean the data cache - usually precedes a data cache invalidation.
++ // Forces the data cache content to be written to main memory - only
++ // required if using write-back data cache
++ asm volatile(
++ "MOV r3,pc;"
++ "LDR r1, =0;"
++ " MOV r4,pc;"
++ " LDR r0, =0;"
++ " ORR r2, r1, r0;"
++ " MCR p15, 0, r2, c7, c10, 2 ;" // I (BHC) think that this should be c10, 2 not c14, 1 -- See ARM ARM
++ " ADD r0, r0, #0x10;"
++ " CMP r0,#0x40;"
++ " BXNE r4;"
++ " ADD r1, r1, #0x04000000;"
++ " CMP r1, #0x0;"
++ "BXNE r3;"
++ :
++ :
++ : "r0","r1","r2","r3","r4");
++}
++
++void Cache_DrainWriteBuffer(void)
++{
++ // Forces the write buffer to update to main memory
++ asm volatile(
++ "LDR r1, =0;"
++ "MCR p15, 0, r1, c7, c10, 4 ;"
++ :
++ :
++ : "r1");
++}
++
++void Cache_FlushPrefetchBuffer(void)
++{
++ // Forces the CPU to flush the instruction prefetch buffer
++ asm volatile(
++ "LDR r1, =0;"
++ "MCR p15, 0, r1, c7, c5, 4 ;"
++ :
++ :
++ : "r1");
++}
++
++void Cache_InvalidateDataCache(void)
++{
++ asm volatile(
++ "LDR r1, =0;"
++ "MCR p15, 0, r1, c7, c6, 0;"
++ :
++ :
++ : "r1");
++}
++
++void Cache_InvalidateInstructionCache(void)
++{
++ asm volatile(
++ "LDR r1, =0;"
++ "MCR p15, 0, r1, c7, c5, 0;"
++ :
++ :
++ : "r1");
++}
++
++void Cache_InstOn(void)
++{
++ // Invalidate the instruction cache, in case there's anything
++ // left from when it was last enabled
++ Cache_InvalidateInstructionCache();
++
++ // Enable the instruction cache
++ CoPro15Regs_SetCP15Reg1(CP15R1_I_ENABLE);
++}
++
++void Cache_InstOff(void)
++{
++ // Disable the instruction cache
++ CoPro15Regs_ClearCP15Reg1(CP15R1_I_ENABLE);
++}
++
++void Cache_DataOn(void)
++{
++ // Invalidate the data cache, in case there's anything left from when
++ // it was last enabled
++ Cache_InvalidateDataCache();
++
++ // Enable the data cache
++ CoPro15Regs_SetCP15Reg1(CP15R1_C_ENABLE);
++}
++
++void Cache_DataOff(void)
++{
++ // Ensure all data in data cache or write buffer is written to memory
++ Cache_CleanDataCache();
++ Cache_DrainWriteBuffer();
++
++ // Disable the data cache
++ CoPro15Regs_ClearCP15Reg1(CP15R1_C_ENABLE);
++}
++
++void Cache_WriteBufferOn(void)
++{
++ // Enable the write buffer
++ CoPro15Regs_SetCP15Reg1(CP15R1_W_ENABLE);
++}
++
++void Cache_WriteBufferOff(void)
++{
++ // Ensure all data in the write buffer is written to memory
++ Cache_DrainWriteBuffer();
++
++ // Disable the write buffer
++ CoPro15Regs_ClearCP15Reg1(CP15R1_W_ENABLE);
++}
++
++int MMU_SetDomainAccessValue(
++ int domainNumber,
++ int value) {
++ int status = 0;
++ if ((value < NUM_DOMAIN_ACCESS_VALUES) && (domainNumber < NUM_DOMAINS))
++ {
++ // Insert the 2-bit domain field into the slot for the specified domain
++ unsigned long registerContents = CoPro15Regs_GetCP15Reg3();
++ registerContents &= ~(3UL << (2*domainNumber));
++ registerContents |= ((unsigned long)value << (2*domainNumber));
++ CoPro15Regs_SetCP15Reg3(registerContents);
++ status = 1;
++ }
++ return status;
++}
++
++void MMU_SetAlignmentChecked(int alignmentChecked) {
++ alignmentChecked ? CoPro15Regs_SetCP15Reg1(CP15R1_A_ENABLE) : CoPro15Regs_ClearCP15Reg1(CP15R1_A_ENABLE);
++}
++
++void MMU_SetEnabled(int enabled) {
++ enabled ? CoPro15Regs_SetCP15Reg1(CP15R1_M_ENABLE) : CoPro15Regs_ClearCP15Reg1(CP15R1_M_ENABLE);
++}
++void MMU_InvalidateDataTLB(void)
++{
++ asm volatile(
++ "MCR p15, 0, r0, c8, c6, 0;"
++ :
++ :
++ : "r0");
++}
++
++void MMU_InvalidateInstructionTLB(void)
++{
++ asm volatile(
++ "MCR p15, 0, r0, c8, c5, 0;"
++ :
++ :
++ : "r0");
++}
++
++void MMU_SetROMPermission(int rOM_Permitted) {
++ rOM_Permitted ? CoPro15Regs_SetCP15Reg1(CP15R1_ROM) : CoPro15Regs_ClearCP15Reg1(CP15R1_ROM);
++}
++
++void MMU_SetSystemPermission(int systemPermitted) {
++ systemPermitted ? CoPro15Regs_SetCP15Reg1(CP15R1_SYSTEM) : CoPro15Regs_ClearCP15Reg1(CP15R1_SYSTEM);
++}
++
++void MMU_SetTranslationTableBaseAddress(unsigned long *baseAddress) {
++ CoPro15Regs_SetCP15Reg2((unsigned long)baseAddress);
++}
++
++unsigned long SetBit(
++ unsigned long source,
++ int state,
++ int offset)
++{
++ source = state ? (source | (1UL << offset)) :
++ (source & ~(1UL << offset));
++ return source;
++}
++
++unsigned long SetField(
++ unsigned long source,
++ unsigned long newFieldContents,
++ int offset,
++ int length)
++{
++ unsigned long mask = (1UL << length) - 1;
++ source &= ~(mask << offset);
++ source |= ((newFieldContents & mask) << offset);
++ return source;
++}
++
++unsigned long FD_SetUserData(
++ unsigned long userData,
++ unsigned long descriptor)
++{
++ return SetField(descriptor, userData, FD_USER_DATA_BIT, FD_USER_DATA_NUM_BITS);
++}
++
++unsigned long FLPT_CreateFaultDescriptor(unsigned long userData)
++{
++ unsigned long descriptor = FAULT_ID;
++ descriptor = FD_SetUserData(userData, descriptor);
++ return descriptor;
++}
++
++void FLPT_InsertFaultDescriptor(
++ unsigned long *tableBaseAdr,
++ int index,
++ unsigned long descriptor)
++{
++ *(tableBaseAdr + index) = descriptor;
++}
++
++unsigned long SD_SetAccessPermission(
++ int ap,
++ unsigned long descriptor)
++{
++ return SetField(descriptor, ap, SD_AP_BIT, SD_AP_NUM_BITS);
++}
++
++unsigned long SD_SetBaseAddress(
++ unsigned long baseAddress,
++ unsigned long descriptor)
++{
++ unsigned long mask = ~0UL << SD_ADDRESS_BIT;
++ baseAddress &= mask;
++ descriptor &= ~mask;
++ descriptor |= baseAddress;
++ return descriptor;
++}
++
++unsigned long SD_SetBufferable(
++ int bufferable,
++ unsigned long descriptor)
++{
++ return SetBit(descriptor, bufferable, SD_BUFFERABLE_BIT);
++}
++
++unsigned long SD_SetCacheable(
++ int cacheable,
++ unsigned long descriptor)
++{
++ return SetBit(descriptor, cacheable, SD_CACHEABLE_BIT);
++}
++
++unsigned long SD_SetDomain(
++ int domain,
++ unsigned long descriptor)
++{
++ return SetField(descriptor, domain, SD_DOMAIN_BIT, SD_DOMAIN_NUM_BITS);
++}
++
++unsigned long SD_SetImplementationDefined(
++ unsigned long implementationDefined,
++ unsigned long descriptor)
++{
++ return SetBit(descriptor, implementationDefined, SD_IMP_BIT);
++}
++
++unsigned long FLPT_CreateSectionDescriptor(
++ unsigned long baseAddress,
++ unsigned char domain,
++ int implementationDefined,
++ int ap,
++ int bufferable,
++ int cacheable)
++{
++ unsigned long descriptor = FLD_SECTION_ID;
++ descriptor = SD_SetAccessPermission(ap, descriptor);
++ descriptor = SD_SetBaseAddress(baseAddress, descriptor);
++ descriptor = SD_SetBufferable(bufferable, descriptor);
++ descriptor = SD_SetCacheable(cacheable, descriptor);
++ descriptor = SD_SetDomain(domain, descriptor);
++ descriptor = SD_SetImplementationDefined(implementationDefined, descriptor);
++ return descriptor;
++}
++
++void FLPT_InsertSectionDescriptor(
++ unsigned long *tableBaseAdr,
++ int index,
++ unsigned long descriptor)
++{
++ *(tableBaseAdr + index) = descriptor;
++}
++
++void FLPT_Zeroise(
++ unsigned long *base_adr,
++ int numberOfdescriptors) {
++ unsigned long faultDescriptor = FLPT_CreateFaultDescriptor(0);
++ int i;
++ for (i=0; i < numberOfdescriptors; i++) {
++ FLPT_InsertFaultDescriptor(base_adr, i, faultDescriptor);
++ }
++}
++
++void configure_caches(void)
++{
++ // Disable caches
++// Cache_DataOff();
++printf("1");
++ Cache_InstOff();
++// Cache_WriteBufferOff();
++
++ // Disable MMU
++printf("2");
++ MMU_SetEnabled(0);
++printf("3");
++ MMU_InvalidateDataTLB();
++printf("4");
++ MMU_InvalidateInstructionTLB();
++
++ // Setup the MMU
++printf("5");
++ MMU_SetAlignmentChecked(1);
++printf("6");
++ MMU_SetROMPermission(0);
++printf("7");
++ MMU_SetSystemPermission(1);
++
++ // Allow client access to all protection domains
++ int i;
++ for (i=0; i < NUM_DOMAINS; i++) {
++ MMU_SetDomainAccessValue(i, DAV_CLIENT);
++ }
++printf("8");
++
++ // Allocate first level page table, which we'll populate only with section
++ // descriptors, which cover 1MB each. Table must be aligned to a 16KB
++ // boundary.
++ // We'll put it 4KB into the SRAM and it will occupy:
++ // 64 entries for SDRAM
++ // 1 entry for SRAM
++ // 16 entries for APB bridge A
++ // 16 entries for APB bridge B
++ // The largest memory address we need to map is that of the SRAM at
++ // 0x4c000000 -> (4c000000/2^20)*4 = offset 1300h from table start ->
++ // require at least 1300h/4 +1 entries in table = 1217
++ unsigned long *firstLevelPageTableBaseAdr = (unsigned long*)SRAM_BASE;
++ FLPT_Zeroise(firstLevelPageTableBaseAdr, 4096);
++printf("9");
++
++ // Map entire adr space uncached, unbuffered, read/write, virtual == physical
++ unsigned megabytesPresent = 4096;
++ unsigned index = 0;
++ for (i=0; i < megabytesPresent; i++) {
++ FLPT_InsertSectionDescriptor(
++ firstLevelPageTableBaseAdr,
++ index,
++ FLPT_CreateSectionDescriptor(
++ index * 1024 * 1024, // Base address
++ 0, // Domain number
++ 0, // Implementation defined
++ AP_LEVEL_1, // Access permissions
++ 0, // Bufferable
++ 0)); // Cacheable
++
++ ++index;
++ }
++printf("10");
++
++ // Map SDRAM as cached and buffered, read/write, virtual == physical
++ megabytesPresent = 64;
++ index = PHYS_SDRAM_1_PA / (1024 * 1024);
++ for (i=0; i < megabytesPresent; i++) {
++ FLPT_InsertSectionDescriptor(
++ firstLevelPageTableBaseAdr,
++ index,
++ FLPT_CreateSectionDescriptor(
++ index * 1024 * 1024, // Base address
++ 0, // Domain number
++ 0, // Implementation defined
++ AP_LEVEL_1, // Access permissions
++ 1, // Bufferable
++ 1)); // Cacheable
++
++ ++index;
++ }
++printf("11");
++
++ // Map SRAM as cached and buffered, read/write, virtual == physical
++ megabytesPresent = 1; // Actually only 32KB
++ index = SRAM_BASE / (1024 * 1024);
++ for (i=0; i < megabytesPresent; i++) {
++ FLPT_InsertSectionDescriptor(
++ firstLevelPageTableBaseAdr,
++ index,
++ FLPT_CreateSectionDescriptor(
++ index * 1024 * 1024, // Base address
++ 0, // Domain number
++ 0, // Implementation defined
++ AP_LEVEL_1, // Access permissions
++ 1, // Bufferable
++ 1)); // Cacheable
++
++ ++index;
++ }
++printf("12");
++
++ // Map APB bridge A address space as uncached, unbuffered, read/write,
++ // virtual == physical
++ megabytesPresent = 16;
++ index = APB_BRIDGE_A_BASE_PA / (1024 * 1024);
++ for (i=0; i < megabytesPresent; i++) {
++ FLPT_InsertSectionDescriptor(
++ firstLevelPageTableBaseAdr,
++ index,
++ FLPT_CreateSectionDescriptor(
++ index * 1024 * 1024, // Base address
++ 0, // Domain number
++ 0, // Implementation defined
++ AP_LEVEL_1, // Access permissions
++ 0, // Bufferable
++ 0)); // Cacheable
++
++ ++index;
++ }
++printf("13");
++
++ // Map APB bridge B address space as uncached, unbuffered, read/write,
++ // virtual == physical
++ megabytesPresent = 16;
++ index = APB_BRIDGE_B_BASE_PA / (1024 * 1024);
++ for (i=0; i < megabytesPresent; i++) {
++ FLPT_InsertSectionDescriptor(
++ firstLevelPageTableBaseAdr,
++ index,
++ FLPT_CreateSectionDescriptor(
++ index * 1024 * 1024, // Base address
++ 0, // Domain number
++ 0, // Implementation defined
++ AP_LEVEL_1, // Access permissions
++ 0, // Bufferable
++ 0)); // Cacheable
++
++ ++index;
++ }
++printf("14");
++
++ // Load base address of first level page table
++ MMU_SetTranslationTableBaseAddress(firstLevelPageTableBaseAdr);
++printf("15");
++
++ // Enable MMU
++ MMU_SetEnabled(1);
++printf("16");
++
++ // Enable caches
++ Cache_DataOn();
++printf("17");
++ Cache_InstOn();
++printf("18");
++ Cache_WriteBufferOn();
++printf("19");
++}
++
+diff -Nurd u-boot-1.1.2/include/asm-arm/barrier.h u-boot-1.1.2-oxe810/include/asm-arm/barrier.h
+--- u-boot-1.1.2/include/asm-arm/barrier.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-oxe810/include/asm-arm/barrier.h 2008-06-11 17:55:08.000000000 +0200
+@@ -0,0 +1,25 @@
++#if !defined(__BARRIER_H__)
++#define __BARRIER_H__
++
++static inline void rmb(void)
++{
++ asm volatile ("" : : : "memory");
++}
++
++/*
++ * wmb() Would normally need to ensure shared memory regions are marked as
++ * non-cacheable and non-bufferable, then the work to be done by wmb() is
++ * to ensure the compiler and any possible CPU out of order writes are
++ * flushed to memory, however we have no data cache and as far as I'm
++ * aware we can't use the MMU to set page properties, so in our case wmb()
++ * must cause the compiler to flush.
++ */
++
++static inline void wmb(void)
++{
++ // Cause the compiler to flush any registers containing pending write data
++ // to memory
++ asm volatile ("" : : : "memory");
++
++}
++#endif // #if !defined(__BARRIER_H__)
+diff -Nurd u-boot-1.1.2/include/asm-arm/global_data.h u-boot-1.1.2-oxe810/include/asm-arm/global_data.h
+--- u-boot-1.1.2/include/asm-arm/global_data.h 2003-10-10 12:05:43.000000000 +0200
++++ u-boot-1.1.2-oxe810/include/asm-arm/global_data.h 2008-06-11 17:55:08.000000000 +0200
+@@ -61,6 +61,7 @@
+ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
+ #define GD_FLG_SILENT 0x00004 /* Silent mode */
+
+-#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8")
++#define DECLARE_GLOBAL_DATA_PTR register gd_t* volatile gd asm ("r8");
+
+ #endif /* __ASM_GBL_DATA_H */
++
+diff -Nurd u-boot-1.1.2/include/asm-arm/mach-types.h u-boot-1.1.2-oxe810/include/asm-arm/mach-types.h
+--- u-boot-1.1.2/include/asm-arm/mach-types.h 2004-10-10 20:41:14.000000000 +0200
++++ u-boot-1.1.2-oxe810/include/asm-arm/mach-types.h 2008-06-11 17:55:08.000000000 +0200
+@@ -624,6 +624,7 @@
+ #define MACH_TYPE_RMS100 611
+ #define MACH_TYPE_KB9200 612
+ #define MACH_TYPE_SX1 613
++#define MACH_TYPE_OXNAS 1152
+
+ #ifdef CONFIG_ARCH_EBSA110
+ # ifdef machine_arch_type
+@@ -7945,6 +7946,18 @@
+ # define machine_is_sx1() (0)
+ #endif
+
++#ifdef CONFIG_MACH_OXNAS
++# ifdef machine_arch_type
++# undef machine_arch_type
++# define machine_arch_type __machine_arch_type
++# else
++# define machine_arch_type MACH_TYPE_OXNAS
++# endif
++# define machine_is_oxnas() (machine_arch_type == MACH_TYPE_OXNAS)
++#else
++# define machine_is_oxnas() (0)
++#endif
++
+ /*
+ * These have not yet been registered
+ */
+diff -Nurd u-boot-1.1.2/include/asm-arm/u-boot.h u-boot-1.1.2-oxe810/include/asm-arm/u-boot.h
+--- u-boot-1.1.2/include/asm-arm/u-boot.h 2002-11-03 01:33:10.000000000 +0100
++++ u-boot-1.1.2-oxe810/include/asm-arm/u-boot.h 2008-06-11 17:55:08.000000000 +0200
+@@ -41,6 +41,8 @@
+ ulong start;
+ ulong size;
+ } bi_dram[CONFIG_NR_DRAM_BANKS];
++ unsigned long bi_sramstart; /* start of SRAM memory */
++ unsigned long bi_sramsize; /* size of SRAM memory */
+ } bd_t;
+
+ #define bi_env_data bi_env->data
+diff -Nurd u-boot-1.1.2/include/ata.h u-boot-1.1.2-oxe810/include/ata.h
+--- u-boot-1.1.2/include/ata.h 2004-03-14 23:25:50.000000000 +0100
++++ u-boot-1.1.2-oxe810/include/ata.h 2008-06-11 17:55:11.000000000 +0200
+@@ -80,7 +80,12 @@
+ /*
+ * Device / Head Register Bits
+ */
++#ifdef CONFIG_OXNAS
++#define ATA_DEVICE(x) (0)
++#else
+ #define ATA_DEVICE(x) ((x & 1)<<4)
++#endif // CONFIG_OXNAS
++
+ #define ATA_LBA 0xE0
+
+ /*
+diff -Nurd u-boot-1.1.2/include/cmd_confdefs.h u-boot-1.1.2-oxe810/include/cmd_confdefs.h
+--- u-boot-1.1.2/include/cmd_confdefs.h 2004-12-16 18:59:53.000000000 +0100
++++ u-boot-1.1.2-oxe810/include/cmd_confdefs.h 2008-06-11 17:55:11.000000000 +0200
+@@ -92,6 +92,7 @@
+ #define CFG_CMD_XIMG 0x0400000000000000ULL /* Load part of Multi Image */
+ #define CFG_CMD_UNIVERSE 0x0800000000000000ULL /* Tundra Universe Support */
+ #define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */
++#define CFG_CMD_LEDFAIL 0x2000000000000000ULL /* OXNAS Failure LED support */
+
+ #define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFULL /* ALL commands */
+
+diff -Nurd u-boot-1.1.2/include/common.h u-boot-1.1.2-oxe810/include/common.h
+--- u-boot-1.1.2/include/common.h 2004-12-13 10:49:01.000000000 +0100
++++ u-boot-1.1.2-oxe810/include/common.h 2008-06-11 17:55:11.000000000 +0200
+@@ -204,7 +204,7 @@
+ /* common/cmd_nvedit.c */
+ int env_init (void);
+ void env_relocate (void);
+-char *getenv (uchar *);
++char *getenv (const uchar *);
+ int getenv_r (uchar *name, uchar *buf, unsigned len);
+ int saveenv (void);
+ #ifdef CONFIG_PPC /* ARM version to be fixed! */
+diff -Nurd u-boot-1.1.2/include/configs/oxnas.h u-boot-1.1.2-oxe810/include/configs/oxnas.h
+--- u-boot-1.1.2/include/configs/oxnas.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-oxe810/include/configs/oxnas.h 2008-06-12 13:57:57.000000000 +0200
+@@ -0,0 +1,593 @@
++/*
++ * (C) Copyright 2005
++ * Oxford Semiconductor Ltd
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#define readb(p) (*(volatile u8 *)(p))
++#define readl(p) (*(volatile u32 *)(p))
++#define writeb(v, p) (*(volatile u8 *)(p)= (v))
++#define writel(v, p) (*(volatile u32*)(p)=(v))
++
++#define CFG_FLASH_EMPTY_INFO
++
++/**
++ * Architecture
++ */
++#define CONFIG_ARM926EJS 1
++#define CONFIG_OXNAS 1
++#define CONFIG_OXNAS_ENABLE_PCI /* Enables PCI clock and takes out of reset - needed if require access to static bus */
++#define CONFIG_OXNAS_FEEDBACK_PCI_CLKS /* Feedback PCI clock out 3 to drive PCI core clock - needed if require access to static bus */
++#define CONFIG_OXNAS_MANUAL_STATIC_ARBITRATION
++#if (USE_SATA == 1)
++#define CONFIG_OXNAS_USE_SATA /* Define to include support for SATA disks */
++#if (USE_SATA_ENV == 1)
++#define ENV_ON_SATA /* Define to have the U-Boot env. stored on SATA disk */
++#endif // USE_SATA_ENV
++#endif // USE_SATA
++#if (USE_FLASH == 0)
++#define CFG_NO_FLASH /* Define to NOT include flash support on static bus*/
++#endif //USE_FLASH
++
++/* Won't be using any interrupts */
++#undef CONFIG_USE_IRQ
++
++/* Everything, incl board info, in Hz */
++#undef CFG_CLKS_IN_HZ
++
++#define CFG_HUSH_PARSER 1
++#define CFG_PROMPT_HUSH_PS2 "> "
++
++/* Miscellaneous configurable options */
++#define CFG_LONGHELP /* undef to save memory */
++#ifdef CFG_HUSH_PARSER
++#define CFG_PROMPT "$ " /* Monitor Command Prompt */
++#else
++#define CFG_PROMPT "# " /* Monitor Command Prompt */
++#endif
++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
++
++/* Print Buffer Size */
++#define CFG_PBSIZE ((CFG_CBSIZE)+sizeof(CFG_PROMPT)+16)
++#define CFG_MAXARGS 16 /* max number of command args */
++#define CFG_BARGSIZE (CFG_CBSIZE) /* Boot Argument Buffer Size */
++
++#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
++#define CONFIG_SETUP_MEMORY_TAGS 1
++#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */
++#define CONFIG_INITRD_TAG 1 /* allow initrd tag to be generated */
++
++/* May want to do some setup prior to relocation */
++#define CONFIG_INIT_CRITICAL
++
++/* ARM specific late initialisation */
++#define BOARD_LATE_INIT
++
++/**
++ * Stack sizes
++ *
++ * The stack sizes are set up in start.S using the settings below
++ */
++#define CONFIG_STACKSIZE (128*1024) /* regular stack */
++#ifdef CONFIG_USE_IRQ
++#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
++#endif
++
++/**
++ * RAM
++ */
++#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of SDRAM */
++#define PHYS_SDRAM_1_PA 0x48000000 /* SDRAM Bank #1 */
++#if (NAS_VERSION == 810)
++#define PHYS_SDRAM_1_MAX_SIZE (256 * 1024 * 1024)
++#endif // NAS_VERSION
++#define CFG_SRAM_BASE ((PHYS_SDRAM_1_PA) + (PHYS_SDRAM_1_MAX_SIZE))
++#if (NAS_VERSION == 810)
++#define CFG_SRAM_SIZE (128 * 1024)
++#endif // NAS_VERSION
++
++#define INITIALISE_SDRAM
++
++/* Default location from which bootm etc will load */
++#define CFG_LOAD_ADDR (PHYS_SDRAM_1_PA)
++
++/**
++ * Core addresses
++ */
++#define MAC_BASE_PA 0x40400000
++#define STATIC_CS0_BASE_PA 0x41000000
++#define STATIC_CS1_BASE_PA 0x41400000
++#define STATIC_CS2_BASE_PA 0x41800000
++#define STATIC_CONTROL_BASE_PA 0x41C00000
++#define SATA_DATA_BASE_PA 0x42000000
++
++#define APB_BRIDGE_A_BASE_PA 0x44000000
++#define APB_BRIDGE_B_BASE_PA 0x45000000
++
++#define GPIO_1_PA ((APB_BRIDGE_A_BASE_PA) + 0x0)
++#define GPIO_2_PA ((APB_BRIDGE_A_BASE_PA) + 0x100000)
++
++#define SYS_CONTROL_BASE_PA ((APB_BRIDGE_B_BASE_PA) + 0x0)
++#define DMA_BASE_PA ((APB_BRIDGE_B_BASE_PA) + 0x600000)
++#define RPS_BASE ((APB_BRIDGE_B_BASE_PA) + 0x300000)
++
++/* Static bus registers */
++#define STATIC_CONTROL_VERSION ((STATIC_CONTROL_BASE_PA) + 0x0)
++#define STATIC_CONTROL_BANK0 ((STATIC_CONTROL_BASE_PA) + 0x4)
++#define STATIC_CONTROL_BANK1 ((STATIC_CONTROL_BASE_PA) + 0x8)
++#define STATIC_CONTROL_BANK2 ((STATIC_CONTROL_BASE_PA) + 0xC)
++
++/* Clock to the ARM/DDR */
++#if (FPGA == 0)
++#define NOMINAL_ARMCLK ((PLL400) / 2)
++#define NOMINAL_SYSCLK ((PLL400) / 4)
++#else // !FPGA
++#define NOMINAL_ARMCLK (FPGA_ARM_CLK)
++#define NOMINAL_SYSCLK ((PLL400) / 4)
++#endif // !FPGA
++
++/**
++ * Timer
++ */
++#define CFG_TIMERBASE ((RPS_BASE) + 0x200)
++#define TIMER_PRESCALE_BIT 2
++#define TIMER_PRESCALE_1_ENUM 0
++#define TIMER_PRESCALE_16_ENUM 1
++#define TIMER_PRESCALE_256_ENUM 2
++#define TIMER_MODE_BIT 6
++#define TIMER_MODE_FREE_RUNNING 0
++#define TIMER_MODE_PERIODIC 1
++#define TIMER_ENABLE_BIT 7
++#define TIMER_ENABLE_DISABLE 0
++#define TIMER_ENABLE_ENABLE 1
++
++#define TIMER_PRESCALE_ENUM (TIMER_PRESCALE_256_ENUM)
++#define CFG_HZ ((RPSCLK) / 256)
++
++/**
++ * GPIO
++ */
++#define GPIO_1_OE ((GPIO_1_PA) + 0x4)
++#define GPIO_1_SET_OE ((GPIO_1_PA) + 0x1C)
++#define GPIO_1_CLR_OE ((GPIO_1_PA) + 0x20)
++
++#define GPIO_2_OE ((GPIO_2_PA) + 0x4)
++#define GPIO_2_SET_OE ((GPIO_2_PA) + 0x1C)
++#define GPIO_2_CLR_OE ((GPIO_2_PA) + 0x20)
++
++/**
++ * Serial Configuration
++ */
++#define EXT_UART_BASE 0x28000000
++
++#define UART_1_BASE (APB_BRIDGE_A_BASE_PA + 0x200000)
++#define UART_2_BASE (APB_BRIDGE_A_BASE_PA + 0x300000)
++#define UART_3_BASE (APB_BRIDGE_A_BASE_PA + 0x900000)
++#define UART_4_BASE (APB_BRIDGE_A_BASE_PA + 0xA00000)
++
++#define CFG_NS16550 1
++#define CFG_NS16550_SERIAL 1
++#define CFG_NS16550_REG_SIZE 1
++
++#if (USE_EXTERNAL_UART != 0)
++#define CFG_NS16550_CLK 16000000
++#define CFG_NS16550_COM1 (EXT_UART_BASE)
++#else // USE_EXTERNAL_UART
++#define CFG_NS16550_CLK (NOMINAL_SYSCLK)
++#define USE_UART_FRACTIONAL_DIVIDER
++#if (INTERNAL_UART == 1)
++#define CONFIG_OXNAS_UART1
++#define CFG_NS16550_COM1 (UART_1_BASE)
++#elif (INTERNAL_UART == 2)
++#define CONFIG_OXNAS_UART2
++#define CFG_NS16550_COM1 (UART_2_BASE)
++#elif (INTERNAL_UART == 3)
++#define CONFIG_OXNAS_UART3
++#define CFG_NS16550_COM1 (UART_3_BASE)
++#else
++#define CONFIG_OXNAS_UART4
++#define CFG_NS16550_COM1 (UART_4_BASE)
++#endif // CONFIG_OXNAS_UART
++#endif // USE_EXTERNAL_UART
++
++#define CONFIG_CONS_INDEX 1
++#define CONFIG_BAUDRATE 115200
++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
++
++/**
++ * Monitor commands
++ */
++#define BASE_COMMANDS (CFG_CMD_IMI | \
++ CFG_CMD_IMLS | \
++ CFG_CMD_BDI | \
++ CFG_CMD_NET | \
++ CFG_CMD_PING | \
++ CFG_CMD_ENV | \
++ CFG_CMD_RUN | \
++ CFG_CMD_MEMORY)
++
++#ifdef CFG_NO_FLASH
++#define FLASH_COMMANDS (BASE_COMMANDS)
++#else
++#define FLASH_COMMANDS (BASE_COMMANDS | CFG_CMD_FLASH)
++#endif // CFG_NO_FLASH
++
++#ifdef CONFIG_OXNAS_USE_SATA
++#define SATA_COMMANDS (FLASH_COMMANDS | CFG_CMD_IDE | CFG_CMD_EXT2 | CFG_CMD_LEDFAIL)
++#else
++#define SATA_COMMANDS (FLASH_COMMANDS)
++#endif // CONFIG_OXNAS_USE_SATA
++
++#define CONFIG_COMMANDS SATA_COMMANDS
++
++/* This must be included AFTER the definition of CONFIG_COMMANDS */
++#include <cmd_confdefs.h>
++
++/**
++ * Booting
++ */
++#if (LINUX_ROOT_RAIDED == 1)
++#define LINUX_ROOT_DEVICE "root=/dev/md1"
++#else
++#define LINUX_ROOT_DEVICE "root=/dev/sda1"
++#endif
++#define CONFIG_BOOTARGS LINUX_ROOT_DEVICE " console=ttyS0,115200 elevator=cfq gmac.mac_adr=0x00,0x30,0xe0,0x00,0x00,0x01"
++
++#ifdef CONFIG_OXNAS_USE_SATA
++#define CONFIG_BOOTDELAY 2
++#define CONFIG_BOOTCOMMAND "run select0 load boot || run select0 load2 boot || run lightled select1 load extinguishled boot || run lightled select1 load2 extinguishled boot || lightled"
++#define CONFIG_EXTRA_ENV_SETTINGS \
++ "select0=ide dev 0\0" \
++ "select1=ide dev 1\0" \
++ "load=ide read 0x48500000 12c 1644\0" \
++ "load2=ide read 0x48500000 2a6e 1644\0" \
++ "lightled=ledfail 1\0" \
++ "extinguishled=ledfail 0\0" \
++ "boot=bootm 48500000\0"
++#else // CONFIG_OXNAS_USE_SATA
++#define CONFIG_BOOTDELAY 15
++#define CONFIG_BOOTCOMMAND "bootm 0x41020000"
++#endif // CONFIG_OXNAS_USE_SATA
++
++//#define CONFIG_SHOW_BOOT_PROGRESS 1
++
++/**
++ * Networking
++ */
++#define CONFIG_ETHADDR 00:30:e0:00:00:01
++#define CONFIG_NETMASK 255.255.0.0
++#define CONFIG_IPADDR 172.31.0.128
++#define CONFIG_SERVERIP 172.31.0.100
++#define CONFIG_BOOTFILE "uImage"
++#define CFG_AUTOLOAD "n"
++#define CONFIG_NET_RETRY_COUNT 30
++
++/**
++ * Flash support
++ */
++#ifndef CFG_NO_FLASH
++
++#define FORCE_TOP_BOOT_FLASH 1
++
++#define CFG_FLASH_CFI 1
++#define CFG_FLASH_CFI_DRIVER 1
++
++#define NUM_FLASH_MAIN_BLOCKS 63 /* For Intel 28F320B3T */
++#define NUM_FLASH_PARAM_BLOCKS 8 /* For Intel 28F320B3T */
++#define FLASH_MAIN_BLOCK_SIZE (64*1024) /* For Intel 28F320B3T family */
++#define FLASH_PARAM_BLOCK_SIZE (8*1024) /* For Intel 28F320B3T family */
++
++/* Assuming counts main blocks and parameter blocks, as the Intel/AMD detection */
++/* I'm intending to copy would seem to indicate */
++#define CFG_MAX_FLASH_SECT (NUM_FLASH_MAIN_BLOCKS + NUM_FLASH_PARAM_BLOCKS)
++
++#define CFG_MAX_FLASH_BANKS 1 /* Assume counts flash devices */
++#define FLASH_BASE_OFF 0
++#define CFG_FLASH_BASE ((STATIC_CS0_BASE_PA) + (FLASH_BASE_OFF))
++#define PHYS_FLASH_1 (CFG_FLASH_BASE)
++
++#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */
++#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */
++#define CFG_FLASH_WRITE_ATTEMPTS 5
++
++#define STATIC_BUS_FLASH_CONFIG 0x4f1f3f3f /* Slow ASIC settings */
++
++#endif // !CFG_NO_FLASH
++
++/**
++ * Environment organization
++ */
++#ifdef ENV_ON_SATA
++
++/* Environment on SATA disk */
++#define SIZE_TO_SECTORS(x) ((x) / 512)
++#define CFG_ENV_IS_IN_DISK
++#define CFG_ENV_SIZE (8*1024)
++#define ENVIRONMENT_OFFSET ((CFG_SRAM_SIZE) - (CFG_ENV_SIZE) - 1024)
++#define CFG_ENV_ADDR ((CFG_SRAM_BASE) + (ENVIRONMENT_OFFSET))
++#define ROM_LOADER_LOAD_START_SECTOR 1
++#define CFG_ENV_DISK_SECTOR ((ROM_LOADER_LOAD_START_SECTOR) + SIZE_TO_SECTORS(ENVIRONMENT_OFFSET))
++#define ROM_LOADER_LOAD_REDUNDANT_START_SECTOR 10608
++#define CFG_ENV_DISK_REDUNDANT_SECTOR ((ROM_LOADER_LOAD_REDUNDANT_START_SECTOR) + SIZE_TO_SECTORS(ENVIRONMENT_OFFSET))
++
++#else
++/** Flash based environment
++ *
++ * It appears that all flash env start/size info. has to be pre-defined. How
++ * this is supposed to work when the flash detection code could cope with all
++ * sorts of different flash is hard to see.
++ * It appears from the README that with bottom/top boot flashes with smaller
++ * parameter blocks available, the environment code will only use a single
++ * one of these smaller sectors for the environment, i.e. CFG_ENV_SECT_SIZE
++ * is the size of the environment. I hope this isn't really true. The defines
++ * below may well not work if this is the truth
++ */
++#define CFG_ENV_IS_IN_FLASH
++/* Environment in flash device parameter blocks */
++#define CFG_ENV_SECT_SIZE (8*1024)
++/* First parameter block for environment */
++#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
++/* Second parameter block for backup environment */
++#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
++/* Main environment occupies first parameter block */
++#define CFG_ENV_ADDR ((CFG_FLASH_BASE)+((NUM_FLASH_MAIN_BLOCKS)*(FLASH_MAIN_BLOCK_SIZE)))
++/* Backup environment occupies second parameter block */
++#define CFG_ENV_ADDR_REDUND ((CFG_ENV_ADDR)+(CFG_ENV_SIZE))
++
++#endif // ENV_ON_SATA
++
++#define CONFIG_ENV_OVERWRITE
++
++/* Magic number that indicates rebooting into upgrade mode */
++#define UPGRADE_MAGIC 0x31 /* ASCII '1' */
++
++/* Magic number that indicates user recovery on reboot */
++/* Also defined in oxnas_user_recovery.agent */
++#define RECOVERY_MAGIC 0x31 /* ASCII '1' */
++
++/* Magic number that indicates controlled power down on reboot */
++/* Also defined in controlled_power_down.sh in init.d */
++#define CONTROLLED_POWER_DOWN_MAGIC 0x31 /* ASCII '1' */
++
++/* This flag is set in SRAM location by Co Proc */
++#define CONTROLLED_POWER_UP_MAGIC 0x31 /* ASCII '1' */
++/* 9k + a quad from top */
++/* Be carefule on changing the location of this flag
++ * u-boot has other things to write in SRAM too
++ */
++#define POWER_ON_FLAG_SRAM_OFFSET 9220
++
++/* Size of malloc() pool */
++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
++
++/**
++ * ASM startup control
++ */
++/* Start of address within SRAM of loader's exception table. */
++/* ROM-based exception table will redirect to here */
++#define EXCEPTION_BASE (CFG_SRAM_BASE)
++
++/**
++ * Disk related stuff
++ */
++#define CONFIG_LBA48
++#define CONFIG_DOS_PARTITION
++#define CFG_IDE_MAXDEVICE 2
++#define CFG_IDE_MAXBUS 1
++#define CONFIG_IDE_PREINIT
++#undef CONFIG_IDE_RESET
++#undef CONFIG_IDE_LED
++#define CFG_ATA_DATA_OFFSET 0
++#define CFG_ATA_REG_OFFSET 0
++#define CFG_ATA_ALT_OFFSET 0
++
++/**
++ * System block reset and clock control
++ */
++#define SYS_CTRL_USB11_CTRL (SYS_CONTROL_BASE_PA + 0x00)
++#define SYS_CTRL_PCI_CTRL0 (SYS_CONTROL_BASE_PA + 0x04)
++#define SYS_CTRL_PCI_CTRL1 (SYS_CONTROL_BASE_PA + 0x08)
++#define SYS_CTRL_GPIO_PRIMSEL_CTRL_0 (SYS_CONTROL_BASE_PA + 0x0C)
++#define SYS_CTRL_GPIO_PRIMSEL_CTRL_1 (SYS_CONTROL_BASE_PA + 0x10)
++#define SYS_CTRL_GPIO_SECSEL_CTRL_0 (SYS_CONTROL_BASE_PA + 0x14)
++#define SYS_CTRL_GPIO_SECSEL_CTRL_1 (SYS_CONTROL_BASE_PA + 0x18)
++#define SYS_CTRL_GPIO_TERTSEL_CTRL_0 (SYS_CONTROL_BASE_PA + 0x8C)
++#define SYS_CTRL_GPIO_TERTSEL_CTRL_1 (SYS_CONTROL_BASE_PA + 0x90)
++#define SYS_CTRL_USB11_STAT (SYS_CONTROL_BASE_PA + 0x1c)
++#define SYS_CTRL_PCI_STAT (SYS_CONTROL_BASE_PA + 0x20)
++#define SYS_CTRL_CKEN_SET_CTRL (SYS_CONTROL_BASE_PA + 0x2C)
++#define SYS_CTRL_CKEN_CLR_CTRL (SYS_CONTROL_BASE_PA + 0x30)
++#define SYS_CTRL_RSTEN_SET_CTRL (SYS_CONTROL_BASE_PA + 0x34)
++#define SYS_CTRL_RSTEN_CLR_CTRL (SYS_CONTROL_BASE_PA + 0x38)
++#define SYS_CTRL_PLLSYS_CTRL (SYS_CONTROL_BASE_PA + 0x48)
++#define SYS_CTRL_PLLSYS_KEY_CTRL (SYS_CONTROL_BASE_PA + 0x6C)
++#define SYS_CTRL_GMAC_CTRL (SYS_CONTROL_BASE_PA + 0x78)
++#define SYS_CTRL_UART_CTRL (SYS_CONTROL_BASE_PA + 0x94)
++
++#define SYS_CTRL_CKEN_COPRO_BIT 0
++#define SYS_CTRL_CKEN_DMA_BIT 1
++#define SYS_CTRL_CKEN_DPE_BIT 2
++#define SYS_CTRL_CKEN_DDR_BIT 3
++#define SYS_CTRL_CKEN_SATA_BIT 4
++#define SYS_CTRL_CKEN_I2S_BIT 5
++#define SYS_CTRL_CKEN_USBHS_BIT 6
++#define SYS_CTRL_CKEN_MAC_BIT 7
++#define SYS_CTRL_CKEN_PCI_BIT 8
++#define SYS_CTRL_CKEN_STATIC_BIT 9
++#define SYS_CTRL_CKEN_DDR_PHY_BIT 10
++
++#define SYS_CTRL_RSTEN_ARM_BIT 0
++#define SYS_CTRL_RSTEN_COPRO_BIT 1
++#define SYS_CTRL_RSTEN_USBHS_BIT 4
++#define SYS_CTRL_RSTEN_USBHSPHY_BIT 5
++#define SYS_CTRL_RSTEN_MAC_BIT 6
++#define SYS_CTRL_RSTEN_PCI_BIT 7
++#define SYS_CTRL_RSTEN_DMA_BIT 8
++#define SYS_CTRL_RSTEN_DPE_BIT 9
++#define SYS_CTRL_RSTEN_DDR_BIT 10
++#define SYS_CTRL_RSTEN_SATA_BIT 11
++#define SYS_CTRL_RSTEN_SATA_LINK_BIT 12
++#define SYS_CTRL_RSTEN_SATA_PHY_BIT 13
++#define SYS_CTRL_RSTEN_STATIC_BIT 15
++#define SYS_CTRL_RSTEN_GPIO_BIT 16
++#define SYS_CTRL_RSTEN_UART1_BIT 17
++#define SYS_CTRL_RSTEN_UART2_BIT 18
++#define SYS_CTRL_RSTEN_MISC_BIT 19
++#define SYS_CTRL_RSTEN_I2S_BIT 20
++#define SYS_CTRL_RSTEN_AHB_MON_BIT 21
++#define SYS_CTRL_RSTEN_UART3_BIT 22
++#define SYS_CTRL_RSTEN_UART4_BIT 23
++#define SYS_CTRL_RSTEN_SGDMA_BIT 24
++#define SYS_CTRL_RSTEN_DDR_PHY_BIT 25
++#define SYS_CTRL_RSTEN_BUS_BIT 31
++
++#define SYS_CTRL_GMAC_RGMII 2
++#define SYS_CTRL_GMAC_SIMPLE_MAX 1
++#define SYS_CTRL_GMAC_CKEN_GTX 0
++
++#define SYS_CTRL_CKCTRL_CTRL_ADDR (SYS_CONTROL_BASE_PA + 0x64)
++
++#define SYS_CTRL_CKCTRL_PCI_DIV_BIT 0
++#define SYS_CTRL_CKCTRL_SLOW_BIT 8
++
++#define SYS_CTRL_UART2_DEQ_EN 0
++#define SYS_CTRL_UART3_DEQ_EN 1
++#define SYS_CTRL_UART3_IQ_EN 2
++#define SYS_CTRL_UART4_IQ_EN 3
++#define SYS_CTRL_UART4_NOT_PCI_MODE 4
++
++#define SYS_CTRL_PCI_CTRL1_PCI_STATIC_RQ_BIT 11
++
++/**
++ * SATA related definitions
++ */
++#define ATA_PORT_CTL 0
++#define ATA_PORT_FEATURE 1
++#define ATA_PORT_NSECT 2
++#define ATA_PORT_LBAL 3
++#define ATA_PORT_LBAM 4
++#define ATA_PORT_LBAH 5
++#define ATA_PORT_DEVICE 6
++#define ATA_PORT_COMMAND 7
++
++#define SATA_0_REGS_BASE (APB_BRIDGE_B_BASE_PA + 0x900000)
++#define SATA_1_REGS_BASE (APB_BRIDGE_B_BASE_PA + 0x910000)
++#define SATA_HOST_REGS_BASE (APB_BRIDGE_B_BASE_PA + 0x9e0000)
++
++/* The offsets to the SATA registers */
++#define SATA_ORB1_OFF 0
++#define SATA_ORB2_OFF 1
++#define SATA_ORB3_OFF 2
++#define SATA_ORB4_OFF 3
++#define SATA_ORB5_OFF 4
++
++#define SATA_FIS_ACCESS 11
++#define SATA_INT_STATUS_OFF 12 /* Read only */
++#define SATA_INT_CLR_OFF 12 /* Write only */
++#define SATA_INT_ENABLE_OFF 13 /* Read only */
++#define SATA_INT_ENABLE_SET_OFF 13 /* Write only */
++#define SATA_INT_ENABLE_CLR_OFF 14 /* Write only */
++#define SATA_VERSION_OFF 15
++#define SATA_CONTROL_OFF 23
++#define SATA_COMMAND_OFF 24
++#define SATA_PORT_CONTROL_OFF 25
++#define SATA_DRIVE_CONTROL_OFF 26
++
++/* The offsets to the link registers that are access in an asynchronous manner */
++#define SATA_LINK_DATA 28
++#define SATA_LINK_RD_ADDR 29
++#define SATA_LINK_WR_ADDR 30
++#define SATA_LINK_CONTROL 31
++
++/* SATA interrupt status register fields */
++#define SATA_INT_STATUS_EOC_RAW_BIT ( 0 + 16)
++#define SATA_INT_STATUS_ERROR_BIT ( 2 + 16)
++#define SATA_INT_STATUS_EOADT_RAW_BIT ( 1 + 16)
++
++/* SATA core command register commands */
++#define SATA_CMD_WRITE_TO_ORB_REGS 2
++#define SATA_CMD_WRITE_TO_ORB_REGS_NO_COMMAND 4
++
++#define SATA_CMD_BUSY_BIT 7
++
++#define SATA_SCTL_CLR_ERR 0x00000316UL
++
++#define SATA_OPCODE_MASK 0x3
++
++#define SATA_LBAL_BIT 0
++#define SATA_LBAM_BIT 8
++#define SATA_LBAH_BIT 16
++#define SATA_HOB_LBAH_BIT 24
++#define SATA_DEVICE_BIT 24
++#define SATA_NSECT_BIT 0
++#define SATA_FEATURE_BIT 16
++#define SATA_COMMAND_BIT 24
++#define SATA_CTL_BIT 24
++
++/* ATA status (7) register field definitions */
++#define ATA_STATUS_BSY_BIT 7
++#define ATA_STATUS_DRDY_BIT 6
++#define ATA_STATUS_DF_BIT 5
++#define ATA_STATUS_DRQ_BIT 3
++#define ATA_STATUS_ERR_BIT 0
++
++/* ATA device (6) register field definitions */
++#define ATA_DEVICE_FIXED_MASK 0xA0
++#define ATA_DEVICE_DRV_BIT 4
++#define ATA_DEVICE_DRV_NUM_BITS 1
++#define ATA_DEVICE_LBA_BIT 6
++
++/* ATA control (0) register field definitions */
++#define ATA_CTL_SRST_BIT 2
++
++/* ATA Command register initiated commands */
++#define ATA_CMD_INIT 0x91
++#define ATA_CMD_IDENT 0xEC
++
++#define SATA_STD_ASYNC_REGS_OFF 0x20
++#define SATA_SCR_STATUS 0
++#define SATA_SCR_ERROR 1
++#define SATA_SCR_CONTROL 2
++#define SATA_SCR_ACTIVE 3
++#define SATA_SCR_NOTIFICAION 4
++
++#define SATA_BURST_BUF_FORCE_EOT_BIT 0
++#define SATA_BURST_BUF_DATA_INJ_ENABLE_BIT 1
++#define SATA_BURST_BUF_DIR_BIT 2
++#define SATA_BURST_BUF_DATA_INJ_END_BIT 3
++#define SATA_BURST_BUF_FIFO_DIS_BIT 4
++#define SATA_BURST_BUF_DIS_DREQ_BIT 5
++#define SATA_BURST_BUF_DREQ_BIT 6
++
++/* Button on GPIO 32 */
++#define RECOVERY_BUTTON (0x00000001 << 0)
++#define RECOVERY_PRISEL_REG SYS_CTRL_GPIO_PRIMSEL_CTRL_1
++#define RECOVERY_SECSEL_REG SYS_CTRL_GPIO_SECSEL_CTRL_1
++#define RECOVERY_TERSEL_REG SYS_CTRL_GPIO_TERTSEL_CTRL_1
++#define RECOVERY_CLR_OE_REG GPIO_2_CLR_OE
++#define RECOVERY_DEBOUNCE_REG GPIO_2_INPUT_DEBOUNCE_ENABLE
++#define RECOVERY_DATA GPIO_2_PA
++
++#endif // CONFIG_H
+diff -Nurd u-boot-1.1.2/include/_exports.h u-boot-1.1.2-oxe810/include/_exports.h
+--- u-boot-1.1.2/include/_exports.h 2003-09-12 17:35:33.000000000 +0200
++++ u-boot-1.1.2-oxe810/include/_exports.h 2008-06-11 17:55:11.000000000 +0200
+@@ -12,6 +12,7 @@
+ EXPORT_FUNC(get_timer)
+ EXPORT_FUNC(vprintf)
+ EXPORT_FUNC(do_reset)
++EXPORT_FUNC(raise)
+ #if (CONFIG_COMMANDS & CFG_CMD_I2C)
+ EXPORT_FUNC(i2c_write)
+ EXPORT_FUNC(i2c_read)
+diff -Nurd u-boot-1.1.2/include/flash.h u-boot-1.1.2-oxe810/include/flash.h
+--- u-boot-1.1.2/include/flash.h 2004-12-16 19:01:48.000000000 +0100
++++ u-boot-1.1.2-oxe810/include/flash.h 2008-06-11 17:55:11.000000000 +0200
+@@ -207,6 +207,7 @@
+ #define ATM_ID_BV1614 0x000000C0 /* 49BV1614 ID */
+ #define ATM_ID_BV1614A 0x000000C8 /* 49BV1614A ID */
+ #define ATM_ID_BV6416 0x000000D6 /* 49BV6416 ID */
++#define ATM_ID_BV322 0x000000c9 /* 49BV322A ID */
+
+ #define FUJI_ID_29F800BA 0x22582258 /* MBM29F800BA ID (8M) */
+ #define FUJI_ID_29F800TA 0x22D622D6 /* MBM29F800TA ID (8M) */
+@@ -405,6 +406,7 @@
+ #define FLASH_MAN_INTEL 0x00300000
+ #define FLASH_MAN_MT 0x00400000
+ #define FLASH_MAN_SHARP 0x00500000
++#define FLASH_MAN_ATM 0x00070000 /* Atmel */
+
+
+ #define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */
+diff -Nurd u-boot-1.1.2/include/ns16550.h u-boot-1.1.2-oxe810/include/ns16550.h
+--- u-boot-1.1.2/include/ns16550.h 2004-06-07 01:13:57.000000000 +0200
++++ u-boot-1.1.2-oxe810/include/ns16550.h 2008-06-11 17:55:11.000000000 +0200
+@@ -19,6 +19,10 @@
+ unsigned char lsr; /* 5 */
+ unsigned char msr; /* 6 */
+ unsigned char scr; /* 7 */
++#if defined(CONFIG_OXNAS)
++ unsigned char ext; /* 8 */
++ unsigned char dlf; /* 9 */
++#endif
+ #if defined(CONFIG_OMAP730)
+ unsigned char mdr1; /* 8 */
+ unsigned char reg9; /* 9 */
+diff -Nurd u-boot-1.1.2/lib_arm/board.c u-boot-1.1.2-oxe810/lib_arm/board.c
+--- u-boot-1.1.2/lib_arm/board.c 2004-08-02 00:48:22.000000000 +0200
++++ u-boot-1.1.2-oxe810/lib_arm/board.c 2008-06-11 17:55:06.000000000 +0200
+@@ -39,6 +39,9 @@
+ #include "../drivers/lan91c96.h"
+ #endif
+
++DECLARE_GLOBAL_DATA_PTR
++
++
+ #if (CONFIG_COMMANDS & CFG_CMD_NAND)
+ void nand_init (void);
+ #endif
+@@ -106,7 +109,6 @@
+
+ static int init_baudrate (void)
+ {
+- DECLARE_GLOBAL_DATA_PTR;
+
+ uchar tmp[64]; /* long enough for environment variables */
+ int i = getenv_r ("baudrate", tmp, sizeof (tmp));
+@@ -142,16 +144,18 @@
+ */
+ static int display_dram_config (void)
+ {
+- DECLARE_GLOBAL_DATA_PTR;
+ int i;
+
+ puts ("RAM Configuration:\n");
+
+ for(i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
+- printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
++ printf ("\tBank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
+ print_size (gd->bd->bi_dram[i].size, "\n");
+ }
+
++ puts("SRAM Configuration:\n");
++ printf("\t%dKB at 0x%08x\n", gd->bd->bi_sramsize >> 10, gd->bd->bi_sramstart);
++
+ return (0);
+ }
+
+@@ -191,6 +195,12 @@
+ cpu_init, /* basic cpu dependent setup */
+ board_init, /* basic board dependent setup */
+ interrupt_init, /* set up exceptions */
++#ifdef CONFIG_OXNAS
++ /* Need early console to see SATA env. load messages */
++ init_baudrate, /* initialze baudrate settings */
++ serial_init, /* serial communications setup */
++ console_init_f, /* stage 1 init of console */
++#endif // CONFIG_OXNAS
+ env_init, /* initialize environment */
+ init_baudrate, /* initialze baudrate settings */
+ serial_init, /* serial communications setup */
+@@ -206,7 +216,6 @@
+
+ void start_armboot (void)
+ {
+- DECLARE_GLOBAL_DATA_PTR;
+
+ ulong size;
+ init_fnc_t **init_fnc_ptr;
+@@ -232,9 +241,11 @@
+ }
+ }
+
++#ifndef CFG_NO_FLASH
+ /* configure available FLASH banks */
+ size = flash_init ();
+ display_flash_config (size);
++#endif // CFG_NO_FLASH
+
+ #ifdef CONFIG_VFD
+ # ifndef PAGE_SIZE
+@@ -354,6 +365,12 @@
+ {
+ puts ("### ERROR ### Please RESET the board ###\n");
+ for (;;);
++}
++
++void raise (int n)
++{
++ puts ("### ERROR ### Please RESET the board ###\n");
++ for (;;);
+ }
+
+ #ifdef CONFIG_MODEM_SUPPORT
+diff -Nurd u-boot-1.1.2/MAKEALL u-boot-1.1.2-oxe810/MAKEALL
+--- u-boot-1.1.2/MAKEALL 2004-12-31 10:32:48.000000000 +0100
++++ u-boot-1.1.2-oxe810/MAKEALL 2008-06-11 17:55:31.000000000 +0200
+@@ -154,7 +154,7 @@
+ lpd7a400 mx1ads mx1fs2 omap1510inn \
+ omap1610h2 omap1610inn omap730p2 scb9328 \
+ smdk2400 smdk2410 trab VCMA9 \
+- versatile \
++ versatile oxnas \
+ "
+
+ #########################################################################
+diff -Nurd u-boot-1.1.2/Makefile u-boot-1.1.2-oxe810/Makefile
+--- u-boot-1.1.2/Makefile 2004-12-19 10:58:11.000000000 +0100
++++ u-boot-1.1.2-oxe810/Makefile 2008-06-11 17:55:31.000000000 +0200
+@@ -1296,6 +1296,9 @@
+ SX1_config : unconfig
+ @./mkconfig $(@:_config=) arm arm925t sx1
+
++oxnas_config : unconfig
++ @./mkconfig $(@:_config=) arm arm926ejs oxnas
++
+ # TRAB default configuration: 8 MB Flash, 32 MB RAM
+ trab_config \
+ trab_bigram_config \
+@@ -1561,11 +1564,12 @@
+ clean:
+ find . -type f \
+ \( -name 'core' -o -name '*.bak' -o -name '*~' \
+- -o -name '*.o' -o -name '*.a' \) -print \
++ -o -name '*.o' -o -name '*.a' -o -name '.depend' \) -print \
+ | xargs rm -f
+ rm -f examples/hello_world examples/timer \
+ examples/eepro100_eeprom examples/sched \
+- examples/mem_to_mem_idma2intr examples/82559_eeprom
++ examples/mem_to_mem_idma2intr examples/82559_eeprom \
++ examples/mem_test
+ rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr
+ rm -f tools/mpc86x_clk tools/ncb
+ rm -f tools/easylogo/easylogo tools/bmp_logo
+diff -Nurd u-boot-1.1.2/net/net.c u-boot-1.1.2-oxe810/net/net.c
+--- u-boot-1.1.2/net/net.c 2004-10-12 00:51:14.000000000 +0200
++++ u-boot-1.1.2-oxe810/net/net.c 2008-06-11 17:55:11.000000000 +0200
+@@ -225,7 +225,7 @@
+ return;
+
+ t = get_timer(0);
+-
++
+ /* check for arp timeout */
+ if ((t - NetArpWaitTimerStart) > ARP_TIMEOUT * CFG_HZ) {
+ NetArpWaitTry++;
+@@ -235,6 +235,7 @@
+ NetArpWaitTry = 0;
+ NetStartAgain();
+ } else {
++ puts ("\nARP Resend request\n");
+ NetArpWaitTimerStart = t;
+ ArpRequest();
+ }
+@@ -738,7 +739,7 @@
+ #if defined(CONFIG_NET_MULTI)
+ printf ("Using %s device\n", eth_get_name());
+ #endif /* CONFIG_NET_MULTI */
+- NetSetTimeout (10 * CFG_HZ, PingTimeout);
++ NetSetTimeout (30 * CFG_HZ, PingTimeout);
+ NetSetHandler (PingHandler);
+
+ PingSend();
+@@ -1384,7 +1385,7 @@
+ */
+ /* XXX point to ip packet */
+ (*packetHandler)((uchar *)ip, 0, 0, 0);
+- break;
++ return;/**break; BHC Changed to remove second invocation of ping handler below */
+ #endif
+ default:
+ return;
+@@ -1492,10 +1493,11 @@
+ NetCksum(uchar * ptr, int len)
+ {
+ ulong xsum;
++ ushort *s = ptr;
+
+ xsum = 0;
+ while (len-- > 0)
+- xsum += *((ushort *)ptr)++;
++ xsum += *s++;
+ xsum = (xsum & 0xffff) + (xsum >> 16);
+ xsum = (xsum & 0xffff) + (xsum >> 16);
+ return (xsum & 0xffff);
+diff -Nurd u-boot-1.1.2/net/tftp.c u-boot-1.1.2-oxe810/net/tftp.c
+--- u-boot-1.1.2/net/tftp.c 2004-04-15 23:48:55.000000000 +0200
++++ u-boot-1.1.2-oxe810/net/tftp.c 2008-06-11 17:55:11.000000000 +0200
+@@ -106,6 +106,7 @@
+ volatile uchar * pkt;
+ volatile uchar * xp;
+ int len = 0;
++ volatile ushort * s;
+
+ /*
+ * We will always be sending some sort of packet, so
+@@ -117,7 +118,9 @@
+
+ case STATE_RRQ:
+ xp = pkt;
+- *((ushort *)pkt)++ = htons(TFTP_RRQ);
++ s = (ushort *)pkt;
++ *s++ = htons(TFTP_RRQ);
++ pkt = (uchar *)s;
+ strcpy ((char *)pkt, tftp_filename);
+ pkt += strlen(tftp_filename) + 1;
+ strcpy ((char *)pkt, "octet");
+@@ -135,15 +138,19 @@
+ case STATE_DATA:
+ case STATE_OACK:
+ xp = pkt;
+- *((ushort *)pkt)++ = htons(TFTP_ACK);
+- *((ushort *)pkt)++ = htons(TftpBlock);
++ s = (ushort *)pkt;
++ *s++ = htons(TFTP_ACK);
++ *s++ = htons(TftpBlock);
++ pkt = (uchar *)s;
+ len = pkt - xp;
+ break;
+
+ case STATE_TOO_LARGE:
+ xp = pkt;
+- *((ushort *)pkt)++ = htons(TFTP_ERROR);
+- *((ushort *)pkt)++ = htons(3);
++ s = (ushort *)pkt;
++ *s++ = htons(TFTP_ERROR);
++ *s++ = htons(3);
++ pkt = (uchar *)s;
+ strcpy ((char *)pkt, "File too large");
+ pkt += 14 /*strlen("File too large")*/ + 1;
+ len = pkt - xp;
+@@ -151,8 +158,10 @@
+
+ case STATE_BAD_MAGIC:
+ xp = pkt;
+- *((ushort *)pkt)++ = htons(TFTP_ERROR);
+- *((ushort *)pkt)++ = htons(2);
++ s = (ushort *)pkt;
++ *s++ = htons(TFTP_ERROR);
++ *s++ = htons(2);
++ pkt = (uchar *)s;
+ strcpy ((char *)pkt, "File has bad magic");
+ pkt += 18 /*strlen("File has bad magic")*/ + 1;
+ len = pkt - xp;
+@@ -167,6 +176,7 @@
+ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len)
+ {
+ ushort proto;
++ ushort *s;
+
+ if (dest != TftpOurPort) {
+ return;
+@@ -180,7 +190,9 @@
+ }
+ len -= 2;
+ /* warning: don't use increment (++) in ntohs() macros!! */
+- proto = *((ushort *)pkt)++;
++ s = (ushort *)pkt;
++ proto = *s++;
++ pkt = (uchar *)s;
+ switch (ntohs(proto)) {
+
+ case TFTP_RRQ:
diff --git a/recipes/u-boot/u-boot-1.1.2/u-boot-1.1.2-neon.patch b/recipes/u-boot/u-boot-1.1.2/u-boot-1.1.2-neon.patch
new file mode 100644
index 0000000000..3809a75f51
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.2/u-boot-1.1.2-neon.patch
@@ -0,0 +1,19155 @@
+diff -u -r --new-file u-boot-1.1.2/board/bd2003/bd2003.c u-boot-1.1.2-neon/board/bd2003/bd2003.c
+--- u-boot-1.1.2/board/bd2003/bd2003.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/bd2003/bd2003.c 2007-08-11 21:07:19.000000000 +0200
+@@ -0,0 +1,94 @@
++/*
++ * (C) Copyright 2002
++ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
++ *
++ * (C) Copyright 2002
++ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
++ * Marius Groeger <mgroeger@sysgo.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <config.h>
++#include <common.h>
++#include <version.h>
++#include <stdarg.h>
++#include <linux/types.h>
++#include <devices.h>
++#include <lcd.h>
++#include <lcd_panels.h>
++
++/* ------------------------------------------------------------------------- */
++/*
++ * LCD panel declarations
++ */
++
++vidinfo_t panel_info = {
++ vl_col: 1024, //this is corrected in SetPanelInfo
++ vl_row: 768,
++ vl_bpix: LCD_BPP,
++ vl_lcd_line_length: (320 * NBITS(LCD_BPP) ) >> 3
++};
++
++void disable_lcd_panel( void )
++{
++}
++
++
++/* ------------------------------------------------------------------------- */
++
++
++/*
++ * Miscelaneous platform dependent initialisations
++ */
++
++int board_init (void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ /* memory and cpu-speed are setup before relocation */
++ /* so we do _nothing_ here */
++
++ /* arch number of Neon Board */
++ gd->bd->bi_arch_number = MACH_TYPE_BD2003 ;
++
++ /* adress of boot parameters */
++ gd->bd->bi_boot_params = 0xa0000100;
++
++ return 0;
++}
++
++int board_late_init(void)
++{
++ setenv("stdout", "serial");
++ setenv("stderr", "serial");
++ return 0;
++}
++
++
++int dram_init (void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++
++ return 0;
++}
+diff -u -r --new-file u-boot-1.1.2/board/bd2003/config.mk u-boot-1.1.2-neon/board/bd2003/config.mk
+--- u-boot-1.1.2/board/bd2003/config.mk 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/bd2003/config.mk 2007-08-11 21:07:19.000000000 +0200
+@@ -0,0 +1,4 @@
++#TEXT_BASE = 0xa1700000
++TEXT_BASE = 0xA1F00000
++#TEXT_BASE = 0
++PXALCD = 1
+diff -u -r --new-file u-boot-1.1.2/board/bd2003/.cvsignore u-boot-1.1.2-neon/board/bd2003/.cvsignore
+--- u-boot-1.1.2/board/bd2003/.cvsignore 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/bd2003/.cvsignore 2007-08-11 21:07:19.000000000 +0200
+@@ -0,0 +1,2 @@
++.depend
++
+diff -u -r --new-file u-boot-1.1.2/board/bd2003/flash.c u-boot-1.1.2-neon/board/bd2003/flash.c
+--- u-boot-1.1.2/board/bd2003/flash.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/bd2003/flash.c 2007-08-11 21:07:19.000000000 +0200
+@@ -0,0 +1,477 @@
++/*
++ * (C) Copyright 2001
++ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
++ *
++ * (C) Copyright 2001
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <linux/byteorder/swab.h>
++#include <asm/arch/pxa250Base.h>
++#include <asm/arch/pxaHardware.h>
++#include "lcd.h"
++
++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
++
++/* Board support for 1 or 2 flash devices */
++#define FLASH_PORT_WIDTH32
++#undef FLASH_PORT_WIDTH16
++
++#ifdef FLASH_PORT_WIDTH16
++#define FLASH_PORT_WIDTH ushort
++#define FLASH_PORT_WIDTHV vu_short
++#define SWAP(x) __swab16(x)
++#else
++#define FLASH_PORT_WIDTH ulong
++#define FLASH_PORT_WIDTHV vu_long
++#define SWAP(x) __swab32(x)
++#endif
++
++#define FPW FLASH_PORT_WIDTH
++#define FPWV FLASH_PORT_WIDTHV
++
++#define mb() __asm__ __volatile__ ("" : : : "memory")
++
++/*-----------------------------------------------------------------------
++ * Functions
++ */
++static ulong flash_get_size (FPW *addr, flash_info_t *info);
++static int write_data (flash_info_t *info, ulong dest, FPW data);
++static void flash_get_offsets (ulong base, flash_info_t *info);
++void inline spin_wheel_init(ulong addr, ulong cnt);
++void inline spin_wheel_done( int worked );
++void inline spin_wheel (ulong numleft);
++
++/*-----------------------------------------------------------------------
++ */
++ulong bases[] = {PHYS_FLASH_1,PHYS_FLASH_2,1};
++unsigned long flash_init (void)
++{
++ int i=0;
++ int j=0;
++ ulong size = 0;
++ ulong base;
++
++ while (i < CFG_MAX_FLASH_BANKS) {
++ base = bases[j++];
++ flash_info[i].start[0] = 0;
++ if (base & 1) break;
++ if (flash_get_size ((FPW *) base, &flash_info[i])) {
++ flash_get_offsets (base, &flash_info[i]);
++ size += flash_info[i].size;
++ i++;
++ }
++ else {
++printf( "error reading flash size\n" );
++ }
++ }
++ if (size>0) {
++ base = flash_info[0].start[0];
++ // Protect monitor and environment sectors
++ flash_protect ( FLAG_PROTECT_SET,
++ base,
++ base + monitor_flash_len - 1,
++ &flash_info[0] );
++
++ flash_protect ( FLAG_PROTECT_SET,
++ base+CFG_ENV_OFFSET,
++ base+CFG_ENV_OFFSET + CFG_ENV_SIZE - 1, &flash_info[0] );
++ }
++
++ return size;
++}
++
++/*-----------------------------------------------------------------------
++ */
++static void flash_get_offsets (ulong base, flash_info_t *info)
++{
++ int i;
++
++ if (info->flash_id == FLASH_UNKNOWN) {
++ return;
++ }
++
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
++ for (i = 0; i < info->sector_count; i++) {
++ info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
++ info->protect[i] = 0;
++ }
++ }
++}
++
++/*-----------------------------------------------------------------------
++ */
++void flash_print_info (flash_info_t *info)
++{
++ int i;
++
++ if (info->flash_id == FLASH_UNKNOWN) {
++ printf ("missing or unknown FLASH type\n");
++ return;
++ }
++
++ switch (info->flash_id & FLASH_VENDMASK) {
++ case FLASH_MAN_INTEL:
++ printf ("INTEL ");
++ break;
++ default:
++ printf ("Unknown Vendor ");
++ break;
++ }
++
++ switch (info->flash_id & FLASH_TYPEMASK) {
++ case FLASH_28F128J3A:
++ printf ("28F128J3A\n");
++ break;
++ default:
++ printf ("Unknown Chip Type\n");
++ break;
++ }
++
++ printf (" Size: %ld MB in %d Sectors\n",
++ info->size >> 20, info->sector_count);
++
++ printf (" Sector Start Addresses:");
++ for (i = 0; i < info->sector_count; ++i) {
++ if ((i % 5) == 0)
++ printf ("\n ");
++ printf (" %08lX%s",
++ info->start[i],
++ info->protect[i] ? " (RO)" : " ");
++ }
++ printf ("\n");
++ return;
++}
++
++/*
++ * The following code cannot be run from FLASH!
++ */
++static ulong flash_get_size (FPW *addr, flash_info_t *info)
++{
++ volatile FPW value;
++ volatile unsigned long *mc = (unsigned long *)MEMORY_CONTROL_BASE;
++ unsigned long val = 1<<3;
++
++ info->flash_id = FLASH_UNKNOWN;
++ info->sector_count = 0;
++ info->size = 0;
++
++ if (((ulong)addr) > 0x14000000) return 0;
++ val = mc[(MSC0>>2) +(((ulong)addr)>>27)];
++ if (((ulong)addr) & 0x04000000) val = val>>16;
++ if ( val & (1<<3)) return 0; //if 16 bit bus then return
++
++ /* Write auto select command: read Manufacturer ID */
++ addr[0x5555] = (FPW) 0x00AA00AA;
++ addr[0x2AAA] = (FPW) 0x00550055;
++ addr[0x5555] = (FPW) 0x00900090;
++
++ mb ();
++ value = addr[0];
++
++ switch (value) {
++
++ case (FPW) 0:
++ case (FPW) INTEL_MANUFACT & 0xFF0000 :
++ case (FPW) INTEL_MANUFACT & 0x0000FF :
++ case (FPW) INTEL_MANUFACT:
++ info->flash_id = FLASH_MAN_INTEL;
++ break;
++
++ default:
++printf( "Invalid flash manufacturer %x\n", value );
++ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
++ return (0); /* no or unknown flash */
++ }
++
++ mb ();
++ value = addr[1]; /* device ID */
++
++ switch (value) {
++
++ case (FPW) 0:
++ case (FPW) INTEL_ID_28F128J3A & 0xFF0000 :
++ case (FPW) INTEL_ID_28F128J3A & 0x0000FF :
++ case (FPW) INTEL_ID_28F128J3A:
++ info->flash_id += FLASH_28F128J3A;
++ info->sector_count = 128;
++ info->size = 0x02000000;
++ break; /* => 16 MB */
++
++ default:
++printf( "Unknown flash device %x\n", value );
++ info->flash_id = FLASH_UNKNOWN;
++ break;
++ }
++
++ if (info->sector_count > CFG_MAX_FLASH_SECT) {
++ printf ("** ERROR: sector count %d > max (%d) **\n",
++ info->sector_count, CFG_MAX_FLASH_SECT);
++ info->sector_count = CFG_MAX_FLASH_SECT;
++ }
++
++ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
++
++ return (info->size);
++}
++
++
++/*-----------------------------------------------------------------------
++ */
++
++int flash_erase (flash_info_t *info, int s_first, int s_last)
++{
++ int flag, prot, sect;
++ ulong type, start, last;
++ int rcode = 0;
++
++ if ((s_first < 0) || (s_first > s_last)) {
++ if (info->flash_id == FLASH_UNKNOWN) {
++ printf ("- missing\n");
++ } else {
++ printf ("- no sectors to erase\n");
++ }
++ return 1;
++ }
++
++ type = (info->flash_id & FLASH_VENDMASK);
++ if ((type != FLASH_MAN_INTEL)) {
++ printf ("Can't erase unknown flash type %08lx - aborted\n",
++ info->flash_id);
++ return 1;
++ }
++
++ prot = 0;
++ for (sect = s_first; sect <= s_last; ++sect) {
++ if (info->protect[sect]) {
++ prot++;
++ }
++ }
++
++ if (prot) {
++ printf ("- Warning: %d protected sectors will not be erased!\n",
++ prot);
++ } else {
++ printf ("\n");
++ }
++
++ start = get_timer (0);
++ last = start;
++
++ /* Disable interrupts which might cause a timeout here */
++ flag = disable_interrupts ();
++
++ /* Start erase on unprotected sectors */
++ for (sect = s_first; sect <= s_last; sect++) {
++ if (info->protect[sect] == 0) { /* not protected */
++ char temp[80];
++ FPWV *addr = (FPWV *) (info->start[sect]);
++ FPW status;
++
++ sprintf (temp, "Erasing sector %2d ... \r", sect);
++ lcd_puts( temp );
++
++ /* arm simple, non interrupt dependent timer */
++ reset_timer_masked ();
++
++ *addr = (FPW) 0x00500050; /* clear status register */
++ *addr = (FPW) 0x00200020; /* erase setup */
++ *addr = (FPW) 0x00D000D0; /* erase confirm */
++
++ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
++ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
++ printf ("Timeout\n");
++ *addr = (FPW) 0x00B000B0; /* suspend erase */
++ *addr = (FPW) 0x00FF00FF; /* reset to read mode */
++ rcode = 1;
++ break;
++ }
++ }
++
++ *addr = 0x00500050; /* clear status register cmd. */
++ *addr = 0x00FF00FF; /* resest to read mode */
++ }
++ }
++ lcd_puts( "\r\n" );
++ return rcode;
++}
++
++/*-----------------------------------------------------------------------
++ * Copy memory to flash, returns:
++ * 0 - OK
++ * 1 - write timeout
++ * 2 - Flash not erased
++ * 4 - Flash not identified
++ */
++
++int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
++{
++ ulong cp, wp;
++ FPW data;
++ int count, i, l, rc, port_width;
++
++ rc = 0 ;
++ if (info->flash_id == FLASH_UNKNOWN) {
++ return 4;
++ }
++/* get lower word aligned address */
++#ifdef FLASH_PORT_WIDTH16
++ wp = (addr & ~1);
++ port_width = 2;
++#else
++ wp = (addr & ~3);
++ port_width = 4;
++#endif
++
++ spin_wheel_init(addr,cnt);
++
++ /*
++ * handle unaligned start bytes
++ */
++ if ((l = addr - wp) != 0) {
++ data = 0;
++ for (i = 0, cp = wp; i < l; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++ for (; i < port_width && cnt > 0; ++i) {
++ data = (data << 8) | *src++;
++ --cnt;
++ ++cp;
++ }
++ for (; cnt == 0 && i < port_width; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++
++ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
++ goto out;
++ }
++ wp += port_width;
++ }
++
++ /*
++ * handle word aligned part
++ */
++ count = 0;
++ while (cnt >= port_width) {
++ data = 0;
++ for (i = 0; i < port_width; ++i) {
++ data = (data << 8) | *src++;
++ }
++ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
++ goto out;
++ }
++ wp += port_width;
++ cnt -= port_width;
++ if (count++ > 0x800) {
++ spin_wheel (cnt);
++ count = 0;
++ }
++ }
++
++ if (cnt) {
++ /*
++ * handle unaligned tail bytes
++ */
++ data = 0;
++ for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
++ data = (data << 8) | *src++;
++ --cnt;
++ }
++ for (; i < port_width; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++
++ rc = write_data (info, wp, SWAP (data));
++ }
++
++out:
++ spin_wheel_done(0 == rc);
++ return rc ;
++}
++
++/*-----------------------------------------------------------------------
++ * Write a word or halfword to Flash, returns:
++ * 0 - OK
++ * 1 - write timeout
++ * 2 - Flash not erased
++ */
++static int write_data (flash_info_t *info, ulong dest, FPW data)
++{
++ FPWV *addr = (FPWV *) dest;
++ FPW old = *addr ;
++ ulong status;
++ int flag;
++
++ /* Check if Flash is (sufficiently) erased */
++ if ((old & data) != data) {
++ printf ("not erased at %08lx (%lx)\n", (ulong) addr, old);
++ return (2);
++ }
++
++ if( old != data )
++ {
++ /* Disable interrupts which might cause a timeout here */
++ flag = disable_interrupts ();
++
++ *addr = (FPW) 0x00400040; /* write setup */
++ *addr = data;
++
++ /* arm simple, non interrupt dependent timer */
++ reset_timer_masked ();
++
++ /* wait while polling the status register */
++ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
++ if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
++ *addr = (FPW) 0x00FF00FF; /* restore read mode */
++ return (1);
++ }
++ }
++ *addr = (FPW) 0x00FF00FF; /* restore read mode */
++ } /* need to program? */
++
++
++ return (0);
++}
++
++void inline spin_wheel_init(ulong addr, ulong cnt)
++{
++ char temp[80];
++ sprintf( temp,
++ "\nprogramming flash\n"
++ "%08lx->%08lx\n"
++ " ", addr, cnt );
++ lcd_puts( temp );
++}
++
++void inline spin_wheel_done( int worked )
++{
++ if( worked )
++ spin_wheel(0);
++ lcd_puts( worked ? "\ncompleted.\n" : "\nfailed!\n" );
++}
++
++void inline spin_wheel( ulong numleft )
++{
++ char temp[40];
++ sprintf( temp, "\r %08lx", numleft );
++ lcd_puts( temp );
++}
+diff -u -r --new-file u-boot-1.1.2/board/bd2003/init.script u-boot-1.1.2-neon/board/bd2003/init.script
+--- u-boot-1.1.2/board/bd2003/init.script 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/bd2003/init.script 2007-08-11 21:07:19.000000000 +0200
+@@ -0,0 +1,42 @@
++if fatload mmc 0 a0000000 logo.bmp ; then
++ bmp info a0000000 ;
++ bmp display a0000000 ;
++else
++ lecho "No logo present" ;
++fi
++
++if fatload mmc 0 a2000000 uimage ; then
++ lecho 'load Linux'
++ if fatload mmc 0 a2200000 mmcinitrd.u-boot ; then
++ echo 'using initrd' ;
++ lecho "Booting Linux"
++ set bootargs root=/dev/ram0 console=ttyS0,115200 debug=7 mtdparts=phys_mapped_flash:1024k(armboot),256k(params),-(rootfs1)
++ bootm a2000000 a2200000
++ else
++ echo 'testing cramfs img' ;
++ if fatload mmc 0 a2200000 cramfs.img ; then
++ if cmp.b 00140000 a2200000 $filesize ; then
++ echo 'cramfs images match' ;
++ else
++ lecho 'filesystems differ...' ;
++ protect off all ;
++ erase 00140000 01ffffff ;
++ cp.b a2200000 00140000 $filesize ;
++ fi
++
++ set bootargs console=ttyS0,115200 debug=7 mtdparts=phys_mapped_flash:1024k(armboot),256k(params),-(rootfs1) root=/dev/mtdblock3 rootfstype=cramfs
++ lecho "Booting Linux"
++ bootm a2000000
++ fi
++ fi
++else
++ echo "No Linux kernel" ;
++fi
++
++lecho 'No Linux, try CE'
++
++if fatload mmc 0 A0030000 nk.nb0 ; then
++ g A0030000 ;
++else
++ echo "No WinCE image" ;
++fi
+diff -u -r --new-file u-boot-1.1.2/board/bd2003/Makefile u-boot-1.1.2-neon/board/bd2003/Makefile
+--- u-boot-1.1.2/board/bd2003/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/bd2003/Makefile 2007-08-11 21:07:19.000000000 +0200
+@@ -0,0 +1,48 @@
++
++#
++# (C) Copyright 2000
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = lib$(BOARD).a
++
++OBJS := bd2003.o flash.o
++SOBJS := memsetup.o
++
++$(LIB): $(OBJS) $(SOBJS)
++ $(AR) crv $@ $(OBJS) $(SOBJS)
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
++
++-include .depend
++
++#########################################################################
+diff -u -r --new-file u-boot-1.1.2/board/bd2003/memsetup.S u-boot-1.1.2-neon/board/bd2003/memsetup.S
+--- u-boot-1.1.2/board/bd2003/memsetup.S 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/bd2003/memsetup.S 2007-08-11 21:07:19.000000000 +0200
+@@ -0,0 +1,64 @@
++/*
++ * Most of this taken from Redboot hal_platform_setup.h with cleanup
++ *
++ * NOTE: I haven't clean this up considerably, just enough to get it
++ * running. See hal_platform_setup.h for the source. See
++ * board/cradle/memsetup.S for another PXA250 setup that is
++ * much cleaner.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <config.h>
++#include <version.h>
++
++#define BAUDRATE 115200
++#include <asm/arch/platformTypes.h>
++#include <configs/select.h>
++#include <asm/arch/pxaGpio.h>
++#include <asm/arch/pxaMacro3.h>
++
++DRAM_SIZE: .long CFG_DRAM_SIZE
++
++/* wait for coprocessor write complete */
++ .macro CPWAIT reg
++ mrc p15,0,\reg,c2,c0,0
++ mov \reg,\reg
++ sub pc,pc,#4
++ .endm
++
++
++/*
++ * Memory setup
++ */
++
++.globl memsetup
++memsetup:
++
++ mov r10, lr
++
++ InitCS0_CS1 r0,sp
++ InitGPIO r0,sp
++ InitIC_Clocks r0,sp
++ InitUART r0,sp,UART_BASE,BAUDRATE
++ InitUART r0,sp,UART_BASE+0x600000,9600
++ InitChangeCPUSpeed r0
++ InitMemory r0,sp,r1
++
++ mov pc, lr
+diff -u -r --new-file u-boot-1.1.2/board/bd2003/u-boot.lds u-boot-1.1.2-neon/board/bd2003/u-boot.lds
+--- u-boot-1.1.2/board/bd2003/u-boot.lds 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/bd2003/u-boot.lds 2007-08-11 21:07:19.000000000 +0200
+@@ -0,0 +1,56 @@
++/*
++ * (C) Copyright 2000
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++ . = 0x00000000;
++
++ . = ALIGN(4);
++ .text :
++ {
++ cpu/pxa/start.o (.text)
++ cpu/pxa/ministart.o (.text)
++ *(.text)
++ }
++
++ . = ALIGN(4);
++ .rodata : { *(.rodata) }
++
++ . = ALIGN(4);
++ .data : { *(.data) }
++
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
+diff -u -r --new-file u-boot-1.1.2/board/bd2003/u-bootmini.lds u-boot-1.1.2-neon/board/bd2003/u-bootmini.lds
+--- u-boot-1.1.2/board/bd2003/u-bootmini.lds 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/bd2003/u-bootmini.lds 2007-08-11 21:07:19.000000000 +0200
+@@ -0,0 +1,56 @@
++/*
++ * (C) Copyright 2000
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++OUTPUT_ARCH(arm)
++ENTRY(StartUp)
++SECTIONS
++{
++ . = 0x00000000;
++
++ . = ALIGN(4);
++ .text :
++ {
++ cpu/pxa/minidebug.o (.text)
++ cpu/pxa/ministart.o (.text)
++ *(.text)
++ }
++
++ . = ALIGN(4);
++ .rodata : { *(.rodata) }
++
++ . = ALIGN(4);
++ .data : { *(.data) }
++
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
+diff -u -r --new-file u-boot-1.1.2/board/halogen/config.mk u-boot-1.1.2-neon/board/halogen/config.mk
+--- u-boot-1.1.2/board/halogen/config.mk 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/halogen/config.mk 2007-08-11 21:07:19.000000000 +0200
+@@ -0,0 +1,4 @@
++#TEXT_BASE = 0xa1700000
++TEXT_BASE = 0xA1F00000
++#TEXT_BASE = 0
++PXALCD = 1
+diff -u -r --new-file u-boot-1.1.2/board/halogen/.cvsignore u-boot-1.1.2-neon/board/halogen/.cvsignore
+--- u-boot-1.1.2/board/halogen/.cvsignore 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/halogen/.cvsignore 2007-08-11 21:07:19.000000000 +0200
+@@ -0,0 +1,2 @@
++.depend
++
+diff -u -r --new-file u-boot-1.1.2/board/halogen/flash.c u-boot-1.1.2-neon/board/halogen/flash.c
+--- u-boot-1.1.2/board/halogen/flash.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/halogen/flash.c 2007-08-11 21:07:19.000000000 +0200
+@@ -0,0 +1,482 @@
++/*
++ * (C) Copyright 2001
++ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
++ *
++ * (C) Copyright 2001
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <linux/byteorder/swab.h>
++#include <asm/arch/pxa250Base.h>
++#include <asm/arch/pxaHardware.h>
++#include "lcd.h"
++
++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
++
++/* Board support for 1 or 2 flash devices */
++#define FLASH_PORT_WIDTH32
++#undef FLASH_PORT_WIDTH16
++
++#ifdef FLASH_PORT_WIDTH16
++#define FLASH_PORT_WIDTH ushort
++#define FLASH_PORT_WIDTHV vu_short
++#define SWAP(x) __swab16(x)
++#else
++#define FLASH_PORT_WIDTH ulong
++#define FLASH_PORT_WIDTHV vu_long
++#define SWAP(x) __swab32(x)
++#endif
++
++#define FPW FLASH_PORT_WIDTH
++#define FPWV FLASH_PORT_WIDTHV
++
++#define mb() __asm__ __volatile__ ("" : : : "memory")
++
++/*-----------------------------------------------------------------------
++ * Functions
++ */
++static ulong flash_get_size (FPW *addr, flash_info_t *info);
++static int write_data (flash_info_t *info, ulong dest, FPW data);
++static void flash_get_offsets (ulong base, flash_info_t *info);
++void inline spin_wheel_init(ulong addr, ulong cnt);
++void inline spin_wheel_done( int worked );
++void inline spin_wheel (ulong numleft);
++
++/*-----------------------------------------------------------------------
++ */
++ulong bases[] = {PHYS_FLASH_1,PHYS_FLASH_2,1};
++unsigned long flash_init (void)
++{
++ int i=0;
++ int j=0;
++ ulong size = 0;
++ ulong base;
++
++ while (i < CFG_MAX_FLASH_BANKS) {
++ base = bases[j++];
++ flash_info[i].start[0] = 0;
++ if (base & 1) break;
++ if (flash_get_size ((FPW *) base, &flash_info[i])) {
++ flash_get_offsets (base, &flash_info[i]);
++ size += flash_info[i].size;
++ i++;
++ }
++ else {
++printf( "error reading flash size\n" );
++ }
++ }
++ if (size>0) {
++ base = flash_info[0].start[0];
++ // Protect monitor and environment sectors
++ flash_protect ( FLAG_PROTECT_SET,
++ base,
++ base + monitor_flash_len - 1,
++ &flash_info[0] );
++
++ flash_protect ( FLAG_PROTECT_SET,
++ base+CFG_ENV_OFFSET,
++ base+CFG_ENV_OFFSET + CFG_ENV_SIZE - 1, &flash_info[0] );
++ }
++
++ return size;
++}
++
++/*-----------------------------------------------------------------------
++ */
++static void flash_get_offsets (ulong base, flash_info_t *info)
++{
++ int i;
++
++ if (info->flash_id == FLASH_UNKNOWN) {
++ return;
++ }
++
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
++ for (i = 0; i < info->sector_count; i++) {
++ info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
++ info->protect[i] = 0;
++ }
++ }
++}
++
++/*-----------------------------------------------------------------------
++ */
++void flash_print_info (flash_info_t *info)
++{
++ int i;
++
++ if (info->flash_id == FLASH_UNKNOWN) {
++ printf ("missing or unknown FLASH type\n");
++ return;
++ }
++
++ switch (info->flash_id & FLASH_VENDMASK) {
++ case FLASH_MAN_INTEL:
++ printf ("INTEL ");
++ break;
++ default:
++ printf ("Unknown Vendor ");
++ break;
++ }
++
++ switch (info->flash_id & FLASH_TYPEMASK) {
++ case FLASH_28F128J3A:
++ printf ("28F128J3A\n");
++ break;
++ default:
++ printf ("Unknown Chip Type\n");
++ break;
++ }
++
++ printf (" Size: %ld MB in %d Sectors\n",
++ info->size >> 20, info->sector_count);
++
++ printf (" Sector Start Addresses:");
++ for (i = 0; i < info->sector_count; ++i) {
++ if ((i % 5) == 0)
++ printf ("\n ");
++ printf (" %08lX%s",
++ info->start[i],
++ info->protect[i] ? " (RO)" : " ");
++ }
++ printf ("\n");
++ return;
++}
++
++/*
++ * The following code cannot be run from FLASH!
++ */
++static ulong flash_get_size (FPW *addr, flash_info_t *info)
++{
++ volatile FPW value;
++ volatile unsigned long *mc = (unsigned long *)MEMORY_CONTROL_BASE;
++ unsigned long val = 1<<3;
++
++ info->flash_id = FLASH_UNKNOWN;
++ info->sector_count = 0;
++ info->size = 0;
++
++ if (((ulong)addr) > 0x14000000) return 0;
++ val = mc[(MSC0>>2) +(((ulong)addr)>>27)];
++ if (((ulong)addr) & 0x04000000) val = val>>16;
++ if ( val & (1<<3)) return 0; //if 16 bit bus then return
++
++ /* Write auto select command: read Manufacturer ID */
++ addr[0x5555] = (FPW) 0x00AA00AA;
++ addr[0x2AAA] = (FPW) 0x00550055;
++ addr[0x5555] = (FPW) 0x00900090;
++
++ mb ();
++ value = addr[0];
++
++ switch (value) {
++
++ case (FPW) 0:
++ case (FPW) STM_MANUFACT:
++ case (FPW) INTEL_MANUFACT & 0xFF0000 :
++ case (FPW) INTEL_MANUFACT & 0x0000FF :
++ case (FPW) INTEL_MANUFACT:
++ info->flash_id = FLASH_MAN_INTEL;
++ break;
++
++ default:
++printf( "Invalid flash manufacturer %x\n", value );
++ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
++ return (0); /* no or unknown flash */
++ }
++
++ mb ();
++ value = addr[1]; /* device ID */
++
++ switch (value) {
++
++ case (FPW) 0:
++ case (FPW) INTEL_ID_28F128J3A & 0xFF0000 :
++ case (FPW) INTEL_ID_28F128J3A & 0x0000FF :
++ case (FPW) INTEL_ID_28F128J3A:
++ info->flash_id += FLASH_28F128J3A;
++ info->sector_count = 128;
++ info->size = 0x01000000;
++ break; /* => 16 MB x 1 */
++ case (FPW) INTEL_ID_28F320J3A:
++ info->flash_id += FLASH_28F320J3A;
++ info->sector_count = 32 ;
++ info->size = 0x400000 ;
++ break; /* => 4 MB x 1 */
++ default:
++printf( "Unknown flash device %x\n", value );
++ info->flash_id = FLASH_UNKNOWN;
++ break;
++ }
++
++ if (info->sector_count > CFG_MAX_FLASH_SECT) {
++ printf ("** ERROR: sector count %d > max (%d) **\n",
++ info->sector_count, CFG_MAX_FLASH_SECT);
++ info->sector_count = CFG_MAX_FLASH_SECT;
++ }
++
++ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
++
++ return (info->size);
++}
++
++
++/*-----------------------------------------------------------------------
++ */
++
++int flash_erase (flash_info_t *info, int s_first, int s_last)
++{
++ int flag, prot, sect;
++ ulong type, start, last;
++ int rcode = 0;
++
++ if ((s_first < 0) || (s_first > s_last)) {
++ if (info->flash_id == FLASH_UNKNOWN) {
++ printf ("- missing\n");
++ } else {
++ printf ("- no sectors to erase\n");
++ }
++ return 1;
++ }
++
++ type = (info->flash_id & FLASH_VENDMASK);
++ if ((type != FLASH_MAN_INTEL)) {
++ printf ("Can't erase unknown flash type %08lx - aborted\n",
++ info->flash_id);
++ return 1;
++ }
++
++ prot = 0;
++ for (sect = s_first; sect <= s_last; ++sect) {
++ if (info->protect[sect]) {
++ prot++;
++ }
++ }
++
++ if (prot) {
++ printf ("- Warning: %d protected sectors will not be erased!\n",
++ prot);
++ } else {
++ printf ("\n");
++ }
++
++ start = get_timer (0);
++ last = start;
++
++ /* Disable interrupts which might cause a timeout here */
++ flag = disable_interrupts ();
++
++ /* Start erase on unprotected sectors */
++ for (sect = s_first; sect <= s_last; sect++) {
++ if (info->protect[sect] == 0) { /* not protected */
++ char temp[80];
++ FPWV *addr = (FPWV *) (info->start[sect]);
++ FPW status;
++
++ sprintf (temp, "Erasing sector %2d ... \r", sect);
++ lcd_puts( temp );
++
++ /* arm simple, non interrupt dependent timer */
++ reset_timer_masked ();
++
++ *addr = (FPW) 0x00500050; /* clear status register */
++ *addr = (FPW) 0x00200020; /* erase setup */
++ *addr = (FPW) 0x00D000D0; /* erase confirm */
++
++ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
++ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
++ printf ("Timeout\n");
++ *addr = (FPW) 0x00B000B0; /* suspend erase */
++ *addr = (FPW) 0x00FF00FF; /* reset to read mode */
++ rcode = 1;
++ break;
++ }
++ }
++
++ *addr = 0x00500050; /* clear status register cmd. */
++ *addr = 0x00FF00FF; /* resest to read mode */
++ }
++ }
++ lcd_puts( "\r\n" );
++ return rcode;
++}
++
++/*-----------------------------------------------------------------------
++ * Copy memory to flash, returns:
++ * 0 - OK
++ * 1 - write timeout
++ * 2 - Flash not erased
++ * 4 - Flash not identified
++ */
++
++int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
++{
++ ulong cp, wp;
++ FPW data;
++ int count, i, l, rc, port_width;
++
++ rc = 0 ;
++ if (info->flash_id == FLASH_UNKNOWN) {
++ return 4;
++ }
++/* get lower word aligned address */
++#ifdef FLASH_PORT_WIDTH16
++ wp = (addr & ~1);
++ port_width = 2;
++#else
++ wp = (addr & ~3);
++ port_width = 4;
++#endif
++
++ spin_wheel_init(addr,cnt);
++
++ /*
++ * handle unaligned start bytes
++ */
++ if ((l = addr - wp) != 0) {
++ data = 0;
++ for (i = 0, cp = wp; i < l; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++ for (; i < port_width && cnt > 0; ++i) {
++ data = (data << 8) | *src++;
++ --cnt;
++ ++cp;
++ }
++ for (; cnt == 0 && i < port_width; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++
++ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
++ goto out;
++ }
++ wp += port_width;
++ }
++
++ /*
++ * handle word aligned part
++ */
++ count = 0;
++ while (cnt >= port_width) {
++ data = 0;
++ for (i = 0; i < port_width; ++i) {
++ data = (data << 8) | *src++;
++ }
++ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
++ goto out;
++ }
++ wp += port_width;
++ cnt -= port_width;
++ if (count++ > 0x800) {
++ spin_wheel (cnt);
++ count = 0;
++ }
++ }
++
++ if (cnt) {
++ /*
++ * handle unaligned tail bytes
++ */
++ data = 0;
++ for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
++ data = (data << 8) | *src++;
++ --cnt;
++ }
++ for (; i < port_width; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++
++ rc = write_data (info, wp, SWAP (data));
++ }
++
++out:
++ spin_wheel_done(0 == rc);
++ return rc ;
++}
++
++/*-----------------------------------------------------------------------
++ * Write a word or halfword to Flash, returns:
++ * 0 - OK
++ * 1 - write timeout
++ * 2 - Flash not erased
++ */
++static int write_data (flash_info_t *info, ulong dest, FPW data)
++{
++ FPWV *addr = (FPWV *) dest;
++ FPW old = *addr ;
++ ulong status;
++ int flag;
++
++ /* Check if Flash is (sufficiently) erased */
++ if ((old & data) != data) {
++ printf ("not erased at %08lx (%lx)\n", (ulong) addr, old);
++ return (2);
++ }
++
++ if( old != data )
++ {
++ /* Disable interrupts which might cause a timeout here */
++ flag = disable_interrupts ();
++
++ *addr = (FPW) 0x00400040; /* write setup */
++ *addr = data;
++
++ /* arm simple, non interrupt dependent timer */
++ reset_timer_masked ();
++
++ /* wait while polling the status register */
++ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
++ if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
++ *addr = (FPW) 0x00FF00FF; /* restore read mode */
++ return (1);
++ }
++ }
++ *addr = (FPW) 0x00FF00FF; /* restore read mode */
++ } /* need to program? */
++
++
++ return (0);
++}
++
++void inline spin_wheel_init(ulong addr, ulong cnt)
++{
++ char temp[80];
++ sprintf( temp,
++ "\nprogramming flash\n"
++ "%08lx->%08lx\n"
++ " ", addr, cnt );
++ lcd_puts( temp );
++}
++
++void inline spin_wheel_done( int worked )
++{
++ if( worked )
++ spin_wheel(0);
++ lcd_puts( worked ? "\ncompleted.\n" : "\nfailed!\n" );
++}
++
++void inline spin_wheel( ulong numleft )
++{
++ char temp[40];
++ sprintf( temp, "\r %08lx", numleft );
++ lcd_puts( temp );
++}
+diff -u -r --new-file u-boot-1.1.2/board/halogen/halogen.c u-boot-1.1.2-neon/board/halogen/halogen.c
+--- u-boot-1.1.2/board/halogen/halogen.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/halogen/halogen.c 2007-08-11 21:07:19.000000000 +0200
+@@ -0,0 +1,94 @@
++/*
++ * (C) Copyright 2002
++ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
++ *
++ * (C) Copyright 2002
++ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
++ * Marius Groeger <mgroeger@sysgo.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <config.h>
++#include <common.h>
++#include <version.h>
++#include <stdarg.h>
++#include <linux/types.h>
++#include <devices.h>
++#include <lcd.h>
++#include <lcd_panels.h>
++
++/* ------------------------------------------------------------------------- */
++/*
++ * LCD panel declarations
++ */
++
++vidinfo_t panel_info = {
++ vl_col: 1024, //this is corrected in SetPanelInfo
++ vl_row: 768,
++ vl_bpix: LCD_BPP,
++ vl_lcd_line_length: (320 * NBITS(LCD_BPP) ) >> 3
++};
++
++void disable_lcd_panel( void )
++{
++}
++
++
++/* ------------------------------------------------------------------------- */
++
++
++/*
++ * Miscelaneous platform dependent initialisations
++ */
++
++int board_init (void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ /* memory and cpu-speed are setup before relocation */
++ /* so we do _nothing_ here */
++
++ /* arch number of Neon Board */
++ gd->bd->bi_arch_number = MACH_TYPE_HALOGEN ;
++
++ /* adress of boot parameters */
++ gd->bd->bi_boot_params = 0xa0000100;
++
++ return 0;
++}
++
++int board_late_init(void)
++{
++ setenv("stdout", "serial");
++ setenv("stderr", "serial");
++ return 0;
++}
++
++
++int dram_init (void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++
++ return 0;
++}
+diff -u -r --new-file u-boot-1.1.2/board/halogen/init.script u-boot-1.1.2-neon/board/halogen/init.script
+--- u-boot-1.1.2/board/halogen/init.script 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/halogen/init.script 2007-08-11 21:07:19.000000000 +0200
+@@ -0,0 +1,42 @@
++if fatload mmc 0 a0008000 logo*.bmp ; then
++ bmp info a0008000 ;
++ bmp display a0008000 ;
++else
++ lecho "No logo present" ;
++fi
++
++if fatload mmc 0 a2000000 uim* ; then
++ lecho 'load Linux'
++ if fatload mmc 0 a2200000 mmcinitrd* ; then
++ echo 'using initrd' ;
++ lecho "Booting Linux"
++ set bootargs root=/dev/ram0 console=ttyS0,115200 debug=7 mtdparts=phys_mapped_flash:1024k(armboot),256k(params),-(rootfs1)
++ bootm a2000000 a2200000
++ else
++ echo 'testing cramfs img' ;
++ if fatload mmc 0 a2200000 cramfs* ; then
++ if cmp.b 00140000 a2200000 $filesize ; then
++ echo 'cramfs images match' ;
++ else
++ lecho 'filesystems differ...' ;
++ protect off all ;
++ erase 00140000 01ffffff ;
++ cp.b a2200000 00140000 $filesize ;
++ fi
++
++ set bootargs console=ttyS0,115200 debug=7 mtdparts=phys_mapped_flash:1024k(armboot),256k(params),-(rootfs1) root=/dev/mtdblock3 rootfstype=cramfs
++ lecho "Booting Linux"
++ bootm a2000000
++ fi
++ fi
++else
++ echo "No Linux kernel" ;
++fi
++
++lecho 'No Linux, try CE'
++
++if fatload mmc 0 A0030000 nk*.nb0 ; then
++ g A0030000 ;
++else
++ echo "No WinCE image" ;
++fi
+diff -u -r --new-file u-boot-1.1.2/board/halogen/Makefile u-boot-1.1.2-neon/board/halogen/Makefile
+--- u-boot-1.1.2/board/halogen/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/halogen/Makefile 2007-08-11 21:07:19.000000000 +0200
+@@ -0,0 +1,48 @@
++
++#
++# (C) Copyright 2000
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = lib$(BOARD).a
++
++OBJS := halogen.o flash.o
++SOBJS := memsetup.o
++
++$(LIB): $(OBJS) $(SOBJS)
++ $(AR) crv $@ $(OBJS) $(SOBJS)
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
++
++-include .depend
++
++#########################################################################
+diff -u -r --new-file u-boot-1.1.2/board/halogen/memsetup.S u-boot-1.1.2-neon/board/halogen/memsetup.S
+--- u-boot-1.1.2/board/halogen/memsetup.S 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/halogen/memsetup.S 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,64 @@
++/*
++ * Most of this taken from Redboot hal_platform_setup.h with cleanup
++ *
++ * NOTE: I haven't clean this up considerably, just enough to get it
++ * running. See hal_platform_setup.h for the source. See
++ * board/cradle/memsetup.S for another PXA250 setup that is
++ * much cleaner.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <config.h>
++#include <version.h>
++
++#define BAUDRATE 115200
++#include <asm/arch/platformTypes.h>
++#include <configs/select.h>
++#include <asm/arch/pxaGpio.h>
++#include <asm/arch/pxaMacro3.h>
++
++DRAM_SIZE: .long CFG_DRAM_SIZE
++
++/* wait for coprocessor write complete */
++ .macro CPWAIT reg
++ mrc p15,0,\reg,c2,c0,0
++ mov \reg,\reg
++ sub pc,pc,#4
++ .endm
++
++
++/*
++ * Memory setup
++ */
++
++.globl memsetup
++memsetup:
++
++ mov r10, lr
++
++ InitCS0_CS1 r0,sp
++ InitGPIO r0,sp
++ InitIC_Clocks r0,sp
++ InitUART r0,sp,UART_BASE,BAUDRATE
++ InitUART r0,sp,UART_BASE+0x600000,9600
++ InitChangeCPUSpeed r0
++ InitMemory r0,sp,r1
++
++ mov pc, lr
+diff -u -r --new-file u-boot-1.1.2/board/halogen/u-boot.lds u-boot-1.1.2-neon/board/halogen/u-boot.lds
+--- u-boot-1.1.2/board/halogen/u-boot.lds 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/halogen/u-boot.lds 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,56 @@
++/*
++ * (C) Copyright 2000
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++ . = 0x00000000;
++
++ . = ALIGN(4);
++ .text :
++ {
++ cpu/pxa/start.o (.text)
++ cpu/pxa/ministart.o (.text)
++ *(.text)
++ }
++
++ . = ALIGN(4);
++ .rodata : { *(.rodata) }
++
++ . = ALIGN(4);
++ .data : { *(.data) }
++
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
+diff -u -r --new-file u-boot-1.1.2/board/halogen/u-bootmini.lds u-boot-1.1.2-neon/board/halogen/u-bootmini.lds
+--- u-boot-1.1.2/board/halogen/u-bootmini.lds 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/halogen/u-bootmini.lds 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,56 @@
++/*
++ * (C) Copyright 2000
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++OUTPUT_ARCH(arm)
++ENTRY(StartUp)
++SECTIONS
++{
++ . = 0x00000000;
++
++ . = ALIGN(4);
++ .text :
++ {
++ cpu/pxa/minidebug.o (.text)
++ cpu/pxa/ministart.o (.text)
++ *(.text)
++ }
++
++ . = ALIGN(4);
++ .rodata : { *(.rodata) }
++
++ . = ALIGN(4);
++ .data : { *(.data) }
++
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
+diff -u -r --new-file u-boot-1.1.2/board/neon/config.mk u-boot-1.1.2-neon/board/neon/config.mk
+--- u-boot-1.1.2/board/neon/config.mk 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/neon/config.mk 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,4 @@
++#TEXT_BASE = 0xa1700000
++TEXT_BASE = 0xA1F00000
++#TEXT_BASE = 0
++#PXALCD = 1
+diff -u -r --new-file u-boot-1.1.2/board/neon/.cvsignore u-boot-1.1.2-neon/board/neon/.cvsignore
+--- u-boot-1.1.2/board/neon/.cvsignore 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/neon/.cvsignore 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,2 @@
++.depend
++
+diff -u -r --new-file u-boot-1.1.2/board/neon/flash.c u-boot-1.1.2-neon/board/neon/flash.c
+--- u-boot-1.1.2/board/neon/flash.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/neon/flash.c 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,482 @@
++/*
++ * (C) Copyright 2001
++ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
++ *
++ * (C) Copyright 2001
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <linux/byteorder/swab.h>
++#include <asm/arch/pxa250Base.h>
++#include <asm/arch/pxaHardware.h>
++#include "lcd.h"
++
++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
++
++/* Board support for 1 or 2 flash devices */
++#define FLASH_PORT_WIDTH32
++#undef FLASH_PORT_WIDTH16
++
++#ifdef FLASH_PORT_WIDTH16
++#define FLASH_PORT_WIDTH ushort
++#define FLASH_PORT_WIDTHV vu_short
++#define SWAP(x) __swab16(x)
++#else
++#define FLASH_PORT_WIDTH ulong
++#define FLASH_PORT_WIDTHV vu_long
++#define SWAP(x) __swab32(x)
++#endif
++
++#define FPW FLASH_PORT_WIDTH
++#define FPWV FLASH_PORT_WIDTHV
++
++#define mb() __asm__ __volatile__ ("" : : : "memory")
++
++/*-----------------------------------------------------------------------
++ * Functions
++ */
++static ulong flash_get_size (FPW *addr, flash_info_t *info);
++static int write_data (flash_info_t *info, ulong dest, FPW data);
++static void flash_get_offsets (ulong base, flash_info_t *info);
++void inline spin_wheel_init(ulong addr, ulong cnt);
++void inline spin_wheel_done( int worked );
++void inline spin_wheel (ulong numleft);
++
++/*-----------------------------------------------------------------------
++ */
++ulong bases[] = {PHYS_FLASH_1,PHYS_FLASH_2,1};
++unsigned long flash_init (void)
++{
++ int i=0;
++ int j=0;
++ ulong size = 0;
++ ulong base;
++
++ while (i < CFG_MAX_FLASH_BANKS) {
++ base = bases[j++];
++ flash_info[i].start[0] = 0;
++ if (base & 1) break;
++ if (flash_get_size ((FPW *) base, &flash_info[i])) {
++ flash_get_offsets (base, &flash_info[i]);
++ size += flash_info[i].size;
++ i++;
++ }
++ else {
++printf( "error reading flash size\n" );
++ }
++ }
++ if (size>0) {
++ base = flash_info[0].start[0];
++ // Protect monitor and environment sectors
++ flash_protect ( FLAG_PROTECT_SET,
++ base,
++ base + monitor_flash_len - 1,
++ &flash_info[0] );
++
++ flash_protect ( FLAG_PROTECT_SET,
++ base+CFG_ENV_OFFSET,
++ base+CFG_ENV_OFFSET + CFG_ENV_SIZE - 1, &flash_info[0] );
++ }
++
++ return size;
++}
++
++/*-----------------------------------------------------------------------
++ */
++static void flash_get_offsets (ulong base, flash_info_t *info)
++{
++ int i;
++
++ if (info->flash_id == FLASH_UNKNOWN) {
++ return;
++ }
++
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
++ for (i = 0; i < info->sector_count; i++) {
++ info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
++ info->protect[i] = 0;
++ }
++ }
++}
++
++/*-----------------------------------------------------------------------
++ */
++void flash_print_info (flash_info_t *info)
++{
++ int i;
++
++ if (info->flash_id == FLASH_UNKNOWN) {
++ printf ("missing or unknown FLASH type\n");
++ return;
++ }
++
++ switch (info->flash_id & FLASH_VENDMASK) {
++ case FLASH_MAN_INTEL:
++ printf ("INTEL ");
++ break;
++ default:
++ printf ("Unknown Vendor ");
++ break;
++ }
++
++ switch (info->flash_id & FLASH_TYPEMASK) {
++ case FLASH_28F128J3A:
++ printf ("28F128J3A\n");
++ break;
++ default:
++ printf ("Unknown Chip Type\n");
++ break;
++ }
++
++ printf (" Size: %ld MB in %d Sectors\n",
++ info->size >> 20, info->sector_count);
++
++ printf (" Sector Start Addresses:");
++ for (i = 0; i < info->sector_count; ++i) {
++ if ((i % 5) == 0)
++ printf ("\n ");
++ printf (" %08lX%s",
++ info->start[i],
++ info->protect[i] ? " (RO)" : " ");
++ }
++ printf ("\n");
++ return;
++}
++
++/*
++ * The following code cannot be run from FLASH!
++ */
++static ulong flash_get_size (FPW *addr, flash_info_t *info)
++{
++ volatile FPW value;
++ volatile unsigned long *mc = (unsigned long *)MEMORY_CONTROL_BASE;
++ unsigned long val = 1<<3;
++
++ info->flash_id = FLASH_UNKNOWN;
++ info->sector_count = 0;
++ info->size = 0;
++
++ if (((ulong)addr) > 0x14000000) return 0;
++ val = mc[(MSC0>>2) +(((ulong)addr)>>27)];
++ if (((ulong)addr) & 0x04000000) val = val>>16;
++ if ( val & (1<<3)) return 0; //if 16 bit bus then return
++
++ /* Write auto select command: read Manufacturer ID */
++ addr[0x5555] = (FPW) 0x00AA00AA;
++ addr[0x2AAA] = (FPW) 0x00550055;
++ addr[0x5555] = (FPW) 0x00900090;
++
++ mb ();
++ value = addr[0];
++
++ switch (value) {
++
++ case (FPW) 0:
++ case (FPW) STM_MANUFACT:
++ case (FPW) INTEL_MANUFACT & 0xFF0000 :
++ case (FPW) INTEL_MANUFACT & 0x0000FF :
++ case (FPW) INTEL_MANUFACT:
++ info->flash_id = FLASH_MAN_INTEL;
++ break;
++
++ default:
++printf( "Invalid flash manufacturer %x\n", value );
++ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
++ return (0); /* no or unknown flash */
++ }
++
++ mb ();
++ value = addr[1]; /* device ID */
++
++ switch (value) {
++
++ case (FPW) 0:
++ case (FPW) INTEL_ID_28F128J3A & 0xFF0000 :
++ case (FPW) INTEL_ID_28F128J3A & 0x0000FF :
++ case (FPW) INTEL_ID_28F128J3A:
++ info->flash_id += FLASH_28F128J3A;
++ info->sector_count = 128;
++ info->size = 0x02000000;
++ break; /* => 16 MB x 2 */
++ case (FPW) INTEL_ID_28F320J3A:
++ info->flash_id += FLASH_28F320J3A;
++ info->sector_count = 32 ;
++ info->size = 0x800000 ;
++ break; /* => 4 MB x 2 */
++ default:
++printf( "Unknown flash device %x\n", value );
++ info->flash_id = FLASH_UNKNOWN;
++ break;
++ }
++
++ if (info->sector_count > CFG_MAX_FLASH_SECT) {
++ printf ("** ERROR: sector count %d > max (%d) **\n",
++ info->sector_count, CFG_MAX_FLASH_SECT);
++ info->sector_count = CFG_MAX_FLASH_SECT;
++ }
++
++ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
++
++ return (info->size);
++}
++
++
++/*-----------------------------------------------------------------------
++ */
++
++int flash_erase (flash_info_t *info, int s_first, int s_last)
++{
++ int flag, prot, sect;
++ ulong type, start, last;
++ int rcode = 0;
++
++ if ((s_first < 0) || (s_first > s_last)) {
++ if (info->flash_id == FLASH_UNKNOWN) {
++ printf ("- missing\n");
++ } else {
++ printf ("- no sectors to erase\n");
++ }
++ return 1;
++ }
++
++ type = (info->flash_id & FLASH_VENDMASK);
++ if ((type != FLASH_MAN_INTEL)) {
++ printf ("Can't erase unknown flash type %08lx - aborted\n",
++ info->flash_id);
++ return 1;
++ }
++
++ prot = 0;
++ for (sect = s_first; sect <= s_last; ++sect) {
++ if (info->protect[sect]) {
++ prot++;
++ }
++ }
++
++ if (prot) {
++ printf ("- Warning: %d protected sectors will not be erased!\n",
++ prot);
++ } else {
++ printf ("\n");
++ }
++
++ start = get_timer (0);
++ last = start;
++
++ /* Disable interrupts which might cause a timeout here */
++ flag = disable_interrupts ();
++
++ /* Start erase on unprotected sectors */
++ for (sect = s_first; sect <= s_last; sect++) {
++ if (info->protect[sect] == 0) { /* not protected */
++ char temp[80];
++ FPWV *addr = (FPWV *) (info->start[sect]);
++ FPW status;
++
++ sprintf (temp, "Erasing sector %2d ... \r", sect);
++ lcd_puts( temp );
++
++ /* arm simple, non interrupt dependent timer */
++ reset_timer_masked ();
++
++ *addr = (FPW) 0x00500050; /* clear status register */
++ *addr = (FPW) 0x00200020; /* erase setup */
++ *addr = (FPW) 0x00D000D0; /* erase confirm */
++
++ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
++ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
++ printf ("Timeout\n");
++ *addr = (FPW) 0x00B000B0; /* suspend erase */
++ *addr = (FPW) 0x00FF00FF; /* reset to read mode */
++ rcode = 1;
++ break;
++ }
++ }
++
++ *addr = 0x00500050; /* clear status register cmd. */
++ *addr = 0x00FF00FF; /* resest to read mode */
++ }
++ }
++ lcd_puts( "\r\n" );
++ return rcode;
++}
++
++/*-----------------------------------------------------------------------
++ * Copy memory to flash, returns:
++ * 0 - OK
++ * 1 - write timeout
++ * 2 - Flash not erased
++ * 4 - Flash not identified
++ */
++
++int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
++{
++ ulong cp, wp;
++ FPW data;
++ int count, i, l, rc, port_width;
++
++ rc = 0 ;
++ if (info->flash_id == FLASH_UNKNOWN) {
++ return 4;
++ }
++/* get lower word aligned address */
++#ifdef FLASH_PORT_WIDTH16
++ wp = (addr & ~1);
++ port_width = 2;
++#else
++ wp = (addr & ~3);
++ port_width = 4;
++#endif
++
++ spin_wheel_init(addr,cnt);
++
++ /*
++ * handle unaligned start bytes
++ */
++ if ((l = addr - wp) != 0) {
++ data = 0;
++ for (i = 0, cp = wp; i < l; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++ for (; i < port_width && cnt > 0; ++i) {
++ data = (data << 8) | *src++;
++ --cnt;
++ ++cp;
++ }
++ for (; cnt == 0 && i < port_width; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++
++ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
++ goto out;
++ }
++ wp += port_width;
++ }
++
++ /*
++ * handle word aligned part
++ */
++ count = 0;
++ while (cnt >= port_width) {
++ data = 0;
++ for (i = 0; i < port_width; ++i) {
++ data = (data << 8) | *src++;
++ }
++ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
++ goto out;
++ }
++ wp += port_width;
++ cnt -= port_width;
++ if (count++ > 0x800) {
++ spin_wheel (cnt);
++ count = 0;
++ }
++ }
++
++ if (cnt) {
++ /*
++ * handle unaligned tail bytes
++ */
++ data = 0;
++ for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
++ data = (data << 8) | *src++;
++ --cnt;
++ }
++ for (; i < port_width; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *) cp);
++ }
++
++ rc = write_data (info, wp, SWAP (data));
++ }
++
++out:
++ spin_wheel_done(0 == rc);
++ return rc ;
++}
++
++/*-----------------------------------------------------------------------
++ * Write a word or halfword to Flash, returns:
++ * 0 - OK
++ * 1 - write timeout
++ * 2 - Flash not erased
++ */
++static int write_data (flash_info_t *info, ulong dest, FPW data)
++{
++ FPWV *addr = (FPWV *) dest;
++ FPW old = *addr ;
++ ulong status;
++ int flag;
++
++ /* Check if Flash is (sufficiently) erased */
++ if ((old & data) != data) {
++ printf ("not erased at %08lx (%lx)\n", (ulong) addr, old);
++ return (2);
++ }
++
++ if( old != data )
++ {
++ /* Disable interrupts which might cause a timeout here */
++ flag = disable_interrupts ();
++
++ *addr = (FPW) 0x00400040; /* write setup */
++ *addr = data;
++
++ /* arm simple, non interrupt dependent timer */
++ reset_timer_masked ();
++
++ /* wait while polling the status register */
++ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
++ if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
++ *addr = (FPW) 0x00FF00FF; /* restore read mode */
++ return (1);
++ }
++ }
++ *addr = (FPW) 0x00FF00FF; /* restore read mode */
++ } /* need to program? */
++
++
++ return (0);
++}
++
++void inline spin_wheel_init(ulong addr, ulong cnt)
++{
++ char temp[80];
++ sprintf( temp,
++ "\nprogramming flash\n"
++ "%08lx->%08lx\n"
++ " ", addr, cnt );
++ lcd_puts( temp );
++}
++
++void inline spin_wheel_done( int worked )
++{
++ if( worked )
++ spin_wheel(0);
++ lcd_puts( worked ? "\ncompleted.\n" : "\nfailed!\n" );
++}
++
++void inline spin_wheel( ulong numleft )
++{
++ char temp[40];
++ sprintf( temp, "\r %08lx", numleft );
++ lcd_puts( temp );
++}
+diff -u -r --new-file u-boot-1.1.2/board/neon/init.script u-boot-1.1.2-neon/board/neon/init.script
+--- u-boot-1.1.2/board/neon/init.script 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/neon/init.script 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,42 @@
++if fatload mmc 0 a0008000 logo*.bmp ; then
++ bmp info a0008000 ;
++ bmp display a0008000 ;
++else
++ lecho "No logo present" ;
++fi
++
++if fatload mmc 0 a2000000 uim* ; then
++ lecho 'load Linux'
++ if fatload mmc 0 a2200000 mmcinitrd* ; then
++ echo 'using initrd' ;
++ lecho "Booting Linux"
++ set bootargs root=/dev/ram0 console=ttyS0,115200 debug=7 mtdparts=phys_mapped_flash:1024k(armboot),256k(params),-(rootfs1)
++ bootm a2000000 a2200000
++ else
++ echo 'testing cramfs img' ;
++ if fatload mmc 0 a2200000 cramfs* ; then
++ if cmp.b 00140000 a2200000 $filesize ; then
++ echo 'cramfs images match' ;
++ else
++ lecho 'filesystems differ...' ;
++ protect off all ;
++ erase 00140000 01ffffff ;
++ cp.b a2200000 00140000 $filesize ;
++ fi
++
++ set bootargs console=ttyS0,115200 debug=7 mtdparts=phys_mapped_flash:1024k(armboot),256k(params),-(rootfs1) root=/dev/mtdblock3 rootfstype=cramfs
++ lecho "Booting Linux"
++ bootm a2000000
++ fi
++ fi
++else
++ echo "No Linux kernel" ;
++fi
++
++lecho 'No Linux, try CE'
++
++if fatload mmc 0 A0030000 nk*.nb0 ; then
++ g A0030000 ;
++else
++ echo "No WinCE image" ;
++fi
+diff -u -r --new-file u-boot-1.1.2/board/neon/Makefile u-boot-1.1.2-neon/board/neon/Makefile
+--- u-boot-1.1.2/board/neon/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/neon/Makefile 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,48 @@
++
++#
++# (C) Copyright 2000
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = lib$(BOARD).a
++
++OBJS := neon.o flash.o rtc_M41T81S.o
++SOBJS := memsetup.o
++
++$(LIB): $(OBJS) $(SOBJS)
++ $(AR) crv $@ $(OBJS) $(SOBJS)
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
++ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
++
++-include .depend
++
++#########################################################################
+diff -u -r --new-file u-boot-1.1.2/board/neon/memsetup.S u-boot-1.1.2-neon/board/neon/memsetup.S
+--- u-boot-1.1.2/board/neon/memsetup.S 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/neon/memsetup.S 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,64 @@
++/*
++ * Most of this taken from Redboot hal_platform_setup.h with cleanup
++ *
++ * NOTE: I haven't clean this up considerably, just enough to get it
++ * running. See hal_platform_setup.h for the source. See
++ * board/cradle/memsetup.S for another PXA250 setup that is
++ * much cleaner.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <config.h>
++#include <version.h>
++
++#define BAUDRATE 115200
++#include <asm/arch/platformTypes.h>
++#include <configs/select.h>
++#include <asm/arch/pxaGpio.h>
++#include <asm/arch/pxaMacro3.h>
++
++DRAM_SIZE: .long CFG_DRAM_SIZE
++
++/* wait for coprocessor write complete */
++ .macro CPWAIT reg
++ mrc p15,0,\reg,c2,c0,0
++ mov \reg,\reg
++ sub pc,pc,#4
++ .endm
++
++
++/*
++ * Memory setup
++ */
++
++.globl memsetup
++memsetup:
++
++ mov r10, lr
++
++ InitCS0_CS1 r0,sp
++ InitGPIO r0,sp
++ InitIC_Clocks r0,sp
++ InitUART r0,sp,UART_BASE,BAUDRATE
++ InitUART r0,sp,UART_BASE+0x600000,9600
++ InitChangeCPUSpeed r0
++ InitMemory r0,sp,r1
++
++ mov pc, lr
+diff -u -r --new-file u-boot-1.1.2/board/neon/neon.c u-boot-1.1.2-neon/board/neon/neon.c
+--- u-boot-1.1.2/board/neon/neon.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/neon/neon.c 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,615 @@
++/*
++ * (C) Copyright 2002
++ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
++ *
++ * (C) Copyright 2002
++ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
++ * Marius Groeger <mgroeger@sysgo.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <config.h>
++#include <common.h>
++#include <version.h>
++#include <stdarg.h>
++#include <linux/types.h>
++#include <devices.h>
++#include <lcd.h>
++#include <lcd_panels.h>
++
++#define FASTCLOCK1 0x291A0201 //faster pixel clock: P2S = 1, P2 = 9 (/6) ( panel source 1, divide by 6)
++ // V2S = 1, V2 = 10 (/12) ( crt source 1, divide by 12)
++ // M2S = 0, MR = 2 (/4) (sdram source 1, divide by 4)
++ // M1S = 0, MR = 1 (/2)
++ // miscTimReg[5:4] == 0 (336 MHz)
++ // / 6 == 56 MHz
++ //
++#define FASTCLOCK2 0x291A0201
++#define FASTCLOCK3 0x00080800
++
++#define SLOWCLOCK1 0x0A1A0201 //slow pixel clock: P2S = 0, P2 = 10 (/12) ( panel source 0, divide by 12)
++ // V2S = 1, V2 = 10 (/12) ( crt source 1, divide by 12)
++ // M2S = 0, MR = 2 (/4) (sdram source 1, divide by 4)
++ // M1S = 0, MR = 1 (/2)
++ // miscTimReg[5:4] == 0 (288 MHz)
++ // / 12 == 24 MHz
++ //
++#define SLOWCLOCK2 0x0A1A0A09
++#define SLOWCLOCK3 0x00090900
++
++unsigned long const fbStart = 0x0C000000 ;
++unsigned long const fbMax = 0x00800000 ; //
++
++unsigned long const mmioStart = 0xFE00000 ;
++unsigned long const mmioLength = 0x00200000 ;
++unsigned long const lcdPaletteRegs = 0xFE80400 ;
++unsigned long const crtPaletteRegs = 0xFE80C00 ;
++unsigned long paletteRegs = 0xFE80400 ;
++
++const unsigned int sm501_list1[]={
++ 0x0FE00000,
++ 0x00100000,0x00001002,0x00000000,0x00000000,0x07F127C0,0x05146732,0x40715128,0x00000000,
++ 0x00000000,0x00180002,0x00000002,0x00000002,0x00000000,0x00000000,0x0000001F,0x291A0201,
++ 0x0000001F,0x291A0201,0x00000007,0x291A0201,0x00018000,0x00000000,0x00000000,0x00000000,
++ 0x050100A0,0x00000000,0x00080800};
++
++const unsigned int sm501_list2[]={ 0x0fe80000,
++/* 80000 dispctrl */ 0x0F013100, // 0f0d0105
++/* 80004 pan */ 0x00000000,
++/* 80008 colorkey */ 0x00000000,
++/* 8000C fbaddr */ 0x00000000,
++/* 80010 offsetww */ 0x00000000, // ((LCD_XRES)<<16)+(LCD_XRES),
++/* 80014 fbwidth */ 0x00000000, // (LCD_XRES<<16),
++/* 80018 fbheight */ 0x00000000, // (LCD_YRES<<16),
++/* 8001C tllocate */ 0x00000000,
++/* 80020 brlocate */ 0x00000000, // ((LCD_YRES-1)<<16)+(LCD_XRES-1),
++/* 80024 htotal */ 0x00000000, // ((LCD_BEGIN_OF_LINE_WAIT_COUNT+
++/* */ // LCD_XRES+
++/* */ // LCD_END_OF_LINE_WAIT_COUNT+
++/* */ // LCD_HORIZONTAL_SYNC_PULSE_WIDTH-1)<<16)
++/* */ // +(LCD_XRES-1),
++/* 80028 hsync */ 0x00000000, // (LCD_HORIZONTAL_SYNC_PULSE_WIDTH<<16)
++/* */ // +(LCD_XRES+LCD_BEGIN_OF_LINE_WAIT_COUNT-1),
++/* 8002C vtotal */ 0x00000000, // ((LCD_BEGIN_FRAME_WAIT_COUNT+
++/* */ // LCD_YRES+
++/* */ // LCD_END_OF_FRAME_WAIT_COUNT+
++/* */ // LCD_VERTICAL_SYNC_PULSE_WIDTH-1)<<16)
++/* */ // +(LCD_YRES-1),
++/* 80030 vsync */ 0x00000000, // (LCD_VERTICAL_SYNC_PULSE_WIDTH<<16)
++/* */ // +(LCD_YRES+LCD_BEGIN_FRAME_WAIT_COUNT-1)
++};
++
++static unsigned const miscCtrl = 0x00000004 ;
++static unsigned const curClockReg = 0x0000003C ;
++static unsigned const pm0ClockReg = 0x00000044 ;
++static unsigned const pm1ClockReg = 0x0000004C ;
++static unsigned const miscTimReg = 0x00000068 ;
++
++static unsigned const dispctrlReg = 0x00080000 ;
++static unsigned const offsetReg = 0x00080010 ; // ((xres)<<16)+(xres),
++static unsigned const fbWidthReg = 0x00080014 ; // (xres<<16),
++static unsigned const fbHeightReg = 0x00080018 ; // (yres<<16),
++static unsigned const brLocateReg = 0x00080020 ; // ((yres-1)<<16)+(xres-1),
++static unsigned const hTotalReg = 0x00080024 ; // (left_margin+xres+right_margin+hsync_len-1) << 16
++ // + xres
++static unsigned const hSyncReg = 0x00080028 ; // (hsync_len<<16) + (xres+left_margin-1)
++static unsigned const vTotalReg = 0x0008002c ; // (top_margin+yres+lower_margin+vsync_len-1) << 16
++ // + yres-1
++static unsigned const vSyncReg = 0x00080030 ; // (vsync_len<<16) + yres+top_margin-1
++
++/*
++ * CRT regs
++ */
++static unsigned const crtctrlReg = 0x00080200 ;
++static unsigned const crtFbAddrReg = 0x00080204 ;
++static unsigned const crtFbOffsReg = 0x00080208 ;
++static unsigned const crtFbHTotReg = 0x0008020C ;
++static unsigned const crtFbHSynReg = 0x00080210 ;
++static unsigned const crtFbVTotReg = 0x00080214 ;
++static unsigned const crtFbVSynReg = 0x00080218 ;
++
++#define DISPCRTL_ENABLE 4
++
++#define CLOCK_ACTIVEHIGH 0
++#define CLOCK_ACTIVELOW (1<<14)
++#define CLOCK_ACTIVEMASK (1<<14)
++
++#define LCDTYPE_TFT 0
++#define LCDTYPE_STN12 (3<<18)
++#define LCDTYPE_MASK (3<<18)
++
++#define READREG( addr ) *( (unsigned long volatile *)((addr)+mmioStart) )
++#define STUFFREG( addr, value ) *( (unsigned long volatile *)((addr)+mmioStart) ) = (value)
++
++const unsigned int sm501_list3[]={0x0fe80040,
++ 0x00010000,0x0703E360,0x00200400,0x00A81330,0x0385009C,0x02200240,0x00000000,0x00000000,
++ 0x00EDEDED,0x089C4040,0x0031E3B0};
++
++const unsigned int sm501_list4[]={0x0fe80080,
++ 0x00010000,0x05121880,0x28800C00,0x00108030,0x02090040,0x00840050,0x00000000,0x00000000,
++ 0x0141A200,0x020A0802,0x0088D109,0x20820040,0x10800000,0x30029200,0x00080821,0x01010400,
++ 0x44000120,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
++ 0x00000000,0x00000000,0x00000000,0x00000000};
++
++const unsigned int sm501_list5[]={0x0fe800f0,
++ 0x0070F800,0x00780140,0x00000000,0x0000FFFF,0x00010000};
++
++struct itemEntry {
++ const int cnt;
++ const unsigned int* p;
++};
++
++const struct itemEntry lists[] = {
++ {sizeof(sm501_list1)>>2,sm501_list1},
++ {sizeof(sm501_list2)>>2,sm501_list2},
++ {sizeof(sm501_list3)>>2,sm501_list3},
++ {sizeof(sm501_list4)>>2,sm501_list4},
++ {sizeof(sm501_list5)>>2,sm501_list5}
++};
++
++int lcd_color_fg;
++int lcd_color_bg;
++
++void *lcd_base; /* Start of framebuffer memory */
++void *lcd_console_address; /* Start of console buffer */
++
++short console_col;
++short console_row;
++
++
++ulong calc_fbsize (void)
++{
++ if( cur_lcd_panel )
++ {
++ int line_length = (cur_lcd_panel->xres * NBITS (LCD_BPP)) / 8;
++ return ( cur_lcd_panel->yres * line_length ) + PAGE_SIZE ;
++ }
++ else
++ return 0 ;
++}
++
++void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
++{
++ unsigned long *const palette = (unsigned long *)paletteRegs ;
++ unsigned long const rgb = ((unsigned long)red ) << 16
++ | ((unsigned long)green ) << 8
++ | blue ;
++ palette[regno] = rgb ;
++}
++
++void lcd_ctrl_init (void *lcdbase)
++{
++ unsigned short *fbMem;
++ char *panelName ;
++
++ unsigned long val=0;
++ const struct itemEntry* l = lists;
++ int count = sizeof(lists)/sizeof(struct itemEntry);
++ printf( "sm501 init start\n");
++
++ while (count) {
++ int cnt = l->cnt-1;
++ const unsigned long* p = (unsigned long*)l->p;
++ volatile unsigned int* reg = (unsigned int*)(*p++);
++// printf( "set regs: %p, cnt:%x, from %p, l:%p\n", reg, cnt, p,l );
++// while (reg==0) {
++// }
++
++ while (cnt) {
++ val = *p++;
++// printf( "set reg: %p = %x from %p\n", reg, val, p );
++ *reg++ = val;
++ cnt--;
++ }
++ count--;
++ l++;
++ }
++// printf( "sm501 init middle\n");
++
++ panelName = getenv( "panel" );
++// printf( "after getenv\n");
++ if( panelName )
++ {
++ struct lcd_panel_info_t const *panel ;
++ panel = find_lcd_panel( panelName );
++ if( panel )
++ {
++ printf( "panel %s found: %u x %u\n", panelName, panel->xres, panel->yres );
++// printf( "before set_lcd_panel\n");
++ set_lcd_panel( panel );
++// printf( "after set_lcd_panel\n");
++ }
++ else
++ printf( "panel %s not found\n", panelName );
++ }
++
++ fbMem = (unsigned short *)fbStart ;
++ lcd_base = fbMem ;
++
++/*
++Settings for Hitachi 5.7
++ PANEL_HORIZONTAL_TOTAL, 01c00160);
++ PANEL_HORIZONTAL_SYNC, 00400161);
++ PANEL_VERTICAL_TOTAL, 0x010800f0);
++ PANEL_VERTICAL_SYNC, 0x00020104);
++
++In bdlogo.bmp - offset 436 is pixel data
++ STUFFREG( hTotalReg, 0x01800140 );
++ STUFFREG( hSyncReg, 0x0008014f );
++ STUFFREG( vTotalReg, 0x010700F0 );
++ STUFFREG( vSyncReg, 0x00020100 );
++*/
++ printf( "lcd_ctrl_init exit\n");
++}
++
++void lcd_enable (void)
++{
++}
++
++#define BIT29 (1<<29)
++
++static void setClockReg( unsigned reg, unsigned long value )
++{
++ unsigned oldValue = READREG( reg );
++ if( (oldValue & BIT29) != (value&BIT29) )
++ {
++ oldValue = (oldValue & (~BIT29))
++ | (value & BIT29);
++ STUFFREG( reg, oldValue );
++ udelay(16000);
++ }
++
++ if( oldValue != value )
++ STUFFREG( reg, value );
++}
++
++vidinfo_t panel_info = {
++ vl_col: 320, //this is corrected in SetPanelInfo
++ vl_row: 240,
++ vl_bpix: LCD_BPP,
++ vl_lcd_line_length: (320 * NBITS(LCD_BPP) ) >> 3
++};
++
++static void SetPanelInfo(struct lcd_panel_info_t const *panel)
++{
++ panel_info.vl_col = panel->xres;
++ panel_info.vl_row = panel->yres;
++ panel_info.vl_bpix = LCD_BPP;
++ panel_info.vl_lcd_line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) >> 3;
++ printf("panel: %ix%ix%i\n",panel_info.vl_col,panel_info.vl_row,(1<<panel_info.vl_bpix));
++}
++
++static unsigned long clockRegs[] = {
++ SLOWCLOCK1, SLOWCLOCK2,
++ FASTCLOCK1, FASTCLOCK2
++};
++
++static unsigned const numClockRegs = sizeof(clockRegs)/sizeof(clockRegs[0])/2 ;
++
++/*
++ * The following tables were built by screen-scraping and sorting
++ * the tables in the SM501 manual:
++ *
++ * Fields are:
++ * frequency in Hz
++ * clock source (0 == 288MHz, 1 == 366 MHz)
++ * select bits (5 bits for panels, 4 bits for CRTs)
++ */
++#define ENTRIESPERFREQ 3
++unsigned long const panelFrequencies[] = {
++ 450000/2, 0<<29, 0x17<<24,
++ 525000/2, 1<<29, 0x17<<24,
++ 750000/2, 0<<29, 0x0f<<24,
++ 875000/2, 1<<29, 0x0f<<24,
++ 900000/2, 0<<29, 0x16<<24,
++ 1050000/2, 1<<29, 0x16<<24,
++ 1500000/2, 0<<29, 0x0e<<24,
++ 1750000/2, 1<<29, 0x0e<<24,
++ 1800000/2, 0<<29, 0x15<<24,
++ 2100000/2, 1<<29, 0x15<<24,
++ 2250000/2, 0<<29, 0x07<<24,
++ 2625000/2, 1<<29, 0x07<<24,
++ 3000000/2, 0<<29, 0x0d<<24,
++ 3500000/2, 1<<29, 0x0d<<24,
++ 3600000/2, 0<<29, 0x14<<24,
++ 4200000/2, 1<<29, 0x14<<24,
++ 4500000/2, 0<<29, 0x06<<24,
++ 5250000/2, 1<<29, 0x06<<24,
++ 6000000/2, 0<<29, 0x0c<<24,
++ 7000000/2, 1<<29, 0x0c<<24,
++ 7200000/2, 0<<29, 0x13<<24,
++ 8400000/2, 1<<29, 0x13<<24,
++ 9000000/2, 0<<29, 0x05<<24,
++ 10500000/2, 1<<29, 0x05<<24,
++ 12000000/2, 0<<29, 0x0b<<24,
++ 14000000/2, 1<<29, 0x0b<<24,
++ 14400000/2, 0<<29, 0x12<<24,
++ 16800000/2, 1<<29, 0x12<<24,
++ 18000000/2, 0<<29, 0x04<<24,
++ 21000000/2, 1<<29, 0x04<<24,
++ 24000000/2, 0<<29, 0x0a<<24,
++ 28000000/2, 1<<29, 0x0a<<24,
++ 28800000/2, 0<<29, 0x11<<24,
++ 33600000/2, 1<<29, 0x11<<24,
++ 36000000/2, 0<<29, 0x03<<24,
++ 42000000/2, 1<<29, 0x03<<24,
++ 48000000/2, 0<<29, 0x09<<24,
++ 56000000/2, 1<<29, 0x09<<24,
++ 57600000/2, 0<<29, 0x10<<24,
++ 67200000/2, 1<<29, 0x10<<24,
++ 72000000/2, 0<<29, 0x02<<24,
++ 84000000/2, 1<<29, 0x02<<24,
++ 96000000/2, 0<<29, 0x08<<24,
++ 112000000/2, 1<<29, 0x08<<24,
++ 144000000/2, 0<<29, 0x01<<24,
++ 168000000/2, 1<<29, 0x01<<24,
++ 288000000/2, 0<<29, 0x00<<24,
++ 336000000/2, 1<<29, 0x00<<24
++};
++#define numPanelFrequencies (sizeof(panelFrequencies)/sizeof(panelFrequencies[0])/ENTRIESPERFREQ)
++
++unsigned long const crtFrequencies[] = {
++ 750000/2, 0<<20, 0x0f<<16,
++ 875000/2, 1<<20, 0x0f<<16,
++ 1500000/2, 0<<20, 0x0e<<16,
++ 1750000/2, 1<<20, 0x0e<<16,
++ 2250000/2, 0<<20, 0x07<<16,
++ 2625000/2, 1<<20, 0x07<<16,
++ 3000000/2, 0<<20, 0x0d<<16,
++ 3500000/2, 1<<20, 0x0d<<16,
++ 4500000/2, 0<<20, 0x06<<16,
++ 5250000/2, 1<<20, 0x06<<16,
++ 6000000/2, 0<<20, 0x0c<<16,
++ 7000000/2, 1<<20, 0x0c<<16,
++ 9000000/2, 0<<20, 0x05<<16,
++ 10500000/2, 1<<20, 0x05<<16,
++ 12000000/2, 0<<20, 0x0b<<16,
++ 14000000/2, 1<<20, 0x0b<<16,
++ 18000000/2, 0<<20, 0x04<<16,
++ 21000000/2, 1<<20, 0x04<<16,
++ 24000000/2, 0<<20, 0x0a<<16,
++ 28000000/2, 1<<20, 0x0a<<16,
++ 36000000/2, 0<<20, 0x03<<16,
++ 42000000/2, 1<<20, 0x03<<16,
++ 48000000/2, 0<<20, 0x09<<16,
++ 56000000/2, 1<<20, 0x09<<16,
++ 72000000/2, 0<<20, 0x02<<16,
++ 84000000/2, 1<<20, 0x02<<16,
++ 96000000/2, 0<<20, 0x08<<16,
++ 112000000/2, 1<<20, 0x08<<16,
++ 144000000/2, 0<<20, 0x01<<16,
++ 168000000/2, 1<<20, 0x01<<16,
++ 288000000/2, 0<<20, 0x00<<16,
++ 336000000/2, 1<<20, 0x00<<16
++};
++#define numCrtFrequencies (sizeof(crtFrequencies)/sizeof(crtFrequencies[0])/ENTRIESPERFREQ)
++
++unsigned long const * const frequencies[] = {
++ panelFrequencies,
++ crtFrequencies
++};
++
++unsigned const numFrequencies[] = {
++ numPanelFrequencies,
++ numCrtFrequencies
++};
++
++static unsigned long const clockMasks[] = {
++ 0x3F<<24,
++ 0x1F<<16
++};
++
++static void updateCRT( unsigned long const *freq,
++ struct lcd_panel_info_t const *panel )
++{
++ unsigned long reg ;
++ unsigned long crtCtrl = 0x00010304 ; // FIFO 3 or more, CRT Timing, CRT data, enable 8-bit
++ if( panel->act_high )
++ crtCtrl |= (3<<14); // horizontal and vertical phase
++ STUFFREG( crtFbAddrReg, 0 );
++ STUFFREG( crtFbOffsReg, ((panel->xres)<<16)+(panel->xres) );
++ STUFFREG( crtFbHTotReg, (( panel->left_margin
++ +panel->xres
++ +panel->right_margin
++ +panel->hsync_len - 1) << 16 )
++ + panel->xres-1 );
++ STUFFREG( crtFbHSynReg, (panel->hsync_len<<16)+ (panel->xres+panel->left_margin-1) );
++ STUFFREG( crtFbVTotReg, (( panel->upper_margin
++ +panel->yres
++ +panel->lower_margin
++ +panel->vsync_len-1 ) << 16 )
++ + panel->yres-1 );
++ STUFFREG( crtFbVSynReg,(panel->vsync_len<<16)
++ + panel->yres+panel->upper_margin-1 );
++ STUFFREG( crtctrlReg, crtCtrl ); // enable
++
++ reg = READREG( miscCtrl ) & ~0x1000 ;
++ STUFFREG( miscCtrl, reg );
++}
++
++void set_lcd_panel( struct lcd_panel_info_t const *panel )
++{
++ unsigned long dispctrl = READREG( dispctrlReg );
++ dispctrl &= ~(CLOCK_ACTIVEMASK|LCDTYPE_MASK);
++ if( !panel->act_high )
++ dispctrl |= CLOCK_ACTIVELOW ;
++ else
++ dispctrl &= ~CLOCK_ACTIVEMASK ;
++
++ if( !panel->active )
++ dispctrl |= LCDTYPE_STN12 ;
++ else
++ dispctrl &= ~LCDTYPE_MASK ;
++
++ if (panel->crt==0) dispctrl |= 4;
++
++ STUFFREG( offsetReg, ((panel->xres)<<16)+(panel->xres) );
++ STUFFREG( fbWidthReg, (panel->xres<<16) );
++ STUFFREG( fbHeightReg, (panel->yres<<16) );
++ STUFFREG( brLocateReg, ((panel->yres-1)<<16)+(panel->xres-1) );
++ STUFFREG( hTotalReg, (( panel->left_margin
++ +panel->xres
++ +panel->right_margin
++ +panel->hsync_len - 1) << 16 )
++ + panel->xres-1 );
++ STUFFREG( hSyncReg, (panel->hsync_len<<16)+ (panel->xres+panel->left_margin-1) );
++ STUFFREG( vTotalReg, (( panel->upper_margin
++ +panel->yres
++ +panel->lower_margin
++ +panel->vsync_len-1 ) << 16 )
++ + panel->yres-1 );
++ STUFFREG( vSyncReg, (panel->vsync_len<<16)
++ + panel->yres+panel->upper_margin-1 );
++
++ if( panel->pixclock < numClockRegs )
++ {
++ unsigned long const *clk = clockRegs+(panel->pixclock*2);
++ setClockReg( curClockReg, *clk );
++ setClockReg( pm0ClockReg, *clk++ );
++ setClockReg( pm1ClockReg, *clk );
++ }
++ else
++ {
++ int const isCRT = (0 != panel->crt);
++ int crt ;
++
++ for( crt = 0 ; crt < 2 ; crt++ )
++ {
++ unsigned long reg ;
++ unsigned long const *freq = frequencies[crt];
++ unsigned const count = numFrequencies[crt];
++
++ unsigned long f, diffl, diffh ;
++ int i ;
++ unsigned long low, high ;
++
++ //
++ // linear scan for closest frequency
++ //
++ for( i = 0 ; i < count ; i++, freq += ENTRIESPERFREQ )
++ {
++ if( *freq > panel->pixclock )
++ break;
++ }
++
++ low = (i > 0)
++ ? freq[0-ENTRIESPERFREQ]
++ : 0 ;
++ diffl = panel->pixclock - low ;
++
++ high = (i < count )
++ ? *freq
++ : 0xFFFFFFFF ;
++ diffh = high - panel->pixclock ;
++
++ if( diffh < diffl )
++ {
++ f = high ;
++ }
++ else
++ {
++ f = low ;
++ freq-- ;
++ }
++
++ printf( "pixclock == %lu, frequency %u/%u -> %lu\n",
++ panel->pixclock, low, high, f );
++
++ reg = READREG( curClockReg ) & ~(clockMasks[crt]);
++
++ // Clock source
++ printf( "source %u, divisor %u\n", freq[1], freq[2] );
++ reg |= freq[1];
++ reg |= freq[2];
++
++ setClockReg( curClockReg, reg );
++ setClockReg( pm0ClockReg, reg );
++ setClockReg( pm1ClockReg, reg );
++
++ if( isCRT )
++ {
++ paletteRegs = crtPaletteRegs ;
++ updateCRT( freq, panel );
++ }
++ else
++ paletteRegs = lcdPaletteRegs ;
++ }
++ }
++ STUFFREG( dispctrlReg, dispctrl );
++ cur_lcd_panel = panel ;
++ SetPanelInfo(panel);
++}
++
++void disable_lcd_panel( void )
++{
++ unsigned long dispctrl = READREG( dispctrlReg );
++ unsigned long crtctrl = READREG( crtctrlReg );
++
++ dispctrl &= ~(DISPCRTL_ENABLE);
++ STUFFREG( dispctrlReg, dispctrl );
++
++ crtctrl &= ~(DISPCRTL_ENABLE);
++ STUFFREG( crtctrlReg, crtctrl );
++}
++
++/* ------------------------------------------------------------------------- */
++
++
++/*
++ * Miscelaneous platform dependent initialisations
++ */
++
++int board_init (void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ /* memory and cpu-speed are setup before relocation */
++ /* so we do _nothing_ here */
++
++ /* arch number of Neon Board */
++ gd->bd->bi_arch_number = MACH_TYPE_BD2003 ;
++
++ /* adress of boot parameters */
++ gd->bd->bi_boot_params = 0xa0000100;
++
++ /* address of frame buffer */
++ gd->fb_base = fbStart ;
++
++ return 0;
++}
++
++int board_late_init(void)
++{
++ setenv("stdout", "serial");
++ setenv("stderr", "serial");
++ return 0;
++}
++
++
++int dram_init (void)
++{
++ DECLARE_GLOBAL_DATA_PTR;
++
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++
++ return 0;
++}
+diff -u -r --new-file u-boot-1.1.2/board/neon/rtc_M41T81S.c u-boot-1.1.2-neon/board/neon/rtc_M41T81S.c
+--- u-boot-1.1.2/board/neon/rtc_M41T81S.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/neon/rtc_M41T81S.c 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,663 @@
++/*
++ * M41T81S:
++ *
++ * This module defines a single 'rtc' command to read/write or
++ * test the ST Micro Real Time Clock attached to the SM-501
++ * I2C pins.
++ *
++ * If called with no parameters, it will display the current time
++ * to the console device and set the 'time' environment variable.
++ *
++ * If called with a single parameter of "test", it will read the
++ * current time, wait a second and read the current time again.
++ * It will return success (zero) if the RTC time appears to tick
++ * by 1 second.
++ *
++ * If called with one or two parameters that appear to fit an
++ * ISO 8601 time format (i.e. YYYY-MM-DD HH:MM:SS.00 ), it will
++ * set the date and time.
++ *
++ * Copyright (c) Boundary Devices, 2006
++ *
++ */
++#include "sm501.h"
++#include <config.h>
++#include <common.h>
++#include <version.h>
++#include <stdarg.h>
++#include <command.h>
++
++int WriteI2C(int bVal);
++int ReadI2C(int ack);
++int I2CStart(int bSlaveAddress);
++void I2CStop(void);
++void I2CInit(void);
++
++//////////////////////////////////////////////////////////
++
++#define SM501_GPIO_DATA 0x10000
++#define SM501_GPIO_DIR 0x10008
++
++#define INPUT 0
++#define OUTPUT 1
++
++#define I2C_CLK 46
++#define I2C_DATA 47
++#define GPBIT_MASK(bitnum) (1<<(bitnum&0x1f))
++#define GPBIT_TEST(bitnum) ( (ReadReg(SM501_GPIO_DATA + ((bitnum>>5)<<2))) & (1<<(bitnum&0x1f)) )
++#define GPBIT_TESTBIT(c,bitnum) ( c & (1<<(bitnum&0x1f)) )
++#define GPBIT_SET(x,bitnum,value) ( (value) ? ((x) | (1<<(bitnum&0x1f))) : ((x) & ~(1<<(bitnum&0x1f))) )
++
++//0.400 Mhz protocol = 1/.4 uSec = 10/4 uSec = 2.5 uSec
++//4 should be safe
++#define I2CWait 4
++#define LongBusWait 8
++#define StartBusWait 12
++
++typedef struct {
++ unsigned short wYear;
++ unsigned short wMonth;
++ unsigned short wDayOfWeek;
++ unsigned short wDay;
++ unsigned short wHour;
++ unsigned short wMinute;
++ unsigned short wSecond;
++ unsigned short wMilliseconds;
++} SYSTEMTIME ;
++
++typedef SYSTEMTIME *LPSYSTEMTIME ;
++
++void I2CInit(void)
++{
++ int i;
++
++ for(i=0; i<9; i++)
++ {
++ I2CStop();
++ }
++}
++
++
++#define ReadReg(reg) READ_SM501_REG(reg)
++#define WriteReg(reg,data) STUFF_SM501_REG((reg), (data))
++
++void SetVal_ClkData(int clk,int data)
++{
++#if (I2C_DATA>>5)==(I2C_CLK>>5)
++ ulong c = ReadReg( SM501_GPIO_DATA + ((I2C_DATA>>5)<<2) );
++ c = GPBIT_SET(c, I2C_DATA, data);
++ c = GPBIT_SET(c, I2C_CLK, clk);
++ WriteReg(SM501_GPIO_DATA + ((I2C_DATA>>5)<<2), c);
++#else
++ ulong c = ReadReg( SM501_GPIO_DATA + ((I2C_DATA>>5)<<2) );
++ c = GPBIT_SET(c, I2C_DATA, data);
++ WriteReg(SM501_GPIO_DATA + ((I2C_DATA>>5)<<2), c);
++
++ c = ReadReg( SM501_GPIO_DATA + ((I2C_CLK>>5)<<2) );
++ c = GPBIT_SET(c, I2C_CLK, clk);
++ WriteReg(SM501_GPIO_DATA + ((I2C_CLK>>5)<<2), c);
++#endif
++}
++
++void SetDir_ClkData(int clk,int data)
++{
++ ulong c,c1;
++#if (I2C_DATA>>5)==(I2C_CLK>>5)
++ c = ReadReg( SM501_GPIO_DIR + ((I2C_CLK>>5)<<2) );
++ if (clk==OUTPUT) {
++ //will be low, and can then change data
++ c1 = GPBIT_SET(c, I2C_CLK, OUTPUT);
++ if (c!=c1) WriteReg( SM501_GPIO_DIR + ((I2C_CLK>>5)<<2), c1);
++ c = GPBIT_SET(c1, I2C_DATA, data);
++ } else {
++ //clk might be low currently, so change data 1st
++ c1 = GPBIT_SET(c, I2C_DATA, data);
++ if (c!=c1) WriteReg( SM501_GPIO_DIR + ((I2C_DATA>>5)<<2), c1);
++ c = GPBIT_SET(c1, I2C_CLK, INPUT);
++ }
++ if (c!=c1) WriteReg( SM501_GPIO_DIR + ((I2C_CLK>>5)<<2), c);
++#else
++ if (clk==OUTPUT) {
++ //will be low, and can then change data
++ c = ReadReg( SM501_GPIO_DIR + ((I2C_CLK>>5)<<2) );
++ c1 = GPBIT_SET(c, I2C_CLK, OUTPUT);
++ if (c!=c1) WriteReg( SM501_GPIO_DIR + ((I2C_CLK>>5)<<2), c1);
++
++ c1 = ReadReg( SM501_GPIO_DIR + ((I2C_DATA>>5)<<2) );
++ c = GPBIT_SET(c1, I2C_DATA, data);
++ if (c!=c1) WriteReg( SM501_GPIO_DIR + ((I2C_DATA>>5)<<2), c);
++ } else {
++ //clk might be low currently, so change data 1st
++ c = ReadReg( SM501_GPIO_DIR + ((I2C_DATA>>5)<<2) );
++ c1 = GPBIT_SET(c, I2C_DATA, data);
++ if (c!=c1) WriteReg( SM501_GPIO_DIR + ((I2C_DATA>>5)<<2), c1);
++
++ c1 = ReadReg( SM501_GPIO_DIR + ((I2C_CLK>>5)<<2) );
++ c = GPBIT_SET(c1, I2C_CLK, INPUT);
++ if (c!=c1) c1WriteReg( SM501_GPIO_DIR + ((I2C_CLK>>5)<<2), c);
++ }
++#endif
++}
++void SetDir_Clk(int clk)
++{
++ ulong c = ReadReg( SM501_GPIO_DIR + ((I2C_CLK>>5)<<2) );
++ c = GPBIT_SET(c, I2C_CLK, clk);
++ WriteReg( SM501_GPIO_DIR + ((I2C_CLK>>5)<<2), c);
++}
++
++void I2CStop()
++{
++ SetDir_Clk(OUTPUT); //low clock
++ udelay(I2CWait);
++ SetDir_ClkData(OUTPUT,OUTPUT); //low clock, low data
++ udelay(I2CWait);
++
++ //Drive Write SCL High
++ SetDir_Clk(INPUT); //high clock
++ udelay(I2CWait);
++
++ // Drive Write SDA High
++ SetDir_ClkData(INPUT,INPUT); //transition on data from low to high while clock is high is a stop control signal
++ udelay(LongBusWait);
++
++}
++
++
++//return 0 for success
++int WriteI2C(int bVal)
++{
++
++ int mask;
++ int i;
++
++ // Enable Write SDA and SCL, and Drv SCL low
++ SetDir_Clk(OUTPUT); //clock low
++ udelay(I2CWait); //hold time
++
++ for (mask=0x80; mask; mask>>=1)
++ {
++ SetDir_ClkData(OUTPUT, (bVal & mask) ? INPUT : OUTPUT); // Write data bits to SDA
++ udelay(LongBusWait);
++
++ SetDir_Clk(INPUT); // Drv CLK High
++ udelay(I2CWait);
++
++ SetDir_Clk(OUTPUT); // Drv CLK Low
++ udelay(I2CWait); //hold time after clock goes low
++ }
++
++
++ SetDir_ClkData(OUTPUT,INPUT); // Disable Write SDA
++ udelay(LongBusWait); //wait for acknowledge to be placed on SDA
++ SetDir_Clk(INPUT); // Drive Clock High
++
++ // Read SDA, until SDA==0
++ for (i=0; i<255; i++) {
++ udelay(LongBusWait);
++ if (!GPBIT_TEST(I2C_DATA)) {
++ SetDir_Clk(OUTPUT); // Drv Clk LOW
++ return 0; //success
++ }
++ }
++
++ printf( "WriteI2C(%i) failed\n", bVal );
++ return -1;
++}
++
++int ReadI2C(int ack)
++{
++ int mask;
++ int byRet = 0;
++
++// SetVal_ClkData(0,0);
++ SetDir_Clk(OUTPUT); //clock low
++ udelay(I2CWait); //hold time
++
++ SetDir_ClkData(OUTPUT,INPUT); //clock low, data input
++ for (mask=0x80; mask; mask>>=1)
++ {
++ // Disable Write SDA, Drive SCL to LOW
++ SetDir_Clk(OUTPUT); //clock low
++ udelay(LongBusWait);
++
++ // Enable Write SCL, Drive SCL to HIGH
++ SetDir_Clk(INPUT); //clock high
++ udelay(I2CWait);
++
++ // Read data bits from SDA
++ if (GPBIT_TEST(I2C_DATA)) byRet |= mask; //sample data bit
++ }
++
++ SetDir_Clk(OUTPUT); //clock low
++ udelay(I2CWait); //let them stop driving data line
++
++ if (ack) {
++ SetDir_ClkData(OUTPUT,OUTPUT); //clock low, data low for ack
++ }
++ udelay(I2CWait);
++ SetDir_Clk(INPUT); //clock high
++ udelay(I2CWait); //wait ack/noack phase
++ return byRet;
++
++}
++
++int I2CStart(int SlaveAddress)
++{
++ int ret;
++ udelay(I2CWait);
++ // Enable Write SDA and Write SCL, and drive them high
++ SetDir_ClkData(INPUT,INPUT);
++ SetVal_ClkData(0,0); //they float high anyway
++ udelay(StartBusWait);
++
++ // Drive Data
++ SetDir_ClkData(INPUT,OUTPUT); //drive data low, (high to low transition on data, while clock high is start signal)
++ udelay(StartBusWait);
++
++ ret = WriteI2C(SlaveAddress);
++ if (ret) {
++ printf( "I2CStart failed write of device address\n" );
++ }
++ return ret;
++}
++
++#define M41T81S_SlaveAddrWrite 0xd0
++#define M41T81S_SlaveAddrRead 0xd1
++
++#define M_HUNDREDTHS 0 //00-99 BCD
++#define M_SECONDS 1 //00-59 BCD, bit 7 ST (oscillator is stopped bit)
++#define M_MINUTES 2 //00-59 BCD
++#define M_HOURS 3 //high 2 bits are CENTURY, low 6 BCD 00-23
++#define M_WEEKDAY 4 //01-07
++#define M_DAY 5 //01-31 BCD
++#define M_MONTH 6 //01-12 BCD
++#define M_YEAR 7 //00-99 BCD
++#define M_CALIBRATION 8
++#define M_WATCHDOG 9
++#define M_ALARM_MOTH 0x0a //01-12 BCD, high 3 bits enable
++#define M_ALARM_DAY 0x0b //01-31 BCD. high 2 bits RPT4, RPT5
++#define M_ALARM_HOUR 0x0c //00-23 BCD, high 2 bits RPT3, HT
++#define M_ALARM_MINUTES 0x0d //00-59 BCD, high bit RPT2
++#define M_ALARM_SECONDS 0x0e //00-59 BCD, high bit RPT1
++#define M_FLAGS 0x0f //bit 7(WDF), 6(AF), 4(BL), 2(OF)
++#define M_SQW 0x13 //bit 7(RS3), 6(RS2), 5(RS1), 4(RS0)
++
++//M_FLAGS bit mask definitions
++#define MF_WDF 0x80 //Watchdog flag
++#define MF_AF 0x40 //Alarm flag
++#define MF_BL 0x10 //Battery low
++#define MF_OF 0x04 //Oscillator fail
++static int bcd(int val,int low, int high)
++{
++ int tens = val>>4;
++ int ones = val & 0xf;
++ if ((tens > 9) || (ones > 9)) return -1;
++ val = (tens*10) + ones;
++ if ((val < low) || (val > high)) return -1;
++ return val;
++}
++static unsigned char toBcd(int val)
++{
++ int tens = val/10;
++ int rem = val - (tens*10);
++ if (tens >= 10) tens = tens % 10;
++ return (tens<<4) | rem;
++}
++
++static int GetTime(LPSYSTEMTIME lpst)
++{
++ unsigned char b[M_YEAR+1];
++ unsigned char * p = b;
++ unsigned char flags;
++ int i;
++ I2CInit(); //send a bunch of stops
++
++ if (I2CStart(M41T81S_SlaveAddrWrite)) return -1;
++ if (WriteI2C(M_ALARM_HOUR)) return -1;
++ if (I2CStart(M41T81S_SlaveAddrRead)) return -1;
++
++ b[0] = (unsigned char)ReadI2C(0); //read Halt bit
++ I2CStop();
++
++ if (b[0] & 0x40) {
++ //halted, restart it
++ if (I2CStart(M41T81S_SlaveAddrWrite)) return -1;
++ if (WriteI2C(M_ALARM_HOUR)) return -1;
++ if (WriteI2C(b[0] & ~0x40)) return -1; //clear Halt bit
++ I2CStop();
++ }
++
++ if (I2CStart(M41T81S_SlaveAddrWrite)) return -1;
++ if (WriteI2C(M_HUNDREDTHS)) return -1;
++ if (I2CStart(M41T81S_SlaveAddrRead)) return -1;
++ for (i=0; i<M_YEAR; i++) *p++ = (unsigned char)ReadI2C(1);
++ *p++ = (unsigned char)ReadI2C(0); //read year
++ I2CStop();
++
++ if (I2CStart(M41T81S_SlaveAddrWrite)) return -1;
++ if (WriteI2C(M_FLAGS)) return -1;
++ if (I2CStart(M41T81S_SlaveAddrRead)) return -1;
++ flags = (unsigned char)ReadI2C(0); //read flags
++ I2CStop();
++
++ if (flags & MF_BL) {
++ printf( "M41T81S_GetTime: Battery low\n" );
++ }
++ if (flags & MF_OF) {
++ printf( "M41T81S_GetTime: Oscillator failed\n" );
++
++ //stop oscillator
++ if (I2CStart(M41T81S_SlaveAddrWrite)) return -1;
++ if (WriteI2C(M_SECONDS)) return -1;
++ if (WriteI2C(b[M_SECONDS] | 0x80)) return -1; //set stop bit
++ I2CStop();
++
++ //start oscillator
++ if (I2CStart(M41T81S_SlaveAddrWrite)) return -1;
++ if (WriteI2C(M_SECONDS)) return -1;
++ if (WriteI2C(b[M_SECONDS] & ~0x80)) return -1; //clear stop bit
++ I2CStop();
++ }
++
++
++ lpst->wYear = ( (b[M_YEAR] > 0x99) || ((b[M_YEAR]&0xf) > 0x9) ) ? 0 :
++ (bcd(b[M_YEAR],0,99) + ( (b[M_HOURS]&0x40) ? 2100 : 2000));
++ lpst->wMonth = bcd(b[M_MONTH],1,12);
++ lpst->wDayOfWeek = bcd(b[M_WEEKDAY],1,7);
++ lpst->wDay = bcd(b[M_DAY],1,31);
++ lpst->wHour = bcd(b[M_HOURS]&0x3f,0,23);
++ lpst->wMinute = bcd(b[M_MINUTES],0,59);
++ lpst->wSecond = bcd(b[M_SECONDS]&0x7f,0,59);
++ lpst->wMilliseconds = bcd(b[M_HUNDREDTHS],0,99)*10;
++
++ if (b[M_SECONDS] & 0x80) {
++ //oscillator is stopped, restart it
++ if (I2CStart(M41T81S_SlaveAddrWrite)) return -1;
++ if (WriteI2C(M_SECONDS)) return -1;
++ if (WriteI2C(b[M_SECONDS] & ~0x80)) return -1; //clear stop bit
++ I2CStop();
++ }
++
++/*
++ printf( "M41T81S_GetTime: Year:%u, Month:%u, Day:%u, Hour:%u, Minute:%u, second:%u, milli:%u\n",
++ lpst->wYear, lpst->wMonth,lpst->wDay, lpst->wHour, lpst->wMinute, lpst->wSecond,lpst->wMilliseconds );
++*/
++ if (flags & MF_OF) {
++ if (I2CStart(M41T81S_SlaveAddrWrite)) return -1;
++ if (WriteI2C(M_FLAGS)) return -1;
++ if (WriteI2C(flags & ~MF_OF)) return -1; //clear oscillator failed bit
++ I2CStop();
++ }
++ return 0;
++}
++
++static int SetTime(LPSYSTEMTIME lpst)
++{
++ unsigned char b[M_YEAR+1];
++ unsigned char flags;
++ int i;
++ if (lpst->wYear < 2004) {
++ lpst->wYear = 2004; //don't allow it to be set in the far past.
++ lpst->wMonth = 1;
++ lpst->wDay = 1;
++ lpst->wDayOfWeek = 4; //Thursday Jan. 1, 2004
++ }
++
++/* printf( "M41T81S_SetTime: Year:%u, Month:%u, Day:%u, Hour:%u, Minute:%u, second:%u, milli:%u\n",
++ lpst->wYear, lpst->wMonth,lpst->wDay, lpst->wHour, lpst->wMinute, lpst->wSecond,lpst->wMilliseconds );
++*/
++ b[M_HUNDREDTHS] = 0; //toBcd(lpst->wMilliseconds/10);
++ b[M_SECONDS] = toBcd(lpst->wSecond);
++ b[M_MINUTES] = toBcd(lpst->wMinute);
++ b[M_HOURS] = toBcd(lpst->wHour) | ( ((lpst->wYear % 200) >= 100) ? 0xc0 : 0x80);
++ b[M_WEEKDAY] = (unsigned char)lpst->wDayOfWeek;
++ b[M_DAY] = toBcd(lpst->wDay);
++ b[M_MONTH] = toBcd(lpst->wMonth);
++ b[M_YEAR] = toBcd( lpst->wYear % 100);
++
++ if (I2CStart(M41T81S_SlaveAddrWrite)) return -1;
++ if (WriteI2C(M_HUNDREDTHS)) return -1;
++
++ for (i=M_HUNDREDTHS; i<=M_YEAR; i++) {
++ if (WriteI2C(b[i])) return -1;
++ }
++ I2CStop();
++
++ if (I2CStart(M41T81S_SlaveAddrWrite)) return -1;
++ if (WriteI2C(M_FLAGS)) return -1;
++ if (I2CStart(M41T81S_SlaveAddrRead)) return -1;
++ flags = (unsigned char)ReadI2C(0); //read flags
++ I2CStop();
++
++/* printf( "M41T81S_SetTime: Year:%u, Month:%u, Day:%u, Weekday:%u, Hour:%u, Minute:%u, second:%u flags:%u\n",
++ lpst->wYear, lpst->wMonth, lpst->wDay, lpst->wDayOfWeek, lpst->wHour, lpst->wMinute, lpst->wSecond, flags );
++*/
++
++ if (flags & MF_OF) {
++ if (I2CStart(M41T81S_SlaveAddrWrite)) return -1;
++ if (WriteI2C(M_FLAGS)) return -1;
++ if (WriteI2C(flags & ~MF_OF)) return -1; //clear oscillator failed bit
++ I2CStop();
++ }
++ return 0;
++}
++
++int M41T81S_GetTime(LPSYSTEMTIME lpst)
++{
++ int ret;
++ int reg = (READ_SM501_REG(SMIR_POWER_MODE_CONTROL) & 1) ? SMIR_PWRM1_GATE : SMIR_PWRM0_GATE;
++ int gate = READ_SM501_REG(reg);
++ if ((gate & 0x40)==0) STUFF_SM501_REG(reg, gate | 0x40);
++ STUFF_SM501_REG(SMIR_GPIO_32_63_CONTROL,
++ READ_SM501_REG(SMIR_GPIO_32_63_CONTROL)
++ & ~(GPBIT_MASK(I2C_CLK)|GPBIT_MASK(I2C_DATA))); // set as gpio controlled
++ udelay(LongBusWait);
++ ret = GetTime(lpst);
++ udelay(I2CWait);
++ SetDir_ClkData(INPUT,INPUT); //high clock, high data, just for safety, should be input already
++ if ((gate & 0x40)==0){
++ STUFF_SM501_REG( reg,
++ READ_SM501_REG( reg )
++ & ~0x40 ); //disable gpio if was originally
++ }
++
++ return ret;
++}
++int M41T81S_SetTime(LPSYSTEMTIME lpst)
++{
++ int ret;
++ int reg = (READ_SM501_REG(SMIR_POWER_MODE_CONTROL) & 1) ? SMIR_PWRM1_GATE : SMIR_PWRM0_GATE;
++ int gate = READ_SM501_REG(reg);
++ if ((gate & 0x40)==0) STUFF_SM501_REG(reg, gate | 0x40);
++ STUFF_SM501_REG(SMIR_GPIO_32_63_CONTROL,
++ READ_SM501_REG(SMIR_GPIO_32_63_CONTROL)
++ & ~(GPBIT_MASK(I2C_CLK)|GPBIT_MASK(I2C_DATA))); // set as gpio controlled
++ udelay(LongBusWait);
++ ret = SetTime(lpst);
++ udelay(I2CWait);
++ SetDir_ClkData(INPUT,INPUT); //high clock, high data, just for safety, should be input already
++ if ((gate & 0x40)==0){
++ STUFF_SM501_REG( reg,
++ READ_SM501_REG( reg )
++ & ~0x40 ); //disable gpio if was originally
++ }
++
++ return ret;
++}
++
++static int badTime( LPSYSTEMTIME lpst )
++{
++ return ( 1 > lpst->wMonth)
++ ||
++ ( 12 < lpst->wMonth)
++ ||
++ ( 1 > lpst->wDay)
++ ||
++ ( 12 < lpst->wDay)
++ ||
++ ( 24 <= lpst->wHour)
++ ||
++ ( 60 <= lpst->wMinute)
++ ||
++ ( 60 <= lpst->wSecond)
++ ||
++ ( 1000 <= lpst->wMilliseconds );
++}
++
++static unsigned diffMs( LPSYSTEMTIME lpst1,
++ LPSYSTEMTIME lpst2 )
++{
++ return ( (long)lpst2->wMilliseconds-(long)lpst1->wMilliseconds )
++ + ( (long)lpst2->wSecond-(long)lpst1->wSecond)*1000
++ + ( (long)lpst2->wMinute-(long)lpst1->wMinute)*60000
++ + ( (long)lpst2->wHour-(long)lpst1->wHour)*3600000 ;
++}
++
++static void printTime( LPSYSTEMTIME t )
++{
++ printf( "%04u-%02u-%02u %02u:%02u:%02u.%02u",
++ t->wYear, t->wMonth, t->wDay,
++ t->wHour, t->wMinute, t->wSecond, t->wMilliseconds/10 );
++}
++
++// returns zero for success
++static int parseTime( LPSYSTEMTIME t,
++ char const *dateString,
++ char const *timeString )
++{
++ int rval = 1 ;
++ char *nextIn ;
++ unsigned long inVal = simple_strtoul( dateString, &nextIn, 10 );
++ if( ( 0 == inVal ) || ( 2999 < inVal ) || ( '-' != *nextIn ) )
++ goto bail ;
++
++ nextIn++ ;
++ t->wYear = inVal ;
++
++ inVal = simple_strtoul( nextIn, &nextIn, 10 );
++ if( ( 0 == inVal ) || ( 12 < inVal ) || ( '-' != *nextIn ) )
++ goto bail ;
++
++ nextIn++ ;
++ t->wMonth = inVal ;
++
++ inVal = simple_strtoul( nextIn, &nextIn, 10 );
++ if( ( 0 == inVal ) || ( 31 < inVal ) || ( '\0' != *nextIn ) )
++ goto bail ;
++
++ nextIn++ ;
++ t->wDay = inVal ;
++
++ t->wHour = 0 ; t->wMinute = 0 ; t->wSecond = 0 ; t->wMilliseconds = 0 ;
++
++ if( 0 != timeString )
++ {
++ inVal = simple_strtoul( timeString, &nextIn, 10 );
++ if( ( 23 < inVal ) || ( ':' != *nextIn ) )
++ goto bail ;
++
++ nextIn++ ;
++ t->wHour = inVal ;
++
++ inVal = simple_strtoul( nextIn, &nextIn, 10 );
++ if( ( 59 < inVal ) || ( ':' != *nextIn ) )
++ goto bail ;
++
++ nextIn++ ;
++ t->wMinute = inVal ;
++
++ inVal = simple_strtoul( nextIn, &nextIn, 10 );
++ if( ( 59 < inVal ) || ( '.' != *nextIn ) )
++ goto bail ;
++
++ nextIn++ ;
++ t->wSecond = inVal ;
++
++ inVal = simple_strtoul( nextIn, &nextIn, 10 );
++ if( ( 99 < inVal ) || ( '\0' != *nextIn ) )
++ goto bail ;
++
++ nextIn++ ;
++ t->wMilliseconds = inVal*10 ;
++ rval = 0 ;
++ }
++ else
++ rval = 0 ;
++
++bail:
++ return rval ;
++}
++
++int do_rtc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
++{
++ int rval = 1 ;
++
++ if( 1 == argc )
++ {
++ SYSTEMTIME t ;
++ int rval = M41T81S_GetTime( &t );
++ if( 0 == rval )
++ {
++ printTime(&t);
++ }
++ }
++ else if( ( 2 == argc ) && ( 0 == strcmp( "test", argv[1] ) ) )
++ {
++ SYSTEMTIME t ;
++ int rval = M41T81S_GetTime( &t );
++ if( 0 == rval ){
++ if( badTime(&t) ){
++ printf( "time not initialized...initializing\n" );
++ t.wYear = 2006 ;
++ t.wMonth = 6 ;
++ t.wDay = 3 ;
++ memset( &t, 0, sizeof(t) );
++ rval = M41T81S_SetTime(&t);
++ }
++ }
++
++ if( 0 == rval )
++ {
++ SYSTEMTIME t2 ;
++ udelay( 1000000 ); // wait a sec
++ rval = M41T81S_GetTime( &t2 );
++ if( 0 == rval )
++ {
++ unsigned diff = diffMs(&t,&t2);
++
++ if( ( diff < 800 ) || ( diff > 1200 ) )
++ {
++ rval = 1 ; // clock not moving or moving too fast (bad oscillator?)
++ if( 0 == diff )
++ printf( "check RTC oscillator\n" );
++#ifdef DEBUG
++ printf( "rtc test failed!\n"
++ "difftime: %u\n", diff );
++ printf( "t1: " ); printTime( &t ); printf( "\n" );
++ printf( "t2: " ); printTime( &t2 ); printf( "\n" );
++#endif
++ }
++ }
++ }
++ }
++ else if( ( 2 == argc ) || ( 3 == argc ) )
++ {
++ SYSTEMTIME t ;
++ if( 0 == parseTime( &t, argv[1], ( 3 == argc ) ? argv[2] : 0 ) )
++ {
++ rval = M41T81S_SetTime(&t);
++ }
++ else
++ printf( "Invalid time format: use YYYY-MM-DD HH:MM:SS\n" );
++ }
++
++ return rval ;
++}
++
++U_BOOT_CMD(
++ rtc, 127, 0, do_rtc,
++ "rtc - get/set/test RTC\n",
++ NULL
++);
++
++
+diff -u -r --new-file u-boot-1.1.2/board/neon/sm501.h u-boot-1.1.2-neon/board/neon/sm501.h
+--- u-boot-1.1.2/board/neon/sm501.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/neon/sm501.h 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,22 @@
++#ifndef __SM501_H__
++#define __SM501_H__
++
++/*
++ * sm501.h
++ *
++ * Defines constants and macros for the SM-501 Graphics Controller.
++ *
++ */
++
++extern unsigned long const mmioStart ;
++extern unsigned long const mmioLength ;
++
++#define SMIR_GPIO_32_63_CONTROL 0x0000c
++#define SMIR_PWRM0_GATE 0x00040
++#define SMIR_PWRM1_GATE 0x00048
++#define SMIR_POWER_MODE_CONTROL 0x00054
++
++#define READ_SM501_REG( addr ) *( (unsigned long volatile *)((addr)+mmioStart) )
++#define STUFF_SM501_REG( addr, value ) *( (unsigned long volatile *)((addr)+mmioStart) ) = (value)
++
++#endif
+diff -u -r --new-file u-boot-1.1.2/board/neon/u-boot.lds u-boot-1.1.2-neon/board/neon/u-boot.lds
+--- u-boot-1.1.2/board/neon/u-boot.lds 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/neon/u-boot.lds 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,56 @@
++/*
++ * (C) Copyright 2000
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++ . = 0x00000000;
++
++ . = ALIGN(4);
++ .text :
++ {
++ cpu/pxa/start.o (.text)
++ cpu/pxa/ministart.o (.text)
++ *(.text)
++ }
++
++ . = ALIGN(4);
++ .rodata : { *(.rodata) }
++
++ . = ALIGN(4);
++ .data : { *(.data) }
++
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
+diff -u -r --new-file u-boot-1.1.2/board/neon/u-bootmini.lds u-boot-1.1.2-neon/board/neon/u-bootmini.lds
+--- u-boot-1.1.2/board/neon/u-bootmini.lds 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/board/neon/u-bootmini.lds 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,56 @@
++/*
++ * (C) Copyright 2000
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++OUTPUT_ARCH(arm)
++ENTRY(StartUp)
++SECTIONS
++{
++ . = 0x00000000;
++
++ . = ALIGN(4);
++ .text :
++ {
++ cpu/pxa/minidebug.o (.text)
++ cpu/pxa/ministart.o (.text)
++ *(.text)
++ }
++
++ . = ALIGN(4);
++ .rodata : { *(.rodata) }
++
++ . = ALIGN(4);
++ .data : { *(.data) }
++
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
+diff -u -r --new-file u-boot-1.1.2/common/cmd_boot.c u-boot-1.1.2-neon/common/cmd_boot.c
+--- u-boot-1.1.2/common/cmd_boot.c 2003-10-09 01:26:14.000000000 +0200
++++ u-boot-1.1.2-neon/common/cmd_boot.c 2007-08-11 21:07:20.000000000 +0200
+@@ -59,6 +59,7 @@
+ */
+ argv[0] = (char *)gd;
+ #endif
++ *((ulong*)0x40e00014) |= (1<<25); //make gpio89 an output(ac97_reset)
+ #if !defined(CONFIG_NIOS)
+ rc = ((ulong (*)(int, char *[]))addr) (--argc, &argv[1]);
+ #else
+diff -u -r --new-file u-boot-1.1.2/common/cmd_bootm.c u-boot-1.1.2-neon/common/cmd_bootm.c
+--- u-boot-1.1.2/common/cmd_bootm.c 2004-11-21 01:06:34.000000000 +0100
++++ u-boot-1.1.2-neon/common/cmd_bootm.c 2007-08-11 21:07:20.000000000 +0200
+@@ -29,8 +29,6 @@
+ #include <command.h>
+ #include <image.h>
+ #include <malloc.h>
+-#include <zlib.h>
+-#include <bzlib.h>
+ #include <environment.h>
+ #include <asm/byteorder.h>
+
+@@ -73,10 +71,12 @@
+ # define CHUNKSZ (64 * 1024)
+ #endif
+
++#ifdef CONFIG_GZIP
++#include <zlib.h>
+ int gunzip (void *, int, unsigned char *, unsigned long *);
+-
+ static void *zalloc(void *, unsigned, unsigned);
+ static void zfree(void *, void *, unsigned);
++#endif
+
+ #if (CONFIG_COMMANDS & CFG_CMD_IMI)
+ static int image_info (unsigned long addr);
+@@ -327,12 +327,17 @@
+ break;
+ case IH_COMP_GZIP:
+ printf (" Uncompressing %s ... ", name);
++#ifdef CONFIG_GZIP
+ if (gunzip ((void *)ntohl(hdr->ih_load), unc_len,
+ (uchar *)data, &len) != 0) {
+ puts ("GUNZIP ERROR - must RESET board to recover\n");
+ SHOW_BOOT_PROGRESS (-6);
+ do_reset (cmdtp, flag, argc, argv);
+ }
++#else
++ printf( "GUNZIP not supported\n" );
++#endif
++
+ break;
+ #ifdef CONFIG_BZIP2
+ case IH_COMP_BZIP2:
+@@ -1221,6 +1226,8 @@
+ printf ("%s %s %s (%s)", arch, os, type, comp);
+ }
+
++#ifdef CONFIG_GZIP
++
+ #define ZALLOC_ALIGNMENT 16
+
+ static void *zalloc(void *x, unsigned items, unsigned size)
+@@ -1302,6 +1309,8 @@
+
+ return (0);
+ }
++#endif // CONFIG_GZIP
++
+
+ #ifdef CONFIG_BZIP2
+ void bz_internal_error(int errcode)
+diff -u -r --new-file u-boot-1.1.2/common/cmd_fat.c u-boot-1.1.2-neon/common/cmd_fat.c
+--- u-boot-1.1.2/common/cmd_fat.c 2004-08-28 23:09:15.000000000 +0200
++++ u-boot-1.1.2-neon/common/cmd_fat.c 2007-08-11 21:07:20.000000000 +0200
+@@ -30,6 +30,13 @@
+ #include <net.h>
+ #include <ata.h>
+
++#define CONFIG_FATLOAD_TICKS
++#define CONFIG_FATLOAD_ADLER
++
++#ifdef CONFIG_FATLOAD_ADLER
++#include <zlib.h>
++#endif
++
+ #if (CONFIG_COMMANDS & CFG_CMD_FAT)
+
+ #undef DEBUG
+@@ -83,6 +90,11 @@
+ int dev=0;
+ int part=1;
+ char *ep;
++#ifdef CONFIG_FATLOAD_TICKS
++ ulong ticks1 ;
++ ulong ticks2 ;
++ ulong ticks3 ;
++#endif
+
+ if (argc < 5) {
+ printf ("usage: fatload <interface> <dev[:part]> <addr> <filename> [bytes]\n");
+@@ -110,6 +122,10 @@
+ count = simple_strtoul (argv[5], NULL, 16);
+ else
+ count = 0;
++#ifdef CONFIG_FATLOAD_TICKS
++ ticks1 = get_timer( 0 );
++#endif
++
+ size = file_fat_read (argv[4], (unsigned char *) offset, count);
+
+ if(size==-1) {
+@@ -117,7 +133,21 @@
+ return 1;
+ }
+
+- printf ("\n%ld bytes read\n", size);
++ printf ("\n%ld bytes read", size);
++
++#ifdef CONFIG_FATLOAD_TICKS
++ ticks2 = get_timer( 0 );
++ printf( " in %lu ticks, (%lu ms)", (ticks2-ticks1), (ticks2-ticks1)/(CFG_HZ/1000) );
++#endif
++
++#ifdef CONFIG_FATLOAD_ADLER
++ printf( ", adler == 0x" );
++ printf( "%08lx", adler32(0, (Bytef *)offset, size ) );
++ ticks3 = get_timer( 0 );
++ printf( " in %lu ticks, (%lu ms)", (ticks3-ticks2), (ticks3-ticks2)/(CFG_HZ/1000) );
++#endif
++
++ printf( "\n" );
+
+ sprintf(buf, "%lX", size);
+ setenv("filesize", buf);
+diff -u -r --new-file u-boot-1.1.2/common/cmd_flash.c u-boot-1.1.2-neon/common/cmd_flash.c
+--- u-boot-1.1.2/common/cmd_flash.c 2004-12-31 10:32:50.000000000 +0100
++++ u-boot-1.1.2-neon/common/cmd_flash.c 2007-08-11 21:07:20.000000000 +0200
+@@ -507,7 +507,7 @@
+ );
+
+ U_BOOT_CMD(
+- erase, 3, 1, do_flerase,
++ erase, 3, 0, do_flerase,
+ "erase - erase FLASH memory\n",
+ "start end\n"
+ " - erase FLASH from addr 'start' to addr 'end'\n"
+diff -u -r --new-file u-boot-1.1.2/common/cmd_lcdpanel.c u-boot-1.1.2-neon/common/cmd_lcdpanel.c
+--- u-boot-1.1.2/common/cmd_lcdpanel.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/common/cmd_lcdpanel.c 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,265 @@
++/*
++ * Module cmd_lcdpanel.cpp
++ *
++ * This module defines ...
++ *
++ *
++ * Change History :
++ *
++ * $Log: cmd_lcdpanel.c,v $
++ * Revision 1.8 2005/09/19 13:15:59 ericn
++ * -allow zeros in most fields
++ *
++ * Revision 1.7 2005/08/22 16:30:32 ericn
++ * -update panel env var w/lcdp command
++ *
++ * Revision 1.6 2005/07/18 03:05:53 ericn
++ * -allow cmdline config of CRT
++ *
++ * Revision 1.5 2005/07/06 05:26:54 ericn
++ * -make lcdinfo command conditional on PXALCD
++ *
++ * Revision 1.4 2005/07/04 18:49:01 ericn
++ * -added lcdi command
++ *
++ * Revision 1.3 2005/06/02 04:01:30 ericn
++ * -allow zero value of pixclock (meaning slow one)
++ *
++ * Revision 1.2 2005/04/30 20:32:44 ericn
++ * -added disable cmd
++ *
++ * Revision 1.1 2005/04/09 17:49:15 ericn
++ * -Initial import
++ *
++ *
++ * Copyright Boundary Devices, Inc. 2005
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++
++#include <common.h>
++#include <command.h>
++#if (CONFIG_COMMANDS & CFG_CMD_LCDPANEL)
++
++#include <malloc.h>
++#include <lcd_panels.h>
++
++extern char console_buffer[]; /* console I/O buffer */
++
++static void print_panel_info( struct lcd_panel_info_t const *panel )
++{
++ printf( "------------------------------------\n"
++ "name : %s\n", panel->name );
++ printf( "pixclock : %u\n", panel->pixclock );
++ printf( "xres : %u\n", panel->xres );
++ printf( "yres : %u\n", panel->yres );
++ printf( "act_high : %u\n", panel->act_high );
++ printf( "hsync_len : %u\n", panel->hsync_len );
++ printf( "left_margin : %u\n", panel->left_margin );
++ printf( "right_margin : %u\n", panel->right_margin );
++ printf( "vsync_len : %u\n", panel->vsync_len );
++ printf( "upper_margin : %u\n", panel->upper_margin );
++ printf( "lower_margin : %u\n", panel->lower_margin );
++ printf( "active : %u\n", panel->active );
++ printf( "CRT ? %u\n", panel->crt );
++}
++
++static struct lcd_panel_info_t const *prompt_for_panel( void )
++{
++ struct lcd_panel_info_t *panel = (struct lcd_panel_info_t *)malloc(sizeof(struct lcd_panel_info_t));
++ int bytesRead ;
++
++ memset( panel, 0, sizeof(*panel));
++
++ bytesRead = readline( "name: " );
++ if( 0 < bytesRead )
++ {
++ panel->name = strdup( console_buffer );
++ bytesRead = readline( "pixclock: " );
++ if( 0 < bytesRead )
++ {
++ char *endp;
++ ulong value = simple_strtoul( console_buffer, &endp, 0 );
++ if( endp > console_buffer )
++ {
++ panel->pixclock = value ;
++ bytesRead = readline( "xres: " );
++ if( ( 0 < bytesRead )
++ && ( 0 != ( value = simple_strtoul( console_buffer, &endp, 0 ) ) )
++ && ( endp > console_buffer ) )
++ {
++ panel->xres = value ;
++ bytesRead = readline( "yres: " );
++ if( ( 0 < bytesRead )
++ && ( 0 != ( value = simple_strtoul( console_buffer, &endp, 0 ) ) )
++ && ( endp > console_buffer ) )
++ {
++ panel->yres = value ;
++ bytesRead = readline( "act_high: " );
++ if( ( 0 < bytesRead )
++ && ( 1 >= ( value = simple_strtoul( console_buffer, &endp, 0 ) ) )
++ && ( endp > console_buffer ) )
++ {
++ panel->act_high = value ;
++ bytesRead = readline( "hsync_len: " );
++ if( ( 0 < bytesRead )
++ && ( 0 != ( value = simple_strtoul( console_buffer, &endp, 0 ) ) )
++ && ( endp > console_buffer ) )
++ {
++ panel->hsync_len = value ;
++ bytesRead = readline( "left_margin: " );
++ value = simple_strtoul( console_buffer, &endp, 0 );
++ if( ( 0 < bytesRead )
++ && ( endp > console_buffer ) )
++ {
++ panel->left_margin = value ;
++ bytesRead = readline( "right_margin: " );
++ value = simple_strtoul( console_buffer, &endp, 0 );
++ if( ( 0 < bytesRead )
++ && ( endp > console_buffer ) )
++ {
++ panel->right_margin = value ;
++ bytesRead = readline( "vsync_len: " );
++ value = simple_strtoul( console_buffer, &endp, 0 );
++ if( ( 0 < bytesRead )
++ && ( endp > console_buffer ) )
++ {
++ panel->vsync_len = value ;
++ bytesRead = readline( "upper_margin: " );
++ value = simple_strtoul( console_buffer, &endp, 0 );
++ if( ( 0 < bytesRead )
++ && ( endp > console_buffer ) )
++ {
++ panel->upper_margin = value ;
++ bytesRead = readline( "lower_margin: " );
++ value = simple_strtoul( console_buffer, &endp, 0 );
++ if( ( 0 < bytesRead )
++ && ( endp > console_buffer ) )
++ {
++ panel->lower_margin = value ;
++ bytesRead = readline( "active (0|1) : " );
++ value = simple_strtoul( console_buffer, &endp, 0 );
++ if( ( 0 < bytesRead ) && ( endp > console_buffer ) )
++ {
++ panel->active = value ;
++ bytesRead = readline( "crt (0|1) : " );
++ value = simple_strtoul( console_buffer, &endp, 0 );
++ if( ( 0 < bytesRead )
++ &&
++ ( endp > console_buffer ) )
++ {
++ panel->crt = value ;
++ print_panel_info( panel );
++ return panel ;
++ }
++ }
++ }
++ }
++ }
++ }
++ }
++ }
++ }
++ }
++ }
++ }
++ }
++ }
++
++ free( panel );
++
++ return 0 ;
++}
++
++static int lcdpanel(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
++{
++ if ( 1 == argc ) {
++ if( cur_lcd_panel )
++ print_panel_info( cur_lcd_panel );
++ else
++ printf( "no panel defined\n" );
++ }
++ else {
++ struct lcd_panel_info_t const *panel = find_lcd_panel( argv[1] );
++ if( panel ) {
++ printf( "found panel %s\n", panel->name );
++ set_lcd_panel( panel );
++ setenv( "panel", panel->name );
++ }
++ else if( '+' == *argv[1] ) {
++ panel = prompt_for_panel();
++ if( panel )
++ {
++ print_panel_info( panel );
++ set_lcd_panel( panel );
++ }
++ }
++ else if( '?' == *argv[1] )
++ {
++ int i ;
++ for( i = 0 ; i < num_lcd_panels ; i++ )
++ print_panel_info( lcd_panels+i );
++ }
++ else if( '-' == *argv[1] )
++ {
++ disable_lcd_panel();
++ printf( "panel disabled\n" );
++ }
++ else
++ printf( "panel %s not found\n", argv[1] );
++ }
++
++ return 0;
++}
++
++
++U_BOOT_CMD(
++ lcdpanel, 2, 0, lcdpanel,
++ "lcdpanel [panelName|?|+|-]\n"
++ " init lcd panel with panel name\n"
++ " ? will display the supported panels\n"
++ " + will prompt for panel details\n"
++ " - will disable the panel\n",
++ NULL
++);
++
++#ifdef PXALCD
++#include <lcd.h>
++
++static int lcdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
++{
++ printf( "--> lcdinfo:\n"
++ "screen: %08lx\n"
++ "palette: %08lx/%u\n",
++ panel_info.pxa.screen,
++ panel_info.pxa.palette,
++ panel_info.pxa.palette_size );
++ return 0 ;
++}
++
++U_BOOT_CMD(
++ lcdinfo, 2, 0, lcdinfo,
++ "lcdinfo\n",
++ NULL
++);
++#endif
++
++#endif /* CFG_CMD_LCDPANEL */
++
++
++
++
+diff -u -r --new-file u-boot-1.1.2/common/cmd_lcdpanel.h u-boot-1.1.2-neon/common/cmd_lcdpanel.h
+--- u-boot-1.1.2/common/cmd_lcdpanel.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/common/cmd_lcdpanel.h 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,24 @@
++#ifndef __CMD_LCDPANEL_H__
++#define __CMD_LCDPANEL_H__ "$Id: cmd_lcdpanel.h,v 1.1 2005/04/09 17:49:16 ericn Exp $"
++
++/*
++ * cmd_lcdpanel.h
++ *
++ * This header file declares ...
++ *
++ *
++ * Change History :
++ *
++ * $Log: cmd_lcdpanel.h,v $
++ * Revision 1.1 2005/04/09 17:49:16 ericn
++ * -Initial import
++ *
++ *
++ *
++ * Copyright Boundary Devices, Inc. 2005
++ */
++
++
++
++#endif
++
+diff -u -r --new-file u-boot-1.1.2/common/cmd_mmc.c u-boot-1.1.2-neon/common/cmd_mmc.c
+--- u-boot-1.1.2/common/cmd_mmc.c 2003-07-01 23:07:07.000000000 +0200
++++ u-boot-1.1.2-neon/common/cmd_mmc.c 2007-08-11 21:07:20.000000000 +0200
+@@ -43,4 +43,71 @@
+ NULL
+ );
+
++int do_mmc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
++{
++ if( 5 == argc )
++ {
++ unsigned long args[4];
++ unsigned i ;
++ for( i = 1 ; i < 5 ; i++ )
++ {
++ char *endp ;
++ args[i-1] = simple_strtoul(argv[i], &endp, 16 );
++ if( 0 != *endp )
++ {
++ printf( "arg[%u] is not a valid hex number\n", i );
++ break;
++ }
++ }
++
++ if( 5 == i )
++ {
++ uchar *resp = mmc_cmd( (ushort)args[0],
++ (ushort)args[1],
++ (ushort)args[2],
++ (ushort)args[3] );
++ ushort numWords = 0 ;
++ switch( args[3] )
++ {
++ case MMC_CMDAT_R1:
++ case MMC_CMDAT_R3:
++ numWords = 3;
++ break;
++
++ case MMC_CMDAT_R2:
++ numWords = 8;
++ break;
++
++ default:
++ printf( "Invalid response type %lu, options are [1,2,3]\n", args[3] );
++ break;
++ }
++
++ if( resp )
++ {
++ for( i = 0 ; i < numWords*2 ; i++ )
++ {
++ printf( "%02X ", resp[i] );
++ }
++ printf( "\n" );
++ }
++ else
++ printf( "no response\n" );
++ }
++ }
++ else
++ printf ("Usage:\n%s\n", cmdtp->usage);
++
++ return 0;
++}
++
++extern uchar *
++mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat);
++
++U_BOOT_CMD(
++ mmccmd, 5, 0, do_mmc_cmd,
++ "mmccmd - issue mmc command\n",
++ "mmccmd cmd# argh(hex) argl(hex) rsptype\n"
++);
++
+ #endif /* CFG_CMD_MMC */
+diff -u -r --new-file u-boot-1.1.2/common/cmd_net.c u-boot-1.1.2-neon/common/cmd_net.c
+--- u-boot-1.1.2/common/cmd_net.c 2004-06-09 14:42:26.000000000 +0200
++++ u-boot-1.1.2-neon/common/cmd_net.c 2007-08-11 21:07:20.000000000 +0200
+@@ -46,6 +46,104 @@
+ "[loadAddress] [bootfilename]\n"
+ );
+
++extern int get_rom_mac (char *v_rom_mac);
++extern int set_rom_mac (char const *v_rom_mac);
++
++/*
++ * returns -1 if not valid hex
++ */
++static int hexValue( char c )
++{
++ if( ( '0' <= c ) && ( '9' >= c ) )
++ {
++ return c-'0' ;
++ }
++ else if( ( 'A' <= c ) && ( 'F' >= c ) )
++ {
++ return c-'A'+10 ;
++ }
++ else if( ( 'a' <= c ) && ( 'f' >= c ) )
++ {
++ return c-'a'+10 ;
++ }
++ else
++ return -1 ;
++}
++
++// returns non-zero to indicate success
++static int parse_mac( char const *macString, // input
++ char *macaddr ) // output: not NULL-terminated
++{
++ int i ;
++ for( i = 0 ; i < 6 ; i++ )
++ {
++ char high, low, term ;
++ int highval, lowval ;
++ high = *macString++ ;
++
++ if( ( 0 == high )
++ ||
++ ( 0 > ( highval = hexValue(high) ) ) )
++ break ;
++ low = *macString++ ;
++ if( ( 0 == low )
++ ||
++ ( 0 > ( lowval = hexValue(low) ) ) )
++ break ;
++
++ term = *macString++ ;
++ if( 5 > i )
++ {
++ if( ( '-' != term ) && ( ':' != term ) )
++ break ;
++ }
++ else if( '\0' != term )
++ break ;
++
++ *macaddr++ = (highval<<4) | lowval ;
++ }
++
++ return ( 6 == i );
++}
++
++int do_mac (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
++{
++ if( 2 == argc )
++ {
++ char mac[6];
++ if( parse_mac( argv[1], mac ) )
++ {
++ printf( "setting mac address to %02x:%02x:%02x:%02x:%02x:%02x\n",
++ mac[0],mac[1],mac[2],mac[3],mac[4],mac[5] );
++ if( set_rom_mac( mac ) )
++ printf( "done\n" );
++ else
++ printf( "Error setting mac address\n" );
++ }
++ else
++ printf( "Error parsing mac: use form NN:NN:NN:NN:NN:NN\n" );
++ }
++ else
++ {
++ char mac[6];
++ if( get_rom_mac( mac ) )
++ printf( "mac address %02x:%02x:%02x:%02x:%02x:%02x\n",
++ mac[0],mac[1],mac[2],mac[3],mac[4],mac[5] );
++ else if( 0xFF == mac[0] )
++ printf( "MAC has not been programmed\n" );
++ else
++ printf( "error reading mac\n" );
++ }
++ return 0 ;
++}
++
++U_BOOT_CMD(
++ mac, 3, 1, do_mac,
++ "mac\t- read/write mac address\n",
++ "- supply a parameter of the form NN:NN:NN:NN:NN:NN to set"
++);
++
++
+ int do_tftpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+ {
+ return netboot_common (TFTP, cmdtp, argc, argv);
+diff -u -r --new-file u-boot-1.1.2/common/cmd_not.c u-boot-1.1.2-neon/common/cmd_not.c
+--- u-boot-1.1.2/common/cmd_not.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/common/cmd_not.c 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,55 @@
++/*
++ * (C) Copyright 2006
++ * Eric Nelson, Boundary Devices
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <config.h>
++#include <command.h>
++
++#if (CONFIG_COMMANDS & CFG_CMD_NOT)
++
++int do_not (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
++{
++ int rval = 1 ;
++ if( 1 < argc )
++ {
++ cmd_tbl_t *cmd = find_cmd(argv[1]);
++ if( cmd )
++ {
++ rval = ( 0 == cmd->cmd(cmd, flag, argc-1, argv+1) );
++ }
++ else
++ printf( "command %s not found\n", argv[1] );
++ }
++ else
++ printf( "Usage not command [..params]\n" );
++
++ return rval ;
++}
++
++U_BOOT_CMD(
++ not, 127, 0, do_not,
++ "not - negate a command\n",
++ NULL
++);
++
++#endif /* CONFIG_COMMANDS & CFG_CMD_NOT */
+diff -u -r --new-file u-boot-1.1.2/common/cmd_nvedit.c u-boot-1.1.2-neon/common/cmd_nvedit.c
+--- u-boot-1.1.2/common/cmd_nvedit.c 2004-09-30 00:55:14.000000000 +0200
++++ u-boot-1.1.2-neon/common/cmd_nvedit.c 2007-08-11 21:07:20.000000000 +0200
+@@ -487,16 +487,21 @@
+ {
+ int i, nxt;
+
++// printf ("before WATCHDOG_RESET\n");
+ WATCHDOG_RESET();
++// printf ("after WATCHDOG_RESET\n");
+
+ for (i=0; env_get_char(i) != '\0'; i=nxt+1) {
+ int val;
+
++// printf ("i= %i\n", i);
+ for (nxt=i; env_get_char(nxt) != '\0'; ++nxt) {
+ if (nxt >= CFG_ENV_SIZE) {
+ return (NULL);
+ }
++// putc(env_get_char(nxt));
+ }
++// printf ("\n");
+ if ((val=envmatch(name, i)) < 0)
+ continue;
+ return (env_get_addr(val));
+diff -u -r --new-file u-boot-1.1.2/common/command.c u-boot-1.1.2-neon/common/command.c
+--- u-boot-1.1.2/common/command.c 2004-04-18 19:39:39.000000000 +0200
++++ u-boot-1.1.2-neon/common/command.c 2007-08-11 21:07:20.000000000 +0200
+@@ -27,6 +27,9 @@
+
+ #include <common.h>
+ #include <command.h>
++#ifdef CONFIG_LCD
++#include "lcd.h"
++#endif
+
+ int
+ do_version (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+@@ -74,6 +77,41 @@
+ " - echo args to console; \\c suppresses newline\n"
+ );
+
++#ifdef CONFIG_LCD
++
++int
++do_lecho (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
++{
++ int i, putnl = 1;
++
++ for (i = 1; i < argc; i++) {
++ char *p = argv[i], c;
++
++ if (i > 1)
++ putc(' ');
++ while ((c = *p++) != '\0') {
++ if (c == '\\' && *p == 'c') {
++ putnl = 0;
++ p++;
++ } else {
++ lcd_putc(c);
++ }
++ }
++ }
++
++ if (putnl)
++ lcd_putc('\n');
++ return 0;
++}
++
++U_BOOT_CMD(
++ lecho, CFG_MAXARGS, 1, do_lecho,
++ "lecho - echo args to lcd\n",
++ "[args..]\n"
++ " - echo args to lcd; \\c suppresses newline\n"
++);
++#endif
++
+ #ifdef CFG_HUSH_PARSER
+
+ int
+diff -u -r --new-file u-boot-1.1.2/common/env_flash.c u-boot-1.1.2-neon/common/env_flash.c
+--- u-boot-1.1.2/common/env_flash.c 2004-03-14 02:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/common/env_flash.c 2007-08-11 21:07:20.000000000 +0200
+@@ -83,6 +83,10 @@
+ #define OBSOLETE_FLAG 0
+ #endif /* CFG_ENV_ADDR_REDUND */
+
++#ifdef CFG_ENV_IS_IN_FLASH
++static env_t *flash_addr_new = (env_t *)CFG_ENV_ADDR ;
++#endif
++
+ extern uchar default_environment[];
+ extern int default_environment_size;
+
+diff -u -r --new-file u-boot-1.1.2/common/fnmatch.c u-boot-1.1.2-neon/common/fnmatch.c
+--- u-boot-1.1.2/common/fnmatch.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/common/fnmatch.c 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,166 @@
++/*
++ * (C) Copyright 2005
++ * Boundary Devices
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++
++#include <common.h>
++#include <config.h>
++#include <part.h>
++
++/* Some file systems are case-insensitive. If FOLD_FN_CHAR is
++ #defined, it maps the character C onto its "canonical" form. In a
++ case-insensitive system, it would map all alphanumeric characters
++ to lower case. Under Windows NT, / and \ are both path component
++ separators, so FOLD_FN_CHAR would map them both to /. */
++#define FOLD_FN_CHAR(c) (c)
++
++
++int fnmatch(const char *pattern, const char *string, int flags)
++{
++ register const char *p = pattern, *n = string;
++ register char c;
++
++ while ((c = *p++) != '\0')
++ {
++ switch (c)
++ {
++ case '?':
++ if (*n == '\0')
++ return FNM_NOMATCH;
++ else if ((flags & FNM_PATHNAME) && *n == '/')
++ return FNM_NOMATCH;
++ else if ((flags & FNM_PERIOD) && *n == '.' &&
++ (n == string || ((flags & FNM_PATHNAME) && n[-1] == '/')))
++ return FNM_NOMATCH;
++ break;
++
++ case '\\':
++ if (!(flags & FNM_NOESCAPE))
++ c = *p++;
++ if (FOLD_FN_CHAR (*n) != FOLD_FN_CHAR (c))
++ return FNM_NOMATCH;
++ break;
++
++ case '*':
++ if ((flags & FNM_PERIOD) && *n == '.' &&
++ (n == string || ((flags & FNM_PATHNAME) && n[-1] == '/')))
++ return FNM_NOMATCH;
++
++ for (c = *p++; c == '?' || c == '*'; c = *p++, ++n)
++ if (((flags & FNM_PATHNAME) && *n == '/') ||
++ (c == '?' && *n == '\0'))
++ return FNM_NOMATCH;
++
++ if (c == '\0')
++ return 0;
++
++ {
++ char c1 = (!(flags & FNM_NOESCAPE) && c == '\\') ? *p : c;
++ for (--p; *n != '\0'; ++n)
++ if ((c == '[' || FOLD_FN_CHAR (*n) == FOLD_FN_CHAR (c1)) &&
++ fnmatch(p, n, flags & ~FNM_PERIOD) == 0)
++ return 0;
++ return FNM_NOMATCH;
++ }
++
++ case '[':
++ {
++ /* Nonzero if the sense of the character class is inverted. */
++ register int not;
++
++ if (*n == '\0')
++ return FNM_NOMATCH;
++
++ if ((flags & FNM_PERIOD) && *n == '.' &&
++ (n == string || ((flags & FNM_PATHNAME) && n[-1] == '/')))
++ return FNM_NOMATCH;
++
++ not = (*p == '!' || *p == '^');
++ if (not)
++ ++p;
++
++ c = *p++;
++ for (;;)
++ {
++ register char cstart = c, cend = c;
++
++ if (!(flags & FNM_NOESCAPE) && c == '\\')
++ cstart = cend = *p++;
++
++ if (c == '\0')
++ /* [ (unterminated) loses. */
++ return FNM_NOMATCH;
++
++ c = *p++;
++
++ if ((flags & FNM_PATHNAME) && c == '/')
++ /* [/] can never match. */
++ return FNM_NOMATCH;
++
++ if (c == '-' && *p != ']')
++ {
++ cend = *p++;
++ if (!(flags & FNM_NOESCAPE) && cend == '\\')
++ cend = *p++;
++ if (cend == '\0')
++ return FNM_NOMATCH;
++ c = *p++;
++ }
++
++ if (*n >= cstart && *n <= cend)
++ goto matched;
++
++ if (c == ']')
++ break;
++ }
++ if (!not)
++ return FNM_NOMATCH;
++ break;
++
++ matched:;
++ /* Skip the rest of the [...] that already matched. */
++ while (c != ']')
++ {
++ if (c == '\0')
++ /* [... (unterminated) loses. */
++ return FNM_NOMATCH;
++
++ c = *p++;
++ if (!(flags & FNM_NOESCAPE) && c == '\\')
++ /* 1003.2d11 is unclear if this is right. %%% */
++ ++p;
++ }
++ if (not)
++ return FNM_NOMATCH;
++ }
++ break;
++
++ default:
++ if (FOLD_FN_CHAR (c) != FOLD_FN_CHAR (*n))
++ return FNM_NOMATCH;
++ }
++
++ ++n;
++ }
++
++ if (*n == '\0')
++ return 0;
++
++ return FNM_NOMATCH;
++}
++
+diff -u -r --new-file u-boot-1.1.2/common/lcd.c u-boot-1.1.2-neon/common/lcd.c
+--- u-boot-1.1.2/common/lcd.c 2004-12-10 12:40:50.000000000 +0100
++++ u-boot-1.1.2-neon/common/lcd.c 2007-08-11 21:07:20.000000000 +0200
+@@ -41,7 +41,7 @@
+ #endif
+ #include <lcd.h>
+
+-#if defined(CONFIG_PXA250)
++#if defined(CONFIG_PXA250) || defined(CONFIG_PXA270)
+ #include <asm/byteorder.h>
+ #endif
+
+@@ -94,8 +94,46 @@
+ static int lcd_getfgcolor (void);
+ #endif /* NOT_USED_SO_FAR */
+
+-/************************************************************************/
++static int luminance( int red, int green, int blue )
++{
++ //
++ // I've seen a couple of different algorithms here:
++ // (max+min)/2
++/*
++
++ int max = MAX( red, MAX( green, blue ) );
++ int min = MIN( red, MIN( green, blue ) );
++ return (max+min)/2 ;
++*/
++
++ // A more mathematically-correct version
++// return (int)(c.R*0.3 + c.G*0.59+ c.B*0.11);
++
++ // Just return 'green'
++ // return green;
++
++ // and one that uses shifts and adds to come close to the above
++ //
++ // red = 5/16= 0.3125 == 1/4 + 1/16
++ // green = 9/16= 0.5625 == 1/2 + 1/16
++ // blue = 1/8 = 0.125
++ //
++ if( 0 < red )
++ red = (red>>2) + (red>>4);
++ else
++ red = 0 ;
++ if( 0 < green )
++ green = (green>>1) + (green>>4) ;
++ else
++ green = 0 ;
++ if( 0 < blue )
++ blue = blue >> 3 ;
++ else
++ blue = 0 ;
++ return red+green+blue ;
++}
+
++/************************************************************************/
+ /*----------------------------------------------------------------------*/
+
+ static void console_scrollup (void)
+@@ -221,10 +259,10 @@
+ uchar *dest;
+ ushort off, row;
+
+- dest = (uchar *)(lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) / 8);
++ dest = (uchar *)(lcd_base + y * panel_info.vl_lcd_line_length + x * (1 << LCD_BPP) / 8);
+ off = x * (1 << LCD_BPP) % 8;
+
+- for (row=0; row < VIDEO_FONT_HEIGHT; ++row, dest += lcd_line_length) {
++ for (row=0; row < VIDEO_FONT_HEIGHT; ++row, dest += panel_info.vl_lcd_line_length) {
+ uchar *s = str;
+ uchar *d = dest;
+ int i;
+@@ -337,8 +375,6 @@
+
+ lcd_base = (void *)(gd->fb_base);
+
+- lcd_line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
+-
+ lcd_init (lcd_base); /* LCD initialization */
+
+ /* Device initialization */
+@@ -389,7 +425,7 @@
+ /* set framebuffer to background color */
+ memset ((char *)lcd_base,
+ COLOR_MASK(lcd_getbgcolor()),
+- lcd_line_length*panel_info.vl_row);
++ panel_info.vl_lcd_line_length*panel_info.vl_row);
+ #endif
+ /* Paint the logo and retrieve LCD base address */
+ debug ("[LCD] Drawing the logo...\n");
+@@ -500,12 +536,13 @@
+ #ifdef CONFIG_LCD_LOGO
+ void bitmap_plot (int x, int y)
+ {
+- ushort *cmap;
++ PALETTEVAL_TYPE *cmap;
+ ushort i, j;
+ uchar *bmap;
+ uchar *fb;
+ ushort *fb16;
+-#if defined(CONFIG_PXA250)
++
++#if defined(PXALCD)
+ struct pxafb_info *fbi = &panel_info.pxa;
+ #elif defined(CONFIG_MPC823)
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+@@ -514,17 +551,18 @@
+
+ debug ("Logo: width %d height %d colors %d cmap %d\n",
+ BMP_LOGO_WIDTH, BMP_LOGO_HEIGHT, BMP_LOGO_COLORS,
+- sizeof(bmp_logo_palette)/(sizeof(ushort)));
++ sizeof(bmp_logo_palette)/(sizeof(PALETTEVAL_TYPE)));
+
+ bmap = &bmp_logo_bitmap[0];
+- fb = (char *)(lcd_base + y * lcd_line_length + x);
++ fb = (char *)(lcd_base + y * panel_info.vl_lcd_line_length + x);
+
+ if (NBITS(panel_info.vl_bpix) < 12) {
+ /* Leave room for default color map */
+-#if defined(CONFIG_PXA250)
+- cmap = (ushort *)fbi->palette;
++#if defined(PXALCD)
++ cmap = (PALETTEVAL_TYPE *)fbi->palette;
+ #elif defined(CONFIG_MPC823)
+ cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]);
++#elif defined(CONFIG_SM501)
+ #endif
+
+ WATCHDOG_RESET();
+@@ -532,10 +570,13 @@
+ /* Set color map */
+ for (i=0; i<(sizeof(bmp_logo_palette)/(sizeof(ushort))); ++i) {
+ ushort colreg = bmp_logo_palette[i];
+-#ifdef CFG_INVERT_COLORS
+- *cmap++ = 0xffff - colreg;
++#if defined(CONFIG_SM501)
+ #else
++ #ifdef CFG_INVERT_COLORS
++ *cmap++ = 0xffff - colreg;
++ #else
+ *cmap++ = colreg;
++ #endif
+ #endif
+ }
+
+@@ -548,7 +589,7 @@
+ }
+ }
+ else { /* true color mode */
+- fb16 = (ushort *)(lcd_base + y * lcd_line_length + x);
++ fb16 = (ushort *)(lcd_base + y * panel_info.vl_lcd_line_length + x);
+ for (i=0; i<BMP_LOGO_HEIGHT; ++i) {
+ for (j=0; j<BMP_LOGO_WIDTH; j++) {
+ fb16[j] = bmp_logo_palette[(bmap[j])];
+@@ -570,7 +611,11 @@
+ */
+ int lcd_display_bitmap(ulong bmp_image, int x, int y)
+ {
+- ushort *cmap;
++#if defined(CONFIG_SM501)
++ uchar *cmap ;
++#else
++ PALETTEVAL_TYPE *cmap;
++#endif
+ ushort i, j;
+ uchar *fb;
+ bmp_image_t *bmp=(bmp_image_t *)bmp_image;
+@@ -579,7 +624,12 @@
+ unsigned long width, height;
+ unsigned colors,bpix;
+ unsigned long compression;
+-#if defined(CONFIG_PXA250)
++ int maxLum = 0 ;
++ int bgCol = 0 ;
++ int minLum = 0xFFFF ;
++ int fgCol = 0 ;
++
++#if defined(PXALCD)
+ struct pxafb_info *fbi = &panel_info.pxa;
+ #elif defined(CONFIG_MPC823)
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+@@ -590,7 +640,7 @@
+ (bmp->header.signature[1]=='M'))) {
+ printf ("Error: no valid bmp image at %lx\n", bmp_image);
+ return 1;
+-}
++ }
+
+ width = le32_to_cpu (bmp->header.width);
+ height = le32_to_cpu (bmp->header.height);
+@@ -616,33 +666,64 @@
+ (int)width, (int)height, (int)colors);
+
+ if (bpix==8) {
+-#if defined(CONFIG_PXA250)
+- cmap = (ushort *)fbi->palette;
++#if defined(PXALCD)
++ cmap = (PALETTEVAL_TYPE *)fbi->palette;
+ #elif defined(CONFIG_MPC823)
+ cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
++#elif defined(CONFIG_SM501)
++ cmap = (uchar *)paletteRegs ;
+ #else
+ # error "Don't know location of color map"
+ #endif
+
+ /* Set color map */
+ for (i=0; i<colors; ++i) {
++ int lum ;
+ bmp_color_table_entry_t cte = bmp->color_table[i];
++#if defined(CONFIG_SM501)
++ *cmap++ = cte.blue ;
++ *cmap++ = cte.green ;
++ *cmap++ = cte.red ;
++ *cmap++ = 0 ;
++#elif defined(CONFIG_PXA270) && defined(PXALCD)
++ *cmap = 0xFF000000 ;
++ *cmap |= cte.red << 16 ;
++ *cmap |= cte.green << 8 ;
++ *cmap |= cte.blue ;
++ *cmap++ ;
++#else
+ ushort colreg =
+ ( ((cte.red) << 8) & 0xf800) |
+ ( ((cte.green) << 4) & 0x07e0) |
+ ( (cte.blue) & 0x001f) ;
+-
+-#ifdef CFG_INVERT_COLORS
++ #ifdef CFG_INVERT_COLORS
+ *cmap = 0xffff - colreg;
+-#else
++ #else
+ *cmap = colreg;
+-#endif
+-#if defined(CONFIG_PXA250)
++ #endif
++ #if defined(PXALCD)
+ cmap++;
+-#elif defined(CONFIG_MPC823)
++ #elif defined(CONFIG_MPC823)
+ cmap--;
++ #endif
+ #endif
++ lum = luminance( cte.red, cte.green, cte.blue );
++ if( lum > maxLum )
++ {
++ maxLum = lum ;
++ bgCol = i ;
++ }
++
++ if( lum < minLum )
++ {
++ minLum = lum ;
++ fgCol = i ;
++ }
+ }
++
++ printf( "bgcolor %u, fg %u\n", bgCol, fgCol );
++ lcd_color_fg = fgCol ;
++ lcd_color_bg = bgCol ;
+ }
+
+ padded_line = (width&0x3) ? ((width&~0x3)+4) : (width);
+@@ -653,16 +734,16 @@
+
+ bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset);
+ fb = (uchar *) (lcd_base +
+- (y + height - 1) * lcd_line_length + x);
++ (y + height - 1) * panel_info.vl_lcd_line_length + x);
+ for (i = 0; i < height; ++i) {
+ for (j = 0; j < width ; j++)
+-#if defined(CONFIG_PXA250)
++#if defined(CONFIG_PXA250) || defined(CONFIG_PXA270)
+ *(fb++)=*(bmap++);
+ #elif defined(CONFIG_MPC823)
+ *(fb++)=255-*(bmap++);
+ #endif
+- bmap += (width - padded_line);
+- fb -= (width + lcd_line_length);
++ bmap += (padded_line-width);
++ fb -= (width + panel_info.vl_lcd_line_length);
+ }
+
+ return (0);
+@@ -735,7 +816,7 @@
+ #endif /* LCD_INFO */
+
+ #if defined(CONFIG_LCD_LOGO) && !defined(LCD_INFO_BELOW_LOGO)
+- return ((void *)((ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length));
++ return ((void *)((ulong)lcd_base + BMP_LOGO_HEIGHT * panel_info.vl_lcd_line_length));
+ #else
+ return ((void *)lcd_base);
+ #endif /* CONFIG_LCD_LOGO */
+diff -u -r --new-file u-boot-1.1.2/common/lcd_panels.c u-boot-1.1.2-neon/common/lcd_panels.c
+--- u-boot-1.1.2/common/lcd_panels.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/common/lcd_panels.c 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,286 @@
++/*
++ * Module lcd_panels.cpp
++ *
++ * This module defines the num_lcd_panels and lcd_panels
++ * constants as declared in lcd_panels.h
++ *
++ * Change History :
++ *
++ * $Log: lcd_panels.c,v $
++ * Revision 1.9 2006/05/23 18:46:39 ericn
++ * -added hitachi_wxga panel
++ *
++ * Revision 1.8 2005/09/19 13:15:43 ericn
++ * -updated sharp_qvga timing
++ *
++ * Revision 1.7 2005/07/18 03:05:35 ericn
++ * -update crt1024x768 timings
++ *
++ * Revision 1.6 2005/07/07 03:42:22 tkisky
++ * -make my CRT 1024x768 display work
++ *
++ * Revision 1.5 2005/06/02 04:02:39 ericn
++ * -added qvga_portrait
++ *
++ * Revision 1.4 2005/05/15 18:59:00 tkisky
++ * -change polarity of hitachi_wvga
++ *
++ * Revision 1.3 2005/05/03 15:32:11 ericn
++ * -fast pixclock for hvga, remove redundant 1024x768
++ *
++ * Revision 1.2 2005/04/30 20:33:22 ericn
++ * -added CRT support
++ *
++ * Revision 1.1 2005/04/09 17:49:17 ericn
++ * -Initial import
++ *
++ *
++ * Copyright Boundary Devices, Inc. 2005
++ */
++
++
++#include "lcd_panels.h"
++#include <common.h>
++
++/*
++Settings for Hitachi 5.7
++ PANEL_HORIZONTAL_TOTAL, 01c00160); // should be 34+320+1+64-1= 418 = 0x1A2 (Hex)
++ + 0x13f+16
++ PANEL_HORIZONTAL_SYNC, 00400161); hsync_len == 64 lmargin=0x161-0x13f=34
++ PANEL_VERTICAL_TOTAL, 0x010800f0);
++ PANEL_VERTICAL_SYNC, 0x00020104); vsync=2, upper_margin=0x0104-0xf0-1= 19
++
++In bdlogo.bmp - offset 436 is pixel data
++
++Sharp 5.7 active
++
++ STUFFREG( hTotalReg, 0x01800140 ); // should be 16+320+1+8-1 == 0x158
++ + 0x13f (width-1)
++ STUFFREG( hSyncReg, 0x0008014f ); hsync_len == 8 lmargin=0x14f-0x13f=16
++ STUFFREG( vTotalReg, 0x010700F0 );
++ STUFFREG( vSyncReg, 0x00020100 ); vsync=2, upper_margin=0x0100-0xf0+1= 17
++
++static unsigned const hTotalReg = 0x00080024 ; // 015F0140
++static unsigned const hSyncReg = 0x00080028 ; // 0008014f
++static unsigned const vTotalReg = 0x0008002c ; // 010700F0
++static unsigned const vSyncReg = 0x00080030 ; // 000200FE
++
++const unsigned int sm501_list2[]={0x0fe80000,
++dispctrl 0x0F013104, // 0f0d0105
++pan 0x00000000,
++colorkey 0x00000000,
++fbaddr 0x00000000,
++offsetww ((LCD_XRES)<<16)+(LCD_XRES),
++fbwidth (LCD_XRES<<16),
++fbheight (LCD_YRES<<16),
++tllocate 0x00000000,
++brlocate ((LCD_YRES-1)<<16)+(LCD_XRES-1),
++htotal ((LCD_BEGIN_OF_LINE_WAIT_COUNT+
++ LCD_XRES+
++ LCD_END_OF_LINE_WAIT_COUNT+
++ LCD_HORIZONTAL_SYNC_PULSE_WIDTH-1)<<16)
++ +(LCD_XRES-1),
++hsync (LCD_HORIZONTAL_SYNC_PULSE_WIDTH<<16)
++ +(LCD_XRES+LCD_BEGIN_OF_LINE_WAIT_COUNT-1),
++vtotal ((LCD_BEGIN_FRAME_WAIT_COUNT+
++ LCD_YRES+
++ LCD_END_OF_FRAME_WAIT_COUNT+
++ LCD_VERTICAL_SYNC_PULSE_WIDTH-1)<<16)
++ +(LCD_YRES-1),
++vsync (LCD_VERTICAL_SYNC_PULSE_WIDTH<<16)
++ +(LCD_YRES+LCD_BEGIN_FRAME_WAIT_COUNT-1)};
++*/
++
++static struct lcd_panel_info_t const lcd_panels_[] = {
++
++ /* char const *name */ { "hitachi_qvga"
++ /* unsigned long pixclock */ , 0
++ /* unsigned short xres */ , 320
++ /* unsigned short yres */ , 240
++ /* unsigned char act_high */ , 1
++ /* unsigned char hsync_len */ , 64
++ /* unsigned char left_margin */ , 1
++ /* unsigned char right_margin */ , 16
++ /* unsigned char vsync_len */ , 20
++ /* unsigned char upper_margin */ , 8
++ /* unsigned char lower_margin */ , 3
++ /* unsigned char active */ , 1
++ /* unsigned char crt */ , 0 }
++
++ /* char const *name */ , { "sharp_qvga"
++ /* unsigned long pixclock */ , 0
++ /* unsigned short xres */ , 320 /* , 320 */
++ /* unsigned short yres */ , 240 /* , 240 */
++ /* unsigned char act_high */ , 1 /* , 1 */
++ /* unsigned char hsync_len */ , 20 /* , 8 */
++ /* unsigned char left_margin */ , 1 /* , 16 */
++ /* unsigned char right_margin */ , 30 /* , 1 */
++ /* unsigned char vsync_len */ , 4 /* , 20 */
++ /* unsigned char upper_margin */ , 17 /* , 17 */
++ /* unsigned char lower_margin */ , 3 /* , 3 */
++ /* unsigned char active */ , 1 /* , 1 */
++ /* unsigned char crt */ , 0 }
++
++ /* char const *name */ , { "qvga_portrait"
++ /* unsigned long pixclock */ , 0
++ /* unsigned short xres */ , 240
++ /* unsigned short yres */ , 320
++ /* unsigned char act_high */ , 1
++ /* unsigned char hsync_len */ , 64
++ /* unsigned char left_margin */ , 34
++ /* unsigned char right_margin */ , 1
++ /* unsigned char vsync_len */ , 20
++ /* unsigned char upper_margin */ , 8
++ /* unsigned char lower_margin */ , 3
++ /* unsigned char active */ , 1
++ /* unsigned char crt */ , 0
++ /* unsigned rotation */ , 90 }
++
++ /* char const *name */ , { "hitachi_hvga"
++ /* unsigned long pixclock */ , 1
++ /* unsigned short xres */ , 640
++ /* unsigned short yres */ , 240
++ /* unsigned char act_high */ , 1
++ /* unsigned char hsync_len */ , 64
++ /* unsigned char left_margin */ , 34
++ /* unsigned char right_margin */ , 1
++ /* unsigned char vsync_len */ , 20
++ /* unsigned char upper_margin */ , 8
++ /* unsigned char lower_margin */ , 3
++ /* unsigned char active */ , 1
++ /* unsigned char crt */ , 0 }
++
++ /* char const *name */ , { "sharp_vga"
++ /* unsigned long pixclock */ , 1
++ /* unsigned short xres */ , 640
++ /* unsigned short yres */ , 480
++ /* unsigned char act_high */ , 1
++ /* unsigned char hsync_len */ , 64
++ /* unsigned char left_margin */ , 60
++ /* unsigned char right_margin */ , 60
++ /* unsigned char vsync_len */ , 20
++ /* unsigned char upper_margin */ , 34
++ /* unsigned char lower_margin */ , 3
++ /* unsigned char active */ , 1
++ /* unsigned char crt */ , 0 }
++
++ /* char const *name */ , { "hitachi_wvga"
++ /* unsigned long pixclock */ , 1
++ /* unsigned short xres */ , 800
++ /* unsigned short yres */ , 480
++ /* unsigned char act_high */ , 1
++ /* unsigned char hsync_len */ , 64
++ /* unsigned char left_margin */ , 1
++ /* unsigned char right_margin */ , 39
++ /* unsigned char vsync_len */ , 20
++ /* unsigned char upper_margin */ , 8
++ /* unsigned char lower_margin */ , 3
++ /* unsigned char active */ , 1
++ /* unsigned char crt */ , 0 }
++// Note that you can use the nifty tool at the
++// following location to generate these values:
++// http://www.tkk.fi/Misc/Electronics/faq/vga2rgb/calc.html
++, {
++ name: "crt1024x768",
++ pixclock: 65000000,
++ xres: 1024,
++ yres: 768,
++ act_high : 0,
++ hsync_len: 136,
++ left_margin: 24,
++ right_margin: 160,
++ vsync_len: 6,
++ upper_margin: 3,
++ lower_margin: 29,
++ active : 0,
++ crt : 1
++}
++, {
++ name: "hitachi_wxga",
++ pixclock: 1,
++ xres: 1024,
++ yres: 768,
++ act_high : 1,
++ hsync_len: 64,
++ left_margin: 1,
++ right_margin: 39,
++ vsync_len: 20,
++ upper_margin: 8,
++ lower_margin: 3,
++ active : 1,
++ crt : 0
++}
++};
++
++/*
++. e
++typedef enum _polarity_t
++{
++ POSITIVE,
++ NEGATIVE,
++}
++polarity_t;
++
++typedef struct _mode_table_t
++{
++ // Horizontal timing.
++ int horizontal_total;
++ int horizontal_display_end;
++ int horizontal_sync_start;
++ int horizontal_sync_width;
++ polarity_t horizontal_sync_polarity;
++
++ // Vertical timing.
++ int vertical_total;
++ int vertical_display_end;
++ int vertical_sync_start;
++ int vertical_sync_height;
++ polarity_t vertical_sync_polarity;
++
++ // Refresh timing.
++ long pixel_clock;
++ long horizontal_frequency;
++ long vertical_frequency;
++}
++mode_table_t;
++
++ // 1024 x 768
++ htotal dend hsstrt hsw hpolar vtot vdend vdstrt vsh vpolar pixclk hfreq vfreq
++{ 1344, 1024, 1048, 136, NEGATIVE, 806, 768, 771, 6, NEGATIVE, 65000000, 48363, 60 },
++{ 1328, 1024, 1048, 136, NEGATIVE, 806, 768, 771, 6, NEGATIVE, 75000000, 56476, 70 },
++{ 1312, 1024, 1040, 96, POSITIVE, 800, 768, 769, 3, POSITIVE, 78750000, 60023, 75 },
++{ 1376, 1024, 1072, 96, POSITIVE, 808, 768, 769, 3, POSITIVE, 94500000, 68677, 85 },
++
++0FE80200/00010000 + CRT regs
++0FE80204/00180000 +
++0FE80208/08000800 +
++0FE8020C/05D003FF +
++0FE80210/00C80424 +
++0FE80214/032502FF +
++0FE80218/00060302 +
++0FE8021C/00000000 +
++0FE80220/00000000 +
++0FE80224/00400200 +
++0FE80228/00000000 +
++0FE8022C/00000000 +
++0FE80230/00000800 +
++0FE80234/00000000 +
++0FE80238/08000000 +
++0FE8023C/00000400 +
++*/
++
++struct lcd_panel_info_t const * const lcd_panels = lcd_panels_ ;
++unsigned const num_lcd_panels = sizeof(lcd_panels_)/sizeof(lcd_panels_[0]);
++
++struct lcd_panel_info_t const *find_lcd_panel( char const * name )
++{
++ unsigned i ;
++ for( i = 0 ; i < num_lcd_panels ; i++ )
++ {
++ if( 0 == strcmp( lcd_panels_[i].name, name ) )
++ return lcd_panels_+i ;
++ }
++ return 0 ;
++}
++
++struct lcd_panel_info_t const *cur_lcd_panel = 0 ;
+diff -u -r --new-file u-boot-1.1.2/common/Makefile u-boot-1.1.2-neon/common/Makefile
+--- u-boot-1.1.2/common/Makefile 2004-12-16 18:35:57.000000000 +0100
++++ u-boot-1.1.2-neon/common/Makefile 2007-08-11 21:07:20.000000000 +0200
+@@ -35,16 +35,16 @@
+ cmd_eeprom.o cmd_elf.o cmd_ext2.o \
+ cmd_fat.o cmd_fdc.o cmd_fdos.o cmd_flash.o cmd_fpga.o \
+ cmd_i2c.o cmd_ide.o cmd_immap.o cmd_itest.o cmd_jffs2.o \
+- cmd_load.o cmd_log.o \
++ cmd_lcdpanel.o cmd_load.o cmd_log.o \
+ cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
+- cmd_nand.o cmd_net.o cmd_nvedit.o \
++ cmd_nand.o cmd_net.o cmd_not.o cmd_nvedit.o \
+ cmd_pci.o cmd_pcmcia.o cmd_portio.o \
+ cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o cmd_usb.o cmd_vfd.o \
+ command.o console.o devices.o dlmalloc.o docecc.o \
+ environment.o env_common.o \
+ env_nand.o env_dataflash.o env_flash.o env_eeprom.o env_nvram.o env_nowhere.o exports.o \
+- flash.o fpga.o \
+- hush.o kgdb.o lcd.o lists.o lynxkdi.o \
++ flash.o fnmatch.o fpga.o \
++ hush.o kgdb.o lcd.o lcd_panels.o lists.o lynxkdi.o \
+ memsize.o miiphybb.o miiphyutil.o \
+ s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o \
+ usb.o usb_kbd.o usb_storage.o \
+diff -u -r --new-file u-boot-1.1.2/config.mk u-boot-1.1.2-neon/config.mk
+--- u-boot-1.1.2/config.mk 2004-10-10 00:21:30.000000000 +0200
++++ u-boot-1.1.2-neon/config.mk 2007-08-11 21:07:20.000000000 +0200
+@@ -22,6 +22,7 @@
+ #
+
+ #########################################################################
++sinclude select.mk # include DISPLAY_TYPE, HARDWARE_TYPE, SOFTWARE_TYPE, INCLUDE_MINIDEBUG
+
+ # clean the slate ...
+ PLATFORM_RELFLAGS =
+@@ -106,11 +107,15 @@
+ OPTFLAGS= -Os #-fomit-frame-pointer
+ ifndef LDSCRIPT
+ #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug
++ifeq ($(INCLUDE_MINIDEBUG),y)
++LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-bootmini.lds
++else
+ LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
+ endif
++endif
+ OBJCFLAGS += --gap-fill=0xff
+
+-gccincdir := $(shell $(CC) -print-file-name=include)
++gccincdir := "$(shell $(CC) -print-file-name=include)"
+
+ CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \
+ -D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) \
+@@ -170,11 +175,19 @@
+
+ #########################################################################
+
++ifdef LISTINGS
++%.s: %.S
++ $(CPP) $(AFLAGS) -Wa,-alh=$(basename $<).lst -o $@ $(CURDIR)/$<
++%.o: %.S
++ $(CC) $(AFLAGS) -c -Wa,-alh=$(basename $<).lst -o $@ $(CURDIR)/$<
++%.o: %.c
++ $(CC) $(CFLAGS) -c -Wa,-alh=$(basename $<).lst -o $@ $<
++else
+ %.s: %.S
+ $(CPP) $(AFLAGS) -o $@ $(CURDIR)/$<
+ %.o: %.S
+ $(CC) $(AFLAGS) -c -o $@ $(CURDIR)/$<
+ %.o: %.c
+ $(CC) $(CFLAGS) -c -o $@ $<
+-
++endif
+ #########################################################################
+diff -u -r --new-file u-boot-1.1.2/Configure u-boot-1.1.2-neon/Configure
+--- u-boot-1.1.2/Configure 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/Configure 2007-08-11 21:07:19.000000000 +0200
+@@ -0,0 +1,170 @@
++#!/bin/bash
++#=======================================================================
++DISPLAY_TYPE_CHOICES="DA640X240 DA320X240 DA800X480 DA640X480 DA240X320 DA800X600 DA1024X768 DP320X240 DP480X320 DL122X32"
++PLATFORM_TYPE_CHOICES="NEONB NEON HALOGEN BD2003 GAME_WITH_SMC GAME_CONTROLLER"
++# BOUNDARY_OLD_BOARD #lcd pin reordering for rgb problem, don't use VLIO(gp18 is turnstile)
++# OLD_GAME_CONTROLLER GAME_CONTROLLER_PLAITED_A1
++REVISION_CHOICES="1 2"
++
++SOFTWARE_TYPE_CHOICES="WINCE LINUX GAME"
++INCLUDE_MINIDEBUG_CHOICES="y n"
++CPU_CLOCK_CHOICES="100 200 300 400"
++CPU_CLOCK_PXA270_CHOICES="104 208 312 416 520 624"
++
++CONFIG_H=include/configs/select.h
++CONFIG_MK=select.mk
++CONFIG_LOG=select.log
++
++fail ()
++{
++ echo ""
++ echo "Configuration failed."
++ echo ""
++ exit 1
++}
++
++if [ -f $CONFIG_MK ] ; then
++. ./$CONFIG_LOG
++fi
++
++
++
++#=======================================================================
++
++
++arg () {
++ VALUE="`echo X"$2" | sed -e 's/^X--[a-zA-Z_]*=//'`"
++ eval $1=\"$VALUE\"
++ eval $1_P='y'
++}
++
++usage () {
++ echo "bad parameters"
++ exit 1
++}
++
++while [ $# -gt 0 ] ; do
++ case "$1" in
++ --DISPLAY_TYPE=*) arg DISPLAY_TYPE $1 ;;
++ --PLATFORM_TYPE=*) arg PLATFORM_TYPE $1 ;;
++ --SOFTWARE_TYPE=*) arg SOFTWARE_TYPE $1 ;;
++ --INCLUDE_MINIDEBUG=*) arg INCLUDE_MINIDEBUG $1 ;;
++ --CPU_CLOCK=*) arg CPU_CLOCK $1 ;;
++ *) usage ;;
++ esac
++ shift
++done
++
++#=======================================================================
++
++write_str () {
++ value=`eval echo '$'$1`
++ echo "$1=$value" >> $CONFIG_MK
++ echo "$1=\"$value\"" >> $CONFIG_LOG
++ if [ x$3 != x ] ; then
++ choices=`eval echo '$'$2`
++ str=""
++ for a in $choices ; do
++ if [ -n "$str" ] ; then str="$str && " ; fi
++ str="$str!defined($3$a)";
++ done
++ echo "#if $str" >> $CONFIG_H
++ echo "#define $3$value" >> $CONFIG_H
++ echo "#endif" >> $CONFIG_H
++ else
++ echo "#ifndef $1" >> $CONFIG_H
++ echo "#define $1 $value" >> $CONFIG_H
++ echo "#endif" >> $CONFIG_H
++ fi
++}
++
++prompt () {
++ eval $3=\"$2\"
++ /bin/echo -e "$1 [$2]: \c"
++ read tmp
++ if [ -n "$tmp" ] ; then eval $3=\"$tmp\" ; fi
++ if [ ! -t 1 ] ; then echo $3 ; fi
++}
++noprompt () {
++ eval $3=\"$2\"
++ /bin/echo -e "$1 [$2]: "
++ if [ ! -t 1 ] ; then echo $3 ; fi
++}
++
++
++ask_str () {
++ choices=`eval echo '$'$3`
++ default=`eval echo '$'$2`
++ ppp=`eval echo '$'$2_P`
++ ans=""
++ stop="0"
++ if [ x$ppp = x"y" ] ; then
++ noprompt "$1 ($choices)" "$default" answer
++ for a in $choices ; do
++ if [ x$a = x$answer ] ; then ans=$a; stop="1"; break; fi;
++ done
++ if [ $stop != "1" ] ; then default=""; fi;
++ fi
++ while [ $stop != "1" ] ; do
++ prompt "$1 ($choices)" "$default" answer
++ for a in $choices ; do
++ if [ x$a = x$answer ] ; then ans=$a; stop="1"; break; fi;
++ done
++ done
++ eval $2=\"$ans\"
++}
++#=======================================================================
++
++echo ""
++echo " -------- U-Boot Boundary Devices Specific Configuration Script --------"
++echo ""
++echo ""
++
++ask_str "Choose display type" DISPLAY_TYPE DISPLAY_TYPE_CHOICES
++ask_str "Choose hardware type" PLATFORM_TYPE PLATFORM_TYPE_CHOICES
++ if [ x$PLATFORM_TYPE = xHALOGEN ] ; then
++ask_str "Choose hardware revision" PLATFORM_REV REVISION_CHOICES
++ fi
++ask_str "Choose software type" SOFTWARE_TYPE SOFTWARE_TYPE_CHOICES
++ask_str "Include minidebug" INCLUDE_MINIDEBUG INCLUDE_MINIDEBUG_CHOICES
++
++ if [ x$PLATFORM_TYPE = xHALOGEN ] ; then
++ask_str "CPU clock" CPU_CLOCK CPU_CLOCK_PXA270_CHOICES
++ else
++ask_str "CPU clock" CPU_CLOCK CPU_CLOCK_CHOICES
++ fi
++
++rm -f $CONFIG_H $CONFIG_MK
++
++cat << 'EOF' > $CONFIG_H
++/*
++ Automatically generated by 'make xxx_config' -- don't edit!
++*/
++#include <asm/arch/platformTypes.h>
++EOF
++
++cat << 'EOF' > $CONFIG_MK
++#
++# Automatically generated by 'make xxx_config' -- don't edit!
++#
++EOF
++
++cat << 'EOF' > $CONFIG_LOG
++#!/bin/bash
++EOF
++
++chmod 777 $CONFIG_LOG
++
++write_str DISPLAY_TYPE DISPLAY_TYPE_CHOICES
++write_str PLATFORM_TYPE PLATFORM_TYPE_CHOICES
++ if [ x$PLATFORM_TYPE = xHALOGEN ] ; then
++write_str PLATFORM_REV REVISION_CHOICES
++ fi
++write_str SOFTWARE_TYPE SOFTWARE_TYPE_CHOICES
++write_str INCLUDE_MINIDEBUG INCLUDE_MINIDEBUG_CHOICES
++ if [ x$PLATFORM_TYPE = xHALOGEN ] ; then
++write_str CPU_CLOCK CPU_CLOCK_PXA270_CHOICES
++ else
++write_str CPU_CLOCK CPU_CLOCK_CHOICES
++ fi
++echo "Configuration successful."
+diff -u -r --new-file u-boot-1.1.2/cpu/mpc8xx/lcd.c u-boot-1.1.2-neon/cpu/mpc8xx/lcd.c
+--- u-boot-1.1.2/cpu/mpc8xx/lcd.c 2004-10-10 01:26:00.000000000 +0200
++++ u-boot-1.1.2-neon/cpu/mpc8xx/lcd.c 2007-08-11 21:07:20.000000000 +0200
+@@ -255,7 +255,6 @@
+ /*----------------------------------------------------------------------*/
+
+
+-int lcd_line_length;
+
+ int lcd_color_fg;
+ int lcd_color_bg;
+diff -u -r --new-file u-boot-1.1.2/cpu/pxa/config.mk u-boot-1.1.2-neon/cpu/pxa/config.mk
+--- u-boot-1.1.2/cpu/pxa/config.mk 2003-05-23 14:36:21.000000000 +0200
++++ u-boot-1.1.2-neon/cpu/pxa/config.mk 2007-08-11 21:15:47.000000000 +0200
+@@ -21,8 +21,19 @@
+ # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ # MA 02111-1307 USA
+ #
+-
+-PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
+- -mshort-load-bytes -msoft-float
+-
+-PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100
+++sinclude ../../select.mk # include DISPLAY_TYPE, HARDWARE_TYPE, SOFTWARE_TYPE, INCLUDE_MINIDEBUG
+++
+++PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8
+++PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4
+++GCC_MAJOR := $(shell $(CC) -v 2>&1 | grep version | cut -d' ' -f3 | cut -d'.' -f1)
+++GCC_MINOR := $(shell $(CC) -v 2>&1 | grep version | cut -d' ' -f3 | cut -d'.' -f2)
+++
+++ifneq ($(GCC_MAJOR),3)
+++ PLATFORM_CPPFLAGS += -mtune=strongarm1100
+++ PLATFORM_RELFLAGS += -msoft-float
+++else
+++ PLATFORM_CPPFLAGS += -mtune=xscale
+++ ifneq ($(GCC_MINOR),4)
+++ PLATFORM_RELFLAGS += -msoft-float
+++ endif
+++endif
+diff -u -r --new-file u-boot-1.1.2/cpu/pxa/cpu.c u-boot-1.1.2-neon/cpu/pxa/cpu.c
+--- u-boot-1.1.2/cpu/pxa/cpu.c 2004-02-08 20:38:44.000000000 +0100
++++ u-boot-1.1.2-neon/cpu/pxa/cpu.c 2007-08-11 21:07:20.000000000 +0200
+@@ -33,6 +33,7 @@
+ #include <common.h>
+ #include <command.h>
+ #include <asm/arch/pxa-regs.h>
++#include <asm/arch/mmc.h>
+
+ int cpu_init (void)
+ {
+@@ -59,8 +60,12 @@
+
+ unsigned long i;
+
++ MMC_STRPCL = MMC_STRPCL_STOP_CLK;
++
+ disable_interrupts ();
+
++ dcache_disable();
++
+ /* turn off I-cache */
+ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ i &= ~0x1000;
+@@ -129,21 +134,6 @@
+ return (i & 0x1000);
+ }
+
+-/* we will never enable dcache, because we have to setup MMU first */
+-void dcache_enable (void)
+-{
+- return;
+-}
+-
+-void dcache_disable (void)
+-{
+- return;
+-}
+-
+-int dcache_status (void)
+-{
+- return 0; /* always off */
+-}
+
+ void set_GPIO_mode(int gpio_mode)
+ {
+diff -u -r --new-file u-boot-1.1.2/cpu/pxa/Makefile u-boot-1.1.2-neon/cpu/pxa/Makefile
+--- u-boot-1.1.2/cpu/pxa/Makefile 2003-06-16 00:40:43.000000000 +0200
++++ u-boot-1.1.2-neon/cpu/pxa/Makefile 2007-08-11 21:07:20.000000000 +0200
+@@ -23,10 +23,45 @@
+
+ include $(TOPDIR)/config.mk
+
++CPU_TYPE=xscale
++
++ifeq ($(SOFTWARE_TYPE),WINCE)
++STACKS_VALID = -DCONFIG_STACKS_VALID
++else
++
++ifeq ($(SOFTWARE_TYPE),GAME)
++STACKS_VALID = -DCONFIG_STACKS_VALID
++else
++STACKS_VALID =
++endif
++endif
++ARM_ELF_GCC ?= arm-elf-gcc
++
+ LIB = lib$(CPU).a
+
+-START = start.o
+-OBJS = serial.o interrupts.o cpu.o i2c.o pxafb.o mmc.o
++ifeq ($(INCLUDE_MINIDEBUG),y)
++START = minidebug.o ministart.o
++else
++START = start.o ministart.o
++endif
++OBJS = serial.o interrupts.o cpu.o i2c.o mmc.o
++
++ifdef PXALCD
++ OBJS += pxafb.o
++endif
++
++ifeq ($(PLATFORM_TYPE),HALOGEN)
++ OBJS += usb_ohci.o
++else
++ifeq ($(PLATFORM_TYPE),NEON)
++ OBJS += usb_ohci.o
++else
++ifeq ($(PLATFORM_TYPE),NEONB)
++ OBJS += usb_ohci.o
++else
++endif
++endif
++endif
+
+ all: .depend $(START) $(LIB)
+
+@@ -35,9 +70,13 @@
+
+ #########################################################################
+
+-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
+- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
++.depend: Makefile $(START) $(OBJS)
++ $(CC) -M $(CFLAGS) -DUBOOT=1 $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+ sinclude .depend
+
++minidebug.o : minidebug.S Makefile
++ $(ARM_ELF_GCC) -c $(D_GNUC) -DUBOOT=1 -DDISPLAY_TYPE=$(DISPLAY_TYPE) -DPLATFORM_TYPE=$(PLATFORM_TYPE) -DPLATFORM_REV=$(PLATFORM_REV) -DSOFTWARE_TYPE=$(SOFTWARE_TYPE) $(STACKS_VALID) -DCPU_CLOCK=$(CPU_CLOCK) \
++ $(SOFT_FLOAT) -I$(TOPDIR)/include -mtune=$(CPU_TYPE) -mcpu=$(CPU_TYPE) -o $@ $<
++
+ #########################################################################
+diff -u -r --new-file u-boot-1.1.2/cpu/pxa/minidebug.S u-boot-1.1.2-neon/cpu/pxa/minidebug.S
+--- u-boot-1.1.2/cpu/pxa/minidebug.S 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/cpu/pxa/minidebug.S 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,3850 @@
++ .nolist
++ .ifdef __ARMASM
++UBOOT EQU 0
++CONFIG_UNSCRAMBLE_LCD EQU 0
++LCD_REORDER_BLUE EQU 1
++ .endif
++
++#ifdef UBOOT
++#include <asm/arch/platformTypes.h>
++#include <configs/select.h>
++#include <asm/arch/pxaGpio.h>
++#include <asm/arch/pxaMacro3.h>
++#include <asm/arch/miniMac.inc>
++#include <asm/arch/burn.inc>
++#else
++#include "platformTypes.h"
++#include "pxaGpio.h"
++#include "pxaMacro3.h"
++#include "miniMac.inc"
++#include "burn.inc"
++ .ifdef __ARMASM
++ STARTUPTEXT
++ EXTERN HeadStart
++ .endif
++#endif
++
++ .list
++ .global StartUp
++
++
++#define L1(a) ((CH_##a))
++#define L2(a,b) ((CH_##a)+(CH_##b<<8))
++#define L3(a,b,c) ((CH_##a)+(CH_##b<<8)+(CH_##c<<16))
++#define L4(a,b,c,d) ((CH_##a)+(CH_##b<<8)+(CH_##c<<16)+(CH_##d<<24))
++
++#define C2(a,b) ((CH_##a<<8)+(CH_##b))
++#define C3(a,b,c) ((CH_##a<<16)+(CH_##b<<8)+(CH_##c))
++#define C4(a,b,c,d) ((CH_##a<<24)+(CH_##b<<16)+(CH_##c<<8)+(CH_##d))
++
++// *******************************************************************************************
++// *******************************************************************************************
++
++
++//.global _start
++//_start:
++StartUp:
++ b V_Reset //0
++ b V_UndefinedInstr //4
++ b V_SWI //8
++ b V_PrefetchAbort //0x0c
++ b V_DataAbort //0x10
++ b V_Unused //0x14, not used
++ b V_IRQ //0x18
++// b V_FIQ //0x1c
++
++//In Linux, all modes switch almost immediately to the SVC mode
++//and it is the only one with a valid stack
++//FIQ & SWI stacks are always assumed valid
++V_FIQ:
++ V_VectorEntrance V_rWork,V_rBranch,SIG_FIQ
++
++join_fiq:
++ CheckBranch V_rWork,V_rBranch
++ V_VectorExitCC V_rWork,V_rBranch,eq,eqia
++ CheckLdr V_rWork,V_rBranch
++ V_VectorExitCC1 V_rWork,V_rBranch,cc,ccia
++join_fiq2:
++ sub sp,sp,#(DEBUG_SPACE-DBG_R0) //the extra 12 bytes already on stack are needed for indirect return for SDS bug
++ stmia sp,{r0,r1}
++ sub r1,V_rBranch,#8 //restore to SIG_xxx value
++ add r0,sp,#(DEBUG_SPACE-DBG_R0)
++ ldr V_rWork,[r0],#4
++ ldr V_rBranch,[r0],#8
++ str r0,[sp,#DBG_HSP-DBG_R0]
++ sub r0,sp,#DBG_R0
++join_fiq3:
++ mov r1,r1,LSR #2
++ and r1,r1,#0xf
++ b SaveRest2
++V_Reset:
++//this is either a normal processor reset, or a debug exception in halt mode
++ mrs sp,cpsr
++ and sp,sp,#0x1f
++ cmp sp,#0x15
++ bne 2f
++//this is a debug exception in halt mode
++ CP14_DCSR mrc,sp
++ and sp,sp,#0x1c
++ cmp sp,#0 //reset
++ cmpne sp,#5<<2 //vector trap (reset vector)
++ bne 10f //initialization already done
++
++ BigMov sp,PWR_MANAGER_BASE
++ ldr sp,[sp,#RCSR]
++ tst sp,#2
++ tsteq pc,#0xff000000
++ bne 2f //br if watchdog reset or if not nCS0 address
++
++//signal debugger that he can download into main instruction cache now
++ CP14_TX mcr,sp
++1:
++ CP14_TXRXCTRL mrc,r15 //r15 means update condition codes
++ bpl 1b
++ CP14_RX mrc,sp //just read and discard
++2:
++ CP14_DCSR mrc,sp
++ orr sp,sp,#1<<31 //set global debug enable bit
++ CP14_DCSR mcr,sp
++
++// InitGPIO r0,sp
++// InitIC_Clocks r0,sp
++// InitUART r0,sp,UART_BASE,BAUDRATE
++// TransMacro L1(U)
++ b MainInitializationCode //this can be in the main instruction cache not locked
++ //because it is only executed upon reset
++
++10:
++ cmp sp,#1<<2 //Instruction breakpoint
++ mov sp,r0 //save r0
++ BigMov r0,DEBUG_BASE
++ str sp,[r0,#DBG_R0]
++ str r1,[r0,#DBG_R1]
++ str r2,[r0,#DBG_R2]
++SSDebug:
++ bne 11f
++//this is a breakpoint
++ ldr r1,[r0,#DBG_TRACE]
++ tst r1,#1
++ beq 11f
++ cmn r1,#1
++ moveq r1,#0
++ CP15_IBCR1 mrc,sp
++ sub r2,lr,#3
++ cmp sp,r2
++ CP15_IBCR1 mcreq,r1 //remove breakpoint if single-stepping
++ beq 11f
++ CP15_IBCR0 mrc,sp
++ cmp sp,r2
++ CP15_IBCR0 mcreq,r1
++11:
++ mrs r2,spsr
++ sub lr,lr,#4
++
++ str r3,[r0,#DBG_R3]
++ ldrb r3,[r0,#DBG_Mode]
++SaveDebug:
++ CP14_DCSR mrc,sp
++// str sp,[r0,#DBG_Temp] //the mcr CP14_DCSR instruction below will trash sp in SDS (special debug state)
++ and r1,sp,#0x1c
++ orr sp,sp,#0x1c
++ CP14_DCSR mcr,sp
++ mov r1,r1,LSR #2
++ add r1,r1,#SIG_DBG
++ b SaveR4andUp
++
++V_UndefinedInstr:
++ VectorEntrance rWork,rBranch,SIG_UNDEFINED_INSTRUCTION
++ JOIN b
++V_IRQ:
++ VectorEntrance rWork,rBranch,SIG_IRQ
++
++ .if STACKS_VALID
++ JOIN b
++ .else
++join_irq:
++ CheckBranch I_rWork,I_rBranch
++ I_VectorExitCC I_rWork,I_rBranch,eq,eqia
++
++ CheckLdr I_rWork,I_rBranch
++ I_VectorExitCC1 I_rWork,I_rBranch,cc,ccia
++join_irq2:
++ strd r0,[I_rWork,#DBG_R0-DBG_MAGIC]
++ sub r0,I_rWork,#DBG_MAGIC
++ sub r1,I_rBranch,#8 //restore to SIG_xxx value
++ ldr I_rWork,[r0,#DBG_TEMP]
++ add sp,r0,#DBG_INDIRECT_R0+8 //sp is trashed, if stacks assumed invalid
++ str sp,[r0,#DBG_HSP]
++ b join_fiq3
++ .endif
++
++//sp is valid for this!!!!!, what a treat
++V_SWI:
++ V_VectorEntrance V_rWork,V_rBranch,SIG_SWI
++ b join_fiq
++
++//monitor mode also has instruction breakpoint, bkpt instruction
++V_PrefetchAbort:
++ VectorEntrance rWork,rBranch,SIG_PREFETCH_ABORT
++ CP15_FSR mrc,rWork
++ tst rWork,#1<<9
++ bne DEBUG_EVENT //br if a debug event, in monitor mode
++
++//the 1st instruction after exiting special debug state can cause an abort or possibly the wrong instruction to execute.
++//the Immu is not turned on until the 2nd instruction.
++ tst rWork,#1<<10
++ JOIN beq
++ and rWork,rWork,#0xf
++ cmp rWork,#0x6
++ JOIN bne //br if not an external abort
++
++ CP15_CONTROL mrc,rWork //get the control register
++ tst rWork,#1 //test MMU
++
++ BigMov rWork,DEBUG_BASE+DBG_ABORT_PC
++ swpne rWork,lr,[rWork] //save lr as a flag so not infinite errors, if mmu on
++ cmpne rWork,lr
++
++ .if STACKS_VALID
++ ldrne rBranch,[sp,#4]
++ ldrne rWork,[sp],#12
++ subnes pc,lr,#4 //retry access
++ .else
++ BigMov rWork,DEBUG_BASE+DBG_MAGIC
++ ldrne rWork,[rWork,#DBG_TEMP-DBG_MAGIC]
++ subnes pc,lr,#4 //retry access
++ .endif
++
++ add rBranch,rBranch,#8
++ JOIN2 b
++
++//stacks aren't kept valid
++//monitor mode also has data breakpoint, external debug break, trace-buffer full break
++V_DataAbort:
++ VectorEntrance rWork,rBranch,SIG_DATA_ABORT
++ CP15_FSR mrc,rWork
++ tst rWork,#1<<9
++ JOIN beq
++ sub lr,lr,#4 //+8 of offending instruction for most data aborts instead of +4
++DEBUG_EVENT:
++ BigMov rWork,DEBUG_BASE+DBG_MAGIC
++ strd r0,[rWork,#DBG_R0-DBG_MAGIC]
++ sub r0,rWork,#DBG_MAGIC
++
++ .if STACKS_VALID
++ ldr rWork,[sp],#4
++ ldr rBranch,[sp],#8
++ .else
++ ldr rWork,[r0,#DBG_TEMP]
++ add sp,r0,#DBG_INDIRECT_R0+8 //sp is trashed, if stacks assumed invalid
++ .endif
++ str sp,[r0,#DBG_HSP]
++ CP14_DCSR mrc,sp
++ and sp,sp,#0x1c
++ cmp sp,#1<<2 //Instruction breakpoint
++ str r2,[r0,#DBG_R2]
++ b SSDebug
++
++V_Unused:
++ mov sp,r0 //save r0
++ BigMov r0,DEBUG_BASE
++ str sp,[r0,#DBG_R0]
++ str r1,[r0,#DBG_R1]
++ mov r1,#SIG_UNUSED
++// b SaveRest2
++
++//r0 - debug storage
++//r1 - reason for getting here
++SaveRest2:
++ str r2,[r0,#DBG_R2]
++ sub lr,lr,#4
++ mrs r2,spsr
++ str r3,[r0,#DBG_R3]
++ ldrb r3,[r0,#DBG_Mode]
++//r2 - spsr
++//r3 - DBG_MODE - don't assume that ram is working upon reset
++SaveR4andUp:
++ str r4,[r0,#DBG_R4]
++ str lr,[r0,#DBG_PC] //return PC
++ str r2,[r0,#DBG_CPSR] //return CPSR
++ mrs r4,cpsr
++ str r4,[r0,#DBG_HCPSR] //mode to return to before exception return
++
++ tst r2,#0xf
++ orreq r2,r2,#0xdf //if user mode, switch to system mode to access user registers, set I, F
++ orrne r2,r2,#0xc0 //set I, F
++ msr cpsr_c,r2
++
++ add r2,r0,#DBG_R5
++ stmia r2,{r5,r6,r7,r8,r9,sl,fp,ip,sp,lr}
++// **********************************
++// **********************************
++
++ mov rDBG,r0
++ mov r6,r1 //reason
++ mov r5,r3 //DBG_MODE
++ strb r2,[rDBG,#DBG_LastSignal]
++ CP15_CONTROL mrc,r1 //get the control register
++ tst r1,#1
++ BigMov rUart,UART_BASE //this is right if MMU is off
++ blne GetUartAddress //if MMU is on
++ b gdb_lastSignal1
++
++//r1 - CP15_CONTROL(r1)
++GetUartAddress:
++ tst r1,#1<<13 //assume 1:1 mapping for TTBR if relocation vector is off
++// see if identity mapping is enabled
++ CP15_TTBR mrc,r1
++// using Big will generate no instructions if Wince, throwing off my reloc vector
++// BigAdd2Ne r1,(SDRAM_BASE_C_VIRTUAL-0xA0000000)
++ addne r1,r1,#(SDRAM_BASE_C_VIRTUAL-0xA0000000) //convert this physical address to a virtual address if relocation vector ON
++
++ ldr r2,[r1,rUart,lsr #18]
++ sub r2,r2,rUart
++ cmp r2,#1<<20
++ movcc pc,lr //identity mapping on
++
++ mov r3,rUart
++ BigMov rUart,UART_VIRT_BASE
++1: ldr r2,[r1,rUart,lsr #18]
++ tst r2,#3
++ beq 2f
++ sub r2,r2,r3
++ cmp r2,#1<<20
++ movcc pc,lr //br if found virtual address
++ adds rUart,rUart,#1<<20
++ moveq rUart,#0xE0000000
++ b 1b
++2:
++ BigOrr2 r3,0xc02
++ str r3,[r1,rUart,lsr #18] //steal this unused entry
++// b cache_clean_invalidate_all
++
++cache_clean_invalidate_all:
++//flush data cache, if data cache is enabled
++ CP15_CONTROL mrc,r0 //get the control register
++ tst r0,#4
++ moveq pc,lr //return if disabled
++
++// Set baseaddress as the 1st virtual address of a 32k range used only
++// to flush the data cache. baseaddress should be aligned on a 32 byte(cache-line) boundary.
++// If the virtual range beginning with baseaddress is used for any purpos other than flushing
++// the data cache, then cachelinecount must be doubled from 1024 to 2048
++ mov r1,#cachelinecount
++ ldr r0,[rDBG,#DBG_PC] //I hope my return address is mapped
++ BigBic2 r0,0xffff
++1:
++ CP15_CF_ALLOC_LINE mcr,r0 //allocate a cache line for r0
++ add r0,r0,#cachelinesize
++ subs r1,r1,#1
++ bne 1b
++
++// teq r2, #0 // if running only from cache, an invalidate could be fatal if not done from minicache
++ // and then, a return to caller would not be allowed, so invalidate is postponed
++// CP15_CF_INVAL_I mcrne,r0
++ CP15_CF_DRAIN mcr,r0
++ CP15_CF_INVAL_D mcr,r0
++// The instruction cache is guaranteed to be invalidated at this point. The
++// next instruction sees the result of the invalidate command.
++ mov pc,lr
++
++
++//r0 - value to printm r9 - chksum
++PrintHexEndian:
++#if LITTLE_ENDIAN
++ mov r2,#8
++1: mov r4,r0
++ mov r3,lr
++2: tst r2,#1
++ moveq r0,r4,LSR #4
++ andne r0,r4,#0xf
++ andeq r0,r0,#0xf
++ movne r4,r4,ROR #8
++ cmp r0,#0xA
++ addcs r0,r0,#L1(a)-0x0a
++ addcc r0,r0,#L1(0)
++ add r9,r9,r0
++ bl Transmit
++ subs r2,r2,#1
++ bne 2b
++ mov pc,r3
++
++PrintHexByteEndian:
++ mov r2,#2
++ b 1b
++#else
++ mov r2,#8
++ mov r4,r0
++1: mov r3,lr
++2: mov r4,r4,ROR #28
++ and r0,r4,#0xf
++ cmp r0,#0xA
++ addcs r0,r0,#L1(a)-0x0a
++ addcc r0,r0,#L1(0)
++ add r9,r9,r0
++ bl Transmit
++ subs r2,r2,#1
++ bne 2b
++ mov pc,r3
++PrintHexByteEndian:
++ mov r4,r0,LSL #24
++ mov r2,#2
++ b 1b
++#endif
++
++PrintHexByte:
++ mov r4,r0,LSL #24
++ mov r2,#2
++ b PrintHex1
++
++TransmitCRLF:
++ BigMov r0,L2(CR,LF)
++ b Transmit
++
++
++ .if STACKS_VALID
++ .else
++// *******************************************************
++ RelocationVector 0
++// *******************************************************
++ .endif
++
++
++//IN: r0 - value to print
++//OUT: r0-r4 trashed
++PrintHex:
++ mov r2,#8
++ mov r4,r0
++PrintHex1:
++ mov r3,lr
++1: mov r4,r4,ROR #28
++ and r0,r4,#0xf
++ cmp r0,#0xA
++ addcs r0,r0,#L1(A)-0x0a
++ addcc r0,r0,#L1(0)
++ bl Transmit
++ subs r2,r2,#1
++ bne 1b
++ mov pc,r3
++
++
++TransmitSPACE:
++ mov r0,#L1(SPACE)
++// b Transmit
++
++//IN: r0 - character to transmit
++//OUT: r0 - last character transmitted, r1 - trashed
++Transmit1:
++Transmit:
++1: ldr r1,[rUart,#UART_LSR]
++ ands r1,r1,#0x20
++ beq 1b
++ mov r1,r0
++ and r1,r1,#0xff
++ str r1,[rUart,#UART_THR]
++ movs r1,r0,LSR #8
++ movne r0,r1
++ bne 1b
++ mov pc,lr //return
++
++TransmitChkSum:
++ add r9,r9,r0
++ b Transmit
++
++ .if STACKS_VALID
++// *******************************************************
++ RelocationVector 2
++// *******************************************************
++ .endif
++
++//OUT:
++//z-0 good data in r0
++//z-1 timeout, r0 is 0
++//r1 - loop cnt time remaining
++Receive:
++ mov r1,#RECEIVE_LOOP_COUNT
++Receive1:
++1: ldr r0,[rUart,#UART_LSR]
++ ands r0,r0,#0x1
++ ldrne r0,[rUart,#UART_RBR]
++ movne pc,lr //return
++
++ subs r1,r1,#1
++ bne 1b
++ mov pc,lr //return
++
++
++
++
++//IN: r2 - symbol #
++//OUT: r1:r0 - value,
++GetRegVal:
++ cmp r2,#SYM_FP0
++ bcs GetSpecialReg
++#if DBG_R0
++ add r1,rDBG,#DBG_R0
++ ldr r0,[r1,r2,LSL #2]
++#else
++ ldr r0,[rDBG,r2,LSL #2]
++#endif
++ mov r1,#0
++ mov pc,lr
++
++// ********************************************************************
++// ********************************************************************
++// ********************************************************************
++
++
++gdb_lastSignal:
++ ldrb r6,[rDBG,#DBG_LastSignal]
++ ldrb r5,[rDBG,#DBG_Mode]
++gdb_lastSignal1:
++ ldr r0,[rUart,#UART_LCR]
++ strb r0,[rDBG,#DBG_FFUART_LCR]
++ bic r0,r0,#0x80 //make sure DLAB is clear
++ str r0,[rUart,#UART_LCR]
++
++
++1: mov r9,#0 //chksum
++ mov r0,#L1(DOLLAR)
++ bl Transmit
++// mov r0,#L1(T)
++ mov r0,#L1(S)
++ bl TransmitChkSum
++ mov r0,r6
++ bl PrintHexByteEndian
++// mov r0,#L1(F)
++// bl TransmitChkSum
++// mov r0,#L1(COLON)
++// bl TransmitChkSum
++// mov r2,#SYM_PC
++// bl GetRegVal
++// bl PrintHexEndian
++
++ mov r0,#L1(POUND)
++ bl Transmit
++ and r0,r9,#0xff
++ bl PrintHexByteEndian
++ mov r3,#0
++ mov r1,#RECEIVE_LOOP_COUNT
++10:
++ bl Receive1 //z-0 good data in r0, z-1 timeout, r0 is 0
++ moveq rNum1,#0
++ beq 12f //br if timeout
++ cmpne r6,#SIG_RESET //disable cr abort on power up
++// beq 10b //uncomment to stop <cr> from stopping
++
++ cmp r0,#L1(PLUS)
++ beq WaitForDollarSign
++ cmp r0,#L1(DOLLAR)
++ beq ReadGDB
++
++ cmp r0,#L1(MINUS)
++ beq 1b
++ tst r5,#1
++ cmpeq r0,#GDB_EXIT_CHAR
++ bne 10b //br if in GDB mode or NOT <cr>
++ mov rNum1,#1
++
++//r6 -SIG_xxx
++12:
++ bl TransmitCRLF
++ cmp r6,#SIG_DBG
++ BigMov r0,L4(D,B,G,MINUS)
++ blcs Transmit1
++
++ mov r2,#0
++ mov r3,#0
++ mov r4,#0
++ cmp r6,#SIG_RESET
++ cmpne r6,#SIG_DBG_RESET
++ BigMovEq r0,L4(R,e,s,e)
++ BigMovEq r2,L1(t)
++ cmp r6,#SIG_UNDEFINED_INSTRUCTION
++ BigMovEq r0,L4(U,n,d,e)
++ BigMovEq r2,L1(f)
++// BigMovEq r3,L1(d)
++ cmp r6,#SIG_SWI
++ BigMovEq r0,L3(S,w,i)
++ cmp r6,#SIG_PREFETCH_ABORT
++ BigMovEq r0,L4(P,r,e,f)
++ BigMovEq r2,L4(e,t,c,h)
++ cmp r6,#SIG_DATA_ABORT
++ BigMovEq r0,L4(D,a,t,a)
++ cmpne r6,#SIG_PREFETCH_ABORT
++ BigMovEq r3,L4(SPACE,A,b,o)
++ BigMovEq r4,L2(r,t)
++ cmp r6,#SIG_UNUSED
++ BigMovEq r0,L4(U,n,u,s)
++ BigMovEq r2,L2(e,d)
++ cmp r6,#SIG_IRQ
++ BigMovEq r0,L3(I,r,q)
++ cmp r6,#SIG_FIQ
++ BigMovEq r0,L3(F,i,q)
++ cmp r6,#SIG_DBG_INSTRUCTION_BKPT
++ BigMovEq r0,L4(I,n,s,t)
++ BigMovEq r2,L4(SPACE,B,r,k)
++ cmp r6,#SIG_DBG_DATA_BKPT
++ BigMovEq r0,L4(D,a,t,a)
++ BigMovEq r2,L4(SPACE,B,r,k)
++ cmp r6,#SIG_DBG_BKPT_SOFTWARE
++ BigMovEq r0,L4(B,k,p,t)
++ cmp r6,#SIG_DBG_EXTERNAL
++ BigMovEq r0,L4(E,x,t,e)
++ BigMovEq r2,L4(r,n,a,l)
++ cmp r6,#SIG_DBG_VECTOR_TRAP
++ BigMovEq r0,L4(V,e,c,t)
++ BigMovEq r2,L4(o,r,SPACE,T)
++ BigMovEq r3,L3(r,a,p)
++ cmp r6,#SIG_DBG_TRACE_BUFFER_FULL
++ BigMovEq r0,L4(T,r,a,c)
++ BigMovEq r2,L4(e,SPACE,F,u)
++ BigMovEq r3,L2(l,l)
++ cmp r6,#SIG_DBG_RESERVED
++ BigMovEq r0,L4(R,e,s,e)
++ BigMovEq r2,L4(r,v,e,d)
++
++ bl Transmit1
++ movs r0,r2
++ blne Transmit1
++ movs r0,r3
++ blne Transmit1
++ movs r0,r4
++ blne Transmit1
++
++ bl TransmitSPACE
++ mov r2,#SYM_PC
++ bl GetRegVal
++ bl PrintHex
++// bl TransmitSPACE
++ bl TransmitCRLF
++
++ rsbs r0,pc,#0x800
++ BigMov r0,FLASH_READ_CMD
++
++#if (PLATFORM_TYPE==NEONB)
++ BigMov r1,VIRTUAL_CS1 //remember, although instruction fetches are physical, data are still virtual
++#else
++ BigMov r1,VIRTUAL_CS0 //remember, although instruction fetches are physical, data are still virtual
++#endif
++ cmphs rUart,#0x41000000
++ strhs r0,[r1] //if (pc is in minicache) & (rUart is in virtual memory) then
++ //make sure flash is in read mode, we are almost off the minicache
++
++#if (PLATFORM_TYPE==NEONB)
++ adr lr,AfterPCPrint
++ add r1,r1,lr //virtual address of AfterPCPrint if in Linux for data fetch
++ cmp lr,#0x800
++ BigOrr2Eq lr,FLASH_BASE_ADDRESS //if in low part of CS0 flash, try CS1 flash
++ BigMov r0,0xe3a00055 //instruction mov r0,#55
++ cmp rUart,#0x41000000
++ movlo r1,lr //use physical address of AfterPCPrint for data fetch
++ ldr r2,[r1]
++ cmp r2,r0
++ moveq pc,lr //br if CS1 valid
++ b AfterPCPrint_error
++#else
++ b AfterPCPrint1
++#endif
++
++// ******************************************************************************************
++//A MAIN goal is for all the code above this point to fit into the 2k mini instruction cache
++//So that if difficult errors occur and the flash isn't functioning properly, we can
++//at least get the PC printed out before a crash.
++// ******************************************************************************************
++
++
++//IN: r2 - symbol #, z-1 if SYM_FP0
++//OUT: r1:r0 - value,
++GetSpecialReg:
++ bne 2f
++//MRA{<cond>} <RdLo>,<RdHi>,acc0
++ mra r0,r1,acc0
++ mov pc,lr
++
++ .if STACKS_VALID
++ .else
++//Must keep this aligned at 0x800 if Bal
++ mac_AfterPCPrint 1
++ .endif
++
++2: cmp r2,#SYM_FSR
++ CP15_FSR mrceq,r0
++ cmp r2,#SYM_FAR
++ CP15_FAR mrceq,r0
++ cmp r2,#SYM_DCSR
++ CP14_DCSR mrceq,r0
++ cmp r2,#SYM_TTBR
++ CP15_TTBR mrceq,r0
++ cmp r2,#SYM_CTRL
++ CP15_CONTROL mrceq,r0
++ mov r1,#0
++ mov pc,lr
++
++//out: c-1 means hex char, r0 - character read, r1 - 0:15 if r0 is a hex character
++ReadHex:
++1: ldr r0,[rUart,#UART_LSR]
++ ands r0,r0,#0x1
++ ldrne r0,[rUart,#UART_RBR]
++ beq 1b //br on timeout
++ rsbs r1,r0,#L1(9) //reverse subtract
++ subcss r1,r0,#L1(0)
++ movcs pc,lr
++
++ rsbs r1,r0,#L1(f) //reverse subtract
++ subcss r1,r0,#L1(a)
++ addcs r1,r1,#10
++
++ movcs pc,lr
++
++ rsbs r1,r0,#L1(F) //reverse subtract
++ subcss r1,r0,#L1(A)
++ addcs r1,r1,#10
++ mov pc,lr
++
++ .if STACKS_VALID
++//Must keep this aligned at 0x800 if Bal
++ mac_AfterPCPrint 0
++ .endif
++
++
++//r2:r1:r0 value to print, r9 - chksum
++PrintHexEndian12:
++ .if 1
++ orr r3,r0,r1
++ orrs r3,r3,r2
++ bne 1f
++ mov r3,lr
++ mov r0,#L1(0)
++ bl TransmitChkSum
++ mov r0,#L1(ASTERISK)
++ bl TransmitChkSum
++ mov r0,#29+24-1
++ mov lr,r3
++ b TransmitChkSum
++ .endif
++1:
++#if LITTLE_ENDIAN
++ mov r7,lr
++ mov r5,r1
++ mov r6,r2
++ bl PrintHexEndian //r0
++ mov r0,r5
++ bl PrintHexEndian //r1
++ mov r0,r6
++ mov lr,r7
++ b PrintHexEndian //r2
++
++#else
++ mov r7,lr
++ mov r5,r0
++ mov r6,r1
++ mov r0,r2
++ bl PrintHexEndian //r2
++ mov r0,r6
++ bl PrintHexEndian //r1
++ mov r0,r5
++ mov lr,r7
++ b PrintHexEndian //r0
++#endif
++
++
++MainInitializationCode:
++ cmp pc,#MEM_START
++ biclo sp,pc,#FLASH_BASE_ADDRESS
++ rsblos sp,sp,#0x4000
++ movlo r1,#0
++ blo InitializeCont2 //br if not ram and not from reset vector
++
++//pc - 0-0x4000, 0x04000000-0x04004000, 0xa000000-0xffffffff
++ InitCS0_CS1 r0,sp
++ InitGPIO r0,sp
++
++#if (PLATFORM_TYPE==NEONB)
++ adr lr,AfterPCPrint
++ cmp lr,#0x800
++ bne InitializeCont1
++ BigOrr2 lr,FLASH_BASE_ADDRESS //if in low part of CS0 flash, try CS1 flash
++ BigMov r0,0xe3a00055 //instruction mov r0,#55
++ ldr r2,[lr]
++ cmp r2,r0
++ addeq pc,lr,#InitializeCont-AfterPCPrint //br if CS1 valid
++#endif
++ b InitializeCont1
++
++//OUT: r0,r2 value, r7 trashed
++ReadHexEndian:
++ mov r3,lr
++ ReadHexE r2,r7
++ mov r0,r2
++ mov pc,r3
++
++
++//OUT: r2:r1:r0 value
++ReadHexEndian12:
++ mov r3,lr
++
++#if LITTLE_ENDIAN
++ ReadHexE r4,r7
++ ReadHexE r5,r7
++ ReadHexE r2,r7
++ mov r0,r4
++ mov r1,r5
++#else
++ ReadHexE r2,r7
++ ReadHexE r5,r7
++ ReadHexE r4,r7
++ mov r0,r4
++ mov r1,r5
++#endif
++ mov pc,r3
++
++
++
++ReadGDB:
++ mov r8,#0
++ mov r9,#0
++ mov rGdbNum3,#0
++ mov rGdbChkSum,#0
++1: bl Receive
++ beq 1b //br on timeout
++ cmp r0,#L1(G)
++ beq gdb_G
++// cmp r0,#L1(q)
++// beq gdb_q
++ mov rGdbCmd,r0 //r5 - command being requested
++ add rGdbChkSum,rGdbChkSum,r0 //update checksum
++ bl GetNumber
++ mov r6,r2
++ mov r7,r0
++ cmp r0,#L1(POUND)
++ beq 2f
++ cmp rGdbCmd,#L1(P)
++ beq gdb_P
++// cmp r0,#L1(COMMA)
++// cmpne r0,#L1(SEMICOLON)
++// cmpne r0,#L1(COLON)
++// cmpne r0,#L1(EQUAL)
++ bl GetNumber
++ mov r8,r2
++ mov r9,r0
++ cmp r0,#L1(POUND)
++ beq 2f
++ cmp rGdbCmd,#L1(M)
++ beq gdb_M
++ cmp rGdbCmd,#L1(X)
++ beq gdb_X
++
++ bl GetNumber
++ mov rGdbNum3,r2
++ cmp r0,#L1(POUND)
++ bne WaitForPound
++
++//# found, check chksum
++2: bl ReadChksum
++ and rGdbChkSum,rGdbChkSum,#0xff
++ cmp rGdbChkSum,r2
++ bne CheckSumError
++ mov r0,#L1(PLUS)
++ bl Transmit
++
++ cmp rGdbCmd,#L1(g)
++ beq gdb_g
++ cmp rGdbCmd,#L1(p)
++ beq gdb_p
++ cmp rGdbCmd,#L1(m)
++ beq gdb_m
++ cmp rGdbCmd,#L1(c)
++ beq gdb_c
++ cmp rGdbCmd,#L1(C)
++ beq gdb_C
++ cmp rGdbCmd,#L1(s)
++ beq gdb_s
++ cmp rGdbCmd,#L1(S)
++ beq gdb_S
++ cmp rGdbCmd,#L1(z)
++ beq gdb_z
++ cmp rGdbCmd,#L1(Z)
++ beq gdb_Z
++ cmp rGdbCmd,#L1(t)
++ beq gdb_t
++ cmp rGdbCmd,#L1(QUESTION_MARK)
++ beq gdb_lastSignal
++ cmp rGdbCmd,#L1(D)
++ beq gdb_D
++//this is an unimplemented command
++UnImplemented:
++ BigMov r0,L4(DOLLAR,POUND,0,0)
++ bl Transmit1
++ b WaitForDollarSign
++
++
++SendError01:
++ mov r9,#0 //chksum
++ mov r0,#L1(DOLLAR)
++ bl Transmit
++ mov r0,#L1(E)
++ bl TransmitChkSum
++ mov r0,#L1(0)
++ bl TransmitChkSum
++ mov r0,#L1(1)
++ bl TransmitChkSum
++ sub r5,pc,#.+8-SendError01
++ b FinishPacket
++
++
++SendOK:
++ mov r9,#0 //chksum
++ mov r0,#L1(DOLLAR)
++ bl Transmit
++ mov r0,#L1(O)
++ bl TransmitChkSum
++ mov r0,#L1(K)
++ bl TransmitChkSum
++ sub r5,pc,#.+8-SendOK
++ b FinishPacket
++
++CheckSumError:
++ mov r0,#L1(MINUS)
++ bl Transmit
++WaitForDollarSign:
++11: bl GetNumber //$ will branch to ReadGDB
++ b 11b
++WaitForPound:
++11: bl GetNumber
++ cmp r0,#L1(POUND)
++ bne 11b
++ bl ReadChksum
++ and rGdbChkSum,rGdbChkSum,#0xff
++ cmp rGdbChkSum,r2
++ bne CheckSumError
++ mov r0,#L1(PLUS)
++ bl Transmit
++ b UnImplemented
++
++
++
++FinishPacket:
++ mov r0,#L1(POUND)
++ bl Transmit
++ and r0,r9,#0xff
++ bl PrintHexByte
++10: mov r2,#5
++11: bl ReadHex
++ cmp r0,#L1(DOLLAR)
++ beq ReadGDB
++ cmp r0,#L1(PLUS)
++ beq WaitForDollarSign
++ cmp r0,#L1(MINUS)
++
++
++ moveq pc,r5 //retransmit packet
++ cmp r0,#GDB_EXIT_CHAR
++ bne 10b
++ subs r2,r2,#1
++ beq Prompt
++ b 11b
++
++ .if 0
++gdb_q:
++ mov r2,#0
++ mov r3,#0
++1: bl ReadHex
++ cmp r0,#L1(DOLLAR)
++ beq ReadGDB
++ cmp r0,#GDB_EXIT_CHAR
++ beq Prompt
++ cmp r0,#L1(POUND)
++ beq 2f
++ add rGdbChkSum,rGdbChkSum,r0 //update checksum
++ mov r1,r2,LSR #24
++ orr r3,r1,r3,LSL #8
++ orr r2,r0,r2,LSL #8
++ b 1b
++2:
++ bl ReadChksum
++ and rGdbChkSum,rGdbChkSum,#0xff
++ cmp rGdbChkSum,r2
++ bne CheckSumError
++ mov r0,#L1(PLUS)
++ bl Transmit
++ b UnImplemented
++ .endif
++
++
++//Detach command - gdb is exiting
++gdb_D:
++//clear break/watch points
++ b Prompt
++
++//r6 - addr, r8 - PP, rGdbNum3 - mm
++gdb_t:
++ b UnImplemented
++
++
++//read general registers
++gdb_g:
++ mov r9,#0 //chksum
++ mov r0,#L1(DOLLAR)
++ bl Transmit
++ mov r8,#0
++1: mov r2,r8
++ bl GetRegVal
++ bl PrintHexEndian
++ add r8,r8,#1
++ cmp r8,#SYM_PC+1
++ bne 1b
++
++ mov r2,#SYM_FP0
++ bl GetRegVal
++ mov r8,#0
++2: mov r2,#0
++ bl PrintHexEndian12 //fp0-7
++ mov r0,#0
++ mov r1,#0
++ add r8,r8,#1
++ cmp r8,#8
++ bne 2b
++
++ bl PrintHexEndian //fps
++
++ mov r2,#SYM_CPSR
++ bl GetRegVal
++ bl PrintHexEndian //cpsr
++
++ sub r5,pc,#.+8-gdb_g
++ b FinishPacket
++
++
++//Read general register
++//r6 - reg #
++gdb_p:
++ mov r9,#0 //chksum
++ mov r0,#L1(DOLLAR)
++ bl Transmit
++ mov r2,r6
++ cmp r6,#SYM_PC+1
++ bcs 2f
++
++1: bl GetRegVal
++3: bl PrintHexEndian
++4: sub r5,pc,#.+8-gdb_p
++ b FinishPacket
++2: cmp r6,#25
++ mov r2,#SYM_CPSR
++ beq 1b
++ cmp r6,#24 //fps
++ mov r0,#0
++ beq 3b
++ cmp r6,#16 //fp0
++ mov r0,#0
++ mov r1,#0
++ mov r2,#SYM_FP0
++ mov rGdbNum3,r6
++ bleq GetRegVal
++ mov r2,#0
++ bl PrintHexEndian12 //fp0-7
++ mov r6,rGdbNum3
++ b 4b
++
++//read memory
++//r6 - addr, r8 - length
++gdb_m:
++ mov r9,#0 //chksum
++ mov r0,#L1(DOLLAR)
++ bl Transmit
++ mov r5,r6
++ movs r7,r8
++ beq 4f
++1:
++ tst r5,#3
++ bne 3f
++ cmp r7,#4
++ bcc 3f
++ ldr r0,[r5],#4
++ bl PrintHexEndian
++ subs r7,r7,#4
++ bne 1b
++ b 4f
++
++3: ldrb r0,[r5],#1
++ bl PrintHexByteEndian
++ subs r7,r7,#1
++ bne 1b
++4: sub r5,pc,#.+8-gdb_m
++ b FinishPacket
++
++
++//continue
++//r6 - address, 0- current PC
++gdb_c:
++ mov r8,r6
++//r8 - address, 0- current PC
++gdb_C:
++ movs rNum1,r8
++ movne rValidCnt,#F_NUM1_MASK
++ moveq rValidCnt,#0
++ tst rNum1,#3
++ bne SendError01
++ mov r4,#1
++ b Go_Cmd1
++
++//step
++//r6 - address, 0- current PC
++gdb_s:
++ mov r8,r6
++//r8 - address, 0- current PC
++gdb_S:
++ movs rNum1,r8
++ movne rValidCnt,#F_NUM1_MASK
++ moveq rValidCnt,#0
++ tst rNum1,#3
++ bne SendError01
++ mov r4,#1
++ b Trace_Cmd1
++
++
++
++//watchpoints/breakpoints - remove
++//r6 - type, r8 - address
++gdb_z:
++ cmp r6,#0 //software breakpoint
++ cmpne r6,#1 //hardware breakpoint
++ bne UnImplemented
++// mov rNum1,r8 //same reg
++ bl BC_Do
++ b SendOK
++
++
++
++//watchpoints/breakpoints - insert
++gdb_Z:
++ cmp r6,#0 //software breakpoint
++ cmpne r6,#1 //hardware breakpoint
++ bne UnImplemented
++// mov rNum1,r8 //same reg
++ bl BS_Do // z-0 if r0==rNum1, breakpoint was already set
++ cmpne r0,rNum1
++ beq SendOK
++ b SendError01
++
++
++//gdb routines below have not done checksum yet
++//write general registers
++gdb_G:
++ mov r8,#0
++1: bl ReadHexEndian
++ mov r2,r8
++ mov r1,#0
++ bl StoreRegVal //r2 - symbol #, r1:r0 - value
++ add r8,r8,#1
++ cmp r8,#SYM_PC+1
++ bne 1b
++
++ bl ReadHexEndian12
++ mov r2,#SYM_FP0
++ bl StoreRegVal //r2 - symbol #, r1:r0 - value
++
++ mov r8,#1
++2: bl ReadHexEndian12
++ add r8,r8,#1
++ cmp r8,#8
++ bne 2b
++
++ bl ReadHexEndian //fps
++ bl ReadHexEndian //cpsr
++
++ mov r2,#SYM_CPSR
++ bl StoreRegVal //r2 - symbol #, r1:r0 - value
++FinishWritePacket:
++ bl FinishWriteP
++ b SendOK
++FinishWriteP:
++ mov r4,lr
++ bl ReadHex
++ cmp r0,#L1(POUND)
++ bne CheckSumError
++ bl ReadChksum
++ and rGdbChkSum,rGdbChkSum,#0xff
++ cmp rGdbChkSum,r2
++ bne CheckSumError
++ mov r0,#L1(PLUS)
++ bl Transmit
++ mov pc,r4
++
++
++
++
++//write general register
++//r6 - reg#
++gdb_P:
++ mov r8,r6
++ cmp r6,#SYM_PC+1
++ bcs 2f
++1:
++ bl ReadHexEndian
++4: mov r6,r0
++ mov r7,r1
++ bl FinishWriteP
++ mov r0,r6
++ mov r1,r7
++ mov r2,r8
++ bl StoreRegVal //r2 - symbol #, r1:r0 - value
++ b SendOK
++
++3: bl ReadHexEndian
++ b FinishWritePacket
++
++2: cmp r6,#25
++ mov r8,#SYM_CPSR
++ beq 1b
++ cmp r6,#24 //fps
++ beq 3b
++ bl ReadHexEndian12
++ cmp r6,#16 //fp0
++ bne FinishWritePacket
++ mov r8,#SYM_FP0
++ b 4b
++
++
++//write memory
++//r6 - addr, r8 - length
++gdb_M:
++ movs r8,r8
++ beq FinishWritePacket
++
++1: tst r6,#3
++ beq 3f
++2: bl ReadHexByteEndian
++ strb r2,[r6],#1
++ subs r8,r8,#1
++ bne 1b
++ b FinishWritePacket
++3: cmp r8,#4
++ bcc 2b
++ bl ReadHexEndian
++ str r2,[r6],#4
++ subs r8,r8,#4
++ bne 3b
++ b FinishWritePacket
++
++
++//write memory binary with 0x7d, "$","#", escaped with 0x7d
++//r6 - addr, r8 - length
++gdb_X:
++ movs r8,r8
++ beq FinishWritePacket
++
++1: tst r6,#3
++ beq 3f
++2: bl ReadByteEndian
++ strb r0,[r6],#1
++ subs r8,r8,#1
++ bne 1b
++ b FinishWritePacket
++3: cmp r8,#4
++ bcc 2b
++ bl ReadEndian
++ str r0,[r6],#4
++ subs r8,r8,#4
++ bne 3b
++ b FinishWritePacket
++
++
++
++ReadEndian:
++ mov r4,lr
++ mov r5,#4
++1: bl ReadByteEndian
++
++#if LITTLE_ENDIAN
++ mov r0,r0,LSL #24
++ orr r2,r0,r2,LSR #8
++#else
++ orr r2,r0,r2,LSL #8
++#endif
++
++ subs r5,r5,#1
++ bne 1b
++ mov r0,r2
++ mov pc,r4
++
++
++ReadByteEndian:
++ mov r3,lr
++ bl ReadHex
++ add rGdbChkSum,rGdbChkSum,r0 //update checksum
++ cmp r0,#0x7d
++ beq 1f
++ cmp r0,#L1(DOLLAR)
++ cmpne r0,#L1(POUND)
++ beq CheckSumError
++ mov pc,r3
++1:
++ bl ReadHex
++ add rGdbChkSum,rGdbChkSum,r0 //update checksum
++ mov pc,r3
++
++
++ReadHexByteEndian:
++ mov r3,lr
++ bl ReadHex
++ bcc CheckSumError
++ add rGdbChkSum,rGdbChkSum,r0 //update checksum
++ mov r2,r1
++ bl ReadHex
++ bcc CheckSumError
++ add rGdbChkSum,rGdbChkSum,r0 //update checksum
++ add r2,r1,r2,LSL #4
++ mov pc,r3
++
++//OUT: r2 - checksum
++ReadChksum:
++ mov r3,lr
++ bl ReadHex
++ movcs r2,r1
++ blcs ReadHex
++ addcs r2,r1,r2,LSL #4
++ mvncc r2,#0
++ mov pc,r3
++
++//out: r0 exit character, r2 - number, rGdbChkSum - updated
++GetNumber:
++ mov r2,#0
++ mov r3,lr
++1: bl ReadHex
++ bcc 3f
++ add rGdbChkSum,rGdbChkSum,r0 //update checksum
++2: tst r2,#0xf0000000
++ movne pc,r3 //return on number overflow
++ add r2,r1,r2,LSL #4
++ b 1b
++3: cmp r0,#L1(DOLLAR)
++ beq ReadGDB
++ cmp r0,#GDB_EXIT_CHAR
++ beq Prompt
++ cmp r0,#L1(POUND)
++ addne rGdbChkSum,rGdbChkSum,r0 //update checksum
++ mov pc,r3
++
++// *****************************************************************
++#if (PLATFORM_TYPE==NEONB)
++AfterPCPrint_error:
++ bl TransmitCRLF
++ BigMov r0,L4(F,l,a,s)
++ bl Transmit1
++ BigMov r0,L4(h,SPACE,i,s)
++ bl Transmit1
++ BigMov r0,L4(SPACE,i,n,v)
++ bl Transmit1
++ BigMov r0,L4(a,l,i,d)
++ bl Transmit1
++ bl TransmitCRLF
++#endif
++AfterPCPrint1:
++ mov rPrevNum1,#MEM_START
++ movs rNum1,rNum1
++ tsteq r6,#7 //make sure it's a SIG_RESET, or SIG_DBG_RESET, and timeout
++ bne 1f
++ BigBic r0,pc,FLASH_BASE_ADDRESS
++ cmp r0,#0x4000
++ blo Gl_Cmd //auto start program if running in flash
++1:
++ b R_Cmd
++// b Prompt2
++
++
++Invalid:
++ bl TransmitCRLF
++ BigMov r0,L4(i,n,v,a)
++ bl Transmit1
++ BigMov r0,L3(l,i,d)
++ bl Transmit1
++ b Prompt
++Prompt1:
++ mov rPrevNum1,#MEM_START
++Prompt:
++1: bl TransmitCRLF
++Prompt2:
++ mov r0,#L1(PERIOD)
++ bl Transmit
++ bl TransmitSPACE
++ mov rFieldStart,#1
++ bl ReadCommand
++
++ mov r2,r0 //save exit character
++ cmp r0,#0x0d
++ blne Transmit
++ bl TransmitCRLF
++
++ cmp rCommand,#0
++ bne 2f
++ cmp r2,#0x0d
++ beq 1b
++ cmp r2,#L1(PLUS)
++ addeq rPrevNum1,rPrevNum1,#4
++ beq Examine_Cmd
++ cmp r2,#L1(MINUS)
++ subeq rPrevNum1,rPrevNum1,#4
++ beq Examine_Cmd
++ b 1b
++
++2: tst rSymbol,#F_NUM1_MASK
++ mov r0,rNum1
++ blne GetSymbolNumber
++ bne Invalid
++ mov rNum1,r0
++
++ tst rSymbol,#F_NUM2_MASK
++ mov r0,rNum2
++ blne GetSymbolNumber
++ bne Invalid
++ mov rNum2,r0
++
++ cmp rCommand,#L1(E)
++ beq Examine_Cmd
++ cmp rCommand,#L1(D)
++ beq Deposit_Cmd
++ cmp rCommand,#L1(G)
++ beq Go_Cmd
++ cmp rCommand,#L1(R)
++ beq R_Cmd
++ cmp rCommand,#L1(T)
++ beq Trace_Cmd
++ BigMov r0,C2(D,L)
++ cmp rCommand,r0
++ beq Download_Cmd
++ cmp rCommand,#L1(QUESTION_MARK)
++ beq Help_Cmd
++
++ mov r0,r0,LSL #8
++ orr r0,r0,#L1(W)
++ cmp rCommand,r0
++ beq Download_Wireless_Cmd
++
++ BigMov r0,C4(S,S,I,D)
++ cmp rCommand,r0
++ beq SSID_Cmd
++
++ BigMov r0,C3(M,A,C)
++ cmp rCommand,r0
++ beq MAC_Cmd
++
++ BigMov r0,C4(B,U,R,N)
++ cmp rCommand,r0
++ beq Burn_Cmd
++
++ BigMov r0,C2(B,B)
++ cmp rCommand,r0
++ beq Burn2_Cmd
++
++ BigMov r0,C4(B,A,L,L) //Burn all of flash, erase end.
++ cmp rCommand,r0
++ beq BurnAll_Cmd
++
++ cmp rCommand,#L1(V)
++ beq Verify_Cmd
++
++ BigMov r0,C2(V,V)
++ cmp rCommand,r0
++ beq Verify2_Cmd
++
++ BigMov r0,C2(G,L)
++ cmp rCommand,r0
++ beq Gl_Cmd //go linux!!
++
++ BigEor2 r0,C2(G,L)^C2(G,G)
++ cmp rCommand,r0
++ beq GG_Cmd //go without cache invalidate
++
++ BigMov r0,C2(T,T)
++ cmp rCommand,r0
++ beq TT_Cmd //Trace without cache invalidate
++
++ BigMov r0,C2(B,S)
++ cmp rCommand,r0
++ beq BS_Cmd
++
++ BigEor2 r0,C2(B,S)^C2(B,E)
++ cmp rCommand,r0
++ beq BE_Cmd
++
++ BigEor2 r0,C2(B,E)^C2(B,C)
++ cmp rCommand,r0
++ beq BC_Cmd
++
++ BigEor2 r0,C2(B,C)^C2(W,C)
++ cmp rCommand,r0
++ beq WC_Cmd
++
++ BigEor2 r0,C2(W,C)^C2(W,W)
++ cmp rCommand,r0
++ beq WW_Cmd
++
++ BigEor2 r0,C2(W,W)^C2(W,R)
++ cmp rCommand,r0
++ beq WR_Cmd
++
++ mov r0,r0,LSL #8
++ orr r0,r0,#L1(W)
++ cmp rCommand,r0
++ beq WRW_Cmd
++
++ BigMov r0,C3(M,M,U)
++ cmp rCommand,r0
++ beq MMU_Cmd
++// mov r0,rCommand
++// bl PrintHex
++ b Invalid
++
++//IN: rFieldStart - starting field (this is a blank counting field)
++//OUT:
++ReadCommand:
++ mov r3,lr
++ mov rSymbol,#0
++ mov rField,rFieldStart
++ mov rValidCnt,#0 //low nibble: # of blanks before command
++ //next: # of chars in command
++ //next: # of blanks
++ //next: # of hex digits in num1
++ //next: # of blanks
++ //next: # of hex digits in num2
++ mov rCommand,#0 //command
++ mov rNum1,#0 //1st number
++ mov rNum2,#0 //2nd number
++
++1: bl Receive
++ beq 1b //br on timeout
++ cmp r0,#L1(DOLLAR)
++ beq ReadGDB
++ cmp r0,#L1(PLUS)
++ cmpne r0,#L1(MINUS)
++ cmpne r0,#L1(AT_SIGN)
++ cmpeq rValidCnt,#0
++ cmpne r0,#0x0d
++ moveq pc,r3 //return on -,+, 1st on line or <cr>
++
++ cmp r0,#L1(SPACE)
++ bne 2f
++ bl Transmit
++ tst rValidCnt,#0x80000000
++ eorne rValidCnt,rValidCnt,#0x80000000 //clear bit 31 to mark as blank field
++ movne rField,rField,LSL #F_INC
++//now we are in a counting blanks field
++ rsb r2,rField,rField,LSL #F_INC //get a field mask
++ and r1,rValidCnt,r2
++ cmp r1,r2
++ beq Invalid //br if field is full
++ add rValidCnt,rValidCnt,rField
++ b 1b
++2:
++ cmp r0,#0x08 //Backspace
++ cmpne r0,#0x7f //del or Backspace
++ bne 4f
++ cmp rValidCnt,#0
++ beq 1b //br if nothing to remove
++ BigMov r0,L3(BACKSPACE,SPACE,BACKSPACE)
++ bl Transmit1
++ sub rValidCnt,rValidCnt,rField
++ mov r0,#4
++ tst rSymbol,rField
++ movne r0,#8
++ cmp rField,#F_COMMAND
++ moveq rCommand,rCommand,LSR #8
++ cmp rField,#F_NUM1
++ moveq rNum1,rNum1,LSR r0
++ cmp rField,#F_NUM2
++ moveq rNum2,rNum2,LSR r0
++
++3: rsb r0,rField,rField,LSL #F_INC //get a field mask
++ tst rValidCnt,r0
++ bne 1b //br if still more in this field
++ bic rSymbol,rSymbol,rField
++ cmp rField,rFieldStart
++ beq 1b
++//move back to lower field
++ mov rField,rField,LSR #F_INC
++ eors rValidCnt,rValidCnt,#0x80000000
++ b 3b
++
++4: bl Transmit
++ tst rValidCnt,#0x80000000
++ orreq rValidCnt,rValidCnt,#0x80000000 //set bit 31 to mark as data field
++ moveq rField,rField,LSL #F_INC
++ cmp rField,#F_UNDEF
++ beq Invalid
++//now we are in a data field
++ rsbs r1,rField,#F_COMMAND
++ rsbges r1,r0,#L1(9) //reverse subtract
++ subges r1,r0,#L1(0)
++ movge rField,rField,LSL #F_INC+F_INC //advance to number field if in range "0"-"9"
++
++ rsb r2,rField,rField,LSL #F_INC //get a field mask
++ and r1,rValidCnt,r2
++ cmp r1,r2
++ beq Invalid //field is full
++ add rValidCnt,rValidCnt,rField
++
++ rsbs r1,r0,#L1(z) //reverse subtract
++ subges r1,r0,#L1(a)
++ andge r0,r0,#0xdf //convert to uppercase if was "a"-"z"
++ cmp rField,#F_COMMAND
++ bne 6f
++ tst rCommand,#0xff000000
++ bne Invalid
++ add rCommand,r0,rCommand,LSL #8
++ b 1b
++
++6: tst rSymbol,rField
++ bne 15f
++ rsbs r1,r0,#L1(9) //reverse subtract
++ subges r1,r0,#L1(0)
++ bge 5f
++ rsbs r1,r0,#L1(F) //reverse subtract
++ subges r1,r0,#L1(A)
++ add r1,r1,#10
++ bge 5f
++ orr rSymbol,rSymbol,rField
++//now if number started with "A"-"F", convert back to ascii
++
++ cmp rField,#F_NUM1
++ mov r1,rValidCnt,LSR #F_NUM1_BIT //# of nibbles +1 in rNum
++ movne r1,rValidCnt,LSR #F_NUM2_BIT
++ and r1,r1,#((1<<F_INC)-1)
++
++ subs r1,r1,#1 //# of nibbles in rNum
++ beq 15f
++
++
++
++ cmp r1,#3
++ bcs Invalid //br if too many leading hex characters
++ mov r1,r1,LSL #2 //# of bits valid in rNum
++ cmp rField,#F_NUM1
++ rsb lr,r1,#24
++ moveq r2,rNum1,ROR r1
++ movne r2,rNum2,ROR r1
++ orr r2,r2,r0,LSL lr //save r0 character
++
++ mov lr,#0
++26: mov r0,r2,LSR #28
++ cmp r0,#10
++ addcs r0,r0,#L1(A)-10
++ addcc r0,r0,#L1(0)
++ orr lr,r0,lr,LSL #8
++ mov r2,r2,LSL #4
++ subs r1,r1,#4
++ bne 26b
++
++ cmp rField,#F_NUM1
++ mov r0,r2,LSR #24 //restore r0
++ moveq rNum1,lr
++ movne rNum2,lr
++ b 15f
++
++5:
++ cmp rField,#F_NUM1
++ bne 7f
++ tst rNum1,#0xf0000000
++ bne Invalid
++ add rNum1,r1,rNum1,LSL #4
++ b 1b
++7: tst rNum2,#0xf0000000
++ bne Invalid
++ add rNum2,r1,rNum2,LSL #4
++ b 1b
++
++15:
++ cmp rField,#F_NUM1
++ bne 17f
++ tst rNum1,#0xff000000
++ bne Invalid
++ add rNum1,r0,rNum1,LSL #8
++ b 1b
++17: tst rNum2,#0xff000000
++ bne Invalid
++ add rNum2,r0,rNum2,LSL #8
++ b 1b
++
++//rNum1 - 0 off, 1 on
++MMU_Cmd:
++ bl cache_clean_invalidate_all
++ tst rNum1,#1
++//now enable/disable MMU, Data Cache
++ CP15_CONTROL mrc,r1 //get the control register
++ biceq r1,r1,#0x5
++ orrne r1,r1,#0x5
++ CP15_CONTROL mcr,r1 //set the control register
++ CPWAIT r0
++ BigMov rUart,UART_BASE //this is right if MMU is off
++ blne GetUartAddress //if mmu is on
++ b Prompt
++
++// ********************************************************************
++// ********************************************************************
++// ********************************************************************
++// r3 - -1 : Trace, 0 : Go
++// r4 - 0 : normal, 1 : mark gdb mode
++// rNum2 - 0 : invalidate cache, 1 : don't invalidate cache
++//go without cache invalidate
++GG_Cmd:
++ mov r4,#0
++ mov r3,#0
++ mov rNum2,#1
++ b Go2
++Go_Cmd:
++ mov r4,#0
++Go_Cmd1:
++ mov r3,#0
++Go1:
++ bl cache_clean_invalidate_all
++ .if 0
++ mov rNum2,#0
++ .else
++ mov rNum2,#1
++ .endif
++Go2:
++
++ ldrb r2,[rDBG,#DBG_Mode]
++ and r2,r2,#0xfe
++ orr r2,r2,r4
++ strb r2,[rDBG,#DBG_Mode] //mark gdb mode
++
++ tst rValidCnt,#F_NUM1_MASK
++ strne rNum1,[rDBG,#DBG_PC] //return pc
++ ldreq rNum1,[rDBG,#DBG_PC] //return pc
++ orr r0,rNum1,#1
++ CP15_IBCR0 mrc,rBCR0
++ CP15_IBCR1 mrc,rBCR1
++ cmp r0,rBCR0
++ ldr r7,[rDBG,#DBG_CPSR]
++ mov r2,rBCR0 //save temporary
++ moveq rBCR0,#0
++ cmp r0,rBCR1
++ moveq rBCR1,#0
++
++ cmpne r0,r2
++ streq r0,[rDBG,#DBG_TRACE] //this is the current instruction breakpoint value
++ beq 4f //br if a bkpt matches current instruction
++ cmp r3,#0
++ str r3,[rDBG,#DBG_TRACE] //-1 : Trace, 0 : Go
++ beq 6f
++
++
++4: bl CalcNextPc //IN: rNum1: current PC, r7- cpsr; OUT: rNum1: next PC
++ tst r0,#1
++ bne Invalid
++ orr r1,r0,#1
++
++ tst rBCR0,#1
++ moveq rBCR0,r1
++ beq 5f
++ tst rBCR1,#1
++ moveq rBCR1,r1
++ strne rBCR0,[rDBG,#DBG_TRACE] //need to steal this breakpoint momentarily
++ movne rBCR0,r1
++5:
++ CP15_IBCR0 mcr,rBCR0
++ CP15_IBCR1 mcr,rBCR1
++
++6:
++ ldrb r0,[rDBG,#DBG_FFUART_LCR]
++ str r0,[rUart,#UART_LCR] //restore value
++ add r0,rDBG,#DBG_R2
++
++ bl ClearStickyAbort
++ BigMov r1,UART_BASE //physical address
++ movs rNum2,rNum2,LSR #1 //carry flag 1 : don't invalidate cache
++ teq r1,rUart //this lets me know if identity mapping is used, or MMU is off, C & V are not affected by instruction
++
++ ldmia r0,{r2,r3,r4,r5,r6,r7,r8,r9,sl,fp,ip,sp,lr}
++//z-0 return indirect, setup stack to contain real return address
++ ldrne r1,[r0,#DBG_PC-DBG_R2]
++ strne r1,[sp,#-4]!
++
++ ldr r1,[r0,#DBG_HCPSR-DBG_R2]
++ orr r1,r1,#0xc0 //set I, F
++ msr cpsr_c,r1
++// ldr r1,[r0,#DBG_CPSR-DBG_R2] //don't allow changing return mode for now... to messy
++// msr spsr,r1
++ CP15_CF_DRAIN mcr,r1 //make sure data cache write buffers are drained
++ b InvalidateAndReturn //z-1 return direct, z-0 return indirect
++
++
++
++ClearStickyAbort:
++ CP14_DCSR mrc,r1
++ tst r1,#1<<5
++ bic r1,r1,#1<<5 //clear sticky abort bit
++ CP14_DCSR mcrne,r1
++ mov pc,lr
++TT_Cmd:
++ mov r4,#0
++ mvn r3,#0
++ mov rNum2,#1
++ b Go2
++
++Trace_Cmd:
++ mov r4,#0
++Trace_Cmd1:
++ mvn r3,#0
++ b Go1
++
++
++//IN: rNum1: current PC, r7- cpsr
++//OUT: r0: next PC
++//trashed: r1,r2,r3,r4,r6
++CalcNextPc:
++ mov r4,lr
++ bl ClearStickyAbort
++ ldr r2,[rNum1]
++ add r0,rNum1,#4
++ nop //let abort have time to signal
++ bl ClearStickyAbort
++ movne pc,r4
++//1st check to see if condition codes allow instruction to execute
++1:
++ mov r3,r2,LSR #28
++ msr CPSR_f,r7
++ add pc,pc,r3,LSL #3
++ nop
++ beq 2f //0-eq
++ mov pc,r4
++ bne 2f //1-ne
++ mov pc,r4
++ bcs 2f //2-cs
++ mov pc,r4
++ bcc 2f //3-cc
++ mov pc,r4
++ bmi 2f //4-mi
++ mov pc,r4
++ bpl 2f //5-pl
++ mov pc,r4
++ bvs 2f //6-vs
++ mov pc,r4
++ bvc 2f //7-vc
++ mov pc,r4
++ bhi 2f //8-hi
++ mov pc,r4
++ bls 2f //9-ls
++ mov pc,r4
++ bge 2f //a-ge
++ mov pc,r4
++ blt 2f //b-lt
++ mov pc,r4
++ bgt 2f //c-gt
++ mov pc,r4
++ ble 2f //d-le
++ mov pc,r4
++ b 2f //e-al
++ mov pc,r4 //just a spacer instruction, never executed
++ //f-nv
++
++ and r3,r2,#0xfe000000
++ cmp r3,#0xfa000000
++ movne pc,r4
++//BLX instruction changing into thumb mode
++ movs r3,r2,LSL #8 //mov H bit to carry flag
++ orrcs r3,r3,#1<<7
++ add r0,r0,#4
++ add r0,r0,r3,ASR #6
++ mov pc,r4
++
++
++//instruction WILL execute
++2:
++ mov r3,r2,LSR #25
++ and r3,r3,#0x7
++ and r1,r2,#0x0000f000
++ cmp r1, #0x0000f000
++ mov r1,r2,LSL #20
++ mov r1,r1,LSR #20 //r1 gets low 12 bits of r2
++ add pc,pc,r3,LSL #2
++ nop
++ b 10f
++ b 11f
++ b 12f
++ b 13f
++ b 14f
++ b 15f
++ mov pc,r4 //6
++ mov pc,r4 //7
++//nnnn 000n
++10:
++ movne pc,r4
++ and r3,r2,#0x01800000
++ cmp r3, #0x01000000
++ bne 51f
++ and r3,r2,#0x0ff00000
++ cmp r3, #0x01200000
++ andeq r3,r2,#0x000000d0
++ cmpeq r3, #0x00000010
++//B{L} <Rm> instruction -eq
++ andeq r3,r2,#0xf
++#if DBG_R0
++ addeq r0,rDBG,#DBG_R0
++ ldreq r0,[r0,r3,LSL #2]
++#else
++ ldreq r0,[rDBG,r3,LSL #2]
++#endif
++
++ biceq r0,r0,#1
++ mov pc,r4
++
++
++51: tst r2,#1<<4
++ bne 52f
++ add r0,r0,#4 //pc+8
++ bl RegShiftImmed
++ b 50f
++52:
++ tst r2,#1<<7
++ movne pc,r4 //return if LDR|STR<H|D|B|SB|SH>|MUL|MLA...
++//this is a shift by a register value
++ add r0,r0,#4 //pc+8
++ bl RegShiftReg
++ b 50f
++
++//nnnn 001n immediate
++11:
++ movne pc,r4
++ and r3,r2,#0x01800000
++ cmp r3, #0x01000000
++ moveq pc,r4 //return if TST|TEQ|CMP|CMN|MRS|MSR|SMLA.....
++ and r6,r1,#0xff
++ mov r3,r1,LSR #7
++ BIC r3,r3,#1
++ mov r1,r6,ROR r3
++ add r0,r0,#4 //pc+8
++//r1 has 2nd operand
++50:
++ mov r3,r2,LSR #16
++ and r3,r3,#0xf
++ cmp r3,#0xf
++ moveq r6,r0 //pc+8
++#if DBG_R0
++ addne r6,rDBG,#DBG_R0
++ ldrne r6,[r6,r3,LSL #2] //<Rn> - r6
++#else
++ ldrne r6,[rDBG,r3,LSL #2] //<Rn> - r6
++#endif
++
++//r6 has 1st operand
++ mov r3,r2,LSR #21
++ and r3,r3,#0xf
++ msr CPSR_f,r7
++ add pc,pc,r3,LSL #3
++ nop
++ and r0,r6,r1 //0-AND
++ mov pc,r4
++ eor r0,r6,r1 //1-EOR
++ mov pc,r4
++ sub r0,r6,r1 //2-SUB
++ mov pc,r4
++ rsb r0,r6,r1 //3-RSB
++ mov pc,r4
++ add r0,r6,r1 //4-ADD
++ mov pc,r4
++ adc r0,r6,r1 //5-ADC
++ mov pc,r4
++ sbc r0,r6,r1 //6-SBC
++ mov pc,r4
++ rsc r0,r6,r1 //7-RSC
++ mov pc,r4
++ sub r0,r0,#4 //8-TST, cannot get here
++ mov pc,r4
++ sub r0,r0,#4 //9-TEQ, cannot get here
++ mov pc,r4
++ sub r0,r0,#4 //A-CMP, cannot get here
++ mov pc,r4
++ sub r0,r0,#4 //B-CMN, cannot get here
++ mov pc,r4
++ orr r0,r6,r1 //C-ORR
++ mov pc,r4
++ mov r0,r1 //D-MOV
++ mov pc,r4
++ bic r0,r6,r1 //E-BIC
++ mov pc,r4
++ mvn r0,r1 //F-MVN
++ mov pc,r4
++
++//LDR
++12:
++13:
++ tsteq r2,#1<<22 //B bit 22 1 : Byte, 0: Word
++ movne pc,r4
++ tst r2,#1<<20 //L bit 20 1 : LDR, 0:STR
++ moveq pc,r4
++
++ add r0,r0,#4 //pc+8
++ tst r2,#1<<24 //P bit
++ moveq r1,#0
++ beq 34f
++ tst r2,#1<<25
++ beq 34f //branch if immediate12bits value is in r1
++ bl RegShiftImmed
++34:
++ mov r3,r2,LSR #16
++ and r3,r3,#0xf
++ cmp r3,#0xf
++ moveq r6,r0 //pc+8
++#if DBG_R0
++ addne r6,rDBG,#DBG_R0
++ ldrne r6,[r6,r3,LSL #2] //<Rn> - r6
++#else
++ ldrne r6,[rDBG,r3,LSL #2] //<Rn> - r6
++#endif
++
++ tst r2,#1<<23 //U bit Up/Down, Add/Sub
++ addne r6,r6,r1
++ subeq r6,r6,r1
++ ldr r0,[r6]
++ mov pc,r4
++
++
++//LDM
++14:
++ and r3,r2,#(1<<15)+(1<<20)
++ cmp r3, #(1<<15)+(1<<20)
++ movne pc,r4
++
++//LDM to PC -eq
++ add r0,r0,#4 //pc+8
++ mov r3,r2,LSR #16
++ and r3,r3,#0xf
++ cmp r3,#0xf
++ moveq r1,r0 //pc+8, should never execute
++#if DBG_R0
++ addne r1,rDBG,#DBG_R0
++ ldrne r1,[r1,r3,LSL #2] //<Rn> - r1
++#else
++ ldrne r1,[rDBG,r3,LSL #2] //<Rn> - r1
++#endif
++
++//r1 is already correct address for downward from base (U==0), included(P==0)
++ tst r2,#1<<23 //U bit
++ beq 4f
++ mov r6,r2,LSL #16
++3: movs r6,r6,LSL #1
++ addcs r1,r1,#4
++ bne 3b
++ eor r2,r2,#1<<24
++4: tst r2,#1<<24 //P bit
++ subne r1,r1,#4
++ ldr r0,[r1]
++ mov pc,r4
++
++//B{L} instruction
++15:
++ mov r3,r2,LSL #8
++ add r0,r0,#4
++ add r0,r0,r3,ASR #6
++ mov pc,r4
++
++//IN: r0 - pc+4, r2 instruction, r1 low 12 bits of instruction
++//OUT: r1 - shifted value, r2 - unchanged, r0 - pc+8
++RegShiftImmed:
++ mov r1,r1,LSR #7 //Shift_imm - r1
++ and r3,r2,#0xf
++ cmp r3,#0xf
++ moveq r6,r0 //pc+8
++#if DBG_R0
++ addne r6,rDBG,#DBG_R0
++ ldrne r6,[r6,r3,LSL #2] //<Rm> - r6
++#else
++ ldrne r6,[rDBG,r3,LSL #2] //<Rm> - r6
++#endif
++
++ tst r2,#1<<6
++ bne 32f
++ tst r2,#1<<5
++ bne 31f
++ mov r1,r6,LSL r1 //<Rm> shf Shift_imm - r1
++ mov pc,lr
++
++31: cmp r1,#0
++ movne r1,r6,LSR r1
++ mov pc,lr
++
++32: tst r2,#1<<5
++ bne 33f
++ cmp r1,#0
++ moveq r1,#32
++ mov r1,r6,ASR r1
++ mov pc,lr
++
++33: cmp r1,#0
++ movne r1,r6,ROR r1
++ movne pc,lr
++
++ msr CPSR_f,r7
++ mov r1,r6, RRX
++ mov pc,lr
++
++
++//IN: r2 instruction, r1 low 12 bits of instruction
++//OUT: r1 - shifted value, r2 - unchanged, r0 - pc+8
++RegShiftReg:
++ mov r3,r1,LSR #8
++ cmp r3,#0xf
++ moveq r1,r0 //pc+8
++#if DBG_R0
++ addne r1,rDBG,#DBG_R0
++ ldrne r1,[r1,r3,LSL #2] //<Rs> - r1
++#else
++ ldrne r1,[rDBG,r3,LSL #2] //<Rs> - r1
++#endif
++
++ and r3,r2,#0xf
++ cmp r3,#0xf
++ moveq r6,r0 //pc+8
++#if DBG_R0
++ addne r6,rDBG,#DBG_R0
++ ldrne r6,[r6,r3,LSL #2] //<Rm> - r6
++#else
++ ldrne r6,[rDBG,r3,LSL #2] //<Rm> - r6
++#endif
++ tst r2,#1<<6
++ bne 32f
++ tst r2,#1<<5
++ moveq r1,r6,LSL r1 //<Rm> shf <Rs> - r1
++ movne r1,r6,LSR r1
++ mov pc,lr
++
++32: tst r2,#1<<5
++ moveq r1,r6,ASR r1
++ movne r1,r6,ROR r1
++ mov pc,lr
++
++
++
++//IN: r0 - register name
++//OUT: r0 - location
++GetSymbolNumber:
++ BigMov r1,C2(R,0)
++ sub r2,r0,r1
++ cmp r2,#10
++ bcc 1f
++
++ BigMov r1,C3(R,1,0)
++ sub r2,r0,r1
++ cmp r2,#6
++ bcc 2f
++
++ BigMov r1,C3(F,P,0)
++ cmp r1,r0
++ moveq r2,#SYM_FP0
++ beq 1f
++
++ BigMov r1,C2(S,L)
++ cmp r1,r0
++ moveq r2,#SYM_SL
++ beq 1f
++
++ BigMov r1,C2(F,P)
++ cmp r1,r0
++ moveq r2,#SYM_FP
++ beq 1f
++
++ BigEor2 r1,C2(F,P)^C2(I,P)
++ cmp r1,r0
++ moveq r2,#SYM_IP
++ beq 1f
++
++ BigEor2 r1,C2(I,P)^C2(S,P)
++ cmp r1,r0
++ moveq r2,#SYM_SP
++ beq 1f
++
++ BigMov r1,C2(L,R)
++ cmp r1,r0
++ moveq r2,#SYM_LR
++ beq 1f
++
++ BigMov r1,C2(P,C)
++ cmp r1,r0
++ moveq r2,#SYM_PC
++ beq 1f
++
++ BigMov r1,C4(C,P,S,R)
++ cmp r1,r0
++ moveq r2,#SYM_CPSR
++ beq 1f
++
++ BigMov r1,C3(F,S,R)
++ cmp r1,r0
++ moveq r2,#SYM_FSR
++ beq 1f
++
++ BigMov r1,C3(F,A,R)
++ cmp r1,r0
++ moveq r2,#SYM_FAR
++ beq 1f
++
++ BigMov r1,C4(D,C,S,R)
++ cmp r1,r0
++ moveq r2,#SYM_DCSR
++ beq 1f
++
++ BigMov r1,C4(T,T,B,R)
++ cmp r1,r0
++ moveq r2,#SYM_TTBR
++ beq 1f
++
++ BigMov r1,C4(C,T,R,L)
++ cmp r1,r0
++ moveq r2,#SYM_CTRL
++ beq 1f
++
++// BigMov r1,C3(F,P,S)
++// cmp r1,r0
++// moveq r2,#SYM_FPS-SYM_F0
++ movne pc,lr
++
++
++//3: add r2,r2,#SYM_F0-SYM_SL
++2: add r2,r2,#SYM_SL
++1: BigMov r0,DEBUG_SYM
++ add r0,r0,r2
++ subs r2,r2,r2
++ mov pc,lr
++
++
++
++//IN: r0 - symbol address or number to print
++PrintHexOrSymbol:
++ BigAdd r1,r0,-DEBUG_SYM
++ cmp r1,#SYM_LAST+1
++ bcs PrintHex
++ mov r0,#0
++
++//IN: r1 register #, r0 {31:16}- 2 characters to print after
++PrintRegName:
++ cmp r1,#SYM_SL
++ bcs 1f
++ add r0,r0,r1,LSL #8
++ add r0,r0,#L2(NULL,0)
++// cmp r1,#10
++// subge r0,r0,#10<<8
++// movge r0,r0,LSL #8
++// addge r0,r0,#L2(NULL,1)
++ add r0,r0,#L1(R)
++20: b Transmit1
++1: BigOrr2Eq r0,L2(S,L)
++ cmp r1,#SYM_FP
++ BigOrr2Eq r0,L2(F,P)
++ cmp r1,#SYM_IP
++ BigOrr2Eq r0,L2(I,P)
++ cmp r1,#SYM_SP
++ BigOrr2Eq r0,L2(S,P)
++ cmp r1,#SYM_LR
++ BigOrr2Eq r0,L2(L,R)
++ cmp r1,#SYM_PC
++ BigOrr2Eq r0,L2(P,C)
++ ble 20b
++ cmp r1,#SYM_FP0
++
++ mov r0,r0,LSL #8
++ BigOrr2Eq r0,L3(F,P,0)
++ cmp r1,#SYM_FSR
++ BigOrr2Eq r0,L3(F,S,R)
++ cmp r1,#SYM_FAR
++ BigOrr2Eq r0,L3(F,A,R)
++
++ cmp r1,#SYM_CPSR
++ BigMovEq r0,L4(C,P,S,R)
++ cmp r1,#SYM_DCSR
++ BigMovEq r0,L4(D,C,S,R)
++ cmp r1,#SYM_TTBR
++ BigMovEq r0,L4(T,T,B,R)
++ cmp r1,#SYM_CTRL
++ BigMovEq r0,L4(C,T,R,L)
++ b Transmit1
++
++
++//r2 - symbol #
++PrintRegVal:
++ mov r6,lr
++ bl GetRegVal
++ cmp r2,#SYM_FP0
++ bne 1f
++ mov r5,r0
++ mov r0,r1
++ bl PrintHexByte //40 bits
++ mov r0,r5
++1: mov lr,r6
++ b PrintHex
++
++
++
++
++
++//r2 - symbol #, r1:r0 - value
++StoreRegVal:
++ cmp r2,#SYM_FP0
++ bcs 1f
++#if DBG_R0
++ add r1,rDBG,#DBG_R0
++ str r0,[r1,r2,LSL #2]
++#else
++ str r0,[rDBG,r2,LSL #2]
++#endif
++ mov pc,lr
++1:
++ bne 2f
++//MAR{<cond>} acc0,<RdLo>,<RdHi>
++ mar acc0,r0,r1
++ mov pc,lr
++2: cmp r2,#SYM_FSR
++ CP15_FSR mcreq,r0
++ cmp r2,#SYM_FAR
++ CP15_FAR mcreq,r0
++ cmp r2,#SYM_DCSR
++ CP14_DCSR mcreq,r0
++ cmp r2,#SYM_TTBR
++ CP15_TTBR mcreq,r0
++ cmp r2,#SYM_CTRL
++ CP15_CONTROL mcreq,r0
++ mov pc,lr
++
++R_Cmd:
++ mov r7,#0
++1: mov r1,r7
++ BigMov r0,L4(NULL,NULL,COLON,SPACE)
++ bl PrintRegName
++ bl TransmitSPACE
++ mov r2,r7
++ bl PrintRegVal
++ bl TransmitSPACE
++ bl TransmitSPACE
++ add r7,r7,#1
++ tst r7,#3
++ bleq TransmitCRLF
++ cmp r7,#SYM_LAST_RCMD+1
++ bne 1b
++ b Prompt
++BS_Cmd:
++ tst rValidCnt,#F_NUM1_MASK
++ beq BE_Cmd
++ tst rSymbol,#F_NUM1_MASK
++ mov r0,rNum1
++ blne GetSymValue
++ mov rNum1,r0
++ bl BS_Do
++ beq Prompt
++ b BE_Cmd
++
++//out: z-1 breakpoint just set
++// z-0 if r0==rNum1, breakpoint was already set
++BS_Do:
++ CP15_IBCR0 mrc,r0
++ CP15_IBCR1 mrc,r1
++ orr rNum1,rNum1,#1
++ cmp r0,rNum1
++ cmpne r1,rNum1
++ beq 2f
++ tst r0,#1
++ CP15_IBCR0 mcreq,rNum1
++ moveq pc,lr
++ tst r1,#1
++ CP15_IBCR1 mcreq,rNum1
++ mov pc,lr
++
++2: mov r0,rNum1
++ movs r1,#1
++ mov pc,lr
++
++BC_Cmd:
++ tst rValidCnt,#F_NUM1_MASK
++ beq BE_Cmd
++ tst rSymbol,#F_NUM1_MASK
++ mov r0,rNum1
++ blne GetSymValue
++ mov rNum1,r0
++ bl BC_Do
++ beq Prompt
++ b BE_Cmd
++
++//out: z-1 breakpoint just cleared
++BC_Do:
++ CP15_IBCR0 mrc,r0
++ CP15_IBCR1 mrc,r1
++ orr rNum1,rNum1,#1
++ mov r2,#0
++ cmp r0,rNum1
++ CP15_IBCR0 mcreq,r2
++ cmp r1,rNum1
++ CP15_IBCR1 mcreq,r2
++ cmpne r0,rNum1
++ mov pc,lr
++
++BE_Cmd:
++ BigMov r0,L4(B,K,P,T)
++ bl Transmit1
++ bl TransmitSPACE
++ BigMov r0,L4(S,t,a,t)
++ bl Transmit1
++ BigMov r0,L4(u,s,COLON,SPACE)
++ bl Transmit1
++ CP15_IBCR0 mrc,r0
++ tst r0,#1
++ bic r0,r0,#1
++ blne PrintHex
++ bl TransmitSPACE
++
++ CP15_IBCR1 mrc,r0
++ tst r0,#1
++ bic r0,r0,#1
++ blne PrintHex
++ b Prompt
++
++WatchStatus:
++ BigMov r0,L4(W,A,T,C)
++ bl Transmit1
++ BigMov r0,L2(H,SPACE)
++ bl Transmit1
++ BigMov r0,L4(S,t,a,t)
++ bl Transmit1
++ BigMov r0,L4(u,s,COLON,SPACE)
++ bl Transmit1
++ CP15_DBCON mrc,r5
++ tst r5,#0x0f
++ beq 10f
++ tst r5,#0x03
++ bne 1f
++ tst r5,#0x100
++ bne 10f //br if dbr1 is mask (nothing being watched)
++ b 4f
++1:
++ CP15_DBR0 mrc,r0
++ bl PrintHex
++ bl 20f
++ tst r5,#0x100
++ beq 3f
++ BigMov r0,L2(M,COLON)
++ bl Transmit1
++ CP15_DBR1 mrc,r0 //read mask
++ bl PrintHex
++ b 10f
++3:
++ tst r5,#3<<2
++ beq 10f
++4:
++ CP15_DBR1 mrc,r0
++ bl PrintHex
++ mov r5,r5,LSR #2
++ bl 20f
++10: b Prompt
++
++
++20:
++ BigMov r0,L4(SPACE,R,W,SPACE)
++ tst r5,#1
++ beq 21f
++ tst r5,#2
++ BigEor2Eq r0,L4(SPACE,R,W,SPACE)^L4(SPACE,SPACE,W,SPACE) //store only
++ BigEor2Ne r0,L4(SPACE,R,W,SPACE)^L4(SPACE,R,SPACE,SPACE) //load only
++21:
++ b Transmit1
++
++WC_Cmd:
++ mov r0,#0
++ CP15_DBCON mcr,r0
++ b Prompt
++WRW_Cmd:
++ mov r4,#2
++ b WW_JOIN
++WR_Cmd:
++ mov r4,#3
++ b WW_JOIN
++WW_Cmd:
++ mov r4,#1
++WW_JOIN:
++ tst rValidCnt,#F_NUM1_MASK
++ beq WatchStatus
++ tst rSymbol,#F_NUM1_MASK
++ mov r0,rNum1
++ blne GetSymValue
++ mov rNum1,r0
++
++ tst rValidCnt,#F_NUM2_MASK
++ beq 3f
++ tst rSymbol,#F_NUM2_MASK
++ mov r0,rNum2
++ blne GetSymValue
++ mov rNum2,r0
++ orr r4,r4,#0x100 //mask
++1:
++ mov r0,#0
++ CP15_DBCON mcr,r0
++ CP15_DBR0 mcr,rNum1
++ CP15_DBR1 mcr,rNum2
++2:
++ CP15_DBCON mcr,r4
++ b Prompt
++3:
++ CP15_DBCON mrc,r5
++ mov rNum2,#0
++ tst r5,#0x100
++ bne 1b //br if mask was used previously
++ tst r5,#0x0f
++ beq 1b
++ mov r0,#0
++ CP15_DBCON mcr,r0
++ tst r5,#3
++ orreq r4,r5,r4
++ bicne r5,r5,#3<<2
++ orrne r4,r5,r4,LSL #2
++ CP15_DBR0 mcreq,rNum1
++ CP15_DBR1 mcrne,rNum1
++ b 2b
++
++
++//IN: rNum2 address
++//OUT: r1:r0 val
++GetSymValue:
++ BigAdd r2,rNum2,-DEBUG_SYM
++ cmp r2,#SYM_LAST+1
++ bcc GetRegVal
++ mov r0,rNum2
++ mov r1,#0
++ mov pc,lr
++//IN: rPrevNum1 address or symbol
++//OUT: r1:r0 val
++GetValue:
++ BigAdd r2,rPrevNum1,-DEBUG_SYM
++ cmp r2,#SYM_LAST+1
++ bcc GetRegVal
++ ldr r0,[rPrevNum1]
++ mov r1,#0
++ mov pc,lr
++
++
++//IN: rNum1 address
++PrintLocationOrRegVal:
++ BigAdd r2,rNum1,-DEBUG_SYM
++ cmp r2,#SYM_LAST+1
++ bcc PrintRegVal
++ tst r5,#3
++ tsteq rNum1,#3
++ bne 1f
++ ldr r0,[rNum1]
++ b PrintHex
++1: ldrb r0,[rNum1]
++ b PrintHexByte
++
++//IN: rPrevNum1 address, r1:r0 - value
++StoreLocationOrReg:
++ BigAdd r2,rPrevNum1,-DEBUG_SYM
++ cmp r2,#SYM_LAST+1
++ bcc StoreRegVal
++ tst r5,#3
++ tsteq rPrevNum1,#3
++ bne 1f
++ str r0,[rPrevNum1]
++ mov pc,lr
++1: strb r0,[rPrevNum1]
++ mov pc,lr
++
++GetChangeAmount:
++ BigAdd r0,rPrevNum1,-DEBUG_SYM
++ cmp r0,#SYM_LAST+1
++ movcs r0,#4
++ movcc r0,#1
++ tst r5,#3
++// tsteq rPrevNum1,#3
++ movne r0,#1
++ mov pc,lr
++
++Examine_Cmd:
++ tst rValidCnt,#F_NUM1_MASK
++ moveq rNum1,rPrevNum1
++ movne rPrevNum1,rNum1
++ mov r5,rNum1
++ tst rValidCnt,#F_NUM2_MASK
++ bne 12f
++1: mov r0,rNum1
++ bl PrintHexOrSymbol
++ mov r0,#L1(FSLASH)
++ bl Transmit
++
++ bl PrintLocationOrRegVal
++
++ bl TransmitSPACE
++ mov rFieldStart,#1<<(F_INC+F_INC+F_INC+F_INC) //blank before num2 field
++ str r5,[rDBG,#DBG_TEMP]
++ bl ReadCommand
++ ldr r5,[rDBG,#DBG_TEMP]
++ mov r3,r0 //save exit character
++ mov r0,rNum2
++ mov r1,#0
++ tst rSymbol,#F_NUM2_MASK
++ beq 20f
++ blne GetSymbolNumber
++ bne Invalid
++ mov rNum2,r0
++ bl GetSymValue
++
++20:
++ cmp r3,#L1(PLUS)
++ cmpne r3,#L1(MINUS)
++ cmpne r3,#L1(AT_SIGN)
++ beq 2f
++ tst rValidCnt,#F_NUM2_MASK
++ beq Prompt
++ bl StoreLocationOrReg
++ mov r3,#L1(PLUS)
++ b 3f
++
++2: mov r0,r3
++ bl Transmit
++3: bl TransmitCRLF
++ bl GetChangeAmount
++ cmp r3,#L1(AT_SIGN)
++ beq 5f
++ cmp r3,#L1(PLUS)
++ addeq rPrevNum1,rPrevNum1,r0
++ subne rPrevNum1,rPrevNum1,r0
++4: mov rNum1,rPrevNum1
++ b 1b
++
++5: bl GetValue
++ mov rPrevNum1,r0
++ mov r5,r0
++ b 4b
++
++11: sub r0,rNum1,r5
++ cmp r0,#0x1000
++ bhs Prompt //no more than 128 lines per examine command
++ bl TransmitCRLF
++12: mov r0,rNum1
++ bl PrintHexOrSymbol
++ mov r0,#L1(FSLASH)
++ bl Transmit
++13:
++ bl GetChangeAmount
++ bcc 14f
++ add r0,rNum1,#3
++ cmp r0,rNum2
++ bhi 16f
++ tst r5,#3
++ tsteq rNum1,#3
++ bne 16f
++14: bl PrintLocationOrRegVal
++ bl GetChangeAmount
++15: add rNum1,rNum1,r0
++ cmp rNum1,rNum2
++ bhi Prompt
++ tst rNum1,#0x1f
++ beq 11b
++ bl TransmitSPACE
++ tst rNum1,#0x0f
++ bleq TransmitSPACE
++ b 13b
++16:
++ ldrb r0,[rNum1]
++ bl PrintHexByte
++ mov r0,#1
++ b 15b
++
++Deposit_Cmd:
++ tst rValidCnt,#F_NUM1_MASK
++ beq Invalid
++ tst rValidCnt,#F_NUM2_MASK
++ beq Invalid
++ mov r0,rNum2
++ mov r1,#0
++ tst rSymbol,#F_NUM2_MASK
++ blne GetSymValue
++ mov rPrevNum1,rNum1
++ bl StoreLocationOrReg
++ b Prompt
++
++
++Download_Cmd:
++ tst rValidCnt,#F_NUM1_MASK
++ beq Invalid
++ tst rNum1,#3
++ bne Invalid
++ cmp rNum1,#MEM_START
++ bcc Invalid //br if rNum1 is below ram start,
++ //NOTE: arm sets the carry to the opposite of most processors on subtract, compare
++
++ mov rDest,rNum1
++ mov rDestHead,rNum1
++ mov rPrevNum1,rNum1
++ mov rPrevCRC,#0
++ mov rRunningCRC,#0
++ mov rNak,#L1(C) //current NAK character
++ mov rBlockNum,#1 //block # to receive
++
++#if DDEBUG
++ b 47f
++91:
++ cmp rBlockNum,#1
++ beq 47f
++ mov r2,#L1(1)
++ b 45f
++92:
++ mov r2,#L1(2)
++ b 45f
++93:
++ mov r2,#L1(3)
++ b 45f
++94:
++ mov r2,#L1(4)
++ b 45f
++95:
++ mov r2,#L1(5)
++45:
++ BigMov r0,L3(CAN,CAN,CAN) //abort
++ bl Transmit1
++46: bl Receive
++ bne 46b //branch until timeout
++ mov r0,r2
++ bl Transmit
++ b Invalid
++#else
++91:
++92:
++93:
++94:
++95:
++#endif
++
++47:
++
++ mov r0,rNak
++15:
++ bl Transmit
++2: bl Receive
++ beq 91b //branch on timeout
++
++ mov rPacketLength,#128-1
++ cmp r0,#SOH
++ addne rPacketLength,rPacketLength,#1024-1-(128-1)
++ cmpne r0,#STX
++ beq 3f
++ cmp r0,#CAN
++ bne 16f
++ bl Receive
++ cmp r0,#CAN
++ bne 10f
++ b Invalid
++16: cmp r0,#EOT
++ bne 10f
++ mov r0,#ACK
++ bl Transmit
++
++#if DDEBUG
++ mov rDestHead,rDest
++ mov r0,rDest
++ bl PrintHex
++ bl TransmitSPACE
++ mov r0,rBlockNum
++ bl PrintHex
++
++ bl TransmitSPACE
++ mov r0,rRunningCRC
++ bl PrintHex
++ mov rDest,rDestHead
++#endif
++
++// now verify that ram is STILL valid by recomputing the CRC
++ mov rCRC,#0
++ mov r1,rPrevNum1
++ b 83f
++82:
++ ldrb r0,[r1],#1
++//
++ eor r0,rCRC,r0,LSL #24
++ eor r0,r0,r0,LSR #4 //c is in high byte of r0
++ and r0,r0,#0xff000000
++
++ mov rCRC,rCRC,LSL #8
++ eor rCRC,rCRC,r0,LSL #4
++ orr rCRC,rCRC,r0,LSR #8
++
++ eor rCRC,rCRC,r0,LSR #3
++//
++83: cmp r1,rDest
++ bne 82b
++#if DDEBUG
++ bl TransmitSPACE
++ mov r0,rCRC
++ bl PrintHex
++#endif
++
++ cmp rCRC,rRunningCRC
++ bne 84f
++ BigMov r0,L3(O,K,SPACE)
++ bl Transmit1
++ mov r0,rPrevNum1
++ mov rDestHead,rDest
++ bl PrintHex
++ mov r0,#L1(MINUS)
++ bl Transmit
++ mov r0,rDestHead
++ bl PrintHex
++ b Prompt
++84:
++ BigMov r0,L4(E,R,R,O)
++ bl Transmit1
++ mov r0,#L1(R)
++ bl Transmit
++ b Prompt
++
++3: bl Receive
++ beq 92b
++ mov r2,r0
++ bl Receive
++ beq 93b
++ eor r0,r0,#0xff
++ cmp r0,r2 //check 1's complement blk #
++ bne 10f
++ cmp r2,rBlockNum //check blk #
++ bne 20f
++80:
++ mov rDestHead,rDest //rDestHead - start of buffer, rDest end of buffer
++ mov rPrevCRC,rRunningCRC
++ mov rCRC,#0 //crc
++
++//alternative CRC calculation routines
++ .if 0
++ BigMov r2,CRC_POLY
++4: bl Receive
++ beq 8f //branch on timeout
++ eor rCRC,rCRC,r0,LSL #24
++ mov r1,#8
++5:
++ movs rCRC,rCRC,LSL #1
++ eorcs rCRC,rCRC,r2
++ subs r1,r1,#1
++ bne 5b
++ strb r0,[rDest],#1
++ subs rPacketLength,rPacketLength,#1
++ bge 4b
++ mov rCRC,rCRC,LSR #16 //CRC was only in the high half
++
++ .endif
++
++
++
++ .if 1
++4: bl Receive
++ beq 8f //branch on timeout
++//
++//calculate CRC
++//unsigned int crc = 0;
++//unsigned int c = 0;
++//for (i=3; i<max; i++)
++//{
++// c = crc ^ (buf[i]<<24);
++// c ^= (c >> 4);
++// c &= 0xff000000;
++// crc = (((crc<<8) ^ (c << 4)) | (c>>8)) ^ (c >> 3);
++//}
++//crc >>= 16;
++//
++ eor r1,rCRC,r0,LSL #24
++ eor r1,r1,r1,LSR #4
++ and r1,r1,#0xff000000
++
++ mov rCRC,rCRC,LSL #8
++ eor rCRC,rCRC,r1,LSL #4
++ orr rCRC,rCRC,r1,LSR #8
++ eor rCRC,rCRC,r1,LSR #3
++
++//also save a running total CRC to use to verify RAM after download is complete
++//
++ eor r1,rRunningCRC,r0,LSL #24
++ eor r1,r1,r1,LSR #4 //c is in high byte of r1
++ and r1,r1,#0xff000000
++
++ mov rRunningCRC,rRunningCRC,LSL #8
++ eor rRunningCRC,rRunningCRC,r1,LSL #4
++ orr rRunningCRC,rRunningCRC,r1,LSR #8
++
++ eor rRunningCRC,rRunningCRC,r1,LSR #3
++//
++#if LITTLE_ENDIAN
++ mov r0,r0,LSL #24
++ orr r2,r0,r2,LSR #8 //this assumes a little endian memory system
++#else
++ orr r2,r0,r2,LSL #8 //this assumes a big endian memory system
++#endif
++
++ tst rPacketLength,#3
++ streq r2,[rDest],#4
++ subs rPacketLength,rPacketLength,#1
++ bge 4b
++ mov rCRC,rCRC,LSR #16 //CRC was only in the high half
++ .endif
++
++
++
++
++ bl Receive
++ beq 8f //branch on timeout
++ mov r2,r0
++ bl Receive
++ beq 8f //branch on timeout
++ add r2,r0,r2,LSL #8
++ cmp rCRC,r2
++ bne 9f //branch on crc mismatch
++//packet is good
++ add rBlockNum,rBlockNum,#1
++ and rBlockNum,rBlockNum,#0xff
++ mov rNak,#NAK
++ mov r0,#ACK
++ b 15b
++20:
++ sub r1,rBlockNum,#1
++ and r1,r1,#0xff
++ cmp r1,r2
++ bne 21f //br if not trying to transmit the packet I just ACKed
++ mov rDest,rDestHead //reset pointer to previous packet
++ mov rRunningCRC,rPrevCRC
++ mov rBlockNum,r1 //correct blk #
++ b 80b
++
++21: BigMov r0,L3(CAN,CAN,CAN) //abort code
++ bl Transmit1
++48: bl Receive
++ bne 48b //branch until timeout
++
++#if DDEBUG
++ mov r0,r2
++ bl PrintHex
++ bl TransmitSPACE
++ mov r0,rBlockNum
++ bl PrintHex
++#endif
++
++ b Invalid //give up
++
++
++8: mov rDest,rDestHead //reset register
++ mov rRunningCRC,rPrevCRC
++ b 94b //send NAK
++9:
++#if DDEBUG //debug code
++ BigMov r0,L3(CAN,CAN,CAN) //abort code
++ bl Transmit1
++44: bl Receive
++ bne 44b //branch until timeout
++ mov r0,r2
++ bl PrintHex
++ bl TransmitSPACE
++ mov r0,rCRC
++ bl PrintHex
++ b Invalid
++#endif
++
++ mov rDest,rDestHead
++ mov rRunningCRC,rPrevCRC
++
++
++10: bl Receive
++ bne 10b //branch until timeout
++ b 95b //send NAK and wait for packet
++
++
++
++// *******************************************************************************************
++// *******************************************************************************************
++// *******************************************************************************************
++// *******************************************************************************************
++//Code above this point must fit in 2k mini cache or be burned on flash
++//
++//Code below this point need not be in the 2k mini-instruction cache,
++//it can be temporarily placed in the main instruction cache unlocked
++// *******************************************************************************************
++
++InitializeCont1:
++//pc - 0-0x4000, 0x04000000-0x04004000, 0xa000000-0xffffffff
++ InitIC_Clocks r0,sp
++ InitUART r0,sp,FFUART_BASE,BAUDRATE
++ InitUART r0,sp,BTUART_BASE,BAUDRATE
++ InitUART r0,sp,STUART_BASE,9600
++ InitChangeCPUSpeed r0
++ InitMemory r0,sp,r1
++ BigMov r1,MACH_TYPE_SCANPASS
++ SaveRegisters r0,sp
++// *******************************************************
++ InitMMU r0
++ InitPWR r0,r1,sp //out: r1 RCSR
++InitializeCont2:
++ cmp pc,#MEM_START
++ bhs 89f //if in ram, must be mdebug
++ bic sp,pc,#FLASH_BASE_ADDRESS
++ cmp sp,#0x4000
++ mov r2,#FUNC_REQ_GL
++ bhs 87f //br if not part of reset vector
++ tst r1,#RCSR_SLEEP_RESET
++ beq 89f //; Not sleep.
++ mov r2,#FUNC_REQ_WAKEUP
++87: adr r7,88f
++ adr lr,89f
++ mov r10,r1 //RCSR
++ b TryRoutine1
++88: ldmia sp,{rPrevNum1,rUart,rDBG}
++89:
++ mov r2,lr
++ bl CalcMemEnd
++ mov r3,r0
++ mov lr,r2
++// *******************************************************
++//0xnnnn0000 - 16k remapping of flash address 0 for relocated vector table
++//0xnnnn4000 - 16k 16k 1st level descriptors table
++//0xnnnn8000 - 16k 2 x 1k 2nd level descriptor tables
++//0xnnnnc000 - 16k 12k skipped, 4k debug data
++//end of ram
++ BigSub sp,r3,0x8000
++ sub r2,sp,#0x4000
++ mov r1,r2
++ BigMov r0,0x0402 //section descriptor, ap-01, privileged r/w
++ //map virt to phys 1-to-1, non-cache, non-bufferable
++1: str r0,[r2],#4
++ add r0,r0,#1<<20
++ cmp r2,sp
++ bne 1b
++
++
++ add sp,r1,r3,LSR #(20-2)
++ add r1,r1,#((MEM_START>>20)&0xfff)<<2 //microsoft assembler bug propagates the sign bit
++ BigMov r0,(MEM_START&0xfff00000)+0x040A //cacheable (write through)
++2: str r0,[r1],#4
++ cmp r1,sp
++ addne r0,r0,#1<<20
++ bne 2b
++//r0 is physical address of last meg of memory
++ orr r1,r2,#1 //2nd level descriptor address (1k boundary), coarse page table
++
++ .ifdef __ARMASM
++ GBLA TABLE_CNT
++ .endif
++ .if ((DEBUG_START&0xfff00000) - (0xffff0000&0xfff00000))
++ .set TABLE_CNT,2
++ str r1,[r2,#((DEBUG_START>>18)&0x3ffc)-0x4000] //r2 is the end of the 16k table
++ add r1,r1,#0x400
++
++ .else
++ .set TABLE_CNT,1
++ .endif
++
++ str r1,[r2,#-4] //map (0xfff00000) to 2nd level page table
++ //last meg of memory (contains relocated reset vector)
++ add sp,r2,#((256*TABLE_CNT)-16)<<2 //256 - 4byte entries each mapping 4k
++
++//clear out 1 or 2 level 2 page tables
++ mov r1,#0
++3: str r1,[r2],#4
++ cmp r2,sp
++ bne 3b
++
++
++ BigMov r1,0x559 //map to flash in 1 - 64k page
++ add sp,sp,#16<<2
++4: str r1,[r2],#4
++ cmp r2,sp
++ bne 4b
++
++ bic r0,r0,#0x000ff
++ orr r0,r0,#0x0000e //cacheable writeback 4k page
++// orr r0,r0,#0x0000a //cacheable writethru 4k page
++ orr r0,r0,#0x00aa0 //privileged r/w, user read
++ orr r0,r0,#0xff000 //last 4k of ram
++
++ str r0,[r2,#((DEBUG_START>>10)&0x3fc)-(TABLE_CNT*0x400)] //debug variables, r2 is end of 1k tables
++
++ BigMov r0,0xffffffff
++ CP15_DACR mcr,r0
++
++ BigSub r0,r3,0xc000 //MEM_END-0xc000
++ CP15_TTBR mcr,r0
++//enable MMU
++ CP15_TLB_UNLOCK_I mcr,r0
++ CP15_TLB_UNLOCK_D mcr,r0
++ CP15_TLB_INVAL_BOTH mcr,r0
++
++ CP15_CONTROL mrc,r1 //get the control register
++ orr r1,r1,#0x1 //set bit 0 - enable MMU
++ CPWAIT r0
++ CP15_CONTROL mcr,r1 //set the control register
++ CPWAIT r0
++
++//enable the instruction cache
++ CP15_CF_UNLOCK_I mcr,r0
++// CP15_CF_INVAL_I mcr,r0 //I might be running from cache only, don't invalidate
++
++ orr r1,r1,#0x1000 //set bit 12 -- the I bit
++ CP15_CONTROL mcr,r1 //set the control register
++ CPWAIT r0
++
++//enable the data cache
++ CP15_CF_UNLOCK_D mcr,r0
++ CP15_CF_INVAL_D mcr,r0 //this will also drain write buffer
++ CP15_CF_DRAIN mcr,r0 //make sure it is drained just to be very safe
++
++ orr r1,r1,#0x4 //set bit 4 -- the D bit
++ CP15_CONTROL mcr,r1 //set the control register
++ CPWAIT r0
++
++ .if 0
++//if not in halt mode, lock 64k of flash remap in instruction TLB(contains override relocated vector table)
++//halt mode uses the mini cache and physical addresses only for this
++ CP14_DCSR mrc,r0
++ BigMov r1,0xffff0000
++ tst r0,#0x40000000
++//I am currently executing from flash, marked as uncacheable
++ CP15_TLB_LOCK_IENTRY mcreq,r1 //lock 64k if not in halt mode
++ CPWAIT r0
++ .endif
++
++//now lock debug data into data cache
++ BigMov r1,DEBUG_START
++ mov r2,#DEBUG_SPACE>>5 //3 or 4 cache lines to lock
++ CP15_TLB_LOCK_DENTRY mcr,r1
++ mov sp,#1
++ CP15_CF_LOCK_D_CSR mcr,sp //data cache is into lock mode
++ CPWAIT r0
++5: pld [r1]
++ add r1,r1,#32 //lock and load
++ CP15_CF_DRAIN mcr,r0
++ subs r2,r2,#1
++ bne 5b
++
++ mov sp,#0
++ CP15_CF_LOCK_D_CSR mcr,sp //data cache is out of lock mode
++ CPWAIT r0
++
++ BigMov r0,0x3fff
++ CP15_CP_ACCESS mcr,r0 //enable access to all coprocessors
++//now disable MMU, Data Cache
++ .if 1
++ CP15_CONTROL mrc,r1 //get the control register
++ bic r1,r1,#0x5
++ CP15_CONTROL mcr,r1 //set the control register
++ CPWAIT r0
++ .endif
++#if (DO_GPTEST==0)
++// TransMacro L1(U)
++
++#if (PLATFORM_TYPE==BD2003) || (PLATFORM_TYPE==BOUNDARY_OLD_BOARD) || (PLATFORM_TYPE==OLD_GAME_CONTROLLER) || (PLATFORM_TYPE==HALOGEN)
++ sub r0,r3,#0x100000 //last meg-8k for video ram
++ sub r1,r3,#0x2000 //8K from end, last 4k is debug variables
++ str r1,[r1,#FDESC_FDADR] //next frame descriptor address, loop to self
++ str r0,[r1,#FDESC_FSADR] //start of frame
++ str r0,[r1,#FDESC_FIDR] //id of frame, anything I want
++ BigMov r2,SCREEN_WIDTH*SCREEN_HEIGHT*BYTES_PER_PIXEL
++ str r2,[r1,#FDESC_DCMD] //length of dma transfer
++
++#if (BYTES_PER_PIXEL==2)
++ BigMov sp,(BLUE_VAL<<0)+(GREEN_VAL<<5)+(RED_VAL<<11) //rgb value
++ orr sp,sp,sp,LSL #16
++79: str sp,[r0],#4
++ subs r2,r2,#4
++ bne 79b
++#else
++ BigMov r1,(BLUE_VAL<<0)+(GREEN_VAL<<6)+(RED_VAL<<12) //rgb value
++ orr r1,r1,r1,LSL #24
++
++ mov sp,r1,LSR #8
++ orr sp,sp,sp,LSL #24
++
++ mov lr,sp,LSR #8
++ orr lr,lr,lr,LSL #24
++79: stmia r0!,{r1,sp,lr}
++ subs r2,r2,#12
++ bne 79b
++ sub r1,r3,#0x2000 //8K from end, last 4k is debug variables
++#endif
++
++ InitLCD r0,sp,r1 //r1 has descriptor address
++#endif
++
++
++// ****************************
++ mrs r1, CPSR
++ bic r2, r1,#PSR_MODE_MASK
++ orr r0, r2,#PSR_NOINTS_MASK+PSR_MODE_SVC //change to supervisor stack
++ msr CPSR_c, r0
++ BigMov r0,SS_START+SS_SUPERVISOR
++ mov sp, r0
++
++ orr r2, r2, #PSR_NOINTS_MASK+PSR_MODE_IRQ //irq stack
++ msr CPSR_c, r2
++ BigAdd sp, r0, SS_IRQ
++
++ sub r2, r2, #PSR_MODE_IRQ-PSR_MODE_FIQ //fiq stack
++ msr CPSR_c, r2
++ BigAdd sp, r0, SS_IRQ+SS_FIQ
++
++ add r2, r2, #PSR_MODE_SYSTEM-PSR_MODE_FIQ //system(user mode)
++ msr CPSR_c, r2
++ BigAdd sp, r0, SS_IRQ+SS_FIQ+SS_SYSTEM
++
++ sub r2, r2, #PSR_MODE_SYSTEM-PSR_MODE_UNDEF //undefined stack
++ msr CPSR_c, r2
++ BigAdd sp, r0, SS_IRQ+SS_FIQ+SS_SYSTEM+SS_UNDEFINED
++
++ sub r2, r2, #PSR_MODE_UNDEF-PSR_MODE_ABORT //Abort stack
++ msr CPSR_c, r2
++ BigAdd sp, r0, SS_IRQ+SS_FIQ+SS_SYSTEM+SS_UNDEFINED+SS_ABORT
++//
++ msr CPSR_c, r1
++ sub r2, r2, #PSR_MODE_ABORT-PSR_MODE_SVC //supervisor stack
++
++// ****************************
++ CP14_DCSR mrc,sp
++ tst sp,#1<<5 //test sticky abort bit
++ mov sp,r0
++ BigMovEq r0,DEBUG_BASE+DBG_MAGIC
++ BigAddNe r0,r3,(-0x1000+((DEBUG_BASE+DBG_MAGIC)&0xfff)) //don't use virtual address if memory isn't working right
++ sub r0,r0,#DBG_MAGIC
++
++ and r1,r1,#PSR_MODE_MASK
++ mov r3,#0
++ cmp r1,#PSR_MODE_DEBUG
++ BigMov lr,0xa0008000 //default start pc
++ beq SaveDebug //br if a debug exception in halt mode
++ mov r1,#SIG_RESET
++ b SaveR4andUp
++#else
++//#define GPBIT 2
++//#define GPL GPLR1
++#define GPBIT 9
++#define GPL GPLR0
++#define GPMASK (1<<GPBIT)
++GPTest:
++ BigMov rUart,UART_BASE
++ BigMov fp,GPIO_BASE
++ mov r6,#GPMASK
++ str r6,[fp,#GPSR0]
++
++2: bl TransmitCRLF
++ mov r3,#40
++20: mov r2,#0x300000
++
++1: ldr r0,[fp]
++ and r0,r1,#GPMASK
++ cmp r0,r6
++ subnes r2,r2,#1
++ bne 1b //wait for desired state
++
++ mov r1,#L1(0)
++ add r0,r1,r0,LSR #GPBIT
++ bl Transmit
++
++ mov r0,#GPMASK
++ eors r6,r6,#GPMASK //get new desired state
++ streq r0,[fp,#GPCR0]
++ strne r0,[fp,#GPSR0]
++ subs r3,r3,#1
++ bne 20b
++ b 2b
++#endif
++
++
++
++
++ .if 0 //macro tests
++ BigMov r0,-1
++ BigMov r0,-5
++ BigMov r0,0x0ffffff0
++ BigMov r0,1
++ BigMov r0,0xff
++ BigMov r0,0xf000000f
++ BigMov r0,0x80010003
++ .endif
++
++
++TransLineR3:
++ mov r4,#0
++TransLineR4:
++ mov r5,#0
++TransLineR5:
++ mov r6,#0
++TransLineR6:
++ mov r7,#0
++TransLineR7:
++ mov fp,lr
++ mov r0,r2
++ bl Transmit1
++
++ BigEor r0,rSP,L4(SPACE,SPACE,SPACE,SPACE)^L4(SPACE,SPACE,MINUS,SPACE)
++ bl Transmit1
++
++ mov r0,r3
++ bl Transmit1
++ movs r0,r4
++ blne Transmit1
++ movs r0,r5
++ blne Transmit1
++ movs r0,r6
++ blne Transmit1
++ movs r0,r7
++ blne Transmit1
++ mov lr,fp
++ b TransmitCRLF
++
++Help_Cmd:
++ BigMov rSP,L2(SPACE,SPACE)
++ orr rSP,rSP,rSP,LSL #16
++
++ BigEor r2,rSP,L4(SPACE,SPACE,SPACE,SPACE)^L4(B,C,SPACE,SPACE) //BC -Breakpoint clear
++ BigEor r3,r2, L4(B,C,SPACE,SPACE)^L4(B,r,e,a)
++ BigMov r4, L4(k,p,o,i)
++ BigEor r5,rSP,L4(SPACE,SPACE,SPACE,SPACE)^L4(n,t,SPACE,c)
++ BigMov r6, L4(l,e,a,r)
++ bl TransLineR6
++
++ BigEor2 r2,L4(B,C,SPACE,SPACE) ^L4(B,E,SPACE,SPACE) //BE -Breakpoint examine
++ BigEor2 r5,L4(n,t,SPACE,c) ^L4(n,t,SPACE,e)
++ BigMov r6, L4(x,a,m,i)
++ BigMov r7, L2(n,e)
++ bl TransLineR7
++
++ BigEor2 r2,L4(B,E,SPACE,SPACE) ^L4(B,S,SPACE,SPACE) //BS -Breakpoint set
++ BigEor2 r5,L4(n,t,SPACE,e) ^L4(n,t,SPACE,s)
++ BigMov r6, L2(e,t)
++ bl TransLineR6
++
++ BigEor2 r2,L4(B,S,SPACE,SPACE) ^L4(B,U,R,N) //BURN-Write to flash
++ BigMov r3, L4(W,r,i,t)
++ BigEor r4,rSP,L4(SPACE,SPACE,SPACE,SPACE)^L4(e,SPACE,t,o)
++ BigMov r5, L4(SPACE,f,l,a)
++ BigMov r6, L2(s,h)
++ bl TransLineR6
++
++ BigEor r2,rSP,L4(SPACE,SPACE,SPACE,SPACE)^L4(E,SPACE,SPACE,SPACE) //E -Examine
++ BigEor r3,r2, L4(E,SPACE,SPACE,SPACE)^L4(E,x,a,m)
++ BigMov r4, L3(i,n,e)
++ bl TransLineR4
++
++ BigEor r2,rSP,L4(SPACE,SPACE,SPACE,SPACE)^L4(D,SPACE,SPACE,SPACE) //D -Deposit
++ BigEor r3,r2, L4(D,SPACE,SPACE,SPACE)^L4(D,e,p,o)
++ BigMov r4, L3(s,i,t)
++ bl TransLineR4
++
++ BigEor2 r2,L4(D,SPACE,SPACE,SPACE) ^L4(D,L,SPACE,SPACE) //DL -Download
++ BigEor2 r3,L4(D,e,p,o) ^L4(D,o,w,n)
++ BigMov r4, L4(l,o,a,d)
++ bl TransLineR4
++
++ BigEor2 r2,L4(D,L,SPACE,SPACE) ^L4(D,L,W,SPACE) //DLW -Download wireless
++ BigEor r5,rSP,L4(SPACE,SPACE,SPACE,SPACE)^L4(SPACE,w,i,r)
++ BigMov r6, L4(e,l,e,s)
++ BigMov r7, L1(s)
++ bl TransLineR7
++
++ BigEor r2,rSP,L4(SPACE,SPACE,SPACE,SPACE)^L4(G,SPACE,SPACE,SPACE) //G -Go
++ BigMov r3, L2(G,o)
++ bl TransLineR3
++
++ BigEor2 r2,L4(G,SPACE,SPACE,SPACE) ^L4(G,L,SPACE,SPACE) //GL -Go Linux
++ BigEor2 r3,L2(G,o) ^L4(G,o,SPACE,L)
++ BigMov r4, L4(i,n,u,x)
++ bl TransLineR4
++
++ BigEor2 r2,L4(G,L,SPACE,SPACE) ^L4(G,G,SPACE,SPACE) //GG -Go no cache clear
++ BigEor2 r3,L4(G,o,SPACE,L) ^L4(G,o,SPACE,n)
++ BigEor r4,rSP,L4(SPACE,SPACE,SPACE,SPACE)^L4(o,SPACE,c,a)
++ BigEor r5,rSP,L4(SPACE,SPACE,SPACE,SPACE)^L4(c,h,e,SPACE)
++ BigMov r6, L4(c,l,e,a)
++ BigMov r7, L1(r)
++ bl TransLineR7
++
++ BigEor r2,rSP,L4(SPACE,SPACE,SPACE,SPACE)^L4(R,SPACE,SPACE,SPACE) //R -Registers
++ BigEor r3,r2, L4(R,SPACE,SPACE,SPACE)^L4(R,e,g,i)
++ BigMov r4, L4(s,t,e,r)
++ BigMov r5, L1(s)
++ bl TransLineR5
++
++ BigMov r2, L4(S,S,I,D) //SSID- Set SSID string
++ BigEor r3,rSP,L4(SPACE,SPACE,SPACE,SPACE)^L4(S,e,t,SPACE)
++ mov r4,r2
++ BigMov r5, L4(SPACE,s,t,r)
++ BigMov r6, L3(i,n,g)
++ bl TransLineR6
++
++ BigEor r2,rSP,L4(SPACE,SPACE,SPACE,SPACE)^L4(T,SPACE,SPACE,SPACE) //T -Trace
++ BigEor r3,r2, L4(T,SPACE,SPACE,SPACE)^L4(T,r,a,c)
++ BigMov r4,L1(e)
++ bl TransLineR4
++
++ BigEor2 r2,L4(T,SPACE,SPACE,SPACE) ^L4(T,T,SPACE,SPACE) //TT -Trace
++ BigEor2 r4,L1(e) ^L4(e,SPACE,n,o)
++ BigEor r5,rSP,L4(SPACE,SPACE,SPACE,SPACE)^L4(SPACE,c,a,c)
++ BigEor r6,rSP,L4(SPACE,SPACE,SPACE,SPACE)^L4(h,e,SPACE,c)
++ BigMov r7, L4(l,e,a,r)
++ bl TransLineR7
++
++ BigEor r2,rSP,L4(SPACE,SPACE,SPACE,SPACE)^L4(V,SPACE,SPACE,SPACE) //V -Verify
++ BigEor r3,r2, L4(V,SPACE,SPACE,SPACE)^L4(V,e,r,i)
++ BigMov r4, L2(f,y)
++ bl TransLineR4
++
++ BigEor r2,rSP,L4(SPACE,SPACE,SPACE,SPACE)^L4(W,C,SPACE,SPACE) //WC -Watch clear
++ BigEor r3,r2, L4(W,C,SPACE,SPACE)^L4(W,a,t,c)
++ BigEor r4,rSP,L4(SPACE,SPACE,SPACE,SPACE)^L4(h,SPACE,c,l)
++ BigMov r5, L3(e,a,r)
++ bl TransLineR5
++
++ BigEor2 r2,L4(W,C,SPACE,SPACE) ^L4(W,R,SPACE,SPACE) //WR -Watch read
++ BigEor2 r4,L4(h,SPACE,c,l) ^L4(h,SPACE,r,e)
++ BigMov r5, L2(a,d)
++ bl TransLineR5
++
++ BigEor2 r2,L4(W,R,SPACE,SPACE) ^L4(W,R,W,SPACE) //WRW -Watch read/write
++ BigEor2 r5,L2(a,d) ^L4(a,d,FSLASH,w)
++ BigMov r6, L4(r,i,t,e)
++ bl TransLineR6
++
++ BigEor r2,rSP,L4(SPACE,SPACE,SPACE,SPACE)^L4(W,W,SPACE,SPACE) //WW -Watch write
++ BigEor2 r4,L4(h,SPACE,r,e) ^L4(h,SPACE,w,r)
++ BigMov r5, L3(i,t,e)
++ bl TransLineR5
++
++ BigEor r2,rSP,L4(SPACE,SPACE,SPACE,SPACE)^L4(QUESTION_MARK,SPACE,SPACE,SPACE) //? -Help
++ BigMov r3, L4(H,e,l,p)
++ bl TransLineR3
++
++ b Prompt
++
++//.global CalcMemEnd
++CalcMemEnd:
++ CalcMemSize r1,r0,MEMORY_CONTROL_BASE //out: r0 - mem size
++ BigAdd2 r0,MEM_START //32 meg
++ mov pc,lr
++
++
++//rRamSector - start (rNum1)
++//rRamEnd - end (rNum2)
++Verify_Cmd:
++ mov r5,#CMD_VERIFY
++ b Burn1
++Verify2_Cmd:
++ mov r5,#CMD_VERIFY
++ b Burn2
++BurnAll_Cmd:
++ mov r5,#CMD_BURNALL
++ b Burn1
++Burn2_Cmd:
++ mov r5,#CMD_BURN
++Burn2:
++ BigMov r4,FLASH_BASE_ADDRESS+(16<<20)
++ b BurnContinue
++Burn_Cmd:
++ mov r5,#CMD_BURN
++Burn1:
++ BigMov r4,FLASH_BASE_ADDRESS
++BurnContinue:
++ tst rValidCnt,#F_NUM1_MASK
++ tstne rValidCnt,#F_NUM2_MASK
++ beq Invalid
++ tst rRamSector,#3
++ bne Invalid
++ tst rRamEnd,#3
++ bne Invalid
++ cmp rRamSector,rRamEnd
++ bhs Invalid
++ cmp rRamSector,#MEM_START
++ blo Invalid //br if rRamSector is below ram start,
++ bl CalcMemEnd
++ mov r1,r4
++ cmp rRamEnd,r0
++ bhi Invalid //br if rRamEnd is above ram end,
++ sub lr,rRamEnd,rRamSector
++ cmp lr,#f128j3a_SIZE
++ bhi Invalid
++
++ mvn r2,#0
++ tst rRamEnd,#1
++ strneb r2,[rRamEnd],#1
++ tst rRamEnd,#2
++ strneh r2,[rRamEnd],#2
++
++//1st verify that flash needs burned
++ mov lr,rRamSector
++1: ldr r2,[lr],#4
++ ldr r3,[r1],#4
++ cmp r2,r3
++ bne 2f
++ cmp lr,rRamEnd
++ blo 1b
++
++ cmp r5,#CMD_BURNALL
++ beq 3f
++ BigMov r0,L4(V,e,r,i)
++ bl Transmit1
++ BigMov r0,L4(f,i,e,d)
++ bl Transmit1
++ b Prompt
++2:
++ sub r1,r1,#4
++ cmp r5,#CMD_VERIFY
++ bne 3f
++ sub r0,lr,#4
++20:
++ bl Burn_error
++ b Prompt
++3:
++ mov rFlashSector,r1,LSR #18
++ mov rFlashSector,rFlashSector,LSL #18 //round to 256k boundary
++ add rRamSector,rRamSector,rFlashSector
++ sub rRamSector,rRamSector,r4
++ BigMov r3,MEMORY_CONTROL_BASE
++ tst rFlashSector,#1<<26
++ ldr r1,[r3,#MSC0]
++ movne r1,r1,LSR #16 //nCS1 being used for flash
++ tst r1,#1<<3 //bit 3 - 1 means 16 bit mode
++ adr r4,Burn_Rtn32
++ ldr r3,[r4]
++ BigMov r2,0xe58d5054 //NOTE: when 1st instruction of Burn_Rtn32 changes (or DBG_TEMP value), this must change as well
++ adrne r4,Burn_Rtn16
++
++ cmp r4,#MEM_START
++ bhs 10f
++//I must move the burn code, unless I'm only running from cache
++ cmp r2,r3
++ bne 10f
++ tst r1,#1<<3 //bit 3 - 1 means 16 bit mode
++ BigAdd r1,r0,(-0x1000+((DEBUG_BASE+DBG_START)&0xfe0)-32)
++ moveq r3,#((Burn_Rtn_End-Burn_Rtn32)+0x1f)&(~0x1f) //round to 32 byte (cache line)boundary
++ movne r3,#((Burn_Rtn_End-Burn_Rtn16)+0x1f)&(~0x1f) //round to 32 byte (cache line)boundary
++ add r2,r4,r3
++ sub r1,r1,r3
++ mov r0,r1
++4: ldr r3,[r4],#4
++ str r3,[r1],#4
++ cmp r4,r2
++ blo 4b
++
++ mov r4,r0
++5:
++ CP15_CF_INVAL_ILINE mcr,r4
++ add r4,r4,#32
++ cmp r4,r1
++ blo 5b
++
++ CP15_CF_INVAL_BTB mcr,r4
++
++ CP15_CF_DRAIN mcr,r4 //data cache is disabled, but it should still drain first
++ CPWAIT r1
++
++ BigMov rFlashBase,FLASH_BASE_ADDRESS
++ mov rRet,#0
++ blx r0
++ b 20b //unknow Man/dev Id if it returns from here
++
++10:
++//I'm running from ram, or from cache only
++ BigMov rFlashBase,FLASH_BASE_ADDRESS
++ adr rRet,11f
++ blx r4
++ b 20b //unknow Man/dev Id if it returns from here
++11: b Prompt
++
++
++
++
++//BurnRtn istr,ildr,mask,shift,inc,plait
++Burn_Rtn32:
++ BurnRtn str,ldr,0xffffffff,0,0,4,0
++Burn_Rtn16:
++#if 1
++ BigMov r0,FLASH_STATUS_CLEAR_CMD&0xffff
++ strh r0,[rFlashBase,#0]
++ delay
++ BigMov r0,FLASH_ID_CMD&0xffff
++ strh r0,[rFlashBase,#0]
++ delay
++ ldrh r2,[rFlashBase,#2]
++
++ BigMov r0,FLASH_READ_CMD&0xffff
++ strh r0,[rFlashBase,#0]
++ delayCnt r0,((40/10)*COUNT_MULT)
++ cmp r2,#0x16
++ cmpne r2,#0x17
++ cmpne r2,#0x18
++ beq 99f
++//(PLATFORM_TYPE==GAME_CONTROLLER_PLAITED_A1)
++ BurnRtn strh,ldrh, 0xffff,0,1,4,1 //the plait version (a1 jumpered to a high address line)
++99:
++ BurnRtn strh,ldrh, 0xffff,1,1,2,0 //the non-plait version (a1 correct)
++#else
++
++#if (PLATFORM_TYPE==GAME_CONTROLLER_PLAITED_A1)
++ BurnRtn strh,ldrh, 0xffff,0,1,4,1 //the plait version (a1 jumpered to a high address line)
++#else
++99:
++ BurnRtn strh,ldrh, 0xffff,1,1,2,0 //the non-plait version (a1 correct)
++#endif
++
++#endif
++
++Timeout:
++ BigMov r0,L4(T,i,m,e)
++ bl TransmitR
++ BigMov r0,L4(d,SPACE,o,u)
++ bl TransmitR
++ BigMov r0,L2(t,SPACE)
++ bl TransmitR
++
++ mov r0,rRamSector
++ mov r1,rFlashSector
++ ldr r2,[r0]
++ ldr r3,[r1]
++ bl Burn_error
++ b Burn_return
++
++ReturnError:
++ sub r0,r0,#4
++ sub r1,r1,#4
++ bl Burn_error
++ b Burn_return
++
++PrintSector:
++ mov r5,lr
++ bl TransmitR_CRLF
++ BigMov r0,L4(S,e,c,t)
++ bl TransmitR
++ BigMov r0,L3(o,r,SPACE)
++ bl TransmitR
++ mov r0,rFlashSector
++ bl PrintHexR
++ mov r0,#L1(SPACE)
++ bl TransmitR
++ mov r0,rRamSector
++ mov r1,rFlashSector
++ mov pc,r5
++
++PrintErasing:
++ mov r5,lr
++ BigMov r0,L4(E,r,a,s)
++ bl TransmitR
++ BigMov r0,L4(i,n,g,SPACE)
++ mov lr,r5
++ b TransmitR
++
++PrintProgramming:
++ mov r5,lr
++ BigMov r0,L4(P,r,o,g)
++ bl TransmitR
++ BigMov r0,L4(r,a,m,m)
++ bl TransmitR
++ BigMov r0,L4(i,n,g,SPACE)
++ bl TransmitR
++ mov r0,rRamSector
++ mov r1,rFlashSector
++ mov pc,r5
++
++PrintVerifying:
++ mov r5,lr
++ BigMov r0,L4(V,e,r,i)
++ bl TransmitR
++ BigMov r0,L4(f,y,i,n)
++ bl TransmitR
++ BigMov r0,L4(g,PERIOD,PERIOD,PERIOD)
++ bl TransmitR
++ mov r0,rRamSector
++ mov r1,rFlashSector
++ mov pc,r5
++
++PrintSuccess:
++ bl TransmitR_CRLF
++ BigMov r0,L4(S,u,c,c)
++ bl TransmitR
++ BigMov r0,L3(e,s,s)
++ bl TransmitR
++// b Burn_return
++
++Burn_return:
++ bl TransmitR_CRLF
++ bl WaitTxEmpty
++ movs rRet,rRet
++ CP15_CF_INVAL_BOTH mcreq,r1 //invalidate if return is reset vector
++ CPWAIT r1
++ mov pc,rRet
++
++Burn_error:
++ mov r8,lr
++ mov r5,r1
++ mov sl,r2
++ mov r7,r3
++ bl PrintHexR
++ mov r0,#L1(COLON)
++ bl TransmitR
++ mov r0,sl
++ bl PrintHexR
++ bl TransmitSPACER
++
++ mov r0,r5
++ bl PrintHexR
++ mov r0,#L1(COLON)
++ bl TransmitR
++ mov r0,r7
++ mov lr,r8
++ b PrintHexR
++
++ DEFINE_FLASH_GPIO_WAIT_FOR_IDLE
++
++
++WaitTxEmpty:
++1: ldr r1,[rUart,#UART_LSR]
++ ands r1,r1,#0x40
++ beq 1b
++ mov pc,lr //return
++
++TransmitSPACER:
++ mov r0,#L1(SPACE)
++ b TransmitR
++TransmitR_CRLF:
++ BigMov r1,L2(CR,LF)
++trR:
++ mov r0,r1
++//IN: r0 - character to transmit
++//OUT: r0 - last character transmitted, r1 - trashed
++TransmitR:
++1: ldr r1,[rUart,#UART_LSR]
++ ands r1,r1,#0x20
++ beq 1b
++ mov r1,r0
++ and r1,r1,#0xff
++ str r1,[rUart,#UART_THR]
++ movs r1,r0,LSR #8
++ bne trR
++ mov pc,lr //return
++//IN: r0 - value to print
++//OUT: r0-r4 trashed
++PrintHexR:
++ mov r2,#8
++ mov r4,r0
++ mov r3,lr
++1: mov r4,r4,ROR #28
++ and r0,r4,#0xf
++ cmp r0,#0xA
++ addcs r0,r0,#L1(A)-0x0a
++ addcc r0,r0,#L1(0)
++ bl TransmitR
++ subs r2,r2,#1
++ bne 1b
++ mov pc,r3
++
++Burn_Rtn_End:
++
++
++SSID_Cmd:
++ BigMov r0,L4(I,d,COLON,SPACE)
++ bl Transmit1
++ bl CalcMemEnd
++ BigAdd r5,r0,(-0x1000+((DEBUG_BASE+DBG_START)&0xfff)-32)
++ mov r6,#31
++1: bl Receive
++ beq 1b //br on timeout
++ cmp r0,#CR
++ beq 2f
++ strb r0,[r5],#1
++ bl Transmit1
++ subs r6,r6,#1
++ bne 1b
++2: mov r0,#0
++ strb r0,[r5],#1
++ b Prompt
++
++MAC_Cmd:
++ mov r2,#FUNC_REQ_MAC
++ b join_cmd
++Download_Wireless_Cmd:
++ tst rValidCnt,#F_NUM1_MASK
++ beq Invalid
++ tst rNum1,#3
++ bne Invalid
++ cmp rNum1,#MEM_START
++ bcc Invalid //br if rNum1 is below ram start,
++ //NOTE: arm sets the carry to the opposite of most processors on subtract, compare
++ mov r2,#FUNC_REQ_DLW
++join_cmd:
++ bl TryRoutine
++ ldmia sp,{rPrevNum1,rUart,rDBG}
++ bl SetupATAG //dlw is now overwriting ATAG space, so set it again
++ b Prompt
++
++//struct tag_mem32 {
++// u32 size;
++// u32 start; /* physical start address */
++//};
++
++//out: r2,r7 - saved, r0 - CalcMemEnd return value
++SetupATAG:
++ mov r3,lr
++ bl CalcMemEnd
++ mov lr,r3
++ BigMov r1,TAGGED_LIST
++ BigMov r3,2
++ BigMov r4,ATAG_CORE
++ BigMov r5,4
++ BigEor r6,r4,(ATAG_MEM^ATAG_CORE)
++ stmia r1!,{r3,r4,r5,r6}
++ BigMov r4,MEM_START
++ BigMov r5,0
++ sub r3,r0,r4
++ stmia r1,{r3,r4,r5}
++ mov pc,lr
++
++
++Gl_Cmd:
++ mov r2,#FUNC_REQ_PIC
++ bl TryRoutine
++ ldmia sp,{rPrevNum1,rUart,rDBG}
++
++ BigMov r1,MACH_TYPE_SCANPASS
++ str r1,[rDBG,#DBG_R1]
++ mov r2,#FUNC_REQ_GL
++ bl TryRoutine
++ ldmia sp,{rPrevNum1,rUart,rDBG}
++ movs rNum1,r4
++ bne Go_Cmd
++ b Prompt
++
++//r2- function select
++TryRoutine:
++ mov r10,#0
++ mov r7,lr
++ bl TryRoutine1
++ b Invalid
++//r10- RCSR
++//r2- function select
++//r7- main return
++//lr- error return
++TryRoutine1:
++ adr r0,MiniDebugEnd
++ ldr r1,[r0]
++ BigMov r3,0xe1a08000
++ cmp r1,r3
++ movne pc,lr //failure return
++ bl SetupATAG //out: r0 - calcMemEnd return value
++ mov lr,r7
++
++ BigAdd r1,r0,(-0x1000+((DEBUG_BASE+DBG_START)&0xfff)-32) //@ssid
++ mov r0,r1
++ stmdb r0!,{rPrevNum1,rUart,rDBG}
++ mov sp,r0
++ mov fp,r0
++ mov r0,rNum1
++ adr r4,MiniDebugEnd
++ mov r3,#DEF_DISPLAY_INDEX
++ b HeadStart
++
++ .ifdef __ARMASM
++ DUP 6,0xffffffff
++ align 256
++ .else
++ .balignl 256,0xffffffff
++ .endif
++
++MiniDebugEnd:
++//This is defined in head.S or minidebug.lds
++//HeadStart:
+diff -u -r --new-file u-boot-1.1.2/cpu/pxa/ministart.S u-boot-1.1.2-neon/cpu/pxa/ministart.S
+--- u-boot-1.1.2/cpu/pxa/ministart.S 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/cpu/pxa/ministart.S 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,270 @@
++/*
++ * armboot - Startup Code for XScale
++ *
++ * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
++ * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
++ * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
++ * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
++ * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
++ * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
++ * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <config.h>
++#include <version.h>
++#include <asm/arch/pxaMacro.h>
++
++#define Mode_SVC 0x13
++#define NoIntsMask 0xc0
++.globl _bss_start
++.globl _bss_end
++
++//defined globals
++.globl HeadStart
++.globl _armboot_start
++
++//r3 - display type
++HeadStart:
++ mov r8,r0 //there is a check for this instruction before jumping here
++
++// ********************************************************************
++// Set processor into Supervisior mode (SVC) and disable IRQ & FIQ
++//
++ mrs r0, CPSR
++ bic r0, r0,#0x1f
++ orr r0, r0,#(Mode_SVC | NoIntsMask)
++ msr cpsr_c, r0
++//exit SDS, if currently active
++ msr SPSR, r0
++ adr lr,1f
++ movs pc,lr
++1:
++ b relocate
++// ********************************************************************
++_armboot_start:
++_TEXT_BASE: .word TEXT_BASE
++
++_start_armboot: .word start_armboot
++/*
++ * These are defined in the board-specific linker script.
++ */
++_bss_start: .word __bss_start
++_bss_end: .word _end
++
++#ifdef CONFIG_USE_IRQ
++/* IRQ stack memory (calculated at run-time) */
++.globl IRQ_STACK_START
++IRQ_STACK_START:
++ .word 0x0badc0de
++
++/* IRQ stack memory (calculated at run-time) */
++.globl FIQ_STACK_START
++FIQ_STACK_START:
++ .word 0x0badc0de
++#endif
++
++relocate: /* relocate U-Boot to RAM */
++ adr r0, HeadStart /* r0 <- current position of code */
++ bic r0,r0,#0xff
++ bic r0,r0,#0xff00 //64k aligned
++ ldr r1, _TEXT_BASE
++ cmp r0, r1 /* don't reloc during debug */
++ beq stack_setup
++
++ ldr r2, _bss_start
++
++copy_loop:
++ ldmia r0!, {r3-r10} /* copy from source address [r0] */
++ stmia r1!, {r3-r10} /* copy to target address [r1] */
++ cmp r1, r2 /* until dest end addreee [r2] */
++ ble copy_loop
++
++ /* Set up the stack */
++stack_setup:
++ ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
++ BigSub2 r0,(CFG_MALLOC_LEN+CFG_GBL_DATA_SIZE+CFG_MMU_SPACE_RESERVED) //malloc area,bdinfo
++#ifdef CONFIG_USE_IRQ
++ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
++#endif
++ sub sp, r0, #12 /* leave 3 words for abort-stack */
++
++clear_bss:
++ ldr r0, _bss_start /* find start of bss segment */
++ ldr r1, _bss_end /* stop here */
++ mov r2, #0x00000000 /* clear */
++
++clbss_l:str r2, [r0] /* clear loop... */
++ add r0, r0, #4
++ cmp r0, r1
++ bne clbss_l
++ bl dcache_enable
++
++ ldr pc, _start_armboot
++
++
++FlushCache:
++ CP15_CONTROL mrc,r0
++ tst r0, #4 //is data cache enabled
++ beq 2f
++// b 2f
++ mov r1, #2048
++ add r0,pc,#0x20000 //make sure I don't alloc a line in this subroutine
++ BigBic2 r0, 0xffff
++1: CP15_CF_ALLOC_LINE mcr,r0
++ add r0, r0, #0x20
++ subs r1, r1, #1
++ bne 1b
++
++ CP15_CF_DRAIN mcr,r0
++ CPWAIT r0
++2: CP15_CF_INVAL_BOTH mcr,r0
++ CPWAIT r0
++ mov pc, lr
++
++
++
++//void dcache_disable (void)
++.globl dcache_disable
++dcache_disable:
++ mov r3,lr
++ bl FlushCache
++ CP15_CONTROL mrc,r1
++
++ BigBic2 r1, 0x2805 //disable high vector, branch target buffer, disable data cache, MMU
++ .balignl 32,0xe1a00000 //cacheline boundary (32 bytes)
++ //Needed so that if new flash is burnt
++ //and flash != ram copy,
++ //mov pc, r3 will be in cache and execute correctly
++ //(r3 is 0) return to the reset vector
++ CP15_CONTROL mcr,r1
++ CPWAIT r0
++ mov pc, r3
++
++
++//int dcache_status (void)
++.globl dcache_status
++dcache_status:
++ CP15_CONTROL mrc,r0 //get the control register
++ and r0,r0,#1
++ mov pc,lr
++
++#define MEM_START1 0xa0000000
++#define MEM_END1 0xa4000000
++//void dcache_enable (void)
++.globl dcache_enable
++dcache_enable:
++ stmdb sp!,{r5,r6,lr}
++ bl FlushCache
++#if !defined(CFG_MMU_SPACE_RESERVED) || (CFG_MMU_SPACE_RESERVED<(1<<14))
++ mov r0,#1<<15 //16k plus alignment of 16k
++ bl malloc
++ add r6,r0,#(1<<14) //16k alignment
++ BigBic2 r6,(1<<14)-1
++#else
++ ldr r6, _TEXT_BASE /* upper 128 KiB: relocated uboot */
++ BigSub2 r6,(CFG_MMU_SPACE_RESERVED) //malloc area,bdinfo
++#endif
++ mov r2,r6
++ add r5,r6,#(1<<14) //16k 1st level page table
++ BigMov r0,0x0402 //section descriptor, ap-01, privileged r/w
++ //map virt to phys 1-to-1, non-cache, non-bufferable
++1: str r0,[r2],#4
++ add r0,r0,#1<<20
++ cmp r2,r5
++ bne 1b
++
++
++ mov r3,#MEM_END1
++ add r5,r6,r3,LSR #(20-2)
++ add r1,r6,#(MEM_START1>>20)<<2
++ BigMov r0,(MEM_START1&0xfff00000)+0x040A //cacheable (write through)
++2: str r0,[r1],#4
++ cmp r1,r5
++ addne r0,r0,#1<<20
++ bne 2b
++
++ BigMov r0,0xffffffff
++ CP15_DACR mcr,r0
++
++ CP15_TTBR mcr,r6
++//enable MMU
++ CP15_TLB_UNLOCK_I mcr,r0
++ CP15_TLB_UNLOCK_D mcr,r0
++ CP15_TLB_INVAL_BOTH mcr,r0
++
++ CP15_CONTROL mrc,r1 //get the control register
++ BigOrr2 r1,0x201 // enable MMU, r bit
++ BigBic2 r1,0x100 // disable S bit, ap -0 means read only by all
++ CPWAIT r0
++ CP15_CONTROL mcr,r1 //set the control register
++ CPWAIT r0
++
++//enable the instruction cache
++ CP15_CF_UNLOCK_I mcr,r0
++// CP15_CF_INVAL_I mcr,r0 //I might be running from cache only, don't invalidate
++
++ orr r1,r1,#0x1000 //set bit 12 -- the I bit
++ CP15_CONTROL mcr,r1 //set the control register
++ CPWAIT r0
++
++//enable the data cache
++// CP15_CF_UNLOCK_D mcr,r0
++ CP15_CF_INVAL_D mcr,r0 //this will also drain write buffer
++ CP15_CF_DRAIN mcr,r0 //make sure it is drained just to be very safe
++
++ orr r1,r1,#0x4 //set bit 4 -- the D bit
++ CP15_CONTROL mcr,r1 //set the control register
++ CPWAIT r0
++
++ BigMov r0,0x3fff
++ CP15_CP_ACCESS mcr,r0 //enable access to all coprocessors
++ ldmia sp!,{r5,r6,pc}
++
++
++
++/****************************************************************************/
++/* */
++/* Reset function: the PXA250 doesn't have a reset function, so we have to */
++/* perform a watchdog timeout for a soft reset. */
++/* */
++/****************************************************************************/
++.globl reset_cpu
++ /* FIXME: this code is PXA250 specific. How is this handled on */
++ /* other XScale processors? */
++
++reset_cpu:
++ BigMov r0,0x40a00000 //OSTIMER_BASE
++ /* We set OWE:WME (watchdog enable) and wait until timeout happens */
++
++ ldr r1, [r0, #OWER]
++ orr r1, r1, #0x0001 /* bit0: WME */
++ str r1, [r0, #OWER]
++
++ /* OS timer does only wrap every 1165 seconds, so we have to set */
++ /* the match register as well. */
++
++ ldr r1, [r0, #OSCR] /* read OS timer */
++ add r1, r1, #0x800 /* let OSMR3 match after */
++ add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
++ str r1, [r0, #OSMR3]
++
++reset_endless:
++ b reset_endless
+diff -u -r --new-file u-boot-1.1.2/cpu/pxa/mmc.c u-boot-1.1.2-neon/cpu/pxa/mmc.c
+--- u-boot-1.1.2/cpu/pxa/mmc.c 2003-10-16 01:53:52.000000000 +0200
++++ u-boot-1.1.2-neon/cpu/pxa/mmc.c 2007-08-11 21:07:20.000000000 +0200
+@@ -27,6 +27,7 @@
+ #include <asm/errno.h>
+ #include <asm/arch/hardware.h>
+ #include <part.h>
++#include <command.h>
+
+ #ifdef CONFIG_MMC
+
+@@ -47,9 +48,19 @@
+ static uchar mmc_buf[MMC_BLOCK_SIZE];
+ static mmc_csd_t mmc_csd;
+ static int mmc_ready = 0;
++static int isSD = 0 ;
++static int startBlock = 0 ;
++static ushort RCA = MMC_DEFAULT_RCA ;
++static struct partition part ;
+
++static void stop_clock( void )
++{
++ MMC_STRPCL = MMC_STRPCL_STOP_CLK;
++ MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF;
++ while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF));
++}
+
+-static uchar *
++uchar *
+ /****************************************************/
+ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)
+ /****************************************************/
+@@ -59,9 +70,8 @@
+ int words, i;
+
+ debug("mmc_cmd %x %x %x %x\n", cmd, argh, argl, cmdat);
+- MMC_STRPCL = MMC_STRPCL_STOP_CLK;
+- MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF;
+- while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF));
++ stop_clock();
++
+ MMC_CMD = cmd;
+ MMC_ARGH = argh;
+ MMC_ARGL = argl;
+@@ -71,9 +81,10 @@
+ while (!(MMC_I_REG & MMC_I_REG_END_CMD_RES));
+
+ status = MMC_STAT;
+- debug("MMC status %x\n", status);
++ debug("MMC status %lx\n", status);
+ if (status & MMC_STAT_TIME_OUT_RESPONSE)
+ {
++ printf( "mmc_cmd timeout: cmd: 0x%x, args: 0x%04x%04x, status 0x%lx\n", cmd, argh, argl, status );
+ return 0;
+ }
+
+@@ -85,7 +96,7 @@
+ break;
+
+ case MMC_CMDAT_R2:
+- words = 8;
++ words = 9;
+ break;
+
+ default:
+@@ -109,6 +120,22 @@
+ return resp;
+ }
+
++static void mmc_setblklen( ulong blklen )
++{
++ static ulong prevLen = -1UL ;
++ if( blklen != prevLen )
++ {
++ ushort argh, argl ;
++
++ argh = blklen >> 16;
++ argl = blklen & 0xffff;
++
++ /* set block len */
++ mmc_cmd( MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1);
++ prevLen = blklen ;
++ }
++}
++
+ int
+ /****************************************************/
+ mmc_block_read(uchar *dst, ulong src, ulong len)
+@@ -117,20 +144,18 @@
+ uchar *resp;
+ ushort argh, argl;
+ ulong status;
++ unsigned char volatile *rxFIFO = (unsigned char *)&(MMC_RXFIFO);
+
+ if (len == 0)
+ {
+ return 0;
+ }
+
+- debug("mmc_block_rd dst %lx src %lx len %d\n", (ulong)dst, src, len);
++ debug("mmc_block_rd dst %lx src %lx len %ld\n", (ulong)dst, src, len);
+
+- argh = len >> 16;
+- argl = len & 0xffff;
+-
+- /* set block len */
+- resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1);
++ mmc_setblklen( len );
+
++ src += (startBlock*MMC_BLOCK_SIZE);
+ /* send read command */
+ argh = src >> 16;
+ argl = src & 0xffff;
+@@ -147,15 +172,14 @@
+ {
+ if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ)
+ {
+- *dst++ = MMC_RXFIFO;
+- len--;
+- }
+- status = MMC_STAT;
+- if (status & MMC_STAT_ERRORS)
+- {
+- printf("MMC_STAT error %lx\n", status);
+- return -1;
++ int i, bytes = min(32,len);
++ len -= bytes;
++
++ for (i=0; i<bytes; i++)
++ *dst++ = *rxFIFO ;
+ }
++ else if (MMC_STAT & MMC_STAT_ERRORS)
++ break;
+ }
+ MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE;
+ while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE));
+@@ -338,7 +362,7 @@
+ aligned_end = mmc_block_address & end;
+
+ /* all block aligned accesses */
+- debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
++ debug("src %p dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+ if (part_start)
+ {
+@@ -357,22 +381,22 @@
+ dst += part_len;
+ src += part_len;
+ }
+- debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
++ debug("src %p dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+ for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size)
+ {
+- debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
++ debug("al src %p dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+ if ((mmc_block_write(dst, (uchar *)src, mmc_block_size)) < 0)
+ {
+ return -1;
+ }
+ }
+- debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
++ debug("src %p dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+ if (part_end && dst < end)
+ {
+- debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
++ debug("pe src %p dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
+ src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
+ if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0)
+ {
+@@ -392,13 +416,324 @@
+ mmc_bread(int dev_num, ulong blknr, ulong blkcnt, ulong *dst)
+ /****************************************************/
+ {
++ debug( "read %lu blocks at block #%lu\n", blkcnt, blknr );
++
++ if( 0 < blkcnt )
++ {
++ if( 0 != getenv( "mblock" ) )
++ {
+ int mmc_block_size = MMC_BLOCK_SIZE;
+ ulong src = blknr * mmc_block_size + CFG_MMC_BASE;
+
+ mmc_read(src, (uchar *)dst, blkcnt*mmc_block_size);
++ }
++ else
++ {
++ ulong src = (blknr+startBlock) * MMC_BLOCK_SIZE ;
++ ulong status ;
++ uchar *dstb = (uchar *)dst ;
++ unsigned char volatile *rxFIFO = (unsigned char *)&(MMC_RXFIFO);
++
++ MMC_RDTO = 0xffff;
++ MMC_BLKLEN = MMC_BLOCK_SIZE ;
++ MMC_NOB = blkcnt ;
++
++ mmc_setblklen( MMC_BLOCK_SIZE );
++ mmc_cmd( MMC_CMD_RD_BLK_MULTI,
++ src >> 16,
++ src & 0xFFFF,
++ MMC_CMDAT_R1|MMC_CMDAT_READ|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN );
++
++ // read the data
++ for( blknr = 0 ; blknr < blkcnt ; blknr++ )
++ {
++ unsigned len = MMC_BLOCK_SIZE ;
++
++ while (len)
++ {
++ int i ;
++ MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ;
++ while( (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) == 0 )
++ {
++ }
++
++ for (i = 0; i < 32 ; i++ )
++ {
++ *dstb++ = *rxFIFO ;
++ }
++ len -= 32 ;
++ }
++ } // for each block
++
++ MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE;
++ while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE));
++ status = MMC_STAT;
++ if (status & MMC_STAT_ERRORS)
++ {
++ printf("MMC_STAT error %lx\n", status);
++ return -1;
++ }
++// printf( "completed mread... now stop\n" );
++
++ mmc_cmd( MMC_CMD_STOP, 0, 0, MMC_CMDAT_R1);
++
++ } // multi-block read
++ } // or why bother?
+ return blkcnt;
+ }
+
++static void dumpResponse( uchar *resp, unsigned bytes )
++{
++ debug( "rsp: " );
++ if( resp )
++ {
++ while( bytes-- )
++ debug( "%02X ", *resp++ );
++ debug( "\n" );
++ }
++ else
++ debug( "NULL\n" );
++}
++
++int SDCard_test( void )
++{
++ unsigned short response ;
++ unsigned long ignore ;
++ unsigned char *resp ;
++
++ mmc_cmd(0, 0, 0, 0);
++
++ resp = mmc_cmd(SD_APP_CMD55, 0, 0, MMC_CMDAT_R1);
++ if( !resp )
++ {
++ printf( "SDInitErr1\n" );
++ return -ENODEV ;
++ }
++
++ resp = mmc_cmd(SD_APP_CMD41, 0x0020, 0, MMC_CMDAT_INIT|MMC_CMDAT_R1);
++ if( !resp )
++ {
++ printf( "SDInitErr2\n" );
++ return -ENODEV ;
++ }
++
++ memcpy( &response, resp, sizeof( response ) );
++
++ while (response != 0x3f80)//continue doing ACMD1 until busy bit in response is set
++ {
++ //CMD55 APP_CMD
++ MMC_STRPCL = 0x00000001;//stop clock
++ while ((MMC_STAT & 0x00000100) == 0x00000100); //wait for clock to stop
++ MMC_CMD = 0x00000037;//CMD55 index APP_CMD
++ MMC_ARGH = 0x00000000;//relative card address 0x0
++ MMC_ARGL = 0x00000000;//stuff bits
++ MMC_CMDAT = 0x00000001;//expect response 1
++ MMC_STRPCL = 0x00000002;//start clock
++ while ((MMC_STAT & 0x00002000) == 0x00000000);//wait for end_cmd_res
++ //read response FIFO
++ response = MMC_RES & 0x0000ffff ;
++ ignore = MMC_RES ;
++ ignore = MMC_RES ;
++
++ //ACMD41
++ MMC_STRPCL = 0x00000001;//stop clock
++ while ((MMC_STAT & 0x00000100) == 0x00000100); //wait for clock to stop
++ MMC_CMD = 0x00000029;//ACMD41 index SD_APP_SEND_OP_COND
++ MMC_ARGH = 0x00000020;//set voltage limit of system in command argument
++ MMC_ARGL = 0x00000000;
++ MMC_CMDAT = 0x00000003;//expect response 3
++ MMC_STRPCL = 0x00000002;//start clock
++ while ((MMC_STAT & 0x00002000) == 0x00000000);//wait for end_cmd_res
++
++ //read response FIFO
++ response = MMC_RES & 0x0000ffff ;
++ ignore = MMC_RES ;
++ ignore = MMC_RES ;
++ }
++
++ return 0 ;
++}
++
++#ifdef DEBUG
++static void print_mmc_csd( struct mmc_csd *csd )
++{
++ printf( "ecc: %u\n", csd->ecc );
++ printf( "file_format: %u\n", csd->file_format );
++ printf( "tmp_write_protect: %u\n", csd->tmp_write_protect );
++ printf( "perm_write_protect: %u\n", csd->perm_write_protect );
++ printf( "copy: %u\n", csd->copy );
++ printf( "file_format_grp: %u\n", csd->file_format_grp );
++ printf( "content_prot_app: %u\n", csd->content_prot_app );
++ printf( "rsvd3: %u\n", csd->rsvd3 );
++ printf( "write_bl_partial: %u\n", csd->write_bl_partial );
++ printf( "write_bl_len: %u\n", csd->write_bl_len );
++ printf( "r2w_factor: %u\n", csd->r2w_factor );
++ printf( "default_ecc: %u\n", csd->default_ecc );
++ printf( "wp_grp_enable: %u\n", csd->wp_grp_enable );
++ printf( "wp_grp_size: %u\n", csd->wp_grp_size );
++ printf( "erase_grp_mult: %u\n", csd->erase_grp_mult );
++ printf( "erase_grp_size: %u\n", csd->erase_grp_size );
++ printf( "c_size_mult1: %u\n", csd->c_size_mult1 );
++ printf( "vdd_w_curr_max: %u\n", csd->vdd_w_curr_max );
++ printf( "vdd_w_curr_min: %u\n", csd->vdd_w_curr_min );
++ printf( "vdd_r_curr_max: %u\n", csd->vdd_r_curr_max );
++ printf( "vdd_r_curr_min: %u\n", csd->vdd_r_curr_min );
++ printf( "c_size: %u\n", csd->c_size );
++ printf( "rsvd2: %u\n", csd->rsvd2 );
++ printf( "dsr_imp: %u\n", csd->dsr_imp );
++ printf( "read_blk_misalign: %u\n", csd->read_blk_misalign );
++ printf( "write_blk_misalign: %u\n", csd->write_blk_misalign );
++ printf( "read_bl_partial: %u\n", csd->read_bl_partial );
++ printf( "read_bl_len: %u\n", csd->read_bl_len );
++ printf( "ccc: %u\n", csd->ccc );
++ printf( "tran_speed %u\n", csd->tran_speed );
++ printf( "nsac; %u\n", csd->nsac );
++ printf( "taac; %u\n", csd->taac );
++ printf( "rsvd1: %u\n", csd->rsvd1 );
++ printf( "spec_vers: %u\n", csd->spec_vers );
++ printf( "csd_structure: %u\n", csd->csd_structure );
++}
++#endif
++
++#define DOS_PART_MAGIC_OFFSET 0x1fe
++#define DOS_FS_TYPE_OFFSET 0x36
++#define MSDOS_LABEL_MAGIC1 0x55
++#define MSDOS_LABEL_MAGIC2 0xAA
++
++struct bpb { // see http://staff.washington.edu/dittrich/misc/fatgen103.pdf
++ unsigned char jump[3];
++ char oemName[8];
++ unsigned short bytesPerSector ;
++ unsigned char sectorsPerCluster ;
++ unsigned short reservedSectorCount ;
++ unsigned char numFats ;
++ unsigned short rootEntCount ;
++ unsigned short totalSec16 ;
++ unsigned char media ; // 0xF8
++ unsigned short fatSz16 ;
++ unsigned short secPerTrack ;
++ unsigned short numHeads ;
++ unsigned long hiddenSectors ;
++ unsigned long totalSectors32 ;
++ unsigned char driveNum ;
++ unsigned char reserved1 ; // 0x00
++ unsigned char bootSig ; // 0x29
++ unsigned long volumeId ;
++ char volumeLabel[11];
++ char fileSysType[8];
++} __attribute__((packed));
++
++#define isprint(__c) (((__c)>=0x20)&&((__c)<=0x7f))
++
++static int find_mbr( int max_blocks )
++{
++ int i ;
++ ulong addr = 0 ;
++
++printf( "---- searching %d blocks for MBR\n", max_blocks );
++
++ for( i = 0 ; i < 10 ; i++, addr += MMC_BLOCK_SIZE )
++ {
++ uchar data[MMC_BLOCK_SIZE];
++ if( 0 == mmc_block_read(data, addr, sizeof(data) ))
++ {
++ memcpy( &part, data+0x1be, sizeof(part));
++ if( ( data[DOS_PART_MAGIC_OFFSET] == MSDOS_LABEL_MAGIC1 )
++ &&
++ ( data[DOS_PART_MAGIC_OFFSET + 1] == MSDOS_LABEL_MAGIC2 ) )
++ {
++ if( ( ('\x00' == part.boot_ind )
++ ||
++ ('\x80' == part.boot_ind ) )
++ &&
++ ( 10 > part.head )
++ &&
++ ( part.end_head >= part.head ) )
++ {
++ printf( "partition info found at block %u\n", i );
++ printf( "boot:%02x head:%02x sec:%02x cyl:%02x sys:%02x endh:%02x ends:%02x endc:%02x start:%08x, count:%08x\n",
++ part.boot_ind, part.head, part.sector, part.cyl,
++ part.sys_ind, part.end_head, part.end_sector, part.end_cyl,
++ part.start_sect, part.nr_sects );
++ printf( "MBR found at block %d\n", i );
++ return part.start_sect ;
++ }
++ else {
++ struct bpb const *bootParams = (struct bpb *)data ;
++ unsigned j ;
++ for( j = 0 ; j < sizeof(data); j++ )
++ {
++ if( 0 == ( j & 0x0f ) )
++ printf( "%04x ", j );
++ printf( "%02x ", data[j] );
++ if( 7 == ( j & 7 ) )
++ printf( " " );
++ if( 0x0f == ( j & 0x0f ) )
++ {
++ unsigned b ;
++ for( b = j-15 ; b <= j ; b++ )
++ {
++ uchar c = data[b];
++ if( isprint(c) )
++ printf( "%c", c );
++ else
++ printf( "." );
++ if( 7 == ( b & 7 ) )
++ printf( " " );
++ }
++ printf( "\n" );
++ }
++ }
++ printf( "Invalid MBR\n" );
++ printf( "---> Boot Parameter block\n" );
++ printf( "jump %02x %02x %02x\n", bootParams->jump[0],bootParams->jump[1],bootParams->jump[2]);
++ printf( "bytesPerSector: %04x\n", bootParams->bytesPerSector );
++ printf( "sectorsPerCluster: %02x\n", bootParams->sectorsPerCluster );
++ printf( "reservedSectors %04x\n", bootParams->reservedSectorCount );
++ printf( "numFats: %02x\n", bootParams->numFats );
++ printf( "rootEntCount: %04x\n", bootParams->rootEntCount );
++ printf( "totalSec16: %04x\n", bootParams->totalSec16 );
++ printf( "media: %02x\n", bootParams->media );
++ printf( "fatsz16: %04x", bootParams->fatSz16 );
++ printf( "secPerTrack: %04x\n", bootParams->secPerTrack );
++ printf( "numHeads = %04x\n", bootParams->numHeads );
++ printf( "hidden = %08lx\n", bootParams->hiddenSectors );
++ printf( "totalSec32 = %08lx\n", bootParams->totalSectors32 );
++ printf( "drive #%u\n", bootParams->driveNum );
++ printf( "reserved1: %02x\n", bootParams->reserved1 );
++ printf( "bootSig: %02x\n", bootParams->bootSig );
++ printf( "volume: %08lx\n", bootParams->volumeId );
++ part.boot_ind = 0 ;
++ part.head = 0 ;
++ part.sector = 2 ;
++ part.cyl = 0 ;
++ part.sys_ind = 6 ;
++ part.end_head = bootParams->numHeads ;
++ part.end_sector = 0xe0 ;
++ part.end_cyl = 0xc9 ;
++ part.start_sect = 0 ;
++ part.nr_sects = bootParams->totalSectors32 ;
++ printf( "partition info found at block %u\n", i );
++ printf( "boot:%02x head:%02x sec:%02x cyl:%02x sys:%02x endh:%02x ends:%02x endc:%02x start:%08x, count:%08x\n",
++ part.boot_ind, part.head, part.sector, part.cyl,
++ part.sys_ind, part.end_head, part.end_sector, part.end_cyl,
++ part.start_sect, part.nr_sects );
++ printf( "MBR found at block %d\n", i );
++ return 0 ;
++ }
++ }
++ }
++ else
++ {
++ printf( "!!! Error reading mmc block %u\n", i );
++ break;
++ }
++ }
++
++ printf( "MBR not found!\n" );
++ return -1 ;
++}
++
+ int
+ /****************************************************/
+ mmc_init(int verbose)
+@@ -406,7 +741,8 @@
+ {
+ int retries, rc = -ENODEV;
+ uchar *resp;
+-
++ mmc_cid_t *cid ;
++ mmc_csd_t *csd ;
+ #ifdef CONFIG_LUBBOCK
+ set_GPIO_mode( GPIO6_MMCCLK_MD );
+ set_GPIO_mode( GPIO8_MMCCS0_MD );
+@@ -419,23 +755,63 @@
+ MMC_RESTO = MMC_RES_TO_MAX;
+ MMC_SPI = MMC_SPI_DISABLE;
+
++ if( 0 == SDCard_test() )
++ {
++ printf( "SD card detected!\n" );
++ isSD = 1 ;
++ }
++ else
++ {
++ isSD = 0 ;
++
+ /* reset */
+- retries = 10;
+- resp = mmc_cmd(0, 0, 0, 0);
++ mmc_cmd(0, 0, 0, 0);
+ resp = mmc_cmd(1, 0x00ff, 0xc000, MMC_CMDAT_INIT|MMC_CMDAT_BUSY|MMC_CMDAT_R3);
+- while (retries-- && resp && !(resp[4] & 0x80))
++ if( 0 == resp )
++ {
++ printf( "MMC CMD1 error\n" );
++ return -1 ;
++ }
++
++ printf( "init: " ); dumpResponse( resp, 6 );
++ retries = 0 ;
++ do
+ {
+- debug("resp %x %x\n", resp[0], resp[1]);
+- udelay(50);
++ udelay(100);
+ resp = mmc_cmd(1, 0x00ff, 0xff00, MMC_CMDAT_BUSY|MMC_CMDAT_R3);
++ debug( "cmd1: " ); dumpResponse( resp, 6 );
++ retries++ ;
++ } while( resp && ( 0 == ( resp[4] & 0x80 ) ) );
++
++ if( 0 == resp )
++ {
++ printf( "MMC CMD1 error2\n" );
++ return -1 ;
++ }
++
++ do {
++ udelay(100);
++ resp = mmc_cmd(1, 0x00ff, 0xff00, MMC_CMDAT_BUSY|MMC_CMDAT_R3);
++ debug( "cmd1: " ); dumpResponse( resp, 6 );
++ retries++ ;
++ } while( resp && ( 0 != ( resp[4] & 0x80 ) ) );
++
++ printf( "after busy: %s, %d retries\n",
++ resp ? "have INIT response"
++ : "no INIT response",
++ retries );
+ }
+
+ /* try to get card id */
+ resp = mmc_cmd(2, 0, 0, MMC_CMDAT_R2);
+- if (resp)
++ if( !resp )
+ {
++ printf( "Bad CMDAT_R2 response\n" );
++ return -1 ;
++ }
++
+ /* TODO configure mmc driver depending on card attributes */
+- mmc_cid_t *cid = (mmc_cid_t *)resp;
++ cid = (mmc_cid_t *)resp;
+ if (verbose)
+ {
+ printf("MMC found. Card desciption is:\n");
+@@ -449,6 +825,12 @@
+ printf("Month = %d\n",cid->month);
+ printf("Year = %d\n",1997 + cid->year);
+ }
++ sprintf(mmc_dev.product,"%s",cid->name);
++ sprintf(mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x",
++ cid->id[0], cid->id[1], cid->id[2],
++ cid->sn[0], cid->sn[1], cid->sn[2]);
++ sprintf(mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev);
++
+ /* fill in device description */
+ mmc_dev.if_type = IF_TYPE_MMC;
+ mmc_dev.dev = 0;
+@@ -457,30 +839,118 @@
+ /* FIXME fill in the correct size (is set to 32MByte) */
+ mmc_dev.blksz = 512;
+ mmc_dev.lba = 0x10000;
+- sprintf(mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x",
+- cid->id[0], cid->id[1], cid->id[2],
+- cid->sn[0], cid->sn[1], cid->sn[2]);
+- sprintf(mmc_dev.product,"%s",cid->name);
+- sprintf(mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev);
+ mmc_dev.removable = 0;
+ mmc_dev.block_read = mmc_bread;
+
+ /* MMC exists, get CSD too */
+ resp = mmc_cmd(MMC_CMD_SET_RCA, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1);
+- resp = mmc_cmd(MMC_CMD_SEND_CSD, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R2);
+- if (resp)
++
++ if( resp )
+ {
+- mmc_csd_t *csd = (mmc_csd_t *)resp;
+- memcpy(&mmc_csd, csd, sizeof(csd));
+- rc = 0;
+- mmc_ready = 1;
+- /* FIXME add verbose printout for csd */
++ if( isSD )
++ RCA = ((ushort)resp[4] << 8 ) | resp[3];
++ else
++ RCA = MMC_DEFAULT_RCA ;
+ }
++ else
++ {
++ printf( "no SET_RCA response\n" );
++ return -1 ;
+ }
+
++#if 0
++/*
++ * According to a Toshiba doc, the following is supposed to give
++ * the size of the 'protected' area (so we can ignore it).
++
++ * Unfortunately, I can't get the numbers to add up, so we walk
++ * til we find an MBR instead.
++ */
++ if( isSD )
++ {
++ printf( "sending CMD55\n" );
++ resp = mmc_cmd(SD_APP_CMD55, RCA, 0, MMC_CMDAT_R1);
++ if( !resp )
++ {
++ printf( "Error 0x%04x sending APP CMD\n", MMC_STAT );
++ return -1 ;
++ }
++ else
++ {
++ printf( "have CMD55 response\n" );
++ memset( resp, 0, 20 );
++ }
++
++ resp = mmc_cmd(SD_STATUS, RCA, 0, MMC_CMDAT_R1 );
++ if( resp )
++ {
++ sd_status_t *status ;
++ int i ;
++ printf( "SDSTATUS returned\n" );
++ for( i = 0 ; i < 16 ; i++ )
++ printf( "%02x ", resp[i] );
++ printf( "\n" );
++ status = (sd_status_t *)resp ;
++ printf( "bus_width: %u\n", status->bus_width );
++ printf( "secured_mode: %u\n", status->secured_mode );
++ printf( "unused0: %x\n", status->unused0 );
++ printf( "card_type: %x\n", status->card_type );
++ printf( "prot_size: %lx\n", status->prot_size );
++ }
++ else
++ {
++ printf( "Error reading SD_STATUS\n" );
++ return -1 ;
++ }
++ }
++#endif
++
++ MMC_STRPCL = MMC_STRPCL_STOP_CLK;
++ MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF;
++ while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF));
++
+ MMC_CLKRT = 0; /* 20 MHz */
+- resp = mmc_cmd(7, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1);
++ resp = mmc_cmd(7, RCA, 0, MMC_CMDAT_R1);
++ if( !resp )
++ {
++ printf( "Error selecting RCA %x\n", RCA );
++ return -1 ;
++ }
++
++ resp = mmc_cmd(7, 0, 0, MMC_CMDAT_R1);
++ if( !resp )
++ {
++ // this is normal
++ }
++
++ resp = mmc_cmd(MMC_CMD_SEND_CSD, RCA, 0, MMC_CMDAT_R2);
++ if (!resp)
++ {
++ printf( "Error reading CSD\n" );
++ return -1 ;
++ }
++
++ csd = (mmc_csd_t *)resp;
++ memcpy(&mmc_csd, csd, sizeof(*csd));
++ rc = 0;
++
++#ifdef DEBUG
++ dumpResponse( resp, sizeof( *csd ) );
++ print_mmc_csd( csd );
++#endif
++
++ resp = mmc_cmd(7, RCA, 0, MMC_CMDAT_R1);
++ if( !resp )
++ {
++ printf( "Error selecting RCA %x\n", RCA );
++ return -1 ;
++ }
++
++ mmc_ready = 1;
++ startBlock = find_mbr(mmc_csd.c_size);
+
++ printf( "registering device: startBlock == %d, isSD ? %s\n",
++ startBlock, isSD ? "yes" : "no" );
+ fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */
+
+ return rc;
+@@ -503,4 +973,41 @@
+ return 0;
+ }
+
++#if (CONFIG_COMMANDS & CFG_CMD_MMC)
++
++int do_mmc_detect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
++{
++ unsigned long gplr1 = GPLR1 ;
++ int rval = ( 0 != (gplr1 & 0x10) );
++#ifdef DEBUG
++ printf ("Checking for MMC card: %lx, %d\n", gplr1, rval );
++#endif
++ return rval ;
++}
++
++U_BOOT_CMD(
++ mmcdet, 1, 0, do_mmc_detect,
++ "mmcdet - detect mmc card\n",
++ NULL
++);
++
++int do_mmc_wp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
++{
++ unsigned long gplr1 = GPLR1 ;
++ int rval = ( 0 == (gplr1 & 0x40) );
++#ifdef DEBUG
++ printf ("Checking MMC write protect: %lx, %d\n", gplr1, rval );
++#endif
++ return rval ;
++}
++
++U_BOOT_CMD(
++ mmcwp, 1, 0, do_mmc_wp,
++ "mmcwp - detect mmc write protect\n",
++ NULL
++);
++
++#endif
++
+ #endif
++
+diff -u -r --new-file u-boot-1.1.2/cpu/pxa/pxafb.c u-boot-1.1.2-neon/cpu/pxa/pxafb.c
+--- u-boot-1.1.2/cpu/pxa/pxafb.c 2004-10-10 01:26:00.000000000 +0200
++++ u-boot-1.1.2-neon/cpu/pxa/pxafb.c 2007-08-11 21:07:20.000000000 +0200
+@@ -36,6 +36,10 @@
+ #include <lcd.h>
+ #include <asm/arch/pxa-regs.h>
+
++#ifdef CFG_CMD_LCDPANEL
++#include <lcd_panels.h>
++#endif
++
+ /* #define DEBUG */
+
+ #ifdef CONFIG_LCD
+@@ -147,6 +151,38 @@
+ #endif /* CONFIG_HITACHI_SX14 */
+
+ /*----------------------------------------------------------------------*/
++#ifdef CONFIG_SHARP_QVGA
++/* Sharp 1/4 VGA LCD */
++#define LCD_BPP LCD_COLOR8
++
++/* you have to set lccr0 and lccr3 (including pcd) */
++#define REG_LCCR0 0x003008F8
++#define REG_LCCR3 (0x0040FF0C|(LCD_BPP<<24))
++
++vidinfo_t panel_info = {
++ vl_col: 320,
++ vl_row: 240,
++ vl_width: 167,
++ vl_height: 109,
++ vl_clkp: CFG_HIGH,
++ vl_oep: CFG_HIGH,
++ vl_hsp: CFG_HIGH,
++ vl_vsp: CFG_HIGH,
++ vl_dp: CFG_HIGH,
++ vl_bpix: LCD_BPP,
++ vl_lbw: 1,
++ vl_splt: 0,
++ vl_clor: 1,
++ vl_tft: 1,
++ vl_hpw: 64,
++ vl_blw: 34,
++ vl_elw: 1,
++ vl_vpw: 20,
++ vl_bfw: 8,
++ vl_efw: 3,
++};
++#endif /* CONFIG_SHARP_QVGA */
++
+
+ #if LCD_BPP == LCD_COLOR8
+ void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
+@@ -163,7 +199,6 @@
+ void lcd_ctrl_init (void *lcdbase);
+ void lcd_enable (void);
+
+-int lcd_line_length;
+ int lcd_color_fg;
+ int lcd_color_bg;
+
+@@ -185,10 +220,28 @@
+
+ void lcd_ctrl_init (void *lcdbase)
+ {
++#ifdef CFG_CMD_LCDPANEL
++ char const *panelName = getenv( "panel" );
++ if( panelName )
++ {
++ struct lcd_panel_info_t const *panel ;
++ panel = find_lcd_panel( panelName );
++ if( panel )
++ {
++ printf( "panel %s found: %u x %u\n", panelName, panel->xres, panel->yres );
++ panel_info.pxa.screen = (u_long)lcdbase;
++ set_lcd_panel( panel );
++ }
++ else
++ printf( "panel %s not found\n", panelName );
++ }
++#else
+ pxafb_init_mem(lcdbase, &panel_info);
+ pxafb_init(&panel_info);
+ pxafb_setup_gpio(&panel_info);
+ pxafb_enable_controller(&panel_info);
++#endif
++
+ }
+
+ /*----------------------------------------------------------------------*/
+@@ -204,6 +257,7 @@
+ void
+ lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
+ {
++#if defined( CONFIG_PXA250 )
+ struct pxafb_info *fbi = &panel_info.pxa;
+ unsigned short *palette = (unsigned short *)fbi->palette;
+ u_int val;
+@@ -219,7 +273,22 @@
+ palette[regno] = val;
+ #endif
+ }
++#elif defined( CONFIG_PXA270 )
++ struct pxafb_info *fbi = &panel_info.pxa;
++ u32 *palette = (u32 *)fbi->palette;
++ u32 val;
++
++ if (regno < fbi->palette_size) {
++ val = 0xFF000000 ; // transparency
++ val |= (red << 16);
++ val |= (green << 8);
++ val |= blue ;
+
++ palette[regno] = val;
++ }
++#else
++#error no processor defined
++#endif
+ debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
+ regno, &palette[regno],
+ red, green, blue,
+@@ -284,7 +353,7 @@
+ fbi->screen = (u_long)lcdbase;
+
+ fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
+- palette_mem_size = fbi->palette_size * sizeof(u16);
++ palette_mem_size = fbi->palette_size * sizeof(PALETTEVAL_TYPE);
+
+ debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
+ /* locate palette and descs at end of page following fb */
+@@ -376,11 +445,16 @@
+ static int pxafb_init (vidinfo_t *vid)
+ {
+ struct pxafb_info *fbi = &vid->pxa;
++ unsigned long const REG_LCCR3 = 0x0040FF0C|(LCD_BPP<<24);
+
+ debug("Configuring PXA LCD\n");
+
+- fbi->reg_lccr0 = REG_LCCR0;
+- fbi->reg_lccr3 = REG_LCCR3;
++#if defined( CONFIG_PXA270 )
++ LCCR4 = 0x00010000 ;
++#endif
++
++ fbi->reg_lccr0 = 0x003008F8;
++ fbi->reg_lccr3 = REG_LCCR3 ;
+
+ debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
+ vid->vl_col, vid->vl_hpw,
+@@ -429,7 +503,7 @@
+
+ fbi->dmadesc_palette->fsadr = fbi->palette;
+ fbi->dmadesc_palette->fidr = 0;
+- fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
++ fbi->dmadesc_palette->ldcmd = (fbi->palette_size * sizeof(PALETTEVAL_TYPE)) | LDCMD_PAL;
+
+ if( NBITS(vid->vl_bpix) < 12)
+ {
+@@ -465,6 +539,39 @@
+ return 0;
+ }
+
++
++#ifdef CFG_CMD_LCDPANEL
++
++void set_lcd_panel( struct lcd_panel_info_t const *panel )
++{
++ panel_info.vl_col = panel->xres ;
++ panel_info.vl_row = panel->yres ;
++ panel_info.vl_clkp = panel->act_high ;
++ panel_info.vl_oep = panel->act_high ;
++ panel_info.vl_hsp = panel->act_high ;
++ panel_info.vl_vsp = panel->act_high ;
++ panel_info.vl_dp = panel->act_high ;
++ panel_info.vl_bpix = LCD_BPP ;
++ panel_info.vl_lcd_line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) >> 3;
++ panel_info.vl_lbw = 1 ;
++ panel_info.vl_splt = 0 ;
++ panel_info.vl_clor = 1 ;
++ panel_info.vl_tft = panel->active ;
++ panel_info.vl_hpw = panel->hsync_len ;
++ panel_info.vl_blw = panel->left_margin ;
++ panel_info.vl_elw = panel->right_margin ;
++ panel_info.vl_vpw = panel->vsync_len ;
++ panel_info.vl_bfw = panel->upper_margin ;
++ panel_info.vl_efw = panel->lower_margin ;
++
++ pxafb_init_mem( (void *)panel_info.pxa.screen, &panel_info);
++ pxafb_init(&panel_info);
++ pxafb_setup_gpio(&panel_info);
++ pxafb_enable_controller(&panel_info);
++}
++
++#endif // dynamic LCD panel support
++
+ /************************************************************************/
+ /************************************************************************/
+
+diff -u -r --new-file u-boot-1.1.2/cpu/pxa/sm501_usb.h u-boot-1.1.2-neon/cpu/pxa/sm501_usb.h
+--- u-boot-1.1.2/cpu/pxa/sm501_usb.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/cpu/pxa/sm501_usb.h 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,66 @@
++#ifndef SM501_USB_INCLUDED
++#define SM501_USB_INCLUDED
++
++ #if defined(CONFIG_SM501)
++ #define USB_GATE_MODE0 __REG(0xFE00040)
++ #define USB_GATE_MODE1 __REG(0xFE00048)
++ #define ENABLE_USBH (1<<11)
++
++ /*
++ * USB Host Controller
++ */
++ #define USBH_BASE 0xFE40000
++ #define UHCREV __REG(0xFE40000)
++ #define UHCHCON __REG(0xFE40004)
++ #define UHCCOMS __REG(0xFE40008)
++ #define UHCINTS __REG(0xFE4000C)
++ #define UHCINTE __REG(0xFE40010)
++ #define UHCINTD __REG(0xFE40014)
++ #define UHCHCCA __REG(0xFE40018)
++ #define UHCPCED __REG(0xFE4001C)
++ #define UHCCHED __REG(0xFE40020)
++ #define UHCCCED __REG(0xFE40024)
++ #define UHCBHED __REG(0xFE40028)
++ #define UHCBCED __REG(0xFE4002C)
++ #define UHCDHEAD __REG(0xFE40030)
++ #define UHCFMI __REG(0xFE40034)
++ #define UHCFMR __REG(0xFE40038)
++ #define UHCFMN __REG(0xFE4003C)
++ #define UHCPERS __REG(0xFE40040)
++ #define UHCLST __REG(0xFE40044)
++ #define UHCRHDA __REG(0xFE40048)
++ #define UHCRHDB __REG(0xFE4004C)
++ #define UHCRHS __REG(0xFE40050)
++ #define UHCRHPS1 __REG(0xFE40054)
++ #define UHCRHPS2 __REG(0xFE40058)
++ #define UHCRHPS3 __REG(0xFE4005C)
++ #define UHCSTAT __REG(0xFE40060)
++ #define UHCHR __REG(0xFE40064)
++ #define UHCHIE __REG(0xFE40068)
++ #define UHCHIT __REG(0xFE4006C)
++
++ #define UHCHR_FSBIR (1<<0)
++ #define UHCHR_FHR (1<<1)
++ #define UHCHR_CGR (1<<2)
++ #define UHCHR_SSDC (1<<3)
++ #define UHCHR_UIT (1<<4)
++ #define UHCHR_SSE (1<<5)
++ #define UHCHR_PSPL (1<<6)
++ #define UHCHR_PCPL (1<<7)
++ #define UHCHR_SSEP0 (1<<9)
++ #define UHCHR_SSEP1 (1<<10)
++ #define UHCHR_SSEP2 (1<<11)
++
++ #define UHCHIE_UPRIE (1<<13)
++ #define UHCHIE_UPS2IE (1<<12)
++ #define UHCHIE_UPS1IE (1<<11)
++ #define UHCHIE_TAIE (1<<10)
++ #define UHCHIE_HBAIE (1<<8)
++ #define UHCHIE_RWIE (1<<7)
++
++ #define UHCCOMS_HCR 1
++ #define UHCRHS_LPS 1
++ #define UHCHR_SSE (1<<5)
++
++ #endif
++#endif
+diff -u -r --new-file u-boot-1.1.2/cpu/pxa/start.S u-boot-1.1.2-neon/cpu/pxa/start.S
+--- u-boot-1.1.2/cpu/pxa/start.S 2004-06-09 02:11:02.000000000 +0200
++++ u-boot-1.1.2-neon/cpu/pxa/start.S 2007-08-11 21:07:20.000000000 +0200
+@@ -61,23 +61,10 @@
+ * - jump to second stage
+ */
+
+-_TEXT_BASE:
+- .word TEXT_BASE
+
+-.globl _armboot_start
+-_armboot_start:
+- .word _start
++_textBase:
++ .word TEXT_BASE
+
+-/*
+- * These are defined in the board-specific linker script.
+- */
+-.globl _bss_start
+-_bss_start:
+- .word __bss_start
+-
+-.globl _bss_end
+-_bss_end:
+- .word _end
+
+ #ifdef CONFIG_USE_IRQ
+ /* IRQ stack memory (calculated at run-time) */
+@@ -111,47 +98,9 @@
+ #ifdef CONFIG_INIT_CRITICAL
+ bl cpu_init_crit /* we do sys-critical inits */
+ #endif
++ b HeadStart
+
+-relocate: /* relocate U-Boot to RAM */
+- adr r0, _start /* r0 <- current position of code */
+- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
+- cmp r0, r1 /* don't reloc during debug */
+- beq stack_setup
+-
+- ldr r2, _armboot_start
+- ldr r3, _bss_start
+- sub r2, r3, r2 /* r2 <- size of armboot */
+- add r2, r0, r2 /* r2 <- source end address */
+-
+-copy_loop:
+- ldmia r0!, {r3-r10} /* copy from source address [r0] */
+- stmia r1!, {r3-r10} /* copy to target address [r1] */
+- cmp r0, r2 /* until source end addreee [r2] */
+- ble copy_loop
+-
+- /* Set up the stack */
+-stack_setup:
+- ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
+- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
+- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+-#ifdef CONFIG_USE_IRQ
+- sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
+-#endif
+- sub sp, r0, #12 /* leave 3 words for abort-stack */
+-
+-clear_bss:
+- ldr r0, _bss_start /* find start of bss segment */
+- ldr r1, _bss_end /* stop here */
+- mov r2, #0x00000000 /* clear */
+
+-clbss_l:str r2, [r0] /* clear loop... */
+- add r0, r0, #4
+- cmp r0, r1
+- bne clbss_l
+-
+- ldr pc, _start_armboot
+-
+-_start_armboot: .word start_armboot
+
+
+ /****************************************************************************/
+@@ -167,16 +116,7 @@
+ IC_BASE: .word 0x40d00000
+ #define ICMR 0x04
+
+-/* Reset-Controller */
+-RST_BASE: .word 0x40f00030
+-#define RCSR 0x00
+-
+-/* Operating System Timer */
+-OSTIMER_BASE: .word 0x40a00000
+-#define OSMR3 0x0C
+-#define OSCR 0x10
+-#define OWER 0x18
+-#define OIER 0x1C
++
+
+ /* Clock Manager Registers */
+ #ifdef CFG_CPUSPEED
+@@ -288,7 +228,7 @@
+ stmia sp, {r0 - r12} /* Calling r0-r12 */
+ add r8, sp, #S_PC
+
+- ldr r2, _armboot_start
++ ldr r2, _textBase
+ sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+ sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
+@@ -325,7 +265,7 @@
+ .endm
+
+ .macro get_bad_stack
+- ldr r13, _armboot_start @ setup our mode stack
++ ldr r13, _textBase @ setup our mode stack
+ sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+ sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+
+@@ -416,36 +356,3 @@
+
+ #endif
+
+-/****************************************************************************/
+-/* */
+-/* Reset function: the PXA250 doesn't have a reset function, so we have to */
+-/* perform a watchdog timeout for a soft reset. */
+-/* */
+-/****************************************************************************/
+-
+- .align 5
+-.globl reset_cpu
+-
+- /* FIXME: this code is PXA250 specific. How is this handled on */
+- /* other XScale processors? */
+-
+-reset_cpu:
+-
+- /* We set OWE:WME (watchdog enable) and wait until timeout happens */
+-
+- ldr r0, OSTIMER_BASE
+- ldr r1, [r0, #OWER]
+- orr r1, r1, #0x0001 /* bit0: WME */
+- str r1, [r0, #OWER]
+-
+- /* OS timer does only wrap every 1165 seconds, so we have to set */
+- /* the match register as well. */
+-
+- ldr r1, [r0, #OSCR] /* read OS timer */
+- add r1, r1, #0x800 /* let OSMR3 match after */
+- add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
+- str r1, [r0, #OSMR3]
+-
+-reset_endless:
+-
+- b reset_endless
+diff -u -r --new-file u-boot-1.1.2/cpu/pxa/usb_ohci.c u-boot-1.1.2-neon/cpu/pxa/usb_ohci.c
+--- u-boot-1.1.2/cpu/pxa/usb_ohci.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/cpu/pxa/usb_ohci.c 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,1679 @@
++/*
++ * URB OHCI HCD (Host Controller Driver) for USB on the S3C2400.
++ *
++ * (C) Copyright 2003
++ * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ * Note: Part of this code has been derived from linux
++ *
++ */
++/*
++ * IMPORTANT NOTES
++ * 1 - you MUST define LITTLEENDIAN in the configuration file for the
++ * board or this driver will NOT work!
++ * 2 - this driver is intended for use with USB Mass Storage Devices
++ * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
++ */
++
++#include <common.h>
++/* #include <pci.h> no PCI on the S3C24X0 */
++
++#ifdef CONFIG_USB_OHCI
++
++#include <asm/arch/pxa-regs.h>
++
++#include <malloc.h>
++#include <usb.h>
++#include "usb_ohci.h"
++
++#if defined( CONFIG_SM501 )
++#include "sm501_usb.h"
++#endif
++
++// #define OHCI_USE_NPS /* force NoPowerSwitching mode */
++// #define OHCI_VERBOSE_DEBUG /* not always helpful */
++
++
++/* For initializing controller (mask in an HCFS mode too) */
++#define OHCI_CONTROL_INIT \
++ (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
++
++#define readl(a) (*((vu_long *)(a)))
++#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
++
++#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
++
++//#define DEBUG
++#ifdef DEBUG
++#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
++#else
++#define dbg(format, arg...) do {} while(0)
++#endif /* DEBUG */
++#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
++#define SHOW_INFO
++#ifdef SHOW_INFO
++#define info(format, arg...) printf("INFO: " format "\n", ## arg)
++#else
++#define info(format, arg...) do {} while(0)
++#endif
++
++#define m16_swap(x) swap_16(x)
++#define m32_swap(x) swap_32(x)
++
++/* global ohci_t */
++static ohci_t gohci;
++/* this must be aligned to a 256 byte boundary */
++struct ohci_hcca ghcca[1];
++/* a pointer to the aligned storage */
++struct ohci_hcca *phcca;
++/* this allocates EDs for all possible endpoints */
++struct ohci_device ohci_dev;
++/* urb_priv */
++urb_priv_t urb_priv;
++/* RHSC flag */
++int got_rhsc;
++/* device which was disconnected */
++struct usb_device *devgone;
++
++/*-------------------------------------------------------------------------*/
++
++/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
++ * The erratum (#4) description is incorrect. AMD's workaround waits
++ * till some bits (mostly reserved) are clear; ok for all revs.
++ */
++#define OHCI_QUIRK_AMD756 0xabcd
++#define read_roothub(hc, register, mask) ({ \
++ u32 temp = readl (&hc->regs->roothub.register); \
++ if (hc->flags & OHCI_QUIRK_AMD756) \
++ while (temp & mask) \
++ temp = readl (&hc->regs->roothub.register); \
++ temp; })
++
++static u32 roothub_a (struct ohci *hc)
++ { return read_roothub (hc, a, 0xfc0fe000); }
++static inline u32 roothub_b (struct ohci *hc)
++ { return readl (&hc->regs->roothub.b); }
++static inline u32 roothub_status (struct ohci *hc)
++ { return readl (&hc->regs->roothub.status); }
++static u32 roothub_portstatus (struct ohci *hc, int i)
++ { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
++
++
++/* forward declaration */
++static int hc_interrupt (void);
++static void
++td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
++ int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
++
++/*-------------------------------------------------------------------------*
++ * URB support functions
++ *-------------------------------------------------------------------------*/
++
++/* free HCD-private data associated with this URB */
++
++static void urb_free_priv (urb_priv_t * urb)
++{
++ int i;
++ int last;
++ struct td * td;
++
++ last = urb->length - 1;
++ if (last >= 0) {
++ for (i = 0; i <= last; i++) {
++ td = urb->td[i];
++ if (td) {
++ td->usb_dev = NULL;
++ urb->td[i] = NULL;
++ }
++ }
++ }
++}
++
++/*-------------------------------------------------------------------------*/
++
++#ifdef DEBUG
++static int sohci_get_current_frame_number (struct usb_device * dev);
++
++/* debug| print the main components of an URB
++ * small: 0) header + data packets 1) just header */
++
++static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
++ int transfer_len, struct devrequest * setup, char * str, int small)
++{
++ urb_priv_t * purb = &urb_priv;
++
++ dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
++ str,
++ sohci_get_current_frame_number (dev),
++ usb_pipedevice (pipe),
++ usb_pipeendpoint (pipe),
++ usb_pipeout (pipe)? 'O': 'I',
++ usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
++ (usb_pipecontrol (pipe)? "CTRL": "BULK"),
++ purb->actual_length,
++ transfer_len, dev->status);
++#ifdef OHCI_VERBOSE_DEBUG
++ if (!small) {
++ int i, len;
++
++ if (usb_pipecontrol (pipe)) {
++ printf (__FILE__ ": cmd(8):");
++ for (i = 0; i < 8 ; i++)
++ printf (" %02x", ((__u8 *) setup) [i]);
++ printf ("\n");
++ }
++ if (transfer_len > 0 && buffer) {
++ printf (__FILE__ ": data(%d/%d):",
++ purb->actual_length,
++ transfer_len);
++ len = usb_pipeout (pipe)?
++ transfer_len: purb->actual_length;
++ for (i = 0; i < 16 && i < len; i++)
++ printf (" %02x", ((__u8 *) buffer) [i]);
++ printf ("%s\n", i < len? "...": "");
++ }
++ }
++#endif
++}
++
++/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
++void ep_print_int_eds (ohci_t *ohci, char * str) {
++ int i, j;
++ __u32 * ed_p;
++ for (i= 0; i < 32; i++) {
++ j = 5;
++ ed_p = &(ohci->hcca->int_table [i]);
++ if (*ed_p == 0)
++ continue;
++ printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
++ while (*ed_p != 0 && j--) {
++ ed_t *ed = (ed_t *)m32_swap(ed_p);
++ printf (" ed: %4x;", ed->hwINFO);
++ ed_p = &ed->hwNextED;
++ }
++ printf ("\n");
++ }
++}
++
++static void ohci_dump_intr_mask (char *label, __u32 mask)
++{
++ dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
++ label,
++ mask,
++ (mask & OHCI_INTR_MIE) ? " MIE" : "",
++ (mask & OHCI_INTR_OC) ? " OC" : "",
++ (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
++ (mask & OHCI_INTR_FNO) ? " FNO" : "",
++ (mask & OHCI_INTR_UE) ? " UE" : "",
++ (mask & OHCI_INTR_RD) ? " RD" : "",
++ (mask & OHCI_INTR_SF) ? " SF" : "",
++ (mask & OHCI_INTR_WDH) ? " WDH" : "",
++ (mask & OHCI_INTR_SO) ? " SO" : ""
++ );
++}
++
++static void maybe_print_eds (char *label, __u32 value)
++{
++ ed_t *edp = (ed_t *)value;
++
++ if (value) {
++ dbg ("%s %08x", label, value);
++ dbg ("%08x", edp->hwINFO);
++ dbg ("%08x", edp->hwTailP);
++ dbg ("%08x", edp->hwHeadP);
++ dbg ("%08x", edp->hwNextED);
++ }
++}
++
++static char * hcfs2string (int state)
++{
++ switch (state) {
++ case OHCI_USB_RESET: return "reset";
++ case OHCI_USB_RESUME: return "resume";
++ case OHCI_USB_OPER: return "operational";
++ case OHCI_USB_SUSPEND: return "suspend";
++ }
++ return "?";
++}
++
++/* dump control and status registers */
++static void ohci_dump_status (ohci_t *controller)
++{
++ struct ohci_regs *regs = controller->regs;
++ __u32 temp;
++
++ temp = readl (&regs->revision) & 0xff;
++ if (temp != 0x10)
++ dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
++
++ temp = readl (&regs->control);
++ dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
++ (temp & OHCI_CTRL_RWE) ? " RWE" : "",
++ (temp & OHCI_CTRL_RWC) ? " RWC" : "",
++ (temp & OHCI_CTRL_IR) ? " IR" : "",
++ hcfs2string (temp & OHCI_CTRL_HCFS),
++ (temp & OHCI_CTRL_BLE) ? " BLE" : "",
++ (temp & OHCI_CTRL_CLE) ? " CLE" : "",
++ (temp & OHCI_CTRL_IE) ? " IE" : "",
++ (temp & OHCI_CTRL_PLE) ? " PLE" : "",
++ temp & OHCI_CTRL_CBSR
++ );
++
++ temp = readl (&regs->cmdstatus);
++ dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
++ (temp & OHCI_SOC) >> 16,
++ (temp & OHCI_OCR) ? " OCR" : "",
++ (temp & OHCI_BLF) ? " BLF" : "",
++ (temp & OHCI_CLF) ? " CLF" : "",
++ (temp & OHCI_HCR) ? " HCR" : ""
++ );
++
++ ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
++ ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
++
++ maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
++
++ maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
++ maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
++
++ maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
++ maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
++
++ maybe_print_eds ("donehead", readl (&regs->donehead));
++}
++
++static void ohci_dump_roothub (ohci_t *controller, int verbose)
++{
++ __u32 temp, ndp, i;
++
++ temp = roothub_a (controller);
++ ndp = (temp & RH_A_NDP);
++
++ if (verbose) {
++ dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
++ ((temp & RH_A_POTPGT) >> 24) & 0xff,
++ (temp & RH_A_NOCP) ? " NOCP" : "",
++ (temp & RH_A_OCPM) ? " OCPM" : "",
++ (temp & RH_A_DT) ? " DT" : "",
++ (temp & RH_A_NPS) ? " NPS" : "",
++ (temp & RH_A_PSM) ? " PSM" : "",
++ ndp
++ );
++ temp = roothub_b (controller);
++ dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
++ temp,
++ (temp & RH_B_PPCM) >> 16,
++ (temp & RH_B_DR)
++ );
++ temp = roothub_status (controller);
++ dbg ("roothub.status: %08x%s%s%s%s%s%s",
++ temp,
++ (temp & RH_HS_CRWE) ? " CRWE" : "",
++ (temp & RH_HS_OCIC) ? " OCIC" : "",
++ (temp & RH_HS_LPSC) ? " LPSC" : "",
++ (temp & RH_HS_DRWE) ? " DRWE" : "",
++ (temp & RH_HS_OCI) ? " OCI" : "",
++ (temp & RH_HS_LPS) ? " LPS" : ""
++ );
++ }
++
++ for (i = 0; i < ndp; i++) {
++ temp = roothub_portstatus (controller, i);
++ dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
++ i,
++ temp,
++ (temp & RH_PS_PRSC) ? " PRSC" : "",
++ (temp & RH_PS_OCIC) ? " OCIC" : "",
++ (temp & RH_PS_PSSC) ? " PSSC" : "",
++ (temp & RH_PS_PESC) ? " PESC" : "",
++ (temp & RH_PS_CSC) ? " CSC" : "",
++
++ (temp & RH_PS_LSDA) ? " LSDA" : "",
++ (temp & RH_PS_PPS) ? " PPS" : "",
++ (temp & RH_PS_PRS) ? " PRS" : "",
++ (temp & RH_PS_POCI) ? " POCI" : "",
++ (temp & RH_PS_PSS) ? " PSS" : "",
++
++ (temp & RH_PS_PES) ? " PES" : "",
++ (temp & RH_PS_CCS) ? " CCS" : ""
++ );
++ }
++}
++
++static void ohci_dump (ohci_t *controller, int verbose)
++{
++ dbg ("OHCI controller usb-%s state", controller->slot_name);
++
++ /* dumps some of the state we know about */
++ ohci_dump_status (controller);
++ if (verbose)
++ ep_print_int_eds (controller, "hcca");
++ dbg ("hcca frame #%04x", controller->hcca->frame_no);
++ ohci_dump_roothub (controller, 1);
++}
++
++
++#endif /* DEBUG */
++
++/*-------------------------------------------------------------------------*
++ * Interface functions (URB)
++ *-------------------------------------------------------------------------*/
++
++/* get a transfer request */
++
++int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
++ int transfer_len, struct devrequest *setup, int interval)
++{
++ ohci_t *ohci;
++ ed_t * ed;
++ urb_priv_t *purb_priv;
++ int i, size = 0;
++
++ ohci = &gohci;
++
++ /* when controller's hung, permit only roothub cleanup attempts
++ * such as powering down ports */
++ if (ohci->disabled) {
++ err("sohci_submit_job: EPIPE");
++ return -1;
++ }
++
++ /* every endpoint has a ed, locate and fill it */
++ if (!(ed = ep_add_ed (dev, pipe))) {
++ err("sohci_submit_job: ENOMEM");
++ return -1;
++ }
++
++ /* for the private part of the URB we need the number of TDs (size) */
++ switch (usb_pipetype (pipe)) {
++ case PIPE_BULK: /* one TD for every 4096 Byte */
++ size = (transfer_len - 1) / 4096 + 1;
++ break;
++ case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
++ size = (transfer_len == 0)? 2:
++ (transfer_len - 1) / 4096 + 3;
++ break;
++ }
++
++ if (size >= (N_URB_TD - 1)) {
++ err("need %d TDs, only have %d", size, N_URB_TD);
++ return -1;
++ }
++ purb_priv = &urb_priv;
++ purb_priv->pipe = pipe;
++
++ /* fill the private part of the URB */
++ purb_priv->length = size;
++ purb_priv->ed = ed;
++ purb_priv->actual_length = 0;
++
++ /* allocate the TDs */
++ /* note that td[0] was allocated in ep_add_ed */
++ for (i = 0; i < size; i++) {
++ purb_priv->td[i] = td_alloc (dev);
++ if (!purb_priv->td[i]) {
++ purb_priv->length = i;
++ urb_free_priv (purb_priv);
++ err("sohci_submit_job: ENOMEM");
++ return -1;
++ }
++ }
++
++ if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
++ urb_free_priv (purb_priv);
++ err("sohci_submit_job: EINVAL");
++ return -1;
++ }
++
++ /* link the ed into a chain if is not already */
++ if (ed->state != ED_OPER)
++ ep_link (ohci, ed);
++
++ /* fill the TDs and link it to the ed */
++ td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
++
++ return 0;
++}
++
++/*-------------------------------------------------------------------------*/
++
++#ifdef DEBUG
++/* tell us the current USB frame number */
++
++static int sohci_get_current_frame_number (struct usb_device *usb_dev)
++{
++ ohci_t *ohci = &gohci;
++
++ return m16_swap (ohci->hcca->frame_no);
++}
++#endif
++
++/*-------------------------------------------------------------------------*
++ * ED handling functions
++ *-------------------------------------------------------------------------*/
++
++/* link an ed into one of the HC chains */
++
++static int ep_link (ohci_t *ohci, ed_t *edi)
++{
++ volatile ed_t *ed = edi;
++
++ ed->state = ED_OPER;
++
++ switch (ed->type) {
++ case PIPE_CONTROL:
++ ed->hwNextED = 0;
++ if (ohci->ed_controltail == NULL) {
++ writel (ed, &ohci->regs->ed_controlhead);
++ } else {
++ ohci->ed_controltail->hwNextED = m32_swap (ed);
++ }
++ ed->ed_prev = ohci->ed_controltail;
++ if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
++ !ohci->ed_rm_list[1] && !ohci->sleeping) {
++ ohci->hc_control |= OHCI_CTRL_CLE;
++ writel (ohci->hc_control, &ohci->regs->control);
++ }
++ ohci->ed_controltail = edi;
++ break;
++
++ case PIPE_BULK:
++ ed->hwNextED = 0;
++ if (ohci->ed_bulktail == NULL) {
++ writel (ed, &ohci->regs->ed_bulkhead);
++ } else {
++ ohci->ed_bulktail->hwNextED = m32_swap (ed);
++ }
++ ed->ed_prev = ohci->ed_bulktail;
++ if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
++ !ohci->ed_rm_list[1] && !ohci->sleeping) {
++ ohci->hc_control |= OHCI_CTRL_BLE;
++ writel (ohci->hc_control, &ohci->regs->control);
++ }
++ ohci->ed_bulktail = edi;
++ break;
++ }
++ return 0;
++}
++
++/*-------------------------------------------------------------------------*/
++
++/* unlink an ed from one of the HC chains.
++ * just the link to the ed is unlinked.
++ * the link from the ed still points to another operational ed or 0
++ * so the HC can eventually finish the processing of the unlinked ed */
++
++static int ep_unlink (ohci_t *ohci, ed_t *ed)
++{
++ ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
++
++ switch (ed->type) {
++ case PIPE_CONTROL:
++ if (ed->ed_prev == NULL) {
++ if (!ed->hwNextED) {
++ ohci->hc_control &= ~OHCI_CTRL_CLE;
++ writel (ohci->hc_control, &ohci->regs->control);
++ }
++ writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
++ } else {
++ ed->ed_prev->hwNextED = ed->hwNextED;
++ }
++ if (ohci->ed_controltail == ed) {
++ ohci->ed_controltail = ed->ed_prev;
++ } else {
++ ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
++ }
++ break;
++
++ case PIPE_BULK:
++ if (ed->ed_prev == NULL) {
++ if (!ed->hwNextED) {
++ ohci->hc_control &= ~OHCI_CTRL_BLE;
++ writel (ohci->hc_control, &ohci->regs->control);
++ }
++ writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
++ } else {
++ ed->ed_prev->hwNextED = ed->hwNextED;
++ }
++ if (ohci->ed_bulktail == ed) {
++ ohci->ed_bulktail = ed->ed_prev;
++ } else {
++ ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
++ }
++ break;
++ }
++ ed->state = ED_UNLINK;
++ return 0;
++}
++
++
++/*-------------------------------------------------------------------------*/
++
++/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
++ * but the USB stack is a little bit stateless so we do it at every transaction
++ * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
++ * in all other cases the state is left unchanged
++ * the ed info fields are setted anyway even though most of them should not change */
++
++static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
++{
++ td_t *td;
++ ed_t *ed_ret;
++ volatile ed_t *ed;
++
++ ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
++ (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
++
++ if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
++ err("ep_add_ed: pending delete");
++ /* pending delete request */
++ return NULL;
++ }
++
++ if (ed->state == ED_NEW) {
++ ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
++ /* dummy td; end of td list for ed */
++ td = td_alloc (usb_dev);
++ ed->hwTailP = m32_swap (td);
++ ed->hwHeadP = ed->hwTailP;
++ ed->state = ED_UNLINK;
++ ed->type = usb_pipetype (pipe);
++ ohci_dev.ed_cnt++;
++ }
++
++ ed->hwINFO = m32_swap (usb_pipedevice (pipe)
++ | usb_pipeendpoint (pipe) << 7
++ | (usb_pipeisoc (pipe)? 0x8000: 0)
++ | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
++ | usb_pipeslow (pipe) << 13
++ | usb_maxpacket (usb_dev, pipe) << 16);
++
++ return ed_ret;
++}
++
++/*-------------------------------------------------------------------------*
++ * TD handling functions
++ *-------------------------------------------------------------------------*/
++
++/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
++
++static void td_fill (ohci_t *ohci, unsigned int info,
++ void *data, int len,
++ struct usb_device *dev, int index, urb_priv_t *urb_priv)
++{
++ volatile td_t *td, *td_pt;
++#ifdef OHCI_FILL_TRACE
++ int i;
++#endif
++
++ if (index > urb_priv->length) {
++ err("index > length");
++ return;
++ }
++ /* use this td as the next dummy */
++ td_pt = urb_priv->td [index];
++ td_pt->hwNextTD = 0;
++
++ /* fill the old dummy TD */
++ td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
++
++ td->ed = urb_priv->ed;
++ td->next_dl_td = NULL;
++ td->index = index;
++ td->data = (__u32)data;
++#ifdef OHCI_FILL_TRACE
++ if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
++ for (i = 0; i < len; i++)
++ printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
++ printf("\n");
++ }
++#endif
++ if (!len)
++ data = 0;
++
++ td->hwINFO = m32_swap (info);
++ td->hwCBP = m32_swap (data);
++ if (data)
++ td->hwBE = m32_swap (data + len - 1);
++ else
++ td->hwBE = 0;
++ td->hwNextTD = m32_swap (td_pt);
++ td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
++
++ /* append to queue */
++ td->ed->hwTailP = td->hwNextTD;
++}
++
++/*-------------------------------------------------------------------------*/
++
++/* prepare all TDs of a transfer */
++
++static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
++ int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
++{
++ ohci_t *ohci = &gohci;
++ int data_len = transfer_len;
++ void *data;
++ int cnt = 0;
++ __u32 info = 0;
++ unsigned int toggle = 0;
++
++ /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
++ if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
++ toggle = TD_T_TOGGLE;
++ } else {
++ toggle = TD_T_DATA0;
++ usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
++ }
++ urb->td_cnt = 0;
++ if (data_len)
++ data = buffer;
++ else
++ data = 0;
++
++ switch (usb_pipetype (pipe)) {
++ case PIPE_BULK:
++ info = usb_pipeout (pipe)?
++ TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
++ while(data_len > 4096) {
++ td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
++ data += 4096; data_len -= 4096; cnt++;
++ }
++ info = usb_pipeout (pipe)?
++ TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
++ td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
++ cnt++;
++
++ if (!ohci->sleeping)
++ writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
++ break;
++
++ case PIPE_CONTROL:
++ info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
++ td_fill (ohci, info, setup, 8, dev, cnt++, urb);
++ if (data_len > 0) {
++ info = usb_pipeout (pipe)?
++ TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
++ /* NOTE: mishandles transfers >8K, some >4K */
++ td_fill (ohci, info, data, data_len, dev, cnt++, urb);
++ }
++ info = usb_pipeout (pipe)?
++ TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
++ td_fill (ohci, info, data, 0, dev, cnt++, urb);
++ if (!ohci->sleeping)
++ writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
++ break;
++ }
++ if (urb->length != cnt)
++ dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
++}
++
++/*-------------------------------------------------------------------------*
++ * Done List handling functions
++ *-------------------------------------------------------------------------*/
++
++
++/* calculate the transfer length and update the urb */
++
++static void dl_transfer_length(td_t * td)
++{
++ __u32 tdINFO, tdBE, tdCBP;
++ urb_priv_t *lurb_priv = &urb_priv;
++
++ tdINFO = m32_swap (td->hwINFO);
++ tdBE = m32_swap (td->hwBE);
++ tdCBP = m32_swap (td->hwCBP);
++
++
++ if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
++ ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
++ if (tdBE != 0) {
++ if (td->hwCBP == 0)
++ lurb_priv->actual_length += tdBE - td->data + 1;
++ else
++ lurb_priv->actual_length += tdCBP - td->data;
++ }
++ }
++}
++
++/*-------------------------------------------------------------------------*/
++
++/* replies to the request have to be on a FIFO basis so
++ * we reverse the reversed done-list */
++
++static td_t * dl_reverse_done_list (ohci_t *ohci)
++{
++ __u32 td_list_hc;
++ td_t *td_rev = NULL;
++ td_t *td_list = NULL;
++ urb_priv_t *lurb_priv = NULL;
++
++ td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
++ ohci->hcca->done_head = 0;
++
++ while (td_list_hc) {
++ td_list = (td_t *)td_list_hc;
++
++ if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
++ lurb_priv = &urb_priv;
++ dbg(" USB-error/status: %x : %p",
++ TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
++ if (td_list->ed->hwHeadP & m32_swap (0x1)) {
++ if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
++ td_list->ed->hwHeadP =
++ (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
++ (td_list->ed->hwHeadP & m32_swap (0x2));
++ lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
++ } else
++ td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
++ }
++ }
++
++ td_list->next_dl_td = td_rev;
++ td_rev = td_list;
++ td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
++ }
++ return td_list;
++}
++
++/*-------------------------------------------------------------------------*/
++
++/* td done list */
++static int dl_done_list (ohci_t *ohci, td_t *td_list)
++{
++ td_t *td_list_next = NULL;
++ ed_t *ed;
++ int cc = 0;
++ int stat = 0;
++ /* urb_t *urb; */
++ urb_priv_t *lurb_priv;
++ __u32 tdINFO, edHeadP, edTailP;
++
++ while (td_list) {
++ td_list_next = td_list->next_dl_td;
++
++ lurb_priv = &urb_priv;
++ tdINFO = m32_swap (td_list->hwINFO);
++
++ ed = td_list->ed;
++
++ dl_transfer_length(td_list);
++
++ /* error code of transfer */
++ cc = TD_CC_GET (tdINFO);
++ if (cc != 0) {
++ dbg("ConditionCode %#x", cc);
++ stat = cc_to_error[cc];
++ }
++
++ if (ed->state != ED_NEW) {
++ edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
++ edTailP = m32_swap (ed->hwTailP);
++
++ /* unlink eds if they are not busy */
++ if ((edHeadP == edTailP) && (ed->state == ED_OPER))
++ ep_unlink (ohci, ed);
++ }
++
++ td_list = td_list_next;
++ }
++ return stat;
++}
++
++/*-------------------------------------------------------------------------*
++ * Virtual Root Hub
++ *-------------------------------------------------------------------------*/
++
++/* Device descriptor */
++static __u8 root_hub_dev_des[] =
++{
++ 0x12, /* __u8 bLength; */
++ 0x01, /* __u8 bDescriptorType; Device */
++ 0x10, /* __u16 bcdUSB; v1.1 */
++ 0x01,
++ 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
++ 0x00, /* __u8 bDeviceSubClass; */
++ 0x00, /* __u8 bDeviceProtocol; */
++ 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
++ 0x00, /* __u16 idVendor; */
++ 0x00,
++ 0x00, /* __u16 idProduct; */
++ 0x00,
++ 0x00, /* __u16 bcdDevice; */
++ 0x00,
++ 0x00, /* __u8 iManufacturer; */
++ 0x01, /* __u8 iProduct; */
++ 0x00, /* __u8 iSerialNumber; */
++ 0x01 /* __u8 bNumConfigurations; */
++};
++
++
++/* Configuration descriptor */
++static __u8 root_hub_config_des[] =
++{
++ 0x09, /* __u8 bLength; */
++ 0x02, /* __u8 bDescriptorType; Configuration */
++ 0x19, /* __u16 wTotalLength; */
++ 0x00,
++ 0x01, /* __u8 bNumInterfaces; */
++ 0x01, /* __u8 bConfigurationValue; */
++ 0x00, /* __u8 iConfiguration; */
++ 0x40, /* __u8 bmAttributes;
++ Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
++ 0x00, /* __u8 MaxPower; */
++
++ /* interface */
++ 0x09, /* __u8 if_bLength; */
++ 0x04, /* __u8 if_bDescriptorType; Interface */
++ 0x00, /* __u8 if_bInterfaceNumber; */
++ 0x00, /* __u8 if_bAlternateSetting; */
++ 0x01, /* __u8 if_bNumEndpoints; */
++ 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
++ 0x00, /* __u8 if_bInterfaceSubClass; */
++ 0x00, /* __u8 if_bInterfaceProtocol; */
++ 0x00, /* __u8 if_iInterface; */
++
++ /* endpoint */
++ 0x07, /* __u8 ep_bLength; */
++ 0x05, /* __u8 ep_bDescriptorType; Endpoint */
++ 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
++ 0x03, /* __u8 ep_bmAttributes; Interrupt */
++ 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
++ 0x00,
++ 0xff /* __u8 ep_bInterval; 255 ms */
++};
++
++static unsigned char root_hub_str_index0[] =
++{
++ 0x04, /* __u8 bLength; */
++ 0x03, /* __u8 bDescriptorType; String-descriptor */
++ 0x09, /* __u8 lang ID */
++ 0x04, /* __u8 lang ID */
++};
++
++static unsigned char root_hub_str_index1[] =
++{
++ 28, /* __u8 bLength; */
++ 0x03, /* __u8 bDescriptorType; String-descriptor */
++ 'O', /* __u8 Unicode */
++ 0, /* __u8 Unicode */
++ 'H', /* __u8 Unicode */
++ 0, /* __u8 Unicode */
++ 'C', /* __u8 Unicode */
++ 0, /* __u8 Unicode */
++ 'I', /* __u8 Unicode */
++ 0, /* __u8 Unicode */
++ ' ', /* __u8 Unicode */
++ 0, /* __u8 Unicode */
++ 'R', /* __u8 Unicode */
++ 0, /* __u8 Unicode */
++ 'o', /* __u8 Unicode */
++ 0, /* __u8 Unicode */
++ 'o', /* __u8 Unicode */
++ 0, /* __u8 Unicode */
++ 't', /* __u8 Unicode */
++ 0, /* __u8 Unicode */
++ ' ', /* __u8 Unicode */
++ 0, /* __u8 Unicode */
++ 'H', /* __u8 Unicode */
++ 0, /* __u8 Unicode */
++ 'u', /* __u8 Unicode */
++ 0, /* __u8 Unicode */
++ 'b', /* __u8 Unicode */
++ 0, /* __u8 Unicode */
++};
++
++/* Hub class-specific descriptor is constructed dynamically */
++
++
++/*-------------------------------------------------------------------------*/
++
++#define OK(x) len = (x); break
++#ifdef DEBUG
++#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
++#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
++#else
++#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
++#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
++#endif
++#define RD_RH_STAT roothub_status(&gohci)
++#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
++
++/* request to virtual root hub */
++
++int rh_check_port_status(ohci_t *controller)
++{
++ __u32 temp, ndp, i;
++ int res;
++
++ res = -1;
++ temp = roothub_a (controller);
++ ndp = (temp & RH_A_NDP);
++ for (i = 0; i < ndp; i++) {
++ temp = roothub_portstatus (controller, i);
++ /* check for a device disconnect */
++ if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
++ (RH_PS_PESC | RH_PS_CSC)) &&
++ ((temp & RH_PS_CCS) == 0)) {
++ res = i;
++ break;
++ }
++ }
++ return res;
++}
++
++static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
++ void *buffer, int transfer_len, struct devrequest *cmd)
++{
++ void * data = buffer;
++ int leni = transfer_len;
++ int len = 0;
++ int stat = 0;
++ __u32 datab[4];
++ __u8 *data_buf = (__u8 *)datab;
++ __u16 bmRType_bReq;
++ __u16 wValue;
++ __u16 wIndex;
++ __u16 wLength;
++
++#ifdef DEBUG
++urb_priv.actual_length = 0;
++pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
++#else
++ wait_ms(1);
++#endif
++ if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
++ info("Root-Hub submit IRQ: NOT implemented");
++ return 0;
++ }
++
++ bmRType_bReq = cmd->requesttype | (cmd->request << 8);
++ wValue = m16_swap (cmd->value);
++ wIndex = m16_swap (cmd->index);
++ wLength = m16_swap (cmd->length);
++
++ info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
++ dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
++
++ switch (bmRType_bReq) {
++ /* Request Destination:
++ without flags: Device,
++ RH_INTERFACE: interface,
++ RH_ENDPOINT: endpoint,
++ RH_CLASS means HUB here,
++ RH_OTHER | RH_CLASS almost ever means HUB_PORT here
++ */
++
++ case RH_GET_STATUS:
++ *(__u16 *) data_buf = m16_swap (1); OK (2);
++ case RH_GET_STATUS | RH_INTERFACE:
++ *(__u16 *) data_buf = m16_swap (0); OK (2);
++ case RH_GET_STATUS | RH_ENDPOINT:
++ *(__u16 *) data_buf = m16_swap (0); OK (2);
++ case RH_GET_STATUS | RH_CLASS:
++ *(__u32 *) data_buf = m32_swap (
++ RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
++ OK (4);
++ case RH_GET_STATUS | RH_OTHER | RH_CLASS:
++ *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
++
++ case RH_CLEAR_FEATURE | RH_ENDPOINT:
++ switch (wValue) {
++ case (RH_ENDPOINT_STALL): OK (0);
++ }
++ break;
++
++ case RH_CLEAR_FEATURE | RH_CLASS:
++ switch (wValue) {
++ case RH_C_HUB_LOCAL_POWER:
++ OK(0);
++ case (RH_C_HUB_OVER_CURRENT):
++ WR_RH_STAT(RH_HS_OCIC); OK (0);
++ }
++ break;
++
++ case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
++ switch (wValue) {
++ case (RH_PORT_ENABLE):
++ WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
++ case (RH_PORT_SUSPEND):
++ WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
++ case (RH_PORT_POWER):
++ WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
++ case (RH_C_PORT_CONNECTION):
++ WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
++ case (RH_C_PORT_ENABLE):
++ WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
++ case (RH_C_PORT_SUSPEND):
++ WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
++ case (RH_C_PORT_OVER_CURRENT):
++ WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
++ case (RH_C_PORT_RESET):
++ WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
++ }
++ break;
++
++ case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
++ switch (wValue) {
++ case (RH_PORT_SUSPEND):
++ WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
++ case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
++ if (RD_RH_PORTSTAT & RH_PS_CCS)
++ WR_RH_PORTSTAT (RH_PS_PRS);
++ OK (0);
++ case (RH_PORT_POWER):
++ WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
++ case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
++ if (RD_RH_PORTSTAT & RH_PS_CCS)
++ WR_RH_PORTSTAT (RH_PS_PES );
++ OK (0);
++ }
++ break;
++
++ case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
++
++ case RH_GET_DESCRIPTOR:
++ switch ((wValue & 0xff00) >> 8) {
++ case (0x01): /* device descriptor */
++ len = min_t(unsigned int,
++ leni,
++ min_t(unsigned int,
++ sizeof (root_hub_dev_des),
++ wLength));
++ data_buf = root_hub_dev_des; OK(len);
++ case (0x02): /* configuration descriptor */
++ len = min_t(unsigned int,
++ leni,
++ min_t(unsigned int,
++ sizeof (root_hub_config_des),
++ wLength));
++ data_buf = root_hub_config_des; OK(len);
++ case (0x03): /* string descriptors */
++ if(wValue==0x0300) {
++ len = min_t(unsigned int,
++ leni,
++ min_t(unsigned int,
++ sizeof (root_hub_str_index0),
++ wLength));
++ data_buf = root_hub_str_index0;
++ OK(len);
++ }
++ if(wValue==0x0301) {
++ len = min_t(unsigned int,
++ leni,
++ min_t(unsigned int,
++ sizeof (root_hub_str_index1),
++ wLength));
++ data_buf = root_hub_str_index1;
++ OK(len);
++ }
++ default:
++ stat = USB_ST_STALLED;
++ }
++ break;
++
++ case RH_GET_DESCRIPTOR | RH_CLASS:
++ {
++ __u32 temp = roothub_a (&gohci);
++
++ data_buf [0] = 9; /* min length; */
++ data_buf [1] = 0x29;
++ data_buf [2] = temp & RH_A_NDP;
++ data_buf [3] = 0;
++ if (temp & RH_A_PSM) /* per-port power switching? */
++ data_buf [3] |= 0x1;
++ if (temp & RH_A_NOCP) /* no overcurrent reporting? */
++ data_buf [3] |= 0x10;
++ else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
++ data_buf [3] |= 0x8;
++
++ /* corresponds to data_buf[4-7] */
++ datab [1] = 0;
++ data_buf [5] = (temp & RH_A_POTPGT) >> 24;
++ temp = roothub_b (&gohci);
++ data_buf [7] = temp & RH_B_DR;
++ if (data_buf [2] < 7) {
++ data_buf [8] = 0xff;
++ } else {
++ data_buf [0] += 2;
++ data_buf [8] = (temp & RH_B_DR) >> 8;
++ data_buf [10] = data_buf [9] = 0xff;
++ }
++
++ len = min_t(unsigned int, leni,
++ min_t(unsigned int, data_buf [0], wLength));
++ OK (len);
++ }
++
++ case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
++
++ case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
++
++ default:
++ dbg ("unsupported root hub command");
++ stat = USB_ST_STALLED;
++ }
++
++#ifdef DEBUG
++ ohci_dump_roothub (&gohci, 1);
++#else
++ wait_ms(1);
++#endif
++
++ len = min_t(int, len, leni);
++ if (data != data_buf)
++ memcpy (data, data_buf, len);
++ dev->act_len = len;
++ dev->status = stat;
++
++#ifdef DEBUG
++ if (transfer_len)
++ urb_priv.actual_length = transfer_len;
++ pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
++#else
++ wait_ms(1);
++#endif
++
++ return stat;
++}
++
++/*-------------------------------------------------------------------------*/
++
++/* common code for handling submit messages - used for all but root hub */
++/* accesses. */
++int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
++ int transfer_len, struct devrequest *setup, int interval)
++{
++ int stat = 0;
++ int maxsize = usb_maxpacket(dev, pipe);
++ int timeout;
++
++ /* device pulled? Shortcut the action. */
++ if (devgone == dev) {
++ dev->status = USB_ST_CRC_ERR;
++ return 0;
++ }
++
++#ifdef DEBUG
++ urb_priv.actual_length = 0;
++ pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
++#else
++ wait_ms(1);
++#endif
++ if (!maxsize) {
++ err("submit_common_message: pipesize for pipe %lx is zero",
++ pipe);
++ return -1;
++ }
++
++ if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
++ err("sohci_submit_job failed");
++ return -1;
++ }
++
++ wait_ms(10);
++ /* ohci_dump_status(&gohci); */
++
++ /* allow more time for a BULK device to react - some are slow */
++#define BULK_TO 5000 /* timeout in milliseconds */
++ if (usb_pipetype (pipe) == PIPE_BULK)
++ timeout = BULK_TO;
++ else
++ timeout = 100;
++
++ /* wait for it to complete */
++ for (;;) {
++ /* check whether the controller is done */
++ stat = hc_interrupt();
++ if (stat < 0) {
++ stat = USB_ST_CRC_ERR;
++ break;
++ }
++ if (stat >= 0 && stat != 0xff) {
++ /* 0xff is returned for an SF-interrupt */
++ break;
++ }
++ if (--timeout) {
++ wait_ms(1);
++ } else {
++ err("CTL:TIMEOUT ");
++ stat = USB_ST_CRC_ERR;
++ break;
++ }
++ }
++ /* we got an Root Hub Status Change interrupt */
++ if (got_rhsc) {
++#ifdef DEBUG
++ ohci_dump_roothub (&gohci, 1);
++#endif
++ got_rhsc = 0;
++ /* abuse timeout */
++ timeout = rh_check_port_status(&gohci);
++ if (timeout >= 0) {
++#if 0 /* this does nothing useful, but leave it here in case that changes */
++ /* the called routine adds 1 to the passed value */
++ usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
++#endif
++ /*
++ * XXX
++ * This is potentially dangerous because it assumes
++ * that only one device is ever plugged in!
++ */
++ devgone = dev;
++ }
++ }
++
++ dev->status = stat;
++ dev->act_len = transfer_len;
++
++#ifdef DEBUG
++ pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
++#else
++ wait_ms(1);
++#endif
++
++ /* free TDs in urb_priv */
++ urb_free_priv (&urb_priv);
++ return 0;
++}
++
++/* submit routines called from usb.c */
++int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
++ int transfer_len)
++{
++ info("submit_bulk_msg");
++ return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
++}
++
++int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
++ int transfer_len, struct devrequest *setup)
++{
++ int maxsize = usb_maxpacket(dev, pipe);
++
++ info("submit_control_msg");
++#ifdef DEBUG
++ urb_priv.actual_length = 0;
++ pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
++#else
++ wait_ms(1);
++#endif
++ if (!maxsize) {
++ err("submit_control_message: pipesize for pipe %lx is zero",
++ pipe);
++ return -1;
++ }
++ if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
++ gohci.rh.dev = dev;
++ /* root hub - redirect */
++ return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
++ setup);
++ }
++
++ return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
++}
++
++int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
++ int transfer_len, int interval)
++{
++ info("submit_int_msg");
++ return -1;
++}
++
++/*-------------------------------------------------------------------------*
++ * HC functions
++ *-------------------------------------------------------------------------*/
++
++/* reset the HC and BUS */
++
++static int hc_reset (ohci_t *ohci)
++{
++ int timeout = 30;
++ int smm_timeout = 50; /* 0,5 sec */
++
++ if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
++ writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
++ info("USB HC TakeOver from SMM");
++ while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
++ wait_ms (10);
++ if (--smm_timeout == 0) {
++ err("USB HC TakeOver failed!");
++ return -1;
++ }
++ }
++ }
++
++ /* Disable HC interrupts */
++ writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
++
++ dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
++ ohci->slot_name,
++ readl (&ohci->regs->control));
++
++ /* Reset USB (needed by some controllers) */
++ writel (0, &ohci->regs->control);
++
++ /* HC Reset requires max 10 us delay */
++ writel (OHCI_HCR, &ohci->regs->cmdstatus);
++ while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
++ if (--timeout == 0) {
++ err("USB HC reset timed out!");
++ return -1;
++ }
++ udelay (1);
++ }
++ return 0;
++}
++
++/*-------------------------------------------------------------------------*/
++
++/* Start an OHCI controller, set the BUS operational
++ * enable interrupts
++ * connect the virtual root hub */
++
++static int hc_start (ohci_t * ohci)
++{
++ __u32 mask;
++ unsigned int fminterval;
++
++ ohci->disabled = 1;
++
++ /* Tell the controller where the control and bulk lists are
++ * The lists are empty now. */
++
++ writel (0, &ohci->regs->ed_controlhead);
++ writel (0, &ohci->regs->ed_bulkhead);
++
++ writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
++
++ fminterval = 0x2edf;
++ writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
++ fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
++ writel (fminterval, &ohci->regs->fminterval);
++ writel (0x628, &ohci->regs->lsthresh);
++
++ /* start controller operations */
++ ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
++ ohci->disabled = 0;
++ writel (ohci->hc_control, &ohci->regs->control);
++
++ /* disable all interrupts */
++ mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
++ OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
++ OHCI_INTR_OC | OHCI_INTR_MIE);
++ writel (mask, &ohci->regs->intrdisable);
++ /* clear all interrupts */
++ mask &= ~OHCI_INTR_MIE;
++ writel (mask, &ohci->regs->intrstatus);
++ /* Choose the interrupts we care about now - but w/o MIE */
++ mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
++ writel (mask, &ohci->regs->intrenable);
++
++#ifdef OHCI_USE_NPS
++ /* required for AMD-756 and some Mac platforms */
++ writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
++ &ohci->regs->roothub.a);
++ writel (RH_HS_LPSC, &ohci->regs->roothub.status);
++#endif /* OHCI_USE_NPS */
++
++#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
++ /* POTPGT delay is bits 24-31, in 2 ms units. */
++ mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
++
++ /* connect the virtual root hub */
++ ohci->rh.devnum = 0;
++
++printf( "---> Done with hc_start\n" );
++
++ return 0;
++}
++
++/*-------------------------------------------------------------------------*/
++
++/* an interrupt happens */
++
++static int
++hc_interrupt (void)
++{
++ ohci_t *ohci = &gohci;
++ struct ohci_regs *regs = ohci->regs;
++ int ints;
++ int stat = -1;
++
++ if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
++ ints = OHCI_INTR_WDH;
++ } else {
++ ints = readl (&regs->intrstatus);
++ }
++
++dbg("Interrupt: %x frame: %x", ints, ohci->hcca->frame_no);
++
++ if (ints & OHCI_INTR_RHSC) {
++dbg("rhsc\n" );
++ got_rhsc = 1;
++ }
++
++ if (ints & OHCI_INTR_UE) {
++ ohci->disabled++;
++ err ("OHCI Unrecoverable Error, controller usb-%s disabled",
++ ohci->slot_name);
++ /* e.g. due to PCI Master/Target Abort */
++
++#ifdef DEBUG
++ ohci_dump (ohci, 1);
++#else
++ wait_ms(1);
++#endif
++ /* FIXME: be optimistic, hope that bug won't repeat often. */
++ /* Make some non-interrupt context restart the controller. */
++ /* Count and limit the retries though; either hardware or */
++ /* software errors can go forever... */
++ hc_reset (ohci);
++ return -1;
++ }
++
++ if (ints & OHCI_INTR_WDH) {
++ wait_ms(1);
++ writel (OHCI_INTR_WDH, &regs->intrdisable);
++ stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
++ writel (OHCI_INTR_WDH, &regs->intrenable);
++dbg("wdh: %x\n", stat );
++ goto out ;
++ }
++
++ if (ints & OHCI_INTR_SO) {
++ dbg("USB Schedule overrun\n");
++ writel (OHCI_INTR_SO, &regs->intrenable);
++ stat = -1;
++ }
++
++ /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
++ if (ints & OHCI_INTR_SF) {
++ unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
++ wait_ms(1);
++ writel (OHCI_INTR_SF, &regs->intrdisable);
++ if (ohci->ed_rm_list[frame] != NULL)
++ writel (OHCI_INTR_SF, &regs->intrenable);
++ if( -1 == stat )
++ stat = 0xff;
++dbg("sf\n" );
++ }
++ if( 0 == ints )
++ stat = 0 ;
++out:
++ writel (ints, &regs->intrstatus);
++ return stat;
++}
++
++/*-------------------------------------------------------------------------*/
++
++/*-------------------------------------------------------------------------*/
++
++/* De-allocate all resources.. */
++
++static void hc_release_ohci (ohci_t *ohci)
++{
++ dbg ("USB HC release ohci usb-%s", ohci->slot_name);
++
++ if (!ohci->disabled)
++ hc_reset (ohci);
++}
++
++/*-------------------------------------------------------------------------*/
++
++/*
++ * low level initalisation routine, called from usb.c
++ */
++static char ohci_inited = 0;
++
++int usb_lowlevel_init(void)
++{
++#ifdef FIXME
++ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
++ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
++ /*
++ * Set the 48 MHz UPLL clocking. Values are taken from
++ * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
++ */
++ clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
++ gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
++ /*
++ * Enable USB host clock.
++ */
++ clk_power->CLKCON |= (1 << 4);
++#endif
++#ifdef CONFIG_PXA27X
++ /*
++ * Section 20.6.1 of PXA Developer's reference manual
++ */
++ GPCR3 |= 0x80 ; // GP103 low
++
++ UHCHR |= UHCHR_SSEP2|UHCHR_SSEP1 ; // Port 2 and 3 not supported
++ UHCHR &= ~(UHCHR_SSE|UHCHR_SSEP0);
++
++// UHCRHS &= ~UHCRHS_LPS ;
++// UHCCOMS &= ~UHCCOMS_HCR ; // reset
++ CKEN |= CKEN10_USBHOST ;
++ udelay(10);
++ UHCHR &= ~(UHCHR_FHR|UHCHR_SSE);
++#elif defined( CONFIG_SM501 )
++ USB_GATE_MODE0 |= ENABLE_USBH ;
++ USB_GATE_MODE1 |= ENABLE_USBH ;
++#endif
++
++ memset (&gohci, 0, sizeof (ohci_t));
++ memset (&urb_priv, 0, sizeof (urb_priv_t));
++
++ /* align the storage */
++ if ((__u32)&ghcca[0] & 0xff) {
++ err("HCCA not aligned!!");
++ return -1;
++ }
++ phcca = &ghcca[0];
++ info("aligned ghcca %p", phcca);
++ memset(&ohci_dev, 0, sizeof(struct ohci_device));
++ if ((__u32)&ohci_dev.ed[0] & 0x7) {
++ err("EDs not aligned!!");
++ return -1;
++ }
++ memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
++ if ((__u32)gtd & 0x7) {
++ err("TDs not aligned!!");
++ return -1;
++ }
++ ptd = gtd;
++ gohci.hcca = phcca;
++ memset (phcca, 0, sizeof (struct ohci_hcca));
++
++ gohci.disabled = 1;
++ gohci.sleeping = 0;
++ gohci.irq = -1;
++ gohci.regs = (struct ohci_regs *)USBH_BASE ;
++ gohci.flags = 0;
++ gohci.slot_name = "s3c2400";
++
++ if (hc_reset (&gohci) < 0) {
++ err( "----> Error from hc_reset\n" );
++ hc_release_ohci (&gohci);
++ /* Initialization failed */
++#ifdef FIXME
++ clk_power->CLKCON &= ~(1 << 4);
++#endif
++#ifdef CONFIG_PXA27X
++ CKEN &= ~CKEN10_USBHOST ;
++#elif defined( CONFIG_SM501 )
++#endif
++ return -1;
++ }
++
++ /* FIXME this is a second HC reset; why?? */
++ writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
++ wait_ms (10);
++
++ if (hc_start (&gohci) < 0) {
++ err ("can't start usb-%s", gohci.slot_name);
++ hc_release_ohci (&gohci);
++ /* Initialization failed */
++#ifdef FIXME
++ clk_power->CLKCON &= ~(1 << 4);
++#endif
++#ifdef CONFIG_PXA27X
++ CKEN &= ~CKEN10_USBHOST ;
++#elif defined( CONFIG_SM501 )
++#endif
++ return -1;
++ }
++
++#ifdef DEBUG
++ ohci_dump (&gohci, 1);
++#else
++ wait_ms(1);
++#endif
++printf( "----> end of low_level_init()\n" );
++ ohci_inited = 1;
++ return 0;
++}
++
++int usb_lowlevel_stop(void)
++{
++ /* this gets called really early - before the controller has */
++ /* even been initialized! */
++ if (!ohci_inited)
++ return 0;
++ /* TODO release any interrupts, etc. */
++ /* call hc_release_ohci() here ? */
++ hc_reset (&gohci);
++
++#ifdef CONFIG_PXA27X
++ /*
++ * Section 20.7.4.4 of PXA Developer's reference manual
++ */
++ UHCCOMS |= UHCCOMS_HCR ; // reset
++ udelay(10);
++ UHCRHS |= UHCRHS_LPS ;
++ UHCHR |= UHCHR_SSE ;
++ CKEN &= ~CKEN10_USBHOST ;
++#elif defined( CONFIG_SM501 )
++#endif
++
++ return 0;
++}
++
++#endif /* CONFIG_USB_OHCI */
+diff -u -r --new-file u-boot-1.1.2/cpu/pxa/usb_ohci.h u-boot-1.1.2-neon/cpu/pxa/usb_ohci.h
+--- u-boot-1.1.2/cpu/pxa/usb_ohci.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/cpu/pxa/usb_ohci.h 2007-08-11 21:07:20.000000000 +0200
+@@ -0,0 +1,419 @@
++/*
++ * URB OHCI HCD (Host Controller Driver) for USB.
++ *
++ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
++ * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
++ *
++ * usb-ohci.h
++ */
++
++
++static int cc_to_error[16] = {
++
++/* mapping of the OHCI CC status to error codes */
++ /* No Error */ 0,
++ /* CRC Error */ USB_ST_CRC_ERR,
++ /* Bit Stuff */ USB_ST_BIT_ERR,
++ /* Data Togg */ USB_ST_CRC_ERR,
++ /* Stall */ USB_ST_STALLED,
++ /* DevNotResp */ -1,
++ /* PIDCheck */ USB_ST_BIT_ERR,
++ /* UnExpPID */ USB_ST_BIT_ERR,
++ /* DataOver */ USB_ST_BUF_ERR,
++ /* DataUnder */ USB_ST_BUF_ERR,
++ /* reservd */ -1,
++ /* reservd */ -1,
++ /* BufferOver */ USB_ST_BUF_ERR,
++ /* BuffUnder */ USB_ST_BUF_ERR,
++ /* Not Access */ -1,
++ /* Not Access */ -1
++};
++
++/* ED States */
++
++#define ED_NEW 0x00
++#define ED_UNLINK 0x01
++#define ED_OPER 0x02
++#define ED_DEL 0x04
++#define ED_URB_DEL 0x08
++
++/* usb_ohci_ed */
++struct ed {
++ __u32 hwINFO;
++ __u32 hwTailP;
++ __u32 hwHeadP;
++ __u32 hwNextED;
++
++ struct ed *ed_prev;
++ __u8 int_period;
++ __u8 int_branch;
++ __u8 int_load;
++ __u8 int_interval;
++ __u8 state;
++ __u8 type;
++ __u16 last_iso;
++ struct ed *ed_rm_list;
++
++ struct usb_device *usb_dev;
++ __u32 unused[3];
++} __attribute((aligned(16)));
++typedef struct ed ed_t;
++
++
++/* TD info field */
++#define TD_CC 0xf0000000
++#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
++#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
++#define TD_EC 0x0C000000
++#define TD_T 0x03000000
++#define TD_T_DATA0 0x02000000
++#define TD_T_DATA1 0x03000000
++#define TD_T_TOGGLE 0x00000000
++#define TD_R 0x00040000
++#define TD_DI 0x00E00000
++#define TD_DI_SET(X) (((X) & 0x07)<< 21)
++#define TD_DP 0x00180000
++#define TD_DP_SETUP 0x00000000
++#define TD_DP_IN 0x00100000
++#define TD_DP_OUT 0x00080000
++
++#define TD_ISO 0x00010000
++#define TD_DEL 0x00020000
++
++/* CC Codes */
++#define TD_CC_NOERROR 0x00
++#define TD_CC_CRC 0x01
++#define TD_CC_BITSTUFFING 0x02
++#define TD_CC_DATATOGGLEM 0x03
++#define TD_CC_STALL 0x04
++#define TD_DEVNOTRESP 0x05
++#define TD_PIDCHECKFAIL 0x06
++#define TD_UNEXPECTEDPID 0x07
++#define TD_DATAOVERRUN 0x08
++#define TD_DATAUNDERRUN 0x09
++#define TD_BUFFEROVERRUN 0x0C
++#define TD_BUFFERUNDERRUN 0x0D
++#define TD_NOTACCESSED 0x0F
++
++
++#define MAXPSW 1
++
++struct td {
++ __u32 hwINFO;
++ __u32 hwCBP; /* Current Buffer Pointer */
++ __u32 hwNextTD; /* Next TD Pointer */
++ __u32 hwBE; /* Memory Buffer End Pointer */
++
++ __u16 hwPSW[MAXPSW];
++ __u8 unused;
++ __u8 index;
++ struct ed *ed;
++ struct td *next_dl_td;
++ struct usb_device *usb_dev;
++ int transfer_len;
++ __u32 data;
++
++ __u32 unused2[2];
++} __attribute((aligned(32)));
++typedef struct td td_t;
++
++#define OHCI_ED_SKIP (1 << 14)
++
++/*
++ * The HCCA (Host Controller Communications Area) is a 256 byte
++ * structure defined in the OHCI spec. that the host controller is
++ * told the base address of. It must be 256-byte aligned.
++ */
++
++#define NUM_INTS 32 /* part of the OHCI standard */
++struct ohci_hcca {
++ __u32 int_table[NUM_INTS]; /* Interrupt ED table */
++ __u16 frame_no; /* current frame number */
++ __u16 pad1; /* set to 0 on each frame_no change */
++ __u32 done_head; /* info returned for an interrupt */
++ u8 reserved_for_hc[116];
++} __attribute((aligned(256)));
++
++
++/*
++ * Maximum number of root hub ports.
++ */
++#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */
++
++/*
++ * This is the structure of the OHCI controller's memory mapped I/O
++ * region. This is Memory Mapped I/O. You must use the readl() and
++ * writel() macros defined in asm/io.h to access these!!
++ */
++struct ohci_regs {
++ /* control and status registers */
++ __u32 revision;
++ __u32 control;
++ __u32 cmdstatus;
++ __u32 intrstatus;
++ __u32 intrenable;
++ __u32 intrdisable;
++ /* memory pointers */
++ __u32 hcca;
++ __u32 ed_periodcurrent;
++ __u32 ed_controlhead;
++ __u32 ed_controlcurrent;
++ __u32 ed_bulkhead;
++ __u32 ed_bulkcurrent;
++ __u32 donehead;
++ /* frame counters */
++ __u32 fminterval;
++ __u32 fmremaining;
++ __u32 fmnumber;
++ __u32 periodicstart;
++ __u32 lsthresh;
++ /* Root hub ports */
++ struct ohci_roothub_regs {
++ __u32 a;
++ __u32 b;
++ __u32 status;
++ __u32 portstatus[MAX_ROOT_PORTS];
++ } roothub;
++} __attribute((aligned(32)));
++
++
++/* OHCI CONTROL AND STATUS REGISTER MASKS */
++
++/*
++ * HcControl (control) register masks
++ */
++#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
++#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
++#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
++#define OHCI_CTRL_CLE (1 << 4) /* control list enable */
++#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
++#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
++#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
++#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
++#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
++
++/* pre-shifted values for HCFS */
++# define OHCI_USB_RESET (0 << 6)
++# define OHCI_USB_RESUME (1 << 6)
++# define OHCI_USB_OPER (2 << 6)
++# define OHCI_USB_SUSPEND (3 << 6)
++
++/*
++ * HcCommandStatus (cmdstatus) register masks
++ */
++#define OHCI_HCR (1 << 0) /* host controller reset */
++#define OHCI_CLF (1 << 1) /* control list filled */
++#define OHCI_BLF (1 << 2) /* bulk list filled */
++#define OHCI_OCR (1 << 3) /* ownership change request */
++#define OHCI_SOC (3 << 16) /* scheduling overrun count */
++
++/*
++ * masks used with interrupt registers:
++ * HcInterruptStatus (intrstatus)
++ * HcInterruptEnable (intrenable)
++ * HcInterruptDisable (intrdisable)
++ */
++#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
++#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
++#define OHCI_INTR_SF (1 << 2) /* start frame */
++#define OHCI_INTR_RD (1 << 3) /* resume detect */
++#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
++#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
++#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
++#define OHCI_INTR_OC (1 << 30) /* ownership change */
++#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
++
++
++/* Virtual Root HUB */
++struct virt_root_hub {
++ int devnum; /* Address of Root Hub endpoint */
++ void *dev; /* was urb */
++ void *int_addr;
++ int send;
++ int interval;
++};
++
++/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
++
++/* destination of request */
++#define RH_INTERFACE 0x01
++#define RH_ENDPOINT 0x02
++#define RH_OTHER 0x03
++
++#define RH_CLASS 0x20
++#define RH_VENDOR 0x40
++
++/* Requests: bRequest << 8 | bmRequestType */
++#define RH_GET_STATUS 0x0080
++#define RH_CLEAR_FEATURE 0x0100
++#define RH_SET_FEATURE 0x0300
++#define RH_SET_ADDRESS 0x0500
++#define RH_GET_DESCRIPTOR 0x0680
++#define RH_SET_DESCRIPTOR 0x0700
++#define RH_GET_CONFIGURATION 0x0880
++#define RH_SET_CONFIGURATION 0x0900
++#define RH_GET_STATE 0x0280
++#define RH_GET_INTERFACE 0x0A80
++#define RH_SET_INTERFACE 0x0B00
++#define RH_SYNC_FRAME 0x0C80
++/* Our Vendor Specific Request */
++#define RH_SET_EP 0x2000
++
++
++/* Hub port features */
++#define RH_PORT_CONNECTION 0x00
++#define RH_PORT_ENABLE 0x01
++#define RH_PORT_SUSPEND 0x02
++#define RH_PORT_OVER_CURRENT 0x03
++#define RH_PORT_RESET 0x04
++#define RH_PORT_POWER 0x08
++#define RH_PORT_LOW_SPEED 0x09
++
++#define RH_C_PORT_CONNECTION 0x10
++#define RH_C_PORT_ENABLE 0x11
++#define RH_C_PORT_SUSPEND 0x12
++#define RH_C_PORT_OVER_CURRENT 0x13
++#define RH_C_PORT_RESET 0x14
++
++/* Hub features */
++#define RH_C_HUB_LOCAL_POWER 0x00
++#define RH_C_HUB_OVER_CURRENT 0x01
++
++#define RH_DEVICE_REMOTE_WAKEUP 0x00
++#define RH_ENDPOINT_STALL 0x01
++
++#define RH_ACK 0x01
++#define RH_REQ_ERR -1
++#define RH_NACK 0x00
++
++
++/* OHCI ROOT HUB REGISTER MASKS */
++
++/* roothub.portstatus [i] bits */
++#define RH_PS_CCS 0x00000001 /* current connect status */
++#define RH_PS_PES 0x00000002 /* port enable status*/
++#define RH_PS_PSS 0x00000004 /* port suspend status */
++#define RH_PS_POCI 0x00000008 /* port over current indicator */
++#define RH_PS_PRS 0x00000010 /* port reset status */
++#define RH_PS_PPS 0x00000100 /* port power status */
++#define RH_PS_LSDA 0x00000200 /* low speed device attached */
++#define RH_PS_CSC 0x00010000 /* connect status change */
++#define RH_PS_PESC 0x00020000 /* port enable status change */
++#define RH_PS_PSSC 0x00040000 /* port suspend status change */
++#define RH_PS_OCIC 0x00080000 /* over current indicator change */
++#define RH_PS_PRSC 0x00100000 /* port reset status change */
++
++/* roothub.status bits */
++#define RH_HS_LPS 0x00000001 /* local power status */
++#define RH_HS_OCI 0x00000002 /* over current indicator */
++#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
++#define RH_HS_LPSC 0x00010000 /* local power status change */
++#define RH_HS_OCIC 0x00020000 /* over current indicator change */
++#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
++
++/* roothub.b masks */
++#define RH_B_DR 0x0000ffff /* device removable flags */
++#define RH_B_PPCM 0xffff0000 /* port power control mask */
++
++/* roothub.a masks */
++#define RH_A_NDP (0xff << 0) /* number of downstream ports */
++#define RH_A_PSM (1 << 8) /* power switching mode */
++#define RH_A_NPS (1 << 9) /* no power switching */
++#define RH_A_DT (1 << 10) /* device type (mbz) */
++#define RH_A_OCPM (1 << 11) /* over current protection mode */
++#define RH_A_NOCP (1 << 12) /* no over current protection */
++#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
++
++/* urb */
++#define N_URB_TD 48
++typedef struct
++{
++ ed_t *ed;
++ __u16 length; /* number of tds associated with this request */
++ __u16 td_cnt; /* number of tds already serviced */
++ int state;
++ unsigned long pipe;
++ int actual_length;
++ td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
++} urb_priv_t;
++#define URB_DEL 1
++
++/*
++ * This is the full ohci controller description
++ *
++ * Note how the "proper" USB information is just
++ * a subset of what the full implementation needs. (Linus)
++ */
++
++
++typedef struct ohci {
++ struct ohci_hcca *hcca; /* hcca */
++ /*dma_addr_t hcca_dma;*/
++
++ int irq;
++ int disabled; /* e.g. got a UE, we're hung */
++ int sleeping;
++ unsigned long flags; /* for HC bugs */
++
++ struct ohci_regs *regs; /* OHCI controller's memory */
++
++ ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
++ ed_t *ed_bulktail; /* last endpoint of bulk list */
++ ed_t *ed_controltail; /* last endpoint of control list */
++ int intrstatus;
++ __u32 hc_control; /* copy of the hc control reg */
++ struct usb_device *dev[32];
++ struct virt_root_hub rh;
++
++ const char *slot_name;
++} ohci_t;
++
++#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
++
++struct ohci_device {
++ ed_t ed[NUM_EDS];
++ int ed_cnt;
++};
++
++/* hcd */
++/* endpoint */
++static int ep_link(ohci_t * ohci, ed_t * ed);
++static int ep_unlink(ohci_t * ohci, ed_t * ed);
++static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
++
++/*-------------------------------------------------------------------------*/
++
++/* we need more TDs than EDs */
++#define NUM_TD 64
++
++/* +1 so we can align the storage */
++td_t gtd[NUM_TD+1];
++/* pointers to aligned storage */
++td_t *ptd;
++
++/* TDs ... */
++static inline struct td *
++td_alloc (struct usb_device *usb_dev)
++{
++ int i;
++ struct td *td;
++
++ td = NULL;
++ for (i = 0; i < NUM_TD; i++)
++ {
++ if (ptd[i].usb_dev == NULL)
++ {
++ td = &ptd[i];
++ td->usb_dev = usb_dev;
++ break;
++ }
++ }
++
++ return td;
++}
++
++static inline void
++ed_free (struct ed *ed)
++{
++ ed->usb_dev = NULL;
++}
+diff -u -r --new-file u-boot-1.1.2/.cvsignore u-boot-1.1.2-neon/.cvsignore
+--- u-boot-1.1.2/.cvsignore 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/.cvsignore 2007-08-11 21:07:19.000000000 +0200
+@@ -0,0 +1,13 @@
++*.map
++*.scr
++*.gz
++select.h
++*.log
++select.mk
++u-boot
++u-boot.bin
++u-boot.map
++u-boot.map.sorted
++u-boot.srec
++u-boot-binaries.zip
++
+diff -u -r --new-file u-boot-1.1.2/drivers/lan91c96.h u-boot-1.1.2-neon/drivers/lan91c96.h
+--- u-boot-1.1.2/drivers/lan91c96.h 2004-06-07 00:11:41.000000000 +0200
++++ u-boot-1.1.2-neon/drivers/lan91c96.h 2007-08-11 21:07:21.000000000 +0200
+@@ -76,7 +76,7 @@
+
+ #define SMC_IO_EXTENT 16
+
+-#ifdef CONFIG_PXA250
++#if defined( CONFIG_PXA250 ) || defined( CONFIG_PXA270 )
+
+ #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+( r * 4 ))))
+ #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+( r * 4 ))))
+@@ -139,7 +139,7 @@
+ }; \
+ })
+
+-#else /* if not CONFIG_PXA250 */
++#else /* if not CONFIG_PXA250 or CONFIG_PXA270 */
+
+ /*
+ * We have only 16 Bit PCMCIA access on Socket 0
+diff -u -r --new-file u-boot-1.1.2/drivers/smc91111.c u-boot-1.1.2-neon/drivers/smc91111.c
+--- u-boot-1.1.2/drivers/smc91111.c 2004-11-22 23:20:09.000000000 +0100
++++ u-boot-1.1.2-neon/drivers/smc91111.c 2007-08-11 21:07:21.000000000 +0200
+@@ -1583,6 +1583,101 @@
+ return (0);
+ }
+
++#define SMC_GET_INT_MASK() (SMC_inw( SMC91111_INT_REG ) >> 8)
++#define SMC_SET_INT_MASK(x) SMC_outw( (x) << 8, SMC91111_INT_REG )
++#define SMC_CURRENT_BANK() SMC_inw( BANK_SELECT )
++#define SMC_GET_CTL() SMC_inw( CTL_REG )
++#define SMC_SET_CTL(x) SMC_outw( x, CTL_REG )
++#define SMC_GET_MII() SMC_inw( MII_REG )
++#define SMC_SET_MII(x) SMC_outw( x, MII_REG )
++#define SMC_GET_PTR() SMC_inw( PTR_REG )
++#define SMC_SET_PTR(x) SMC_outw( x, PTR_REG )
++
++static int writeEEprom(int i,unsigned short val,unsigned short ctl)
++{
++ SMC_SELECT_BANK( 2 );
++ SMC_SET_PTR( i );
++ SMC_SELECT_BANK( 1 );
++ SMC_outw( val, GP_REG );
++ udelay(1);
++ SMC_SET_CTL( ctl | CTL_EEPROM_SELECT | CTL_STORE );
++ int j=0;
++ do {
++ udelay(10);
++ j++;
++ if (j>=100000) return -1;
++ } while (SMC_GET_CTL() & CTL_STORE);
++ return 0;
++}
++
++#define SMC_SET_MAC_ADDR(addr) \
++ do { \
++ SMC_outw( addr[0]|(addr[1] << 8), ADDR0_REG ); \
++ SMC_outw( addr[2]|(addr[3] << 8), ADDR1_REG ); \
++ SMC_outw( addr[4]|(addr[5] << 8), ADDR2_REG ); \
++ } while (0)
++
++int set_rom_mac (char const *mac)
++{
++ unsigned short saved_bank = SMC_CURRENT_BANK();
++ SMC_SELECT_BANK( 2 );
++
++ unsigned short saved_mask = SMC_GET_INT_MASK();
++ SMC_SET_INT_MASK( 0 );
++
++ unsigned short saved_ptr = SMC_GET_PTR();
++
++ SMC_SELECT_BANK( 1 );
++
++ unsigned short saved_ctl = SMC_GET_CTL();
++
++ SMC_SET_MAC_ADDR(mac);
++
++ SMC_SELECT_BANK( 3 );
++ unsigned short mii_reg = SMC_GET_MII();
++
++ SMC_SET_MII(mii_reg & ~(0x0f));
++
++ SMC_SELECT_BANK( 1 );
++
++ SMC_SET_CTL( saved_ctl | CTL_EEPROM_SELECT );
++ unsigned short cfg = CONFIG_DEFAULT
++ | CONFIG_NO_WAIT
++ | CONFIG_EPH_POWER_EN;
++ unsigned short bar = (unsigned short)( SMC_BASE_ADDRESS );
++//a4, a10,a11,a12 must be all zeros
++ bar = (bar & 0xe000) | ((bar & 0x3e0)<<3) | (0x27);
++ int i=0;
++ while (i < 0x20) {
++ if (writeEEprom(i,cfg,saved_ctl)) break;
++ if (writeEEprom(i+1,bar,saved_ctl)) break;
++ if (writeEEprom(i+2,0,saved_ctl)) break;
++ if (writeEEprom(i+3,0,saved_ctl)) break;
++ i+=4;
++ }
++
++ int j = 0;
++ if (i==0x20) {
++ while (j < 6) {
++ if (writeEEprom(i,mac[j]|(mac[j+1]<<8),saved_ctl)) break;
++ i++; j+=2;
++ }
++ }
++
++ SMC_SET_CTL( saved_ctl );
++
++ SMC_SELECT_BANK( 2 );
++ SMC_SET_PTR( saved_ptr );
++ SMC_SET_INT_MASK( saved_mask );
++ SMC_SELECT_BANK( saved_bank );
++
++ return 6 == j ;
++}
++
++static char const invalidMac[6] = {
++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
++};
++
+ int get_rom_mac (char *v_rom_mac)
+ {
+ #ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */
+@@ -1601,6 +1696,9 @@
+ valid_mac |= v_rom_mac[i];
+ }
+
++ if( valid_mac )
++ valid_mac = ( 0 != memcmp( invalidMac, v_rom_mac, sizeof(invalidMac) ) );
++
+ return (valid_mac ? 1 : 0);
+ #endif
+ }
+diff -u -r --new-file u-boot-1.1.2/drivers/smc91111.h u-boot-1.1.2-neon/drivers/smc91111.h
+--- u-boot-1.1.2/drivers/smc91111.h 2004-11-02 14:00:56.000000000 +0100
++++ u-boot-1.1.2-neon/drivers/smc91111.h 2007-08-11 21:07:21.000000000 +0200
+@@ -74,7 +74,7 @@
+
+ #define SMC_IO_EXTENT 16
+
+-#ifdef CONFIG_PXA250
++#if defined( CONFIG_PXA250 ) || defined( CONFIG_PXA270 )
+
+ #ifdef CONFIG_XSENGINE
+ #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))))
+@@ -176,7 +176,7 @@
+ }; \
+ })
+
+-#else /* if not CONFIG_PXA250 */
++#else /* if not CONFIG_PXA250 or CONFIG_PXA270 */
+
+ #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */
+ /*
+diff -u -r --new-file u-boot-1.1.2/examples/Makefile u-boot-1.1.2-neon/examples/Makefile
+--- u-boot-1.1.2/examples/Makefile 2004-10-10 23:27:33.000000000 +0200
++++ u-boot-1.1.2-neon/examples/Makefile 2007-08-11 21:07:21.000000000 +0200
+@@ -100,12 +100,12 @@
+ LIBCOBJS= stubs.o
+ LIBOBJS = $(LIBAOBJS) $(LIBCOBJS)
+
+-gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+-clibdir := $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`)
++gcclibdir := $(shell dirname "`$(CC) -print-libgcc-file-name`")
++clibdir := $(shell dirname "`$(CC) $(CFLAGS) -print-file-name=libc.a`")
+
+ CPPFLAGS += -I..
+
+-all: .depend $(LIB) $(SREC) $(BIN)
++all: .depend $(LIB)
+
+ #########################################################################
+ $(LIB): .depend $(LIBOBJS)
+diff -u -r --new-file u-boot-1.1.2/fs/fat/fat.c u-boot-1.1.2-neon/fs/fat/fat.c
+--- u-boot-1.1.2/fs/fat/fat.c 2004-12-16 18:57:26.000000000 +0100
++++ u-boot-1.1.2-neon/fs/fat/fat.c 2007-08-11 21:07:21.000000000 +0200
+@@ -52,6 +52,8 @@
+ #define DOS_PART_TBL_OFFSET 0x1be
+ #define DOS_PART_MAGIC_OFFSET 0x1fe
+ #define DOS_FS_TYPE_OFFSET 0x36
++#define DOS_FS_TYPE_OFFSET_FAT_16 0x36 // Code relating to this constant was changed/added by Dubner 2005-05-20
++#define DOS_FS_TYPE_OFFSET_FAT_32 0x52 // Code relating to this constant was changed/added by Dubner 2005-05-20
+
+ int disk_read (__u32 startblock, __u32 getsize, __u8 * bufptr)
+ {
+@@ -83,7 +85,8 @@
+ /* no signature found */
+ return -1;
+ }
+- if(!strncmp(&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) {
++ if(!strncmp(&buffer[DOS_FS_TYPE_OFFSET_FAT_16],"FAT",3)
++ || !strncmp (&buffer[DOS_FS_TYPE_OFFSET_FAT_32], "FAT", 3)) {
+ /* ok, we assume we are on a PBR only */
+ cur_part = 1;
+ part_offset=0;
+@@ -342,7 +345,7 @@
+ newclust = get_fatent(mydata, endclust);
+ if((newclust -1)!=endclust)
+ goto getit;
+- if (newclust <= 0x0001 || newclust >= 0xfff0) {
++ if (newclust <= 0x0001 ) { // || newclust >= 0xfff0) {
+ FAT_DPRINT("curclust: 0x%x\n", newclust);
+ FAT_DPRINT("Invalid FAT entry\n");
+ return gotsize;
+@@ -890,7 +893,7 @@
+ dentptr++;
+ continue;
+ }
+- if (strcmp (fnamecopy, s_name) && strcmp (fnamecopy, l_name)) {
++ if (fnmatch(fnamecopy, s_name,0) && fnmatch(fnamecopy, l_name,0)) {
+ FAT_DPRINT ("RootMismatch: |%s|%s|\n", s_name, l_name);
+ dentptr++;
+ continue;
+diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/BigMacro.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/BigMacro.h
+--- u-boot-1.1.2/include/asm-arm/arch-pxa/BigMacro.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/BigMacro.h 2007-08-11 21:07:21.000000000 +0200
+@@ -0,0 +1,325 @@
++//
++// linux/include/asm-arm/BigMacro.h
++//
++// Author: Troy Kisky
++// Created: Jun 30, 2002
++// Copyright: Boundary Devices
++//
++// This program is free software; you can redistribute it and/or modify
++// it under the terms of the GNU General Public License version 2 as
++// published by the Free Software Foundation.
++//
++ .nolist
++
++//find set bit pair >= curbit
++//out: __nBit
++ .ifdef __ARMASM
++ GBLA __nBit
++ GBLA __nMask
++ GBLA __nVal
++; DCD __nV1
++
++.macro NextSetBitUp val,curBit
++ LCLA __nV1
++ .set __nBit,(\curBit)
++ .set __nV1,(\val)
++ WHILE ( (__nBit < 30) :LAND: ( (__nV1 :AND: (0x03:SHL:__nBit))=0) )
++ .set __nBit,(__nBit)+2
++ WEND
++.endm
++
++//find set bit pair <= curbit
++//out: __nBit
++.macro NextSetBitDown val,curBit
++ LCLA __nV1
++ .set __nBit,(\curBit)
++ .set __nV1,(\val)
++ WHILE ( (__nBit <> 0) :LAND: ( (__nV1:AND:(0xc0:SHL:__nBit))=0) )
++ .set __nBit,(__nBit)-2
++ WEND
++.endm
++ .else
++
++.macro NextSetBitUp val,curBit
++ .set __nBit,(\curBit)
++ .set __nV1,(\val)
++ .if ((__nV1) & (0x03<<(__nBit)))
++ .else
++ .if ((__nBit)-30)
++ NextSetBitUp __nV1,((__nBit)+2)
++ .endif
++ .endif
++ .set __nV1,0
++.endm
++
++//find set bit pair <= curbit
++//out: __nBit
++.macro NextSetBitDown val,curBit
++ .set __nBit,(\curBit)
++ .set __nV1,(\val)
++ .if ((__nV1)&(0xc0<<(__nBit)))
++ .else
++ .if (__nBit)
++ NextSetBitDown __nV1,((__nBit)-2)
++ .endif
++ .endif
++ .set __nV1,0
++.endm
++ .endif
++
++//OUT: __nMask
++.macro NextSetMask val
++ NextSetBitDown \val,24
++ .if (__nBit>=20)
++ NextSetBitUp \val,__nBit
++ .set __nMask,(0xff<<((__nBit)-16))
++ .set __nMask,(((__nMask)>>16)+(((__nMask)<<16)&0xffff0000))
++ .else
++ .set __nMask,(0xff<<(__nBit))
++ .endif
++
++.endm
++
++.macro Big2CC inst,dest,val
++ .set __nVal,(\val)
++ .if (__nVal)<>0
++ NextSetMask __nVal
++ \inst \dest,\dest,#(__nVal)&(__nMask)
++ Big2CC \inst,\dest,(__nVal)&~(__nMask)
++ .endif
++.endm
++
++.macro BigAnd2CC cc,dest,val
++ .set __nVal,(\val)
++ .if (~__nVal)<>0
++ NextSetMask __nVal
++ .if (((__nVal)&~(__nMask))=0)
++ and\cc \dest,\dest,#(__nVal)&(__nMask)
++ .else
++ Big2CC bic\cc,\dest,~__nVal
++ .endif
++ .endif
++.endm
++
++///////////////////////////////////////////////////////
++.macro BigMovCC cc,dest, val
++ .set __nVal,(\val)
++ NextSetMask ~__nVal
++ .if (((~(__nVal))&~(__nMask)) > 0x255)
++ NextSetMask __nVal
++ mov\cc \dest,#(__nVal)&(__nMask)
++ .if (((__nVal)&0xffff) ^ (((__nVal)>>16)&0xffff))<>0
++ Big2CC orr\cc,\dest,(__nVal)&~(__nMask)
++ .else
++ .set __nVal,(__nVal)&~(__nMask)
++ .if (__nVal)<>0
++ NextSetMask __nVal
++ orr\cc \dest,\dest,#(__nVal)&(__nMask)
++ .set __nVal,(__nVal)&~(__nMask)
++ .if (__nVal)<>0
++ orr\cc \dest,\dest,\dest,LSR #16
++ .endif
++ .endif
++ .endif
++ .else
++ mvn\cc \dest,#(~(__nVal))&(__nMask) //complement of complement is original
++ Big2CC bic\cc,\dest,(~(__nVal))&~(__nMask)
++ .endif
++.endm
++
++
++.macro BigAddCC cc,dest,src,val
++ .set __nVal,(\val)
++ .if (__nVal)<>0
++ NextSetMask -__nVal
++ .if (((-(__nVal))&~(__nMask)) > 0x255)
++ NextSetMask __nVal
++ add\cc \dest,\src,#(__nVal)&(__nMask)
++ Big2CC add\cc,\dest,(__nVal)&~(__nMask)
++ .else
++ sub\cc \dest,\src,#(-(__nVal))&(__nMask)
++ Big2CC sub\cc,\dest,(-(__nVal))&~(__nMask)
++ .endif
++ .else
++ mov\cc \dest,\src
++ .endif
++.endm
++
++.macro BigSubCC cc,dest,src,val
++ .set __nVal,(\val)
++ BigAddCC \cc,\dest,\src,-__nVal
++.endm
++
++.macro BigCC inst,cc,dest,src,val
++ .set __nVal,(\val)
++ .if (__nVal)<>0
++ NextSetMask __nVal
++ \inst\cc \dest,\src,#(__nVal)&(__nMask)
++ Big2CC \inst\cc,\dest,(__nVal)&~(__nMask)
++ .else
++ mov\cc \dest,\src
++ .endif
++.endm
++
++
++.macro BigAndCC cc,dest,src,val
++ .set __nVal,(\val)
++ .if (~__nVal)<>0
++ NextSetMask __nVal
++ .if (((__nVal)&~(__nMask))=0)
++ and\cc \dest,\src,#(__nVal)&(__nMask)
++ .else
++ BigCC bic,\cc,\dest,\src,~__nVal
++ .endif
++ .else
++ mov\cc \dest,\src
++ .endif
++.endm
++
++/////////////////////////////////////
++//dest, value
++.macro BigAdd2 dest,val
++ Big2CC add,\dest,\val
++.endm
++.macro BigAdd2Eq dest,val
++ Big2CC addeq,\dest,\val
++.endm
++.macro BigAdd2Ne dest,val
++ Big2CC addne,\dest,\val
++.endm
++
++.macro BigSub2 dest,val
++ Big2CC sub,\dest,\val
++.endm
++.macro BigSub2Eq dest,val
++ Big2CC subeq,\dest,\val
++.endm
++.macro BigSub2Ne dest,val
++ Big2CC subne,\dest,\val
++.endm
++
++.macro BigOrr2 dest,val
++ Big2CC orr,\dest,\val
++.endm
++.macro BigOrr2Eq dest,val
++ Big2CC orreq,\dest,\val
++.endm
++.macro BigOrr2Ne dest,val
++ Big2CC orrne,\dest,\val
++.endm
++
++.macro BigEor2 dest,val
++ Big2CC eor,\dest,\val
++.endm
++.macro BigEor2Eq dest,val
++ Big2CC eoreq,\dest,\val
++.endm
++.macro BigEor2Ne dest,val
++ Big2CC eorne,\dest,\val
++.endm
++.macro BigEor2Cs dest,val
++ Big2CC eorcs,\dest,\val
++.endm
++.macro BigEor2Cc dest,val
++ Big2CC eorcc,\dest,\val
++.endm
++
++.macro BigBic2 dest,val
++ Big2CC bic,\dest,\val
++.endm
++.macro BigBic2Eq dest,val
++ Big2CC biceq,\dest,\val
++.endm
++.macro BigBic2Ne dest,val
++ Big2CC bicne,\dest,\val
++.endm
++
++.macro BigAnd2 dest,val
++ BigAnd2CC al,\dest,\val
++.endm
++.macro BigAnd2Eq dest,val
++ BigAnd2CC eq,\dest,\val
++.endm
++.macro BigAnd2Ne dest,val
++ BigAnd2CC ne,\dest,\val
++.endm
++/////////////////////////////////////
++
++.macro BigMov dest,val
++ BigMovCC al,\dest,\val
++.endm
++.macro BigMovEq dest,val
++ BigMovCC eq,\dest,\val
++.endm
++.macro BigMovNe dest,val
++ BigMovCC ne,\dest,\val
++.endm
++// dest,src,value
++.macro BigAdd dest,src,val
++ BigAddCC al,\dest,\src,\val
++.endm
++.macro BigAddEq dest,src,val
++ BigAddCC eq,\dest,\src,\val
++.endm
++.macro BigAddNe dest,src,val
++ BigAddCC ne,\dest,\src,\val
++.endm
++
++.macro BigSub dest,src,val
++ BigSubCC al,\dest,\src,\val
++.endm
++.macro BigSubEq dest,src,val
++ BigSubCC eq,\dest,\src,\val
++.endm
++.macro BigSubNe dest,src,val
++ BigSubCC ne,\dest,\src,\val
++.endm
++
++.macro BigOrr dest,src,val
++ BigCC orr,al,\dest,\src,\val
++.endm
++.macro BigOrrEq dest,src,val
++ BigCC orr,eq,\dest,\src,\val
++.endm
++.macro BigOrrNe dest,src,val
++ BigCC orr,ne,\dest,\src,\val
++.endm
++
++.macro BigEor dest,src,val
++ BigCC eor,al,\dest,\src,\val
++.endm
++.macro BigEorEq dest,src,val
++ BigCC eor,eq,\dest,\src,\val
++.endm
++.macro BigEorNe dest,src,val
++ BigCC eor,ne,\dest,\src,\val
++.endm
++.macro BigEorCs dest,src,val
++ BigCC eor,cs,\dest,\src,\val
++.endm
++.macro BigEorCc dest,src,val
++ BigCC eor,cc,\dest,\src,\val
++.endm
++
++.macro BigBic dest,src,val
++ BigCC bic,al,\dest,\src,\val
++.endm
++.macro BigBicEq dest,src,val
++ BigCC bic,eq,\dest,\src,\val
++.endm
++.macro BigBicNe dest,src,val
++ BigCC bic,ne,\dest,\src,\val
++.endm
++
++.macro BigAnd dest,src,val
++ BigAndCC al,\dest,\src,\val
++.endm
++.macro BigAndEq dest,src,val
++ BigAndCC eq,\dest,\src,\val
++.endm
++.macro BigAndNe dest,src,val
++ BigAndCC ne,\dest,\src,\val
++.endm
++
++// *******************************************************************************************
++ .list
+diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/burn.inc u-boot-1.1.2-neon/include/asm-arm/arch-pxa/burn.inc
+--- u-boot-1.1.2/include/asm-arm/arch-pxa/burn.inc 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/burn.inc 2007-08-11 21:07:21.000000000 +0200
+@@ -0,0 +1,367 @@
++#define FLASH_GPIO_STATUS 0 //1 means use gp to tell when flash is ready
++
++#if (PLATFORM_TYPE==NEONB)
++#define FLASH_BASE_ADDRESS 0x04000000
++#else
++#define FLASH_BASE_ADDRESS 0x0
++#endif
++
++
++#define FLASH_ID_CMD ((0x0090<<16) + 0x0090) //read Identifier Codes
++#define FLASH_STATUS_CMD ((0x0070<<16) + 0x0070)
++#define FLASH_STATUS_CLEAR_CMD ((0x0050<<16) + 0x0050)
++#define FLASH_READ_CMD ((0x00FF<<16) + 0x00FF) //Read Array/Reset
++#define FLASH_ERASE_CMD ((0x0020<<16) + 0x0020) //Block Erase
++#define FLASH_CONFIRM_CMD ((0x00D0<<16) + 0x00D0) //Block Erase and Program Resume
++//#define FLASH_WRITE_CMD ((0x0040<<16) + 0x0040) //Program word
++#define FLASH_WRITE_TO_BUFFER_CMD ((0x00E8<<16) + 0x00E8) //Program word
++
++#define FLASH_SUCCESS_RSP ((0x0080<<16) + 0x0080)
++
++#define stmicro_manCode ((0x0020<<16) + 0x0020)
++#define intel_manCode ((0x0089<<16) + 0x0089)
++#define SECT_SIZE (1<<18) //256k
++
++#define f320j3a_devCode ((0x0016<<16) + 0x0016)
++#define f320j3a_NUM_SECTORS 32 //for 8M flash
++#define f320j3a_SIZE (f320j3a_NUM_SECTORS*SECT_SIZE)
++
++#define f640j3a_devCode ((0x0017<<16) + 0x0017)
++#define f640j3a_NUM_SECTORS 64 //for 16M flash (8 meg on 16bit boards)
++#define f640j3a_SIZE (f640j3a_NUM_SECTORS*SECT_SIZE)
++
++#define f128j3a_devCode ((0x0018<<16) + 0x0018)
++#define f128j3a_NUM_SECTORS 128 //for 32M flash
++#define f128j3a_SIZE (f128j3a_NUM_SECTORS*SECT_SIZE)
++// *****************************
++#define MANCODE 0
++#define DEVCODE 4
++
++
++
++#define rRet r6
++#define rRamSectorEnd r7
++#define rRamSector rNum1
++#define rRamEnd rNum2
++#define rFlashBase sl //r10
++#define rFlashSector fp //r11
++
++#define CMD_BURN 0
++#define CMD_VERIFY 1
++#define CMD_BURNALL 2
++
++.macro delayCnt rTemp,cnt
++ mov \rTemp,#\cnt
++90: subs \rTemp,\rTemp,#1
++ bne 90b
++.endm
++// *********************************
++//default delay is for write recovery before read, allow 400 MHZ cpu
++.macro delay
++ delayCnt r4,((40/10)*COUNT_MULT)
++.endm
++
++
++
++.macro FLASH_GPIO_WAIT_FOR_IDLE
++ .if FLASH_GPIO_STATUS
++ bl FlashGpioWaitForIdle
++ .endif
++.endm
++
++.macro DEFINE_FLASH_GPIO_WAIT_FOR_IDLE
++ .if FLASH_GPIO_STATUS
++FlashGpioWaitForIdle:
++//500 ns delay for STS going low
++ delayCnt r4,((500/10)*COUNT_MULT) //500ns /10ns (for 100MHZ cpu cycle time) * 4 (100MHZ cpu)
++ mov r5,#0x300000
++ BigMov r4,GPIO_BASE
++91: ldr r2,[r4,#GPLR0]
++ and r2,r2,#3
++ cmp r2,#3
++ subnes r5,r5,#1
++ bne 91b
++ mov pc,lr //return
++ .endif
++.endm
++
++//out: z-1 timeout
++.macro waitForReady istr,ildr,mask,inc
++ BigMov r2,FLASH_STATUS_CMD&\mask
++ \istr r2,[r1,#-\inc]
++
++ FLASH_GPIO_WAIT_FOR_IDLE
++ BigMov r3,FLASH_SUCCESS_RSP&\mask
++
++ mov r5,#0x300000*COUNT_MULT
++ .if FLASH_GPIO_STATUS
++ b 92f
++ .endif
++
++71:
++ delayCnt r4,((500/10)*COUNT_MULT)
++92: \ildr r4,[r1,#-\inc] //!!! read status
++ and r4,r4,r3
++ cmp r4,r3
++ subnes r5,r5,#1
++ bne 71b
++
++ BigMov r2,FLASH_READ_CMD&\mask
++ \istr r2,[r1,#-\inc]
++ delay
++ teq r5,#0
++.endm
++
++
++
++//out: z-1 timeout
++.macro WaitForEraseDone istr,ildr,mask
++ FLASH_GPIO_WAIT_FOR_IDLE
++ BigMov r3,FLASH_SUCCESS_RSP&\mask
++ mov r5,#0x10000
++92:
++ delayCnt r4,0x3000
++ \ildr r4,[rFlashSector]
++ and r4,r4,r3
++ cmp r4,r3
++ subnes r5,r5,#1
++ bne 92b
++
++ BigMov r2,FLASH_READ_CMD&\mask
++ \istr r2,[rFlashSector,#0]
++ delay
++ teq r5,#0
++.endm
++// ***********************************
++
++//r5 - command - CMD_BURN or CMD_BURNALL
++//rRet(r6) succesful burn return address
++//rRamSectorEnd(r7) - but not an input, just how it is used
++//rRamSector(r8) - start
++//rRamEnd(r9) - end
++//rFlashBase(sl,r10) - flash base
++//rFlashSector(fp,r11) - starting flash sector
++//rDBG(sp,r13)
++//lr - return address on failure
++
++.macro BurnRtn istr,ildr,mask,shift,sizeShift,inc,plait
++ str r5,[rDBG,#DBG_TEMP]
++ BigMov r0,FLASH_STATUS_CLEAR_CMD&\mask
++ \istr r0,[rFlashBase,#0]
++ delay
++ BigMov r0,FLASH_ID_CMD&\mask
++ \istr r0,[rFlashBase,#0]
++ delay
++ BigMov r4,intel_manCode&\mask
++ BigMov r1,stmicro_manCode&\mask
++ BigMov r5,f320j3a_devCode&\mask
++ \ildr r2,[rFlashBase,#MANCODE>>\shift]
++ \ildr r3,[rFlashBase,#DEVCODE>>\shift]
++
++ BigMov r0,FLASH_READ_CMD&\mask
++ \istr r0,[rFlashBase,#0]
++ delayCnt r0,((40/10)*COUNT_MULT)
++
++ mov r0,#f320j3a_SIZE>>\sizeShift
++ cmp r3,r5
++
++ BigMovNe r5,f128j3a_devCode&\mask
++ movne r0,#f128j3a_SIZE>>\sizeShift
++ cmpne r3,r5
++
++ BigMovNe r5,f640j3a_devCode&\mask
++ movne r0,#f640j3a_SIZE>>\sizeShift
++ cmpne r3,r5
++
++ cmpeq r2,r4
++ cmpne r2,r1
++ movne r0,#MANCODE>>2
++ movne r1,#DEVCODE>>2
++ movne pc,lr //return if unrecognized chip
++
++ sub r1,rRamEnd,rRamSector
++ sub r2,rFlashSector,rFlashBase
++ add r1,r1,r2
++ cmp r1,r0
++ movhi pc,lr //return if trying to write too much
++
++ ldrb r5,[rDBG,#DBG_TEMP]
++ cmp r5,#CMD_BURNALL
++ streq r0,[rDBG,#DBG_TEMP] //r0 is size of flash
++
++ FLASH_GPIO_WAIT_FOR_IDLE
++1:
++ bl PrintSector
++
++//Now see if block needs erased
++ add rRamSectorEnd,rRamSector,#SECT_SIZE>>\shift
++ cmp rRamSectorEnd,rRamEnd
++ movhi rRamSectorEnd,rRamEnd
++ b 3f
++2:
++ ldr r2,[r0],#4 //read ram
++ ldr r3,[r1],#4 //read flash
++ and r4,r3,r2
++ cmp r4,r2
++ bne 10f
++3: cmp r0,rRamSectorEnd
++ blo 2b
++
++
++ ldr r2,[rDBG,#DBG_TEMP]
++ movs r2,r2
++ beq 20f
++ add r0,rFlashSector,#SECT_SIZE>>\shift
++ b 62f
++61:
++ ldr r2,[r1],#4 //read flash
++ adds r2,r2,#1
++ bne 10f
++62: cmp r1,r0
++ blo 61b
++ b 19f //erase not needed
++
++//erase
++10:
++ BigMov r3,FLASH_READ_CMD&\mask
++ \istr r3,[rFlashBase,#0]
++ delay
++ ldr r3,[r1,#-4] //read flash
++ and r4,r3,r2
++ cmp r4,r2
++ beq 3b //br if (we signal) glitch caused a spurious status register read
++
++ BigMov r0,FLASH_ERASE_CMD&\mask
++ \istr r0,[rFlashSector]
++ BigMov r0,FLASH_CONFIRM_CMD&\mask
++ \istr r0,[rFlashSector]
++ bl PrintErasing
++
++ WaitForEraseDone \istr,\ildr,\mask
++ beq Timeout //br if erase timed out
++
++ .if (\plait)
++ BigMov r0,FLASH_ERASE_CMD&\mask
++ \istr r0,[rFlashSector,#2]
++ BigMov r0,FLASH_CONFIRM_CMD&\mask
++ \istr r0,[rFlashSector,#2]
++ bl PrintErasing
++
++ WaitForEraseDone \istr,\ildr,\mask
++ beq Timeout //br if erase timed out
++ .endif
++
++19: cmp rRamSector,rRamSectorEnd
++ bhs 42f
++
++//programming
++20:
++ bl PrintProgramming
++21:
++ ldr r2,[r0],#4 //read ram
++ ldr r3,[r1],#4 //read flash
++ cmp r2,r3
++ bne 22f
++28:
++ cmp r0,rRamSectorEnd
++ blo 21b
++ b 30f //goto verify
++
++22:
++ sub r1,r1,#4
++ sub r0,r0,#4
++ and r2,r1,#0x3f>>\shift //align to a 64 byte boundary (32 per device)
++ sub r1,r1,r2
++ sub r0,r0,r2
++
++ BigMov r2,FLASH_WRITE_TO_BUFFER_CMD&\mask
++ \istr r2,[r1] //!!! write_to_buffer
++
++ sub r3,rRamSectorEnd,r0
++ mov r3,r3,LSR #2-\shift
++ sub r3,r3,#1
++ cmp r3,#0x0f
++ movhi r3,#0x0f
++ orr r2,r3,r3,LSL #16
++ \istr r2,[r1] //!!! word cnt -1
++25: \ildr r2,[r0],#\inc
++ \istr r2,[r1],#\inc //!!! words
++ subs r3,r3,#1
++ bpl 25b
++ BigMov r2,FLASH_CONFIRM_CMD&\mask
++ \istr r2,[r1,#-\inc] //!!! confirm
++
++ waitForReady \istr,\ildr,\mask,\inc
++
++ .if (\plait)
++ beq 88f
++ sub r1,r1,#\inc
++ sub r0,r0,#\inc
++ and r2,r1,#0x3f>>\shift //align to a 64 byte boundary (32 per device)
++ sub r1,r1,r2
++ sub r0,r0,r2
++
++ BigMov r2,FLASH_WRITE_TO_BUFFER_CMD&\mask
++ \istr r2,[r1,#2]! //!!! write_to_buffer
++ sub r3,rRamSectorEnd,r0
++ add r0,r0,#2
++ mov r3,r3,LSR #2-\shift
++ sub r3,r3,#1
++ cmp r3,#0x0f
++ movhi r3,#0x0f
++ orr r2,r3,r3,LSL #16
++ \istr r2,[r1] //!!! word cnt -1
++85: \ildr r2,[r0],#\inc
++ \istr r2,[r1],#\inc //!!! words
++ subs r3,r3,#1
++ bpl 85b
++ BigMov r2,FLASH_CONFIRM_CMD&\mask
++ \istr r2,[r1,#-\inc] //!!! confirm
++
++ waitForReady \istr,\ildr,\mask,\inc
++ sub r0,r0,#2
++ sub r1,r1,#2
++
++ bne 28b
++88:
++
++ .else
++ bne 28b
++ .endif
++ sub rRamSector,r0,#0x40>>\shift //whoops, timeout
++ sub rFlashSector,r1,#0x40>>\shift
++ b Timeout
++
++
++
++//verify
++30:
++ bl PrintVerifying
++31:
++ ldr r2,[r0],#4 //read ram
++ ldr r3,[r1],#4 //read flash
++ cmp r2,r3
++ bne 33f
++32: cmp r0,rRamSectorEnd
++ blo 31b
++42:
++ add rRamSector,rRamSector,#SECT_SIZE>>\shift
++ add rFlashSector,rFlashSector,#SECT_SIZE>>\shift
++ cmp rRamSector,rRamEnd
++ blo 1b //goto next sector
++
++ ldr r2,[rDBG,#DBG_TEMP]
++ add r2,r2,rFlashBase
++ cmp rFlashSector,r2
++ blo 1b
++
++ b PrintSuccess
++33:
++ BigMov r3,FLASH_READ_CMD&\mask
++ \istr r3,[rFlashBase,#0]
++ delay
++ ldr r3,[r1,#-4] //read flash
++ cmp r2,r3
++ beq 32b //br if (we signal) glitch caused a spurious status register read
++ b ReturnError
++.endm
+diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/miniMac.inc u-boot-1.1.2-neon/include/asm-arm/arch-pxa/miniMac.inc
+--- u-boot-1.1.2/include/asm-arm/arch-pxa/miniMac.inc 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/miniMac.inc 2007-08-11 21:07:21.000000000 +0200
+@@ -0,0 +1,476 @@
++#include "platformTypes.h"
++#define SUB_LR_FALL_THRU_FOR_FIQ 1 //0 for branch
++#define LITTLE_ENDIAN 1 //describes memory system
++#define DDEBUG 0
++#define DO_GPTEST 0
++
++#define MACH_TYPE_SCANPASS 332
++
++#define ATAG_CORE 0x54410001
++#define ATAG_MEM 0x54410002
++#define TAGGED_LIST 0xa0000100
++ .ifdef __ARMASM
++ GBLA STACKS_VALID
++ GBLA CONFIG_STACKS_VALID
++ .set CONFIG_STACKS_VALID,1
++ .endif
++
++#if (SOFTWARE_TYPE==WINCE)
++ .set STACKS_VALID,1
++ .ifdef __ARMASM
++ .else
++#ifndef CONFIG_STACKS_VALID
++#define CONFIG_STACKS_VALID 1
++#endif
++ .endif
++
++#define SDRAM_BASE_C_VIRTUAL 0xA0000000 //0x80000000 is cached mapped, 0xa0000000 is uncacheable
++#define UART_VIRT_BASE 0xAA100000
++#define VMA_DEBUG (0xfff00000)
++#define VIRTUAL_CS0 0xa8000000
++#define VIRTUAL_CS1 0xa8000000
++
++#else
++#ifdef CONFIG_STACKS_VALID
++ .set STACKS_VALID,1
++#else
++ .set STACKS_VALID,0
++#endif
++#define SDRAM_BASE_C_VIRTUAL 0xC0000000
++#define UART_VIRT_BASE 0xf8100000
++//#define VMA_DEBUG 0xff000000
++//!!!!!for some reason the above base causes bizarre problems
++#define VMA_DEBUG (0xfff00000)
++#define VIRTUAL_CS0 0xff000000
++#define VIRTUAL_CS1 0xff100000
++#endif
++
++#define V_rWork r2
++#define V_rBranch r3
++#define I_rWork r2
++#define I_rBranch sp //r13
++
++#ifdef CONFIG_STACKS_VALID
++#define rWork V_rWork
++#define rBranch V_rBranch
++
++#else
++#define rWork I_rWork
++#define rBranch I_rBranch
++#endif
++
++
++#if 0
++#define RED_VAL 0x15
++#define GREEN_VAL 0x2a
++#define BLUE_VAL 0x0a
++#else
++#define RED_VAL 0x0
++#define GREEN_VAL 0x0
++#define BLUE_VAL 0x0
++#endif
++
++//#define BAUDRATE 9600
++//#define BAUDRATE 38400
++//#define BAUDRATE 57600
++//#define BAUDRATE 57600
++#define BAUDRATE 115200
++//#define BAUDRATE 230400
++
++#if (CPU_CLOCK==100)
++#define COUNT_MULT 1
++#else
++#if (CPU_CLOCK==200)
++#define COUNT_MULT 2
++#else
++#if (CPU_CLOCK==300)
++#define COUNT_MULT 3
++#else
++#define COUNT_MULT 4
++#endif
++#endif
++#endif
++
++#if 1 //(SOFTWARE_TYPE==WINCE)
++#define RECEIVE_LOOP_COUNT 0x10000*COUNT_MULT
++#else
++#if (PLATFORM_TYPE==GAME_CONTROLLER_PLAITED_A1)||(PLATFORM_TYPE==GAME_CONTROLLER)||(PLATFORM_TYPE==GAME_WITH_SMC)
++#define RECEIVE_LOOP_COUNT 0x100000*COUNT_MULT
++#else
++#define RECEIVE_LOOP_COUNT 0x300000*3*COUNT_MULT
++#endif
++#endif
++
++// **********************************************************
++#define DBG_MAGIC 95 //this allows BigMov sp,DEBUG_BASE+DBG_MAGIC to generate just 1 instruction
++//#define DBG_START -95
++#define DBG_START 0
++#define DBG_R0 ((0<<2)+DBG_START)
++#define DBG_R1 ((1<<2)+DBG_START)
++#define DBG_R2 ((2<<2)+DBG_START)
++#define DBG_R3 ((3<<2)+DBG_START)
++#define DBG_R4 ((4<<2)+DBG_START)
++#define DBG_R5 ((5<<2)+DBG_START)
++#define DBG_R6 ((6<<2)+DBG_START)
++#define DBG_R7 ((7<<2)+DBG_START)
++#define DBG_R8 ((8<<2)+DBG_START)
++#define DBG_R9 ((9<<2)+DBG_START)
++#define DBG_SL ((10<<2)+DBG_START)
++#define DBG_FP ((11<<2)+DBG_START)
++#define DBG_IP ((12<<2)+DBG_START)
++#define DBG_SP ((13<<2)+DBG_START)
++#define DBG_LR ((14<<2)+DBG_START)
++#define DBG_PC ((15<<2)+DBG_START)
++#define DBG_CPSR ((16<<2)+DBG_START) //this and above have corresponding symbol #s
++
++#define DBG_HCPSR ((17<<2)+DBG_START) //interrupt handler original CPSR
++#define DBG_TRACE ((18<<2)+DBG_START)
++#define DBG_LastSignal ((19<<2)+DBG_START) //only 1 byte
++#define DBG_Mode (((19<<2)+1)+DBG_START) //only 1 byte, bit 0 -1 means gdb mode for control breaks
++#define DBG_FFUART_LCR (((19<<2)+2)+DBG_START) //only 1 byte
++#define DBG_HSP ((20<<2)+DBG_START) //handler stack pointer on entry, for aborts
++#define DBG_TEMP ((21<<2)+DBG_START)
++//22 free
++#define DBG_ABORT_PC ((23<<2)+DBG_START)
++#define DBG_INDIRECT_R0 ((24<<2)+DBG_START) //it needs it's own space in case a debug interrupt
++#define DBG_INDIRECT_LR ((25<<2)+DBG_START) //happens in the return code, but memory is mapped if used
++#define DEBUG_SPACE (((23<<2)|0x1f)+1) //a multiple of 32 bytes
++
++// *********************************************************
++
++#define DEBUG_START (VMA_DEBUG+0x3000-DEBUG_SPACE) //this saves on memory, but the else is easier to debug
++#define VMA_DEBUG_OFFSET (0xffff0000-VMA_DEBUG)
++#define DEBUG_BASE (DEBUG_START-DBG_START)
++#define DEBUG_SYM DEBUG_START
++
++
++#define SYM_R0 0
++#define SYM_R1 1
++#define SYM_R2 2
++#define SYM_R3 3
++#define SYM_R4 4
++#define SYM_R5 5
++#define SYM_R6 6
++#define SYM_R7 7
++#define SYM_R8 8
++#define SYM_R9 9
++#define SYM_SL 10
++#define SYM_FP 11
++#define SYM_IP 12
++#define SYM_SP 13
++#define SYM_LR 14
++#define SYM_PC 15
++#define SYM_CPSR 16
++
++//#define SYM_SPSR 17 //nice to have, but do it later
++//#define SYM_FPS 17
++#define SYM_FP0 17 //40 bits, 5
++#define SYM_FSR 18
++#define SYM_FAR 19
++#define SYM_DCSR 20
++#define SYM_TTBR 21
++#define SYM_CTRL 22
++
++#define SYM_LAST 22
++
++#define SYM_LAST_RCMD (SYM_FP0) //last symbol printed by R cmd
++
++
++
++#define SIG_RESET 0
++#define SIG_UNDEFINED_INSTRUCTION 1
++#define SIG_SWI 2
++#define SIG_PREFETCH_ABORT 3
++#define SIG_DATA_ABORT 4
++#define SIG_UNUSED 5
++#define SIG_IRQ 6
++#define SIG_FIQ 7
++#define SIG_DBG 8
++#define SIG_DBG_RESET 8+0
++#define SIG_DBG_INSTRUCTION_BKPT 8+1
++#define SIG_DBG_DATA_BKPT 8+2
++#define SIG_DBG_BKPT_SOFTWARE 8+3
++#define SIG_DBG_EXTERNAL 8+4
++#define SIG_DBG_VECTOR_TRAP 8+5
++#define SIG_DBG_TRACE_BUFFER_FULL 8+6
++#define SIG_DBG_RESERVED 8+7
++
++#define GDB_EXIT_CHAR 0x0d
++// ******************************************************************
++#define rFieldStart r4
++#define rField r5
++#define rValidCnt r6
++#define rCommand r7
++#define rNum1 r8
++#define rNum2 r9
++#define rSymbol sl //r10
++#define rPrevNum1 fp //r11
++#define rUart ip //r12
++#define rDBG sp
++
++//in Go routine, temporary
++#define rBCR0 sl //r10
++#define rBCR1 fp //r11
++
++//in GDB routines
++#define rGdbCmd r5
++#define rGdbNum1 r6
++#define rGdbTermChar1 r7
++#define rGdbNum2 r8
++#define rGdbTermChar2 r9
++#define rGdbNum3 sl //r10
++#define rGdbChkSum fp //r11
++
++//in Download routine
++#define rDest r3
++#define rPacketLength r4
++#define rDestHead r5
++#define rBlockNum r6
++#define rNak r7
++#define rCRC r8
++#define rRunningCRC r9
++#define rPrevCRC sl //r10
++
++#define rSP r8 //register which contains L4(' ',' ',' ',' '), all spaces
++// ********
++
++#define CR 0x0d
++#define LF 0x0a
++
++// ******************************
++#define F_INC 4
++
++#define F_NUM1_BIT (F_INC*3)
++#define F_NUM2_BIT (F_INC*5)
++
++#define F_COMMAND 1<<(F_INC)
++#define F_NUM1 1<<(F_NUM1_BIT)
++#define F_NUM2 1<<(F_NUM2_BIT)
++#define F_UNDEF 1<<(F_INC*7)
++
++#define F_COMMAND_MASK ((1<<F_INC)-1)<<(F_INC)
++#define F_NUM1_MASK ((1<<F_INC)-1)<<(F_INC*3)
++#define F_NUM2_MASK ((1<<F_INC)-1)<<(F_INC*5)
++// ******************************
++#define cachelinecount 2048 //1024 if baseaddress not used for another purpose
++#define cachelinesize 32
++//#define baseaddress 0 //physical memory does not have to exist here, but a valid descriptor table entry IS required
++
++// *****************************
++#define SOH 1
++#define STX 2
++#define EOT 4
++#define ACK 6
++#define NAK 0x15
++#define CAN 0x18
++
++#define CRC_POLY 0x10210000
++// *****************************
++
++// divide 0x1000 bytes among the stacks
++#define SS_SUPERVISOR 0x0800
++#define SS_IRQ 0x0400
++#define SS_FIQ 0x0100
++#define SS_SYSTEM 0x0100
++#define SS_UNDEFINED 0x0100
++#define SS_ABORT 0x0100
++#define SS_TOTAL (SS_SUPERVISOR+SS_IRQ+SS_FIQ+SS_SYSTEM+SS_UNDEFINED+SS_ABORT)
++#define SS_START 0x0a0008000-0x4400-SS_TOTAL //-17k, 16k for 1st level page table, 1k for 2nd level page table
++// *****************************
++
++
++
++
++// *********************************
++.macro mac_AfterPCPrint branch //vector table at 0xffff0000, br to vector table at VMA_DEBUG
++ .ifdef __ARMASM
++ LCLA cnt
++ .set cnt,$branch
++ WHILE cnt>0
++ b 93f
++ .set cnt,cnt-1
++ WEND
++ .else
++ .rept (\branch)
++ b 93f
++ .endr
++ .endif
++
++AfterPCPrint:
++ mov r0,#0x55
++ b AfterPCPrint1
++InitializeCont:
++ b MainInitializationCode
++93:
++.endm
++
++
++.macro RelocationVector branch //vector table at 0xffff0000, br to vector table at VMA_DEBUG
++ //warning, do not use relocated vectors unless memory management is enabled and VMA_DEBUG is mapped
++ .ifdef __ARMASM
++ LCLA cnt
++ .set cnt,$branch
++ WHILE cnt>0
++ b 71f
++ .set cnt,cnt-1
++ WEND
++ .else
++ .rept (\branch)
++ b 71f
++ .endr
++ .endif
++
++ mov pc,#0x00 //0 - reset always goes to 0 because it will be in physical memory mode for instructions
++ b .-VMA_DEBUG_OFFSET //4 - UndefinedInstr
++ b .-VMA_DEBUG_OFFSET //8 - SWI
++ b .-VMA_DEBUG_OFFSET //0x0c - PrefetchAbort
++ b .-VMA_DEBUG_OFFSET //0x10 - DataAbort
++ b .-VMA_DEBUG_OFFSET //0x14 - Unused
++ b .-VMA_DEBUG_OFFSET //0x18 - IRQ
++ .if SUB_LR_FALL_THRU_FOR_FIQ
++ sub lr,lr,#4 //0x1c - FIQ
++ .else
++ b .-VMA_DEBUG_OFFSET //0x1c - FIQ
++ .endif
++
++//these instructions are always at this address
++//to minimize the effect of a mismatch of minicache and flash
++ReturnWithIndirection:
++ mov r0,r0 //!!!! make sure this instruction is in the 1st 4k of flash so that BigOrr2Ne is guaranteed to work
++ ldr pc,[sp],#4
++
++//c-0 invalidate caches, c-1 skip cache invalidate
++//z-1 return direct, z-0 return indirect
++InvalidateAndReturn:
++ adrne lr,ReturnWithIndirection
++ ldreq lr,[r0,#DBG_PC-DBG_R2]
++ BigOrr2Ne lr,VMA_DEBUG //this range is sure to give an external abort for errata on exiting SDS
++
++//Invalidate the data/instruction cache and branch target buffer
++
++ CP15_CF_INVAL_BOTH mcrcc,r1
++ CPWAIT r1
++
++ ldr sp,[r0,#DBG_HSP-DBG_R2]
++ ldr r1,[r0,#DBG_R1-DBG_R2]
++ str r0,[r0,#DBG_ABORT_PC-DBG_R2] //reset error flag so abort can be retried
++ ldr r0,[r0,#DBG_R0-DBG_R2]
++ movs pc,lr
++71:
++.endm
++
++.macro CheckBranch rTemp,rAddr
++ movs \rTemp,pc //don't redirect if running from flash
++ submi \rAddr, \rAddr, #0x00010000
++ ldrmi \rTemp, [\rAddr], #8
++ eormi \rTemp, \rTemp, #0xea000000
++ tstmi \rTemp, #0xff000000
++ moveq \rTemp, \rTemp, LSL #8
++ addeq \rAddr, \rAddr, \rTemp, ASR #6
++.endm
++.macro CheckLdr rTemp,rAddr //check for instruction LDR pc,[pc,#nnn]
++ eor \rTemp, \rTemp, #0x0f900000
++ eor \rTemp, \rTemp, #0x000ff000
++ cmp \rTemp, #0x1000
++ ldrcc \rAddr,[\rAddr,\rTemp]
++.endm
++
++//this is case where stacks are assumed valid
++.macro V_VectorEntrance Work,Branch,code
++ stmdb sp!,{\Work,\Branch,lr}
++ mov \Branch,#\code<<2
++.endm
++.macro V_VectorExitCC Work,Branch,cc,ccia
++ str\cc \Branch,[sp,#8]
++ ldm\ccia sp!,{\Work,\Branch,pc}
++.endm
++.macro V_VectorExitCC1 Work,Branch,cc,ccia
++ str\cc \Branch,[sp,#8]
++ ldm\ccia sp!,{\Work,\Branch,pc}
++.endm
++
++//this is case where stacks are assumed invalid
++.macro I_VectorEntrance Work,Branch,code
++ BigMov \Branch,DEBUG_BASE+DBG_MAGIC
++ str \Work,[\Branch,#DBG_TEMP-DBG_MAGIC]
++ mov \Branch, #\code<<2
++.endm
++.macro I_VectorExitCC Work,Branch,cc,ccia
++ BigMovCC \cc,\Work,DEBUG_BASE+DBG_MAGIC
++ ldr\cc \Work,[\Work,#DBG_TEMP-DBG_MAGIC]
++ bx\cc \Branch
++.endm
++.macro I_VectorExitCC1 Work,Branch,cc,ccia
++ BigMov \Work,DEBUG_BASE+DBG_MAGIC
++ ldr\cc \Work,[\Work,#DBG_TEMP-DBG_MAGIC]
++ bx\cc \Branch
++.endm
++.macro VectorEntrance Work,Branch,code
++ .if STACKS_VALID
++ V_VectorEntrance \Work,\Branch,\code
++ .else
++ I_VectorEntrance \Work,\Branch,\code
++ .endif
++.endm
++.macro JOIN brcc
++ .if STACKS_VALID
++ \brcc join_fiq
++ .else
++ \brcc join_irq
++ .endif
++.endm
++.macro JOIN2 brcc
++ .if STACKS_VALID
++ \brcc join_fiq2
++ .else
++ \brcc join_irq2
++ .endif
++.endm
++// *****************************************************
++
++.macro SaveRegisters rBase,rTemp
++ CalcMemSize \rBase,\rTemp,MEMORY_CONTROL_BASE //out: \rTemp - mem size
++ BigAdd \rBase,\rTemp,MEM_START-0x1000+((DEBUG_BASE+DBG_MAGIC)&0xfff) //last 4k of memory
++ mov \rTemp,#0
++//great, now memory should be working, let's save registers, only r0(rBase),sp(rTemp) have been lost
++//don't trust LDM,STM instructions in debug mode....
++//or LDR w/Rd=PC, LDR w/RRX addressing mode, SWP, LDC, STC
++// *******************************************************
++// *******************************************************
++ str \rTemp,[\rBase,#DBG_START-32 -DBG_MAGIC]
++ str \rTemp,[\rBase,#DBG_R0 -DBG_MAGIC]
++ str r1, [\rBase,#DBG_R1 -DBG_MAGIC]
++ str r2, [\rBase,#DBG_R2 -DBG_MAGIC]
++ str r3, [\rBase,#DBG_R3 -DBG_MAGIC]
++ str \rTemp,[\rBase,#DBG_TRACE -DBG_MAGIC]
++ str \rTemp,[\rBase,#DBG_LastSignal-DBG_MAGIC]
++.endm
++.macro ReadHexE dest,rCnt1
++
++#if LITTLE_ENDIAN
++ mov \rCnt1,#4
++ mov \dest,#0
++1: bl ReadHex
++ bcc CheckSumError
++ add rGdbChkSum,rGdbChkSum,r0 //update checksum
++ mov r1,r1,LSL #28
++ add \dest,r1,\dest,LSR #8
++
++ bl ReadHex
++ bcc CheckSumError
++ add rGdbChkSum,rGdbChkSum,r0 //update checksum
++ add \dest,\dest,r1,LSL #24
++#else
++ mov \rCnt1,#8
++ mov \dest,#0
++1: bl ReadHex
++ bcc CheckSumError
++ add rGdbChkSum,rGdbChkSum,r0 //update checksum
++ add \dest,r1,\dest,LSL #4
++#endif
++ subs \rCnt1,\rCnt1,#1
++ bne 1b
++.endm
++
++
++
+diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/mmc.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/mmc.h
+--- u-boot-1.1.2/include/asm-arm/arch-pxa/mmc.h 2003-06-27 23:32:42.000000000 +0200
++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/mmc.h 2007-08-11 21:07:21.000000000 +0200
+@@ -4,7 +4,7 @@
+ * Author: Vladimir Shebordaev, Igor Oblakov
+ * Copyright: MontaVista Software Inc.
+ *
+- * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $
++ * $Id: mmc.h,v 1.3 2005/04/16 17:05:19 ericn Exp $
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -113,12 +113,17 @@
+ #define MMC_CMD_SET_RCA 3
+ #define MMC_CMD_SEND_CSD 9
+ #define MMC_CMD_SEND_CID 10
++#define MMC_CMD_STOP 12
+ #define MMC_CMD_SEND_STATUS 13
+ #define MMC_CMD_SET_BLOCKLEN 16
+ #define MMC_CMD_READ_BLOCK 17
+ #define MMC_CMD_RD_BLK_MULTI 18
+ #define MMC_CMD_WRITE_BLOCK 24
+
++#define SD_APP_CMD55 55 /* 0x37 */
++#define SD_APP_CMD41 41 /* 0x29 */
++#define SD_STATUS 13 /* 0x0D */
++
+ #define MMC_MAX_BLOCK_SIZE 512
+
+ #define MMC_R1_IDLE_STATE 0x01
+@@ -197,4 +202,15 @@
+ } mmc_csd_t;
+
+
++typedef struct sd_status {
++ ulong prot_size ;
++ ushort card_type ;
++ ushort bus_width:2,
++ secured_mode:1,
++ unused0: 13 ;
++} sd_status_t ;
++
++extern uchar *
++mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat);
++
+ #endif /* __MMC_PXA_P_H__ */
+diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/platformTypes.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/platformTypes.h
+--- u-boot-1.1.2/include/asm-arm/arch-pxa/platformTypes.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/platformTypes.h 2007-08-11 21:07:21.000000000 +0200
+@@ -0,0 +1,19 @@
++#ifndef __PLATFORMTYPES_H__
++#define __PLATFORMTYPES_H__ 1
++#define NEON 1
++#define NEONB 2
++#define BD2003 3
++#define GAME_WITH_SMC 4
++#define GAME_CONTROLLER 5
++#define GAME_CONTROLLER_PLAITED_A1 6
++#define BOUNDARY_OLD_BOARD 7 //lcd pin reordering for rgb problem, don't use VLIO(gp18 is turnstile)
++#define OLD_GAME_CONTROLLER 8
++#define HALOGEN 9
++
++#if (PLATFORM_TYPE==NEONB)
++#define PHYS_FLASH_BASE 0x04000000
++#else
++#define PHYS_FLASH_BASE 0x0
++#endif
++
++#endif
+diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxa250Base.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxa250Base.h
+--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxa250Base.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxa250Base.h 2007-08-11 21:07:21.000000000 +0200
+@@ -0,0 +1,60 @@
++#ifndef __PXA250BASE_H__
++#define __PXA250BASE_H__ 1
++
++#ifdef __ARMASM
++#define USE_PHYSICAL 1
++#else
++#ifndef _MSC_VER
++#define USE_PHYSICAL 1
++#endif
++#endif
++
++
++#ifndef USE_PHYSICAL
++#if EBOOT_PHYS
++#define USE_PHYSICAL 1
++#endif
++#endif
++
++#if USE_PHYSICAL
++#define PCMCIA_CARD0_IO 0x20000000
++#define PCMCIA_CARD0_ATTR 0x28000000
++#define PCMCIA_CARD0_MEM 0x2c000000
++
++#define PCMCIA_CARD1_IO 0x30000000
++#define PCMCIA_CARD1_ATTR 0x38000000
++#define PCMCIA_CARD1_MEM 0x3c000000
++
++#define FFUART_BASE 0x40100000
++#define BTUART_BASE 0x40200000
++#define STUART_BASE 0x40700000
++#define UART_BASE FFUART_BASE
++//#define UART_BASE BTUART_BASE
++
++#define OS_TIMER_BASE 0x40a00000
++#define IC_BASE 0x40D00000
++#define GPIO_BASE 0x40E00000
++#define PWR_MANAGER_BASE 0x40F00000
++#define CLK_MANAGER_BASE 0x41300000
++#define LCD_CONTROL_BASE 0x44000000
++#define MEMORY_CONTROL_BASE 0x48000000
++
++#define MEM_START 0xa0000000
++
++
++#else
++#include "xsc1.h"
++
++#define PCMCIA_CARD0_IO PCMCIA_S0_IO_U_VIRTUAL
++#define PCMCIA_CARD0_ATTR PCMCIA_S0_ATTR_U_VIRTUAL
++#define PCMCIA_CARD0_MEM PCMCIA_S0_CMN_U_VIRTUAL
++
++#define PCMCIA_CARD1_IO PCMCIA_S1_IO_U_VIRTUAL
++#define PCMCIA_CARD1_ATTR PCMCIA_S1_ATTR_U_VIRTUAL
++#define PCMCIA_CARD1_MEM PCMCIA_S0_CMN_U_VIRTUAL
++
++#define MEMORY_CONTROL_BASE MEMC_BASE_U_VIRTUAL
++#define GPIO_BASE GPIO_BASE_U_VIRTUAL
++#endif
++
++#endif
+diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxaGpio25x.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaGpio25x.h
+--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxaGpio25x.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaGpio25x.h 2007-08-11 21:07:21.000000000 +0200
+@@ -0,0 +1,218 @@
++//gpios for PLATFORM_TYPE== NEON,NEONB,BD2003, or BOUNDARY_OLD_BOARD
++
++#define LCD_CS_STATE HIGH
++
++//CP - Clock and Power Management Unit
++//MMC - Multimedia Card Controller
++//MC - Memory Controller
++//SIU - System Integration Unit
++//SSP - Synchronous Serial Port
++//AC - Audio Controller (AC97)
++//FF - Full Function UART
++//BT - Blue Tooth UART
++//ST - standard UART Port
++//LCD - LCD Controller
++ SPEC_GP 0,IN,HIGH,0 // flash ready low 16, or magStripe T1 Clk(SMC)
++ SPEC_GP 1,IN,HIGH,0 //CP_RST, flash ready high 16, or magStripe T2 Clk(SMC)
++
++#if (PLATFORM_TYPE==NEONB)
++ SPEC_GP 2,IN,HIGH,0 //USB client connection status
++ SPEC_GP 3,IN,HIGH,0 //float means USB Slave not ready to accept data
++ //out 1 means ready (D+ signal)
++ SPEC_GP 4,OUT,LOW,0 //low means don't provide 12 volts to I2C bus
++#else
++#if (PLATFORM_TYPE==NEON)
++ SPEC_GP 2,IN,HIGH,0 //USB client connection status
++ SPEC_GP 3,IN,HIGH,0 //float means USB Slave not ready to accept data
++ SPEC_GP 4,IN,HIGH,0 //UCB1400 irq on NEON board
++#else
++ SPEC_GP 2,OUT,LOW,0 //output to transistor (unused), OUT_DRY_CONTACT2
++ SPEC_GP 3,OUT,HIGH,0
++ SPEC_GP 4,IN,HIGH,0 //interrupt for USB irq 1
++#endif
++#endif
++
++ SPEC_GP 5,IN,HIGH,0 //interrupt for USB irq 2, or SM501
++ SPEC_GP 6,OUT,HIGH,1 //MMC_CLK
++ SPEC_GP 7,OUT,LOW,0 //CP_48MHZ !!! red led, NEON:J13,pin3
++ SPEC_GP 8,OUT,HIGH,1 //MMC_CCS0
++ SPEC_GP 9,OUT,LOW,0 //MMC_CCS1, !!! doorlock, or OUT_DRY_CONTACT1
++ SPEC_GP 10,IN,HIGH,0 //SIU_RTCCLK, Neon/Neonb data 1 for SDIO interrupt
++
++#if (PLATFORM_TYPE==NEON)
++ SPEC_GP 11,OUT,HIGH,0 //CP_3600KHZ, NEON:J12,pin1
++#else
++ SPEC_GP 11,IN,HIGH,0 //CP_3600KHZ, suspend USB slave
++#endif
++ SPEC_GP 12,IN,HIGH,0 //CP_32KHZ, suspend USB host
++
++#if (PLATFORM_TYPE==NEON) || (PLATFORM_TYPE==NEONB)
++ SPEC_GP 13,OUT,HIGH,2 //MC_MBGNT
++ SPEC_GP 14,IN,HIGH,1 //MC_MBREQ
++#else
++ SPEC_GP 13,OUT,HIGH,0 //USB wakeup slave
++ SPEC_GP 14,IN,HIGH,0 //UCB1400 IRQ
++#endif
++
++
++#if (PLATFORM_TYPE==NEONB)
++ SPEC_GP 15,OUT,HIGH,2 //MC_nCS1, eeprom
++#else
++#if (PLATFORM_TYPE==NEON)
++ SPEC_GP 15,OUT,LOW,0 //MC_nCS1, NEON:J13, pin 1
++#else
++ SPEC_GP 15,OUT,LOW,0 //MC_nCS1, !!! amber led
++#endif
++#endif
++
++
++#if (PLATFORM_TYPE==NEON) || (PLATFORM_TYPE==NEONB)
++ SPEC_GP 16,OUT,HIGH,0 //LCD backlight brightness control
++ SPEC_GP 17,OUT,HIGH,0 //LCD backlight ON/OFF
++#else
++ SPEC_GP 16,IN,HIGH,0 //SIU_PWM0, !!! feedback2, left in
++ SPEC_GP 17,IN,HIGH,0 //SIU_PWM1, !!! feedback1, right in
++#endif
++
++#if (PLATFORM_TYPE==BOUNDARY_OLD_BOARD)
++ SPEC_GP 18,OUT,HIGH,0 //MC_RDY, !!! turnstile
++#else
++ SPEC_GP 18,IN,HIGH,1 //MC_RDY, VIO_READY
++#endif
++
++#if (PLATFORM_TYPE==NEON) || (PLATFORM_TYPE==NEONB)
++ SPEC_GP 19,OUT,HIGH,0 //MC_DREQ1, nc
++#else
++ SPEC_GP 19,IN,HIGH,1 //MC_DREQ1, DMA request for USB DC
++#endif
++
++#if (PLATFORM_TYPE==NEON) || (PLATFORM_TYPE==NEONB)
++ SPEC_GP 20,OUT,HIGH,1 //MC_DREQ0, nc
++#else
++ SPEC_GP 20,IN,HIGH,1 //MC_DREQ0, DMA request for USB HC
++#endif
++
++ SPEC_GP 21,IN,HIGH,0 // pcmcia card detect
++ SPEC_GP 22,IN,HIGH,0 // pcmcia intr (active low)
++
++#if (PLATFORM_TYPE==NEON) || (PLATFORM_TYPE==NEONB)
++ SPEC_GP 23,IN,LOW,0 //UCB1400 irq for NEONB, nc for NEW NEON
++#else
++ SPEC_GP 23,OUT,HIGH,0 //SSP_SCLK, nc
++#endif
++
++#if (PLATFORM_TYPE==NEON) || (PLATFORM_TYPE==NEONB)
++ SPEC_GP 24,IN,LOW,0 //SSP_SFRM, SMSC interrupt (active high)
++#else
++ SPEC_GP 24,OUT,HIGH,0 //SSP_SFRM, nc
++#endif
++
++ SPEC_GP 25,OUT,HIGH,0 //SSP_TXD, nc
++ SPEC_GP 26,OUT,HIGH,0 //SSP_RXD, nc
++ SPEC_GP 27,OUT,LOW,0 //SSP_EXTCLK, DC1 (SMC)
++
++ SPEC_GP 28,IN,HIGH,1 //AC_BITCLK, ac97 bitclk
++ SPEC_GP 29,IN,HIGH,1 //AC_SDATAIN0, ac97 datain0
++ SPEC_GP 30,OUT,HIGH,2 //AC_SDATAOUT, ac97 data out
++ SPEC_GP 31,OUT,HIGH,2 //AC_SYNC, ac97 sync
++////////////////////////////////////////////////////////////////////////////////////////////
++
++
++ SPEC_GP 32,OUT,HIGH,0 //AC_SDATAIN1, wet contact
++ SPEC_GP 33,OUT,LOW,0 //MC_nCS5, green led (left), NEON:J13,pin 2
++ SPEC_GP 34,IN,HIGH,1 //FF_RXD
++ SPEC_GP 35,IN,HIGH,1 //FF_CTS
++ SPEC_GP 36,IN,HIGH,0 //FF_DCD, MMC Card Detect
++ SPEC_GP 37,IN,HIGH,1 //FF_DSR
++ SPEC_GP 38,IN,HIGH,0 //FF_RI, MMC Write Protect, MMC/SDIO IRQ
++ SPEC_GP 39,OUT,HIGH,2 //FF_TXD
++ SPEC_GP 40,OUT,HIGH,2 //FF_DTR
++ SPEC_GP 41,OUT,HIGH,2 //FF_RTS
++ SPEC_GP 42,IN,HIGH,1 //BT_RXD
++ SPEC_GP 43,OUT,HIGH,2 //BT_TXD
++#if (PLATFORM_TYPE==NEON)
++ SPEC_GP 44,IN,HIGH,0 //BT_CTS, NEON:J12,pin 2
++#else
++ SPEC_GP 44,OUT,HIGH,0 //BT_CTS, USB wakeup host
++#endif
++ SPEC_GP 45,OUT,LOW,0 //BT_RTS, HIGH 2
++#if (PLATFORM_TYPE==NEON)
++ SPEC_GP 46,IN,HIGH,0 //ST_RXD, NEON:J12,pin 3
++#else
++ SPEC_GP 46,IN,HIGH,2 //ST_RXD
++#endif
++ SPEC_GP 47,OUT,HIGH,1 //ST_TXD
++ SPEC_GP 48,OUT,HIGH,2 //MC_nPOE, pcmcia
++ SPEC_GP 49,OUT,HIGH,2 //MC_nPWE, pcmcia
++ SPEC_GP 50,OUT,HIGH,2 //MC_nPIOR, pcmcia
++ SPEC_GP 51,OUT,HIGH,2 //MC_nPIOW, pcmcia
++ SPEC_GP 52,OUT,HIGH,2 //MC_nPCE1, pcmcia
++ SPEC_GP 53,OUT,HIGH,2 //MC_nPCE2, pcmcia
++ SPEC_GP 54,OUT,HIGH,2 //MC_nPSKTSEL, nc
++ SPEC_GP 55,OUT,HIGH,2 //MC_nPREG, pcmcia attribe vs Io space
++ SPEC_GP 56,IN,HIGH,1 //MC_nPWAIT pcmcia busy
++ SPEC_GP 57,IN,HIGH,1 //MC_nIOIS16, pcmcia 16 bit wide
++ SPEC_GP 58,OUT,HIGH,ALT_LCD //LCD_LDD0, also GP_PIX_D0
++ SPEC_GP 59,OUT,HIGH,ALT_LCD //LCD_LDD1, also GP_PIX_D1
++ SPEC_GP 60,OUT,HIGH,ALT_LCD //LCD_LDD2, also GP_PIX_D2
++ SPEC_GP 61,OUT,HIGH,ALT_LCD //LCD_LDD3, also GP_PIX_D3
++ SPEC_GP 62,OUT,HIGH,ALT_LCD //LCD_LDD4, also GP_PIX_D4
++ SPEC_GP 63,OUT,HIGH,ALT_LCD //LCD_LDD5, also GP_PIX_D5
++
++
++////////////////////////////////////////////////////////////////////////////////////////////
++
++
++ SPEC_GP 64,OUT,HIGH,ALT_LCD //LCD_LDD6, also GP_PIX_D6
++ SPEC_GP 65,OUT,HIGH,ALT_LCD //LCD_LDD7, also GP_PIX_D7
++ SPEC_GP 66,OUT,HIGH,ALT_LCD //LCD_LDD8, also GP_PIX_RESET
++ SPEC_GP 67,OUT,HIGH,ALT_LCD //LCD_LDD9
++ SPEC_GP 68,OUT,HIGH,ALT_LCD //LCD_LDD10
++ SPEC_GP 69,OUT,HIGH,ALT_LCD //LCD_LDD11
++ SPEC_GP 70,OUT,HIGH,ALT_LCD //LCD_LDD12
++
++ SPEC_GP 71,OUT,HIGH,ALT_LCD //LCD_LDD13
++
++ SPEC_GP 72,OUT,HIGH,ALT_LCD //LCD_LDD14
++ SPEC_GP 73,OUT,HIGH,ALT_LCD //LCD_LDD15
++ SPEC_GP 74,OUT,HIGH,ALT_LCD //LCD_FCLK, also GP_PIX_READ
++ SPEC_GP 75,OUT,LCD_CS_STATE,ALT_LCD //LCD_LCLK, also GP_PIX_CS1
++ SPEC_GP 76,OUT,LCD_CS_STATE,ALT_LCD //LCD_PCLK, also GP_PIX_CS0
++ SPEC_GP 77,OUT,HIGH,ALT_LCD //LCD_ACBIAS, also GP_PIX_A0
++ SPEC_GP 78,OUT,HIGH,2 //nCS2, DMA acknowledge channel 1 for USB, SMC91c111 Chip Select nDATACS
++ SPEC_GP 79,OUT,HIGH,2 //nCS3, DMA acknowledge channel 2 for USB, SM501 Chip Select
++ SPEC_GP 80,OUT,HIGH,2 //nCS4, USB chip select, SMC91c111 Chip Select
++ SPEC_GP 81,IN,LOW,0 //GND (pin F16), pxa255 has 9 extra gpios
++ SPEC_GP 82,IN,LOW,0 //GND (pin E16)
++ SPEC_GP 83,IN,LOW,0 //GND (pin E15)
++ SPEC_GP 84,IN,LOW,0 //GND (pin D16)
++ SPEC_GP 85,IN,LOW,0 //GND (pin F15)
++//to maintain compatibility with code written for the pxa250
++//the meaning of gp86-gp89's direction bit is reversed, and alternate function is forced to the SDRAM/AC97 unit's control
++ SPEC_GP 86,IN,HIGH,0 //SDCS2 (pin G3) set as OUTPUT!!!
++ SPEC_GP 87,IN,HIGH,0 //SDCS3 (pin F2) set as OUTPUT!!!
++ SPEC_GP 88,IN,HIGH,0 //old RDnWR(pin D3) set as OUTPUT!!!
++ SPEC_GP 89,IN,LOW,0 //old ac97_reset(pin D10), set as OUTPUT!!!
++ SPEC_GP 90,IN,LOW,0 //undefined
++ SPEC_GP 91,IN,LOW,0 //undefined
++ SPEC_GP 92,IN,LOW,0 //undefined
++ SPEC_GP 93,IN,LOW,0 //undefined
++ SPEC_GP 94,IN,LOW,0 //undefined
++ SPEC_GP 95,IN,LOW,0 //undefined
++
++// ****************************************************************************
++ CREATE_MASK_DIR DRVAL0, SPEC_, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
++ CREATE_MASK_LEVEL SRVAL0, SPEC_, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
++ CREATE_MASK_ALT AFVAL0, SPEC_, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
++ CREATE_MASK_ALT AFVAL16,SPEC_,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
++
++ CREATE_MASK_DIR DRVAL32,SPEC_,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63
++ CREATE_MASK_LEVEL SRVAL32,SPEC_,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63
++ CREATE_MASK_ALT AFVAL32,SPEC_,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47
++ CREATE_MASK_ALT AFVAL48,SPEC_,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63
++
++ CREATE_MASK_DIR DRVAL64,SPEC_,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95
++ CREATE_MASK_LEVEL SRVAL64,SPEC_,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95
++ CREATE_MASK_ALT AFVAL64,SPEC_,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79
++ CREATE_MASK_ALT AFVAL80,SPEC_,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95
++
+diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxaGpio27x.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaGpio27x.h
+--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxaGpio27x.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaGpio27x.h 2007-08-11 21:07:21.000000000 +0200
+@@ -0,0 +1,221 @@
++//gpios for HALOGEN
++
++//CP - Clock and Power Management Unit
++//MMC - Multimedia Card Controller
++//MC - Memory Controller
++//SIU - System Integration Unit
++//SSP - Synchronous Serial Port
++//AC - Audio Controller (AC97)
++//FF - Full Function UART
++//BT - Blue Tooth UART
++//ST - standard UART Port
++//LCD - LCD Controller
++
++ SPEC_GP 0,IN,HIGH,0 //
++ SPEC_GP 1,IN,HIGH,0 //nRESET_GPIO, usb client connect interrupt
++
++ SPEC_GP 2,IN,HIGH,0 //SYS_EN
++
++ SPEC_GP 3,IN,HIGH,0 //PWR_SCL, Rev 1 usb client enable, float means USB Slave not ready to accept data
++ //out 1 means ready
++
++ SPEC_GP 4,IN,HIGH,0 //PWR_SDA
++
++ SPEC_GP 5,IN,HIGH,0 //PWR_CAP 0
++ SPEC_GP 6,IN,HIGH,0 //PWR_CAP 1
++ SPEC_GP 7,IN,HIGH,0 //PWR_CAP 2
++ SPEC_GP 8,IN,HIGH,0 //PWR_CAP 3
++ SPEC_GP 9,OUT,HIGH,0 //NC
++#if (PLATFORM_REV==1)
++ SPEC_GP 10,OUT,HIGH,0 //NC, rev 1 doesn't have MMC write protect, or card detect
++#else
++ SPEC_GP 10,IN,HIGH,0 //MMC card detect
++#endif
++
++ SPEC_GP 11,OUT,HIGH,0 //NC
++ SPEC_GP 12,OUT,HIGH,0 //NC
++ SPEC_GP 13,OUT,HIGH,0 //NC
++
++ SPEC_GP 14,OUT,HIGH,0 //NC
++ SPEC_GP 15,OUT,HIGH,2 //nCS1, NC
++
++
++ SPEC_GP 16,OUT,LOW,0 //PWM0 backlight intensity, 0 brightest
++ SPEC_GP 17,OUT,HIGH,0 //NC
++
++ SPEC_GP 18,IN,HIGH,1 //MC_RDY, VIO_READY
++
++ SPEC_GP 19,OUT,HIGH,0 //NC
++
++ SPEC_GP 20,OUT,HIGH,1 //MC_DREQ0, NC
++
++ SPEC_GP 21,OUT,HIGH,0 //NC
++ SPEC_GP 22,OUT,HIGH,0 //NC
++
++#if (PLATFORM_REV==1)
++ SPEC_GP 23,OUT,HIGH,0 //NC
++#else
++ SPEC_GP 23,IN,HIGH,0 //rev 2 UCB1400 int
++#endif
++
++ SPEC_GP 24,IN,LOW,0 //LAN91c111 Interrupt pin (SMSC)
++
++ SPEC_GP 25,OUT,HIGH,0 //SSP_TXD, nc
++ SPEC_GP 26,OUT,HIGH,0 //SSP_RXD, nc
++ SPEC_GP 27,OUT,HIGH,0 //NC
++
++ SPEC_GP 28,IN,HIGH,1 //AC_BITCLK, ac97 bitclk
++ SPEC_GP 29,IN,HIGH,1 //AC_SDATAIN0, ac97 datain0
++ SPEC_GP 30,OUT,HIGH,2 //AC_SDATAOUT, ac97 data out
++ SPEC_GP 31,OUT,HIGH,2 //AC_SYNC, ac97 sync
++////////////////////////////////////////////////////////////////////////////////////////////
++
++
++ SPEC_GP 32,OUT,HIGH,2 //MMCLK
++ SPEC_GP 33,OUT,HIGH,0 //MC_nCS5, NC
++ SPEC_GP 34,IN,HIGH,1 //(in alt 1:FF_RXD) (out alt 1:USB_P2_2) 2 input, Session Valid
++ SPEC_GP 35,IN,HIGH,0 //(in alt 1:FF_CTS) (in alt 2:USB_P2_1) 1 input, SRP Detect
++#if (PLATFORM_REV==1)
++ SPEC_GP 36,OUT,HIGH,0 //(in alt 1:FF_DCD)
++#else
++ SPEC_GP 36,IN,HIGH,0 //(in alt 1:FF_DCD) (out alt 1:USB_P2_4) 4 output Vbus Enable
++#endif
++ SPEC_GP 37,OUT,HIGH,0 //(in alt 1:FF_DSR) (out alt 1:USB_P2_8) 8 output Vbus Pulsing Enable for SRP
++
++ SPEC_GP 38,IN,HIGH,0 //(in alt 1:FF_RI) (in alt 3:USB_P2_3) //MMC Write Protect (rev 1 is NC),// 3 input, Vbus valid 4.4 Volts
++ SPEC_GP 39,OUT,HIGH,2 //(out alt 2:FF_TXD) (out alt 1:USB_P2_6)
++
++#if (PLATFORM_REV==1)
++ SPEC_GP 40,OUT,HIGH,2 //(out alt 2:FF_DTR)
++#else
++ SPEC_GP 40,IN,HIGH,0 //(out alt 2:FF_DTR) (in alt 3:USB_P2_5) 5 input, Vbus valid 4.0 Volts
++#endif
++
++ SPEC_GP 41,OUT,HIGH,2 //(out alt 2:FF_RTS) (in alt 2:USB_P2_7) 7 input OTG ID
++ SPEC_GP 42,IN,HIGH,1 //BT_RXD
++ SPEC_GP 43,OUT,HIGH,2 //BT_TXD
++ SPEC_GP 44,OUT,HIGH,0 //BT_CTS, NC
++ SPEC_GP 45,OUT,LOW,0 //BT_RTS, NC
++ SPEC_GP 46,IN,HIGH,2 //ST_RXD
++ SPEC_GP 47,OUT,HIGH,1 //ST_TXD
++ SPEC_GP 48,OUT,HIGH,2 //MC_nPOE,NC
++ SPEC_GP 49,OUT,HIGH,2 //MC_nPWE
++ SPEC_GP 50,OUT,HIGH,2 //MC_nPIOR, NC
++ SPEC_GP 51,OUT,HIGH,2 //MC_nPIOW, NC
++ SPEC_GP 52,OUT,HIGH,2 //MC_nPCE1, NC
++ SPEC_GP 53,OUT,HIGH,2 //MC_nPCE2, NC
++ SPEC_GP 54,OUT,HIGH,2 //MC_nPSKTSEL, nc
++ SPEC_GP 55,OUT,HIGH,2 //MC_nPREG, NC
++ SPEC_GP 56,IN,HIGH,1 //MC_nPWAIT NC
++ SPEC_GP 57,IN,HIGH,1 //MC_nIOIS16, NC
++ SPEC_GP 58,OUT,HIGH,ALT_LCD //LCD_LDD0
++ SPEC_GP 59,OUT,HIGH,ALT_LCD //LCD_LDD1
++ SPEC_GP 60,OUT,HIGH,ALT_LCD //LCD_LDD2
++ SPEC_GP 61,OUT,HIGH,ALT_LCD //LCD_LDD3
++ SPEC_GP 62,OUT,HIGH,ALT_LCD //LCD_LDD4
++ SPEC_GP 63,OUT,HIGH,ALT_LCD //LCD_LDD5
++
++
++////////////////////////////////////////////////////////////////////////////////////////////
++
++
++ SPEC_GP 64,OUT,HIGH,ALT_LCD //LCD_LDD6
++ SPEC_GP 65,OUT,HIGH,ALT_LCD //LCD_LDD7
++ SPEC_GP 66,OUT,HIGH,ALT_LCD //LCD_LDD8
++ SPEC_GP 67,OUT,HIGH,ALT_LCD //LCD_LDD9
++ SPEC_GP 68,OUT,HIGH,ALT_LCD //LCD_LDD10
++ SPEC_GP 69,OUT,HIGH,ALT_LCD //LCD_LDD11
++ SPEC_GP 70,OUT,HIGH,ALT_LCD //LCD_LDD12
++
++ SPEC_GP 71,OUT,HIGH,ALT_LCD //LCD_LDD13
++
++ SPEC_GP 72,OUT,HIGH,ALT_LCD //LCD_LDD14
++ SPEC_GP 73,OUT,HIGH,ALT_LCD //LCD_LDD15
++ SPEC_GP 74,OUT,HIGH,ALT_LCD //LCD_FCLK, NC
++ SPEC_GP 75,OUT,HIGH,ALT_LCD //LCD_LCLK
++ SPEC_GP 76,OUT,HIGH,ALT_LCD //LCD_PCLK
++ SPEC_GP 77,OUT,HIGH,ALT_LCD //LCD_ACBIAS
++ SPEC_GP 78,OUT,HIGH,2 //nCS2, SMC91c111 Chip Select nDATACS
++ SPEC_GP 79,OUT,HIGH,2 //nCS3, NC
++ SPEC_GP 80,OUT,HIGH,2 //nCS4, SMC91c111 Chip Select
++ SPEC_GP 81,OUT,HIGH,0 //NC
++ SPEC_GP 82,OUT,HIGH,0 //NC
++ SPEC_GP 83,OUT,HIGH,0 //NC
++ SPEC_GP 84,OUT,HIGH,0 //NC
++ SPEC_GP 85,OUT,HIGH,0 //NC
++ SPEC_GP 86,OUT,HIGH,ALT_LCD //LDD16
++ SPEC_GP 87,OUT,HIGH,ALT_LCD //LDD17
++#if (PLATFORM_REV==1)
++ SPEC_GP 88,OUT,HIGH,0 //NC
++ SPEC_GP 89,OUT,HIGH,0 //NC
++#else
++ SPEC_GP 88,IN,HIGH,1 //port 1 usb power over current
++ SPEC_GP 89,OUT,HIGH,0 //port 1 usb power enable (driver needs to enable usb power (LOW,2)
++#endif
++
++ SPEC_GP 90,OUT,HIGH,0 //NC
++ SPEC_GP 91,OUT,HIGH,0 //NC
++ SPEC_GP 92,OUT,HIGH,1 //MMDAT
++ SPEC_GP 93,OUT,HIGH,0 //NC
++ SPEC_GP 94,OUT,HIGH,0 //NC
++ SPEC_GP 95,OUT,HIGH,0 //NC
++ SPEC_GP 96,OUT,HIGH,0 //NC
++ SPEC_GP 97,OUT,HIGH,0 //NC
++ SPEC_GP 98,OUT,HIGH,0 //NC
++ SPEC_GP 99,OUT,HIGH,0 //NC
++ SPEC_GP 100,OUT,HIGH,0 //NC
++ SPEC_GP 101,OUT,HIGH,0 //NC
++ SPEC_GP 102,OUT,HIGH,0 //NC
++ SPEC_GP 103,OUT,HIGH,0 //port 1,USB Power Enable for REV 1 board (driver needs to enable usb power (LOW,0)
++ SPEC_GP 104,OUT,HIGH,0 //NC
++
++#if (PLATFORM_REV==1)
++ SPEC_GP 105,IN,HIGH,0 //USB Overcurrent
++#else
++ SPEC_GP 105,OUT,HIGH,0 //NC
++#endif
++
++ SPEC_GP 106,OUT,HIGH,0 //NC
++ SPEC_GP 107,OUT,HIGH,0 //NC
++ SPEC_GP 108,OUT,HIGH,0 //NC
++ SPEC_GP 109,OUT,HIGH,1 //MMDAT 1
++ SPEC_GP 110,OUT,HIGH,1 //MMDAT 2
++ SPEC_GP 111,OUT,HIGH,1 //MMDAT 3
++ SPEC_GP 112,OUT,HIGH,1 //MMCMD
++ SPEC_GP 113,OUT,HIGH,2 //AC97 Reset, NC
++ SPEC_GP 114,OUT,HIGH,0 //NC
++ SPEC_GP 115,OUT,HIGH,0 //NC
++ SPEC_GP 116,OUT,HIGH,0 //NC
++ SPEC_GP 117,OUT,HIGH,1 //SCL (I2C)
++ SPEC_GP 118,OUT,HIGH,1 //SDA (I2C)
++ SPEC_GP 119,OUT,HIGH,0 //NC
++ SPEC_GP 120,OUT,HIGH,0 //NC
++ SPEC_GP 121,IN,LOW,0 //undefined
++ SPEC_GP 122,IN,LOW,0 //undefined
++ SPEC_GP 123,IN,LOW,0 //undefined
++ SPEC_GP 124,IN,LOW,0 //undefined
++ SPEC_GP 125,IN,LOW,0 //undefined
++ SPEC_GP 126,IN,LOW,0 //undefined
++ SPEC_GP 127,IN,LOW,0 //undefined
++
++// ****************************************************************************
++ CREATE_MASK_DIR DRVAL0, SPEC_, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
++ CREATE_MASK_LEVEL SRVAL0, SPEC_, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
++ CREATE_MASK_ALT AFVAL0, SPEC_, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
++ CREATE_MASK_ALT AFVAL16,SPEC_,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
++
++ CREATE_MASK_DIR DRVAL32,SPEC_,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63
++ CREATE_MASK_LEVEL SRVAL32,SPEC_,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63
++ CREATE_MASK_ALT AFVAL32,SPEC_,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47
++ CREATE_MASK_ALT AFVAL48,SPEC_,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63
++
++ CREATE_MASK_DIR DRVAL64,SPEC_,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95
++ CREATE_MASK_LEVEL SRVAL64,SPEC_,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95
++ CREATE_MASK_ALT AFVAL64,SPEC_,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79
++ CREATE_MASK_ALT AFVAL80,SPEC_,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95
++
++ CREATE_MASK_DIR DRVAL96,SPEC_,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127
++ CREATE_MASK_LEVEL SRVAL96,SPEC_,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127
++ CREATE_MASK_ALT AFVAL96,SPEC_, 96, 97, 98, 99,100,101,102,103,104,105,106,107,108,109,110,111
++ CREATE_MASK_ALT AFVAL112,SPEC_,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127
++
+diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxaGpio.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaGpio.h
+--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxaGpio.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaGpio.h 2007-08-11 21:07:21.000000000 +0200
+@@ -0,0 +1,142 @@
++#include "platformTypes.h"
++
++#define IN 0
++#define OUT 1
++
++#define LOW 0
++#define HIGH 1
++
++ .ifdef __ARMASM
++.macro SPEC_GP gp_,dir,level,alt
++SPEC_\gp_ EQU \dir+(\level<<8)+(\alt<<16)
++.endm
++ .else
++.macro SPEC_GP gp_,dir,level,alt
++ .set SPEC_\gp_,\dir+(\level<<8)+(\alt<<16)
++.endm
++ .endif
++// *****************************************************************************************
++.macro CREATE_MASK_DIR name,prefix,p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31
++ .ifdef __ARMASM
++ LCLA mask
++ .endif
++ .set mask,((\prefix\p0&1)<<(\p0&0x1f))
++ .set mask,mask | ((\prefix\p1&1)<<(\p1&0x1f))
++ .set mask,mask | ((\prefix\p2&1)<<(\p2&0x1f))
++ .set mask,mask | ((\prefix\p3&1)<<(\p3&0x1f))
++ .set mask,mask | ((\prefix\p4&1)<<(\p4&0x1f))
++ .set mask,mask | ((\prefix\p5&1)<<(\p5&0x1f))
++ .set mask,mask | ((\prefix\p6&1)<<(\p6&0x1f))
++ .set mask,mask | ((\prefix\p7&1)<<(\p7&0x1f))
++ .set mask,mask | ((\prefix\p8&1)<<(\p8&0x1f))
++ .set mask,mask | ((\prefix\p9&1)<<(\p9&0x1f))
++ .set mask,mask | ((\prefix\p10&1)<<(\p10&0x1f))
++ .set mask,mask | ((\prefix\p11&1)<<(\p11&0x1f))
++ .set mask,mask | ((\prefix\p12&1)<<(\p12&0x1f))
++ .set mask,mask | ((\prefix\p13&1)<<(\p13&0x1f))
++ .set mask,mask | ((\prefix\p14&1)<<(\p14&0x1f))
++ .set mask,mask | ((\prefix\p15&1)<<(\p15&0x1f))
++ .set mask,mask | ((\prefix\p16&1)<<(\p16&0x1f))
++ .set mask,mask | ((\prefix\p17&1)<<(\p17&0x1f))
++ .set mask,mask | ((\prefix\p18&1)<<(\p18&0x1f))
++ .set mask,mask | ((\prefix\p19&1)<<(\p19&0x1f))
++ .set mask,mask | ((\prefix\p20&1)<<(\p20&0x1f))
++ .set mask,mask | ((\prefix\p21&1)<<(\p21&0x1f))
++ .set mask,mask | ((\prefix\p22&1)<<(\p22&0x1f))
++ .set mask,mask | ((\prefix\p23&1)<<(\p23&0x1f))
++ .set mask,mask | ((\prefix\p24&1)<<(\p24&0x1f))
++ .set mask,mask | ((\prefix\p25&1)<<(\p25&0x1f))
++ .set mask,mask | ((\prefix\p26&1)<<(\p26&0x1f))
++ .set mask,mask | ((\prefix\p27&1)<<(\p27&0x1f))
++ .set mask,mask | ((\prefix\p28&1)<<(\p28&0x1f))
++ .set mask,mask | ((\prefix\p29&1)<<(\p29&0x1f))
++ .set mask,mask | ((\prefix\p30&1)<<(\p30&0x1f))
++ .set mask,mask | ((\prefix\p31&1)<<(\p31&0x1f))
++ .ifdef __ARMASM
++\name EQU mask
++ .else
++ .set \name,mask
++ .endif
++.endm
++
++.macro CREATE_MASK_LEVEL name,prefix,p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,p16,p17,p18,p19,p20,p21,p22,p23,p24,p25,p26,p27,p28,p29,p30,p31
++ .ifdef __ARMASM
++ LCLA mask
++ .endif
++ .set mask,(((\prefix\p0>>8)&1)<<(\p0&0x1f))
++ .set mask,mask | (((\prefix\p1>>8)&1)<<(\p1&0x1f))
++ .set mask,mask | (((\prefix\p2>>8)&1)<<(\p2&0x1f))
++ .set mask,mask | (((\prefix\p3>>8)&1)<<(\p3&0x1f))
++ .set mask,mask | (((\prefix\p4>>8)&1)<<(\p4&0x1f))
++ .set mask,mask | (((\prefix\p5>>8)&1)<<(\p5&0x1f))
++ .set mask,mask | (((\prefix\p6>>8)&1)<<(\p6&0x1f))
++ .set mask,mask | (((\prefix\p7>>8)&1)<<(\p7&0x1f))
++ .set mask,mask | (((\prefix\p8>>8)&1)<<(\p8&0x1f))
++ .set mask,mask | (((\prefix\p9>>8)&1)<<(\p9&0x1f))
++ .set mask,mask | (((\prefix\p10>>8)&1)<<(\p10&0x1f))
++ .set mask,mask | (((\prefix\p11>>8)&1)<<(\p11&0x1f))
++ .set mask,mask | (((\prefix\p12>>8)&1)<<(\p12&0x1f))
++ .set mask,mask | (((\prefix\p13>>8)&1)<<(\p13&0x1f))
++ .set mask,mask | (((\prefix\p14>>8)&1)<<(\p14&0x1f))
++ .set mask,mask | (((\prefix\p15>>8)&1)<<(\p15&0x1f))
++ .set mask,mask | (((\prefix\p16>>8)&1)<<(\p16&0x1f))
++ .set mask,mask | (((\prefix\p17>>8)&1)<<(\p17&0x1f))
++ .set mask,mask | (((\prefix\p18>>8)&1)<<(\p18&0x1f))
++ .set mask,mask | (((\prefix\p19>>8)&1)<<(\p19&0x1f))
++ .set mask,mask | (((\prefix\p20>>8)&1)<<(\p20&0x1f))
++ .set mask,mask | (((\prefix\p21>>8)&1)<<(\p21&0x1f))
++ .set mask,mask | (((\prefix\p22>>8)&1)<<(\p22&0x1f))
++ .set mask,mask | (((\prefix\p23>>8)&1)<<(\p23&0x1f))
++ .set mask,mask | (((\prefix\p24>>8)&1)<<(\p24&0x1f))
++ .set mask,mask | (((\prefix\p25>>8)&1)<<(\p25&0x1f))
++ .set mask,mask | (((\prefix\p26>>8)&1)<<(\p26&0x1f))
++ .set mask,mask | (((\prefix\p27>>8)&1)<<(\p27&0x1f))
++ .set mask,mask | (((\prefix\p28>>8)&1)<<(\p28&0x1f))
++ .set mask,mask | (((\prefix\p29>>8)&1)<<(\p29&0x1f))
++ .set mask,mask | (((\prefix\p30>>8)&1)<<(\p30&0x1f))
++ .set mask,mask | (((\prefix\p31>>8)&1)<<(\p31&0x1f))
++ .ifdef __ARMASM
++\name EQU mask
++ .else
++ .set \name,mask
++ .endif
++.endm
++
++.macro CREATE_MASK_ALT name,prefix,p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15
++ .ifdef __ARMASM
++ LCLA mask
++ .endif
++ .set mask,(((\prefix\p0>>16)&3)<<((\p0&0x0f)<<1))
++ .set mask,mask | (((\prefix\p1>>16)&3)<<((\p1&0x0f)<<1))
++ .set mask,mask | (((\prefix\p2>>16)&3)<<((\p2&0x0f)<<1))
++ .set mask,mask | (((\prefix\p3>>16)&3)<<((\p3&0x0f)<<1))
++ .set mask,mask | (((\prefix\p4>>16)&3)<<((\p4&0x0f)<<1))
++ .set mask,mask | (((\prefix\p5>>16)&3)<<((\p5&0x0f)<<1))
++ .set mask,mask | (((\prefix\p6>>16)&3)<<((\p6&0x0f)<<1))
++ .set mask,mask | (((\prefix\p7>>16)&3)<<((\p7&0x0f)<<1))
++ .set mask,mask | (((\prefix\p8>>16)&3)<<((\p8&0x0f)<<1))
++ .set mask,mask | (((\prefix\p9>>16)&3)<<((\p9&0x0f)<<1))
++ .set mask,mask | (((\prefix\p10>>16)&3)<<((\p10&0x0f)<<1))
++ .set mask,mask | (((\prefix\p11>>16)&3)<<((\p11&0x0f)<<1))
++ .set mask,mask | (((\prefix\p12>>16)&3)<<((\p12&0x0f)<<1))
++ .set mask,mask | (((\prefix\p13>>16)&3)<<((\p13&0x0f)<<1))
++ .set mask,mask | (((\prefix\p14>>16)&3)<<((\p14&0x0f)<<1))
++ .set mask,mask | (((\prefix\p15>>16)&3)<<((\p15&0x0f)<<1))
++ .ifdef __ARMASM
++\name EQU mask
++ .else
++ .set \name,mask
++ .endif
++.endm
++
++#if (PLATFORM_TYPE==NEON)||(PLATFORM_TYPE==NEONB)||(PLATFORM_TYPE==BD2003)||(PLATFORM_TYPE==BOUNDARY_OLD_BOARD)
++#define ALT_LCD 2
++#include "pxaGpio25x.h"
++#else
++#if (PLATFORM_TYPE==HALOGEN)
++#define ALT_LCD 2
++#include "pxaGpio27x.h"
++#else
++#include "pxaGpioGame.h"
++#endif
++#endif
+diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxaHardware.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaHardware.h
+--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxaHardware.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaHardware.h 2007-08-11 21:07:21.000000000 +0200
+@@ -0,0 +1,288 @@
++//#define GPIO_BASE 0x40E00000
++#define GPLR0 0x00 //level
++#define GPLR1 0x04
++#define GPLR2 0x08
++#define GPLR3 0x100 //level
++
++#define GPDR0 0x0c //direction
++#define GPDR1 0x10
++#define GPDR2 0x14
++#define GPDR3 0x10c //direction
++
++#define GPSR0 0x18 //set
++#define GPSR1 0x1C
++#define GPSR2 0x20
++#define GPSR3 0x118 //set
++
++#define GPCR0 0x24 //clear
++#define GPCR1 0x28
++#define GPCR2 0x2c
++#define GPCR3 0x124 //clear
++
++#define GRER0 0x30 //enable rising edge detect
++#define GRER1 0x34
++#define GRER2 0x38
++#define GRER3 0x130 //enable rising edge detect
++
++#define GFER0 0x3C //enable falling edge detect
++#define GFER1 0x40
++#define GFER2 0x44
++#define GFER3 0x13C //enable falling edge detect
++
++#define GEDR0 0x48 //edge detect status
++#define GEDR1 0x4C
++#define GEDR2 0x50
++#define GEDR3 0x148 //edge detect status
++
++#define GAFR0_L 0x54 //alternate function
++#define GAFR0_U 0x58
++#define GAFR1_L 0x5C
++#define GAFR1_U 0x60
++#define GAFR2_L 0x64
++#define GAFR2_U 0x68
++#define GAFR3_L 0x6c
++#define GAFR3_U 0x70
++
++
++#define UART_RBR 0 //read, DLAB-0 :RECEIVE_BUFFER
++#define UART_THR 0 //write, DLAB-0 :TRANSMIT_BUFFER
++#define UART_DLL 0 //r/w, DLAB-1 :DIVISOR_LOW
++#define UART_IER 4 //r/w, DLAB-0 :INTERRUPT_ENABLE
++#define UART_DLH 4 //r/w, DLAB-1 :DIVISOR_HIGH
++
++#define UART_IIR 8 //read :INTERRUPT_INDENTIFICATION
++#define UART_FCR 8 //write :FIFO_CONTROL
++#define UART_LCR 0x0c //r/w :LINE_CONTROL
++#define UART_MCR 0x10 //r/w :MODEM_CONTROL
++#define UART_LSR 0x14 //read :LINE_STATUS
++#define UART_MSR 0x18 //read :MODEM_STATUS
++#define UART_SPR 0x1c //r/w :SCRATCH_PAD
++#define UART_ISR 0x20 //r/w :INFRARED
++
++//#define IC_BASE 0x40D00000
++#define ICIP 0x00 //IRQ pending status
++#define ICMR 0x04 //interrupt controller mask
++#define ICLR 0x08 //level, 0 - irq, 1 -fiq
++#define ICFP 0x0C //FIQ pending status
++#define ICPR 0x10 //all interrupts pending, no mask
++#define ICCR 0x14 //0 - ignore ICMR in idle mode, 1 - only unmasked interrupts will awaken processor
++
++
++#define __SKIP 8
++#define ICL1_GPIO0 (8 - __SKIP)
++#define ICL1_GPIO1 (9 - __SKIP)
++#define ICL1_GPIO2_80 (10 - __SKIP)
++#define ICL1_USB (11 - __SKIP)
++#define ICL1_PMU (12 - __SKIP)
++#define ICL1_I2S (13 - __SKIP)
++#define ICL1_AC97 (14 - __SKIP)
++#define ICL1_LCD (17 - __SKIP)
++#define ICL1_I2C (18 - __SKIP)
++#define ICL1_ICP (19 - __SKIP)
++#define ICL1_STUART (20 - __SKIP)
++#define ICL1_BTUART (21 - __SKIP)
++#define ICL1_FFUART (22 - __SKIP)
++#define ICL1_MMC (23 - __SKIP)
++#define ICL1_SSP (24 - __SKIP)
++#define ICL1_DMA (25 - __SKIP)
++#define ICL1_OS_TIMER0 (26 - __SKIP)
++#define ICL1_OS_TIMER1 (27 - __SKIP)
++#define ICL1_OS_TIMER2 (28 - __SKIP)
++#define ICL1_OS_TIMER3 (29 - __SKIP)
++#define ICL1_RTC_TICK (30 - __SKIP)
++#define ICL1_RTC_ALARM_MATCH (31 - __SKIP)
++
++//#define OS_TIMER_BASE 0x40a00000
++#define OSMR0 0x00
++#define OSMR1 0x04
++#define OSMR2 0x08
++#define OSMR3 0x0c
++#define OSCR 0x10 //OS timer Count register, increments at 3.6864 Mhz
++#define OSSR 0x14 //OS timer Status Register
++#define OWER 0x18 //OS timer Watchdog Match enable register
++#define OIER 0x1c
++
++//3686400 ticks/seconds = 3.6864 ticks/usec = 1 tick/.271267361111 usec
++#define TICK_PER_USEC_WHOLE 3
++#define TICK_PER_USEC_FRAC 0xAFB7E910
++//////////////////////////////////////////////////////////////////////////////////////////
++
++//#define PWR_MANAGER_BASE 0x40F00000
++#define PMCR 0
++#define PSSR 4
++#define PSPR 8
++#define PWER 0x0c
++#define PRER 0x10
++#define PFER 0x14
++#define PEDR 0x18
++#define PCFR 0x1c
++#define PGSR0 0x20
++#define PGSR1 0x24
++#define PGSR2 0x28
++#define RCSR 0x30
++
++#define PSSR_MASK 0x37
++#define RCSR_MASK 0x0f
++#define RCSR_SLEEP_RESET 4
++
++//#define CLK_MANAGER_BASE 0x41300000
++#define CCCR 0
++#define CKEN 4
++#define OSCC 8
++
++//#define MEMORY_CONTROL_BASE 0x48000000
++#define MDCNFG 0
++#define MDREFR 4
++#define MSC0 8
++#define MSC1 0x0c
++#define MSC2 0x10
++#define MECR 0x14
++#define SXCNFG 0x1c
++#define SXMRS 0x24
++#define MCMEM0 0x28
++#define MCMEM1 0x2c
++#define MCATT0 0x30
++#define MCATT1 0x34
++#define MCIO0 0x38
++#define MCIO1 0x3c
++#define MDMRS 0x40
++#define BOOT_DEF 0x44
++
++
++//#define LCD_CONTROL_BASE 0x44000000
++#define LCD_CR0 0 //master enable last
++#define LCD_CR1 4
++#define LCD_CR2 8
++#define LCD_CR3 0x0c
++#define LCD_FBR0 0x20 //Frame branch register
++#define LCD_FBR1 0x24 //Frame branch register
++#define LCD_SR 0x38
++#define LCD_INT_ID 0x3c
++#define LCD_TMEDS 0x40 //TMED RGB seed
++#define LCD_TMEDC 0x44 //TMED control
++#define LCD_FDADR0 0x200 //frame descriptor address register
++#define LCD_FDADR1 0x210 //frame descriptor address register
++
++#define LCD_FSADR0 0x204 //frame source address register
++#define LCD_FSADR1 0x214 //frame source address register
++
++#define LCD_FIDR0 0x208 //frame ID register
++#define LCD_FIDR1 0x218 //frame ID register
++
++#define LCD_DCMD0 0x20c //dma command
++#define LCD_DCMD1 0x21c //dma command
++
++#define CRO_LDDALT 26 //LDDALT ;0 selects RGB 555, 1 selects RGB 565
++#define CRO_OUC 25 //OUC ;0 underlays, 1 overlays
++#define CR0_CMDIM 24 //CMDIM ;command interrupt mask, 0 - enabled, 1 disabled
++#define CR0_RDSTM 23 //RDSTM ;read status interrupt mask, 0 - enabled, 1 disabled
++#define CR0_LCDT 22 //LCDT ;LCD Panel Type, 1 - internal frame buffer
++#define CR0_IM_OUTPUT_FIFO_UNDERRUN 21 //OUM IM stands for Interrupt Mask
++#define CR0_IM_BRANCH 20 //BSM0
++#define CR0_PALETTE_DMA_REQUEST_DELAY 12 //PDD 8 bit field, 0-255
++#define CR0_IM_LCD_QUICK_DISABLE 11 //QDM
++#define CR0_DISABLE 10 //DIS
++#define CR0_DOUBLE_PIXEL_DATA 9 //DPD
++#define CR0_ACTIVE_SELECT 7 //PAS
++#define CR0_IM_END_OF_FRAME 6 //EOFM0
++#define CR0_IM_INPUT_FIFO_UNDERRUN 5 //IUM
++#define CR0_IM_START_OF_FRAME 4 //SOFM0
++#define CR0_IM_DISABLE_DONE 3 //LDM
++#define CR0_DUAL_PANEL_SELECT 2 //SDS
++#define CR0_MONOCHROME_SELECT 1 //CMS
++#define CR0_ENABLE 0 //ENB
++
++
++
++
++#define CR1_BEGINNING_OF_LINE_WAIT 24 //8 bit field +1
++#define CR1_END_OF_LINE_WAIT 16 //8 bit field +1
++#define CR1_HORIZONTAL_SYNC_PULSE_WIDTH 10 //6 bit field +1
++#define CR1_PIXELS_PER_LINE 0 //10 bit field +1
++
++
++
++#define CR2_BEGINNING_OF_FRAME_WAIT 24 //8 bit field
++#define CR2_END_OF_FRAME_WAIT 16 //8 bit field
++#define CR2_VERTICAL_SYNC_PULSE_WIDTH 10 //6 bit field +1
++#define CR2_LINES_PER_PANEL 0 //10 bit field +1
++
++
++#define CR3_PDFOR 30
++#define CR3_DOUBLE_PCLK 27
++#define CR3_BITS_PER_PIXEL 24 //3 bit field
++//0 - 1 bit
++//1 - 2 bits
++//2 - 4 bits
++//3 - 8 bits
++//4 - 16 bits,
++//5-7 reserved
++#define CR3_BIAS_POLARITY 23
++#define CR3_PCLK_POLARITY 22
++#define CR3_LCLK_POLARITY 21
++#define CR3_FCLK_POLARITY 20
++#define CR3_API 16 //4 bits field, ac bias transitions per interrupt, 0 disable
++#define CR3_ACBIAS_TOGGLE 8 //8 bit field +1
++#define CR3_PCLK_DIVISOR 0 //8 bit field +1
++
++
++
++#define FBR_BRANCH_INT 1
++#define FBR_BRANCH 0
++
++
++#define SR_MISSED_INT 10
++#define SR_BRANCH_INT 9
++#define SR_END_OF_FRAME_INT 8
++#define SR_QUICK_DISABLE_INT 7
++#define SR_OUTPUT_FIFO_UNDERRUN 6
++#define SR_INPUT_FIFO_UNDERRUN0 5
++#define SR_INPUT_FIFO_UNDERRUN1 4
++#define SR_ACBIAS_COUNT_INT 3
++#define SR_BUS_ERROR 2
++#define SR_START_OF_FRAME 1
++#define SR_DISABLE_DONE 0
++
++#define TMEDS_BLUE 16 //8 bit field
++#define TMEDS_GREEN 8 //8 bit field
++#define TMEDS_RED 0 //8 bit field
++
++
++#define TMEDC_MATRIX2_SELECT 14
++#define TMEDC_RESERVED 12 //2 bit field
++#define TMEDC_HORIZONTAL_BEAT_SUPPRESSION 8 //4 bit field
++#define TMEDC_VERTICAL_BEAT_SUPPRESSION 4 //4 bit field
++#define TMEDC_FRAME_NUMBER_ADJUST_EN 3
++#define TMEDC_COLOR_OFFSET_ADJUST_EN 2
++#define TMEDC_FRAME_NUMBER_ADJUST_MATRIX2 1
++#define TMEDC_COLOR_OFFSET_ADJUST_MATRIX2 0
++
++
++#define DCMD_PALETTE 26
++#define DCMD_START_OF_FRAME_INTERRUPT 22
++#define DCMD_END_OF_FRAME_INTERRUPT 21
++#define DCMD_LENGTH 0 //21 bit field
++
++
++#define FDESC_FDADR 0
++#define FDESC_FSADR 4
++#define FDESC_FIDR 8
++#define FDESC_DCMD 0x0c
++
++#define PSR_MODE_MASK 0x1f
++#define PSR_MODE_USER 0x10
++#define PSR_MODE_FIQ 0x11
++#define PSR_MODE_IRQ 0x12
++#define PSR_MODE_SVC 0x13
++#define PSR_MODE_DEBUG 0x15
++#define PSR_MODE_ABORT 0x17
++#define PSR_MODE_UNDEF 0x1b
++#define PSR_MODE_SYSTEM 0x1f
++#define PSR_NOINTS_MASK 0xc0
++
++#define FUNC_REQ_GL 0
++#define FUNC_REQ_DLW 1
++#define FUNC_REQ_GAME 2 //not specifically referenced
++#define FUNC_REQ_MAC 3
++#define FUNC_REQ_WAKEUP 4
++#define FUNC_REQ_PIC 5
+diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxaLcd2.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaLcd2.h
+--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxaLcd2.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaLcd2.h 2007-08-11 21:07:21.000000000 +0200
+@@ -0,0 +1,78 @@
++#include "pxaLcd.h"
++#define DA320X240 0
++#define DA640X240 1
++#define DA800X480 2
++#define DA640X480 3
++#define DA240X320 4
++#define DA800X600 5
++#define DA1024X768 6
++#define DP480X320 7
++#define DP320X240 8
++#define DL122X32 9
++#define UNKNOWN 0xcc
++
++#ifdef __ARMASM
++ GBLS DEF_P
++#endif
++
++#if DISPLAY_TYPE==DA320X240 //5.7 inch display
++#define DEF_P DA320X240_P
++#define DEF_DISPLAY_INDEX 0
++#else
++#if DISPLAY_TYPE==DA640X240 //6.2 inch display
++#define DEF_P DA640X240_P
++#define DEF_DISPLAY_INDEX 1
++#else
++#if DISPLAY_TYPE==DA800X480 //7 or 9 inch display
++#define DEF_P DA800X480_P
++#define DEF_DISPLAY_INDEX 2
++#else
++#if DISPLAY_TYPE==DA640X480 //10.4 inch display
++#define DEF_P DA640X480_P
++#define DEF_DISPLAY_INDEX 3
++#else
++#if DISPLAY_TYPE==DA240X320 //3.5 inch display
++#define DEF_P DA240X320_P
++#define DEF_DISPLAY_INDEX 4
++#else
++#if DISPLAY_TYPE==DA800X600
++#define DEF_P DA800X600_P
++#define DEF_DISPLAY_INDEX 5
++#else
++#if DISPLAY_TYPE==DA1024X768
++#define DEF_P DA1024X768_P
++#define DEF_DISPLAY_INDEX 6
++#else
++#if DISPLAY_TYPE==DP480X320 //5.7 inch display
++#define DEF_P DP480X320_P
++#define DEF_DISPLAY_INDEX 7
++#else
++#if DISPLAY_TYPE==DP320X240 //5.7 inch display
++#define DEF_P DP320X240_P
++#define DEF_DISPLAY_INDEX 8
++#else
++#if DISPLAY_TYPE==DL122X32
++#define DEF_P DL122X32_P
++#define DEF_DISPLAY_INDEX 9
++#else
++#if DISPLAY_TYPE==UNKNOWN
++#define DEF_P DA320X240_P
++#define DEF_DISPLAY_INDEX 0xcc
++
++#else
++#define DEF_P DA320X240_P
++#define DEF_DISPLAY_INDEX 0
++#warning "No display selected, defaulting to DA320X240"
++
++#endif //0xcc
++#endif //9
++#endif //8
++#endif //7
++#endif //6
++#endif //5
++#endif //4
++#endif //3
++#endif //2
++#endif //1
++#endif //0
++
+diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxaLcd.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaLcd.h
+--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxaLcd.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaLcd.h 2007-08-11 21:07:21.000000000 +0200
+@@ -0,0 +1,79 @@
++#include "platformTypes.h"
++#define WINCE 1
++#define LINUX 2
++#define GAME 3
++
++#define PXAFB_BPP 16
++
++#define LCD_PANEL 0
++#define CRT 1
++
++//pixel clock frequency = LCLK / (2*(PCD+1))
++#if (PLATFORM_TYPE==HALOGEN)
++#define __BPP 18
++#define BPP_FORMAT 6
++#define PDFOR 3
++#define BYTES_PER_PIXEL 3
++#else
++#define __BPP 16
++#define BPP_FORMAT 4
++#define PDFOR 0
++#define BYTES_PER_PIXEL 2
++#endif
++
++// ****************************************************************************
++// This is where different display settings reside
++// xres,xsyncWidth,xbegin,xend, yres,ysyncWidth,ybegin,yend, enable,unscramble,rotate,active,bpp,clkdiv,type
++//#define DA320X240_P 320, 64, 34, 1, 240, 20, 8, 3, 1,0,0,1,PXAFB_BPP,4,LCD_PANEL //0
++#define DA320X240_P 320, 64, 34, 11, 240, 5, 8, 3, 1,0,0,1,PXAFB_BPP,4,LCD_PANEL //0
++
++#define DA640X240_P 640, 64, 34, 1, 240, 20, 8, 3, 1,1,0,1,PXAFB_BPP,2,LCD_PANEL //1
++#define DA800X480_P 800, 64, 34, 1, 480, 20, 8, 3, 1,1,0,1,PXAFB_BPP,2,LCD_PANEL //2
++#define DA640X480_P 640, 64, 34,105, 480, 20, 8,14, 1,1,0,1,PXAFB_BPP,2,LCD_PANEL //3
++#define DA240X320_P 240, 64, 34, 1, 320, 20, 8, 3, 1,0,1,1,PXAFB_BPP,5,LCD_PANEL //4
++#define DA800X600_P 800,0x9b,0x31,0x69, 600,0x04,0x01,0x17, 1,1,0,1,PXAFB_BPP,2,CRT //5
++//#define DA1024X768_P 1024,0xc8,0x55,0xb4, 768,0x06,0x0b,0x1d, 1,1,0,1,PXAFB_BPP,2,CRT //6
++//#define DA1024X768_P 1024,0xe4,0x3c,0x70, 768,0x0c,0x0b,0x20, 1,1,0,1,PXAFB_BPP,2,CRT //6
++#define DA1024X768_P 1024,0xe4,0x3c,0x70, 768,0x0c,0x0b,0x20, 1,1,0,1,PXAFB_BPP,2,LCD_PANEL //6
++#define DP480X320_P 480, 64, 34, 1, 320,20,8,3, 1,0,0,0,PXAFB_BPP,3,LCD_PANEL //7
++#define DP320X240_P 320, 64, 34, 1, 240,20,8,3, 1,0,0,0,PXAFB_BPP,4,LCD_PANEL //8
++#define DL122X32_P 320, 64, 34, 1, 240,20,8,3, 0,0,0,0,PXAFB_BPP,4,0 //9
++
++// ********************************************************************************
++#if (PLATFORM_TYPE==BOUNDARY_OLD_BOARD)
++#define MOTHERBOARD_SCRAMBLED
++#endif
++
++//#define CONFIG_UNSCRAMBLE_LCD
++#ifdef CONFIG_UNSCRAMBLE_LCD
++#if 1 //FL_ACTIVE(DEF_P) //passive cannot swap pin order
++#ifdef MOTHERBOARD_SCRAMBLED
++
++#ifndef DAUGHTERBOARD_UNSCRAMBLE
++#define LCD_REORDER_BLUE 15,14, 8, 7, 6
++#define LCD_REORDER_GREEN 13,12,11, 5, 4, 3
++#define LCD_REORDER_RED 10, 9, 2, 1, 0
++#endif
++
++#else
++//motherboard is NOT scrambled
++#ifdef DAUGHTERBOARD_UNSCRAMBLE
++#define LCD_REORDER_BLUE 15,14,13,10, 9
++#define LCD_REORDER_GREEN 8, 4, 3, 2, 12, 11
++#define LCD_REORDER_RED 7, 6, 5, 1, 0
++#endif
++#endif //#ifdef MOTHERBOARD_SCRAMBLED
++#endif //#if FL_ACTIVE(DEF_P)
++#endif //#ifdef CONFIG_UNSCRAMBLE_LCD
++
++#ifndef LCD_REORDER_BLUE
++#if (BYTES_PER_PIXEL==2)
++#define LCD_REORDER_BLUE 0,1,2,3,4
++#define LCD_REORDER_GREEN 5,6,7,8,9,10
++#define LCD_REORDER_RED 11,12,13,14,15
++#else
++#define LCD_REORDER_BLUE 0,1,2,3,4,5
++#define LCD_REORDER_GREEN 6,7,8,9,10,11
++#define LCD_REORDER_RED 12,13,14,15,16,17
++#endif
++#endif
+diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxaMacro2.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaMacro2.h
+--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxaMacro2.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaMacro2.h 2007-08-11 21:07:21.000000000 +0200
+@@ -0,0 +1,540 @@
++#include "pxaMacro.h"
++// ************************************************************************************************
++// ************************************************************************************************
++
++//In: c-0 try 64meg, c-1 try 32meg
++// or if 16 bit mode
++// c-0 try 32meg, c-1 try 16meg
++//Out: z-0 if 16 bit mode
++.macro InitRam rBase,rTemp
++ BigMov \rBase,MEMORY_CONTROL_BASE
++ ldr \rTemp,[\rBase,#BOOT_DEF]
++ tst \rTemp,#1 //bit 0 - 1 means 16 bit mode
++ BigMov \rTemp,M64_MDCNFG_VAL
++ BigEor2Cs \rTemp,(M64_MDCNFG_VAL)^(M32_MDCNFG_VAL)
++#if (!(PLATFORM_TYPE==NEONB)) && (!(PLATFORM_TYPE==HALOGEN))
++ BigOrr2Ne \rTemp,(1<<2) //select 16 bit width
++#endif
++ str \rTemp,[\rBase,#MDCNFG]
++
++ mov \rTemp,#0
++ nop //pxa270 may need this for some reason, depending upon instruction alignment
++ str \rTemp,[\rBase,#MDMRS]
++
++
++ BigMov \rTemp,M64_MDREFR_VAL
++ BigEor2Cs \rTemp,(M64_MDREFR_VAL)^(M32_MDREFR_VAL)
++ str \rTemp,[\rBase,#MDREFR]
++.endm
++
++
++//In: z-1 - c-0 try 64meg, c-1 try 32meg
++// z-0 - c-0 try 32meg, c-1 try 16meg
++//out: rTemp - memory size
++.macro CheckRam rBase,rTemp,rTemp2
++ // Issue read requests to disabled bank to start refresh
++ BigMov \rBase,MEM_START+0x0C000000
++ ldr \rTemp, [\rBase]
++ mov \rTemp,#M32_MEM_SIZE
++ movcc \rTemp,#M64_MEM_SIZE
++#if (!(PLATFORM_TYPE==NEONB)) && (!(PLATFORM_TYPE==HALOGEN))
++ movne \rTemp,\rTemp,LSR #1
++#endif
++ BigMov \rBase,MEM_START
++#if 1
++ mov \rTemp2,#0x24<<2 //0x24 seems to work, but keep it safe
++81: sub \rTemp2,\rTemp2,#1
++ str \rTemp2,[\rBase]
++ movs \rTemp2,\rTemp2 //don't affect carry flag
++ bne 81b
++#endif
++ str \rTemp,[\rBase]
++ str \rBase,[\rBase,\rTemp,LSR #1]
++ ldr \rTemp2,[\rBase]
++ movcs \rTemp2,\rTemp //if 2nd time through, force match
++ cmp \rTemp2,\rTemp
++#if 1
++ strne \rTemp2,[\rBase,#4]
++// teq \rTemp2,\rTemp2
++#endif
++.endm
++
++#define tEHEL 0 //R14
++#define tAPA 3 //r15 25ns/10ns rounded up
++
++#define RDFSelect 13 //R2 : tAVQV : 110ns/10ns = 11; 11-1=10=RDF
++//#define RDFSelect 10 //R2 : tAVQV : 110ns/10ns = 11; 11-1=10=RDF
++ //0-11 map to 0-11
++ //12 -> 13, 13 ->15, 14->18, 15->23
++
++//#if (PLATFORM_TYPE==GAME_CONTROLLER_PLAITED_A1)
++#if (PLATFORM_TYPE==GAME_CONTROLLER_PLAITED_A1)||(PLATFORM_TYPE==GAME_CONTROLLER)||(PLATFORM_TYPE==GAME_WITH_SMC)
++#define BurstSelect 0 //if plaited bug, burst mode will no longer work.
++#else
++#define BurstSelect 2 //0->nonburst,1->SRAM,2->burst of4, 3->burst of 8, 4->variable latency i/o
++#endif
++
++
++#if (PLATFORM_TYPE==NEONB)
++//access time 70ns, 25ns after CS data becomes valid
++// RRR RDN RDF RBW RTX
++// gap between Address to
++// 1-fast chip selects data valid
++// 0-slow recovery 2nd burst access 1st access delay 16-bit bus non-burst(0), sram(1), 4cycle(2), 8cycle(3), VLIO(4)
++#define CS0_MSC (1<<15)+ (1<<12)+ (7<<8)+ ((7-1)<<4)+ 0
++#define CS1_MSC (1<<15)+(((tEHEL+1)>>1)<<12)+((tAPA-1)<<8)+ (RDFSelect<<4)+ (BurstSelect) //fast device
++#else
++#define CS0_MSC (1<<15)+(((tEHEL+1)>>1)<<12)+((tAPA-1)<<8)+ (RDFSelect<<4)+ (BurstSelect) //fast device
++#define CS1_MSC (1<<15)+ (3<<12)+ (2<<8)+ ((3-1)<<4)+ (1<<3) + 4 //SMC chip
++//#define CS1_MSC (1<<15)+ (6<<12)+ ((11-1)<<8)+ ((4-1)<<4)+ (1<<3) + 4 //SMC chip
++#endif
++
++.macro InitCS0_CS1 rBase,rTemp
++ BigMov \rBase,MEMORY_CONTROL_BASE
++ ldr \rTemp,[\rBase,#BOOT_DEF]
++ tst \rTemp,#1 //bit 0 - 1 means 16 bit mode
++ BigMov \rTemp,(CS0_MSC)|((CS1_MSC)<<16)
++/////// BigMov \rTemp,0x7ff07ff0
++ orrne \rTemp,\rTemp,#1<<3 //16 bit bus
++ str \rTemp,[\rBase,#MSC0]
++.endm
++
++
++.macro InitMemory rBase,rTemp,rTemp2
++ cmp pc,#MEM_START
++ bcs 92f //exit if running from ram
++#if 0 //1 to force smaller memory
++ subs \rTemp,\rTemp,\rTemp //set carry flag
++#endif
++
++1:
++ InitRam \rBase, \rTemp //out: \rBase - MEMORY_CONTROL_BASE
++
++#if (PLATFORM_TYPE==BOUNDARY_OLD_BOARD)
++#define CHIP_MODE 0 //don't use VIO_READY
++#else
++#define CHIP_MODE 4 //gp18 is VIO_READY
++#endif
++
++// RRR RDN RDF RBW RTX
++// gap between Address to
++// 1-fast chip selects data valid
++// 0-slow recovery 2nd burst access 1st access delay 16-bit bus non-burst(0), sram(1), 4cycle(2), 8cycle(3), VLIO(4)
++#if 1
++#define CS2_MSC (1<<15)+ (4<<12)+ ((6-2)<<8)+ ((4-1)<<4)+ (1<<3) + CHIP_MODE //for USB dma
++//#define CS2_MSC (1<<15)+ (7<<12)+ ((16-1)<<8)+ ((16-1)<<4)+ (1<<3) + CHIP_MODE //for USB dma
++
++// vlio min 2 vlio min 3
++#if (PLATFORM_TYPE==NEON) || (PLATFORM_TYPE==NEONB)
++#define CS3_MSC (1<<15)+ (1<<12)+ (2<<8)+ ((4-1)<<4)+ (0<<3) + 4 //SM501
++#define CS4_MSC (1<<15)+ (3<<12)+ (2<<8)+ ((4-1)<<4)+ (0<<3) + 4 //SMC chip
++#else
++#if (PLATFORM_TYPE==HALOGEN)
++#define CS3_MSC (1<<15)+ (1<<12)+ (2<<8)+ ((4-1)<<4)+ (0<<3) + 4 //NC
++#define CS4_MSC (1<<15)+ (3<<12)+ (2<<8)+ ((5-1)<<4)+ (0<<3) + 4 //SMC chip
++#else
++#define CS3_MSC (1<<15)+ (4<<12)+ ((6-2)<<8)+ ((4-1)<<4)+ (1<<3) + CHIP_MODE //for USB dma
++//#define CS3_MSC (1<<15)+ (7<<12)+ ((16-1)<<8)+ ((16-1)<<4)+ (1<<3) + CHIP_MODE //for USB dma
++#define CS4_MSC (1<<15)+ (6<<12)+ ((11-1)<<8)+ ((4-1)<<4)+ (1<<3) + CHIP_MODE //for USB IO
++#endif
++#endif
++
++#define CS5_MSC (0<<15)+ (7<<12)+ ((8-1)<<8)+ ((8-1)<<4)+ (1<<3) + (0) //for USB IO delay after CMD write
++#else
++#define CS2_MSC (1<<15)+ (7<<12)+ ((16-1)<<8)+ ((16-1)<<4)+ (1<<3) + CHIP_MODE //for USB dma
++#define CS3_MSC (1<<15)+ (7<<12)+ ((16-1)<<8)+ ((16-1)<<4)+ (1<<3) + CHIP_MODE //for USB dma
++#define CS4_MSC (1<<15)+ (7<<12)+ ((16-1)<<8)+ ((16-1)<<4)+ (1<<3) + CHIP_MODE //for USB IO
++#define CS5_MSC (0<<15)+ (7<<12)+ ((16-1)<<8)+ ((16-1)<<4)+ (1<<3) + (0) //for USB IO delay after CMD write
++#endif
++ BigMov \rTemp,(CS2_MSC)|((CS3_MSC)<<16)
++ str \rTemp,[\rBase,#MSC1]
++ BigMov \rTemp,(CS4_MSC)|((CS5_MSC)<<16)
++ str \rTemp,[\rBase,#MSC2]
++
++
++
++#define PCMCIA_MEM_SETUP_ADDRESS 5 //0-127
++#define PCMCIA_MEM_COMMAND_CODE 3 //0-31
++#define PCMCIA_MEM_HOLD_ADDRESS 2 //0-63
++ BigMov \rTemp,(PCMCIA_MEM_HOLD_ADDRESS<<14)+(PCMCIA_MEM_COMMAND_CODE<<7)+(PCMCIA_MEM_SETUP_ADDRESS<<0)
++ str \rTemp,[\rBase,#MCMEM0]
++ str \rTemp,[\rBase,#MCMEM1]
++#define PCMCIA_ATT_SETUP_ADDRESS 5 //0-127
++#define PCMCIA_ATT_COMMAND_CODE 3 //0-31
++#define PCMCIA_ATT_HOLD_ADDRESS 2 //0-63
++ BigMov \rTemp,(PCMCIA_ATT_HOLD_ADDRESS<<14)+(PCMCIA_ATT_COMMAND_CODE<<7)+(PCMCIA_ATT_SETUP_ADDRESS<<0)
++ str \rTemp,[\rBase,#MCATT0]
++ str \rTemp,[\rBase,#MCATT1]
++#define PCMCIA_IO_SETUP_ADDRESS 5 //0-127
++#define PCMCIA_IO_COMMAND_CODE 3 //0-31
++#define PCMCIA_IO_HOLD_ADDRESS 2 //0-63
++ BigMov \rTemp,(PCMCIA_IO_HOLD_ADDRESS<<14)+(PCMCIA_IO_COMMAND_CODE<<7)+(PCMCIA_IO_SETUP_ADDRESS<<0)
++ str \rTemp,[\rBase,#MCIO0]
++ str \rTemp,[\rBase,#MCIO1]
++ mov \rTemp,#2
++ str \rTemp,[\rBase,#MECR]
++
++ CheckRam \rBase, \rTemp, \rTemp2
++ cmpne \rTemp,#0x0 //set carry flag, keep z-0 (memory size!=0)
++ bne 1b
++92:
++.endm
++
++// *******************************************************************************************
++// *******************************************************************************************
++// *******************************************************************************************
++// *******************************************************************************************
++#define CKEN_PWM0 0
++#define CKEN_PWM1 1
++#define CKEN_AC97 2
++#define CKEN_SSP 3
++#define CKEN_HWUART 4
++#define CKEN_STUART 5
++#define CKEN_FFUART 6
++#define CKEN_BTUART 7
++#define CKEN_I2S 8
++#define CKEN_USB 11
++#define CKEN_MMC 12
++#define CKEN_FICP 13
++#define CKEN_I2C 14
++#define CKEN_LCD 16
++
++#if (PLATFORM_TYPE==NEON) || (PLATFORM_TYPE==BD2003) || (PLATFORM_TYPE==BOUNDARY_OLD_BOARD) || (PLATFORM_TYPE==OLD_GAME_CONTROLLER) || (PLATFORM_TYPE==HALOGEN)
++#define __ENABLED_BTUART_MASK (1<<CKEN_BTUART)
++#define __ENABLED_STUART_MASK (1<<CKEN_STUART)
++#endif
++
++#if (PLATFORM_TYPE==BD2003) || (PLATFORM_TYPE==BOUNDARY_OLD_BOARD) || (PLATFORM_TYPE==OLD_GAME_CONTROLLER) || (PLATFORM_TYPE==HALOGEN)
++#define __ENABLED_LCD_MASK (1<<CKEN_LCD)
++#endif
++
++#ifndef __ENABLED_BTUART_MASK
++#define __ENABLED_BTUART_MASK 0
++#endif
++
++#ifndef __ENABLED_STUART_MASK
++#define __ENABLED_STUART_MASK 0
++#endif
++
++#ifndef __ENABLED_LCD_MASK
++#define __ENABLED_LCD_MASK 0
++#endif
++
++.macro InitIC_Clocks rBase,rTemp
++ BigMov \rBase,IC_BASE
++ mov \rTemp,#0
++ str \rTemp,[\rBase,#ICMR] //disable all interrupts
++
++ BigMov \rBase,CLK_MANAGER_BASE
++#if (PLATFORM_TYPE==HALOGEN)
++#define CKEN_MEMORY_CONTROLLER 22
++#define CKEN_OS_TIMER 9
++
++#define CCCR_L_BIT 0
++#define CCCR_2N_BIT 7
++#define CCCR_A_BIT 25
++
++#define CLKCFG_TURBO_BIT 0
++#define CLKCFG_FREQUENCY_CHANGE_BIT 1
++#define CLKCFG_HALF_TURBO_BIT 2
++#define CLKCFG_FAST_BUS_BIT 3
++
++#if (CPU_CLOCK==104) //13*8 = 104MHz
++#define CCCR_2N 2
++#define CCCR_L 8
++#define CCCR_A 0
++#define CLKCFG_TURBO 0
++#define CLKCFG_FAST_BUS 0
++#else
++#if (CPU_CLOCK==208) //13*16 = 208MHz
++#define CCCR_2N 2
++#define CCCR_L 16
++#define CCCR_A 0
++#define CLKCFG_TURBO 0
++#define CLKCFG_FAST_BUS 0
++#else
++#if (CPU_CLOCK==312) //312MHz
++#define CCCR_2N 3
++#define CCCR_L 16
++#define CCCR_A 0
++#define CLKCFG_TURBO 1
++#define CLKCFG_FAST_BUS 0
++#else
++#if (CPU_CLOCK==416) //416MHz
++#define CCCR_2N 4
++#define CCCR_L 16
++#define CCCR_A 0
++#define CLKCFG_TURBO 1
++#define CLKCFG_FAST_BUS 1
++#else
++#if (CPU_CLOCK==520) //520MHz
++#define CCCR_2N 5
++#define CCCR_L 16
++#define CCCR_A 0
++#define CLKCFG_TURBO 1
++#define CLKCFG_FAST_BUS 1
++#else
++#if (CPU_CLOCK==624) //624MHz
++#define CCCR_2N 6
++#define CCCR_L 16
++#define CCCR_A 0
++#define CLKCFG_TURBO 1
++#define CLKCFG_FAST_BUS 1
++
++#else
++#warning CPU_CLOCK selection not made
++#endif
++#endif
++#endif
++#endif
++#endif
++#endif
++ BigMov \rTemp,(CCCR_L<<CCCR_L_BIT)+(CCCR_2N<<CCCR_2N_BIT)+(CCCR_A<<CCCR_A_BIT)
++ str \rTemp,[\rBase,#CCCR]
++
++ BigMov \rTemp,(1<<CKEN_OS_TIMER)+(1<<CKEN_MEMORY_CONTROLLER)+(1<<CKEN_FFUART)+__ENABLED_BTUART_MASK+__ENABLED_STUART_MASK+__ENABLED_LCD_MASK
++ str \rTemp,[\rBase,#CKEN]
++
++#else
++#define tRP 20
++#define tRCD 20
++#define tRAS 45 //45 ns
++#define tRC 65
++// CRYSTALns 10000000/ 36864 //271ns
++
++#define LSelect 1 //1 : *27 = 10.0469 ns memory clk time, 99.53 MHz
++ // tRP_clk = tRCD_clk= 1.99066 -> 2 clks
++ // tRAS_clk= 4.47899 -> 5 clks
++ // tRC_clk= 6.46966 -> 7 clks
++ //2 : *32 = 8.47711 ns, 117.96 MHz
++ // tRP_clk = tRCD_clk= 2.35929 -> 3 clks
++ // tRAS_clk=5.30841 -> 6
++ // tRC_clk =7.66771 -> 8 clks
++ //3 : *36 = 7.5352 ns, 132.71 MHz
++ // tRP_clk = tRCD_clk= 2.65421 -> 3 clks
++ // tRAS_clk=5.97197 -> 6
++ // tRC_clk = 8.62618 -> 9 clks
++ //4 : *40 = 6.78168ns, 147.46 MHz
++ // tRP_clk = tRCD_clk= 2.94912 -> 3 clks
++ // tRAS_clk=6.63522 -> 7
++ // tRC_clk = 9.58465 -> 10 clks
++ //5 : *45 = 6.02816ns, 165.89 MHz
++ // tRP_clk = tRCD_clk= 3.31776 -> 4 clks
++ // tRAS_clk=7.46496 -> 8
++ // tRC_clk = 10.7827 -> 11 clks
++//MSelect
++//1 : *1
++//2 : *2
++
++//NSelect
++//2 : *1;
++//3 : *1.5;
++//4 : *2;
++//6 : *3
++
++#if (CPU_CLOCK==100)
++#define MSelect 1 //1 : *1 100MHz
++#define NSelect 4 //4 : *2; turbo 200 MHZ
++#define FCS_MASK 2 // turbo off
++#else
++#if (CPU_CLOCK==200)
++#define MSelect 2 //2 : *2 200 MHz
++#define NSelect 3 //3 : *1.5; turbo 300 MHZ
++#define FCS_MASK 2 // turbo off
++#else
++#if (CPU_CLOCK==300)
++#define MSelect 2 //2 : *2 200 MHz
++#define NSelect 3 //3 : *1.5; turbo 300 MHZ
++#define FCS_MASK 3 // turbo on
++#else
++#if (CPU_CLOCK==400)
++
++#if 0 //only pxa255 runs with 200Mhz internal bus, pxa250 doesn't
++#define MSelect 2 //2 : *2 200 MHz
++#define NSelect 4 //4 : *2; turbo 400 MHZ
++#define FCS_MASK 3 // turbo on
++#else
++#define MSelect 3 //2 : *4 400 MHz
++#define NSelect 2 //4 : *1; turbo 400 MHZ
++#define FCS_MASK 2 // turbo off
++#endif
++
++#else
++//////#WARNING CPU_CLOCK selection not made
++#endif
++#endif
++#endif
++#endif
++
++ BigMov \rTemp,(NSelect<<7)+(MSelect<<5)+(LSelect)
++ str \rTemp,[\rBase,#CCCR]
++
++ BigMov \rTemp,(1<<CKEN_FFUART)+__ENABLED_BTUART_MASK+__ENABLED_STUART_MASK+__ENABLED_LCD_MASK
++ str \rTemp,[\rBase,#CKEN]
++#endif //not HALOGEN
++ mov \rTemp,#0 //disable 32.768khz oscillator
++// mov \rTemp,#2 //enable 32.768khz oscillator
++ str \rTemp,[\rBase,#OSCC]
++.endm
++
++.macro InitChangeCPUSpeed rTemp
++#if (PLATFORM_TYPE==HALOGEN)
++ mov \rTemp,#(CLKCFG_FAST_BUS<<CLKCFG_FAST_BUS_BIT)+(CLKCFG_TURBO<<CLKCFG_TURBO_BIT)+(1<<CLKCFG_FREQUENCY_CHANGE_BIT)
++ CP14_CCLKCFG mcr,\rTemp
++#else
++ mov \rTemp,#FCS_MASK
++ CP14_CCLKCFG mcr,\rTemp
++#endif
++.endm
++
++// *******************************************************************************************
++// *******************************************************************************************
++
++.macro InitUART rBase,rTemp,uartaddr,baudrate
++ BigMov \rBase,\uartaddr
++
++ mov \rTemp,#0x83 //DLAB, 8-bit characters
++ str \rTemp,[\rBase,#UART_LCR]
++ mov \rTemp,#(14745600/((\baudrate)<<4))&0xff
++ str \rTemp,[\rBase,#UART_DLL]
++ mov \rTemp,#((14745600/((\baudrate)<<4))>>8)
++ str \rTemp,[\rBase,#UART_DLH]
++
++ mov \rTemp,#3 //8-bit characters
++ str \rTemp,[\rBase,#UART_LCR]
++
++ mov \rTemp,#0xc1 //enable fifo, 32 byte level
++ str \rTemp,[\rBase,#UART_FCR]
++
++ mov \rTemp,#0x40 //UUE- UART unit enable
++ str \rTemp,[\rBase,#UART_IER]
++.endm
++.macro InitGPIO rBase,rTemp
++ BigMov \rBase,GPIO_BASE
++
++ BigMov \rTemp,~SRVAL0
++ str \rTemp,[\rBase,#GPCR0]
++ mvn \rTemp,\rTemp
++ str \rTemp,[\rBase,#GPSR0]
++
++ BigMov \rTemp,~SRVAL32
++ str \rTemp,[\rBase,#GPCR1]
++ mvn \rTemp,\rTemp
++ str \rTemp,[\rBase,#GPSR1]
++
++ BigMov \rTemp,~SRVAL64
++ str \rTemp,[\rBase,#GPCR2]
++ mvn \rTemp,\rTemp
++ str \rTemp,[\rBase,#GPSR2]
++#if (PLATFORM_TYPE==HALOGEN)
++ BigMov \rTemp,~SRVAL96
++ str \rTemp,[\rBase,#GPCR3]
++ mvn \rTemp,\rTemp
++ str \rTemp,[\rBase,#GPSR3]
++#endif
++////////
++ BigMov \rTemp,DRVAL0
++ str \rTemp,[\rBase,#GPDR0]
++
++ BigMov \rTemp,DRVAL32
++ str \rTemp,[\rBase,#GPDR1]
++
++ BigMov \rTemp,DRVAL64
++ str \rTemp,[\rBase,#GPDR2]
++#if (PLATFORM_TYPE==HALOGEN)
++ BigMov \rTemp,DRVAL96
++ str \rTemp,[\rBase,#GPDR3]
++#endif
++////////
++ BigMov \rTemp,AFVAL0
++ str \rTemp,[\rBase,#GAFR0_L]
++ BigMov \rTemp,AFVAL16
++ str \rTemp,[\rBase,#GAFR0_U]
++
++ BigMov \rTemp,AFVAL32
++ str \rTemp,[\rBase,#GAFR1_L]
++ BigMov \rTemp,AFVAL48
++ str \rTemp,[\rBase,#GAFR1_U]
++
++ BigMov \rTemp,AFVAL64
++ str \rTemp,[\rBase,#GAFR2_L]
++ BigMov \rTemp,AFVAL80
++ str \rTemp,[\rBase,#GAFR2_U]
++#if (PLATFORM_TYPE==HALOGEN)
++ BigMov \rTemp,AFVAL96
++ str \rTemp,[\rBase,#GAFR3_L]
++ BigMov \rTemp,AFVAL112
++ str \rTemp,[\rBase,#GAFR3_U]
++#endif
++ BigMov \rBase,PWR_MANAGER_BASE
++ mov \rTemp,#0x30
++ str \rTemp,[\rBase,#PSSR]
++.endm
++
++
++
++.macro TransMacro val
++ BigMov r12,UART_BASE
++91:
++ BigMov r0,\val
++ bl Transmit
++ b 91b
++.endm
++// *******************************************************************************************
++.macro InitMMU rBase,rTemp
++// mov r0,#PSR_NOINTS_MASK+PSR_MODE_SVC
++// msr cpsr_c,r0
++// ********************************************************************
++// Disable the MMU and gang regardless of why we are here.
++ BigMov \rBase,0x2001 //; enable access to all coprocessors
++ CP15_CP_ACCESS mcr,\rBase
++ CPWAIT \rBase
++
++ mov \rBase,#0x00000078 //; get a zero to turn things off (must write bits[6:3] as 1's)
++ CP15_CONTROL mcr,\rBase //; Turn Off MMU, I&D Caches, WB.
++ CPWAIT \rBase
++
++ mov \rBase,#0x00000000 //; get a zero to turn things off
++ cmp pc,#MEM_START
++ CP15_TLB_INVAL_BOTH mcr,\rBase //; flush (invalidate) I/D tlb's
++ CP15_CF_INVAL_BTB mcr,\rBase //invalidate Branch target buffer
++ CP15_CF_INVAL_D mcr,\rBase
++ CP15_CF_INVAL_I mcrcs,\rBase //I might be running from cache only, invalidate if in ram
++ CP15_CF_DRAIN mcr,\rBase //; Drain the write buffer
++ nop
++ nop
++ nop
++ mvn r0, #0 //; grant manager access to all domains
++ CP15_DACR mcr,\rBase
++.endm
++
++//out rTemp1 reset reason
++.macro InitPWR rBase,rTemp1,rTemp2
++ BigMov \rBase,PWR_MANAGER_BASE
++// ********************************************************************
++ ldr \rTemp1,[\rBase,#RCSR] // Read & Init Reset Cause bits in RCSR.
++ and \rTemp1,\rTemp1,#RCSR_MASK // extract the reset cause bits
++ str \rTemp1,[\rBase,#RCSR] // clear the reset cause bits (they're sticky)
++// ********************************************************************
++// Read and store PSSR, too - it will be reset later, after GPIOs are initialized.
++// Unclear when we'll need this information, but don't throw a good status away.
++// ldr \rTemp2, [\rBase,#PSSR]
++// extract the reset cause bits
++// and \rTemp2,\rTemp2,#PSSR_MASK //; r12 now holds the conditioned PSSR
++// orr \rTemp1,\rTemp1,\rTemp2,lsl #16 //; R10 now has RCSR in lower half and PSSR in upper.
++// ********************************************************************
++// Reasons for being here:
++// 1) Hard Reset
++// 2) Wake from Sleep
++// 3) GPIO Reset
++// 4) Watchdog Reset
++// 5) Eboot Handoff
++// If Sleep_Reset: reinit all but RTC, PWRMAN, CLKS (except cp14)... so reinit: OST, INTC, GPIO
++// If GPIO_Reset: reinit all but MEMC.Config, RTC, CLKS (except cp14)... so reinit: treat like sleep
++// If Watchdog_Reset: reinit all but RTC.RTTR, CLK.OSCC... so reinit: treat like a hard reset, minus OSCC and RTTR init.
++// If Hard_Reset: reinit all
++.endm
++
++// *******************************************************************************************
++// *******************************************************************************************
++ .list
+diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxaMacro3.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaMacro3.h
+--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxaMacro3.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaMacro3.h 2007-08-11 21:07:21.000000000 +0200
+@@ -0,0 +1,74 @@
++#include "pxaLcd2.h"
++#include "pxaMacro2.h"
++.macro DEFINE_SCREEN_WIDTH xres,xsyncWidth,xbegin,xend, yres,ysyncWidth,ybegin,yend, enable,unscramble,rotate,active,bpp,clkdiv,type
++ .ifdef __ARMASM
++ GBLA SCREEN_WIDTH
++ .endif
++ .set SCREEN_WIDTH,\xres
++.endm
++
++.macro DEFINE_SCREEN_HEIGHT xres,xsyncWidth,xbegin,xend, yres,ysyncWidth,ybegin,yend, enable,unscramble,rotate,active,bpp,clkdiv,type
++ .ifdef __ARMASM
++ GBLA SCREEN_HEIGHT
++ .endif
++ .set SCREEN_HEIGHT,\yres
++.endm
++
++ DEFINE_SCREEN_WIDTH DEF_P
++ DEFINE_SCREEN_HEIGHT DEF_P
++
++.macro CR0_INIT_VAL reg,xres,xsyncWidth,xbegin,xend, yres,ysyncWidth,ybegin,yend, enable,unscramble,rotate,active,bpp,clkdiv,type
++ BigMov \reg,(\enable<<CR0_ENABLE)+(1<<CR0_IM_DISABLE_DONE)+(1<<CR0_IM_START_OF_FRAME)+\
++ (1<<CR0_IM_INPUT_FIFO_UNDERRUN)+(1<<CR0_IM_END_OF_FRAME)+(\active<<CR0_ACTIVE_SELECT)+\
++ (1<<CR0_IM_LCD_QUICK_DISABLE)+(1<<CR0_IM_BRANCH)+(1<<CR0_IM_OUTPUT_FIFO_UNDERRUN)
++.endm
++
++.macro CR1_INIT_VAL reg,xres,xsyncWidth,xbegin,xend, yres,ysyncWidth,ybegin,yend, enable,unscramble,rotate,active,bpp,clkdiv,type
++ BigMov \reg,((\xres-1)<<CR1_PIXELS_PER_LINE)+((\xsyncWidth-1)<<CR1_HORIZONTAL_SYNC_PULSE_WIDTH)+\
++ ((\xend-1)<<CR1_END_OF_LINE_WAIT)+((\xbegin-1)<<CR1_BEGINNING_OF_LINE_WAIT)
++.endm
++
++.macro CR2_INIT_VAL reg,xres,xsyncWidth,xbegin,xend, yres,ysyncWidth,ybegin,yend, enable,unscramble,rotate,active,bpp,clkdiv,type
++ BigMov \reg,((\yres-1)<<CR2_LINES_PER_PANEL)+((\ysyncWidth-1)<<CR2_VERTICAL_SYNC_PULSE_WIDTH)+\
++ (\yend<<CR2_END_OF_FRAME_WAIT)+(\ybegin<<CR2_BEGINNING_OF_FRAME_WAIT)
++.endm
++
++.macro CR3_INIT_VAL reg,xres,xsyncWidth,xbegin,xend, yres,ysyncWidth,ybegin,yend, enable,unscramble,rotate,active,bpp,clkdiv,type
++//LCD Clock is same as memory clock
++ BigMov \reg,(\clkdiv<<CR3_PCLK_DIVISOR)+((256-1)<<CR3_ACBIAS_TOGGLE)+\
++ (0<<CR3_API)+(0<<CR3_FCLK_POLARITY)+(0<<CR3_LCLK_POLARITY)+\
++ (1<<CR3_PCLK_POLARITY)+(0<<CR3_BIAS_POLARITY)+\
++ (BPP_FORMAT<<CR3_BITS_PER_PIXEL)+(0<<CR3_DOUBLE_PCLK)+(PDFOR<<CR3_PDFOR)
++.endm
++
++#define TMEDS_INIT_VAL (0xaa<<TMEDS_BLUE)+(0x55<<TMEDS_GREEN)+(0x00<<TMEDS_RED)
++#define TMEDC_INIT_VAL (1<<TMEDC_MATRIX2_SELECT)+(3<<TMEDC_RESERVED)+(5<<TMEDC_HORIZONTAL_BEAT_SUPPRESSION)+(4<<TMEDC_VERTICAL_BEAT_SUPPRESSION)+(1<<TMEDC_FRAME_NUMBER_ADJUST_EN)+(1<<TMEDC_COLOR_OFFSET_ADJUST_EN)+(1<<TMEDC_FRAME_NUMBER_ADJUST_MATRIX2)+(1<<TMEDC_COLOR_OFFSET_ADJUST_MATRIX2)
++
++
++.macro InitLCD rBase,rTemp,rDescript
++
++ BigMov \rBase,LCD_CONTROL_BASE
++
++ CR1_INIT_VAL \rTemp,DEF_P
++ str \rTemp,[\rBase,#LCD_CR1]
++
++ CR2_INIT_VAL \rTemp,DEF_P
++ str \rTemp,[\rBase,#LCD_CR2]
++
++ CR3_INIT_VAL \rTemp,DEF_P
++ str \rTemp,[\rBase,#LCD_CR3]
++
++ BigMov \rTemp,0
++ str \rTemp,[\rBase,#LCD_FBR0]
++ str \rTemp,[\rBase,#LCD_FBR1]
++
++ BigMov \rTemp,TMEDS_INIT_VAL
++ str \rTemp,[\rBase,#LCD_TMEDS]
++ BigMov \rTemp,TMEDC_INIT_VAL
++ str \rTemp,[\rBase,#LCD_TMEDC]
++
++ str \rDescript,[\rBase,#LCD_FDADR0]
++
++ CR0_INIT_VAL \rTemp,DEF_P
++ str \rTemp,[\rBase,#LCD_CR0]
++.endm
+diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxaMacro.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaMacro.h
+--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxaMacro.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxaMacro.h 2007-08-11 21:07:21.000000000 +0200
+@@ -0,0 +1,343 @@
++#include "pxa250Base.h"
++#include "pxaHardware.h"
++#include "BigMacro.h"
++ .nolist
++
++//CP14 registers
++.macro CP14_PMNC ins,rx
++ \ins p14,0,\rx,c0,c0,0
++.endm
++.macro CP14_CCNT ins,rx
++ \ins p14,0,\rx,c1,c0,0
++.endm
++.macro CP14_PMN0 ins,rx
++ \ins p14,0,\rx,c2,c0,0
++.endm
++.macro CP14_PMN1 ins,rx
++ \ins p14,0,\rx,c3,c0,0
++.endm
++.macro CP14_CCLKCFG ins,rx
++ \ins p14,0,\rx,c6,c0,0
++.endm
++.macro CP14_PWRMODE ins,rx
++ \ins p14,0,\rx,c7,c0,0
++.endm
++.macro CP14_TX ins,rx
++ \ins p14,0,\rx,c8,c0,0
++.endm
++.macro CP14_RX ins,rx
++ \ins p14,0,\rx,c9,c0,0
++.endm
++.macro CP14_DCSR ins,rx
++ \ins p14,0,\rx,c10,c0,0 //debug control and status register
++.endm
++.macro CP14_TBREG ins,rx
++ \ins p14,0,\rx,c11,c0,0 //trace buffer register
++.endm
++.macro CP14_CHKPT0 ins,rx
++ \ins p14,0,\rx,c12,c0,0 //checkpoint register 0
++.endm
++.macro CP14_CHKPT1 ins,rx
++ \ins p14,0,\rx,c13,c0,0 //checkpoint register 1
++.endm
++.macro CP14_TXRXCTRL ins,rx
++ \ins p14,0,\rx,c14,c0,0
++.endm
++
++
++//CP15 registers
++.macro CP15_ID ins,rx
++ \ins p15,0,\rx,c0,c0,0
++.endm
++.macro CP15_CACHETYPE ins,rx
++ \ins p15,0,\rx,c0,c0,1
++.endm
++.macro CP15_CONTROL ins,rx
++ \ins p15,0,\rx,c1,c0,0
++.endm
++.macro CP15_AUXCONTROL ins,rx
++ \ins p15,0,\rx,c1,c0,1
++.endm
++.macro CP15_TTBR ins,rx
++ \ins p15,0,\rx,c2,c0,0 //translation table base
++.endm
++.macro CP15_DACR ins,rx
++ \ins p15,0,\rx,c3,c0,0 //domain access control register
++.endm
++.macro CP15_FSR ins,rx
++ \ins p15,0,\rx,c5,c0,0 //fault status register
++.endm
++.macro CP15_FAR ins,rx
++ \ins p15,0,\rx,c6,c0,0 //fault address register
++.endm
++
++.macro CP15_CF_ALLOC_LINE ins,rx
++ \ins p15,0,\rx,c7,c2,5 //allocate line in data cache
++.endm
++.macro CP15_CF_INVAL_I ins,rx
++ \ins p15,0,\rx,c7,c5,0 //invalidate instruction cache
++.endm
++.macro CP15_CF_INVAL_ILINE ins,rx
++ \ins p15,0,\rx,c7,c5,1
++.endm
++.macro CP15_CF_INVAL_BTB ins,rx
++ \ins p15,0,\rx,c7,c5,6 //invalidate Branch target buffer
++.endm
++.macro CP15_CF_INVAL_D ins,rx
++ \ins p15,0,\rx,c7,c6,0
++.endm
++.macro CP15_CF_INVAL_DLINE ins,rx
++ \ins p15,0,\rx,c7,c6,1
++.endm
++.macro CP15_CF_INVAL_BOTH ins,rx
++ \ins p15,0,\rx,c7,c7,0 //invalidate instruction & data cache & BTB
++.endm
++.macro CP15_CF_CLEAN_DLINE ins,rx
++ \ins p15,0,\rx,c7,c10,1
++.endm
++.macro CP15_CF_DRAIN ins,rx
++ \ins p15,0,\rx,c7,c10,4
++.endm
++
++.macro CP15_TLB_INVAL_I ins,rx
++ \ins p15,0,\rx,c8,c5,0
++.endm
++.macro CP15_TLB_INVAL_IENTRY ins,rx
++ \ins p15,0,\rx,c8,c5,1
++.endm
++.macro CP15_TLB_INVAL_D ins,rx
++ \ins p15,0,\rx,c8,c6,0
++.endm
++.macro CP15_TLB_INVAL_DENTRY ins,rx
++ \ins p15,0,\rx,c8,c6,1
++.endm
++.macro CP15_TLB_INVAL_BOTH ins,rx
++ \ins p15,0,\rx,c8,c7,0
++.endm
++
++.macro CP15_CF_LOCK_ILINE ins,rx
++ \ins p15,0,\rx,c9,c1,0 //mva to fetch and lock
++.endm
++.macro CP15_CF_UNLOCK_I ins,rx
++ \ins p15,0,\rx,c9,c1,1 //unlock all lines
++.endm
++.macro CP15_CF_LOCK_D_CSR ins,rx
++ \ins p15,0,\rx,c9,c2,0
++.endm
++.macro CP15_CF_UNLOCK_D ins,rx
++ \ins p15,0,\rx,c9,c2,1 //unlock all lines in data cache
++.endm
++
++.macro CP15_TLB_LOCK_IENTRY ins,rx
++ \ins p15,0,\rx,c10,c4,0
++.endm
++.macro CP15_TLB_UNLOCK_I ins,rx
++ \ins p15,0,\rx,c10,c4,1
++.endm
++.macro CP15_TLB_LOCK_DENTRY ins,rx
++ \ins p15,0,\rx,c10,c8,0
++.endm
++.macro CP15_TLB_UNLOCK_D ins,rx
++ \ins p15,0,\rx,c10,c8,1
++.endm
++
++.macro CP15_PID ins,rx
++ \ins p15,0,\rx,c13,c0,0
++.endm
++
++.macro CP15_DBR0 ins,rx
++ \ins p15,0,\rx,c14,c0,0 //Data Breakpoint address register 0
++.endm
++.macro CP15_DBR1 ins,rx
++ \ins p15,0,\rx,c14,c3,0 //Data Breakpoint address/mask register 1
++.endm
++.macro CP15_DBCON ins,rx
++ \ins p15,0,\rx,c14,c4,0 //Data Breakpoint control register
++.endm
++.macro CP15_IBCR0 ins,rx
++ \ins p15,0,\rx,c14,c8,0 //Instruction Breakpoint Control Register 0
++.endm
++.macro CP15_IBCR1 ins,rx
++ \ins p15,0,\rx,c14,c9,0 //Instruction Breakpoint Control Register 1
++.endm
++
++.macro CP15_CP_ACCESS ins,rx
++ \ins p15,0,\rx,c15,c1,0 //Coprocessor access register, set bit n to enable access to coprocessor n
++.endm
++
++
++.macro CPWAIT dest
++ CP15_ID mrc,\dest //read some register in CP15
++ mov \dest,\dest //wait for the read to complete
++ sub pc,pc,#4 //branch to the next instruction, flushing the instruction pipeline
++.endm
++
++// *******************************************************************************************
++// *******************************************************************************************
++// *******************************************************************************************
++// *******************************************************************************************
++// *******************************************************************************************
++// ************************************************************************************************
++// *******************************************************************************************
++// *******************************************************************************************
++// *******************************************************************************************
++
++#define numColumnAddrBits 9
++#define numBankAddrBits 2
++#define ClkSelect 1 //0 : tRP = 2, tRCD = 1, tRAS = 3, tRC = 4
++ //1 : tRP = 2, tRCD = 2, tRAS = 5, tRC = 8
++ //2 : tRP = 3, tRCD = 3, tRAS = 7, tRC = 10
++ //3 : tRP = 3, tRCD = 3, tRAS = 7, tRC = 11
++//64 meg option
++#define M64_numRowAddrBits 13 //for k4s561632a
++#define M64_SA1111_mask 0 //(1<<12)
++#define M64_DRI_cnt (((99530*64)>>M64_numRowAddrBits)>>5) //(# of cycles/ms * # of ms for entire refresh period)/ # of rows/refresh period /32
++#define M64_MDCNFG_VAL 1+((numColumnAddrBits-8)<<3)+((M64_numRowAddrBits-11)<<5)+((numBankAddrBits-1)<<7)+(ClkSelect<<8)+(1<<11)+(M64_SA1111_mask) //DLATCH0, latch return data with return clock
++#define M64_MDREFR_VAL (1<<16)+(1<<15)+(M64_DRI_cnt&0xfff) //don't set bit 20: APD (buggy), bit 16: K1RUN, 15:E1PIN
++//#define M64_MDREFR_VAL (1<<20)+(1<<16)+(1<<15)+(M64_DRI_cnt&0xfff) //20: APD, bit 16: K1RUN, 15:E1PIN
++// 13 9 2 2 (4bytes per address)=2**26=64 MB
++#define M64_MEM_SIZE (1<<(M64_numRowAddrBits+numColumnAddrBits+numBankAddrBits+2))
++#define M64_MEM_END ((MEM_START)+M64_MEM_SIZE)
++
++//32 meg option
++#define M32_numRowAddrBits 12 //for MT48LC8M16A2 - 75 B
++#define M32_SA1111_mask 0
++#define M32_DRI_cnt (((99530*64)>>M32_numRowAddrBits)>>5) //(# of cycles/ms * # of ms for entire refresh period)/ # of rows/refresh period /32
++#define M32_MDCNFG_VAL 1+((numColumnAddrBits-8)<<3)+((M32_numRowAddrBits-11)<<5)+((numBankAddrBits-1)<<7)+(ClkSelect<<8)+(1<<11)+(M32_SA1111_mask) //DLATCH0, latch return data with return clock
++#define M32_MDREFR_VAL (1<<16)+(1<<15)+(M32_DRI_cnt&0xfff) //don't set bit 20: APD (buggy), bit 16: K1RUN, 15:E1PIN
++// 12 9 2 2 (4bytes per address)=2**25=32 MB
++#define M32_MEM_SIZE (1<<(M32_numRowAddrBits+numColumnAddrBits+numBankAddrBits+2))
++#define M32_MEM_END ((MEM_START)+M32_MEM_SIZE)
++// *******************************************************************************************
++//out: rTemp - memory size
++.macro CalcMemSize rBase,rTemp,mem_control_base
++ BigMov \rBase,\mem_control_base
++ ldr \rTemp,[\rBase,#MDCNFG]
++ movs \rTemp,\rTemp,LSR #2+1 //bit 2 - 1 means 16 bit mode, 0 means 32 bit mode, mov to carry flag
++ tst \rTemp,#1<<(5-3) //is number of row address bits 12 or 13 ?
++ moveq \rTemp,#M64_MEM_SIZE
++ movne \rTemp,#M32_MEM_SIZE
++ movcs \rTemp,\rTemp,LSR #1 //half as much if 16 bit mode
++.endm
++
++
++#define CH_NULL 0x00
++#define CH_BACKSPACE 0x08
++#define CH_LF 0x0a
++#define CH_CR 0x0d
++#define CH_CAN 0x18
++#define CH_SPACE 0x20 //" "
++#define CH_EXCLAMATION 0x21 //!
++#define CH_DQUOTE 0x22 //"
++#define CH_POUND 0x23 //#
++#define CH_DOLLAR 0x24 //$
++#define CH_PERCENT 0x25 //%
++#define CH_AMPERSAND 0x26 //&
++#define CH_SQUOTE 0x27 //'
++#define CH_OPEN_PAREN 0x28 //(
++#define CH_CLOSE_PAREN 0x29 //)
++#define CH_ASTERISK 0x2a //*
++#define CH_PLUS 0x2b //+
++#define CH_COMMA 0x2c //,
++#define CH_HYPHEN 0x2d //-
++#define CH_MINUS 0x2d //-
++#define CH_PERIOD 0x2e //.
++#define CH_FSLASH 0x2f // /
++#define CH_0 0x30
++#define CH_1 0x31
++#define CH_2 0x32
++#define CH_3 0x33
++#define CH_4 0x34
++#define CH_5 0x35
++#define CH_6 0x36
++#define CH_7 0x37
++#define CH_8 0x38
++#define CH_9 0x39
++#define CH_COLON 0x3a //:
++#define CH_SEMICOLON 0x3b //;
++#define CH_LESS_THAN 0x3c //<
++#define CH_EQUAL 0x3d //=
++#define CH_GREATER_THAN 0x3e //>
++#define CH_QUESTION_MARK 0x3f //?
++#define CH_AT_SIGN 0x40 //@
++
++#define CH_A 0x41
++#define CH_B 0x42
++#define CH_C 0x43
++#define CH_D 0x44
++#define CH_E 0x45
++#define CH_F 0x46
++#define CH_G 0x47
++#define CH_H 0x48
++#define CH_I 0x49
++#define CH_J 0x4a
++#define CH_K 0x4b
++#define CH_L 0x4c
++#define CH_M 0x4d
++#define CH_N 0x4e
++#define CH_O 0x4f
++#define CH_P 0x50
++#define CH_Q 0x51
++#define CH_R 0x52
++#define CH_S 0x53
++#define CH_T 0x54
++#define CH_U 0x55
++#define CH_V 0x56
++#define CH_W 0x57
++#define CH_X 0x58
++#define CH_Y 0x59
++#define CH_Z 0x5a
++#define CH_OPEN_SQUARE 0x5b //[
++#define CH_BSLASH 0x5c //\..
++#define CH_CLOSE_SQUARE 0x5d //]
++#define CH_CARET 0x5e //^
++#define CH__ 0x5f //_
++#define CH_OPEN_SQUOTE 0x60 //`
++
++#define CH_a 0x61
++#define CH_b 0x62
++#define CH_c 0x63
++#define CH_d 0x64
++#define CH_e 0x65
++#define CH_f 0x66
++#define CH_g 0x67
++#define CH_h 0x68
++#define CH_i 0x69
++#define CH_j 0x6a
++#define CH_k 0x6b
++#define CH_l 0x6c
++#define CH_m 0x6d
++#define CH_n 0x6e
++#define CH_o 0x6f
++#define CH_p 0x70
++#define CH_q 0x71
++#define CH_r 0x72
++#define CH_s 0x73
++#define CH_t 0x74
++#define CH_u 0x75
++#define CH_v 0x76
++#define CH_w 0x77
++#define CH_x 0x78
++#define CH_y 0x79
++#define CH_z 0x7a
++#define CH_OPEN_CURLY 0x7b //{
++#define CH_VERTICAL_BAR 0x7c //|
++#define CH_CLOSE_CURLY 0x7d //}
++#define CH_TILDE 0x7e //~
++#define CH_DELETE 0x7f
++
++
++.macro STARTUPTEXT
++ GBLS AreaName
++ AREA |.astart|,ALIGN=2,CODE
++AreaName SETS "|.astart|"
++.endm
++
++.macro DUP count,val
++ LCLA cnt
++cnt SETA $count
++ WHILE ( cnt<>0)
++ DCD $val
++cnt SETA cnt-1
++ WEND
++.endm
+diff -u -r --new-file u-boot-1.1.2/include/asm-arm/arch-pxa/pxa-regs.h u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxa-regs.h
+--- u-boot-1.1.2/include/asm-arm/arch-pxa/pxa-regs.h 2003-06-27 23:32:42.000000000 +0200
++++ u-boot-1.1.2-neon/include/asm-arm/arch-pxa/pxa-regs.h 2007-08-11 21:07:21.000000000 +0200
+@@ -107,6 +107,17 @@
+ #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
+ #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
+ #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
++
++#if defined(CONFIG_PXA27X)
++#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
++#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
++#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
++#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
++#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
++#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
++#define DCSR_ENRINTR (1 << 9) /* The end of Receive */
++#endif
++
+ #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
+ #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
+ #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
+@@ -156,6 +167,10 @@
+ #define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
+ #define DRCMR39 __REG(0x4000019C) /* Reserved */
+
++#define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */
++#define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */
++#define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */
++
+ #define DRCMRRXSADR DRCMR2
+ #define DRCMRTXSADR DRCMR3
+ #define DRCMRRXBTRBR DRCMR4
+@@ -424,6 +439,12 @@
+ #define ISR __REG(0x40301698) /* I2C Status Register - ISR */
+ #define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
+
++#define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */
++#define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */
++#define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */
++#define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */
++#define PWRISAR __REG(0x40f001A0) /* Power I2C Slave Address Register-ISAR */
++
+ /* ----- Control register bits ---------------------------------------- */
+
+ #define ICR_START 0x1 /* start bit */
+@@ -460,11 +481,9 @@
+ /*
+ * Serial Audio Controller
+ */
+-
+-
+ /* FIXME the audio defines collide w/ the SA1111 defines. I don't like these
+- * short defines because there is too much chance of namespace collision */
+-
++ * short defines because there is too much chance of namespace collision
++ */
+ /*#define SACR0 __REG(0x40400000) / Global Control Register */
+ /*#define SACR1 __REG(0x40400004) / Serial Audio I 2 S/MSB-Justified Control Register */
+ /*#define SASR0 __REG(0x4040000C) / Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
+@@ -711,10 +730,68 @@
+ #define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
+
+
++#if defined(CONFIG_PXA27X)
+ /*
+- * Fast Infrared Communication Port
++ * USB Host Controller
+ */
++#define USBH_BASE 0x4C000000
++#define UHCREV __REG(0x4C000000)
++#define UHCHCON __REG(0x4C000004)
++#define UHCCOMS __REG(0x4C000008)
++#define UHCINTS __REG(0x4C00000C)
++#define UHCINTE __REG(0x4C000010)
++#define UHCINTD __REG(0x4C000014)
++#define UHCHCCA __REG(0x4C000018)
++#define UHCPCED __REG(0x4C00001C)
++#define UHCCHED __REG(0x4C000020)
++#define UHCCCED __REG(0x4C000024)
++#define UHCBHED __REG(0x4C000028)
++#define UHCBCED __REG(0x4C00002C)
++#define UHCDHEAD __REG(0x4C000030)
++#define UHCFMI __REG(0x4C000034)
++#define UHCFMR __REG(0x4C000038)
++#define UHCFMN __REG(0x4C00003C)
++#define UHCPERS __REG(0x4C000040)
++#define UHCLST __REG(0x4C000044)
++#define UHCRHDA __REG(0x4C000048)
++#define UHCRHDB __REG(0x4C00004C)
++#define UHCRHS __REG(0x4C000050)
++#define UHCRHPS1 __REG(0x4C000054)
++#define UHCRHPS2 __REG(0x4C000058)
++#define UHCRHPS3 __REG(0x4C00005C)
++#define UHCSTAT __REG(0x4C000060)
++#define UHCHR __REG(0x4C000064)
++#define UHCHIE __REG(0x4C000068)
++#define UHCHIT __REG(0x4C00006C)
++
++#define UHCHR_FSBIR (1<<0)
++#define UHCHR_FHR (1<<1)
++#define UHCHR_CGR (1<<2)
++#define UHCHR_SSDC (1<<3)
++#define UHCHR_UIT (1<<4)
++#define UHCHR_SSE (1<<5)
++#define UHCHR_PSPL (1<<6)
++#define UHCHR_PCPL (1<<7)
++#define UHCHR_SSEP0 (1<<9)
++#define UHCHR_SSEP1 (1<<10)
++#define UHCHR_SSEP2 (1<<11)
++
++#define UHCHIE_UPRIE (1<<13)
++#define UHCHIE_UPS2IE (1<<12)
++#define UHCHIE_UPS1IE (1<<11)
++#define UHCHIE_TAIE (1<<10)
++#define UHCHIE_HBAIE (1<<8)
++#define UHCHIE_RWIE (1<<7)
++
++#define UHCCOMS_HCR 1
++#define UHCRHS_LPS 1
++#define UHCHR_SSE (1<<5)
++
++#endif
+
++/*
++ * Fast Infrared Communication Port
++ */
+ #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
+ #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
+ #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
+@@ -731,7 +808,21 @@
+ #define RTAR __REG(0x40900004) /* RTC Alarm Register */
+ #define RTSR __REG(0x40900008) /* RTC Status Register */
+ #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
+-
++#define RDAR1 __REG(0x40900018) /* Wristwatch Day Alarm Reg 1 */
++#define RDAR2 __REG(0x40900020) /* Wristwatch Day Alarm Reg 2 */
++#define RYAR1 __REG(0x4090001C) /* Wristwatch Year Alarm Reg 1 */
++#define RYAR2 __REG(0x40900024) /* Wristwatch Year Alarm Reg 2 */
++#define SWAR1 __REG(0x4090002C) /* Stopwatch Alarm Register 1 */
++#define SWAR2 __REG(0x40900030) /* Stopwatch Alarm Register 2 */
++#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
++#define RDCR __REG(0x40900010) /* RTC Day Count Register. */
++#define RYCR __REG(0x40900014) /* RTC Year Count Register. */
++#define SWCR __REG(0x40900028) /* Stopwatch Count Register */
++#define RTCPICR __REG(0x40900034) /* Periodic Interrupt Counter Register */
++
++#define RTSR_PICE (1 << 15) /* Peridoc interrupt count enable */
++#define RTSR_PIALE (1 << 14) /* Peridoc interrupt Alarm enable */
++#define RTSR_PIAL (1 << 13) /* Peridoc interrupt Alarm status */
+ #define RTSR_HZE (1 << 3) /* HZ interrupt enable */
+ #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
+ #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
+@@ -831,6 +922,37 @@
+ /* More handy macros. The argument is a literal GPIO number. */
+
+ #define GPIO_bit(x) (1 << ((x) & 0x1f))
++
++#ifdef CONFIG_PXA27X
++
++/* Interrupt Controller */
++
++#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
++#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
++#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
++#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
++#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
++
++#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
++#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
++#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
++#define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
++#define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
++#define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
++#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
++#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
++
++#define GPLR(x) ((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)
++#define GPDR(x) ((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)
++#define GPSR(x) ((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)
++#define GPCR(x) ((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)
++#define GRER(x) ((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)
++#define GFER(x) ((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)
++#define GEDR(x) ((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)
++#define GAFR(x) ((((x) & 0x7f) < 96) ? _GAFR(x) : \
++ ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))
++#else
++
+ #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
+ #define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
+ #define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
+@@ -840,6 +962,8 @@
+ #define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
+ #define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
+
++#endif
++
+ /* GPIO alternate function assignments */
+
+ #define GPIO1_RST 1 /* reset */
+@@ -1038,6 +1162,8 @@
+ #define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT)
+ #define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT)
+
++#define GPIO117_SCL (117 | GPIO_ALT_FN_1_OUT)
++#define GPIO118_SDA (118 | GPIO_ALT_FN_1_OUT)
+
+ /*
+ * Power Manager
+@@ -1054,8 +1180,62 @@
+ #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
+ #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
+ #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
++#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
+ #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
+
++#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
++#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */
++#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */
++#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */
++#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
++#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
++#define PCMD(x) __REG(0x40F00080 + x*4)
++#define PCMD0 __REG(0x40F00080 + 0 * 4)
++#define PCMD1 __REG(0x40F00080 + 1 * 4)
++#define PCMD2 __REG(0x40F00080 + 2 * 4)
++#define PCMD3 __REG(0x40F00080 + 3 * 4)
++#define PCMD4 __REG(0x40F00080 + 4 * 4)
++#define PCMD5 __REG(0x40F00080 + 5 * 4)
++#define PCMD6 __REG(0x40F00080 + 6 * 4)
++#define PCMD7 __REG(0x40F00080 + 7 * 4)
++#define PCMD8 __REG(0x40F00080 + 8 * 4)
++#define PCMD9 __REG(0x40F00080 + 9 * 4)
++#define PCMD10 __REG(0x40F00080 + 10 * 4)
++#define PCMD11 __REG(0x40F00080 + 11 * 4)
++#define PCMD12 __REG(0x40F00080 + 12 * 4)
++#define PCMD13 __REG(0x40F00080 + 13 * 4)
++#define PCMD14 __REG(0x40F00080 + 14 * 4)
++#define PCMD15 __REG(0x40F00080 + 15 * 4)
++#define PCMD16 __REG(0x40F00080 + 16 * 4)
++#define PCMD17 __REG(0x40F00080 + 17 * 4)
++#define PCMD18 __REG(0x40F00080 + 18 * 4)
++#define PCMD19 __REG(0x40F00080 + 19 * 4)
++#define PCMD20 __REG(0x40F00080 + 20 * 4)
++#define PCMD21 __REG(0x40F00080 + 21 * 4)
++#define PCMD22 __REG(0x40F00080 + 22 * 4)
++#define PCMD23 __REG(0x40F00080 + 23 * 4)
++#define PCMD24 __REG(0x40F00080 + 24 * 4)
++#define PCMD25 __REG(0x40F00080 + 25 * 4)
++#define PCMD26 __REG(0x40F00080 + 26 * 4)
++#define PCMD27 __REG(0x40F00080 + 27 * 4)
++#define PCMD28 __REG(0x40F00080 + 28 * 4)
++#define PCMD29 __REG(0x40F00080 + 29 * 4)
++#define PCMD30 __REG(0x40F00080 + 30 * 4)
++#define PCMD31 __REG(0x40F00080 + 31 * 4)
++
++#define PCMD_MBC (1<<12)
++#define PCMD_DCE (1<<11)
++#define PCMD_LC (1<<10)
++/* FIXME: PCMD_SQC need be checked. */
++#define PCMD_SQC (3<<8) /* currently only bit 8 is changerable, */
++ /* bit 9 should be 0 all day. */
++#define PVCR_VCSA (0x1<<14)
++#define PVCR_CommandDelay (0xf80)
++/* define MACRO for Power Manager General Configuration Register (PCFR) */
++#define PCFR_FVC (0x1 << 10)
++#define PCFR_PI2C_EN (0x1 << 6)
++
++#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
+ #define PSSR_RDH (1 << 5) /* Read Disable Hold */
+ #define PSSR_PH (1 << 4) /* Peripheral Control Hold */
+ #define PSSR_VFS (1 << 2) /* VDD Fault Status */
+@@ -1117,14 +1297,29 @@
+ #define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
+
+ #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
++#if !defined(CONFIG_PXA27X)
+ #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
++#endif
+ #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
+
++#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */
++#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
++#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */
++#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */
++#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
++#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
++#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
++#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */
+ #define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */
++#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */
+ #define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */
+ #define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */
+ #define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */
+ #define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */
++#if defined(CONFIG_PXA27X)
++#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */
++#define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */
++#endif
+ #define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */
+ #define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
+ #define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
+@@ -1137,6 +1332,7 @@
+ #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
+ #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
+
++#if !defined(CONFIG_PXA27X)
+ #define CCCR_L09 (0x1F)
+ #define CCCR_L27 (0x1)
+ #define CCCR_L32 (0x2)
+@@ -1153,6 +1349,7 @@
+ #define CCCR_N20 (0x4 << 7)
+ #define CCCR_N25 (0x5 << 7)
+ #define CCCR_N30 (0x6 << 7)
++#endif
+
+ /*
+ * LCD
+@@ -1164,7 +1361,8 @@
+ #define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */
+ #define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
+ #define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
+-#define LCSR __REG(0x44000038) /* LCD Controller Status Register */
++#define LCSR0 __REG(0x44000038) /* LCD Controller Status Register */
++#define LCSR1 __REG(0x44000034) /* LCD Controller Status Register */
+ #define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */
+ #define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */
+ #define TMEDCR __REG(0x44000044) /* TMED Control Register */
+@@ -1194,6 +1392,11 @@
+ #define LCCR0_PDD_S 12
+ #define LCCR0_BM (1 << 20) /* Branch mask */
+ #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
++#if defined(CONFIG_PXA27X)
++#define LCCR0_LCDT (1 << 22) /* LCD Panel Type */
++#define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */
++#define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */
++#endif
+
+ #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
+ #define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \
+@@ -1257,6 +1460,11 @@
+ #endif
+ #define LCCR3_DPC (1 << 27) /* double pixel clock mode */
+
++#define LCCR3_PDFOR_0 (0 << 30)
++#define LCCR3_PDFOR_1 (1 << 30)
++#define LCCR3_PDFOR_2 (2 << 30)
++#define LCCR3_PDFOR_3 (3 << 30)
++
+
+ #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
+ #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \
+@@ -1265,7 +1473,7 @@
+
+ #define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */
+ #define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \
+- (((Bpp) << FShft (LCCR3_BPP)))
++ ((((Bpp&0x7) << FShft (LCCR3_BPP)))|(((Bpp&0x8)<<26)))
+
+ #define LCCR3_ACB Fld (8, 8) /* AC Bias */
+ #define LCCR3_Acb(Acb) /* BAC Bias */ \
+@@ -1280,33 +1488,50 @@
+ #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
+ /* active Low */
+
+-#define LCSR_LDD (1 << 0) /* LCD Disable Done */
+-#define LCSR_SOF (1 << 1) /* Start of frame */
+-#define LCSR_BER (1 << 2) /* Bus error */
+-#define LCSR_ABC (1 << 3) /* AC Bias count */
+-#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
+-#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
+-#define LCSR_OU (1 << 6) /* output FIFO underrun */
+-#define LCSR_QD (1 << 7) /* quick disable */
+-#define LCSR_EOF (1 << 8) /* end of frame */
+-#define LCSR_BS (1 << 9) /* branch status */
+-#define LCSR_SINT (1 << 10) /* subsequent interrupt */
+-
+-#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
+-
+-#define LCSR_LDD (1 << 0) /* LCD Disable Done */
+-#define LCSR_SOF (1 << 1) /* Start of frame */
+-#define LCSR_BER (1 << 2) /* Bus error */
+-#define LCSR_ABC (1 << 3) /* AC Bias count */
+-#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
+-#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
+-#define LCSR_OU (1 << 6) /* output FIFO underrun */
+-#define LCSR_QD (1 << 7) /* quick disable */
+-#define LCSR_EOF (1 << 8) /* end of frame */
+-#define LCSR_BS (1 << 9) /* branch status */
+-#define LCSR_SINT (1 << 10) /* subsequent interrupt */
++#define LCSR0_LDD (1 << 0) /* LCD Disable Done */
++#define LCSR0_SOF (1 << 1) /* Start of frame */
++#define LCSR0_BER (1 << 2) /* Bus error */
++#define LCSR0_ABC (1 << 3) /* AC Bias count */
++#define LCSR0_IUL (1 << 4) /* input FIFO underrun Lower panel */
++#define LCSR0_IUU (1 << 5) /* input FIFO underrun Upper panel */
++#define LCSR0_OU (1 << 6) /* output FIFO underrun */
++#define LCSR0_QD (1 << 7) /* quick disable */
++#define LCSR0_EOF0 (1 << 8) /* end of frame */
++#define LCSR0_BS (1 << 9) /* branch status */
++#define LCSR0_SINT (1 << 10) /* subsequent interrupt */
++
++#define LCSR1_SOF1 (1 << 0)
++#define LCSR1_SOF2 (1 << 1)
++#define LCSR1_SOF3 (1 << 2)
++#define LCSR1_SOF4 (1 << 3)
++#define LCSR1_SOF5 (1 << 4)
++#define LCSR1_SOF6 (1 << 5)
++
++#define LCSR1_EOF1 (1 << 8)
++#define LCSR1_EOF2 (1 << 9)
++#define LCSR1_EOF3 (1 << 10)
++#define LCSR1_EOF4 (1 << 11)
++#define LCSR1_EOF5 (1 << 12)
++#define LCSR1_EOF6 (1 << 13)
++
++#define LCSR1_BS1 (1 << 16)
++#define LCSR1_BS2 (1 << 17)
++#define LCSR1_BS3 (1 << 18)
++#define LCSR1_BS4 (1 << 19)
++#define LCSR1_BS5 (1 << 20)
++#define LCSR1_BS6 (1 << 21)
++
++#define LCSR1_IU2 (1 << 25)
++#define LCSR1_IU3 (1 << 26)
++#define LCSR1_IU4 (1 << 27)
++#define LCSR1_IU5 (1 << 28)
++#define LCSR1_IU6 (1 << 29)
+
+ #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
++#if defined(CONFIG_PXA27X)
++#define LDCMD_SOFINT (1 << 22)
++#define LDCMD_EOFINT (1 << 21)
++#endif
+
+ /*
+ * Memory controller
+@@ -1369,5 +1594,191 @@
+ #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
+ #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
+
++#if defined(CONFIG_PXA27X)
+
+-#endif
++#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
++
++#define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
++#define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
++#define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
++#define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
++#define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
++#define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
++#define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
++#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
++#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
++
++/* Interrupt Controller */
++
++#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
++#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
++#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
++#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
++#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
++
++/* General Purpose I/O */
++
++#define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */
++#define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */
++#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
++#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
++#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
++#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO <127:96> */
++#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
++#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
++#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
++
++/* Core Clock */
++
++#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
++
++#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
++#define CKEN22_MEMC (1 << 22) /* Memory Controler */
++#define CKEN21_MSHC (1 << 21) /* Memery Stick Host Controller */
++#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
++#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
++#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
++#define CKEN17_MSL (1 << 17) /* MSL Interface Unit Clock Enable */
++#define CKEN15_PWR_I2C (1 << 15) /* PWR_I2C Unit Clock Enable */
++#define CKEN9_OST (1 << 9) /* OS Timer Unit Clock Enable */
++#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
++
++/* Memory controller */
++
++#define MDREFR_K0DB4 (1 << 29) /* SDCLK[0] divide by 4 */
++
++/* LCD registers */
++#define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 4 */
++#define LCCR5 __REG(0x44000014) /* LCD Controller Control Register 5 */
++#define FBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
++#define FBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
++#define FBR2 __REG(0x44000028) /* DMA Channel 2 Frame Branch Register */
++#define FBR3 __REG(0x4400002C) /* DMA Channel 3 Frame Branch Register */
++#define FBR4 __REG(0x44000030) /* DMA Channel 4 Frame Branch Register */
++#define FDADR2 __REG(0x44000220) /* DMA Channel 2 Frame Descriptor Address Register */
++#define FSADR2 __REG(0x44000224) /* DMA Channel 2 Frame Source Address Register */
++#define FIDR2 __REG(0x44000228) /* DMA Channel 2 Frame ID Register */
++#define LDCMD2 __REG(0x4400022C) /* DMA Channel 2 Command Register */
++#define FDADR3 __REG(0x44000230) /* DMA Channel 3 Frame Descriptor Address Register */
++#define FSADR3 __REG(0x44000234) /* DMA Channel 3 Frame Source Address Register */
++#define FIDR3 __REG(0x44000238) /* DMA Channel 3 Frame ID Register */
++#define LDCMD3 __REG(0x4400023C) /* DMA Channel 3 Command Register */
++#define FDADR4 __REG(0x44000240) /* DMA Channel 4 Frame Descriptor Address Register */
++#define FSADR4 __REG(0x44000244) /* DMA Channel 4 Frame Source Address Register */
++#define FIDR4 __REG(0x44000248) /* DMA Channel 4 Frame ID Register */
++#define LDCMD4 __REG(0x4400024C) /* DMA Channel 4 Command Register */
++#define FDADR5 __REG(0x44000250) /* DMA Channel 5 Frame Descriptor Address Register */
++#define FSADR5 __REG(0x44000254) /* DMA Channel 5 Frame Source Address Register */
++#define FIDR5 __REG(0x44000258) /* DMA Channel 5 Frame ID Register */
++#define LDCMD5 __REG(0x4400025C) /* DMA Channel 5 Command Register */
++
++#define OVL1C1 __REG(0x44000050) /* Overlay 1 Control Register 1 */
++#define OVL1C2 __REG(0x44000060) /* Overlay 1 Control Register 2 */
++#define OVL2C1 __REG(0x44000070) /* Overlay 2 Control Register 1 */
++#define OVL2C2 __REG(0x44000080) /* Overlay 2 Control Register 2 */
++#define CCR __REG(0x44000090) /* Cursor Control Register */
++
++#define FBR5 __REG(0x44000110) /* DMA Channel 5 Frame Branch Register */
++#define FBR6 __REG(0x44000114) /* DMA Channel 6 Frame Branch Register */
++
++#define LCCR0_LDDALT (1<<26) /* LDD Alternate mapping bit when base pixel is RGBT16 */
++#define LCCR0_OUC (1<<25) /* Overlay Underlay Control Bit */
++
++#define LCCR5_SOFM1 (1<<0) /* Start Of Frame Mask for Overlay 1 (channel 1) */
++#define LCCR5_SOFM2 (1<<1) /* Start Of Frame Mask for Overlay 2 (channel 2) */
++#define LCCR5_SOFM3 (1<<2) /* Start Of Frame Mask for Overlay 2 (channel 3) */
++#define LCCR5_SOFM4 (1<<3) /* Start Of Frame Mask for Overlay 2 (channel 4) */
++#define LCCR5_SOFM5 (1<<4) /* Start Of Frame Mask for cursor (channel 5) */
++#define LCCR5_SOFM6 (1<<5) /* Start Of Frame Mask for command data (channel 6) */
++
++#define LCCR5_EOFM1 (1<<8) /* End Of Frame Mask for Overlay 1 (channel 1) */
++#define LCCR5_EOFM2 (1<<9) /* End Of Frame Mask for Overlay 2 (channel 2) */
++#define LCCR5_EOFM3 (1<<10) /* End Of Frame Mask for Overlay 2 (channel 3) */
++#define LCCR5_EOFM4 (1<<11) /* End Of Frame Mask for Overlay 2 (channel 4) */
++#define LCCR5_EOFM5 (1<<12) /* End Of Frame Mask for cursor (channel 5) */
++#define LCCR5_EOFM6 (1<<13) /* End Of Frame Mask for command data (channel 6) */
++
++#define LCCR5_BSM1 (1<<16) /* Branch mask for Overlay 1 (channel 1) */
++#define LCCR5_BSM2 (1<<17) /* Branch mask for Overlay 2 (channel 2) */
++#define LCCR5_BSM3 (1<<18) /* Branch mask for Overlay 2 (channel 3) */
++#define LCCR5_BSM4 (1<<19) /* Branch mask for Overlay 2 (channel 4) */
++#define LCCR5_BSM5 (1<<20) /* Branch mask for cursor (channel 5) */
++#define LCCR5_BSM6 (1<<21) /* Branch mask for data command (channel 6) */
++
++#define LCCR5_IUM1 (1<<24) /* Input FIFO Underrun Mask for Overlay 1 */
++#define LCCR5_IUM2 (1<<25) /* Input FIFO Underrun Mask for Overlay 2 */
++#define LCCR5_IUM3 (1<<26) /* Input FIFO Underrun Mask for Overlay 2 */
++#define LCCR5_IUM4 (1<<27) /* Input FIFO Underrun Mask for Overlay 2 */
++#define LCCR5_IUM5 (1<<28) /* Input FIFO Underrun Mask for cursor */
++#define LCCR5_IUM6 (1<<29) /* Input FIFO Underrun Mask for data command */
++
++#define OVL1C1_O1EN (1<<31) /* Enable bit for Overlay 1 */
++#define OVL2C1_O2EN (1<<31) /* Enable bit for Overlay 2 */
++#define CCR_CEN (1<<31) /* Enable bit for Cursor */
++
++/* Keypad controller */
++
++#define KPC __REG(0x41500000) /* Keypad Interface Control register */
++#define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */
++#define KPREC __REG(0x41500010) /* Keypad Intefcace Rotary Encoder register */
++#define KPMK __REG(0x41500018) /* Keypad Intefcace Matrix Key register */
++#define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */
++#define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
++#define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
++#define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
++#define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
++#define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */
++
++#define KPC_AS (0x1 << 30) /* Automatic Scan bit */
++#define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */
++#define KPC_MI (0x1 << 22) /* Matrix interrupt bit */
++#define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */
++#define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */
++#define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */
++#define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */
++#define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */
++#define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */
++#define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */
++#define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */
++#define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */
++#define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */
++#define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */
++#define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Key Debounce select */
++#define KPC_DI (0x1 << 5) /* Direct key interrupt bit */
++#define KPC_DEE0 (0x1 << 2) /* Rotary Encoder 0 Enable */
++#define KPC_DE (0x1 << 1) /* Direct Keypad Enable */
++#define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */
++
++#define KPDK_DKP (0x1 << 31)
++#define KPDK_DK7 (0x1 << 7)
++#define KPDK_DK6 (0x1 << 6)
++#define KPDK_DK5 (0x1 << 5)
++#define KPDK_DK4 (0x1 << 4)
++#define KPDK_DK3 (0x1 << 3)
++#define KPDK_DK2 (0x1 << 2)
++#define KPDK_DK1 (0x1 << 1)
++#define KPDK_DK0 (0x1 << 0)
++
++#define KPREC_OF1 (0x1 << 31)
++#define kPREC_UF1 (0x1 << 30)
++#define KPREC_OF0 (0x1 << 15)
++#define KPREC_UF0 (0x1 << 14)
++
++#define KPMK_MKP (0x1 << 31)
++#define KPAS_SO (0x1 << 31)
++#define KPASMKPx_SO (0x1 << 31)
++
++#define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
++#define PSLR __REG(0x40F00034)
++#define PSTR __REG(0x40F00038) /* Power Manager Standby Configuration Reg */
++#define PSNR __REG(0x40F0003C) /* Power Manager Sense Configuration Reg */
++#define PVCR __REG(0x40F00040) /* Power Manager Voltage Change Control Reg */
++#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-Up Enable Reg */
++#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Status Reg */
++#define OSMR4 __REG(0x40A00080) /* */
++#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
++#define OMCR4 __REG(0x40A000C0) /* */
++
++#endif /* CONFIG_PXA27X */
++
++#endif /* _PXA_REGS_H_ */
+diff -u -r --new-file u-boot-1.1.2/include/asm-arm/mach-types.h u-boot-1.1.2-neon/include/asm-arm/mach-types.h
+--- u-boot-1.1.2/include/asm-arm/mach-types.h 2004-10-10 20:41:14.000000000 +0200
++++ u-boot-1.1.2-neon/include/asm-arm/mach-types.h 2007-08-11 21:07:21.000000000 +0200
+@@ -624,6 +624,9 @@
+ #define MACH_TYPE_RMS100 611
+ #define MACH_TYPE_KB9200 612
+ #define MACH_TYPE_SX1 613
++#define MACH_TYPE_NEON 332
++#define MACH_TYPE_BD2003 332
++#define MACH_TYPE_HALOGEN 332
+
+ #ifdef CONFIG_ARCH_EBSA110
+ # ifdef machine_arch_type
+@@ -7945,6 +7948,42 @@
+ # define machine_is_sx1() (0)
+ #endif
+
++#ifdef CONFIG_ARCH_NEON
++# ifdef machine_arch_type
++# undef machine_arch_type
++# define machine_arch_type __machine_arch_type
++# else
++# define machine_arch_type MACH_TYPE_NEON
++# endif
++# define machine_is_neon() (machine_arch_type == MACH_TYPE_NEON)
++#else
++# define machine_is_neon() (0)
++#endif
++
++#ifdef CONFIG_ARCH_BD2003
++# ifdef machine_arch_type
++# undef machine_arch_type
++# define machine_arch_type __machine_arch_type
++# else
++# define machine_arch_type MACH_TYPE_BD2003
++# endif
++# define machine_is_bd2003() (machine_arch_type == MACH_TYPE_BD2003)
++#else
++# define machine_is_bd2003() (0)
++#endif
++
++#ifdef CONFIG_ARCH_HALOGEN
++# ifdef machine_arch_type
++# undef machine_arch_type
++# define machine_arch_type __machine_arch_type
++# else
++# define machine_arch_type MACH_TYPE_HALOGEN
++# endif
++# define machine_is_halogen() (machine_arch_type == MACH_TYPE_HALOGEN)
++#else
++# define machine_is_halogen() (0)
++#endif
++
+ /*
+ * These have not yet been registered
+ */
+diff -u -r --new-file u-boot-1.1.2/include/asm-arm/processor.h u-boot-1.1.2-neon/include/asm-arm/processor.h
+--- u-boot-1.1.2/include/asm-arm/processor.h 2003-06-26 00:26:36.000000000 +0200
++++ u-boot-1.1.2-neon/include/asm-arm/processor.h 2007-08-11 21:07:21.000000000 +0200
+@@ -48,11 +48,22 @@
+ #include <asm/proc/processor.h>
+ #include <asm/types.h>
+
++#ifdef arm
++#warning arm defined by preprocessor
++#define armX arm
++#undef arm
++#endif
++
+ union debug_insn {
+ u32 arm;
+ u16 thumb;
+ };
+
++#ifdef armX
++#define arm
++#undef armX
++#endif
++
+ struct debug_entry {
+ u32 address;
+ union debug_insn insn;
+diff -u -r --new-file u-boot-1.1.2/include/cmd_confdefs.h u-boot-1.1.2-neon/include/cmd_confdefs.h
+--- u-boot-1.1.2/include/cmd_confdefs.h 2004-12-16 18:59:53.000000000 +0100
++++ u-boot-1.1.2-neon/include/cmd_confdefs.h 2007-08-11 21:07:21.000000000 +0200
+@@ -92,6 +92,8 @@
+ #define CFG_CMD_XIMG 0x0400000000000000ULL /* Load part of Multi Image */
+ #define CFG_CMD_UNIVERSE 0x0800000000000000ULL /* Tundra Universe Support */
+ #define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */
++#define CFG_CMD_LCDPANEL 0x2000000000000000ULL /* Dynamic LCD Panel Support */
++#define CFG_CMD_NOT 0x4000000000000000ULL /* Negate a command */
+
+ #define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFULL /* ALL commands */
+
+diff -u -r --new-file u-boot-1.1.2/include/configs/bd2003.h u-boot-1.1.2-neon/include/configs/bd2003.h
+--- u-boot-1.1.2/include/configs/bd2003.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/include/configs/bd2003.h 2007-08-11 21:07:21.000000000 +0200
+@@ -0,0 +1,315 @@
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++/*
++ * bd2003.h
++ *
++ * This header file declares the configuration constants for the Boundary
++ * Devices BD2003 board.
++ *
++ * Change History :
++ *
++ * $Log: bd2003.h,v $
++ * Revision 1.7 2005/07/18 01:51:59 tkisky
++ * -define display types
++ *
++ * Revision 1.6 2005/07/17 22:52:10 ericn
++ * -fix comment
++ *
++ * Revision 1.5 2005/07/17 22:36:37 ericn
++ * -merge w/boundaryLib
++ *
++ * Revision 1.4 2005/07/02 18:45:55 ericn
++ * -bring up-to-date
++ *
++ * Revision 1.3 2005/04/20 09:05:36 tkisky
++ * -include select.h
++ *
++ * Revision 1.2 2005/04/15 10:40:52 tkisky
++ * -remove LCD_XRES,LCD_YRES
++ *
++ * Revision 1.1 2005/04/09 17:49:24 ericn
++ * -Initial import
++ *
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ * Copyright Boundary Devices, Inc. 2005
++ */
++
++/*
++ * If we are developing, we might want to start armboot from ram
++ * so we MUST NOT initialize critical regs like mem-timing ...
++ */
++#include "select.h"
++
++#define CONFIG_INIT_CRITICAL /* undef for developing */
++#define CONFIG_SETUP_MEMORY_TAGS 1
++#define CONFIG_INITRD_TAG 1
++
++/*
++ * High Level Configuration Options
++ * (easy to change)
++ */
++#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
++#define PXALCD 1 /* Using the PXA display controller */
++#define CONFIG_LCD 1
++
++#define CONFIG_MMC 1
++#define BOARD_LATE_INIT 1
++
++#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
++
++/*
++ * Size of malloc() pool
++ */
++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
++#define CFG_MMU_SPACE_RESERVED (1<<14)
++
++/*
++ * Hardware drivers
++ */
++#define CONFIG_DRIVER_SMC91111
++#define CONFIG_SMC91111_BASE 0x10000300
++#define CONFIG_SMC_USE_32_BIT
++
++/*
++ * select serial console configuration
++ */
++#define CONFIG_FFUART 1 /* we use FFUART on BD2003 */
++
++/* allow to overwrite serial and ethaddr */
++//#define CONFIG_ENV_OVERWRITE
++
++#define CONFIG_BAUDRATE 115200
++
++#define SKIP_COMMANDS ( CFG_CMD_MISC \
++ | CFG_CMD_BDI \
++ | CFG_CMD_BOOTD \
++ | CFG_CMD_LOADS \
++ | CFG_CMD_LOADB \
++ | CFG_CMD_ITEST \
++ | CFG_CMD_FPGA \
++ | CFG_CMD_ECHO \
++ | CFG_CMD_DIAG \
++ | CFG_CMD_DATE \
++ | CFG_CMD_BOOTP \
++ | CFG_CMD_NFS \
++ )
++// | CFG_CMD_FLASH
++// | CFG_CMD_DHCP
++// | CFG_CMD_NET
++// | CFG_CMD_MEMORY
++// | CFG_CMD_ENV
++
++#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL \
++ | CFG_CMD_MMC \
++ | CFG_CMD_FAT \
++ | CFG_CMD_LCDPANEL \
++ | CFG_CMD_FLASH \
++ | CFG_CMD_DHCP \
++ | CFG_CMD_ENV \
++ | CFG_CMD_BMP) & ~(SKIP_COMMANDS) )
++
++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
++#include <cmd_confdefs.h>
++#define CONFIG_BOOTDELAY 3
++#define CONFIG_BOOTCOMMAND "mmcinit; " \
++ "fatload mmc 0 a0000000 init.scr ; autoscr a0000000 ; "
++#define CONFIG_BOOTARGS "console=ttyS0,115200 DEBUG=1 ENV=/etc/bashrc init=/linuxrc rw mtdparts=phys:1024k(armboot),256k(params),-(rootfs1) root=/dev/mtdblock3 rootfstype=cramfs"
++#define CONFIG_CMDLINE_TAG
++
++#define CONFIG_GZIP
++
++/*
++ * Choose one of the following:
++ *
++ * hitachi_qvga
++ * sharp_qvga
++ * hitachi_hvga
++ * sharp_vga
++ * hitachi_wvga - 7 or 9 inch
++ */
++#ifndef DA320X240
++#define DA320X240 0
++#define DA640X240 1
++#define DA800X480 2
++#define DA640X480 3
++#define DA240X320 4
++#define DA800X600 5
++#define DA1024X768 6
++#define DP480X320 7
++#define DP320X240 8
++#define DL122X32 9
++#endif
++
++#if DISPLAY_TYPE == DA640X240
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_hvga" "\0"
++#elif DISPLAY_TYPE == DA240X320
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=qvga_portrait" "\0"
++#elif DISPLAY_TYPE == DA320X240
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_qvga" "\0"
++#elif DISPLAY_TYPE == DA8000X480
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_wvga" "\0"
++#elif DISPLAY_TYPE == DA640X480
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=sharp_vga" "\0"
++#elif DISPLAY_TYPE == DA800X480
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_wvga" "\0"
++#elif DISPLAY_TYPE == DA1024X768
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=crt1024x768" "\0"
++#else
++#error No display selected
++#endif
++
++#define LCD_BPP LCD_COLOR8
++
++
++#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
++#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
++#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
++#endif
++
++/*
++ * Miscellaneous configurable options
++ */
++#define CFG_HUSH_PARSER 1
++#define CFG_PROMPT_HUSH_PS2 "> "
++
++#define CFG_LONGHELP /* undef to save memory */
++#ifdef CFG_HUSH_PARSER
++#define CFG_PROMPT "$ " /* Monitor Command Prompt */
++#else
++#define CFG_PROMPT "=> " /* Monitor Command Prompt */
++#endif
++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
++#define CFG_MAXARGS 16 /* max number of command args */
++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
++#define CFG_DEVICE_NULLDEV 1
++
++#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
++#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
++
++#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
++
++#define CFG_LOAD_ADDR 0xa0030000 /* default load address */
++
++#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
++#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
++
++ /* valid baudrates */
++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
++#define CFG_MMC_BASE 0xF0000000
++
++/*
++ * Stack sizes
++ *
++ * The stack sizes are set up in start.S using the settings below
++ */
++#define CONFIG_STACKSIZE (128*1024) /* regular stack */
++#ifdef CONFIG_USE_IRQ
++#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
++#endif
++
++/*
++ * Physical Memory Map
++ */
++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
++#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
++#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
++
++#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
++#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
++#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
++#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
++#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
++
++#define CFG_DRAM_BASE 0xa0000000
++#define CFG_DRAM_SIZE 0x04000000
++
++
++/*
++ * Memory settings
++ */
++#define CFG_MSC0_VAL 0x23F223F2
++#define CFG_MSC1_VAL 0x3FF1A441
++#define CFG_MSC2_VAL 0x7FF97FF1
++#define CFG_MDCNFG_VAL 0x00001AC9
++#define CFG_MDREFR_VAL 0x00018018
++#define CFG_MDMRS_VAL 0x00000000
++
++/*
++ * FLASH and environment organization
++ */
++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
++#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
++
++/* timeout values are in ticks */
++#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
++#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
++
++/*
++ * Environment is saved in flash at offset 1MB
++ */
++#define CFG_ENV_IS_IN_FLASH 1
++#define CFG_FLASH_BASE 0
++#define CFG_ENV_ADDR ((CFG_FLASH_BASE)+0x100000) /* Addr of Environment Sector */
++#define CFG_ENV_OFFSET ((CFG_ENV_ADDR)-(CFG_FLASH_BASE))
++#define CFG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */
++
++/*
++ * GPIO settings
++ */
++#define CFG_GPSR0_VAL 0x00008000
++#define CFG_GPSR1_VAL 0x00FC0382
++#define CFG_GPSR2_VAL 0x0001FFFF
++#define CFG_GPCR0_VAL 0x00000000
++#define CFG_GPCR1_VAL 0x00000000
++#define CFG_GPCR2_VAL 0x00000000
++#define CFG_GPDR0_VAL 0x0060A800
++#define CFG_GPDR1_VAL 0x00FF0382
++#define CFG_GPDR2_VAL 0x0001C000
++#define CFG_GAFR0_L_VAL 0x98400000
++#define CFG_GAFR0_U_VAL 0x00002950
++#define CFG_GAFR1_L_VAL 0x000A9558
++#define CFG_GAFR1_U_VAL 0x0005AAAA
++#define CFG_GAFR2_L_VAL 0xA0000000
++#define CFG_GAFR2_U_VAL 0x00000002
++
++#define CFG_PSSR_VAL 0x20
++
++/*
++ * PCMCIA and CF Interfaces
++ */
++#define CFG_MECR_VAL 0x00000000
++#define CFG_MCMEM0_VAL 0x00010504
++#define CFG_MCMEM1_VAL 0x00010504
++#define CFG_MCATT0_VAL 0x00010504
++#define CFG_MCATT1_VAL 0x00010504
++#define CFG_MCIO0_VAL 0x00004715
++#define CFG_MCIO1_VAL 0x00004715
++
++#ifndef __ASSEMBLY__
++
++extern unsigned long const fbStart ;
++extern unsigned long paletteRegs ;
++
++#endif /* _ASMLANGUAGE */
++
++#endif
++
+diff -u -r --new-file u-boot-1.1.2/include/configs/.cvsignore u-boot-1.1.2-neon/include/configs/.cvsignore
+--- u-boot-1.1.2/include/configs/.cvsignore 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/include/configs/.cvsignore 2007-08-11 21:07:21.000000000 +0200
+@@ -0,0 +1 @@
++select.h
+diff -u -r --new-file u-boot-1.1.2/include/configs/halogen.h u-boot-1.1.2-neon/include/configs/halogen.h
+--- u-boot-1.1.2/include/configs/halogen.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/include/configs/halogen.h 2007-08-11 21:07:21.000000000 +0200
+@@ -0,0 +1,325 @@
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++/*
++ * halogen.h
++ *
++ * This header file declares the configuration constants for the Boundary
++ * Devices Halogen (PXA-270) boards.
++ *
++ * Change History :
++ *
++ * $Log: halogen.h,v $
++ * Revision 1.6 2005/07/18 01:51:59 tkisky
++ * -define display types
++ *
++ * Revision 1.5 2005/07/17 22:52:10 ericn
++ * -fix comment
++ *
++ * Revision 1.4 2005/07/17 22:36:37 ericn
++ * -merge w/boundaryLib
++ *
++ * Revision 1.3 2005/07/16 16:26:00 ericn
++ * -fix name, memsize
++ *
++ * Revision 1.2 2005/07/10 14:32:45 ericn
++ * -include USB
++ *
++ * Revision 1.1 2005/07/04 16:40:32 ericn
++ * -Initial import
++ *
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ * Copyright Boundary Devices, Inc. 2005
++ */
++
++/*
++ * If we are developing, we might want to start armboot from ram
++ * so we MUST NOT initialize critical regs like mem-timing ...
++ */
++#include "select.h"
++
++#define CONFIG_INIT_CRITICAL /* undef for developing */
++#define CONFIG_SETUP_MEMORY_TAGS 1
++#define CONFIG_INITRD_TAG 1
++
++/*
++ * High Level Configuration Options
++ * (easy to change)
++ */
++#define CONFIG_PXA270 1 /* This is a PXA270 CPU */
++#define CONFIG_PXA27X 1 /* Which is a PXA27X */
++
++#define PXALCD 1 /* Using the PXA display controller */
++#define CONFIG_LCD 1
++
++#define CONFIG_MMC 1
++#define BOARD_LATE_INIT 1
++
++#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
++
++/*
++ * Size of malloc() pool
++ */
++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
++#define CFG_MMU_SPACE_RESERVED (1<<14)
++
++/*
++ * Hardware drivers
++ */
++#define CONFIG_DRIVER_SMC91111
++#define CONFIG_SMC91111_BASE 0x10000300
++#define CONFIG_SMC_USE_32_BIT
++
++/************************************************************
++ * USB support
++ ************************************************************/
++#define LITTLEENDIAN 1 /* Needed by usb_ohci.c */
++#define CFG_DEVICE_DEREGISTER 1 /* Needed by usb_kbd */
++#define CONFIG_DOS_PARTITION 1
++#define CONFIG_USB_OHCI 1
++#define CONFIG_USB_KEYBOARD 1
++#define CONFIG_USB_STORAGE 1
++
++/*
++ * select serial console configuration
++ */
++#define CONFIG_FFUART 1 /* we use FFUART on HALOGEN */
++
++/* allow to overwrite serial and ethaddr */
++//#define CONFIG_ENV_OVERWRITE
++
++#define CONFIG_BAUDRATE 115200
++
++#define SKIP_COMMANDS ( CFG_CMD_MISC \
++ | CFG_CMD_BDI \
++ | CFG_CMD_BOOTD \
++ | CFG_CMD_LOADS \
++ | CFG_CMD_LOADB \
++ | CFG_CMD_ITEST \
++ | CFG_CMD_FPGA \
++ | CFG_CMD_ECHO \
++ | CFG_CMD_DIAG \
++ | CFG_CMD_DATE \
++ | CFG_CMD_BOOTP \
++ | CFG_CMD_NFS \
++ )
++// | CFG_CMD_FLASH
++// | CFG_CMD_DHCP
++// | CFG_CMD_NET
++// | CFG_CMD_MEMORY
++// | CFG_CMD_ENV
++
++#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL \
++ | CFG_CMD_MMC \
++ | CFG_CMD_FAT \
++ | CFG_CMD_LCDPANEL \
++ | CFG_CMD_FLASH \
++ | CFG_CMD_DHCP \
++ | CFG_CMD_ENV \
++ | CFG_CMD_USB \
++ | CFG_CMD_BMP) & ~(SKIP_COMMANDS) )
++
++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
++#include <cmd_confdefs.h>
++#define CONFIG_BOOTDELAY 3
++#define CONFIG_BOOTCOMMAND "mmcinit; " \
++ "fatload mmc 0 a0000000 init.scr ; autoscr a0000000 ; "
++#define CONFIG_BOOTARGS "console=ttyS0,115200 DEBUG=1 ENV=/etc/bashrc init=/linuxrc rw mtdparts=phys:1024k(armboot),256k(params),-(rootfs1) root=/dev/mtdblock3 rootfstype=cramfs"
++#define CONFIG_CMDLINE_TAG
++
++#define CONFIG_GZIP
++
++/*
++ * Choose one of the following:
++ *
++ * hitachi_qvga
++ * sharp_qvga
++ * hitachi_hvga
++ * sharp_vga
++ * hitachi_wvga - 7 or 9 inch
++ */
++#ifndef DA320X240
++#define DA320X240 0
++#define DA640X240 1
++#define DA800X480 2
++#define DA640X480 3
++#define DA240X320 4
++#define DA800X600 5
++#define DA1024X768 6
++#define DP480X320 7
++#define DP320X240 8
++#define DL122X32 9
++#endif
++
++#if DISPLAY_TYPE == DA640X240
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_hvga" "\0"
++#elif DISPLAY_TYPE == DA240X320
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=qvga_portrait" "\0"
++#elif DISPLAY_TYPE == DA320X240
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_qvga" "\0"
++#elif DISPLAY_TYPE == DA8000X480
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_wvga" "\0"
++#elif DISPLAY_TYPE == DA640X480
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=sharp_vga" "\0"
++#elif DISPLAY_TYPE == DA800X480
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_wvga" "\0"
++#elif DISPLAY_TYPE == DA1024X768
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=crt1024x768" "\0"
++#else
++#error No display selected
++#endif
++
++#define LCD_BPP LCD_COLOR8
++
++
++#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
++#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
++#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
++#endif
++
++/*
++ * Miscellaneous configurable options
++ */
++#define CFG_HUSH_PARSER 1
++#define CFG_PROMPT_HUSH_PS2 "> "
++
++#define CFG_LONGHELP /* undef to save memory */
++#ifdef CFG_HUSH_PARSER
++#define CFG_PROMPT "$ " /* Monitor Command Prompt */
++#else
++#define CFG_PROMPT "=> " /* Monitor Command Prompt */
++#endif
++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
++#define CFG_MAXARGS 16 /* max number of command args */
++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
++#define CFG_DEVICE_NULLDEV 1
++
++#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
++#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
++
++#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
++
++#define CFG_LOAD_ADDR 0xa0030000 /* default load address */
++
++#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
++#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
++
++ /* valid baudrates */
++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
++#define CFG_MMC_BASE 0xF0000000
++
++/*
++ * Stack sizes
++ *
++ * The stack sizes are set up in start.S using the settings below
++ */
++#define CONFIG_STACKSIZE (128*1024) /* regular stack */
++#ifdef CONFIG_USE_IRQ
++#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
++#endif
++
++/*
++ * Physical Memory Map
++ */
++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
++#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
++#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
++
++#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
++#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
++#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
++#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
++#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
++
++#define CFG_DRAM_BASE 0xa0000000
++#define CFG_DRAM_SIZE 0x04000000
++
++
++/*
++ * Memory settings
++ */
++#define CFG_MSC0_VAL 0x23F223F2
++#define CFG_MSC1_VAL 0x3FF1A441
++#define CFG_MSC2_VAL 0x7FF97FF1
++#define CFG_MDCNFG_VAL 0x00001AC9
++#define CFG_MDREFR_VAL 0x00018018
++#define CFG_MDMRS_VAL 0x00000000
++
++/*
++ * FLASH and environment organization
++ */
++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
++#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
++
++/* timeout values are in ticks */
++#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
++#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
++
++/*
++ * Environment is saved in flash at offset 1MB
++ */
++#define CFG_ENV_IS_IN_FLASH 1
++#define CFG_FLASH_BASE 0
++#define CFG_ENV_ADDR ((CFG_FLASH_BASE)+0x100000) /* Addr of Environment Sector */
++#define CFG_ENV_OFFSET ((CFG_ENV_ADDR)-(CFG_FLASH_BASE))
++#define CFG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */
++
++/*
++ * GPIO settings
++ */
++#define CFG_GPSR0_VAL 0x00008000
++#define CFG_GPSR1_VAL 0x00FC0382
++#define CFG_GPSR2_VAL 0x0001FFFF
++#define CFG_GPCR0_VAL 0x00000000
++#define CFG_GPCR1_VAL 0x00000000
++#define CFG_GPCR2_VAL 0x00000000
++#define CFG_GPDR0_VAL 0x0060A800
++#define CFG_GPDR1_VAL 0x00FF0382
++#define CFG_GPDR2_VAL 0x0001C000
++#define CFG_GAFR0_L_VAL 0x98400000
++#define CFG_GAFR0_U_VAL 0x00002950
++#define CFG_GAFR1_L_VAL 0x000A9558
++#define CFG_GAFR1_U_VAL 0x0005AAAA
++#define CFG_GAFR2_L_VAL 0xA0000000
++#define CFG_GAFR2_U_VAL 0x00000002
++
++#define CFG_PSSR_VAL 0x20
++
++/*
++ * PCMCIA and CF Interfaces
++ */
++#define CFG_MECR_VAL 0x00000000
++#define CFG_MCMEM0_VAL 0x00010504
++#define CFG_MCMEM1_VAL 0x00010504
++#define CFG_MCATT0_VAL 0x00010504
++#define CFG_MCATT1_VAL 0x00010504
++#define CFG_MCIO0_VAL 0x00004715
++#define CFG_MCIO1_VAL 0x00004715
++
++#ifndef __ASSEMBLY__
++
++extern unsigned long const fbStart ;
++extern unsigned long paletteRegs ;
++
++#endif /* _ASMLANGUAGE */
++
++#endif
++
+diff -u -r --new-file u-boot-1.1.2/include/configs/neon.h u-boot-1.1.2-neon/include/configs/neon.h
+--- u-boot-1.1.2/include/configs/neon.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/include/configs/neon.h 2007-08-11 21:07:21.000000000 +0200
+@@ -0,0 +1,395 @@
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++/*
++ * neon.h
++ *
++ * This header file declares the configuration constants for the Boundary
++ * Devices Neon board.
++ *
++ * Change History :
++ *
++ * $Log: neon.h,v $
++ * Revision 1.27 2006/05/30 15:52:17 ericn
++ * -clear screen after SD wait loop
++ *
++ * Revision 1.26 2006/05/27 22:11:50 ericn
++ * -include 'not', 'sleep' commands, wait for SD, <esc><esc><esc> for prompt
++ *
++ * Revision 1.25 2005/10/22 02:09:31 ericn
++ * -add CONFIG_SUPPORT_VFAT
++ *
++ * Revision 1.24 2005/07/23 19:35:42 ericn
++ * -fix name
++ *
++ * Revision 1.23 2005/07/23 17:13:25 ericn
++ * -add USB support
++ *
++ * Revision 1.22 2005/07/18 01:48:15 tkisky
++ * -define display types
++ *
++ * Revision 1.21 2005/07/17 22:52:10 ericn
++ * -fix comment
++ *
++ * Revision 1.20 2005/07/17 22:36:37 ericn
++ * -merge w/boundaryLib
++ *
++ * Revision 1.19 2005/07/02 18:46:16 ericn
++ * -Neon always has CONFIG_SM501
++ *
++ * Revision 1.18 2005/07/02 14:57:11 ericn
++ * -include INITRD tag
++ *
++ * Revision 1.17 2005/06/02 04:55:06 ericn
++ * -auto-choose qvga_portrait for DA240X320
++ *
++ * Revision 1.16 2005/06/02 04:10:30 ericn
++ * -save environment in flash
++ *
++ * Revision 1.15 2005/05/08 22:07:31 ericn
++ * -added 1024x768, 800x480 options
++ *
++ * Revision 1.14 2005/05/05 04:11:53 ericn
++ * -add flash commands, sharp_vga display selector
++ *
++ * Revision 1.13 2005/05/05 03:22:20 ericn
++ * -change default load addr to WinCE's
++ *
++ * Revision 1.12 2005/05/04 04:22:23 ericn
++ * -updated to allow DHCP
++ *
++ * Revision 1.11 2005/05/03 15:28:56 ericn
++ * -include DHCP support
++ *
++ * Revision 1.10 2005/05/02 15:14:26 ericn
++ * -add SMC driver, remove hard-coded MAC
++ *
++ * Revision 1.9 2005/05/01 15:21:41 ericn
++ * -change crtPalette -> paletteRegs
++ *
++ * Revision 1.8 2005/04/28 03:41:23 ericn
++ * -pass RAM qty to Linux
++ *
++ * Revision 1.7 2005/04/28 03:35:32 ericn
++ * -default to cramfs
++ *
++ * Revision 1.6 2005/04/22 01:57:39 ericn
++ * -fix default boot args
++ *
++ * Revision 1.5 2005/04/20 09:05:36 tkisky
++ * -include select.h
++ *
++ * Revision 1.4 2005/04/18 13:49:10 ericn
++ * -default wvga, use init.scr
++ *
++ * Revision 1.3 2005/04/18 03:58:48 ericn
++ * -added autoscr, hush parser support
++ *
++ * Revision 1.2 2005/04/15 10:41:35 tkisky
++ * -remove LCD_XRES,LCD_YRES, remove extra mmcinit
++ *
++ * Revision 1.1 2005/04/09 17:49:25 ericn
++ * -Initial import
++ *
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ * Copyright Boundary Devices, Inc. 2005
++ */
++
++/*
++ * If we are developing, we might want to start armboot from ram
++ * so we MUST NOT initialize critical regs like mem-timing ...
++ */
++#include "select.h"
++
++#define CONFIG_INIT_CRITICAL /* undef for developing */
++#define CONFIG_SETUP_MEMORY_TAGS 1
++#define CONFIG_INITRD_TAG 1
++
++/*
++ * High Level Configuration Options
++ * (easy to change)
++ */
++#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
++#define CONFIG_NEON 1 /* on a Neon Board */
++#define CONFIG_SM501 1
++#define CONFIG_LCD 1
++
++#define CONFIG_MMC 1
++#define BOARD_LATE_INIT 1
++
++#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
++
++/*
++ * Size of malloc() pool
++ */
++#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
++#define CFG_MMU_SPACE_RESERVED (1<<14)
++
++/*
++ * Hardware drivers
++ */
++#define CONFIG_DRIVER_SMC91111
++#define CONFIG_SMC91111_BASE 0x10000300
++#define CONFIG_SMC_USE_32_BIT
++
++/************************************************************
++ * USB support
++ ************************************************************/
++#define LITTLEENDIAN 1 /* Needed by usb_ohci.c */
++#define CFG_DEVICE_DEREGISTER 1 /* Needed by usb_kbd */
++#define CONFIG_DOS_PARTITION 1
++#define CONFIG_USB_OHCI 1
++#define CONFIG_USB_KEYBOARD 1
++#define CONFIG_USB_STORAGE 1
++
++/*
++ * select serial console configuration
++ */
++#define CONFIG_FFUART 1 /* we use FFUART on NEON */
++
++/* allow to overwrite serial and ethaddr */
++//#define CONFIG_ENV_OVERWRITE
++
++#define CONFIG_BAUDRATE 115200
++
++#define SKIP_COMMANDS ( CFG_CMD_BDI \
++ | CFG_CMD_BOOTD \
++ | CFG_CMD_LOADS \
++ | CFG_CMD_LOADB \
++ | CFG_CMD_ITEST \
++ | CFG_CMD_FPGA \
++ | CFG_CMD_ECHO \
++ | CFG_CMD_DIAG \
++ | CFG_CMD_DATE \
++ | CFG_CMD_BOOTP \
++ | CFG_CMD_NFS \
++ )
++// | CFG_CMD_FLASH
++// | CFG_CMD_DHCP
++// | CFG_CMD_NET
++// | CFG_CMD_MEMORY
++// | CFG_CMD_ENV
++
++#define CONFIG_SUPPORT_VFAT
++#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL \
++ | CFG_CMD_MMC \
++ | CFG_CMD_FAT \
++ | CFG_CMD_LCDPANEL \
++ | CFG_CMD_FLASH \
++ | CFG_CMD_DHCP \
++ | CFG_CMD_ENV \
++ | CFG_CMD_USB \
++ | CFG_CMD_NOT \
++ | CFG_CMD_MISC \
++ | CFG_CMD_BMP) & ~(SKIP_COMMANDS) )
++
++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
++#include <cmd_confdefs.h>
++#define CONFIG_BOOTDELAY 3
++#define CONFIG_BOOTCOMMAND "while not mmcdet ; do cls ; lecho \"insert SD card\" ; sleep 1 ; done ; cls" \
++ "if mmcwp ; then lecho \"write protected\" ; else lecho \"not write protected\" ; fi ; " \
++ "mmcinit; " \
++ "if fatload mmc 0 a0000000 init.scr ; then autoscr a0000000 ; fi"
++#define CONFIG_BOOTARGS "console=ttyS0,115200 DEBUG=1 ENV=/etc/bashrc init=/linuxrc rw mtdparts=phys:1024k(armboot),256k(params),-(rootfs1) root=/dev/mtdblock3 rootfstype=cramfs"
++#define CONFIG_CMDLINE_TAG
++
++#define CONFIG_GZIP
++
++#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
++#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
++#define CONFIG_AUTOBOOT_DELAY_STR "\x1b\x1b\x1b"
++
++/*
++ * Choose one of the following:
++ *
++ * hitachi_qvga
++ * sharp_qvga
++ * hitachi_hvga
++ * sharp_vga
++ * hitachi_wvga - 7 or 9 inch
++ */
++#ifndef DA320X240
++#define DA320X240 0
++#define DA640X240 1
++#define DA800X480 2
++#define DA640X480 3
++#define DA240X320 4
++#define DA800X600 5
++#define DA1024X768 6
++#define DP480X320 7
++#define DP320X240 8
++#define DL122X32 9
++#endif
++
++#if DISPLAY_TYPE == DA640X240
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_hvga" "\0"
++#elif DISPLAY_TYPE == DA240X320
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=qvga_portrait" "\0"
++#elif DISPLAY_TYPE == DA320X240
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_qvga" "\0"
++#elif DISPLAY_TYPE == DA8000X480
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_wvga" "\0"
++#elif DISPLAY_TYPE == DA640X480
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=sharp_vga" "\0"
++#elif DISPLAY_TYPE == DA800X480
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=hitachi_wvga" "\0"
++#elif DISPLAY_TYPE == DA1024X768
++#define CONFIG_EXTRA_ENV_SETTINGS "panel=crt1024x768" "\0"
++#else
++#error No display selected
++#endif
++
++#define LCD_BPP LCD_COLOR8
++
++
++#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
++#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
++#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
++#endif
++
++/*
++ * Miscellaneous configurable options
++ */
++#define CFG_HUSH_PARSER 1
++#define CFG_PROMPT_HUSH_PS2 "> "
++
++#define CFG_LONGHELP /* undef to save memory */
++#ifdef CFG_HUSH_PARSER
++#define CFG_PROMPT "$ " /* Monitor Command Prompt */
++#else
++#define CFG_PROMPT "=> " /* Monitor Command Prompt */
++#endif
++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
++#define CFG_MAXARGS 16 /* max number of command args */
++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
++#define CFG_DEVICE_NULLDEV 1
++
++#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
++#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
++
++#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
++
++#define CFG_LOAD_ADDR 0xa0030000 /* default load address */
++
++#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
++#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
++
++ /* valid baudrates */
++#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
++#define CFG_MMC_BASE 0xF0000000
++
++/*
++ * Stack sizes
++ *
++ * The stack sizes are set up in start.S using the settings below
++ */
++#define CONFIG_STACKSIZE (128*1024) /* regular stack */
++#ifdef CONFIG_USE_IRQ
++#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
++#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
++#endif
++
++/*
++ * Physical Memory Map
++ */
++#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
++#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
++#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
++
++#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
++#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
++#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
++#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
++#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
++
++#define CFG_DRAM_BASE 0xa0000000
++#define CFG_DRAM_SIZE 0x04000000
++
++
++/*
++ * Memory settings
++ */
++#define CFG_MSC0_VAL 0x23F223F2
++#define CFG_MSC1_VAL 0x3FF1A441
++#define CFG_MSC2_VAL 0x7FF97FF1
++#define CFG_MDCNFG_VAL 0x00001AC9
++#define CFG_MDREFR_VAL 0x00018018
++#define CFG_MDMRS_VAL 0x00000000
++
++/*
++ * FLASH and environment organization
++ */
++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
++#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
++
++/* timeout values are in ticks */
++#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
++#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
++
++/*
++ * Environment is saved in flash at offset 1MB
++ */
++#define CFG_ENV_IS_IN_FLASH 1
++#define CFG_FLASH_BASE 0
++#define CFG_ENV_ADDR ((CFG_FLASH_BASE)+0x100000) /* Addr of Environment Sector */
++#define CFG_ENV_OFFSET ((CFG_ENV_ADDR)-(CFG_FLASH_BASE))
++#define CFG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */
++
++/*
++ * GPIO settings
++ */
++#define CFG_GPSR0_VAL 0x00008000
++#define CFG_GPSR1_VAL 0x00FC0382
++#define CFG_GPSR2_VAL 0x0001FFFF
++#define CFG_GPCR0_VAL 0x00000000
++#define CFG_GPCR1_VAL 0x00000000
++#define CFG_GPCR2_VAL 0x00000000
++#define CFG_GPDR0_VAL 0x0060A800
++#define CFG_GPDR1_VAL 0x00FF0382
++#define CFG_GPDR2_VAL 0x0001C000
++#define CFG_GAFR0_L_VAL 0x98400000
++#define CFG_GAFR0_U_VAL 0x00002950
++#define CFG_GAFR1_L_VAL 0x000A9558
++#define CFG_GAFR1_U_VAL 0x0005AAAA
++#define CFG_GAFR2_L_VAL 0xA0000000
++#define CFG_GAFR2_U_VAL 0x00000002
++
++#define CFG_PSSR_VAL 0x20
++
++/*
++ * PCMCIA and CF Interfaces
++ */
++#define CFG_MECR_VAL 0x00000000
++#define CFG_MCMEM0_VAL 0x00010504
++#define CFG_MCMEM1_VAL 0x00010504
++#define CFG_MCATT0_VAL 0x00010504
++#define CFG_MCATT1_VAL 0x00010504
++#define CFG_MCIO0_VAL 0x00004715
++#define CFG_MCIO1_VAL 0x00004715
++
++#ifndef __ASSEMBLY__
++
++extern unsigned long const fbStart ;
++extern unsigned long paletteRegs ;
++
++#endif /* _ASMLANGUAGE */
++
++#endif
++
+diff -u -r --new-file u-boot-1.1.2/include/fat.h u-boot-1.1.2-neon/include/fat.h
+--- u-boot-1.1.2/include/fat.h 2004-04-23 22:32:07.000000000 +0200
++++ u-boot-1.1.2-neon/include/fat.h 2007-08-11 21:07:21.000000000 +0200
+@@ -177,13 +177,13 @@
+
+ /* Private filesystem parameters */
+ typedef struct {
++ __u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */
+ int fatsize; /* Size of FAT in bits */
+ __u16 fatlength; /* Length of FAT in sectors */
+ __u16 fat_sect; /* Starting sector of the FAT */
+ __u16 rootdir_sect; /* Start sector of root directory */
+ __u16 clust_size; /* Size of clusters in sectors */
+ short data_begin; /* The sector of the first cluster, can be negative */
+- __u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */
+ int fatbufnum; /* Used by get_fatent, init to -1 */
+ } fsdata;
+
+diff -u -r --new-file u-boot-1.1.2/include/lcd.h u-boot-1.1.2-neon/include/lcd.h
+--- u-boot-1.1.2/include/lcd.h 2004-10-10 01:26:01.000000000 +0200
++++ u-boot-1.1.2-neon/include/lcd.h 2007-08-11 21:07:21.000000000 +0200
+@@ -31,7 +31,6 @@
+
+ extern char lcd_is_enabled;
+
+-extern int lcd_line_length;
+ extern int lcd_color_fg;
+ extern int lcd_color_bg;
+
+@@ -53,6 +52,7 @@
+ ushort vl_row; /* Number of rows (i.e. 480) */
+ ushort vl_width; /* Width of display area in millimeters */
+ ushort vl_height; /* Height of display area in millimeters */
++ int vl_lcd_line_length;
+
+ /* LCD configuration register */
+ u_char vl_clkp; /* Clock polarity */
+@@ -77,7 +77,7 @@
+
+ extern vidinfo_t panel_info;
+
+-#elif defined CONFIG_PXA250
++#elif defined( PXALCD )
+ /*
+ * PXA LCD DMA descriptor
+ */
+@@ -119,6 +119,7 @@
+ ushort vl_row; /* Number of rows (i.e. 480) */
+ ushort vl_width; /* Width of display area in millimeters */
+ ushort vl_height; /* Height of display area in millimeters */
++ int vl_lcd_line_length;
+
+ /* LCD configuration register */
+ u_char vl_clkp; /* Clock polarity */
+@@ -148,7 +149,29 @@
+
+ extern vidinfo_t panel_info;
+
+-#endif /* CONFIG_MPC823 or CONFIG_PXA250 */
++#if defined( CONFIG_PXA250 )
++ #define PALETTEVAL_TYPE u16
++#elif defined( CONFIG_PXA270 )
++ #define PALETTEVAL_TYPE u32
++#else
++#error no processor defined
++#endif
++
++#elif defined( CONFIG_SM501 )
++
++/*
++ * LCD controller stucture for PXA CPU
++ */
++typedef struct vidinfo {
++ ushort vl_col; /* Number of columns (i.e. 640) */
++ ushort vl_row; /* Number of rows (i.e. 480) */
++ int vl_lcd_line_length;
++ u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
++} vidinfo_t;
++
++extern vidinfo_t panel_info;
++
++#endif /* CONFIG_MPC823 */
+
+ /* Video functions */
+
+@@ -272,7 +295,7 @@
+ #endif
+
+ #define CONSOLE_COLS (panel_info.vl_col / VIDEO_FONT_WIDTH)
+-#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * lcd_line_length)
++#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * panel_info.vl_lcd_line_length)
+ #define CONSOLE_ROW_FIRST (lcd_console_address)
+ #define CONSOLE_ROW_SECOND (lcd_console_address + CONSOLE_ROW_SIZE)
+ #define CONSOLE_ROW_LAST (lcd_console_address + CONSOLE_SIZE \
+diff -u -r --new-file u-boot-1.1.2/include/lcd_panels.h u-boot-1.1.2-neon/include/lcd_panels.h
+--- u-boot-1.1.2/include/lcd_panels.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/include/lcd_panels.h 2007-08-11 21:07:21.000000000 +0200
+@@ -0,0 +1,83 @@
++#ifndef __LCD_PANELS_H__
++#define __LCD_PANELS_H__ "$Id: lcd_panels.h,v 1.3 2005/06/02 04:03:37 ericn Exp $"
++
++/*
++ * lcd_panels.h
++ *
++ * This header file declares the lcd_panel_info_t
++ * data type and the num_lcd_panels and lcd_panels
++ * constants for use in initializing a variety of displays.
++ *
++ * Note that this is based on the pxafb_mach_info structure
++ * in linux-2.4.19/drivers/video/pxafb.h (Nico's patches),
++ * but differs in a couple of respects:
++ *
++ * Doesn't support the color-mapping stuff
++ * Includes an 'active' flag
++ *
++ * Doesn't include the lccr0 and lccr3 fields, since most of
++ * the fields in those registers are display controller options,
++ * not panel options, and the others (so far) can have reasonable
++ * defaults. When (if) we need to support a non-standard display,
++ * we can fill in the blanks with defaults in the previously
++ * supported displays and compute lccr0 and lccr3.
++ *
++ * Change History :
++ *
++ * $Log: lcd_panels.h,v $
++ * Revision 1.3 2005/06/02 04:03:37 ericn
++ * -added rotation field
++ *
++ * Revision 1.2 2005/04/30 20:33:36 ericn
++ * -added CRT support
++ *
++ * Revision 1.1 2005/04/09 17:49:18 ericn
++ * -Initial import
++ *
++ *
++ * Copyright Boundary Devices, Inc. 2005
++ */
++
++struct lcd_panel_info_t {
++ char const *name ;
++ unsigned long pixclock;
++
++ unsigned short xres;
++ unsigned short yres;
++
++ unsigned act_high ; // clock is active high
++ unsigned hsync_len;
++ unsigned left_margin;
++ unsigned right_margin;
++ unsigned vsync_len;
++ unsigned upper_margin;
++ unsigned lower_margin;
++ unsigned active ; // active matrix (TFT) LCD
++ unsigned crt ; // 1 == CRT, not LCD
++ unsigned rotation ;
++};
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++extern unsigned const num_lcd_panels ;
++extern struct lcd_panel_info_t const * const lcd_panels ;
++
++extern struct lcd_panel_info_t const *find_lcd_panel( char const * name );
++
++
++//
++// Each platform needs to define this routine, and
++// set cur_lcd_panel within
++//
++void set_lcd_panel( struct lcd_panel_info_t const *panel );
++extern struct lcd_panel_info_t const *cur_lcd_panel ;
++void disable_lcd_panel( void );
++
++#ifdef __CPLUSPLUS
++};
++#endif
++
++#endif
++
+diff -u -r --new-file u-boot-1.1.2/include/part.h u-boot-1.1.2-neon/include/part.h
+--- u-boot-1.1.2/include/part.h 2004-04-18 19:39:40.000000000 +0200
++++ u-boot-1.1.2-neon/include/part.h 2007-08-11 21:07:21.000000000 +0200
+@@ -24,6 +24,48 @@
+ #define _PART_H
+ #include <ide.h>
+
++enum {
++/* These three have identical behaviour; use the second one if DOS fdisk gets
++ confused about extended/logical partitions starting past cylinder 1023. */
++ DOS_EXTENDED_PARTITION = 5,
++ LINUX_EXTENDED_PARTITION = 0x85,
++ WIN98_EXTENDED_PARTITION = 0x0f,
++
++ LINUX_SWAP_PARTITION = 0x82,
++ LINUX_RAID_PARTITION = 0xfd, /* autodetect RAID partition */
++
++ SOLARIS_X86_PARTITION = LINUX_SWAP_PARTITION,
++
++ DM6_PARTITION = 0x54, /* has DDO: use xlated geom & offset */
++ EZD_PARTITION = 0x55, /* EZ-DRIVE */
++ DM6_AUX1PARTITION = 0x51, /* no DDO: use xlated geom */
++ DM6_AUX3PARTITION = 0x53, /* no DDO: use xlated geom */
++
++ FREEBSD_PARTITION = 0xa5, /* FreeBSD Partition ID */
++ OPENBSD_PARTITION = 0xa6, /* OpenBSD Partition ID */
++ NETBSD_PARTITION = 0xa9, /* NetBSD Partition ID */
++ BSDI_PARTITION = 0xb7, /* BSDI Partition ID */
++/* Ours is not to wonder why.. */
++ BSD_PARTITION = FREEBSD_PARTITION,
++ MINIX_PARTITION = 0x81, /* Minix Partition ID */
++ PLAN9_PARTITION = 0x39, /* Plan 9 Partition ID */
++ UNIXWARE_PARTITION = 0x63, /* Partition ID, same as */
++ /* GNU_HURD and SCO Unix */
++};
++
++struct partition {
++ unsigned char boot_ind; /* 0x80 - active */
++ unsigned char head; /* starting head */
++ unsigned char sector; /* starting sector */
++ unsigned char cyl; /* starting cylinder */
++ unsigned char sys_ind; /* What partition type */
++ unsigned char end_head; /* end head */
++ unsigned char end_sector; /* end sector */
++ unsigned char end_cyl; /* end cylinder */
++ unsigned int start_sect; /* starting sector counting from 0 */
++ unsigned int nr_sects; /* nr of sectors in partition */
++} __attribute__((packed));
++
+ typedef struct block_dev_desc {
+ int if_type; /* type of the interface */
+ int dev; /* device number */
+@@ -118,4 +160,15 @@
+ int test_part_amiga (block_dev_desc_t *dev_desc);
+ #endif
+
++/* Value returned by `fnmatch' if STRING does not match PATTERN. */
++#define FNM_NOMATCH 1
++
++/* Bits set in the FLAGS argument to `fnmatch'. */
++#define FNM_PATHNAME (1 << 0) /* No wildcard can ever match `/'. */
++#define FNM_NOESCAPE (1 << 1) /* Backslashes don't quote special chars. */
++#define FNM_PERIOD (1 << 2) /* Leading `.' is matched only explicitly. */
++#define FNM_NOSYS (-1)
++
++int fnmatch(const char *pattern, const char *string, int flags);
++
+ #endif /* _PART_H */
+diff -u -r --new-file u-boot-1.1.2/lib_arm/armlinux.c u-boot-1.1.2-neon/lib_arm/armlinux.c
+--- u-boot-1.1.2/lib_arm/armlinux.c 2004-10-10 01:26:01.000000000 +0200
++++ u-boot-1.1.2-neon/lib_arm/armlinux.c 2007-08-11 21:07:21.000000000 +0200
+@@ -29,6 +29,7 @@
+ #ifdef CONFIG_HAS_DATAFLASH
+ #include <dataflash.h>
+ #endif
++#include "lcd_panels.h"
+
+ /*cmd_boot.c*/
+ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+@@ -88,6 +89,16 @@
+
+ #ifdef CONFIG_CMDLINE_TAG
+ char *commandline = getenv ("bootargs");
++ if( ( 0 != cur_lcd_panel ) && ( 0 != cur_lcd_panel->rotation ) )
++ {
++ char temp[80];
++ int addedLen = sprintf( temp, " fbrotation=%u", cur_lcd_panel->rotation );
++ unsigned cmdLen = strlen( commandline );
++ char *bigger = (char *)malloc( cmdLen + addedLen + 1 );
++ strcpy( bigger, commandline );
++ strcpy( bigger+cmdLen, temp );
++ commandline = bigger ;
++ }
+ #endif
+
+ theKernel = (void (*)(int, int, uint))ntohl(hdr->ih_ep);
+@@ -365,6 +376,7 @@
+ * We only use it to pass the address and size, the other entries
+ * in the tag_videolfb are not of interest.
+ */
++#ifdef VESA_DISPLAY
+ params->hdr.tag = ATAG_VIDEOLFB;
+ params->hdr.size = tag_size (tag_videolfb);
+
+@@ -374,6 +386,7 @@
+ params->u.videolfb.lfb_size = calc_fbsize();
+
+ params = tag_next (params);
++#endif
+ }
+ #endif /* CONFIG_VFD || CONFIG_LCD */
+
+diff -u -r --new-file u-boot-1.1.2/lib_arm/board.c u-boot-1.1.2-neon/lib_arm/board.c
+--- u-boot-1.1.2/lib_arm/board.c 2004-08-02 00:48:22.000000000 +0200
++++ u-boot-1.1.2-neon/lib_arm/board.c 2007-08-11 21:07:21.000000000 +0200
+@@ -216,7 +216,10 @@
+ #endif
+
+ /* Pointer is writable since we allocated a register for it */
+- gd = (gd_t*)(_armboot_start - CFG_MALLOC_LEN - sizeof(gd_t));
++#ifndef CFG_MMU_SPACE_RESERVED
++#define CFG_MMU_SPACE_RESERVED 0
++#endif
++ gd = (gd_t*)(_armboot_start - CFG_MMU_SPACE_RESERVED - CFG_MALLOC_LEN - sizeof(gd_t));
+ /* compiler optimization barrier needed for GCC >= 3.4 */
+ __asm__ __volatile__("": : :"memory");
+
+@@ -263,7 +266,7 @@
+ #endif /* CONFIG_LCD */
+
+ /* armboot_start is defined in the board-specific linker script */
+- mem_malloc_init (_armboot_start - CFG_MALLOC_LEN);
++ mem_malloc_init (_armboot_start - CFG_MMU_SPACE_RESERVED - CFG_MALLOC_LEN);
+
+ #if (CONFIG_COMMANDS & CFG_CMD_NAND)
+ puts ("NAND:");
+diff -u -r --new-file u-boot-1.1.2/make_all u-boot-1.1.2-neon/make_all
+--- u-boot-1.1.2/make_all 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/make_all 2007-08-11 21:07:21.000000000 +0200
+@@ -0,0 +1,31 @@
++#!/bin/sh
++halogen1_clock="416"
++halogen2_clock="416"
++bd2003_clock="400"
++neon_clock="400"
++neonb_clock="400"
++
++SOFTWARE="LINUX"
++
++targets="halogen1 halogen2 bd2003 neon neonb"
++for suff in $targets ; do
++ make distclean ;
++ REV=""
++ PLATFORM="$suff"
++ if [ $suff = "halogen1" ] ; then REV="1\n"; PLATFORM="halogen"
++ else
++ if [ $suff = "halogen2" ] ; then REV="2\n"; PLATFORM="halogen"
++ fi
++ fi
++ eval clock=\$$suff"_clock"
++ echo -e "DA640X240\n$REV$SOFTWARE\ny\n$clock\n" | make $PLATFORM"_config" ;
++ make u-boot.bin ;
++ mv u-boot.bin u-boot-$suff
++done
++
++
++for suff in $targets ; do
++ mv u-boot-$suff u-boot-$suff.bin
++done
++
++zip u-boot-binaries.zip u-boot-*.bin
+diff -u -r --new-file u-boot-1.1.2/Makefile u-boot-1.1.2-neon/Makefile
+--- u-boot-1.1.2/Makefile 2004-12-19 10:58:11.000000000 +0100
++++ u-boot-1.1.2-neon/Makefile 2007-08-11 21:17:14.000000000 +0200
+@@ -57,7 +57,7 @@
+ CROSS_COMPILE = ppc_8xx-
+ endif
+ ifeq ($(ARCH),arm)
+-CROSS_COMPILE = arm-linux-
++CROSS_COMPILE = arm-elf-
+ endif
+ ifeq ($(ARCH),i386)
+ ifeq ($(HOSTARCH),i386)
+@@ -89,6 +89,9 @@
+ #########################################################################
+ # U-Boot objects....order is important (i.e. start must be first)
+
++ifeq ($(CPU),pxa)
++OBJS =
++else
+ OBJS = cpu/$(CPU)/start.o
+ ifeq ($(CPU),i386)
+ OBJS += cpu/$(CPU)/start16.o
+@@ -100,6 +103,7 @@
+ ifeq ($(CPU),mpc85xx)
+ OBJS += cpu/$(CPU)/resetvec.o
+ endif
++endif
+
+ LIBS = lib_generic/libgeneric.a
+ LIBS += board/$(BOARDDIR)/lib$(BOARD).a
+@@ -121,7 +125,8 @@
+ .PHONY : $(LIBS)
+
+ # Add GCC lib
+-PLATFORM_LIBS += --no-warn-mismatch -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
++LIBGCC_DIRNAME := $(shell dirname "`$(CC) $(CFLAGS) -print-libgcc-file-name`")
++PLATFORM_LIBS += --no-warn-mismatch -L "$(LIBGCC_DIRNAME)" -lgcc
+
+
+ # The "tools" are needed early, so put this first
+@@ -129,13 +134,14 @@
+ SUBDIRS = tools \
+ examples \
+ post \
+- post/cpu
++ post/cpu \
++ cpu/$(CPU)
+ .PHONY : $(SUBDIRS)
+
+ #########################################################################
+ #########################################################################
+
+-ALL = u-boot.srec u-boot.bin System.map
++ALL = u-boot.srec u-boot.bin System.map init.scr upgrade.scr
+
+ all: $(ALL)
+
+@@ -192,6 +198,12 @@
+ grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
+ sort > System.map
+
++init.scr: board/$(BOARDDIR)/init.script
++ tools/mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "autoscript" -d $< $@
++
++upgrade.scr: upgrade.script
++ tools/mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "U-Boot upgrade script" -d $< $@
++
+ #########################################################################
+ else
+ all install u-boot u-boot.srec depend dep:
+@@ -203,6 +215,7 @@
+
+ unconfig:
+ @rm -f include/config.h include/config.mk board/*/config.tmp
++ @rm -f select.mk include/configs/select.h
+
+ #========================================================================
+ # PowerPC
+@@ -1388,6 +1401,22 @@
+ wepep250_config : unconfig
+ @./mkconfig $(@:_config=) arm pxa wepep250
+
++bd-neon_config : unconfig
++ @./mkconfig $(@:_config=) arm pxa neon
++ ./Configure --PLATFORM_TYPE=NEON
++
++neonb_config : unconfig
++ @./mkconfig neon arm pxa neon
++ ./Configure --PLATFORM_TYPE=NEONB --SOFTWARE_TYPE=WINCE --DISPLAY_TYPE=DA640X240
++
++bd2003_config : unconfig
++ @./mkconfig $(@:_config=) arm pxa bd2003
++ ./Configure --PLATFORM_TYPE=BD2003
++
++halogen_config : unconfig
++ @./mkconfig $(@:_config=) arm pxa halogen
++ ./Configure --PLATFORM_TYPE=HALOGEN
++
+ xaeniax_config : unconfig
+ @./mkconfig $(@:_config=) arm pxa xaeniax
+
+@@ -1558,10 +1587,16 @@
+ #########################################################################
+ #########################################################################
+
++ifeq ($(HOSTOS),cygwin)
++FIND = /bin/find
++else
++FIND = find
++endif
++
+ clean:
+- find . -type f \
++ $(FIND) . -type f \
+ \( -name 'core' -o -name '*.bak' -o -name '*~' \
+- -o -name '*.o' -o -name '*.a' \) -print \
++ -o -name '*.o' -o -name '*.a' -o -name '*.lst' \) -print \
+ | xargs rm -f
+ rm -f examples/hello_world examples/timer \
+ examples/eepro100_eeprom examples/sched \
+@@ -1575,7 +1610,7 @@
+ rm -f board/trab/trab_fkt
+
+ clobber: clean
+- find . -type f \( -name .depend \
++ $(FIND) . -type f \( -name .depend \
+ -o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
+ -print0 \
+ | xargs -0 rm -f
+@@ -1585,6 +1620,8 @@
+ rm -f tools/crc32.c tools/environment.c tools/env/crc32.c
+ rm -f tools/inca-swap-bytes cpu/mpc824x/bedbug_603e.c
+ rm -f include/asm/proc include/asm/arch include/asm
++ cd tools && rm -f *.exe
++ rm -f include/configs/select.h select.mk select.log
+
+ mrproper \
+ distclean: clobber unconfig
+diff -u -r --new-file u-boot-1.1.2/patches/arm_flags.patch u-boot-1.1.2-neon/patches/arm_flags.patch
+--- u-boot-1.1.2/patches/arm_flags.patch 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/patches/arm_flags.patch 2007-08-11 21:01:36.000000000 +0200
+@@ -0,0 +1,15 @@
++
++#
++# Patch managed by http://www.holgerschurig.de/patcher.html
++#
++
++--- u-boot-1.1.2/cpu/pxa/config.mk~armflags
+++++ u-boot-1.1.2/cpu/pxa/config.mk
++@@ -23,6 +23,6 @@
++ #
++
++ PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
++- -mshort-load-bytes -msoft-float
+++ -msoft-float
++
++ PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100
+diff -u -r --new-file u-boot-1.1.2/README u-boot-1.1.2-neon/README
+--- u-boot-1.1.2/README 2004-12-16 22:44:03.000000000 +0100
++++ u-boot-1.1.2-neon/README 2007-08-11 21:07:19.000000000 +0200
+@@ -608,6 +608,7 @@
+ CFG_CMD_ITEST Integer/string test of 2 values
+ CFG_CMD_JFFS2 * JFFS2 Support
+ CFG_CMD_KGDB * kgdb
++ CFG_CMD_LCDPANEL * Dynamic LCD Panel support
+ CFG_CMD_LOADB loadb
+ CFG_CMD_LOADS loads
+ CFG_CMD_MEMORY md, mm, nm, mw, cp, cmp, crc, base,
+@@ -812,6 +813,9 @@
+ for differential drivers: 0x00001000
+ for single ended drivers: 0x00005000
+
++- Dynamic LCD Panel support
++ Allows the choice of an LCD panel through the environment.
++ Also allows prompting for panel characteristics.
+
+ - MMC Support:
+ The MMC controller on the Intel PXA is supported. To
+diff -u -r --new-file u-boot-1.1.2/tools/mkimage.c u-boot-1.1.2-neon/tools/mkimage.c
+--- u-boot-1.1.2/tools/mkimage.c 2004-11-21 01:06:36.000000000 +0100
++++ u-boot-1.1.2-neon/tools/mkimage.c 2007-08-11 21:07:22.000000000 +0200
+@@ -618,10 +618,10 @@
+ printf ("Image Name: %.*s\n", IH_NMLEN, hdr->ih_name);
+ printf ("Created: %s", ctime(&timestamp));
+ printf ("Image Type: "); print_type(hdr);
+- printf ("Data Size: %d Bytes = %.2f kB = %.2f MB\n",
++ printf ("Data Size: %ld Bytes = %.2f kB = %.2f MB\n",
+ size, (double)size / 1.024e3, (double)size / 1.048576e6 );
+- printf ("Load Address: 0x%08X\n", ntohl(hdr->ih_load));
+- printf ("Entry Point: 0x%08X\n", ntohl(hdr->ih_ep));
++ printf ("Load Address: 0x%08lX\n", ntohl(hdr->ih_load));
++ printf ("Entry Point: 0x%08lX\n", ntohl(hdr->ih_ep));
+
+ if (hdr->ih_type == IH_TYPE_MULTI || hdr->ih_type == IH_TYPE_SCRIPT) {
+ int i, ptrs;
+@@ -640,7 +640,7 @@
+ for (i=0; len_ptr[i]; ++i) {
+ size = ntohl(len_ptr[i]);
+
+- printf (" Image %d: %8d Bytes = %4d kB = %d MB\n",
++ printf (" Image %d: %8ld Bytes = %4ld kB = %ld MB\n",
+ i, size, size>>10, size>>20);
+ if (hdr->ih_type == IH_TYPE_SCRIPT && i > 0) {
+ /*
+@@ -648,7 +648,7 @@
+ * if planning to do something with
+ * multiple files
+ */
+- printf (" Offset = %08X\n", pos);
++ printf (" Offset = %08lX\n", pos);
+ }
+ /* copy_file() will pad the first files to even word align */
+ size += 3;
+diff -u -r --new-file u-boot-1.1.2/upgrade.script u-boot-1.1.2-neon/upgrade.script
+--- u-boot-1.1.2/upgrade.script 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.2-neon/upgrade.script 2007-08-11 21:07:22.000000000 +0200
+@@ -0,0 +1,32 @@
++lecho "---------> upgrade to newest U-Boot"
++echo "---------> upgrade to newest U-Boot"
++if fatload mmc 0 a0008000 u-boot-*.bin ; then
++ if cmp.b 0 a0008000 $filesize ; then
++ fatload mmc 0 a0008000 *.bmp
++ bmp display a0008000
++ lecho 'Already upgraded. Latest U-Boot is installed' ;
++ echo 'Already upgraded. Latest U-Boot is installed' ;
++ if mmcwp ; then
++ lecho "write protected" ;
++ else
++ lecho "not write protected" ;
++ fi
++ else
++ lecho 'Old U-Boot found. Upgrading' ;
++ echo 'Old U-Boot found. Upgrading' ;
++ protect off all ;
++ lecho 'Erasing' ;
++ echo 'Erasing' ;
++ erase 0 3FFFF ;
++ lecho 'Programming' ;
++ echo 'Programming' ;
++ cp.b a0008000 0 $filesize ;
++ lecho 'Done programming. Cycle power' ;
++ echo 'Done programming. Cycle power' ;
++ fi
++else
++ lecho 'Error loading new U-Boot from SD card'
++ echo 'Error loading new U-Boot from SD card'
++ lecho 'Should have u-boot-neon-something.bin'
++ echo 'Should have u-boot-neon-something.bin'
++fi
+\ No newline at end of file
diff --git a/recipes/u-boot/u-boot-1.1.2/u-boot-emetec.patch b/recipes/u-boot/u-boot-1.1.2/u-boot-emetec.patch
new file mode 100644
index 0000000000..ab3f106e71
--- /dev/null
+++ b/recipes/u-boot/u-boot-1.1.2/u-boot-emetec.patch
@@ -0,0 +1,2170 @@
+diff -uNr u-boot-1.1.2/.pc/.version u-boot-emetec-1.1.2/.pc/.version
+--- u-boot-1.1.2/.pc/.version 2007-04-20 00:01:06.000000000 +0300
++++ u-boot-emetec-1.1.2/.pc/.version 1970-01-01 02:00:00.000000000 +0200
+@@ -1 +0,0 @@
+-2
+diff -uNr u-boot-1.1.2/.pc/applied-patches u-boot-emetec-1.1.2/.pc/applied-patches
+--- u-boot-1.1.2/.pc/applied-patches 2007-04-20 00:01:06.000000000 +0300
++++ u-boot-emetec-1.1.2/.pc/applied-patches 1970-01-01 02:00:00.000000000 +0200
+@@ -1 +0,0 @@
+-arm_flags.patch
+diff -uNr u-boot-1.1.2/.pc/arm_flags.patch/cpu/pxa/config.mk u-boot-emetec-1.1.2/.pc/arm_flags.patch/cpu/pxa/config.mk
+--- u-boot-1.1.2/.pc/arm_flags.patch/cpu/pxa/config.mk 2003-05-23 15:36:21.000000000 +0300
++++ u-boot-emetec-1.1.2/.pc/arm_flags.patch/cpu/pxa/config.mk 1970-01-01 02:00:00.000000000 +0200
+@@ -1,28 +0,0 @@
+-#
+-# (C) Copyright 2002
+-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+-# Marius Groeger <mgroeger@sysgo.de>
+-#
+-# See file CREDITS for list of people who contributed to this
+-# project.
+-#
+-# This program is free software; you can redistribute it and/or
+-# modify it under the terms of the GNU General Public License as
+-# published by the Free Software Foundation; either version 2 of
+-# the License, or (at your option) any later version.
+-#
+-# This program is distributed in the hope that it will be useful,
+-# but WITHOUT ANY WARRANTY; without even the implied warranty of
+-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-# GNU General Public License for more details.
+-#
+-# You should have received a copy of the GNU General Public License
+-# along with this program; if not, write to the Free Software
+-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+-# MA 02111-1307 USA
+-#
+-
+-PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
+- -mshort-load-bytes -msoft-float
+-
+-PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100
+diff -uNr u-boot-1.1.2/MAKEALL u-boot-emetec-1.1.2/MAKEALL
+--- u-boot-1.1.2/MAKEALL 2004-12-31 11:32:48.000000000 +0200
++++ u-boot-emetec-1.1.2/MAKEALL 2005-03-11 22:23:47.000000000 +0200
+@@ -69,7 +69,7 @@
+ ml300 OCOTEA OCRTC ORSG \
+ PCI405 PIP405 PLU405 PMC405 \
+ PPChameleonEVB VOH405 W7OLMC W7OLMG \
+- WALNUT405 WUH405 XPEDITE1K \
++ WALNUT405 WUH405 XPEDITE1K EMETEC405 \
+ "
+
+ #########################################################################
+diff -uNr u-boot-1.1.2/Makefile u-boot-emetec-1.1.2/Makefile
+--- u-boot-1.1.2/Makefile 2004-12-19 11:58:11.000000000 +0200
++++ u-boot-emetec-1.1.2/Makefile 2005-03-14 22:43:56.000000000 +0200
+@@ -54,7 +54,7 @@
+ CROSS_COMPILE =
+ else
+ ifeq ($(ARCH),ppc)
+-CROSS_COMPILE = ppc_8xx-
++CROSS_COMPILE = ppc_4xx-
+ endif
+ ifeq ($(ARCH),arm)
+ CROSS_COMPILE = arm-linux-
+@@ -127,7 +127,6 @@
+ # The "tools" are needed early, so put this first
+ # Don't include stuff already done in $(LIBS)
+ SUBDIRS = tools \
+- examples \
+ post \
+ post/cpu
+ .PHONY : $(SUBDIRS)
+@@ -838,6 +837,9 @@
+
+ VOM405_config: unconfig
+ @./mkconfig $(@:_config=) ppc ppc4xx vom405 esd
++
++EMETEC405_config: unconfig
++ @./mkconfig $(@:_config=) ppc ppc4xx emetec405
+
+ W7OLMC_config \
+ W7OLMG_config: unconfig
+diff -uNr u-boot-1.1.2/board/emetec405/Makefile u-boot-emetec-1.1.2/board/emetec405/Makefile
+--- u-boot-1.1.2/board/emetec405/Makefile 1970-01-01 02:00:00.000000000 +0200
++++ u-boot-emetec-1.1.2/board/emetec405/Makefile 2005-04-26 22:34:53.000000000 +0300
+@@ -0,0 +1,46 @@
++#
++# (C) Copyright 2000
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = lib$(BOARD).a
++
++OBJS = $(BOARD).o flash.o
++
++$(LIB): $(OBJS) $(SOBJS)
++ $(AR) crv $@ $(OBJS)
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
++ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
++
++sinclude .depend
++
++#########################################################################
+diff -uNr u-boot-1.1.2/board/emetec405/config.mk u-boot-emetec-1.1.2/board/emetec405/config.mk
+--- u-boot-1.1.2/board/emetec405/config.mk 1970-01-01 02:00:00.000000000 +0200
++++ u-boot-emetec-1.1.2/board/emetec405/config.mk 2005-03-11 22:26:43.000000000 +0200
+@@ -0,0 +1,28 @@
++#
++# (C) Copyright 2000
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++#
++# emetec EMETEC405 boards
++#
++
++TEXT_BASE = 0xFFFC0000
+diff -uNr u-boot-1.1.2/board/emetec405/emetec405.c u-boot-emetec-1.1.2/board/emetec405/emetec405.c
+--- u-boot-1.1.2/board/emetec405/emetec405.c 1970-01-01 02:00:00.000000000 +0200
++++ u-boot-emetec-1.1.2/board/emetec405/emetec405.c 2005-04-26 23:02:01.000000000 +0300
+@@ -0,0 +1,106 @@
++/*
++ * (C) Copyright 2001-2003
++ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/processor.h>
++#include <command.h>
++#include <malloc.h>
++
++
++int board_early_init_f (void)
++{
++ /*-------------------------------------------------------------------------+
++ | Interrupt controller setup for the Walnut board.
++ | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
++ | IRQ 16 405GP internally generated; active low; level sensitive
++ | IRQ 17-24 RESERVED
++ | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
++ | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
++ | IRQ 27 (EXT IRQ 2) Not Used
++ | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
++ | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
++ | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
++ | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
++ | Note for Walnut board:
++ | An interrupt taken for the FPGA (IRQ 25) indicates that either
++ | the Mouse, Keyboard, IRDA, or External Expansion caused the
++ | interrupt. The FPGA must be read to determine which device
++ | caused the interrupt. The default setting of the FPGA clears
++ |
++ +-------------------------------------------------------------------------*/
++
++ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
++ mtdcr (uicer, 0x00000000); /* disable all ints */
++ mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
++ mtdcr (uicpr, 0xFFFFFFE0); /* set int polarities */
++ mtdcr (uictr, 0x10000000); /* set int trigger levels */
++ mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
++ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
++
++ return 0;
++}
++
++
++int misc_init_f (void)
++{
++ return 0; /* dummy implementation */
++}
++
++
++int misc_init_r (void)
++{
++ return 0; /* dummy implementation */
++}
++
++
++/*
++ * Check Board Identity:
++ */
++int checkboard (void)
++{
++ unsigned char str[64];
++
++ puts ("Board: MAGICBOX\n");
++
++ return 0;
++}
++
++
++long int initdram (int board_type)
++{
++ unsigned long val;
++
++ mtdcr(memcfga, mem_mb0cf);
++ val = mfdcr(memcfgd);
++
++ return (4*1024*1024 << ((val & 0x000e0000) >> 17));
++}
++
++
++int testdram (void)
++{
++ printf ("test: 32 MB - ok\n");
++
++ return (0);
++}
++
+diff -uNr u-boot-1.1.2/board/emetec405/flash.c u-boot-emetec-1.1.2/board/emetec405/flash.c
+--- u-boot-1.1.2/board/emetec405/flash.c 1970-01-01 02:00:00.000000000 +0200
++++ u-boot-emetec-1.1.2/board/emetec405/flash.c 2005-05-25 10:14:13.000000000 +0300
+@@ -0,0 +1,544 @@
++/*
++ * (C) Copyright 2000
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#include <common.h>
++#include <ppc4xx.h>
++#include <asm/processor.h>
++
++flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
++
++/*-----------------------------------------------------------------------
++ * Functions
++ */
++static ulong flash_get_size (vu_long * addr, flash_info_t * info);
++static void flash_get_offsets (ulong base, flash_info_t * info);
++
++/*-----------------------------------------------------------------------
++ */
++unsigned long flash_init (void)
++{
++ unsigned long size_b0;
++ int i;
++ uint pbcr;
++ unsigned long base_b0;
++ int size_val = 0;
++
++ /* Init: no FLASHes known */
++ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
++ flash_info[i].flash_id = FLASH_UNKNOWN;
++ }
++
++ /* Static FLASH Bank configuration here - FIXME XXX */
++
++ size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
++
++ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
++ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
++ size_b0, size_b0<<20);
++ }
++
++ /* Setup offsets */
++ flash_get_offsets (-size_b0, &flash_info[0]);
++
++ /* Re-do sizing to get full correct info */
++ mtdcr(ebccfga, pb0cr);
++ pbcr = mfdcr(ebccfgd);
++ mtdcr(ebccfga, pb0cr);
++ base_b0 = -size_b0;
++ switch (size_b0) {
++ case 1 << 20:
++ size_val = 0;
++ break;
++ case 2 << 20:
++ size_val = 1;
++ break;
++ case 4 << 20:
++ size_val = 2;
++ break;
++ case 8 << 20:
++ size_val = 3;
++ break;
++ case 16 << 20:
++ size_val = 4;
++ break;
++ }
++ pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
++ mtdcr(ebccfgd, pbcr);
++
++ /* Monitor protection ON by default */
++ (void)flash_protect(FLAG_PROTECT_SET,
++ -CFG_MONITOR_LEN,
++ 0xffffffff,
++ &flash_info[0]);
++
++ flash_info[0].size = size_b0;
++
++ return (size_b0);
++}
++
++/*-----------------------------------------------------------------------
++ */
++static void flash_get_offsets (ulong base, flash_info_t *info)
++{
++ int i;
++ short n;
++
++ base += info->size;
++ i = info->sector_count;
++
++ switch (info->flash_id & FLASH_TYPEMASK)
++ {
++ case FLASH_STMW320DT :
++ /* 1 x 16k boot sector */
++ base -= 16 << 10;
++ --i;
++ info->start[i] = base;
++ /* 2 x 8k boot sectors */
++ for (n=0; n<2; ++n) {
++ base -= 8 << 10;
++ --i;
++ info->start[i] = base;
++ }
++ /* 1 x 32k boot sector */
++ base -= 32 << 10;
++ --i;
++ info->start[i] = base;
++ break;
++
++ case FLASH_STMW640DT :
++ /* 8 x 8k boot sectors */
++ for (n=0; n<8; ++n) {
++ base -= 8 << 10;
++ --i;
++ info->start[i] = base;
++ }
++ break;
++ };
++ /* 64k regular sectors */
++ while (i > 0) {
++ base -= 64 << 10;
++ --i;
++ info->start[i] = base;
++ }
++}
++
++/*-----------------------------------------------------------------------
++ */
++static ulong flash_get_size (vu_long *addr, flash_info_t *info)
++{
++ short i;
++ short n;
++ CFG_FLASH_WORD_SIZE value;
++ ulong base = (ulong)addr;
++ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
++
++ /* Write auto select command: read Manufacturer ID */
++ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
++ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
++ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090;
++
++ value = addr2[CFG_FLASH_READ0];
++
++ switch (value) {
++ case (CFG_FLASH_WORD_SIZE)SST_MANUFACT:
++ info->flash_id = FLASH_MAN_SST;
++ break;
++ case (CFG_FLASH_WORD_SIZE)STM_MANUFACT:
++ info->flash_id = FLASH_MAN_STM;
++ break;
++ default:
++ info->flash_id = FLASH_UNKNOWN;
++ info->sector_count = 0;
++ info->size = 0;
++ return (0);
++ }
++
++ value = addr2[CFG_FLASH_READ1]; /* device ID */
++
++ switch (value) {
++ case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
++ info->flash_id += FLASH_STMW320DT;
++ info->sector_count = 67;
++ info->size = 0x00400000;
++
++ /* set up sector start address table for FLASH_STMW320DT */
++ /* set sector offsets for top boot block type */
++ base += info->size;
++ i = info->sector_count;
++ /* 1 x 16k boot sector */
++ base -= 16 << 10;
++ --i;
++ info->start[i] = base;
++ /* 2 x 8k boot sectors */
++ for (n=0; n<2; ++n) {
++ base -= 8 << 10;
++ --i;
++ info->start[i] = base;
++ };
++ /* 1 x 32k boot sector */
++ base -= 32 << 10;
++ --i;
++ info->start[i] = base;
++
++ /* 64k regular sectors */
++ while (i > 0)
++ {
++ base -= 64 << 10;
++ --i;
++ info->start[i] = base;
++ };
++ break; /* => 4 MB */
++
++ case (CFG_FLASH_WORD_SIZE)STM_ID_29W640DT:
++ info->flash_id += FLASH_STMW640DT;
++ info->sector_count = 135;
++ info->size = 0x00800000;
++
++ /* set up sector start address table for FLASH_STMW640DT */
++ /* set sector offsets for top boot block type */
++ base += info->size;
++ i = info->sector_count;
++ /* 8 x 8k boot sectors */
++ for (n=0; n<8; ++n) {
++ base -= 8 << 10;
++ --i;
++ info->start[i] = base;
++ };
++
++ /* 64k regular sectors */
++ while (i > 0)
++ {
++ base -= 64 << 10;
++ --i;
++ info->start[i] = base;
++ };
++
++ break; /* => 8 MB */
++ default:
++ info->flash_id = FLASH_UNKNOWN;
++ return (0); /* => no or unknown flash */
++ }
++
++ /* check for protected sectors */
++ for (i = 0; i < info->sector_count; i++) {
++ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
++ /* D0 = 1 if protected */
++ addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
++ info->protect[i] = 0;
++ else
++ info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
++ }
++
++ /*
++ * Prevent writes to uninitialized FLASH.
++ */
++ if (info->flash_id != FLASH_UNKNOWN) {
++ addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0];
++ *addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
++ }
++
++ return (info->size);
++}
++
++/*-----------------------------------------------------------------------
++ */
++void flash_print_info (flash_info_t *info)
++{
++ int i;
++ int k;
++ int size;
++ int erased;
++ volatile unsigned long *flash;
++
++ switch (info->flash_id & FLASH_TYPEMASK)
++ {
++ case FLASH_STMW320DT :
++ printf ("ST M29W320DT (32 M, top sector)\n");
++ break;
++ case FLASH_STMW640DT :
++ printf ("ST M29W640DT (64 M, top sector)\n");
++ break;
++ default :
++ printf ("Missing or unknown FLASH type\n");
++ return;
++ };
++ printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
++
++ printf (" Sector Start Addresses:");
++ for (i=0; i<info->sector_count; ++i) {
++ /*
++ * Check if whole sector is erased
++ */
++ if (i != (info->sector_count-1))
++ size = info->start[i+1] - info->start[i];
++ else
++ size = info->start[0] + info->size - info->start[i];
++ erased = 1;
++ flash = (volatile unsigned long *)info->start[i];
++ size = size >> 2; /* divide by 4 for longword access */
++ for (k=0; k<size; k++)
++ {
++ if (*flash++ != 0xffffffff)
++ {
++ erased = 0;
++ break;
++ }
++ }
++
++ if ((i % 5) == 0)
++ printf ("\n ");
++ printf (" %08lX%s%s",
++ info->start[i],
++ erased ? " E" : " ",
++ info->protect[i] ? "RO " : " "
++ );
++ }
++ printf ("\n");
++ return;
++}
++
++/*-----------------------------------------------------------------------
++ */
++
++int flash_erase (flash_info_t *info, int s_first, int s_last)
++{
++ volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
++ volatile CFG_FLASH_WORD_SIZE *addr2;
++ int flag, prot, sect, l_sect;
++ ulong start, now, last;
++ int i;
++
++ if ((s_first < 0) || (s_first > s_last)) {
++ if (info->flash_id == FLASH_UNKNOWN) {
++ printf ("- missing\n");
++ } else {
++ printf ("- no sectors to erase\n");
++ }
++ return 1;
++ }
++
++ if (info->flash_id == FLASH_UNKNOWN) {
++ printf ("Can't erase unknown flash type - aborted\n");
++ return 1;
++ }
++
++ prot = 0;
++ for (sect=s_first; sect<=s_last; ++sect) {
++ if (info->protect[sect]) {
++ prot++;
++ }
++ }
++
++ if (prot) {
++ printf ("- Warning: %d protected sectors will not be erased!\n",
++ prot);
++ } else {
++ printf ("\n");
++ }
++
++ l_sect = -1;
++
++ /* Disable interrupts which might cause a timeout here */
++ flag = disable_interrupts();
++
++ /* Start erase on unprotected sectors */
++ for (sect = s_first; sect<=s_last; sect++) {
++ if (info->protect[sect] == 0) { /* not protected */
++ addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);
++ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
++ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
++ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
++ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
++ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
++ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
++ addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050; /* block erase */
++ for (i=0; i<50; i++)
++ udelay(1000); /* wait 1 ms */
++ } else {
++ if (sect == s_first) {
++ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
++ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
++ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
++ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
++ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
++ }
++ addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */
++ }
++ l_sect = sect;
++ }
++ }
++
++ /* re-enable interrupts if necessary */
++ if (flag)
++ enable_interrupts();
++
++ /* wait at least 80us - let's wait 1 ms */
++ udelay (1000);
++
++ /*
++ * We wait for the last triggered sector
++ */
++ if (l_sect < 0)
++ goto DONE;
++
++ start = get_timer (0);
++ last = start;
++ addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]);
++ while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) {
++ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
++ printf ("Timeout\n");
++ return 1;
++ }
++ /* show that we're waiting */
++ if ((now - last) > 1000) { /* every second */
++ putc ('.');
++ last = now;
++ }
++ }
++
++DONE:
++ /* reset to read mode */
++ addr = (CFG_FLASH_WORD_SIZE *)info->start[0];
++ addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
++
++ printf (" done\n");
++ return 0;
++}
++
++/*-----------------------------------------------------------------------
++ * Copy memory to flash, returns:
++ * 0 - OK
++ * 1 - write timeout
++ * 2 - Flash not erased
++ */
++
++int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
++{
++ ulong cp, wp, data;
++ int i, l, rc;
++
++ wp = (addr & ~3); /* get lower word aligned address */
++
++ /*
++ * handle unaligned start bytes
++ */
++ if ((l = addr - wp) != 0) {
++ data = 0;
++ for (i=0, cp=wp; i<l; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *)cp);
++ }
++ for (; i<4 && cnt>0; ++i) {
++ data = (data << 8) | *src++;
++ --cnt;
++ ++cp;
++ }
++ for (; cnt==0 && i<4; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *)cp);
++ }
++
++ if ((rc = write_word(info, wp, data)) != 0) {
++ return (rc);
++ }
++ wp += 4;
++ }
++
++ /*
++ * handle word aligned part
++ */
++ while (cnt >= 4) {
++ data = 0;
++ for (i=0; i<4; ++i) {
++ data = (data << 8) | *src++;
++ }
++ if ((rc = write_word(info, wp, data)) != 0) {
++ return (rc);
++ }
++ wp += 4;
++ cnt -= 4;
++ }
++
++ if (cnt == 0) {
++ return (0);
++ }
++
++ /*
++ * handle unaligned tail bytes
++ */
++ data = 0;
++ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
++ data = (data << 8) | *src++;
++ --cnt;
++ }
++ for (; i<4; ++i, ++cp) {
++ data = (data << 8) | (*(uchar *)cp);
++ }
++
++ return (write_word(info, wp, data));
++}
++
++/*-----------------------------------------------------------------------
++ * Write a word to Flash, returns:
++ * 0 - OK
++ * 1 - write timeout
++ * 2 - Flash not erased
++ */
++static int write_word (flash_info_t *info, ulong dest, ulong data)
++{
++ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
++ volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
++ volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
++ ulong start;
++ int flag;
++ int i;
++
++ /* Check if Flash is (sufficiently) erased */
++ if ((*((volatile ulong *)dest) & data) != data) {
++ return (2);
++ }
++ /* Disable interrupts which might cause a timeout here */
++ flag = disable_interrupts();
++
++ for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++)
++ {
++ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
++ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
++ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
++
++ dest2[i] = data2[i];
++
++ /* re-enable interrupts if necessary */
++ if (flag)
++ enable_interrupts();
++
++ /* data polling for D7 */
++ start = get_timer (0);
++ while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
++ (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
++ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
++ return (1);
++ }
++ }
++ }
++
++ return (0);
++}
+diff -uNr u-boot-1.1.2/board/emetec405/pllmr.c u-boot-emetec-1.1.2/board/emetec405/pllmr.c
+--- u-boot-1.1.2/board/emetec405/pllmr.c 1970-01-01 02:00:00.000000000 +0200
++++ u-boot-emetec-1.1.2/board/emetec405/pllmr.c 2005-03-14 22:32:04.000000000 +0200
+@@ -0,0 +1,19 @@
++#define PLL_CPUDIV_1 0x00000000
++#define PLL_PLBDIV_2 0x00010000
++#define PLL_OPBDIV_2 0x00001000
++#define PLL_EXTBUSDIV_3 0x00000100
++#define PLL_MALDIV_1 0x00000000
++#define PLL_PCIDIV_4 0x00000003
++
++#define PLL_FBKDIV_8 0x00800000
++#define PLL_FWDDIVA_4 0x00040000
++#define PLL_FWDDIVB_4 0x00004000
++#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
++#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
++
++#define PLLMR0_200_100_50_25 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
++ PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
++ PLL_MALDIV_1 | PLL_PCIDIV_4)
++#define PLLMR1_200_100_50_25 (PLL_FBKDIV_8 | \
++ PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
++ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+diff -uNr u-boot-1.1.2/board/emetec405/u-boot.lds u-boot-emetec-1.1.2/board/emetec405/u-boot.lds
+--- u-boot-1.1.2/board/emetec405/u-boot.lds 1970-01-01 02:00:00.000000000 +0200
++++ u-boot-emetec-1.1.2/board/emetec405/u-boot.lds 2003-09-12 11:41:39.000000000 +0300
+@@ -0,0 +1,147 @@
++/*
++ * (C) Copyright 2000
++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_ARCH(powerpc)
++SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
++/* Do we need any of these for elf?
++ __DYNAMIC = 0; */
++SECTIONS
++{
++ .resetvec 0xFFFFFFFC :
++ {
++ *(.resetvec)
++ } = 0xffff
++
++ /* Read-only sections, merged into text segment: */
++ . = + SIZEOF_HEADERS;
++ .interp : { *(.interp) }
++ .hash : { *(.hash) }
++ .dynsym : { *(.dynsym) }
++ .dynstr : { *(.dynstr) }
++ .rel.text : { *(.rel.text) }
++ .rela.text : { *(.rela.text) }
++ .rel.data : { *(.rel.data) }
++ .rela.data : { *(.rela.data) }
++ .rel.rodata : { *(.rel.rodata) }
++ .rela.rodata : { *(.rela.rodata) }
++ .rel.got : { *(.rel.got) }
++ .rela.got : { *(.rela.got) }
++ .rel.ctors : { *(.rel.ctors) }
++ .rela.ctors : { *(.rela.ctors) }
++ .rel.dtors : { *(.rel.dtors) }
++ .rela.dtors : { *(.rela.dtors) }
++ .rel.bss : { *(.rel.bss) }
++ .rela.bss : { *(.rela.bss) }
++ .rel.plt : { *(.rel.plt) }
++ .rela.plt : { *(.rela.plt) }
++ .init : { *(.init) }
++ .plt : { *(.plt) }
++ .text :
++ {
++ /* WARNING - the following is hand-optimized to fit within */
++ /* the sector layout of our flash chips! XXX FIXME XXX */
++
++ cpu/ppc4xx/start.o (.text)
++ cpu/ppc4xx/traps.o (.text)
++ cpu/ppc4xx/interrupts.o (.text)
++ cpu/ppc4xx/serial.o (.text)
++ cpu/ppc4xx/cpu_init.o (.text)
++ cpu/ppc4xx/speed.o (.text)
++ cpu/ppc4xx/405gp_enet.o (.text)
++ common/dlmalloc.o (.text)
++ lib_generic/crc32.o (.text)
++ lib_ppc/extable.o (.text)
++ lib_generic/zlib.o (.text)
++
++/* . = env_offset;*/
++/* common/environment.o(.text)*/
++
++ *(.text)
++ *(.fixup)
++ *(.got1)
++ }
++ _etext = .;
++ PROVIDE (etext = .);
++ .rodata :
++ {
++ *(.rodata)
++ *(.rodata1)
++ *(.rodata.str1.4)
++ }
++ .fini : { *(.fini) } =0
++ .ctors : { *(.ctors) }
++ .dtors : { *(.dtors) }
++
++ /* Read-write section, merged into data segment: */
++ . = (. + 0x00FF) & 0xFFFFFF00;
++ _erotext = .;
++ PROVIDE (erotext = .);
++ .reloc :
++ {
++ *(.got)
++ _GOT2_TABLE_ = .;
++ *(.got2)
++ _FIXUP_TABLE_ = .;
++ *(.fixup)
++ }
++ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
++ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
++
++ .data :
++ {
++ *(.data)
++ *(.data1)
++ *(.sdata)
++ *(.sdata2)
++ *(.dynamic)
++ CONSTRUCTORS
++ }
++ _edata = .;
++ PROVIDE (edata = .);
++
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ __start___ex_table = .;
++ __ex_table : { *(__ex_table) }
++ __stop___ex_table = .;
++
++ . = ALIGN(256);
++ __init_begin = .;
++ .text.init : { *(.text.init) }
++ .data.init : { *(.data.init) }
++ . = ALIGN(256);
++ __init_end = .;
++
++ __bss_start = .;
++ .bss :
++ {
++ *(.sbss) *(.scommon)
++ *(.dynbss)
++ *(.bss)
++ *(COMMON)
++ }
++ _end = . ;
++ PROVIDE (end = .);
++}
+diff -uNr u-boot-1.1.2/copy.sh u-boot-emetec-1.1.2/copy.sh
+--- u-boot-1.1.2/copy.sh 1970-01-01 02:00:00.000000000 +0200
++++ u-boot-emetec-1.1.2/copy.sh 2005-03-17 23:26:42.000000000 +0200
+@@ -0,0 +1,2 @@
++cp u-boot.bin /home/admin/uboot/uboot_v6.bin
++cp u-boot.srec /home/admin/uboot/uboot_v6.srec
+diff -uNr u-boot-1.1.2/cpu/ppc4xx/405gp_enet.c u-boot-emetec-1.1.2/cpu/ppc4xx/405gp_enet.c
+--- u-boot-1.1.2/cpu/ppc4xx/405gp_enet.c 2004-07-02 17:36:35.000000000 +0300
++++ u-boot-emetec-1.1.2/cpu/ppc4xx/405gp_enet.c 2005-05-06 18:07:02.000000000 +0300
+@@ -133,7 +133,7 @@
+ /*-----------------------------------------------------------------------------+
+ * Prototypes and externals.
+ *-----------------------------------------------------------------------------*/
+-static void enet_rcv (struct eth_device *dev, unsigned long malisr);
++static void enet_rcv (struct eth_device *dev, unsigned long malisr);
+
+ int enetInt (struct eth_device *dev);
+ static void mal_err (struct eth_device *dev, unsigned long isr,
+@@ -190,11 +190,15 @@
+ unsigned short reg_short;
+
+ EMAC_405_HW_PST hw_p = dev->priv;
++
++ puts ("Test 1\n");
+ /* before doing anything, figure out if we have a MAC address */
+ /* if not, bail */
+ if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0)
+ return -1;
+
++ puts ("Test 2\n");
++
+ msr = mfmsr ();
+ mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
+
+@@ -1023,6 +1027,8 @@
+ #else
+ emac0_dev = dev;
+ #endif
++ // print device name
++ printf("%s\n", dev->name);
+
+ } /* end for each supported device */
+
+diff -uNr u-boot-1.1.2/cpu/pxa/config.mk u-boot-emetec-1.1.2/cpu/pxa/config.mk
+--- u-boot-1.1.2/cpu/pxa/config.mk 2007-04-20 00:01:06.000000000 +0300
++++ u-boot-emetec-1.1.2/cpu/pxa/config.mk 2003-05-23 15:36:21.000000000 +0300
+@@ -23,6 +23,6 @@
+ #
+
+ PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
+- -msoft-float
++ -mshort-load-bytes -msoft-float
+
+ PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100
+diff -uNr u-boot-1.1.2/include/configs/EMETEC405.h u-boot-emetec-1.1.2/include/configs/EMETEC405.h
+--- u-boot-1.1.2/include/configs/EMETEC405.h 1970-01-01 02:00:00.000000000 +0200
++++ u-boot-emetec-1.1.2/include/configs/EMETEC405.h 2005-05-25 10:08:39.000000000 +0300
+@@ -0,0 +1,349 @@
++/*
++ * (C) Copyright 2001-2003
++ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++/*
++ * board/config.h - configuration options, board specific
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#define FLASH_8MB 1
++/*
++ * High Level Configuration Options
++ * (easy to change)
++ */
++
++#define CONFIG_405EP 1 /* This is a PPC405 CPU */
++#define CONFIG_4xx 1 /* ...member of PPC4xx family */
++#define CONFIG_EMETEC405 1 /* ...on a EMETEC405 board */
++
++#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
++#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
++
++#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
++
++#define CONFIG_BAUDRATE 115200
++#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
++
++#undef CONFIG_BOOTARGS
++#undef CONFIG_BOOTCOMMAND
++#define CONFIG_EXTRA_ENV_SETTINGS \
++ "ramargs=setenv bootargs console=ttyS0,115200 " \
++ "root=/dev/ram rw\0" \
++ "flash_mem=run ramargs;" \
++ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
++ "kernel_addr=ffC00000\0" \
++ "ramdisk_addr=ffCE0000\0" \
++ ""
++#define CONFIG_BOOTCOMMAND "run flash_mem"
++
++#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
++
++#define CONFIG_MII 1 /* MII PHY management */
++#define CONFIG_PHY_ADDR 0 /* PHY address */
++
++#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
++ CFG_CMD_NET | \
++ CFG_CMD_DHCP | \
++ CFG_CMD_IRQ | \
++ CFG_CMD_ELF | \
++ CFG_CMD_I2C | \
++ CFG_CMD_PING | \
++ CFG_CMD_EEPROM )
++
++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
++#include <cmd_confdefs.h>
++
++#undef CONFIG_WATCHDOG /* watchdog disabled */
++
++#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
++
++/*
++ * Miscellaneous configurable options
++ */
++#define CFG_LONGHELP /* undef to save memory */
++#define CFG_PROMPT "=> " /* Monitor Command Prompt */
++
++#undef CFG_HUSH_PARSER /* use "hush" command parser */
++#ifdef CFG_HUSH_PARSER
++#define CFG_PROMPT_HUSH_PS2 "> "
++#endif
++
++#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
++#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
++#else
++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
++#endif
++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
++#define CFG_MAXARGS 16 /* max number of command args */
++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
++
++#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
++
++#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
++
++#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
++#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
++
++#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
++#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
++#define CFG_BASE_BAUD 691200
++
++/* The following table includes the supported baudrates */
++#define CFG_BAUDRATE_TABLE \
++ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
++ 57600, 115200, 230400, 460800, 921600 }
++
++#define CFG_LOAD_ADDR 0x100000 /* default load address */
++#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
++
++#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
++
++#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
++
++#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
++
++#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
++
++/* Ethernet stuff */
++#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
++#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE
++
++#define CONFIG_IPADDR 192.168.0.50
++#define CONFIG_NETMASK 255.255.255.0
++#define CONFIG_SERVERIP 192.168.0.1
++
++/*-----------------------------------------------------------------------
++ * PCI stuff
++ *-----------------------------------------------------------------------
++ */
++#define PCI_HOST_ADAPTER 0 // configure as pci adapter
++#define PCI_HOST_FORCE 1 // configure as pci host
++#define PCI_HOST_AUTO 2 // detected via arbiter enable
++
++#define CONFIG_PCI // include pci support
++#define CONFIG_PCI_HOST PCI_HOST_FORCE // select pci host function
++#define CONFIG_PCI_PNP // do pci plug-and-play
++
++
++#define CFG_PCI_SUBSYS_VENDORID 0x0000 // PCI Vendor ID: IBM
++#define CFG_PCI_SUBSYS_DEVICEID 0x0000 // PCI Device ID: 405GP
++#define CFG_PCI_PTM1LA 0x00000000 // point to sdram
++#define CFG_PCI_PTM1MS 0x80000001 // 2GB, enable hard-wired to 1
++#define CFG_PCI_PTM1PCI 0x00000000 // Host: use this pci address
++#define CFG_PCI_PTM2LA 0x00000000 // disabled
++#define CFG_PCI_PTM2MS 0x00000000 // disabled
++#define CFG_PCI_PTM2PCI 0x00000000 // Host: use this pci address
++
++/*-----------------------------------------------------------------------
++ * Start addresses for the final memory configuration
++ * (Set up by the startup code)
++ * Please note that CFG_SDRAM_BASE _must_ start at 0
++ */
++
++/*
++ * Flash configuration (8,16 or 32 MB)
++ * TEXT base always at 0xFFF00000
++ * ENV_ADDR always at 0xFFF40000
++ * FLASH_BASE at 0xFE000000 for 32 MB
++ * 0xFF000000 for 16 MB
++ * 0xFF800000 for 8 MB
++ * 0xFFC00000 for 4 MB
++ */
++
++#define CFG_SDRAM_BASE 0x00000000
++#define CFG_FLASH_BASE 0xFFFC0000
++#define CFG_MONITOR_BASE CFG_FLASH_BASE
++#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
++#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
++
++/*
++ * For booting Linux, the board info and command line data
++ * have to be in the first 8 MB of memory, since this is
++ * the maximum mapped by the Linux kernel during initialization.
++ */
++#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
++/*-----------------------------------------------------------------------
++ * FLASH organization
++ */
++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
++#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
++
++#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
++#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
++
++#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
++#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
++#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
++/*
++ * The following defines are added for buggy IOP480 byte interface.
++ * All other boards should use the standard values (CPCI405 etc.)
++ */
++#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
++#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
++#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
++
++#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
++
++/*
++#define CFG_ENV_IS_IN_FLASH 1
++//Address and size of Primary Environment Sector
++#define CFG_ENV_ADDR 0xFFFFA000
++#define CFG_ENV_SIZE 0x2000
++*/
++
++/*-----------------------------------------------------------------------
++ * Environment Variable setup
++ */
++#define CFG_ENV_IS_IN_EEPROM 1 // use EEPROM for environment vars
++#define CFG_ENV_OFFSET 0x100 // environment starts at the beginning of the EEPROM
++#define CFG_ENV_SIZE 0x700 // 2048 bytes may be used for env vars
++
++/*-----------------------------------------------------------------------
++ * I2C EEPROM (CAT24WC16) for environment
++ */
++#define CONFIG_HARD_I2C // I2c with hardware support
++#define CFG_I2C_SPEED 400000 // I2C speed and slave address
++#define CFG_I2C_SLAVE 0x7F
++
++#define CFG_I2C_EEPROM_ADDR 0x50 // EEPROM CAT28WC08
++#define CFG_I2C_EEPROM_ADDR_LEN 1 // Bytes of address
++
++#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
++#define CFG_EEPROM_PAGE_WRITE_BITS 4 // The Catalyst CAT24WC08 has
++ // 16 byte page write mode using
++ // last 4 bits of the address
++#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 // and takes up to 10 msec
++#define CFG_EEPROM_PAGE_WRITE_ENABLE
++
++/*-----------------------------------------------------------------------
++ * Cache Configuration
++ */
++#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
++ /* have only 8kB, 16kB is save here */
++#define CFG_CACHELINE_SIZE 32 /* ... */
++#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
++#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
++#endif
++
++/*
++ * Init Memory Controller:
++ *
++ * BR0/1 and OR0/1 (FLASH)
++ */
++
++#if FLASH_8MB == 1
++#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
++#else
++#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
++#endif
++
++/*-----------------------------------------------------------------------
++ * External Bus Controller (EBC) Setup
++ */
++
++/* Memory Bank 0 (Flash Bank 0) initialization */
++#if FLASH_8MB == 1
++#define CFG_EBC_PB0AP 0x92015480
++#define CFG_EBC_PB0CR 0xFFC5B000 /* BAS=0xFFC,BS=8MB,BU=R/W,BW=16bit */
++#else
++#define CFG_EBC_PB0AP 0x92015480
++#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
++#endif
++
++/*-----------------------------------------------------------------------
++ * Definitions for initial stack pointer and data area (in data cache)
++ */
++/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
++#define CFG_TEMP_STACK_OCM 1
++
++/* On Chip Memory location */
++#define CFG_OCM_DATA_ADDR 0xF8000000
++#define CFG_OCM_DATA_SIZE 0x1000
++#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
++#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
++
++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
++#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
++#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
++
++/*-----------------------------------------------------------------------
++ * Definitions for GPIO setup (PPC405EP specific)
++ *
++ * GPIO0[0] - External Bus Controller BLAST output
++ * GPIO0[1-9] - Instruction trace outputs -> GPIO
++ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
++ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
++ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
++ * GPIO0[24-27] - UART0 control signal inputs/outputs
++ * GPIO0[28-29] - UART1 data signal input/output
++ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
++ */
++#define CFG_GPIO0_OSRH 0x40000550
++#define CFG_GPIO0_OSRL 0x00000110
++#define CFG_GPIO0_ISR1H 0x00000000
++#define CFG_GPIO0_ISR1L 0x15555445
++#define CFG_GPIO0_TSRH 0x00000000
++#define CFG_GPIO0_TSRL 0x00000000
++#define CFG_GPIO0_TCR 0xF7FE0014
++
++/*
++ * Internal Definitions
++ *
++ * Boot Flags
++ */
++#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
++#define BOOTFLAG_WARM 0x02 /* Software reboot */
++
++#define PLL_CPUDIV_1 0x00000000
++#define PLL_PLBDIV_2 0x00010000
++#define PLL_OPBDIV_2 0x00001000
++
++#define PLL_EXTBUSDIV_4 0x00000200
++
++#define PLL_MALDIV_1 0x00000000
++#define PLL_PCIDIV_2 0x00000001
++#define PLL_PCIDIV_4 0x00000003
++
++#define PLL_FBKDIV_8 0x00800000
++
++#define PLL_FWDDIVA_4 0x00040000
++#define PLL_FWDDIVB_4 0x00004000
++#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
++#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
++
++#define PLLMR0_200_100_50_25 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
++ PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
++ PLL_MALDIV_1 | PLL_PCIDIV_4)
++#define PLLMR1_200_100_50_25 (PLL_FBKDIV_8 | \
++ PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
++ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
++/*
++ * Default speed selection (cpu_plb_opb_ebc) in mhz.
++ * This value will be set if iic boot eprom is disabled.
++ */
++#define PLLMR0_DEFAULT PLLMR0_200_100_50_25
++#define PLLMR1_DEFAULT PLLMR1_200_100_50_25
++
++#endif /* __CONFIG_H */
+diff -uNr u-boot-1.1.2/include/configs/EMETEC405.h.old u-boot-emetec-1.1.2/include/configs/EMETEC405.h.old
+--- u-boot-1.1.2/include/configs/EMETEC405.h.old 1970-01-01 02:00:00.000000000 +0200
++++ u-boot-emetec-1.1.2/include/configs/EMETEC405.h.old 2005-03-17 23:00:33.000000000 +0200
+@@ -0,0 +1,349 @@
++/*
++ * (C) Copyright 2001-2003
++ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++/*
++ * board/config.h - configuration options, board specific
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++/*
++ * High Level Configuration Options
++ * (easy to change)
++ */
++
++#define CONFIG_405EP 1 /* This is a PPC405 CPU */
++#define CONFIG_4xx 1 /* ...member of PPC4xx family */
++#define CONFIG_EMETEC405 1 /* ...on a EMETEC405 board */
++
++#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
++#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
++
++#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
++
++#define CONFIG_BAUDRATE 115200
++#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
++
++#undef CONFIG_BOOTARGS
++#undef CONFIG_BOOTCOMMAND
++
++#define CONFIG_PREBOOT /* enable preboot variable */
++
++#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
++
++#define CONFIG_MII 1 /* MII PHY management */
++#define CONFIG_PHY_ADDR 0 /* PHY address */
++#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
++
++/*
++#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ // 66 MHz OPB clock
++*/
++
++#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
++ CFG_CMD_DHCP | \
++ CFG_CMD_IRQ | \
++ CFG_CMD_ELF | \
++ CFG_CMD_I2C | \
++ CFG_CMD_MII | \
++ CFG_CMD_PING | \
++ CFG_CMD_EEPROM )
++
++/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
++#include <cmd_confdefs.h>
++
++#undef CONFIG_WATCHDOG /* watchdog disabled */
++
++#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
++
++/*
++ * Miscellaneous configurable options
++ */
++#define CFG_LONGHELP /* undef to save memory */
++#define CFG_PROMPT "=> " /* Monitor Command Prompt */
++
++#undef CFG_HUSH_PARSER /* use "hush" command parser */
++#ifdef CFG_HUSH_PARSER
++#define CFG_PROMPT_HUSH_PS2 "> "
++#endif
++
++#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
++#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
++#else
++#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
++#endif
++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
++#define CFG_MAXARGS 16 /* max number of command args */
++#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
++
++#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
++
++#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
++
++#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
++#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
++
++#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
++#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
++#define CFG_BASE_BAUD 691200
++#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */
++
++/* The following table includes the supported baudrates */
++#define CFG_BAUDRATE_TABLE \
++ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
++ 57600, 115200, 230400, 460800, 921600 }
++
++#define CFG_LOAD_ADDR 0x100000 /* default load address */
++#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
++
++#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
++
++#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
++
++#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
++
++#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
++
++/* Ethernet stuff */
++#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
++#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE
++#define CONFIG_HAS_ETH1
++#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
++
++#define CONFIG_IPADDR 192.168.0.50
++#define CONFIG_IP1ADDR 192.168.0.51
++#define CONFIG_NETMASK 255.255.255.0
++#define CONFIG_SERVERIP 192.168.0.1
++
++/*-----------------------------------------------------------------------
++ * PCI stuff
++ *-----------------------------------------------------------------------
++ */
++#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
++#define PCI_HOST_FORCE 1 /* configure as pci host */
++#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
++
++#undef CONFIG_PCI /* include pci support */
++#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
++#undef CONFIG_PCI_PNP /* do pci plug-and-play */
++ /* resource configuration */
++
++#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
++
++#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
++#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
++#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
++#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
++#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
++#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
++#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
++#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
++#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
++
++/*-----------------------------------------------------------------------
++ * Start addresses for the final memory configuration
++ * (Set up by the startup code)
++ * Please note that CFG_SDRAM_BASE _must_ start at 0
++ */
++#define CFG_SDRAM_BASE 0x00000000
++#define CFG_FLASH_BASE 0xFFFC0000
++#define CFG_MONITOR_BASE CFG_FLASH_BASE
++#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
++#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
++
++/*
++ * For booting Linux, the board info and command line data
++ * have to be in the first 8 MB of memory, since this is
++ * the maximum mapped by the Linux kernel during initialization.
++ */
++#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
++/*-----------------------------------------------------------------------
++ * FLASH organization
++ */
++#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
++#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
++
++#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
++#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
++
++#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
++#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
++#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
++/*
++ * The following defines are added for buggy IOP480 byte interface.
++ * All other boards should use the standard values (CPCI405 etc.)
++ */
++#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
++#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
++#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
++
++#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
++
++#if 0 /* test-only */
++#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
++#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
++#endif
++
++/*-----------------------------------------------------------------------
++ * Environment Variable setup
++ */
++#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
++#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
++#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
++ /* total size of a CAT24WC16 is 2048 bytes */
++
++#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
++#define CFG_NVRAM_SIZE 242 /* NVRAM size */
++
++/*-----------------------------------------------------------------------
++ * I2C EEPROM (CAT24WC16) for environment
++ */
++#define CONFIG_HARD_I2C /* I2c with hardware support */
++#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
++#define CFG_I2C_SLAVE 0x7F
++
++#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
++#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
++/* mask of address bits that overflow into the "EEPROM chip address" */
++#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
++#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
++ /* 16 byte page write mode using*/
++ /* last 4 bits of the address */
++#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
++#define CFG_EEPROM_PAGE_WRITE_ENABLE
++
++/*-----------------------------------------------------------------------
++ * Cache Configuration
++ */
++#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
++ /* have only 8kB, 16kB is save here */
++#define CFG_CACHELINE_SIZE 32 /* ... */
++#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
++#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
++#endif
++
++/*
++ * Init Memory Controller:
++ *
++ * BR0/1 and OR0/1 (FLASH)
++ */
++
++#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
++
++/*-----------------------------------------------------------------------
++ * External Bus Controller (EBC) Setup
++ */
++
++/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
++#define CFG_EBC_PB0AP 0x92015480
++#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
++
++#define DUART0_BA 0xF0000000 /* DUART Base Address */
++#define DUART1_BA 0xF0000008 /* DUART Base Address */
++#define DUART2_BA 0xF0000010 /* DUART Base Address */
++#define DUART3_BA 0xF0000018 /* DUART Base Address */
++
++/*-----------------------------------------------------------------------
++ * FPGA stuff
++ */
++#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
++#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
++
++/* FPGA program pin configuration */
++#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
++#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
++#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
++#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
++#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
++
++/*-----------------------------------------------------------------------
++ * Definitions for initial stack pointer and data area (in data cache)
++ */
++/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
++#define CFG_TEMP_STACK_OCM 1
++
++/* On Chip Memory location */
++#define CFG_OCM_DATA_ADDR 0xF8000000
++#define CFG_OCM_DATA_SIZE 0x1000
++#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
++#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
++
++#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
++#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
++#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
++
++/*-----------------------------------------------------------------------
++ * Definitions for GPIO setup (PPC405EP specific)
++ *
++ * GPIO0[0] - External Bus Controller BLAST output
++ * GPIO0[1-9] - Instruction trace outputs -> GPIO
++ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
++ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
++ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
++ * GPIO0[24-27] - UART0 control signal inputs/outputs
++ * GPIO0[28-29] - UART1 data signal input/output
++ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
++ */
++#define CFG_GPIO0_OSRH 0x40000550
++#define CFG_GPIO0_OSRL 0x00000110
++#define CFG_GPIO0_ISR1H 0x00000000
++#define CFG_GPIO0_ISR1L 0x15555445
++#define CFG_GPIO0_TSRH 0x00000000
++#define CFG_GPIO0_TSRL 0x00000000
++#define CFG_GPIO0_TCR 0xF7FE0014
++
++/*
++ * Internal Definitions
++ *
++ * Boot Flags
++ */
++#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
++#define BOOTFLAG_WARM 0x02 /* Software reboot */
++
++#define PLL_CPUDIV_1 0x00000000
++#define PLL_PLBDIV_2 0x00010000
++#define PLL_OPBDIV_2 0x00001000
++#define PLL_EXTBUSDIV_3 0x00000100
++#define PLL_MALDIV_1 0x00000000
++#define PLL_PCIDIV_4 0x00000003
++
++#define PLL_FBKDIV_8 0x00800000
++#define PLL_FWDDIVA_4 0x00040000
++#define PLL_FWDDIVB_4 0x00004000
++#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
++#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
++
++#define PLLMR0_200_100_50_25 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
++ PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
++ PLL_MALDIV_1 | PLL_PCIDIV_4)
++#define PLLMR1_200_100_50_25 (PLL_FBKDIV_8 | \
++ PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
++ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
++/*
++ * Default speed selection (cpu_plb_opb_ebc) in mhz.
++ * This value will be set if iic boot eprom is disabled.
++ */
++#define PLLMR0_DEFAULT PLLMR0_200_100_50_25
++#define PLLMR1_DEFAULT PLLMR1_200_100_50_25
++
++#endif /* __CONFIG_H */
+diff -uNr u-boot-1.1.2/include/configs/HUB405.h u-boot-emetec-1.1.2/include/configs/HUB405.h
+--- u-boot-1.1.2/include/configs/HUB405.h 2004-12-31 11:32:53.000000000 +0200
++++ u-boot-emetec-1.1.2/include/configs/HUB405.h 2005-03-11 22:19:12.000000000 +0200
+@@ -35,7 +35,7 @@
+
+ #define CONFIG_405EP 1 /* This is a PPC405 CPU */
+ #define CONFIG_4xx 1 /* ...member of PPC4xx family */
+-#define CONFIG_HUB405 1 /* ...on a HUB405 board */
++#define CONFIG_EMETEC405 1 /* ...on a EMETEC405 board */
+
+ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
+ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
+diff -uNr u-boot-1.1.2/include/flash.h u-boot-emetec-1.1.2/include/flash.h
+--- u-boot-1.1.2/include/flash.h 2004-12-16 20:01:48.000000000 +0200
++++ u-boot-emetec-1.1.2/include/flash.h 2005-05-25 10:04:56.000000000 +0300
+@@ -229,7 +229,11 @@
+
+ #define STM_ID_x800AB 0x005B005B /* M29W800AB ID (8M = 512K x 16 ) */
+ #define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */
+-#define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */
++#define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect)*/
++
++#define STM_ID_29W640DT 0x22DE22DE /* M29W640DT ID (64 M, top boot sector) */
++#define STM_ID_29W640DB 0x22DF22DF /* M29W640DB ID (64 M, bottom boot sect)*/
++
+ #define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */
+
+ #define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */
+@@ -328,6 +332,8 @@
+ #define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */
+ #define FLASH_STMW320DT 0x0052 /* STM M29W320DT (32 M, top boot sector) */
+ #define FLASH_STMW320DB 0x0053 /* STM M29W320DB (32 M, bottom boot sect)*/
++#define FLASH_STMW640DT 0x0054 /* STM M29W640DT (64 M, top boot sector) */
++#define FLASH_STMW640DB 0x0055 /* STM M29W640DB (64 M, bottom boot sect)*/
+ #define FLASH_STM320DB 0x00CB /* STM M29W320DB (4M = 64K x 64, bottom)*/
+ #define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */
+ #define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/
+diff -uNr u-boot-1.1.2/include/net.h u-boot-emetec-1.1.2/include/net.h
+--- u-boot-1.1.2/include/net.h 2004-10-10 00:56:21.000000000 +0300
++++ u-boot-emetec-1.1.2/include/net.h 2005-04-27 23:16:40.000000000 +0300
+@@ -331,9 +331,9 @@
+ #define NETLOOP_SUCCESS 3
+ #define NETLOOP_FAIL 4
+
+-#ifdef CONFIG_NET_MULTI
++/* #ifdef CONFIG_NET_MULTI */
+ extern int NetRestartWrap; /* Tried all network devices */
+-#endif
++/* #endif */
+
+ typedef enum { BOOTP, RARP, ARP, TFTP, DHCP, PING, DNS, NFS, CDP, NETCONS } proto_t;
+
+diff -uNr u-boot-1.1.2/lib_ppc/board.c u-boot-emetec-1.1.2/lib_ppc/board.c
+--- u-boot-1.1.2/lib_ppc/board.c 2004-12-31 11:32:54.000000000 +0200
++++ u-boot-emetec-1.1.2/lib_ppc/board.c 2005-04-27 23:03:33.000000000 +0300
+@@ -970,7 +970,8 @@
+ nand_init(); /* go init the NAND */
+ #endif
+
+-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
++
++#if (CONFIG_COMMANDS & CFG_CMD_NET) /* && defined(CONFIG_NET_MULTI) */
+ WATCHDOG_RESET ();
+ puts ("Net: ");
+ eth_initialize (bd);
+diff -uNr u-boot-1.1.2/loadftp.sh u-boot-emetec-1.1.2/loadftp.sh
+--- u-boot-1.1.2/loadftp.sh 1970-01-01 02:00:00.000000000 +0200
++++ u-boot-emetec-1.1.2/loadftp.sh 2005-04-25 21:30:54.000000000 +0300
+@@ -0,0 +1 @@
++cp u-boot.bin /home/ftp/uboot.bin
+diff -uNr u-boot-1.1.2/loadwww.sh u-boot-emetec-1.1.2/loadwww.sh
+--- u-boot-1.1.2/loadwww.sh 1970-01-01 02:00:00.000000000 +0200
++++ u-boot-emetec-1.1.2/loadwww.sh 2005-03-12 13:06:19.000000000 +0200
+@@ -0,0 +1,2 @@
++#!/bin/bash
++rsync -vzr --rsh='ssh -l admin -p 5522' /home/admin/uboot/ admin@mhaber.net:/home/admin/uboot
+diff -uNr u-boot-1.1.2/net/eth.c u-boot-emetec-1.1.2/net/eth.c
+--- u-boot-1.1.2/net/eth.c 2004-12-16 19:49:38.000000000 +0200
++++ u-boot-emetec-1.1.2/net/eth.c 2005-05-06 18:04:08.000000000 +0300
+@@ -25,7 +25,7 @@
+ #include <command.h>
+ #include <net.h>
+
+-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
++#if (CONFIG_COMMANDS & CFG_CMD_NET) /* && defined(CONFIG_NET_MULTI) */
+
+ #ifdef CFG_GT_6426x
+ extern int gt6426x_eth_initialize(bd_t *bis);
+@@ -126,10 +126,13 @@
+ #ifdef CONFIG_DB64460
+ mv6446x_eth_initialize(bis);
+ #endif
++
+ #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
+ ( defined(CONFIG_440) && !defined(CONFIG_NET_MULTI) )
+ ppc_4xx_eth_initialize(bis);
++ eth_number=1;
+ #endif
++
+ #if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
+ ppc_440x_eth_initialize(bis);
+ #endif
+@@ -197,6 +200,7 @@
+ rtl8169_initialize(bis);
+ #endif
+
++#if defined(CONFIG_NET_MULTI)
+ if (!eth_devices) {
+ puts ("No ethernet found.\n");
+ } else {
+@@ -248,7 +252,6 @@
+ dev = dev->next;
+ } while(dev != eth_devices);
+
+-#ifdef CONFIG_NET_MULTI
+ /* update current ethernet name */
+ if (eth_current) {
+ char *act = getenv("ethact");
+@@ -256,14 +259,14 @@
+ setenv("ethact", eth_current->name);
+ } else
+ setenv("ethact", NULL);
+-#endif
+-
+ putc ('\n');
+ }
++#endif
+
+ return eth_number;
+ }
+
++#ifdef CONFIG_NET_MULTI
+ void eth_set_enetaddr(int num, char *addr) {
+ struct eth_device *dev;
+ unsigned char enetaddr[6];
+@@ -362,21 +365,20 @@
+
+ eth_current = eth_current->next;
+
+-#ifdef CONFIG_NET_MULTI
++//#ifdef CONFIG_NET_MULTI
+ /* update current ethernet name */
+ {
+ char *act = getenv("ethact");
+ if (act == NULL || strcmp(act, eth_current->name) != 0)
+ setenv("ethact", eth_current->name);
+ }
+-#endif
++//#endif
+
+ if (first_failed == eth_current) {
+ NetRestartWrap = 1;
+ }
+ }
+
+-#ifdef CONFIG_NET_MULTI
+ void eth_set_current(void)
+ {
+ char *act;
+@@ -397,10 +399,11 @@
+
+ setenv("ethact", eth_current->name);
+ }
+-#endif
+
+ char *eth_get_name (void)
+ {
+ return (eth_current ? eth_current->name : "unknown");
+ }
+ #endif
++
++#endif
+diff -uNr u-boot-1.1.2/net/net.c u-boot-emetec-1.1.2/net/net.c
+--- u-boot-1.1.2/net/net.c 2004-10-12 01:51:14.000000000 +0300
++++ u-boot-emetec-1.1.2/net/net.c 2005-04-27 23:34:20.000000000 +0300
+@@ -126,11 +126,11 @@
+ { 0x01, 0x00, 0x0c, 0xcc, 0xcc, 0xcc };
+ #endif
+ int NetState; /* Network loop state */
+-#ifdef CONFIG_NET_MULTI
++/* #ifdef CONFIG_NET_MULTI */
+ int NetRestartWrap = 0; /* Tried all network devices */
+ static int NetRestarted = 0; /* Network loop restarted */
+ static int NetDevExists = 0; /* At least one device configured */
+-#endif
++/* #endif */
+
+ /* XXX in both little & big endian machines 0xFFFF == ntohs(-1) */
+ ushort NetOurVLAN = 0xFFFF; /* default is without VLAN */
+diff -uNr u-boot-1.1.2/patches/arm_flags.patch u-boot-emetec-1.1.2/patches/arm_flags.patch
+--- u-boot-1.1.2/patches/arm_flags.patch 2007-04-20 00:01:06.000000000 +0300
++++ u-boot-emetec-1.1.2/patches/arm_flags.patch 1970-01-01 02:00:00.000000000 +0200
+@@ -1,15 +0,0 @@
+-
+-#
+-# Patch managed by http://www.holgerschurig.de/patcher.html
+-#
+-
+---- u-boot-1.1.2/cpu/pxa/config.mk~armflags
+-+++ u-boot-1.1.2/cpu/pxa/config.mk
+-@@ -23,6 +23,6 @@
+- #
+-
+- PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
+-- -mshort-load-bytes -msoft-float
+-+ -msoft-float
+-
+- PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100
+diff -uNr u-boot-1.1.2/patches/series u-boot-emetec-1.1.2/patches/series
+--- u-boot-1.1.2/patches/series 2007-04-20 00:01:06.000000000 +0300
++++ u-boot-emetec-1.1.2/patches/series 1970-01-01 02:00:00.000000000 +0200
+@@ -1 +0,0 @@
+-arm_flags.patch -p1
+diff -uNr u-boot-1.1.2/lib_ppc/board.c new-uboot-1.1.2/lib_ppc/board.c
+--- u-boot-1.1.2/lib_ppc/board.c 2005-04-27 23:03:33.000000000 +0300
++++ new-uboot-1.1.2/lib_ppc/board.c 2007-04-20 00:55:16.000000000 +0300
+@@ -347,6 +347,7 @@
+
+ bd_t *bd;
+ ulong len, addr, addr_sp;
++ ulong *s;
+ gd_t *id;
+ init_fnc_t **init_fnc_ptr;
+ #ifdef CONFIG_PRAM
+@@ -466,8 +467,10 @@
+ */
+ addr_sp -= 16;
+ addr_sp &= ~0xF;
+- *((ulong *) addr_sp)-- = 0;
+- *((ulong *) addr_sp)-- = 0;
++ s = (ulong *)addr_sp;
++ *s-- = 0;
++ *s-- = 0;
++ addr_sp = (ulong)s;
+ debug ("Stack Pointer at: %08lx\n", addr_sp);
+
+ /*
+diff -uNr u-boot-1.1.2/net/net.c new-uboot-1.1.2/net/net.c
+--- u-boot-1.1.2/net/net.c 2005-04-27 23:34:20.000000000 +0300
++++ new-uboot-1.1.2/net/net.c 2007-04-20 01:00:26.000000000 +0300
+@@ -1491,14 +1491,17 @@
+ unsigned
+ NetCksum(uchar * ptr, int len)
+ {
+- ulong xsum;
+
+- xsum = 0;
+- while (len-- > 0)
+- xsum += *((ushort *)ptr)++;
+- xsum = (xsum & 0xffff) + (xsum >> 16);
+- xsum = (xsum & 0xffff) + (xsum >> 16);
+- return (xsum & 0xffff);
++ ulong xsum;
++ ushort *p = (ushort *)ptr;
++
++ xsum = 0;
++ while (len-- > 0)
++ xsum += *p++;
++ xsum = (xsum & 0xffff) + (xsum >> 16);
++ xsum = (xsum & 0xffff) + (xsum >> 16);
++ return (xsum & 0xffff);
++
+ }
+
+ int
+diff -uNr u-boot-1.1.2/net/tftp.c new-uboot-1.1.2/net/tftp.c
+--- u-boot-1.1.2/net/tftp.c 2004-04-16 00:48:55.000000000 +0300
++++ new-uboot-1.1.2/net/tftp.c 2005-12-16 18:39:27.000000000 +0200
+@@ -58,7 +58,7 @@
+ static char *tftp_filename;
+
+ #ifdef CFG_DIRECT_FLASH_TFTP
+-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
++extern flash_info_t flash_info[];
+ #endif
+
+ static __inline__ void
+@@ -78,7 +78,7 @@
+ }
+
+ if (rc) { /* Flash is destination for this packet */
+- rc = flash_write ((uchar *)src, (ulong)(load_addr+offset), len);
++ rc = flash_write ((char *)src, (ulong)(load_addr+offset), len);
+ if (rc) {
+ flash_perror (rc);
+ NetState = NETLOOP_FAIL;
+@@ -106,6 +106,7 @@
+ volatile uchar * pkt;
+ volatile uchar * xp;
+ int len = 0;
++ volatile ushort *s;
+
+ /*
+ * We will always be sending some sort of packet, so
+@@ -117,7 +118,9 @@
+
+ case STATE_RRQ:
+ xp = pkt;
+- *((ushort *)pkt)++ = htons(TFTP_RRQ);
++ s = (ushort *)pkt;
++ *s++ = htons(TFTP_RRQ);
++ pkt = (uchar *)s;
+ strcpy ((char *)pkt, tftp_filename);
+ pkt += strlen(tftp_filename) + 1;
+ strcpy ((char *)pkt, "octet");
+@@ -135,15 +138,19 @@
+ case STATE_DATA:
+ case STATE_OACK:
+ xp = pkt;
+- *((ushort *)pkt)++ = htons(TFTP_ACK);
+- *((ushort *)pkt)++ = htons(TftpBlock);
++ s = (ushort *)pkt;
++ *s++ = htons(TFTP_ACK);
++ *s++ = htons(TftpBlock);
++ pkt = (uchar *)s;
+ len = pkt - xp;
+ break;
+
+ case STATE_TOO_LARGE:
+ xp = pkt;
+- *((ushort *)pkt)++ = htons(TFTP_ERROR);
+- *((ushort *)pkt)++ = htons(3);
++ s = (ushort *)pkt;
++ *s++ = htons(TFTP_ERROR);
++ *s++ = htons(3);
++ pkt = (uchar *)s;
+ strcpy ((char *)pkt, "File too large");
+ pkt += 14 /*strlen("File too large")*/ + 1;
+ len = pkt - xp;
+@@ -151,8 +158,10 @@
+
+ case STATE_BAD_MAGIC:
+ xp = pkt;
+- *((ushort *)pkt)++ = htons(TFTP_ERROR);
+- *((ushort *)pkt)++ = htons(2);
++ s = (ushort *)pkt;
++ *s++ = htons(TFTP_ERROR);
++ *s++ = htons(2);
++ pkt = (uchar *)s;
+ strcpy ((char *)pkt, "File has bad magic");
+ pkt += 18 /*strlen("File has bad magic")*/ + 1;
+ len = pkt - xp;
+@@ -167,6 +176,7 @@
+ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len)
+ {
+ ushort proto;
++ ushort *s;
+
+ if (dest != TftpOurPort) {
+ return;
+@@ -180,7 +190,9 @@
+ }
+ len -= 2;
+ /* warning: don't use increment (++) in ntohs() macros!! */
+- proto = *((ushort *)pkt)++;
++ s = (ushort *)pkt;
++ proto = *s++;
++ pkt = (uchar *)s;
+ switch (ntohs(proto)) {
+
+ case TFTP_RRQ:
+@@ -301,14 +313,16 @@
+ void
+ TftpStart (void)
+ {
+- if (BootFile[0] == '\0') {
+- IPaddr_t OurIP = ntohl(NetOurIP);
++#ifdef CONFIG_TFTP_PORT
++ char *ep; /* Environment pointer */
++#endif
+
++ if (BootFile[0] == '\0') {
+ sprintf(default_filename, "%02lX%02lX%02lX%02lX.img",
+- OurIP & 0xFF,
+- (OurIP >> 8) & 0xFF,
+- (OurIP >> 16) & 0xFF,
+- (OurIP >> 24) & 0xFF );
++ NetOurIP & 0xFF,
++ (NetOurIP >> 8) & 0xFF,
++ (NetOurIP >> 16) & 0xFF,
++ (NetOurIP >> 24) & 0xFF );
+ tftp_filename = default_filename;
+
+ printf ("*** Warning: no boot file name; using '%s'\n",
+@@ -354,7 +368,16 @@
+ TftpServerPort = WELL_KNOWN_PORT;
+ TftpTimeoutCount = 0;
+ TftpState = STATE_RRQ;
++ /* Use a pseudo-random port unless a specific port is set */
+ TftpOurPort = 1024 + (get_timer(0) % 3072);
++#ifdef CONFIG_TFTP_PORT
++ if ((ep = getenv("tftpdstp")) != NULL) {
++ TftpServerPort = simple_strtol(ep, NULL, 10);
++ }
++ if ((ep = getenv("tftpsrcp")) != NULL) {
++ TftpOurPort= simple_strtol(ep, NULL, 10);
++ }
++#endif
+ TftpBlock = 0;
+
+ /* zero out server ether in case the server ip has changed */
+diff -uNr u-boot-1.1.2/board/emetec405/flash.c new-uboot-1.1.2/board/emetec405/flash.c
+--- u-boot-1.1.2/board/emetec405/flash.c 2007-04-20 00:40:26.000000000 +0300
++++ new-uboot-1.1.2/board/emetec405/flash.c 2007-04-20 00:41:11.000000000 +0300
+@@ -31,6 +31,7 @@
+ */
+ static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+ static void flash_get_offsets (ulong base, flash_info_t * info);
++static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+ /*-----------------------------------------------------------------------
+ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-27 08:19:52 +0000