diff options
| author | Marcin Juszkiewicz <marcin@juszkiewicz.com.pl> | 2009-09-30 15:06:17 +0200 |
|---|---|---|
| committer | Marcin Juszkiewicz <marcin@juszkiewicz.com.pl> | 2009-09-30 19:06:36 +0200 |
| commit | a261b5ea923854b9a84f91cec0177ff57e905c98 (patch) | |
| tree | 1d2563f24426102c3d6f83873349e79f288f0db3 /recipes/gcc | |
| parent | fe2fa19a4a00b3c7778933c476d57ca46c303c61 (diff) | |
gcc: update Maverick Crunch support to 20090908 version
From Martin W. Guy page http://martinwguy.co.uk/martin/crunch/
The 20090908 version
* performs single and double precision floating point in the FPU (add, sub,
mul, neg, abs, cmp and conversions from single and double precision floats
to integral types).
* by default, disables the floating point cfnegs and cfnegd instructions,
which fail to convert 0 to -0 as they should. You can re-enable them with
the -funsafe-math-optimizations flag, which is one of those enabled
by -ffast-math (gcc-4.3 has an even more specific -fno-signed-zeros flag,
which is one of those enabled by -funsafe-math-optimizations).
* by default, does not respect denormalised values, so the smallest
representable values are ±2-126 for floats and ±2-1022 for doubles instead of
the usual ±2-149 and ±2-1074.
* has a -mieee flag, which enables handling of denormalized values by disabling
all the buggy instructions. With this, floating point addition, subtraction,
negation, absolute value and conversion between floats and integer types are
performed in software, leaving only floating point multiplication and
comparison performed in hardware.
* has no negative impact on regular ARM code generation.
* always works round the hardware bugs in the FPU and no longer has the
-mcirrus-fix-invalid-insns flag since chip development has stopped and all
existing silicon has the same bugs except for the original revision D0 which
is not supported.
* passes GCC's IEEE testsuite except for the one specific test that checks for
correct handling of denormalized values. With -mieee it passes all the math
tests.
* passes all other testsuites that I've tried (see below) including the
stringent "paranoia" floating point IEEE conformance test.
* produces the fastest Maverick code yet: 5.94 MFLOPS according to FFTW's
tests/bench -opatient cf1024 benchmark and LAME takes 2m25 to encode that
30-second WAV file on a 200MHz EP9307 (compared to 5.4 and 2m30 for the
futaris patches for 4.1.2 and 4.2.0).
* does not use the FPU's buggy 64-bit integer instructions unless the new
-mcirrus-di flag is given. Programs that do a lot of 64-bit integer
operations (add, sub, mul, neg, abs, shifts) may be faster using this, but
rigorous testing will be necessary to ensure that bad code is not being
produced. OpenSSL's testsuite fails if this is enabled. There is more detail
at the head of the arm-crunch-cirrus-di-flag.patch file.
Known bugs
* C: Values held in Maverick registers are not restored when performing a
setjmp/longjmp pair. There is a fix to glibc for this in a message to the
linux-cirrus mailing list.
* C++: Similarly, exception unwinding (performing a throw back to a catch block
in a different function) does not restore floating point and 64-bit values
held in Maverick registers.
* C++: Some C++ files will not compile, saying
".save {mv8}" Error: register expected
although the same files will compile with optimization disabled.
There is a patch to make binutils recognize these registers in the .save
macro in a message to the linux-cirrus mailing list.
Diffstat (limited to 'recipes/gcc')
67 files changed, 3176 insertions, 3093 deletions
diff --git a/recipes/gcc/gcc-4.2.4.inc b/recipes/gcc/gcc-4.2.4.inc index 4638ddcdf1..3249c095b5 100644 --- a/recipes/gcc/gcc-4.2.4.inc +++ b/recipes/gcc/gcc-4.2.4.inc @@ -3,7 +3,7 @@ LICENSE = "GPLv3" DEPENDS = "mpfr gmp" -INC_PR = "r8" +INC_PR = "r9" SRC_URI = "${GNU_MIRROR}/gcc/gcc-${PV}/gcc-${PV}.tar.bz2 \ file://100-uclibc-conf.patch;patch=1 \ @@ -41,23 +41,32 @@ SRC_URI = "${GNU_MIRROR}/gcc/gcc-${PV}/gcc-${PV}.tar.bz2 \ " SRC_URI_append_ep93xx = " \ - file://arm-crunch-saveregs.patch;patch=1 \ - file://arm-crunch-20000320.patch;patch=1 \ - file://arm-crunch-compare.patch;patch=1 \ - file://arm-crunch-compare-unordered.patch;patch=1 \ - file://arm-crunch-compare-geu.patch;patch=1 \ - file://arm-crunch-eabi-ieee754.patch;patch=1 \ - file://arm-crunch-eabi-ieee754-div.patch;patch=1 \ - file://arm-crunch-64bit-disable0.patch;patch=1 \ - file://arm-crunch-offset.patch;patch=1 \ - file://arm-crunch-fp_consts.patch;patch=1 \ - file://arm-crunch-neg2.patch;patch=1 \ - file://arm-crunch-predicates3.patch;patch=1 \ - file://arm-crunch-cfcvtds-disable.patch;patch=1 \ - file://arm-crunch-floatsi-disable.patch;patch=1 \ - file://arm-crunch-truncsi-disable.patch;patch=1 \ - file://arm-crunch-cfcvt64-disable.patch;patch=1 \ - file://arm-crunch-cirrus-bugfixes.patch;patch=1 \ + file://ep93xx/arm-crunch-readme.patch;patch=1 \ + file://ep93xx/arm-crunch-saveregs.patch;patch=1 \ + file://ep93xx/arm-crunch-scratch.patch;patch=1 \ + file://ep93xx/arm-crunch-eabi-ieee754-endian-littleword-littlebyte.patch;patch=1 \ + file://ep93xx/arm-crunch-eabi-mvf0-scratch-ieee754.patch;patch=1 \ + file://ep93xx/arm-crunch-20000320.patch;patch=1 \ + file://ep93xx/arm-crunch-disable-cmpdi.patch;patch=1 \ + file://ep93xx/arm-crunch-fix-64bit-const-offsets.patch;patch=1 \ + file://ep93xx/arm-crunch-fp_consts.patch;patch=1 \ + file://ep93xx/arm-crunch-neg-enable.patch;patch=1 \ + file://ep93xx/arm-crunch-neg-protect.patch;patch=1 \ + file://ep93xx/arm-crunch-repair-truncxfsi.patch;patch=1 \ + file://ep93xx/arm-crunch-floatsi-no-scratch.patch;patch=1 \ + file://ep93xx/arm-crunch-movsf-movdf-Uy.patch;patch=1 \ + file://ep93xx/arm-crunch-drop-thumb2.patch;patch=1 \ + file://ep93xx/arm-crunch-arm_dbx_register_number.patch;patch=1 \ + file://ep93xx/arm-crunch-pipeline.patch;patch=1 \ + file://ep93xx/arm-crunch-ccmav-mode.patch;patch=1 \ + file://ep93xx/arm-crunch-cfcpy-with-cfsh64.patch;patch=1 \ + file://ep93xx/arm-crunch-mieee.patch;patch=1 \ + file://ep93xx/arm-size-bugfix.patch;patch=1 \ + file://ep93xx/arm-prologue_use-length.patch;patch=1 \ + file://ep93xx/arm-crunch-cftruncd32-attr.patch;patch=1 \ + file://ep93xx/arm-crunch-fix-cirrus-reorg7.patch;patch=1 \ + file://ep93xx/arm-crunch-cirrus-di-flag.patch;patch=1 \ + file://ep93xx/arm-crunch-disable-floatsi.patch;patch=1 \ " PACKAGE_ARCH_ep93xx = "${MACHINE_ARCH}" diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-32bit-disable.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-32bit-disable.patch deleted file mode 100644 index 88eaee322d..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-32bit-disable.patch +++ /dev/null @@ -1,85 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/cirrus.md-integer 2007-06-15 09:01:37.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-15 09:04:45.000000000 +1000 -@@ -149,7 +149,7 @@ - (match_operand:SI 1 "cirrus_fp_register" "0") - (mult:SI (match_operand:SI 2 "cirrus_fp_register" "v") - (match_operand:SI 3 "cirrus_fp_register" "v"))))] -- "0 && TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "0 && TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfmsc32%?\\t%V0, %V2, %V3" - [(set_attr "type" "mav_farith") - (set_attr "cirrus" "normal")] -@@ -305,7 +305,7 @@ - [(set (match_operand:SF 0 "cirrus_fp_register" "=v") - (float:SF (match_operand:SI 1 "s_register_operand" "r"))) - (clobber (match_scratch:DF 2 "=v"))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2" - [(set_attr "length" "8") - (set_attr "cirrus" "move")] -@@ -315,7 +315,7 @@ - [(set (match_operand:DF 0 "cirrus_fp_register" "=v") - (float:DF (match_operand:SI 1 "s_register_operand" "r"))) - (clobber (match_scratch:DF 2 "=v"))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2" - [(set_attr "length" "8") - (set_attr "cirrus" "move")] -@@ -339,7 +339,7 @@ - [(set (match_operand:SI 0 "s_register_operand" "=r") - (fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register" "v")))) - (clobber (match_scratch:DF 2 "=v"))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" - [(set_attr "length" "8") - (set_attr "cirrus" "normal")] -@@ -349,7 +349,7 @@ - [(set (match_operand:SI 0 "s_register_operand" "=r") - (fix:SI (fix:DF (match_operand:DF 1 "cirrus_fp_register" "v")))) - (clobber (match_scratch:DF 2 "=v"))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" - [(set_attr "length" "8") - (set_attr "cirrus" "normal")] ---- gcc-4.1.2/gcc/config/arm/arm.md-trunc 2007-06-15 10:56:13.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-15 11:01:22.000000000 +1000 -@@ -3130,7 +3130,7 @@ - (float:SF (match_operand:SI 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - " -- if (TARGET_MAVERICK) -+ if (TARGET_MAVERICK && 0) - { - emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1])); - DONE; -@@ -3142,7 +3142,7 @@ - (float:DF (match_operand:SI 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - " -- if (TARGET_MAVERICK) -+ if (TARGET_MAVERICK && 0) - { - emit_insn (gen_cirrus_floatsidf2 (operands[0], operands[1])); - DONE; -@@ -3154,7 +3154,7 @@ - (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))] - "TARGET_ARM && TARGET_HARD_FLOAT" - " -- if (TARGET_MAVERICK) -+ if (TARGET_MAVERICK && 0) - { - if (!cirrus_fp_register (operands[0], SImode)) - operands[0] = force_reg (SImode, operands[0]); -@@ -3170,7 +3170,7 @@ - (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))] - "TARGET_ARM && TARGET_HARD_FLOAT" - " -- if (TARGET_MAVERICK) -+ if (TARGET_MAVERICK && 0) - { - if (!cirrus_fp_register (operands[1], DFmode)) - operands[1] = force_reg (DFmode, operands[0]); diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-64bit-disable-4.2.0.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-64bit-disable-4.2.0.patch deleted file mode 100644 index 60b17852bd..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-64bit-disable-4.2.0.patch +++ /dev/null @@ -1,169 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/cirrus.md-integer 2007-06-15 09:01:37.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-15 09:04:45.000000000 +1000 -@@ -34,7 +34,7 @@ - [(set (match_operand:DI 0 "cirrus_fp_register" "=v") - (plus:DI (match_operand:DI 1 "cirrus_fp_register" "v") - (match_operand:DI 2 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfadd64%?\\t%V0, %V1, %V2" - [(set_attr "type" "mav_farith") - (set_attr "cirrus" "normal")] -@@ -74,7 +74,7 @@ - [(set (match_operand:DI 0 "cirrus_fp_register" "=v") - (minus:DI (match_operand:DI 1 "cirrus_fp_register" "v") - (match_operand:DI 2 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfsub64%?\\t%V0, %V1, %V2" - [(set_attr "type" "mav_farith") - (set_attr "cirrus" "normal")] -@@ -124,7 +124,7 @@ - [(set (match_operand:DI 0 "cirrus_fp_register" "=v") - (mult:DI (match_operand:DI 2 "cirrus_fp_register" "v") - (match_operand:DI 1 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfmul64%?\\t%V0, %V1, %V2" - [(set_attr "type" "mav_dmult") - (set_attr "cirrus" "normal")] -@@ -206,7 +206,7 @@ - [(set (match_operand:DI 0 "cirrus_fp_register" "=v") - (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v") - (match_operand:SI 2 "register_operand" "r")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfrshl64%?\\t%V1, %V0, %s2" - [(set_attr "cirrus" "normal")] - ) -@@ -215,7 +215,7 @@ - [(set (match_operand:DI 0 "cirrus_fp_register" "=v") - (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v") - (match_operand:SI 2 "cirrus_shift_const" "")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfsh64%?\\t%V0, %V1, #%s2" - [(set_attr "cirrus" "normal")] - ) -@@ -224,7 +224,7 @@ - [(set (match_operand:DI 0 "cirrus_fp_register" "=v") - (ashiftrt:DI (match_operand:DI 1 "cirrus_fp_register" "v") - (match_operand:SI 2 "cirrus_shift_const" "")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfsh64%?\\t%V0, %V1, #-%s2" - [(set_attr "cirrus" "normal")] - ) -@@ -232,7 +232,7 @@ - (define_insn "*cirrus_absdi2" - [(set (match_operand:DI 0 "cirrus_fp_register" "=v") - (abs:DI (match_operand:DI 1 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfabs64%?\\t%V0, %V1" - [(set_attr "cirrus" "normal")] - ) -@@ -238,11 +238,12 @@ - ) - - ;; This doesn't really clobber ``cc''. Fixme: aldyh. -+;; maybe buggy? - (define_insn "*cirrus_negdi2" - [(set (match_operand:DI 0 "cirrus_fp_register" "=v") - (neg:DI (match_operand:DI 1 "cirrus_fp_register" "v"))) - (clobber (reg:CC CC_REGNUM))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfneg64%?\\t%V0, %V1" - [(set_attr "cirrus" "normal")] - ) -@@ -324,14 +324,14 @@ - (define_insn "floatdisf2" - [(set (match_operand:SF 0 "cirrus_fp_register" "=v") - (float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfcvt64s%?\\t%V0, %V1" - [(set_attr "cirrus" "normal")]) - - (define_insn "floatdidf2" - [(set (match_operand:DF 0 "cirrus_fp_register" "=v") - (float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfcvt64d%?\\t%V0, %V1" - [(set_attr "cirrus" "normal")]) - -@@ -376,7 +376,7 @@ - (define_insn "*cirrus_arm_movdi" - [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v") - (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "* - { - switch (which_alternative) ---- gcc-4.1.2/gcc/config/arm/arm.md-64 2007-06-15 11:37:42.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-15 11:40:45.000000000 +1000 -@@ -357,7 +357,7 @@ - (clobber (reg:CC CC_REGNUM))])] - "TARGET_EITHER" - " -- if (TARGET_HARD_FLOAT && TARGET_MAVERICK) -+ if (TARGET_HARD_FLOAT && TARGET_MAVERICK && 0) - { - if (!cirrus_fp_register (operands[0], DImode)) - operands[0] = force_reg (DImode, operands[0]); -@@ -393,7 +393,7 @@ - (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0") - (match_operand:DI 2 "s_register_operand" "r, 0"))) - (clobber (reg:CC CC_REGNUM))] -- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" -+ "TARGET_ARM" - "#" - "TARGET_ARM && reload_completed" - [(parallel [(set (reg:CC_C CC_REGNUM) -@@ -421,7 +421,7 @@ - (match_operand:SI 2 "s_register_operand" "r,r")) - (match_operand:DI 1 "s_register_operand" "r,0"))) - (clobber (reg:CC CC_REGNUM))] -- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" -+ "TARGET_ARM" - "#" - "TARGET_ARM && reload_completed" - [(parallel [(set (reg:CC_C CC_REGNUM) -@@ -450,7 +450,7 @@ - (match_operand:SI 2 "s_register_operand" "r,r")) - (match_operand:DI 1 "s_register_operand" "r,0"))) - (clobber (reg:CC CC_REGNUM))] -- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" -+ "TARGET_ARM" - "#" - "TARGET_ARM && reload_completed" - [(parallel [(set (reg:CC_C CC_REGNUM) -@@ -838,7 +838,7 @@ - if (TARGET_HARD_FLOAT && TARGET_MAVERICK - && TARGET_ARM - && cirrus_fp_register (operands[0], DImode) -- && cirrus_fp_register (operands[1], DImode)) -+ && cirrus_fp_register (operands[1], DImode) && 0) - { - emit_insn (gen_cirrus_subdi3 (operands[0], operands[1], operands[2])); - DONE; -@@ -2599,7 +2599,7 @@ - values to iwmmxt regs and back. */ - FAIL; - } -- else if (!TARGET_REALLY_IWMMXT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)) -+ else if (!TARGET_REALLY_IWMMXT) - FAIL; - " - ) -@@ -4215,7 +4215,6 @@ - [(set (match_operand:DI 0 "nonimmediate_operand" "=l,l,l,l,>,l, m,*r") - (match_operand:DI 1 "general_operand" "l, I,J,>,l,mi,l,*r"))] - "TARGET_THUMB -- && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) - && ( register_operand (operands[0], DImode) - || register_operand (operands[1], DImode))" - "* diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-64bit-disable0.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-64bit-disable0.patch deleted file mode 100644 index 95abf68a60..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-64bit-disable0.patch +++ /dev/null @@ -1,47 +0,0 @@ -diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.md gcc-4.1.2/gcc/config/arm/arm.md ---- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.md 2006-09-28 03:10:22.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-15 09:53:21.000000000 +1000 -@@ -6865,10 +6877,12 @@ - ) - - ;; Cirrus DI compare instruction -+;; This is disabled and left go through ARM core registers, because currently -+;; Crunch coprocessor does only signed comparison. - (define_expand "cmpdi" - [(match_operand:DI 0 "cirrus_fp_register" "") - (match_operand:DI 1 "cirrus_fp_register" "")] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK & 0" - "{ - arm_compare_op0 = operands[0]; - arm_compare_op1 = operands[1]; -@@ -6879,7 +6893,7 @@ - [(set (reg:CC CC_REGNUM) - (compare:CC (match_operand:DI 0 "cirrus_fp_register" "v") - (match_operand:DI 1 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK & 0" - "cfcmp64%?\\tr15, %V0, %V1" - [(set_attr "type" "mav_farith") - (set_attr "cirrus" "compare")] -@@ -10105,6 +10119,7 @@ - [(unspec:SI [(match_operand:SI 0 "register_operand" "")] UNSPEC_PROLOGUE_USE)] - "" - "%@ %0 needed for prologue" -+ [(set_attr "length" "0")] - ) - - -diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/cirrus.md gcc-4.1.2/gcc/config/arm/cirrus.md ---- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/cirrus.md 2005-06-25 11:22:41.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-05-15 09:55:29.000000000 +1000 -@@ -348,7 +348,8 @@ - (clobber (match_scratch:DF 2 "=v"))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" - "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" -- [(set_attr "length" "8")] -+ [(set_attr "length" "8") -+ (set_attr "cirrus" "normal")] - ) - - (define_insn "*cirrus_truncdfsf2" diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-and-or.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-and-or.patch deleted file mode 100644 index 24357d316e..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-and-or.patch +++ /dev/null @@ -1,67 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-13 17:16:38.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-13 17:35:19.000000000 +1000 -@@ -8455,7 +8455,7 @@ - (and:SI (match_operator:SI 1 "arm_comparison_operator" - [(match_operand 3 "cc_register" "") (const_int 0)]) - (match_operand:SI 2 "s_register_operand" "r")))] -- "TARGET_ARM" -+ "TARGET_ARM && !TARGET_MAVERICK" - "mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1" - [(set_attr "conds" "use") - (set_attr "length" "8")] -@@ -8466,7 +8466,7 @@ - (ior:SI (match_operator:SI 2 "arm_comparison_operator" - [(match_operand 3 "cc_register" "") (const_int 0)]) - (match_operand:SI 1 "s_register_operand" "0,?r")))] -- "TARGET_ARM" -+ "TARGET_ARM && !TARGET_MAVERICK" - "@ - orr%d2\\t%0, %1, #1 - mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1" -@@ -8734,7 +8734,8 @@ - (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM - && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_OR_Y) -- != CCmode)" -+ != CCmode) -+ && !TARGET_MAVERICK" - "#" - "TARGET_ARM && reload_completed" - [(set (match_dup 7) -@@ -8765,7 +8766,7 @@ - (set (match_operand:SI 7 "s_register_operand" "=r") - (ior:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)]) - (match_op_dup 6 [(match_dup 4) (match_dup 5)])))] -- "TARGET_ARM" -+ "TARGET_ARM && !TARGET_MAVERICK" - "#" - "TARGET_ARM && reload_completed" - [(set (match_dup 0) -@@ -8790,7 +8791,8 @@ - (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM - && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) -- != CCmode)" -+ != CCmode) -+ && !TARGET_MAVERICK" - "#" - "TARGET_ARM && reload_completed - && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) -@@ -8823,7 +8825,7 @@ - (set (match_operand:SI 7 "s_register_operand" "=r") - (and:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)]) - (match_op_dup 6 [(match_dup 4) (match_dup 5)])))] -- "TARGET_ARM" -+ "TARGET_ARM && !TARGET_MAVERICK" - "#" - "TARGET_ARM && reload_completed" - [(set (match_dup 0) -@@ -8850,7 +8852,7 @@ - [(match_operand:SI 4 "s_register_operand" "r,r,r") - (match_operand:SI 5 "arm_add_operand" "rIL,rIL,rIL")]))) - (clobber (reg:CC CC_REGNUM))] -- "TARGET_ARM -+ "TARGET_ARM && !TARGET_MAVERICK - && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) - == CCmode)" - "#" diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-cfcvt64-disable.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-cfcvt64-disable.patch deleted file mode 100644 index f9280b18b5..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-cfcvt64-disable.patch +++ /dev/null @@ -1,19 +0,0 @@ ---- gcc-4.2.0/gcc/config/arm/cirrus.md-original 2007-06-25 15:32:01.000000000 +1000 -+++ gcc-4.2.0/gcc/config/arm/cirrus.md 2007-06-25 15:32:14.000000000 +1000 -@@ -325,14 +325,14 @@ - (define_insn "floatdisf2" - [(set (match_operand:SF 0 "cirrus_fp_register" "=v") - (float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfcvt64s%?\\t%V0, %V1" - [(set_attr "cirrus" "normal")]) - - (define_insn "floatdidf2" - [(set (match_operand:DF 0 "cirrus_fp_register" "=v") - (float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfcvt64d%?\\t%V0, %V1" - [(set_attr "cirrus" "normal")]) - diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-cfcvtds-disable.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-cfcvtds-disable.patch deleted file mode 100644 index ec09ea16a1..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-cfcvtds-disable.patch +++ /dev/null @@ -1,32 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-15 10:06:24.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-15 10:07:21.000000000 +1000 -@@ -355,11 +355,12 @@ - (set_attr "cirrus" "normal")] - ) - -+; appears to be buggy - causes 20000320-1.c to fail in execute/ieee - (define_insn "*cirrus_truncdfsf2" - [(set (match_operand:SF 0 "cirrus_fp_register" "=v") - (float_truncate:SF - (match_operand:DF 1 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfcvtds%?\\t%V0, %V1" - [(set_attr "cirrus" "normal")] - ) ---- gcc-4.1.2/gcc/config/arm/arm.md-truncdfsf2 2007-06-15 10:25:43.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-15 10:27:01.000000000 +1000 -@@ -3181,11 +3181,12 @@ - - ;; Truncation insns - -+;; Maverick Crunch truncdfsf2 is buggy - see cirrus.md - (define_expand "truncdfsf2" - [(set (match_operand:SF 0 "s_register_operand" "") - (float_truncate:SF - (match_operand:DF 1 "s_register_operand" "")))] -- "TARGET_ARM && TARGET_HARD_FLOAT" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" - "" - ) - diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-cirrus-bugfixes.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-cirrus-bugfixes.patch deleted file mode 100644 index cb0af8546d..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-cirrus-bugfixes.patch +++ /dev/null @@ -1,573 +0,0 @@ -diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.c gcc-4.1.2/gcc/config/arm/arm.c ---- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.c 2007-05-09 16:32:29.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-15 09:39:41.000000000 +1000 -@@ -4,6 +4,7 @@ - Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) - and Martin Simmons (@harleqn.co.uk). - More major hacks by Richard Earnshaw (rearnsha@arm.com). -+ Cirrus Crunch bugfixes by Vladimir Ivanov (vladit@nucleusys.com) - - This file is part of GCC. - -@@ -131,9 +132,17 @@ - static bool arm_xscale_rtx_costs (rtx, int, int, int *); - static bool arm_9e_rtx_costs (rtx, int, int, int *); - static int arm_address_cost (rtx); --static bool arm_memory_load_p (rtx); -+// static bool arm_memory_load_p (rtx); - static bool arm_cirrus_insn_p (rtx); --static void cirrus_reorg (rtx); -+// static void cirrus_reorg (rtx); -+static bool arm_mem_access_p (rtx); -+static bool cirrus_dest_regn_p (rtx, int); -+static rtx cirrus_prev_next_mach_insn (rtx, int *, int); -+static rtx cirrus_prev_mach_insn (rtx, int *); -+static rtx cirrus_next_mach_insn (rtx, int *); -+static void cirrus_reorg_branch (rtx); -+static void cirrus_reorg_bug1 (rtx); -+static void cirrus_reorg_bug10_12 (rtx); - static void arm_init_builtins (void); - static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); - static void arm_init_iwmmxt_builtins (void); -@@ -5399,41 +5412,6 @@ - || TREE_CODE (valtype) == COMPLEX_TYPE)); - } - --/* Returns TRUE if INSN is an "LDR REG, ADDR" instruction. -- Use by the Cirrus Maverick code which has to workaround -- a hardware bug triggered by such instructions. */ --static bool --arm_memory_load_p (rtx insn) --{ -- rtx body, lhs, rhs;; -- -- if (insn == NULL_RTX || GET_CODE (insn) != INSN) -- return false; -- -- body = PATTERN (insn); -- -- if (GET_CODE (body) != SET) -- return false; -- -- lhs = XEXP (body, 0); -- rhs = XEXP (body, 1); -- -- lhs = REG_OR_SUBREG_RTX (lhs); -- -- /* If the destination is not a general purpose -- register we do not have to worry. */ -- if (GET_CODE (lhs) != REG -- || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS) -- return false; -- -- /* As well as loads from memory we also have to react -- to loads of invalid constants which will be turned -- into loads from the minipool. */ -- return (GET_CODE (rhs) == MEM -- || GET_CODE (rhs) == SYMBOL_REF -- || note_invalid_constants (insn, -1, false)); --} -- - /* Return TRUE if INSN is a Cirrus instruction. */ - static bool - arm_cirrus_insn_p (rtx insn) -@@ -5452,124 +5433,218 @@ - return attr != CIRRUS_NOT; - } - --/* Cirrus reorg for invalid instruction combinations. */ --static void --cirrus_reorg (rtx first) -+/* Return TRUE if ISN does memory access. */ -+static bool -+arm_mem_access_p (rtx insn) - { -- enum attr_cirrus attr; -- rtx body = PATTERN (first); -- rtx t; -- int nops; -+ enum attr_type attr; - -- /* Any branch must be followed by 2 non Cirrus instructions. */ -- if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN) -- { -- nops = 0; -- t = next_nonnote_insn (first); -+ /* get_attr aborts on USE and CLOBBER. */ -+ if (!insn -+ || GET_CODE (insn) != INSN -+ || GET_CODE (PATTERN (insn)) == USE -+ || GET_CODE (PATTERN (insn)) == CLOBBER) -+ return 0; - -- if (arm_cirrus_insn_p (t)) -- ++ nops; -+ attr = get_attr_type (insn); - -- if (arm_cirrus_insn_p (next_nonnote_insn (t))) -- ++ nops; -+ return attr == TYPE_LOAD_BYTE -+ || attr == TYPE_LOAD1 || attr == TYPE_LOAD2 || attr == TYPE_LOAD3 || attr == TYPE_LOAD4 -+ || attr == TYPE_F_CVT -+ || attr == TYPE_F_MEM_R || attr == TYPE_R_MEM_F || attr == TYPE_F_2_R || attr == TYPE_R_2_F -+ || attr == TYPE_F_LOAD || attr == TYPE_F_LOADS || attr == TYPE_F_LOADD -+ || attr == TYPE_F_STORE || attr == TYPE_F_STORES || attr == TYPE_F_STORED -+ || attr == TYPE_STORE1 || attr == TYPE_STORE2 || attr == TYPE_STORE3 || attr == TYPE_STORE4; -+ -+} - -- while (nops --) -- emit_insn_after (gen_nop (), first); -+/* Return TRUE if destination is certain Cirrus register. */ -+static bool -+cirrus_dest_regn_p (rtx body, int regn) -+{ -+ rtx lhs; -+ int reg; -+ lhs = XEXP (body, 0); -+ if (GET_CODE (lhs) != REG) -+ return 0; - -- return; -- } -+ reg = REGNO (lhs); -+ if (REGNO_REG_CLASS (reg) != CIRRUS_REGS) -+ return 0; - -- /* (float (blah)) is in parallel with a clobber. */ -- if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) -- body = XVECEXP (body, 0, 0); -+ return reg == regn; -+} -+ -+/* Get previous/next machine instruction during Cirrus workaround scans. -+ Assume worst case (for the purpose of Cirrus workarounds) -+ for JUMP / CALL instructions. */ -+static rtx -+cirrus_prev_next_mach_insn (rtx insn, int *len, int next) -+{ -+ rtx t; -+ int l = 0; - -- if (GET_CODE (body) == SET) -+ /* It seems that we can count only on INSN length. */ -+ for ( ; ; ) - { -- rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1); -+ if (next) -+ insn = NEXT_INSN (insn); -+ else -+ insn = PREV_INSN (insn); -+ if (!insn) -+ break; - -- /* cfldrd, cfldr64, cfstrd, cfstr64 must -- be followed by a non Cirrus insn. */ -- if (get_attr_cirrus (first) == CIRRUS_DOUBLE) -- { -- if (arm_cirrus_insn_p (next_nonnote_insn (first))) -- emit_insn_after (gen_nop (), first); -+ if (GET_CODE (insn) == INSN) -+ { -+ l = get_attr_length (insn) / 4; -+ if (l) -+ break; -+ } -+ else if (GET_CODE (insn) == JUMP_INSN) -+ { -+ l = 1; -+ t = is_jump_table (insn); -+ if (t) -+ l += get_jump_table_size (t) / 4; -+ break; -+ } -+ else if (GET_CODE (insn) == CALL_INSN) -+ { -+ l = 1; -+ break; -+ } -+ } - -- return; -- } -- else if (arm_memory_load_p (first)) -- { -- unsigned int arm_regno; -+ if (len) -+ *len = l; - -- /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr, -- ldr/cfmv64hr combination where the Rd field is the same -- in both instructions must be split with a non Cirrus -- insn. Example: -- -- ldr r0, blah -- nop -- cfmvsr mvf0, r0. */ -- -- /* Get Arm register number for ldr insn. */ -- if (GET_CODE (lhs) == REG) -- arm_regno = REGNO (lhs); -- else -- { -- gcc_assert (GET_CODE (rhs) == REG); -- arm_regno = REGNO (rhs); -- } -+ return insn; -+} - -- /* Next insn. */ -- first = next_nonnote_insn (first); -+static rtx -+cirrus_prev_mach_insn (rtx insn, int *len) -+{ -+ return cirrus_prev_next_mach_insn (insn, len, 0); -+} - -- if (! arm_cirrus_insn_p (first)) -- return; -+static rtx -+cirrus_next_mach_insn (rtx insn, int *len) -+{ -+ return cirrus_prev_next_mach_insn (insn, len, 1); -+} - -- body = PATTERN (first); -+/* Cirrus reorg for branch slots. */ -+static void -+cirrus_reorg_branch (rtx insn) -+{ -+ rtx t; -+ int nops, l; - -- /* (float (blah)) is in parallel with a clobber. */ -- if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0)) -- body = XVECEXP (body, 0, 0); -- -- if (GET_CODE (body) == FLOAT) -- body = XEXP (body, 0); -- -- if (get_attr_cirrus (first) == CIRRUS_MOVE -- && GET_CODE (XEXP (body, 1)) == REG -- && arm_regno == REGNO (XEXP (body, 1))) -- emit_insn_after (gen_nop (), first); -+ /* TODO: handle jump-tables. */ -+ t = is_jump_table (insn); -+ if (t) -+ return; -+ -+ /* Any branch must be followed by 2 non Cirrus instructions. */ -+ t = insn; -+ for (nops = 2; nops > 0; ) -+ { -+ if (!cirrus_next_mach_insn (t, 0)) -+ { -+ insn = t; -+ break; -+ } -+ t = cirrus_next_mach_insn (t, &l); -+ if (arm_cirrus_insn_p (t)) -+ break; -+ nops -= l; - -- return; -- } - } - -- /* get_attr cannot accept USE or CLOBBER. */ -- if (!first -- || GET_CODE (first) != INSN -- || GET_CODE (PATTERN (first)) == USE -- || GET_CODE (PATTERN (first)) == CLOBBER) -- return; -+ while (nops-- > 0) -+ emit_insn_after (gen_nop (), insn); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */ -+} - -- attr = get_attr_cirrus (first); -+/* Cirrus reorg for bug #1 (cirrus + cfcmpxx). */ -+static void -+cirrus_reorg_bug1 (rtx insn) -+{ -+ rtx body = PATTERN (insn), body2; -+ rtx t; -+ int i, nops, l; -+ enum attr_cirrus attr; - -- /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...) -- must be followed by a non-coprocessor instruction. */ -- if (attr == CIRRUS_COMPARE) -+ /* Check if destination or clobber is Cirrus register. */ -+ if (GET_CODE (body) == PARALLEL) - { -- nops = 0; -- -- t = next_nonnote_insn (first); -+ for (i = 0; i < XVECLEN (body, 0); i++) -+ { -+ body2 = XVECEXP (body, 0, i); -+ if (GET_CODE (body2) == SET) -+ { -+ if (cirrus_dest_regn_p (body2, LAST_CIRRUS_FP_REGNUM)) -+ { -+ nops = 5; -+ goto fix; -+ } -+ } -+ else if (GET_CODE (body2) == CLOBBER) -+ { -+ if (cirrus_dest_regn_p (body2, LAST_CIRRUS_FP_REGNUM)) -+ { -+ nops = 4; -+ goto fix; -+ } -+ } -+ } -+ } -+ else if (GET_CODE (body) == SET) -+ { -+ if (cirrus_dest_regn_p (body, LAST_CIRRUS_FP_REGNUM)) -+ { -+ nops = 5; -+ goto fix; -+ } -+ } -+ return; - -- if (arm_cirrus_insn_p (t)) -- ++ nops; -+fix: -+ t = insn; -+ for ( ; nops > 0; ) -+ { -+ t = cirrus_next_mach_insn (t, &l); -+ if (!t) -+ break; -+ if (GET_CODE (t) == JUMP_INSN -+ || GET_CODE (t) == CALL_INSN) -+ { -+ nops -= l; -+ break; -+ } -+ else if (arm_cirrus_insn_p (t)) -+ { -+ attr = get_attr_cirrus (t); -+ if (attr == CIRRUS_COMPARE) -+ break; -+ } -+ nops -= l; -+ } - -- if (arm_cirrus_insn_p (next_nonnote_insn (t))) -- ++ nops; -+ while (nops-- > 0) -+ emit_insn_after (gen_nop (), insn); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */ -+} - -- while (nops --) -- emit_insn_after (gen_nop (), first); -+/* Cirrus reorg for bugs #10 and #12 (data aborts). */ -+static void -+cirrus_reorg_bug10_12 (rtx insn) -+{ -+ rtx t; - -- return; -- } -+ t = cirrus_next_mach_insn (insn, 0); -+ if (arm_cirrus_insn_p (t)) -+ if (TARGET_CIRRUS_D0 || -+ get_attr_cirrus (t) == CIRRUS_DOUBLE) -+ emit_insn_after (gen_nop (), insn); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */ - } - - /* Return TRUE if X references a SYMBOL_REF. */ -@@ -7727,7 +7796,7 @@ - { - Mnode * mp; - Mnode * nmp; -- int align64 = 0; -+ int align64 = 0, stuffnop = 0; - - if (ARM_DOUBLEWORD_ALIGN) - for (mp = minipool_vector_head; mp != NULL; mp = mp->next) -@@ -7742,8 +7811,27 @@ - ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n", - INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4); - -+ /* Check if branch before minipool is already stuffed with nops. */ -+ if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1) -+ { -+ rtx t; -+ -+ t = prev_active_insn (scan); -+ if (GET_CODE (t) != INSN -+ || PATTERN (t) != const0_rtx) -+ stuffnop = 1; -+ } - scan = emit_label_after (gen_label_rtx (), scan); - scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan); -+ /* Last instruction was branch, so put two non-Cirrus opcodes. */ -+ if (stuffnop) -+ { -+#if TARGET_CIRRUS /* This is doubling up on nops, so I don't think this is a good idea */ -+ emit_insn_before (gen_nop (), scan); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */ -+ emit_insn_before (gen_nop (), scan); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */ -+#endif -+ } -+ - scan = emit_label_after (minipool_vector_label, scan); - - for (mp = minipool_vector_head; mp != NULL; mp = nmp) -@@ -8151,15 +8239,38 @@ - gcc_assert (GET_CODE (insn) == NOTE); - minipool_pad = 0; - -+#if TARGET_CIRRUS /* I think this is a double-up */ -+ /* Scan all the insn and fix Cirrus issues. */ -+ if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1) -+ { -+ rtx t, s; -+ -+ for (t = cirrus_next_mach_insn (insn, 0); t; t = cirrus_next_mach_insn (t, 0)) -+ if (arm_mem_access_p (t)) -+ cirrus_reorg_bug10_12 (t); -+ -+ if (TARGET_CIRRUS_D0) -+ for (t = cirrus_next_mach_insn (insn, 0); t; t = cirrus_next_mach_insn (t, 0)) -+ if (arm_cirrus_insn_p (t)) -+ cirrus_reorg_bug1 (t); -+ -+ /* Find last insn. */ -+ for (t = insn; ; t = s) -+ { -+ s = cirrus_next_mach_insn (t, 0); -+ if (!s) -+ break; -+ } -+ /* Scan backward and fix branches. - WARNING: appears to cause "bad immediate value for offset" problems! */ -+ for ( ; t; t = cirrus_prev_mach_insn (t, 0)) -+ if (GET_CODE (t) == JUMP_INSN -+ || GET_CODE (t) == CALL_INSN) -+ cirrus_reorg_branch (t); -+ } -+#endif - /* Scan all the insns and record the operands that will need fixing. */ - for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn)) - { -- if (TARGET_CIRRUS_FIX_INVALID_INSNS -- && (arm_cirrus_insn_p (insn) -- || GET_CODE (insn) == JUMP_INSN -- || arm_memory_load_p (insn))) -- cirrus_reorg (insn); -- - if (GET_CODE (insn) == BARRIER) - push_minipool_barrier (insn, address); - else if (INSN_P (insn)) -@@ -11755,16 +11910,10 @@ - || get_attr_conds (this_insn) != CONDS_NOCOND) - fail = TRUE; - -- /* A conditional cirrus instruction must be followed by -- a non Cirrus instruction. However, since we -- conditionalize instructions in this function and by -- the time we get here we can't add instructions -- (nops), because shorten_branches() has already been -- called, we will disable conditionalizing Cirrus -- instructions to be safe. */ -- if (GET_CODE (scanbody) != USE -- && GET_CODE (scanbody) != CLOBBER -- && get_attr_cirrus (this_insn) != CIRRUS_NOT) -+ /* To avoid erratic behaviour, we avoid conditional Cirrus -+ instructions when doing workarounds. */ -+ if (arm_cirrus_insn_p(this_insn) -+ && (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1)) - fail = TRUE; - break; - -diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.h gcc-4.1.2/gcc/config/arm/arm.h ---- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.h 2005-11-05 01:02:51.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.h 2007-05-15 10:15:05.000000000 +1000 -@@ -5,6 +5,7 @@ - and Martin Simmons (@harleqn.co.uk). - More major hacks by Richard Earnshaw (rearnsha@arm.com) - Minor hacks by Nick Clifton (nickc@cygnus.com) -+ Cirrus Crunch fixes by Vladimir Ivanov (vladitx@nucleusys.com) - - This file is part of GCC. - -@@ -140,7 +141,9 @@ - %{msoft-float:%{mhard-float: \ - %e-msoft-float and -mhard_float may not be used together}} \ - %{mbig-endian:%{mlittle-endian: \ -- %e-mbig-endian and -mlittle-endian may not be used together}}" -+ %e-mbig-endian and -mlittle-endian may not be used together}} \ -+%{mfix-crunch-d0:%{mfix-crunch-d1: \ -+ %e-mfix-crunch-d0 and -mfix-crunch-d1 may not be used together}}" - - #ifndef CC1_SPEC - #define CC1_SPEC "" -@@ -179,6 +182,9 @@ - #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) - #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA) - #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK) -+#define TARGET_CIRRUS (arm_arch_cirrus) -+#define TARGET_CIRRUS_D0 0 /* (target_flags & ARM_FLAG_CIRRUS_D0) */ -+#define TARGET_CIRRUS_D1 1 /* (target_flags & ARM_FLAG_CIRRUS_D1) */ - #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP) - #define TARGET_IWMMXT (arm_arch_iwmmxt) - #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM) -diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.opt gcc-4.1.2/gcc/config/arm/arm.opt ---- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.opt 2005-11-05 01:02:51.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.opt 2007-05-15 10:09:31.000000000 +1000 -@@ -68,6 +68,14 @@ - Target Report Mask(CIRRUS_FIX_INVALID_INSNS) - Cirrus: Place NOPs to avoid invalid instruction combinations - -+fix-crunch-d0 -+Target Report Mask(ARM_FLAG_CIRRUS_D0) -+Cirrus: workarounds for Crunch coprocessor revision D0 -+ -+fix-crunch-d1 -+Target Report Mask(ARM_FLAG_CIRRUS_D1) -+Cirrus: workarounds for Crunch coprocessor revision D1 -+ - mcpu= - Target RejectNegative Joined - Specify the name of the target CPU -diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/doc/invoke.texi gcc-4.1.2/gcc/doc/invoke.texi ---- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/doc/invoke.texi 2006-09-26 07:21:58.000000000 +1000 -+++ gcc-4.1.2/gcc/doc/invoke.texi 2007-05-15 10:07:04.000000000 +1000 -@@ -408,7 +408,7 @@ - -msingle-pic-base -mno-single-pic-base @gol - -mpic-register=@var{reg} @gol - -mnop-fun-dllimport @gol ---mcirrus-fix-invalid-insns -mno-cirrus-fix-invalid-insns @gol -+-mfix-crunch-d0 -mfix-crunch-d1 @gol - -mpoke-function-name @gol - -mthumb -marm @gol - -mtpcs-frame -mtpcs-leaf-frame @gol -@@ -7435,17 +7435,12 @@ - Specify the register to be used for PIC addressing. The default is R10 - unless stack-checking is enabled, when R9 is used. - --@item -mcirrus-fix-invalid-insns --@opindex mcirrus-fix-invalid-insns --@opindex mno-cirrus-fix-invalid-insns --Insert NOPs into the instruction stream to in order to work around --problems with invalid Maverick instruction combinations. This option --is only valid if the @option{-mcpu=ep9312} option has been used to --enable generation of instructions for the Cirrus Maverick floating --point co-processor. This option is not enabled by default, since the --problem is only present in older Maverick implementations. The default --can be re-enabled by use of the @option{-mno-cirrus-fix-invalid-insns} --switch. -+@item -mfix-crunch-d0 -+@itemx -mfix-crunch-d1 -+@opindex mfix-crunch-d0 -+@opindex mfix-crunch-d1 -+Enable workarounds for the Cirrus MaverickCrunch coprocessor revisions -+D0 and D1 respectively. - - @item -mpoke-function-name - @opindex mpoke-function-name diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-compare-geu.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-compare-geu.patch deleted file mode 100644 index 3d27cc1d9d..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-compare-geu.patch +++ /dev/null @@ -1,48 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-08 06:39:41.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-08 06:41:00.000000000 +1000 -@@ -7125,6 +7125,22 @@ - (set_attr "length" "8")] - ) - -+; Special pattern to match GEU for MAVERICK. -+(define_insn "*arm_bgeu" -+ [(set (pc) -+ (if_then_else (geu (match_operand 1 "cc_register" "") (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "TARGET_ARM && (TARGET_MAVERICK)" -+ "* -+ gcc_assert (!arm_ccfsm_state); -+ if (get_attr_cirrus (prev_active_insn(insn)) == CIRRUS_COMPARE) -+ return \"beq\\t%l0\;bvs\\t%l0\"; else return \"bge\\t%l0\;nop\"; -+ " -+ [(set_attr "conds" "jump_clob") -+ (set_attr "length" "8")] -+) -+ - ; Special pattern to match UNLT for MAVERICK - UGLY since we need to test for Z=0 && V=0. - (define_insn "*arm_bunlt" - [(set (pc) -@@ -7240,6 +7256,22 @@ - (set_attr "length" "8")] - ) - -+; Special pattern to match reversed GEU for MAVERICK. -+(define_insn "*arm_bgeu_reversed" -+ [(set (pc) -+ (if_then_else (geu (match_operand 1 "cc_register" "") (const_int 0)) -+ (pc) -+ (label_ref (match_operand 0 "" ""))))] -+ "TARGET_ARM && (TARGET_MAVERICK)" -+ "* -+ gcc_assert (!arm_ccfsm_state); -+ -+ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; -+ " -+ [(set_attr "conds" "jump_clob") -+ (set_attr "length" "12")] -+) -+ - ; Special pattern to match reversed UNLT for MAVERICK. - (define_insn "*arm_bunlt_reversed" - [(set (pc) diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-compare-unordered.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-compare-unordered.patch deleted file mode 100644 index c4fcdb3746..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-compare-unordered.patch +++ /dev/null @@ -1,98 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-07 14:45:22.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-07 15:13:58.000000000 +1000 -@@ -7001,16 +7001,16 @@ - (if_then_else (unordered (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0, - arm_compare_op1);" - ) - - (define_expand "bordered" - [(set (pc) - (if_then_else (ordered (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0, - arm_compare_op1);" -@@ -7141,6 +7141,38 @@ - (set_attr "length" "8")] - ) - -+; Special pattern to match UNORDERED for MAVERICK - UGLY since we need to test for Z=0 && N=0. -+(define_insn "*arm_bunordered" -+ [(set (pc) -+ (if_then_else (unordered (match_operand:CCFP 1 "cc_register" "") (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" -+ "* -+ gcc_assert (!arm_ccfsm_state); -+ -+ return \"beq\\t.+12\;bmi\\t.+8\;b\\t%l0\"; -+ " -+ [(set_attr "conds" "jump_clob") -+ (set_attr "length" "12")] -+) -+ -+; Special pattern to match ORDERED for MAVERICK. -+(define_insn "*arm_bordered" -+ [(set (pc) -+ (if_then_else (ordered (match_operand:CCFP 1 "cc_register" "") (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" -+ "* -+ gcc_assert (!arm_ccfsm_state); -+ -+ return \"beq\\t%l0\;bmi\\t%l0\"; -+ " -+ [(set_attr "conds" "jump_clob") -+ (set_attr "length" "8")] -+) -+ - (define_insn "*arm_cond_branch" - [(set (pc) - (if_then_else (match_operator 1 "arm_comparison_operator" -@@ -7224,6 +7256,37 @@ - (set_attr "length" "8")] - ) - -+; Special pattern to match reversed UNORDERED for MAVERICK. -+(define_insn "*arm_bunordered_reversed" -+ [(set (pc) -+ (if_then_else (unordered (match_operand:CCFP 1 "cc_register" "") (const_int 0)) -+ (pc) -+ (label_ref (match_operand 0 "" ""))))] -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" -+ "* -+ gcc_assert (!arm_ccfsm_state); -+ -+ return \"beq\\t%l0\;bmi\\t%l0\"; -+ " -+ [(set_attr "conds" "jump_clob") -+ (set_attr "length" "8")] -+) -+ -+; Special pattern to match reversed ORDERED for MAVERICK - UGLY since we need to test for Z=0 && N=0. -+(define_insn "*arm_bordered_reversed" -+ [(set (pc) -+ (if_then_else (ordered (match_operand:CCFP 1 "cc_register" "") (const_int 0)) -+ (pc) -+ (label_ref (match_operand 0 "" ""))))] -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" -+ "* -+ gcc_assert (!arm_ccfsm_state); -+ -+ return \"beq\\t.+12\;bmi\\t.+8\;b\\t%l0\"; -+ " -+ [(set_attr "conds" "jump_clob") -+ (set_attr "length" "12")] -+) - - (define_insn "*arm_cond_branch_reversed" - [(set (pc) diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-compare-unordered.patch-z-eq b/recipes/gcc/gcc-4.2.4/arm-crunch-compare-unordered.patch-z-eq deleted file mode 100644 index 715fb95086..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-compare-unordered.patch-z-eq +++ /dev/null @@ -1,98 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-07 14:45:22.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-07 15:13:58.000000000 +1000 -@@ -7001,16 +7001,16 @@ - (if_then_else (unordered (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0, - arm_compare_op1);" - ) - - (define_expand "bordered" - [(set (pc) - (if_then_else (ordered (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0, - arm_compare_op1);" -@@ -7141,6 +7141,38 @@ - (set_attr "length" "8")] - ) - -+; Special pattern to match UNORDERED for MAVERICK - UGLY since we need to test for C=0 && N=0 -+(define_insn "*arm_bunordered" -+ [(set (pc) -+ (if_then_else (unordered (match_operand 1 "cc_register" "") (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" -+ "* -+ gcc_assert (!arm_ccfsm_state); -+ -+ return \"bcs\\t.+12\;bmi\\t.+8\;b\\t%l0\"; -+ " -+ [(set_attr "conds" "jump_clob") -+ (set_attr "length" "12")] -+) -+ -+; Special pattern to match ORDERED for MAVERICK. -+(define_insn "*arm_bordered" -+ [(set (pc) -+ (if_then_else (ordered (match_operand 1 "cc_register" "") (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" -+ "* -+ gcc_assert (!arm_ccfsm_state); -+ -+ return \"bcs\\t%l0\;bmi\\t%l0\"; -+ " -+ [(set_attr "conds" "jump_clob") -+ (set_attr "length" "8")] -+) -+ - (define_insn "*arm_cond_branch" - [(set (pc) - (if_then_else (match_operator 1 "arm_comparison_operator" -@@ -7224,6 +7256,37 @@ - (set_attr "length" "8")] - ) - -+; Special pattern to match reversed UNORDERED for MAVERICK. -+(define_insn "*arm_bunordered_reversed" -+ [(set (pc) -+ (if_then_else (unordered (match_operand 1 "cc_register" "") (const_int 0)) -+ (pc) -+ (label_ref (match_operand 0 "" ""))))] -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" -+ "* -+ gcc_assert (!arm_ccfsm_state); -+ -+ return \"bcs\\t%l0\;bmi\\t%l0\"; -+ " -+ [(set_attr "conds" "jump_clob") -+ (set_attr "length" "8")] -+) -+ -+; Special pattern to match reversed ORDERED for MAVERICK - UGLY since we need to test for C=0 && N=0 -+(define_insn "*arm_bordered_reversed" -+ [(set (pc) -+ (if_then_else (ordered (match_operand 1 "cc_register" "") (const_int 0)) -+ (pc) -+ (label_ref (match_operand 0 "" ""))))] -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" -+ "* -+ gcc_assert (!arm_ccfsm_state); -+ -+ return \"bcs\\t.+12\;bmi\\t.+8\;b\\t%l0\"; -+ " -+ [(set_attr "conds" "jump_clob") -+ (set_attr "length" "12")] -+) - - (define_insn "*arm_cond_branch_reversed" - [(set (pc) diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-compare.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-compare.patch deleted file mode 100644 index ccbb4854c3..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-compare.patch +++ /dev/null @@ -1,400 +0,0 @@ -diff -urN gcc-4.1.2/gcc/config/arm/arm.c ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.c ---- gcc-4.1.2/gcc/config/arm/arm.c 2007-05-31 12:39:48.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-29 17:19:38.000000000 +1000 -@@ -11427,26 +11427,53 @@ - /* These encodings assume that AC=1 in the FPA system control - byte. This allows us to handle all cases except UNEQ and - LTGT. */ -- switch (comp_code) -- { -- case GE: return ARM_GE; -- case GT: return ARM_GT; -- case LE: return ARM_LS; -- case LT: return ARM_MI; -- case NE: return ARM_NE; -- case EQ: return ARM_EQ; -- case ORDERED: return ARM_VC; -- case UNORDERED: return ARM_VS; -- case UNLT: return ARM_LT; -- case UNLE: return ARM_LE; -- case UNGT: return ARM_HI; -- case UNGE: return ARM_PL; -- /* UNEQ and LTGT do not have a representation. */ -- case UNEQ: /* Fall through. */ -- case LTGT: /* Fall through. */ -- default: gcc_unreachable (); -- } -- -+ if (!TARGET_MAVERICK) -+ { -+ switch (comp_code) -+ { -+ case GE: return ARM_GE; -+ case GT: return ARM_GT; -+ case LE: return ARM_LS; -+ case LT: return ARM_MI; -+ case NE: return ARM_NE; -+ case EQ: return ARM_EQ; -+ case ORDERED: return ARM_VC; -+ case UNORDERED: return ARM_VS; -+ case UNLT: return ARM_LT; -+ case UNLE: return ARM_LE; -+ case UNGT: return ARM_HI; -+ case UNGE: return ARM_PL; -+ /* UNEQ and LTGT do not have a representation. */ -+ case UNEQ: /* Fall through. */ -+ case LTGT: /* Fall through. */ -+ default: gcc_unreachable (); -+ } -+ } -+ else -+ { -+ /* CIRRUS */ -+ switch (comp_code) -+ { -+#if 1 -+ case GT: return ARM_VS; -+ case LE: return ARM_LE; -+ case LT: return ARM_LT; -+ case NE: return ARM_NE; -+ case EQ: return ARM_EQ; -+ case UNLE: return ARM_VC; -+ case UNGT: return ARM_GT; -+ case UNGE: return ARM_GE; -+ case UNEQ: return ARM_PL; -+ case LTGT: return ARM_MI; -+ /* These do not have a representation. */ -+ case GE: /* Fall through. -UNGE wrong atm */ -+ case UNLT: /* Fall through. -LT wrong atm */ -+ case ORDERED: /* Fall through. -AL wrong atm */ -+ case UNORDERED: /* Fall through. -AL wrong atm */ -+#endif -+ default: gcc_unreachable (); -+ } -+ } - case CC_SWPmode: - switch (comp_code) - { -diff -urN gcc-4.1.2/gcc/config/arm/arm.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.md ---- gcc-4.1.2/gcc/config/arm/arm.md 2007-05-31 12:39:48.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-29 15:17:18.000000000 +1000 -@@ -6952,10 +6952,11 @@ - "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" - ) - -+;broken on cirrus - (define_expand "bge" - [(set (pc) - (if_then_else (ge (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM" -+ "TARGET_ARM" ;; && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) - "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" -@@ -6988,6 +6989,7 @@ - "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" - ) - -+; broken on cirrus? - (define_expand "bgeu" - [(set (pc) - (if_then_else (geu (match_dup 1) (const_int 0)) -@@ -7031,14 +7033,15 @@ - (if_then_else (ungt (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);" - ) - --(define_expand "bunlt" -+; broken for cirrus -+(define_expand "bunlt" - [(set (pc) - (if_then_else (unlt (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);" -@@ -7049,7 +7052,7 @@ - (if_then_else (unge (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);" - ) - -@@ -7058,7 +7061,7 @@ - (if_then_else (unle (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);" - ) - -@@ -7069,7 +7072,7 @@ - (if_then_else (uneq (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);" - ) - -@@ -7078,7 +7081,7 @@ - (if_then_else (ltgt (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);" - ) - -@@ -7086,7 +7089,7 @@ - ;; Patterns to match conditional branch insns. - ;; - --; Special pattern to match UNEQ. -+; Special pattern to match UNEQ for FPA and VFP. - (define_insn "*arm_buneq" - [(set (pc) - (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) -@@ -7102,7 +7105,7 @@ - (set_attr "length" "8")] - ) - --; Special pattern to match LTGT. -+; Special pattern to match LTGT for FPA and VFP. - (define_insn "*arm_bltgt" - [(set (pc) - (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) -@@ -7118,6 +7121,38 @@ - (set_attr "length" "8")] - ) - -+; Special pattern to match GE for MAVERICK. -+(define_insn "*arm_bge" -+ [(set (pc) -+ (if_then_else (ge (match_operand:CCFP 1 "cc_register" "") (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "* -+ gcc_assert (!arm_ccfsm_state); -+ -+ return \"beq\\t%l0\;bvs\\t%l0\"; -+ " -+ [(set_attr "conds" "jump_clob") -+ (set_attr "length" "8")] -+) -+ -+; Special pattern to match UNLT for MAVERICK - UGLY since we need to test for Z=0 && V=0. -+(define_insn "*arm_bunlt" -+ [(set (pc) -+ (if_then_else (unlt (match_operand:CCFP 1 "cc_register" "") (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "* -+ gcc_assert (!arm_ccfsm_state); -+ -+ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; -+ " -+ [(set_attr "conds" "jump_clob") -+ (set_attr "length" "12")] -+) -+ - (define_insn "*arm_cond_branch" - [(set (pc) - (if_then_else (match_operator 1 "arm_comparison_operator" -@@ -7137,7 +7172,7 @@ - (set_attr "type" "branch")] - ) - --; Special pattern to match reversed UNEQ. -+; Special pattern to match reversed UNEQ for FPA and VFP. - (define_insn "*arm_buneq_reversed" - [(set (pc) - (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) -@@ -7153,7 +7188,7 @@ - (set_attr "length" "8")] - ) - --; Special pattern to match reversed LTGT. -+; Special pattern to match reversed LTGT for FPA and VFP. - (define_insn "*arm_bltgt_reversed" - [(set (pc) - (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) -@@ -7169,6 +7204,39 @@ - (set_attr "length" "8")] - ) - -+; Special pattern to match reversed GE for MAVERICK - UGLY since we need to tst for Z=0 && N=0. -+(define_insn "*arm_bge_reversed" -+ [(set (pc) -+ (if_then_else (ge (match_operand:CCFP 1 "cc_register" "") (const_int 0)) -+ (pc) -+ (label_ref (match_operand 0 "" ""))))] -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "* -+ gcc_assert (!arm_ccfsm_state); -+ -+ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; -+ " -+ [(set_attr "conds" "jump_clob") -+ (set_attr "length" "12")] -+) -+ -+; Special pattern to match reversed UNLT for MAVERICK. -+(define_insn "*arm_bunlt_reversed" -+ [(set (pc) -+ (if_then_else (unlt (match_operand:CCFP 1 "cc_register" "") (const_int 0)) -+ (pc) -+ (label_ref (match_operand 0 "" ""))))] -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "* -+ gcc_assert (!arm_ccfsm_state); -+ -+ return \"beq\\t%l0\;bvs\\t%l0\"; -+ " -+ [(set_attr "conds" "jump_clob") -+ (set_attr "length" "8")] -+) -+ -+ - (define_insn "*arm_cond_branch_reversed" - [(set (pc) - (if_then_else (match_operator 1 "arm_comparison_operator" -@@ -7220,8 +7288,9 @@ - "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" - ) - -+;; broken for cirrus - definitely - (define_expand "sge" - [(set (match_operand:SI 0 "s_register_operand" "") - (ge:SI (match_dup 1) (const_int 0)))] -- "TARGET_ARM" -+ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" -@@ -7227,6 +7296,14 @@ - "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" - ) - -+;;; DO NOT add patterns for SGE these can not be represented with MAVERICK -+; (define_expand "sge" -+; [(set (match_operand:SI 0 "s_register_operand" "") -+; (ge:SI (match_dup 1) (const_int 0)))] -+; "TARGET_ARM && (TARGET_MAVERICK)" -+; "gcc_unreachable ();" -+; ) -+ - (define_expand "slt" - [(set (match_operand:SI 0 "s_register_operand" "") - (lt:SI (match_dup 1) (const_int 0)))] -@@ -7248,6 +7325,7 @@ - "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" - ) - -+;; broken for cirrus - maybe - (define_expand "sgeu" - [(set (match_operand:SI 0 "s_register_operand" "") - (geu:SI (match_dup 1) (const_int 0)))] -@@ -7255,6 +7333,14 @@ - "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);" - ) - -+;;; DO NOT add patterns for SGEU these may not be represented with MAVERICK? -+; (define_expand "sgeu" -+; [(set (match_operand:SI 0 "s_register_operand" "") -+; (ge:SI (match_dup 1) (const_int 0)))] -+; "TARGET_ARM && (TARGET_MAVERICK)" -+; "gcc_unreachable ();" -+; ) -+ - (define_expand "sltu" - [(set (match_operand:SI 0 "s_register_operand" "") - (ltu:SI (match_dup 1) (const_int 0)))] -@@ -7281,7 +7367,7 @@ - (define_expand "sungt" - [(set (match_operand:SI 0 "s_register_operand" "") - (ungt:SI (match_dup 1) (const_int 0)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, - arm_compare_op1);" - ) -@@ -7289,23 +7375,32 @@ - (define_expand "sunge" - [(set (match_operand:SI 0 "s_register_operand" "") - (unge:SI (match_dup 1) (const_int 0)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, - arm_compare_op1);" - ) - -+; broken for cirrus - (define_expand "sunlt" - [(set (match_operand:SI 0 "s_register_operand" "") - (unlt:SI (match_dup 1) (const_int 0)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" - "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, - arm_compare_op1);" - ) - -+;;; DO NOT add patterns for SUNLT these can't be represented with MAVERICK -+; (define_expand "sunlt" -+; [(set (match_operand:SI 0 "s_register_operand" "") -+; (unlt:SI (match_dup 1) (const_int 0)))] -+; "TARGET_ARM && (TARGET_MAVERICK)" -+; "gcc_unreachable ();" -+; ) -+ - (define_expand "sunle" - [(set (match_operand:SI 0 "s_register_operand" "") - (unle:SI (match_dup 1) (const_int 0)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, - arm_compare_op1);" - ) -@@ -7371,7 +7466,7 @@ - enum rtx_code code = GET_CODE (operands[1]); - rtx ccreg; - -- if (code == UNEQ || code == LTGT) -+ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) - FAIL; - - ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); -@@ -7390,7 +7485,8 @@ - enum rtx_code code = GET_CODE (operands[1]); - rtx ccreg; - -- if (code == UNEQ || code == LTGT) -+ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) -+ - FAIL; - - /* When compiling for SOFT_FLOAT, ensure both arms are in registers. -@@ -7409,13 +7505,13 @@ - (if_then_else:DF (match_operand 1 "arm_comparison_operator" "") - (match_operand:DF 2 "s_register_operand" "") - (match_operand:DF 3 "arm_float_add_operand" "")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - " - { - enum rtx_code code = GET_CODE (operands[1]); - rtx ccreg; - -- if (code == UNEQ || code == LTGT) -+ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code==GE || code == UNLT || code == ORDERED || code == UNORDERED))) - FAIL; - - ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-compare.patch-z-eq b/recipes/gcc/gcc-4.2.4/arm-crunch-compare.patch-z-eq deleted file mode 100644 index bc40411be4..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-compare.patch-z-eq +++ /dev/null @@ -1,400 +0,0 @@ -diff -urN gcc-4.1.2/gcc/config/arm/arm.c ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.c ---- gcc-4.1.2/gcc/config/arm/arm.c 2007-05-31 12:39:48.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-29 17:19:38.000000000 +1000 -@@ -11427,26 +11427,53 @@ - /* These encodings assume that AC=1 in the FPA system control - byte. This allows us to handle all cases except UNEQ and - LTGT. */ -- switch (comp_code) -- { -- case GE: return ARM_GE; -- case GT: return ARM_GT; -- case LE: return ARM_LS; -- case LT: return ARM_MI; -- case NE: return ARM_NE; -- case EQ: return ARM_EQ; -- case ORDERED: return ARM_VC; -- case UNORDERED: return ARM_VS; -- case UNLT: return ARM_LT; -- case UNLE: return ARM_LE; -- case UNGT: return ARM_HI; -- case UNGE: return ARM_PL; -- /* UNEQ and LTGT do not have a representation. */ -- case UNEQ: /* Fall through. */ -- case LTGT: /* Fall through. */ -- default: gcc_unreachable (); -- } -- -+ if (!TARGET_MAVERICK) -+ { -+ switch (comp_code) -+ { -+ case GE: return ARM_GE; -+ case GT: return ARM_GT; -+ case LE: return ARM_LS; -+ case LT: return ARM_MI; -+ case NE: return ARM_NE; -+ case EQ: return ARM_EQ; -+ case ORDERED: return ARM_VC; -+ case UNORDERED: return ARM_VS; -+ case UNLT: return ARM_LT; -+ case UNLE: return ARM_LE; -+ case UNGT: return ARM_HI; -+ case UNGE: return ARM_PL; -+ /* UNEQ and LTGT do not have a representation. */ -+ case UNEQ: /* Fall through. */ -+ case LTGT: /* Fall through. */ -+ default: gcc_unreachable (); -+ } -+ } -+ else -+ { -+ /* CIRRUS */ -+ switch (comp_code) -+ { -+#if 1 -+ case GT: return ARM_VS; -+ case LE: return ARM_LE; -+ case LT: return ARM_LT; -+ case NE: return ARM_NE; -+ case EQ: return ARM_EQ; -+ case UNLE: return ARM_VC; -+ case UNGT: return ARM_GT; -+ case UNGE: return ARM_GE; -+ case UNEQ: return ARM_PL; -+ case LTGT: return ARM_MI; -+ /* These do not have a representation. */ -+ case GE: /* Fall through. -UNGE wrong atm */ -+ case UNLT: /* Fall through. -LT wrong atm */ -+ case ORDERED: /* Fall through. -AL wrong atm */ -+ case UNORDERED: /* Fall through. -AL wrong atm */ -+#endif -+ default: gcc_unreachable (); -+ } -+ } - case CC_SWPmode: - switch (comp_code) - { -diff -urN gcc-4.1.2/gcc/config/arm/arm.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.md ---- gcc-4.1.2/gcc/config/arm/arm.md 2007-05-31 12:39:48.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-29 15:17:18.000000000 +1000 -@@ -6952,10 +6952,11 @@ - "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" - ) - -+;broken on cirrus - (define_expand "bge" - [(set (pc) - (if_then_else (ge (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM" -+ "TARGET_ARM" - "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" -@@ -6988,6 +6989,7 @@ - "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" - ) - -+; broken on cirrus? - (define_expand "bgeu" - [(set (pc) - (if_then_else (geu (match_dup 1) (const_int 0)) -@@ -7031,14 +7033,15 @@ - (if_then_else (ungt (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);" - ) - --(define_expand "bunlt" -+; broken for cirrus -+(define_expand "bunlt" - [(set (pc) - (if_then_else (unlt (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);" -@@ -7049,7 +7052,7 @@ - (if_then_else (unge (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);" - ) - -@@ -7058,7 +7061,7 @@ - (if_then_else (unle (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);" - ) - -@@ -7069,7 +7072,7 @@ - (if_then_else (uneq (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK - "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);" - ) - -@@ -7078,7 +7081,7 @@ - (if_then_else (ltgt (match_dup 1) (const_int 0)) - (label_ref (match_operand 0 "" "")) - (pc)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK - "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);" - ) - -@@ -7086,7 +7089,7 @@ - ;; Patterns to match conditional branch insns. - ;; - --; Special pattern to match UNEQ. -+; Special pattern to match UNEQ for FPA and VFP. - (define_insn "*arm_buneq" - [(set (pc) - (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) -@@ -7102,7 +7105,7 @@ - (set_attr "length" "8")] - ) - --; Special pattern to match LTGT. -+; Special pattern to match LTGT for FPA and VFP. - (define_insn "*arm_bltgt" - [(set (pc) - (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) -@@ -7118,6 +7121,38 @@ - (set_attr "length" "8")] - ) - -+; Special pattern to match GE for MAVERICK. -+(define_insn "*arm_bge" -+ [(set (pc) -+ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "TARGET_ARM && (TARGET_MAVERICK)" -+ "* -+ gcc_assert (!arm_ccfsm_state); -+ -+ return \"beq\\t%l0\;bvs\\t%l0\"; -+ " -+ [(set_attr "conds" "jump_clob") -+ (set_attr "length" "8")] -+) -+ -+; Special pattern to match UNLT for MAVERICK. -+(define_insn "*arm_bunlt" -+ [(set (pc) -+ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0)) -+ (label_ref (match_operand 0 "" "")) -+ (pc)))] -+ "TARGET_ARM && (TARGET_MAVERICK)" -+ "* -+ gcc_assert (!arm_ccfsm_state); -+ -+ return \"bne\\t%l0\;bvc\\t%l0\"; -+ " -+ [(set_attr "conds" "jump_clob") -+ (set_attr "length" "8")] -+) -+ - (define_insn "*arm_cond_branch" - [(set (pc) - (if_then_else (match_operator 1 "arm_comparison_operator" -@@ -7137,7 +7172,7 @@ - (set_attr "type" "branch")] - ) - --; Special pattern to match reversed UNEQ. -+; Special pattern to match reversed UNEQ for FPA and VFP. - (define_insn "*arm_buneq_reversed" - [(set (pc) - (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) -@@ -7153,7 +7188,7 @@ - (set_attr "length" "8")] - ) - --; Special pattern to match reversed LTGT. -+; Special pattern to match reversed LTGT for FPA and VFP. - (define_insn "*arm_bltgt_reversed" - [(set (pc) - (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) -@@ -7169,6 +7204,39 @@ - (set_attr "length" "8")] - ) - -+; Special pattern to match reversed GE for MAVERICK. -+(define_insn "*arm_bge_reversed" -+ [(set (pc) -+ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0)) -+ (pc) -+ (label_ref (match_operand 0 "" ""))))] -+ "TARGET_ARM && (TARGET_MAVERICK)" -+ "* -+ gcc_assert (!arm_ccfsm_state); -+ -+ return \"bne\\t%l0\;bvc\\t%l0\"; -+ " -+ [(set_attr "conds" "jump_clob") -+ (set_attr "length" "8")] -+) -+ -+; Special pattern to match reversed UNLT for MAVERICK. -+(define_insn "*arm_bunlt_reversed" -+ [(set (pc) -+ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0)) -+ (pc) -+ (label_ref (match_operand 0 "" ""))))] -+ "TARGET_ARM && (TARGET_MAVERICK)" -+ "* -+ gcc_assert (!arm_ccfsm_state); -+ -+ return \"beq\\t%l0\;bvs\\t%l0\"; -+ " -+ [(set_attr "conds" "jump_clob") -+ (set_attr "length" "8")] -+) -+ -+ - (define_insn "*arm_cond_branch_reversed" - [(set (pc) - (if_then_else (match_operator 1 "arm_comparison_operator" -@@ -7220,8 +7288,9 @@ - "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" - ) - -+;; broken for cirrus - definitely - (define_expand "sge" - [(set (match_operand:SI 0 "s_register_operand" "") - (ge:SI (match_dup 1) (const_int 0)))] -- "TARGET_ARM" -+ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" -@@ -7227,6 +7296,14 @@ - "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" - ) - -+;;; DO NOT add patterns for SGE these can not be represented with MAVERICK -+; (define_expand "sge" -+; [(set (match_operand:SI 0 "s_register_operand" "") -+; (ge:SI (match_dup 1) (const_int 0)))] -+; "TARGET_ARM && (TARGET_MAVERICK)" -+; "gcc_unreachable ();" -+; ) -+ - (define_expand "slt" - [(set (match_operand:SI 0 "s_register_operand" "") - (lt:SI (match_dup 1) (const_int 0)))] -@@ -7248,6 +7325,7 @@ - "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" - ) - -+;; broken for cirrus - maybe - (define_expand "sgeu" - [(set (match_operand:SI 0 "s_register_operand" "") - (geu:SI (match_dup 1) (const_int 0)))] -@@ -7255,6 +7333,14 @@ - "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);" - ) - -+;;; DO NOT add patterns for SGEU these may not be represented with MAVERICK? -+; (define_expand "sgeu" -+; [(set (match_operand:SI 0 "s_register_operand" "") -+; (ge:SI (match_dup 1) (const_int 0)))] -+; "TARGET_ARM && (TARGET_MAVERICK)" -+; "gcc_unreachable ();" -+; ) -+ - (define_expand "sltu" - [(set (match_operand:SI 0 "s_register_operand" "") - (ltu:SI (match_dup 1) (const_int 0)))] -@@ -7281,7 +7367,7 @@ - (define_expand "sungt" - [(set (match_operand:SI 0 "s_register_operand" "") - (ungt:SI (match_dup 1) (const_int 0)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, - arm_compare_op1);" - ) -@@ -7289,23 +7375,32 @@ - (define_expand "sunge" - [(set (match_operand:SI 0 "s_register_operand" "") - (unge:SI (match_dup 1) (const_int 0)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, - arm_compare_op1);" - ) - -+; broken for cirrus - (define_expand "sunlt" - [(set (match_operand:SI 0 "s_register_operand" "") - (unlt:SI (match_dup 1) (const_int 0)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" - "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, - arm_compare_op1);" - ) - -+;;; DO NOT add patterns for SUNLT these can't be represented with MAVERICK -+; (define_expand "sunlt" -+; [(set (match_operand:SI 0 "s_register_operand" "") -+; (unlt:SI (match_dup 1) (const_int 0)))] -+; "TARGET_ARM && (TARGET_MAVERICK)" -+; "gcc_unreachable ();" -+; ) -+ - (define_expand "sunle" - [(set (match_operand:SI 0 "s_register_operand" "") - (unle:SI (match_dup 1) (const_int 0)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, - arm_compare_op1);" - ) -@@ -7371,7 +7466,7 @@ - enum rtx_code code = GET_CODE (operands[1]); - rtx ccreg; - -- if (code == UNEQ || code == LTGT) -+ if (code == UNEQ || code == LTGT || code == GE || code == UNLT || code == ORDERED || code == UNORDERED) - FAIL; - - ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); -@@ -7390,7 +7485,8 @@ - enum rtx_code code = GET_CODE (operands[1]); - rtx ccreg; - -- if (code == UNEQ || code == LTGT) -+ if (code == UNEQ || code == LTGT || code == GE || code == UNLT || code == ORDERED || code == UNORDERED) -+ - FAIL; - - /* When compiling for SOFT_FLOAT, ensure both arms are in registers. -@@ -7409,13 +7505,13 @@ - (if_then_else:DF (match_operand 1 "arm_comparison_operator" "") - (match_operand:DF 2 "s_register_operand" "") - (match_operand:DF 3 "arm_float_add_operand" "")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - " - { - enum rtx_code code = GET_CODE (operands[1]); - rtx ccreg; - -- if (code == UNEQ || code == LTGT) -+ if (code == UNEQ || code == LTGT || code == GE || code == UNLT || code == ORDERED || code == UNORDERED) - FAIL; - - ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-dominance.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-dominance.patch deleted file mode 100644 index 517ca8d80e..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-dominance.patch +++ /dev/null @@ -1,12 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/arm.c-original 2007-06-13 11:50:10.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.c 2007-06-13 11:50:56.000000000 +1000 -@@ -6556,6 +6556,9 @@ - enum rtx_code cond1, cond2; - int swapped = 0; - -+ if (TARGET_MAVERICK) // Simple hack for MAVERICK -+ return CCmode; -+ - /* Currently we will probably get the wrong result if the individual - comparisons are not simple. This also ensures that it is safe to - reverse a comparison if necessary. */ diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-eabi-ieee754-div.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-eabi-ieee754-div.patch deleted file mode 100644 index 940f4a65ae..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-eabi-ieee754-div.patch +++ /dev/null @@ -1,139 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/ieee754-df-original.S 2007-06-25 10:22:06.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/ieee754-df.S 2007-06-25 10:27:17.000000000 +1000 -@@ -717,6 +717,10 @@ - cmn r4, #(53 + 1) - movle xl, #0 - bicle xh, xh, #0x7fffffff -+#ifdef __MAVERICK__ -+ cfmvdlr mvd0, xl -+ cfmvdhr mvd0, xh -+#endif - RETLDM "r4, r5, r6" le - - @ Find out proper shift value. -@@ -738,6 +742,10 @@ - adc xh, r2, xh, lsr r4 - orrs lr, lr, r3, lsl #1 - biceq xl, xl, r3, lsr #31 -+#ifdef __MAVERICK__ -+ cfmvdlr mvd0, xl -+ cfmvdhr mvd0, xh -+#endif - RETLDM "r4, r5, r6" - - @ shift result right of 21 to 31 bits, or left 11 to 1 bits after -@@ -752,6 +760,10 @@ - adc xh, xh, #0 - orrs lr, lr, r3, lsl #1 - biceq xl, xl, r3, lsr #31 -+#ifdef __MAVERICK__ -+ cfmvdlr mvd0, xl -+ cfmvdhr mvd0, xh -+#endif - RETLDM "r4, r5, r6" - - @ Shift value right of 32 to 64 bits, or 0 to 32 bits after a switch -@@ -766,6 +778,10 @@ - add xl, xl, r3, lsr #31 - orrs lr, lr, r3, lsl #1 - biceq xl, xl, r3, lsr #31 -+#ifdef __MAVERICK__ -+ cfmvdlr mvd0, xl -+ cfmvdhr mvd0, xh -+#endif - RETLDM "r4, r5, r6" - - @ One or both arguments are denormalized. -@@ -808,6 +824,10 @@ - eor xh, xh, yh - bic xh, xh, #0x7fffffff - mov xl, #0 -+#ifdef __MAVERICK__ -+ cfmvdlr mvd0, xl -+ cfmvdhr mvd0, xh -+#endif - RETLDM "r4, r5, r6" - - 1: @ One or both args are INF or NAN. -@@ -837,12 +857,20 @@ - orr xh, xh, #0x7f000000 - orr xh, xh, #0x00f00000 - mov xl, #0 -+#ifdef __MAVERICK__ -+ cfmvdlr mvd0, xl -+ cfmvdhr mvd0, xh -+#endif - RETLDM "r4, r5, r6" - - @ Return a quiet NAN. - LSYM(Lml_n): - orr xh, xh, #0x7f000000 - orr xh, xh, #0x00f80000 -+#ifdef __MAVERICK__ -+ cfmvdlr mvd0, xl -+ cfmvdhr mvd0, xh -+#endif - RETLDM "r4, r5, r6" - - FUNC_END aeabi_dmul ---- gcc-4.1.2/gcc/config/arm/ieee754-sf-original.S 2007-06-25 10:18:52.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/ieee754-sf.S 2007-06-25 10:40:25.000000000 +1000 -@@ -518,6 +518,9 @@ - @ Check if denormalized result is possible, otherwise return signed 0. - cmn r2, #(24 + 1) - bicle r0, r0, #0x7fffffff -+#ifdef __MAVERICK__ -+ cfmvsr mvf0, r0 -+#endif - RETc(le) - - @ Shift value right, round, etc. -@@ -530,6 +533,9 @@ - adc r0, r0, #0 - orrs r3, r3, ip, lsl #1 - biceq r0, r0, ip, lsr #31 -+#ifdef __MAVERICK__ -+ cfmvsr mvf0, r0 -+#endif - RET - - @ One or both arguments are denormalized. -@@ -567,6 +573,9 @@ - LSYM(Lml_z): - eor r0, r0, r1 - bic r0, r0, #0x7fffffff -+#ifdef __MAVERICK__ -+ cfmvsr mvf0, r0 -+#endif - RET - - 1: @ One or both args are INF or NAN. -@@ -595,12 +604,18 @@ - and r0, r0, #0x80000000 - orr r0, r0, #0x7f000000 - orr r0, r0, #0x00800000 -+#ifdef __MAVERICK__ -+ cfmvsr mvf0, r0 -+#endif - RET - - @ Return a quiet NAN. - LSYM(Lml_n): - orr r0, r0, #0x7f000000 - orr r0, r0, #0x00c00000 -+#ifdef __MAVERICK__ -+ cfmvsr mvf0, r0 -+#endif - RET - - FUNC_END aeabi_fmul -@@ -677,6 +692,9 @@ - adds r2, r2, #127 - rsbgts r3, r2, #255 - orrgt r0, r0, r2, lsl #23 -+#ifdef __MAVERICK__ -+ cfmvsr mvf0, r0 -+#endif - RETc(gt) - - orr r0, r0, #0x00800000 diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-eabi-ieee754.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-eabi-ieee754.patch deleted file mode 100644 index e4929fa20e..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-eabi-ieee754.patch +++ /dev/null @@ -1,100 +0,0 @@ ---- ../gcc-cross-4.1.2-r4-unpatched/gcc-4.1.2/gcc/config/arm/ieee754-df.S 2007-06-07 13:06:52.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/ieee754-df.S 2007-06-07 13:15:49.000000000 +1000 -@@ -42,8 +42,9 @@ - - - @ For FPA, float words are always big-endian. -+@ For MAVERICK, float words are always little-endian. - @ For VFP, floats words follow the memory system mode. --#if defined(__VFP_FP__) && !defined(__ARMEB__) -+#if ((defined(__VFP_FP__) && !defined(__ARMEB__)) || defined(__MAVERICK__)) - #define xl r0 - #define xh r1 - #define yl r2 -@@ -451,8 +452,13 @@ - - orrs r2, r0, r1 - #if !defined (__VFP_FP__) && !defined(__SOFTFP__) -+#if defined (__FPA_FP__) - mvfeqd f0, #0.0 - #endif -+#if defined (__MAVERICK__) -+ cfstrd mvd0, #0.0 -+#endif -+#endif - RETc(eq) - - #if !defined (__VFP_FP__) && !defined(__SOFTFP__) -@@ -473,8 +479,13 @@ - - orrs r2, r0, r1 - #if !defined (__VFP_FP__) && !defined(__SOFTFP__) -+#if defined (__FPA_FP__) - mvfeqd f0, #0.0 - #endif -+#if defined (__MAVERICK__) -+ cfstrd mvd0, #0.0 -+#endif -+#endif - RETc(eq) - - #if !defined (__VFP_FP__) && !defined(__SOFTFP__) -@@ -526,8 +537,14 @@ - @ Legacy code expects the result to be returned in f0. Copy it - @ there as well. - LSYM(f0_ret): -+#if defined (__FPA_FP__) - stmfd sp!, {r0, r1} - ldfd f0, [sp], #8 -+#endif -+#if defined (__MAVERICK__) -+ cfmvdlr mvd0, xl -+ cfmvdhr mvd0, xh -+#endif - RETLDM - - #endif ---- ../gcc-cross-4.1.2-r4-unpatched/gcc-4.1.2/gcc/config/arm/ieee754-sf.S 2007-06-07 13:06:52.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/ieee754-sf.S 2007-06-07 13:21:43.000000000 +1000 -@@ -302,8 +302,13 @@ - - orrs r2, r0, r1 - #if !defined (__VFP_FP__) && !defined(__SOFTFP__) -+#if defined (__FPA_FP__) - mvfeqs f0, #0.0 - #endif -+#if defined (__MAVERICK__) -+ cfmvsr mvf0, #0.0 -+#endif -+#endif - RETc(eq) - - mov r3, #0 -@@ -314,8 +319,13 @@ - - orrs r2, r0, r1 - #if !defined (__VFP_FP__) && !defined(__SOFTFP__) -+#if defined (__FPA_FP__) - mvfeqs f0, #0.0 - #endif -+#if defined (__MAVERICK__) -+ cfmvsr mvf0, #0.0 -+#endif -+#endif - RETc(eq) - - ands r3, ah, #0x80000000 @ sign bit in r3 -@@ -387,8 +397,13 @@ - #if !defined (__VFP_FP__) && !defined(__SOFTFP__) - - LSYM(f0_ret): -+#if defined (__FPA_FP__) - str r0, [sp, #-4]! - ldfs f0, [sp], #4 -+#endif -+#if defined (__MAVERICK__) -+ cfmvsr mvf0, r0 -+#endif - RETLDM - - #endif diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-eabi.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-eabi.patch deleted file mode 100644 index f8992ed499..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-eabi.patch +++ /dev/null @@ -1,64 +0,0 @@ ---- /home/hwilliams/original/gcc-4.1.2/gcc/config/arm/t-linux-eabi 2005-10-10 11:04:31.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/t-linux-eabi 2007-05-15 13:53:05.000000000 +1000 -@@ -1,11 +1,21 @@ - # These functions are included in shared libraries. - TARGET_LIBGCC2_CFLAGS = -fPIC -+TARGET_LIBGCC2_CFLAGS += -mcpu=ep9312 -mfpu=maverick -+LIBGCC2_DEBUG_CFLAGS = -g0 - - # We do not build a Thumb multilib for Linux because the definition of - # CLEAR_INSN_CACHE in linux-gas.h does not work in Thumb mode. - MULTILIB_OPTIONS = - MULTILIB_DIRNAMES = - -+LIB1ASMSRC = arm/lib1funcs.asm -+LIB1ASMFUNCS += _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx \ -+ _negdf2 _addsubdf3 _muldivdf3 _cmpdf2 _unorddf2 _fixdfsi _fixunsdfsi \ -+ _truncdfsf2 _negsf2 _addsubsf3 _muldivsf3 _cmpsf2 _unordsf2 \ -+ _fixsfsi _fixunssfsi -+ -+CRTSTUFF_T_CFLAGS += -mcpu=ep9312 -mfpu=maverick -+ - # Use a version of div0 which raises SIGFPE. - LIB1ASMFUNCS := $(filter-out _dvmd_tls,$(LIB1ASMFUNCS)) _dvmd_lnx - -diff -ruN arm/elf.h gcc-3.4.3/gcc/config/arm/elf.h ---- ../gcc-4.1.2-orig/gcc/config/arm/elf.h 2004-02-24 16:25:22.000000000 +0200 -+++ gcc-4.1.2/gcc/config/arm/elf.h 2005-02-10 00:31:28.000000000 +0200 -@@ -46,7 +46,7 @@ - - #ifndef SUBTARGET_ASM_FLOAT_SPEC - #define SUBTARGET_ASM_FLOAT_SPEC "\ --%{mapcs-float:-mfloat}" -+%{mapcs-float:-mfloat} %{msoft-float:-mfpu=softfpa} %{mcpu=ep9312:-mfpu=maverick}" - #endif - - #ifndef ASM_SPEC -diff -ruN t-linux gcc-4.1.2/gcc/config/arm/t-linux ---- t-linux 2007-05-09 16:32:28.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/t-linux 2007-05-25 11:02:17.000000000 +1000 -@@ -1,19 +1,22 @@ - # Just for these, we omit the frame pointer since it makes such a big - # difference. It is then pointless adding debugging. - TARGET_LIBGCC2_CFLAGS = -fomit-frame-pointer -fPIC -+TARGET_LIBGCC2_CFLAGS += -mcpu=ep9312 -mfpu=maverick -mfloat-abi=softfp -D__MAVERICK__ - LIBGCC2_DEBUG_CFLAGS = -g0 - - LIB1ASMSRC = arm/lib1funcs.asm - LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx \ - _negdf2 _addsubdf3 _muldivdf3 _cmpdf2 _unorddf2 _fixdfsi _fixunsdfsi \ - _truncdfsf2 _negsf2 _addsubsf3 _muldivsf3 _cmpsf2 _unordsf2 \ -- _call_via_rX \ -- _fixsfsi _fixunssfsi _floatdidf _floatdisf -+ _fixsfsi _fixunssfsi - - # MULTILIB_OPTIONS = mhard-float/msoft-float - # MULTILIB_DIRNAMES = hard-float soft-float - - # EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o - -+# EXTRA_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o -+CRTSTUFF_T_CFLAGS += -mcpu=ep9312 -mfpu=maverick -mfloat-abi=softfp -D__MAVERICK__ -+ - # LIBGCC = stmp-multilib - # INSTALL_LIBGCC = install-multilib diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-floatsi-disable-single.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-floatsi-disable-single.patch deleted file mode 100644 index cdd52244a6..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-floatsi-disable-single.patch +++ /dev/null @@ -1,38 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-25 12:12:39.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-25 12:16:13.000000000 +1000 -@@ -301,13 +301,14 @@ - ) - - ;; Convert Cirrus-SI to Cirrus-SF -+; appears to be buggy - (define_insn "cirrus_floatsisf2" - [(set (match_operand:SF 0 "cirrus_fp_register" "=v") - (float:SF (match_operand:SI 1 "s_register_operand" "r"))) - (clobber (match_scratch:DF 2 "=v"))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2" - [(set_attr "length" "8") - (set_attr "cirrus" "move")] - ) - ---- gcc-4.1.2/gcc/config/arm/arm.md-cfcvt 2007-06-25 12:16:53.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-25 12:18:20.000000000 +1000 -@@ -3125,14 +3125,15 @@ - - ;; Fixed <--> Floating conversion insns - -+;; Maverick Crunch floatsisf2 is buggy - see cirrus.md - (define_expand "floatsisf2" - [(set (match_operand:SF 0 "s_register_operand" "") - (float:SF (match_operand:SI 1 "s_register_operand" "")))] -- "TARGET_ARM && TARGET_HARD_FLOAT" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" - " -- if (TARGET_MAVERICK) -+ if (TARGET_MAVERICK && 0) - { - emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1])); - DONE; - } - ") diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-floatsi-disable.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-floatsi-disable.patch deleted file mode 100644 index aa54ec3e04..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-floatsi-disable.patch +++ /dev/null @@ -1,61 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-25 12:12:39.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-25 12:16:13.000000000 +1000 -@@ -301,21 +301,23 @@ - ) - - ;; Convert Cirrus-SI to Cirrus-SF -+; appears to be buggy - (define_insn "cirrus_floatsisf2" - [(set (match_operand:SF 0 "cirrus_fp_register" "=v") - (float:SF (match_operand:SI 1 "s_register_operand" "r"))) - (clobber (match_scratch:DF 2 "=v"))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2" - [(set_attr "length" "8") - (set_attr "cirrus" "move")] - ) - -+;appears to be buggy - (define_insn "cirrus_floatsidf2" - [(set (match_operand:DF 0 "cirrus_fp_register" "=v") - (float:DF (match_operand:SI 1 "s_register_operand" "r"))) - (clobber (match_scratch:DF 2 "=v"))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2" - [(set_attr "length" "8") - (set_attr "cirrus" "move")] ---- gcc-4.1.2/gcc/config/arm/arm.md-cfcvt 2007-06-25 12:16:53.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-25 12:18:20.000000000 +1000 -@@ -3125,24 +3125,26 @@ - - ;; Fixed <--> Floating conversion insns - -+;; Maverick Crunch floatsisf2 is buggy - see cirrus.md - (define_expand "floatsisf2" - [(set (match_operand:SF 0 "s_register_operand" "") - (float:SF (match_operand:SI 1 "s_register_operand" "")))] -- "TARGET_ARM && TARGET_HARD_FLOAT" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" - " -- if (TARGET_MAVERICK) -+ if (TARGET_MAVERICK && 0) - { - emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1])); - DONE; - } - ") - -+;; Maverick Crunch floatsidf2 is buggy - see cirrus.md - (define_expand "floatsidf2" - [(set (match_operand:DF 0 "s_register_operand" "") - (float:DF (match_operand:SI 1 "s_register_operand" "")))] -- "TARGET_ARM && TARGET_HARD_FLOAT" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" - " -- if (TARGET_MAVERICK) -+ if (TARGET_MAVERICK && 0) - { - emit_insn (gen_cirrus_floatsidf2 (operands[0], operands[1])); - DONE; diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-floatunsidf.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-floatunsidf.patch deleted file mode 100644 index 2fe2254db9..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-floatunsidf.patch +++ /dev/null @@ -1,37 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/ieee754-df-original.S 2007-06-25 14:05:35.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/ieee754-df.S 2007-06-25 14:08:03.000000000 +1000 -@@ -382,6 +382,8 @@ - FUNC_END aeabi_dadd - FUNC_END adddf3 - -+#ifndef __MAVERICK__ /* THIS IS A BAD HACK */ -+ - ARM_FUNC_START floatunsidf - ARM_FUNC_ALIAS aeabi_ui2d floatunsidf - -@@ -401,8 +403,14 @@ - FUNC_END aeabi_ui2d - FUNC_END floatunsidf - -+#endif -+ - ARM_FUNC_START floatsidf - ARM_FUNC_ALIAS aeabi_i2d floatsidf -+#ifdef __MAVERICK__ /* THIS IS A BAD HACK */ -+ARM_FUNC_ALIAS floatunsidf floatsidf -+ARM_FUNC_ALIAS aeabi_ui2d floatsidf -+#endif - - teq r0, #0 - moveq r1, #0 -@@ -418,6 +426,10 @@ - mov xh, #0 - b LSYM(Lad_l) - -+#ifdef __MAVERICK__ /* THIS IS A BAD HACK */ -+ FUNC_END aeabi_ui2d floatsidf -+ FUNC_END floatunsidf floatsidf -+#endif - FUNC_END aeabi_i2d - FUNC_END floatsidf - diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-fp_consts.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-fp_consts.patch deleted file mode 100644 index 5f289bbebe..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-fp_consts.patch +++ /dev/null @@ -1,13 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/arm.c-original 2007-06-12 16:17:14.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.c 2007-06-12 16:17:28.000000000 +1000 -@@ -5218,7 +5218,9 @@ - int i; - REAL_VALUE_TYPE r; - -+ if (TARGET_MAVERICK) -+ fp_consts_inited = 0; -- if (TARGET_VFP) -+ else if (TARGET_VFP) - fp_consts_inited = 1; - else - fp_consts_inited = 8; diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-neg.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-neg.patch deleted file mode 100644 index f14ae0190e..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-neg.patch +++ /dev/null @@ -1,30 +0,0 @@ -WARNING: adding this patch causes copysign1.c and mzero3.c to fail... -diff -urN gcc-4.1.2/gcc/config/arm/arm.md-original gcc-4.1.2/gcc/config/arm/arm.md ---- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-12 12:48:14.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-12 12:49:53.000000000 +1000 -@@ -2985,14 +2985,14 @@ - (define_expand "negsf2" - [(set (match_operand:SF 0 "s_register_operand" "") - (neg:SF (match_operand:SF 1 "s_register_operand" "")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "" - ) - - (define_expand "negdf2" - [(set (match_operand:DF 0 "s_register_operand" "") - (neg:DF (match_operand:DF 1 "s_register_operand" "")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "") - - ;; abssi2 doesn't really clobber the condition codes if a different register -@@ -4097,7 +4097,7 @@ - [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m") - (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))] - "TARGET_ARM -- && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP)) -+ && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP || TARGET_MAVERICK)) - && !TARGET_IWMMXT" - "* - switch (which_alternative) diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-neg2.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-neg2.patch deleted file mode 100644 index 4fd91f3215..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-neg2.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/cirrus.md-original 2007-06-12 17:01:24.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-12 17:03:26.000000000 +1000 -@@ -255,18 +256,20 @@ - [(set_attr "cirrus" "normal")] - ) - -+;; appears to be buggy: neg 0 != -0 - (define_insn "*cirrus_negsf2" - [(set (match_operand:SF 0 "cirrus_fp_register" "=v") - (neg:SF (match_operand:SF 1 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfnegs%?\\t%V0, %V1" - [(set_attr "cirrus" "normal")] - ) - -+;; appears to be buggy: neg 0 != -0 - (define_insn "*cirrus_negdf2" - [(set (match_operand:DF 0 "cirrus_fp_register" "=v") - (neg:DF (match_operand:DF 1 "cirrus_fp_register" "v")))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cfnegd%?\\t%V0, %V1" - [(set_attr "cirrus" "normal")] - ) diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-offset.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-offset.patch deleted file mode 100644 index 3a40f0d224..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-offset.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/arm.c-original 2007-06-12 14:46:20.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.c 2007-06-12 14:48:06.000000000 +1000 -@@ -3460,7 +3460,7 @@ - - use_ldrd = (TARGET_LDRD - && (mode == DImode -- || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP)))); -+ || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_MAVERICK || TARGET_VFP)))); - - if (code == POST_INC || code == PRE_DEC - || ((code == PRE_INC || code == POST_DEC) -@@ -3960,7 +3960,7 @@ - /* VFP addressing modes actually allow greater offsets, but for - now we just stick with the lowest common denominator. */ - if (mode == DImode -- || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode)) -+ || ((TARGET_SOFT_FLOAT || TARGET_MAVERICK || TARGET_VFP) && mode == DFmode)) - { - low_n = n & 0x0f; - n &= ~0x0f; diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-predicates.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-predicates.patch deleted file mode 100644 index 4841ff8178..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-predicates.patch +++ /dev/null @@ -1,20 +0,0 @@ -diff -urN gcc-4.1.2/gcc/config/arm/predicates.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/predicates.md ---- gcc-4.1.2/gcc/config/arm/predicates.md 2005-09-11 17:38:02.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/predicates.md 2007-05-30 12:15:54.000000000 +1000 -@@ -171,8 +171,14 @@ - (match_code "eq,ne")) - - ;; True for comparisons other than LTGT or UNEQ. -+(define_special_predicate "arm_comparison_operator" -+; (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt")) ;; original - no LTGT or UNEQ -+; (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltgt,ltu,unordered,ordered,uneq,unlt,unle,unge,ungt")) ;; everything? -+;; True for comparisons other than GE, GEU, UNLT, unordered or ordered. - Cirrus Version - must include ge? --(define_special_predicate "arm_comparison_operator" -+;(define_special_predicate "arm_comparison_operator" -- (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt")) -+(match_code "eq,ne,le,lt,ge,geu,gt,gtu,leu,ltgt,ltu,uneq,unle,unge,ungt")) ;; bad codes removed? -+;(match_code "eq,ne,le,lt,gt,gtu,leu,ltgt,ltu,uneq,unle,unge,ungt")) ;; bad codes removed + ge / geu removed -+ - - (define_special_predicate "minmax_operator" - (and (match_code "smin,smax,umin,umax") diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-predicates2.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-predicates2.patch deleted file mode 100644 index 3e01158fe1..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-predicates2.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/predicates.md-original 2007-06-13 12:25:35.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/predicates.md 2007-06-13 12:25:42.000000000 +1000 -@@ -206,7 +206,6 @@ - || mode == CC_DEQmode - || mode == CC_DLEmode - || mode == CC_DLTmode -- || mode == CC_DGEmode - || mode == CC_DGTmode - || mode == CC_DLEUmode - || mode == CC_DLTUmode diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-predicates3.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-predicates3.patch deleted file mode 100644 index 99e1e6c88c..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-predicates3.patch +++ /dev/null @@ -1,116 +0,0 @@ -diff -urN ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/arm.md gcc-4.1.2/gcc/config/arm/arm.md ---- ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/arm.md 2007-06-14 11:50:53.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-14 11:43:17.000000000 +1000 -@@ -7488,6 +7488,22 @@ - arm_compare_op1);" - ) - -+;(define_expand "suneq" -+; [(set (match_operand:SI 0 "s_register_operand" "") -+; (uneq:SI (match_dup 1) (const_int 0)))] -+; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" -+; "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, -+; arm_compare_op1);" -+;) -+ -+;(define_expand "sltgt" -+; [(set (match_operand:SI 0 "s_register_operand" "") -+; (ltgt:SI (match_dup 1) (const_int 0)))] -+; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" -+; "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, -+; arm_compare_op1);" -+;) -+ - ;;; DO NOT add patterns for SUNEQ or SLTGT, these can't be represented with - ;;; simple ARM instructions. - ; -@@ -10284,13 +10284,73 @@ - "TARGET_ARM && arm_arch5e" - "pld\\t%a0") - -+;; Special predication pattern for Maverick Crunch floating-point -+ -+(define_cond_exec -+ [(match_operator 0 "maverick_comparison_operator" -+ [(match_operand:CCFP 1 "cc_register" "") -+ (const_int 0)])] -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "" -+) -+ -+;; Special predication pattern for Maverick Crunch - !CCFP -+ -+(define_cond_exec -+ [(match_operator 0 "arm_comparison_operator" -+ [(match_operand:CC_NOOV 1 "cc_register" "") -+ (const_int 0)])] -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "" -+) -+ -+(define_cond_exec -+ [(match_operator 0 "arm_comparison_operator" -+ [(match_operand:CC_Z 1 "cc_register" "") -+ (const_int 0)])] -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "" -+) -+ -+(define_cond_exec -+ [(match_operator 0 "arm_comparison_operator" -+ [(match_operand:CC_SWP 1 "cc_register" "") -+ (const_int 0)])] -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "" -+) -+ -+(define_cond_exec -+ [(match_operator 0 "arm_comparison_operator" -+ [(match_operand:CC_C 1 "cc_register" "") -+ (const_int 0)])] -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "" -+) -+ -+(define_cond_exec -+ [(match_operator 0 "arm_comparison_operator" -+ [(match_operand:CC_N 1 "cc_register" "") -+ (const_int 0)])] -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "" -+) -+ -+(define_cond_exec -+ [(match_operator 0 "arm_comparison_operator" -+ [(match_operand:CC 1 "cc_register" "") -+ (const_int 0)])] -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "" -+) -+ - ;; General predication pattern - - (define_cond_exec - [(match_operator 0 "arm_comparison_operator" - [(match_operand 1 "cc_register" "") - (const_int 0)])] -- "TARGET_ARM" -+ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" - "" - ) - -diff -urN ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/predicates.md gcc-4.1.2/gcc/config/arm/predicates.md ---- ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/predicates.md 2005-09-11 17:38:02.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/predicates.md 2007-06-14 11:46:13.000000000 +1000 -@@ -172,7 +172,11 @@ - - ;; True for comparisons other than LTGT or UNEQ. - (define_special_predicate "arm_comparison_operator" - (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt")) -+ -+;; True for comparisons other than GE, GEU, UNLT, UNORDERED or ORDERED - TODO add LTGT and UNEQ - needs extra support elsewhere -+(define_special_predicate "maverick_comparison_operator" -+(match_code "eq,ne,le,lt,gt,gtu,leu,ltu,unle,unge,ungt")) - - (define_special_predicate "minmax_operator" - (and (match_code "smin,smax,umin,umax") diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-saveregs.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-saveregs.patch deleted file mode 100644 index 531ae86610..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-saveregs.patch +++ /dev/null @@ -1,153 +0,0 @@ -diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.c gcc-4.1.2/gcc/config/arm/arm.c ---- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.c 2007-05-09 16:32:29.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-15 09:39:41.000000000 +1000 -@@ -426,7 +435,7 @@ - #define FL_STRONG (1 << 8) /* StrongARM */ - #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ - #define FL_XSCALE (1 << 10) /* XScale */ --#define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */ -+#define FL_CIRRUS (1 << 11) /* Cirrus Crunch coprocessor. */ - #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds - media instructions. */ - #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */ -@@ -490,7 +499,7 @@ - /* Nonzero if this chip is a StrongARM. */ - int arm_tune_strongarm = 0; - --/* Nonzero if this chip is a Cirrus variant. */ -+/* Nonzero if this chip supports Cirrus Crunch coprocessor. */ - int arm_arch_cirrus = 0; - - /* Nonzero if this chip supports Intel Wireless MMX technology. */ -@@ -1184,7 +1193,8 @@ - else - */ - if (arm_arch_cirrus) -- arm_fpu_arch = FPUTYPE_MAVERICK; -+ /* Cirrus crunch coprocessor still requires soft-float division. */ -+ arm_fpu_arch = FPUTYPE_MAVERICK; - else - arm_fpu_arch = FPUTYPE_FPA_EMU2; - #endif -@@ -1567,6 +1577,9 @@ - if (regs_ever_live[regno] && !call_used_regs[regno]) - return 0; - -+ if (TARGET_MAVERICK) -+ return 0; -+ - if (TARGET_REALLY_IWMMXT) - for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++) - if (regs_ever_live[regno] && ! call_used_regs [regno]) -@@ -9775,7 +9886,19 @@ - /* This variable is for the Virtual Frame Pointer, not VFP regs. */ - int vfp_offset = offsets->frame; - -- if (arm_fpu_arch == FPUTYPE_FPA_EMU2) -+ if (arm_fpu_arch == FPUTYPE_MAVERICK) -+ { -+ for (reg = LAST_CIRRUS_FP_REGNUM; reg >= FIRST_CIRRUS_FP_REGNUM; reg--) -+ if (regs_ever_live[reg] && !call_used_regs[reg]) -+ { -+ floats_offset += 8; /* more problems - futaris? */ -+ /* if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1) */ -+ asm_fprintf (f, "\tnop\n"); -+ asm_fprintf (f, "\tcfldrd\tmvd%d, [%r, #-%d]\n", -+ reg - FIRST_CIRRUS_FP_REGNUM, FP_REGNUM, floats_offset - vfp_offset); -+ } -+ } -+ else if (arm_fpu_arch == FPUTYPE_FPA_EMU2) - { - for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) - if (regs_ever_live[reg] && !call_used_regs[reg]) -@@ -9924,7 +10047,18 @@ - output_add_immediate (operands); - } - -- if (arm_fpu_arch == FPUTYPE_FPA_EMU2) -+ if (arm_fpu_arch == FPUTYPE_MAVERICK) -+ { /* order changed - futaris */ -+ for (reg = FIRST_CIRRUS_FP_REGNUM; reg <= LAST_CIRRUS_FP_REGNUM; reg++) -+ if (regs_ever_live[reg] && !call_used_regs[reg]) -+ { -+ /* if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1) */ -+ asm_fprintf (f, "\tnop\n"); -+ asm_fprintf (f, "\tcfldrd\tmvd%u, [%r], #8\n", -+ reg - FIRST_CIRRUS_FP_REGNUM, SP_REGNUM); -+ } /* reg problems - futaris */ -+ } -+ else if (arm_fpu_arch == FPUTYPE_FPA_EMU2) - { - for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) - if (regs_ever_live[reg] && !call_used_regs[reg]) -@@ -10429,9 +10563,19 @@ - if (! IS_VOLATILE (func_type)) - { -+ /* Space for saved MAVERICK registers. */ -+ if (arm_fpu_arch == FPUTYPE_MAVERICK) -+ { -+ for (regno = FIRST_CIRRUS_FP_REGNUM; regno <= LAST_CIRRUS_FP_REGNUM; regno++) -+ if (regs_ever_live[regno] && !call_used_regs[regno]) -+ saved += 8; // 8 in 3.4.3 patch - futaris; -+ } -+ else - /* Space for saved FPA registers. */ -+ { - for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) - if (regs_ever_live[regno] && ! call_used_regs[regno]) - saved += 12; -+ } - - /* Space for saved VFP registers. */ - if (TARGET_HARD_FLOAT && TARGET_VFP) -@@ -10739,7 +10882,19 @@ - - /* Save any floating point call-saved registers used by this - function. */ -- if (arm_fpu_arch == FPUTYPE_FPA_EMU2) -+ if (arm_fpu_arch == FPUTYPE_MAVERICK) -+ { -+ for (reg = LAST_CIRRUS_FP_REGNUM; reg >= FIRST_CIRRUS_FP_REGNUM; reg--) -+ if (regs_ever_live[reg] && !call_used_regs[reg]) -+ { -+ insn = gen_rtx_PRE_DEC (DFmode, stack_pointer_rtx); /* think these causes problems */ -+ insn = gen_rtx_MEM (DFmode, insn); -+ insn = emit_insn (gen_rtx_SET (VOIDmode, insn, -+ gen_rtx_REG (DFmode, reg))); -+ RTX_FRAME_RELATED_P (insn) = 1; saved_regs += 8; /* added by futaris */ -+ } -+ } -+ else if (arm_fpu_arch == FPUTYPE_FPA_EMU2) - { - for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) - if (regs_ever_live[reg] && !call_used_regs[reg]) -@@ -15179,6 +15331,9 @@ - if (IS_FPA_REGNUM (regno)) - return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM; - -+ if (IS_CIRRUS_REGNUM (regno)) -+ return 28 + regno - FIRST_CIRRUS_FP_REGNUM; -+ - if (IS_VFP_REGNUM (regno)) - return 64 + regno - FIRST_VFP_REGNUM; - ---- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-28 15:42:36.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-28 15:42:48.000000000 +1000 -@@ -9800,7 +9800,7 @@ - return arm_output_epilogue (next_nonnote_insn (insn)); - " - ;; Length is absolute worst case -- [(set_attr "length" "44") -+ [(set_attr "length" "108") - (set_attr "type" "block") - ;; We don't clobber the conditions, but the potential length of this - ;; operation is sufficient to make conditionalizing the sequence -@@ -9818,7 +9818,7 @@ - return thumb_unexpanded_epilogue (); - " - ; Length is absolute worst case -- [(set_attr "length" "44") -+ [(set_attr "length" "108") - (set_attr "type" "block") - ;; We don't clobber the conditions, but the potential length of this - ;; operation is sufficient to make conditionalizing the sequence diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-scc.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-scc.patch deleted file mode 100644 index d1330f2543..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-scc.patch +++ /dev/null @@ -1,38 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-13 12:38:06.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-13 12:40:07.000000000 +1000 -@@ -7375,7 +7375,7 @@ - (define_expand "sge" - [(set (match_operand:SI 0 "s_register_operand" "") - (ge:SI (match_dup 1) (const_int 0)))] -- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" -+ "TARGET_ARM" - "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" - ) - -@@ -7434,7 +7434,7 @@ - (define_expand "sunordered" - [(set (match_operand:SI 0 "s_register_operand" "") - (unordered:SI (match_dup 1) (const_int 0)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0, - arm_compare_op1);" - ) -@@ -7442,7 +7442,7 @@ - (define_expand "sordered" - [(set (match_operand:SI 0 "s_register_operand" "") - (ordered:SI (match_dup 1) (const_int 0)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0, - arm_compare_op1);" - ) -@@ -7467,7 +7467,7 @@ - (define_expand "sunlt" - [(set (match_operand:SI 0 "s_register_operand" "") - (unlt:SI (match_dup 1) (const_int 0)))] -- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" - "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, - arm_compare_op1);" - ) diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-truncsi-disable-new.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-truncsi-disable-new.patch deleted file mode 100644 index 6dea43fa7c..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-truncsi-disable-new.patch +++ /dev/null @@ -1,33 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-25 12:46:22.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-25 12:46:41.000000000 +1000 -@@ -337,13 +337,14 @@ - "cfcvt64d%?\\t%V0, %V1" - [(set_attr "cirrus" "normal")]) - -+; appears to be buggy - (define_insn "cirrus_truncsfsi2" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register" "v")))) - (clobber (match_scratch:DF 2 "=v"))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" - [(set_attr "length" "8") - (set_attr "cirrus" "normal")] - ) - ---- gcc-4.1.2/gcc/config/arm/arm.md-cfcvt 2007-06-25 12:46:56.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-25 12:48:08.000000000 +1000 -@@ -3151,10 +3151,11 @@ - } - ") - -+; appears to be buggy for MAVERICK - (define_expand "fix_truncsfsi2" - [(set (match_operand:SI 0 "s_register_operand" "") - (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))] -- "TARGET_ARM && TARGET_HARD_FLOAT" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" - " - if (TARGET_MAVERICK) - { diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-truncsi-disable.patch b/recipes/gcc/gcc-4.2.4/arm-crunch-truncsi-disable.patch deleted file mode 100644 index a5d791a0a4..0000000000 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-truncsi-disable.patch +++ /dev/null @@ -1,56 +0,0 @@ ---- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-25 12:46:22.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-25 12:46:41.000000000 +1000 -@@ -337,21 +337,23 @@ - "cfcvt64d%?\\t%V0, %V1" - [(set_attr "cirrus" "normal")]) - -+; appears to be buggy - (define_insn "cirrus_truncsfsi2" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register" "v")))) - (clobber (match_scratch:DF 2 "=v"))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" - [(set_attr "length" "8") - (set_attr "cirrus" "normal")] - ) - -+; appears to be buggy - (define_insn "cirrus_truncdfsi2" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (fix:SI (fix:DF (match_operand:DF 1 "cirrus_fp_register" "v")))) - (clobber (match_scratch:DF 2 "=v"))] -- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" -+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" - "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" - [(set_attr "length" "8") - (set_attr "cirrus" "normal")] ---- gcc-4.1.2/gcc/config/arm/arm.md-cfcvt 2007-06-25 12:46:56.000000000 +1000 -+++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-25 12:48:08.000000000 +1000 -@@ -3151,10 +3151,11 @@ - } - ") - -+; appears to be buggy for MAVERICK - (define_expand "fix_truncsfsi2" - [(set (match_operand:SI 0 "s_register_operand" "") - (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))] -- "TARGET_ARM && TARGET_HARD_FLOAT" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" - " - if (TARGET_MAVERICK) - { -@@ -3167,10 +3168,11 @@ - } - ") - -+; appears to be buggy for MAVERICK - (define_expand "fix_truncdfsi2" - [(set (match_operand:SI 0 "s_register_operand" "") - (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))] -- "TARGET_ARM && TARGET_HARD_FLOAT" -+ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" - " - if (TARGET_MAVERICK) - { diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/README b/recipes/gcc/gcc-4.2.4/ep93xx/README new file mode 100644 index 0000000000..a656a850cb --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/README @@ -0,0 +1,11 @@ +This is a set of patches for gcc-4.3 that fix code generation for the +Maverick Crunch FPU present in Cirrus Logic EP93xx devices. + +They are based on the patch ideas for OpenEmbedded that Hasjim Williams sent me +privately in April 2008, with my own reimplementation of the CCMAV mode and the +addition of a -mieee switch to fully respect denormalized values (with a 50% +speed penalty). + +See the comments at the top of each patch file for further details. + + Martin Guy <martinwguy@yahoo.it>, 21 November 2008 - 12 March 2009 diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/URL b/recipes/gcc/gcc-4.2.4/ep93xx/URL new file mode 100644 index 0000000000..6d962a4bc4 --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/URL @@ -0,0 +1 @@ +http://martinwguy.co.uk/martin/crunch/gcc-4.2.4-patches/ diff --git a/recipes/gcc/gcc-4.2.4/arm-crunch-20000320.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-20000320.patch index 3fb0da7670..d45295e286 100644 --- a/recipes/gcc/gcc-4.2.4/arm-crunch-20000320.patch +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-20000320.patch @@ -1,5 +1,9 @@ ---- gcc-4.1.2/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c.original 2007-06-07 16:33:44.000000000 +1000 -+++ gcc-4.1.2/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c 2007-06-07 16:34:05.000000000 +1000 +Fix one test in the testsuite to know about Maverick crunch word order + +Index: gcc-4.2.4/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c +=================================================================== +--- gcc-4.2.4.orig/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c 2003-02-03 10:15:15.000000000 +0000 ++++ gcc-4.2.4/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c 2009-08-09 15:43:45.000000000 +0100 @@ -49,7 +49,7 @@ exit (0); diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-arm_dbx_register_number.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-arm_dbx_register_number.patch new file mode 100644 index 0000000000..ec1b5fdfc0 --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-arm_dbx_register_number.patch @@ -0,0 +1,17 @@ +Include the Maverick Crunch registers in the GCC->DWARF2 register number +mapping. Without this, cc -g with maverick hardfloat fails. + +Index: gcc-4.2.4/gcc/config/arm/arm.c +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.c 2009-08-09 15:43:45.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.c 2009-08-09 15:45:06.000000000 +0100 +@@ -15330,6 +15330,9 @@ + if (IS_FPA_REGNUM (regno)) + return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM; + ++ if (IS_CIRRUS_REGNUM (regno)) ++ return 28 + regno - FIRST_CIRRUS_FP_REGNUM; ++ + if (IS_VFP_REGNUM (regno)) + return 64 + regno - FIRST_VFP_REGNUM; + diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-ccmav-mode.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-ccmav-mode.patch new file mode 100644 index 0000000000..47989b6d00 --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-ccmav-mode.patch @@ -0,0 +1,744 @@ +These modifications implement a new condition code mode CCMAV which is used +on floating point comparisons that were performed in the Maverick Crunch FPU. + +This is necessary because the Maverick sets the conditions codes differently +from the ARM/FPA/VFP. Since we do not use the Maverick's 32-bit int modes nor +its 64-bit comparison, these different conditions pertain to all floating point +comparisons when compiling for Maverick hardfloat. + + ARM/FPA/VFP - (cmp*): MaverickCrunch - (cfcmp*): + N Z C V N Z C V + A == B 0 1 1 0 A == B 0 1 0 0 + A < B 1 0 0 0 A < B 1 0 0 0 + A > B 0 0 1 0 A > B 1 0 0 1 + unord 0 0 1 1 unord 0 0 0 0 + +The new mode is set on floating point comparisons instead of the usual +CCFP and CCFPE, then acted upon when the conditional instruction flags +are output. + +Furthermore, the list of conditions that cannot be tested with a single +conditional test is different. On ARM/FPA/VFP it is UNEQ and LTGT while +on Maverick it is GE UNLT ORDERED and UNORDERED. +We handle this with a new predicate "maverick_comparison_operator" that omits +the comparisons that cannot be represented and we split the cond_exec pattern +into for CCMAV mode plus a separate rule for every non-Maverick CC mode. +This prevents generation of conditional instructions that cannot be represented. + +Although Maverick can also represent LTGT and UNEQ with a single test, we do not +include these since it would mean splitting every other rule that uses +"arm_comparison_operator" in a similar way for very little gain. + +A few other tests are added to prevent optimisations that would +generate these unrepresentable conditions. + +None of these changes affect code generation for ARM or for other FPUs. + +One missed optimisation: movsfcc and movdfcc have been +disabled for Maverick because we don't use the Maverick's instructions +conditionally to avoid hardware bugs. But a limited movsfcc and movdfcc +could be included when Maverick, that applies to all modes where the things +to be moved do not involve the Maverick registers, if such a thing is feasible +without the optimizer moving things into registers between the expand and the +instruction generation. + + Martin Guy <martinwguy@yahoo.it>, November 2008 + +Index: gcc-4.2.4/gcc/config/arm/arm-modes.def +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm-modes.def 2007-09-01 16:28:30.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm-modes.def 2009-08-09 15:43:46.000000000 +0100 +@@ -27,6 +27,7 @@ + + /* CCFPEmode should be used with floating inequalities, + CCFPmode should be used with floating equalities. ++ CCMAVmode should be used with comparisons performed in the Maverick FPU + CC_NOOVmode should be used with SImode integer equalities. + CC_Zmode should be used if only the Z flag is set correctly + CC_Nmode should be used if only the N (sign) flag is set correctly +@@ -37,6 +38,7 @@ + CC_MODE (CC_SWP); + CC_MODE (CCFP); + CC_MODE (CCFPE); ++CC_MODE (CCMAV); + CC_MODE (CC_DNE); + CC_MODE (CC_DEQ); + CC_MODE (CC_DLE); +Index: gcc-4.2.4/gcc/config/arm/arm.h +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.h 2009-08-09 15:43:45.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.h 2009-08-09 15:43:46.000000000 +0100 +@@ -2138,7 +2138,7 @@ + #define REVERSIBLE_CC_MODE(MODE) 1 + + #define REVERSE_CONDITION(CODE,MODE) \ +- (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ ++ (((MODE) == CCFPmode || (MODE) == CCFPEmode || (MODE) == CCMAVmode) \ + ? reverse_condition_maybe_unordered (code) \ + : reverse_condition (code)) + +Index: gcc-4.2.4/gcc/config/arm/predicates.md +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/predicates.md 2007-09-01 16:28:30.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/predicates.md 2009-08-09 15:43:46.000000000 +0100 +@@ -181,6 +181,16 @@ + (define_special_predicate "arm_comparison_operator" + (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt")) + ++;; Comparisons that can be predicated after a Maverick FP comparison, true for ++;; floating point comparisons other than GE, UNLT, UNORDERED or ORDERED ++;; ++;; Maverick can also match LTGT and UNEQ with a single condition ++;; but including these means duplicating every rule containing ++;; arm_comparison_operator including cond_branch and all the *cc rules. ++;; Extra speed when predicating ltgt and uneq is rare enough not to be worth it. ++(define_special_predicate "maverick_comparison_operator" ++(match_code "eq,ne,le,lt,gt,unle,unge,ungt")) ++ + (define_special_predicate "minmax_operator" + (and (match_code "smin,smax,umin,umax") + (match_test "mode == GET_MODE (op)"))) +Index: gcc-4.2.4/gcc/config/arm/arm.c +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.c 2009-08-09 15:43:46.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.c 2009-08-09 15:45:03.000000000 +0100 +@@ -1559,6 +1559,14 @@ + return 0; + } + ++ /* Optimisation of __builtin_inunordered at the end of a ++ * function would generate conditional return on (UN)ORDERED, which cannot ++ * be represented by a single condition code test on Maverick. ++ * Since we do not have access to the specific condition used, ++ * we just disable all conditional returns on Maverick. */ ++ if (iscond && TARGET_MAVERICK && TARGET_HARD_FLOAT) ++ return 0; ++ + /* If there are saved registers but the LR isn't saved, then we need + two instructions for the return. */ + if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM))) +@@ -6687,6 +6695,10 @@ + comparison, and CCFPE otherwise. */ + if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) + { ++ /* Comparisons performed in the Maverick FPU set the CCs their own way. */ ++ if (TARGET_HARD_FLOAT && TARGET_MAVERICK) ++ return CCMAVmode; ++ + switch (op) + { + case EQ: +@@ -6705,8 +6717,6 @@ + case LE: + case GT: + case GE: +- if (TARGET_HARD_FLOAT && TARGET_MAVERICK) +- return CCFPmode; + return CCFPEmode; + + default: +@@ -11580,6 +11590,29 @@ + default: gcc_unreachable (); + } + ++ case CCMAVmode: ++ /* Maverick cmp sets the condition codes differently from ARM/FPA/VFP */ ++ switch (comp_code) ++ { ++ case GT: return ARM_VS; ++ case LE: return ARM_LE; ++ case LT: return ARM_LT; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case UNLE: return ARM_VC; ++ case UNGT: return ARM_GT; ++ case UNGE: return ARM_GE; ++ case UNEQ: return ARM_PL; ++ case LTGT: return ARM_MI; ++ /* These cannot be represented by a single condition code. */ ++ case GE: /* Fall through */ ++ case UNLT:/* Fall through */ ++ case ORDERED:/* Fall through */ ++ case UNORDERED:/* Fall through */ ++ default: ++ gcc_unreachable (); ++ } ++ + case CC_SWPmode: + switch (comp_code) + { +Index: gcc-4.2.4/gcc/config/arm/arm.md +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.md 2009-08-09 15:43:46.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.md 2009-08-09 15:45:03.000000000 +0100 +@@ -250,7 +250,9 @@ + ; they are altered at all + ; + ; JUMP_CLOB is used when the condition cannot be represented by a single +-; instruction (UNEQ and LTGT). These cannot be predicated. ++; instruction. This applies to UNEQ and LTGT for ARM/FPA/VFP comparisons, ++; GE UNLT ORDERED and UNORDERED for Maverick comparisons. ++; These cannot be predicated. + ; + ; NOCOND means that the condition codes are neither altered nor affect the + ; output of this insn +@@ -6959,9 +6961,9 @@ + + ;; Cirrus SF compare instruction + (define_insn "*cirrus_cmpsf" +- [(set (reg:CCFP CC_REGNUM) +- (compare:CCFP (match_operand:SF 0 "cirrus_fp_register" "v") +- (match_operand:SF 1 "cirrus_fp_register" "v")))] ++ [(set (reg:CCMAV CC_REGNUM) ++ (compare:CCMAV (match_operand:SF 0 "cirrus_fp_register" "v") ++ (match_operand:SF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfcmps%?\\tr15, %V0, %V1" + [(set_attr "type" "farith") +@@ -6970,9 +6972,9 @@ + + ;; Cirrus DF compare instruction + (define_insn "*cirrus_cmpdf" +- [(set (reg:CCFP CC_REGNUM) +- (compare:CCFP (match_operand:DF 0 "cirrus_fp_register" "v") +- (match_operand:DF 1 "cirrus_fp_register" "v")))] ++ [(set (reg:CCMAV CC_REGNUM) ++ (compare:CCMAV (match_operand:DF 0 "cirrus_fp_register" "v") ++ (match_operand:DF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfcmpd%?\\tr15, %V0, %V1" + [(set_attr "type" "farith") +@@ -7109,12 +7111,18 @@ + "operands[1] = arm_gen_compare_reg (LTU, arm_compare_op0, arm_compare_op1);" + ) + ++;; Some of the following patterns may need two branch instructions, since ++;; there is no single instruction that will handle all cases. Specifically: ++;; ARM/FPA/VFP cannot test UNEQ and LTGT ++;; Maverick cannot test GE on floating point values, UNLT, ORDERED or UNORDERED. ++ + (define_expand "bunordered" + [(set (pc) + (if_then_else (unordered (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7124,7 +7132,8 @@ + (if_then_else (ordered (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7134,7 +7143,8 @@ + (if_then_else (ungt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7143,7 +7153,8 @@ + (if_then_else (unlt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7152,7 +7163,8 @@ + (if_then_else (unge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7161,18 +7173,18 @@ + (if_then_else (unle (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);" + ) + +-;; The following two patterns need two branch instructions, since there is +-;; no single instruction that will handle all cases. + (define_expand "buneq" + [(set (pc) + (if_then_else (uneq (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7181,7 +7193,8 @@ + (if_then_else (ltgt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7189,7 +7202,7 @@ + ;; Patterns to match conditional branch insns. + ;; + +-; Special pattern to match UNEQ. ++; Special pattern to match UNEQ for FPA and VFP. + (define_insn "*arm_buneq" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7205,7 +7218,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match LTGT. ++; Special pattern to match LTGT for FPA and VFP. + (define_insn "*arm_bltgt" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7221,6 +7234,101 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match floating point GE for Maverick. ++(define_insn "*cirrus_bge" ++ [(set (pc) ++ (if_then_else (ge (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++; Special pattern to match UNORDERED for Maverick. ++(define_insn "*cirrus_bunordered" ++ [(set (pc) ++ (if_then_else (unordered (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bmi\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ ++; Special pattern to match ORDERED for Maverick. ++(define_insn "*cirrus_bordered" ++ [(set (pc) ++ (if_then_else (ordered (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bmi\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++; Special pattern to match UNLT for Maverick. ++(define_insn "*cirrus_bunlt" ++ [(set (pc) ++ (if_then_else (unlt (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ ++; Special atterns to match UNEQ and LTGT for Maverick, to handle ++; the two cases not covered by generic *arm_cond_branch ++ ++(define_insn "*cirrus_buneq" ++ [(set (pc) ++ (if_then_else (uneq (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"bpl\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob")] ++) ++ ++(define_insn "*cirrus_bltgt" ++ [(set (pc) ++ (if_then_else (ltgt (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"bmi\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob")] ++) ++ + (define_insn "*arm_cond_branch" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7240,7 +7348,7 @@ + (set_attr "type" "branch")] + ) + +-; Special pattern to match reversed UNEQ. ++; Special pattern to match reversed UNEQ for FPA and VFP. + (define_insn "*arm_buneq_reversed" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7256,7 +7364,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match reversed LTGT. ++; Special pattern to match reversed LTGT for FPA and VFP. + (define_insn "*arm_bltgt_reversed" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7272,6 +7380,101 @@ + (set_attr "length" "8")] + ) + ++; Patterns to match reversed UNEQ and LTGT for Maverick, the two cases ++; not covered by generic "*arm_cond_branch_reversed" ++ ++(define_insn "*cirrus_buneq_reversed" ++ [(set (pc) ++ (if_then_else (uneq (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"bmi\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob")] ++) ++ ++(define_insn "*cirrus_bltgt_reversed" ++ [(set (pc) ++ (if_then_else (ltgt (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"bpl\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob")] ++) ++ ++; Special pattern to match reversed floating point GE for Maverick. ++(define_insn "*cirrus_bge_reversed" ++ [(set (pc) ++ (if_then_else (ge (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ ++; Special pattern to match reversed UNORDERED for Maverick. ++(define_insn "*cirrus_bunordered_reversed" ++ [(set (pc) ++ (if_then_else (unordered (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bmi\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++; Special pattern to match reversed ORDERED for Maverick. ++(define_insn "*cirrus_bordered_reversed" ++ [(set (pc) ++ (if_then_else (ordered (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bmi\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ ++; Special pattern to match reversed UNLT for Maverick. ++(define_insn "*cirrus_bunlt_reversed" ++ [(set (pc) ++ (if_then_else (unlt (match_operand:CCMAV 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ + (define_insn "*arm_cond_branch_reversed" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7323,11 +7526,16 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++; SGE can only be represented as a single condition code on ARM/VFP/FPA, ++; not with Maverick when the operands are floating point. + (define_expand "sge" + [(set (match_operand:SI 0 "s_register_operand" "") + (ge:SI (match_dup 1) (const_int 0)))] + "TARGET_ARM" +- "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" ++ "if (TARGET_HARD_FLOAT && TARGET_MAVERICK ++ && GET_MODE_CLASS (GET_MODE (arm_compare_op0)) == MODE_FLOAT) ++ FAIL; ++ operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" + ) + + (define_expand "slt" +@@ -7365,6 +7573,7 @@ + "operands[1] = arm_gen_compare_reg (LTU, arm_compare_op0, arm_compare_op1);" + ) + ++; SORDERED and SUNORDERED cannot be represented on Maverick + (define_expand "sunordered" + [(set (match_operand:SI 0 "s_register_operand" "") + (unordered:SI (match_dup 1) (const_int 0)))] +@@ -7384,7 +7593,8 @@ + (define_expand "sungt" + [(set (match_operand:SI 0 "s_register_operand" "") + (ungt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7392,11 +7602,13 @@ + (define_expand "sunge" + [(set (match_operand:SI 0 "s_register_operand" "") + (unge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, + arm_compare_op1);" + ) + ++; SUNLT cannot be represented on Maverick + (define_expand "sunlt" + [(set (match_operand:SI 0 "s_register_operand" "") + (unlt:SI (match_dup 1) (const_int 0)))] +@@ -7408,7 +7620,8 @@ + (define_expand "sunle" + [(set (match_operand:SI 0 "s_register_operand" "") + (unle:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7474,20 +7687,32 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) +- FAIL; ++ /* Reject comparisons not representable by a single condition code */ ++ if (TARGET_HARD_FLOAT && TARGET_MAVERICK ++ && GET_MODE_CLASS (GET_MODE (arm_compare_op0)) == MODE_FLOAT) ++ { ++ if (code == GE || code == UNLT || code == ORDERED || code == UNORDERED) ++ FAIL; ++ } ++ else ++ { ++ if (code == UNEQ || code == LTGT) ++ FAIL; ++ } + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); + operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); + }" + ) + ++; We do not use Maverick conditional FP instructions to avoid hardware bugs ++ + (define_expand "movsfcc" + [(set (match_operand:SF 0 "s_register_operand" "") + (if_then_else:SF (match_operand 1 "arm_comparison_operator" "") + (match_operand:SF 2 "s_register_operand" "") + (match_operand:SF 3 "nonmemory_operand" "")))] +- "TARGET_ARM" ++ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" + " + { + enum rtx_code code = GET_CODE (operands[1]); +@@ -9809,7 +10034,7 @@ + + operands[5] = gen_rtx_REG (mode, CC_REGNUM); + operands[6] = gen_rtx_COMPARE (mode, operands[2], operands[3]); +- if (mode == CCFPmode || mode == CCFPEmode) ++ if (mode == CCFPmode || mode == CCFPEmode || mode == CCMAVmode) + rc = reverse_condition_maybe_unordered (rc); + else + rc = reverse_condition (rc); +@@ -9860,7 +10085,7 @@ + + operands[6] = gen_rtx_REG (mode, CC_REGNUM); + operands[7] = gen_rtx_COMPARE (mode, operands[2], operands[3]); +- if (mode == CCFPmode || mode == CCFPEmode) ++ if (mode == CCFPmode || mode == CCFPEmode || mode == CCMAVmode) + rc = reverse_condition_maybe_unordered (rc); + else + rc = reverse_condition (rc); +@@ -9892,7 +10117,7 @@ + + operands[6] = gen_rtx_REG (mode, CC_REGNUM); + operands[7] = gen_rtx_COMPARE (mode, operands[2], operands[3]); +- if (mode == CCFPmode || mode == CCFPEmode) ++ if (mode == CCFPmode || mode == CCFPEmode || mode == CCMAVmode) + rc = reverse_condition_maybe_unordered (rc); + else + rc = reverse_condition (rc); +@@ -10208,13 +10433,75 @@ + "TARGET_ARM && arm_arch5e" + "pld\\t%a0") + ++;; Special predication patterns for Maverick Crunch floating-point ++;; which has a different set of predicable conditions after a floating ++;; point comparison. ++ ++(define_cond_exec ++ [(match_operator 0 "maverick_comparison_operator" ++ [(match_operand:CCMAV 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++;; Every else is the same as the general ARM pattern. ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_NOOV 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_Z 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_SWP 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_C 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_N 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ + ;; General predication pattern + + (define_cond_exec + [(match_operator 0 "arm_comparison_operator" + [(match_operand 1 "cc_register" "") + (const_int 0)])] +- "TARGET_ARM" ++ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" + "" + ) + diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-cfcpy-with-cfsh64.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-cfcpy-with-cfsh64.patch new file mode 100644 index 0000000000..78caac89b6 --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-cfcpy-with-cfsh64.patch @@ -0,0 +1,29 @@ +cfcpys and cfcpyd have hardware bugs which mean they truncate denormalized +values to zero and convert minus zero to plus zero. + +A 64-bit shift with a shift count of 0 copies them bitwise. + + Martin Guy <martinwguy@yahoo.it>, December 2008 + +Index: gcc-4.2.4/gcc/config/arm/cirrus.md +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/cirrus.md 2009-08-09 15:43:46.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/cirrus.md 2009-08-09 15:45:03.000000000 +0100 +@@ -485,7 +485,7 @@ + && (GET_CODE (operands[0]) != MEM + || register_operand (operands[1], SFmode))" + "@ +- cfcpys%?\\t%V0, %V1 ++ cfsh64%?\\t%Z0, %Z1, #0\\t%@ float + cfldrs%?\\t%V0, %1 + cfmvsr%?\\t%V0, %1 + cfmvrs%?\\t%0, %V1 +@@ -514,7 +514,7 @@ + case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\"; + case 2: return \"#\"; + case 3: case 4: return output_move_double (operands); +- case 5: return \"cfcpyd%?\\t%V0, %V1\"; ++ case 5: return \"cfsh64%?\\t%Z0, %Z1, #0\\t%@ double\"; + case 6: return \"cfldrd%?\\t%V0, %1\"; + case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\"; + case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\"; diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-cftruncd32-attr.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-cftruncd32-attr.patch new file mode 100644 index 0000000000..311c47d912 --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-cftruncd32-attr.patch @@ -0,0 +1,14 @@ +Index: gcc-4.2.4/gcc/config/arm/cirrus.md +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/cirrus.md 2009-08-09 15:43:47.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/cirrus.md 2009-08-09 15:44:52.000000000 +0100 +@@ -425,7 +425,8 @@ + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" + [(set_attr "type" "f_cvt") +- (set_attr "length" "8")] ++ (set_attr "length" "8") ++ (set_attr "cirrus" "normal")] + ) + + ; Cirrus hardware bugs: denormalized values on input are truncated to zero diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-cirrus-di-flag.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-cirrus-di-flag.patch new file mode 100644 index 0000000000..e336106a4f --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-cirrus-di-flag.patch @@ -0,0 +1,299 @@ +This patch disables all 64-bit integer operations of the MaverickCrunch unit +unless the new flag -mcirrus-di is supplied (as well as -mcpu-ep9312 +-mfpu=maverick -mfloat-abi=softfp). + +The 64-bit instructions (or their GCC support) are known to be buggy, as shown +for example by openssl-0.9.8g's testsuite: +In the unpacked openssl source directory: + $ ./config + $ vi Makefile + > /^CC= /s/$/-4.3-crunch/ + > /^CFLAG= /s/$/ -mcpu=ep9312 -mfpu=maverick -mfloat-abi=softfp -mcirrus-di/ + > :wq + $ make + $ make test +fails if either of the two files: */sha/sha512.c and */bn/bn_asm.c are compiled +with cirrus 64-bit support enabled. If you disable cfmul64, sha512.c works ok, +but I've disabled everything down to cfadd64, cfsub64 and 64-bit load and store +and bn_asm still fails, which suggests another hardware timing bug. + +Index: gcc-4.2.4/gcc/config/arm/arm.opt +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.opt 2009-08-09 16:08:54.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.opt 2009-08-09 16:08:55.000000000 +0100 +@@ -63,6 +63,10 @@ + Target Report Mask(CALLER_INTERWORKING) + Thumb: Assume function pointers may go to non-Thumb aware code + ++mcirrus-di ++Target Report Mask(CIRRUS_DI) ++Cirrus: Enable processing of 64-bit integers in the MaverickCrunch unit (buggy) ++ + mcpu= + Target RejectNegative Joined + Specify the name of the target CPU +Index: gcc-4.2.4/gcc/config/arm/arm.c +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.c 2009-08-09 16:08:54.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.c 2009-08-09 16:08:55.000000000 +0100 +@@ -12030,7 +12030,8 @@ + upper 32 bits. This causes gcc all sorts of grief. We can't + even split the registers into pairs because Cirrus SI values + get sign extended to 64bits-- aldyh. */ +- return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode); ++ return (GET_MODE_CLASS (mode) == MODE_FLOAT) ++ || (mode == DImode && TARGET_CIRRUS_DI); + + if (TARGET_HARD_FLOAT && TARGET_VFP + && IS_VFP_REGNUM (regno)) +Index: gcc-4.2.4/gcc/config/arm/arm.md +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.md 2009-08-09 16:08:51.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.md 2009-08-09 16:08:55.000000000 +0100 +@@ -356,7 +356,7 @@ + (clobber (reg:CC CC_REGNUM))])] + "TARGET_EITHER" + " +- if (TARGET_HARD_FLOAT && TARGET_MAVERICK) ++ if (TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI) + { + if (!cirrus_fp_register (operands[0], DImode)) + operands[0] = force_reg (DImode, operands[0]); +@@ -392,7 +392,7 @@ + (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0") + (match_operand:DI 2 "s_register_operand" "r, 0"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" ++ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI)" + "#" + "TARGET_ARM && reload_completed" + [(parallel [(set (reg:CC_C CC_REGNUM) +@@ -420,7 +420,7 @@ + (match_operand:SI 2 "s_register_operand" "r,r")) + (match_operand:DI 1 "s_register_operand" "r,0"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" ++ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI)" + "#" + "TARGET_ARM && reload_completed" + [(parallel [(set (reg:CC_C CC_REGNUM) +@@ -449,7 +449,7 @@ + (match_operand:SI 2 "s_register_operand" "r,r")) + (match_operand:DI 1 "s_register_operand" "r,0"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" ++ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI)" + "#" + "TARGET_ARM && reload_completed" + [(parallel [(set (reg:CC_C CC_REGNUM) +@@ -834,7 +834,7 @@ + (clobber (reg:CC CC_REGNUM))])] + "TARGET_EITHER" + " +- if (TARGET_HARD_FLOAT && TARGET_MAVERICK ++ if (TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI + && TARGET_ARM + && cirrus_fp_register (operands[0], DImode) + && cirrus_fp_register (operands[1], DImode)) +@@ -2659,7 +2659,8 @@ + values to iwmmxt regs and back. */ + FAIL; + } +- else if (!TARGET_REALLY_IWMMXT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)) ++ else if (!TARGET_REALLY_IWMMXT ++ && !(TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI)) + FAIL; + " + ) +@@ -4166,7 +4167,8 @@ + [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m") + (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))] + "TARGET_ARM +- && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP)) ++ && !(TARGET_HARD_FLOAT ++ && ((TARGET_MAVERICK && TARGET_CIRRUS_DI) || TARGET_VFP)) + && !TARGET_IWMMXT + && ( register_operand (operands[0], DImode) + || register_operand (operands[1], DImode))" +@@ -4286,7 +4288,7 @@ + [(set (match_operand:DI 0 "nonimmediate_operand" "=l,l,l,l,>,l, m,*r") + (match_operand:DI 1 "general_operand" "l, I,J,>,l,mi,l,*r"))] + "TARGET_THUMB +- && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) ++ && !(TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI) + && ( register_operand (operands[0], DImode) + || register_operand (operands[1], DImode))" + "* +Index: gcc-4.2.4/gcc/config/arm/cirrus.md +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/cirrus.md 2009-08-09 16:08:52.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/cirrus.md 2009-08-16 22:32:00.000000000 +0100 +@@ -85,7 +85,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (plus:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:DI 2 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "cfadd64%?\\t%V0, %V1, %V2" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -126,7 +126,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (minus:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:DI 2 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "cfsub64%?\\t%V0, %V1, %V2" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -176,7 +176,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (mult:DI (match_operand:DI 2 "cirrus_fp_register" "v") + (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "cfmul64%?\\t%V0, %V1, %V2" + [(set_attr "type" "fmul") + (set_attr "cirrus" "normal")] +@@ -230,7 +230,7 @@ + (define_insn "cirrus_ashl_const" + [(set (match_operand:SI 0 "cirrus_fp_register" "=v") + (ashift:SI (match_operand:SI 1 "cirrus_fp_register" "v") +- (match_operand:SI 2 "cirrus_shift_const" "")))] ++ (match_operand:SI 2 "const_cirrus_shift_operand" "")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfsh32%?\\t%V0, %V1, #%s2" + [(set_attr "type" "farith") +@@ -240,7 +240,7 @@ + (define_insn "cirrus_ashiftrt_const" + [(set (match_operand:SI 0 "cirrus_fp_register" "=v") + (ashiftrt:SI (match_operand:SI 1 "cirrus_fp_register" "v") +- (match_operand:SI 2 "cirrus_shift_const" "")))] ++ (match_operand:SI 2 "const_cirrus_shiftrt_operand" "")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfsh32%?\\t%V0, %V1, #-%s2" + [(set_attr "type" "farith") +@@ -261,7 +261,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "register_operand" "r")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "cfrshl64%?\\t%V1, %V0, %s2" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -270,8 +270,8 @@ + (define_insn "cirrus_ashldi_const" + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v") +- (match_operand:SI 2 "cirrus_shift_const" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ (match_operand:SI 2 "const_cirrus_shift_operand" "")))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "cfsh64%?\\t%V0, %V1, #%s2" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -280,8 +280,8 @@ + (define_insn "cirrus_ashiftrtdi_const" + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (ashiftrt:DI (match_operand:DI 1 "cirrus_fp_register" "v") +- (match_operand:SI 2 "cirrus_shift_const" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ (match_operand:SI 2 "const_cirrus_shiftrt_operand" "")))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "cfsh64%?\\t%V0, %V1, #-%s2" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -290,7 +290,7 @@ + (define_insn "*cirrus_absdi2" + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (abs:DI (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "cfabs64%?\\t%V0, %V1" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -301,7 +301,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (neg:DI (match_operand:DI 1 "cirrus_fp_register" "v"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "cfneg64%?\\t%V0, %V1" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -392,7 +392,7 @@ + (define_insn "floatdisf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "cfcvt64s%?\\t%V0, %V1" + [(set_attr "type" "f_cvt") + (set_attr "cirrus" "normal")] +@@ -401,7 +401,7 @@ + (define_insn "floatdidf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "cfcvt64d%?\\t%V0, %V1" + [(set_attr "type" "f_cvt") + (set_attr "cirrus" "normal")] +@@ -454,7 +454,7 @@ + (define_insn "*cirrus_arm_movdi" + [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v") + (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_CIRRUS_DI" + "* + { + switch (which_alternative) +Index: gcc-4.2.4/gcc/doc/invoke.texi +=================================================================== +--- gcc-4.2.4.orig/gcc/doc/invoke.texi 2009-08-09 16:08:54.000000000 +0100 ++++ gcc-4.2.4/gcc/doc/invoke.texi 2009-08-09 16:08:55.000000000 +0100 +@@ -417,6 +417,7 @@ + -msingle-pic-base -mno-single-pic-base @gol + -mpic-register=@var{reg} @gol + -mnop-fun-dllimport @gol ++-mirrus-di @gol + -mieee @gol + -mpoke-function-name @gol + -mthumb -marm @gol +@@ -7770,6 +7771,16 @@ + Specify the register to be used for PIC addressing. The default is R10 + unless stack-checking is enabled, when R9 is used. + ++@item -mcirrus-di ++When compiling for the Maverick FPU, enable handling of 64-bit integers ++in the FPU (add, subtract, multiply, arithmetic shifts and conversions). ++Normally they are disabled because some instruction sequences can give ++erroneous results. ++This option only has any effect if the ++@option{-mcpu=ep9312} @option{-mfpu=maverick} options have been used and is ++disabled by default. ++The default can be re-enabled by use of the @option{-mno-cirrus-di} switch. ++ + @item -mieee + When compiling for the Maverick FPU, disable the instructions that fail + to honor denormalized values. As these include floating point add, sub, +Index: gcc-4.2.4/gcc/config/arm/predicates.md +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/predicates.md 2009-08-16 22:27:01.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/predicates.md 2009-08-16 22:29:15.000000000 +0100 +@@ -460,8 +460,12 @@ + || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS)); + }) + +-(define_predicate "cirrus_shift_const" ++(define_predicate "const_cirrus_shift_operand" + (and (match_code "const_int") +- (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 64"))) ++ (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) <= 31"))) ++ ++(define_predicate "const_cirrus_shiftrt_operand" ++ (and (match_code "const_int") ++ (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) <= 32"))) + + diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-disable-cmpdi.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-disable-cmpdi.patch new file mode 100644 index 0000000000..b48a8cbba9 --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-disable-cmpdi.patch @@ -0,0 +1,30 @@ +Disable the Maverick's cmpdi instruction which cannot perform the simultaneous +signed/unsigned comparison expected by GCC. + +Index: gcc-4.2.4/gcc/config/arm/arm.md +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.md 2007-09-01 16:28:30.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.md 2009-08-09 15:45:18.000000000 +0100 +@@ -6981,10 +6981,12 @@ + ) + + ;; Cirrus DI compare instruction ++;; This is disabled and left go through ARM core registers, because currently ++;; Crunch coprocessor does only signed comparison. + (define_expand "cmpdi" + [(match_operand:DI 0 "cirrus_fp_register" "") + (match_operand:DI 1 "cirrus_fp_register" "")] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK & 0" + "{ + arm_compare_op0 = operands[0]; + arm_compare_op1 = operands[1]; +@@ -6995,7 +6997,7 @@ + [(set (reg:CC CC_REGNUM) + (compare:CC (match_operand:DI 0 "cirrus_fp_register" "v") + (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK & 0" + "cfcmp64%?\\tr15, %V0, %V1" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "compare")] diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-disable-floatsi.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-disable-floatsi.patch new file mode 100644 index 0000000000..7a966c3569 --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-disable-floatsi.patch @@ -0,0 +1,64 @@ +int->float instructions cfcvt32s and cfcvt32d do seem to work but if they are +enabled, the vorbis testsuite (file lib/vorbisenc.c) fail and lame to segfault +on nonstandard bit rate wav files such as 11050 bps (file libmp3lame/util.c). + +Until someone wants to figure out what the real problem is we just disable these +two insns because then everything seems to work. + +Index: gcc-4.2.4/gcc/config/arm/arm.md +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.md 2009-08-19 05:22:36.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.md 2009-09-07 23:56:05.000000000 +0100 +@@ -3190,10 +3190,14 @@ + + ;; Fixed <--> Floating conversion insns + ++; Maverick int->float conversion insns seem to work but tickle an optimization ++; bug in GCC 4.[123].* so we paper over it to get working code :-/ ++; It may be the same as http://gcc.gnu.org/bugzilla/show_bug.cgi?id=39501 ++ + (define_expand "floatsisf2" + [(set (match_operand:SF 0 "s_register_operand" "") + (float:SF (match_operand:SI 1 "s_register_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT" ++ "TARGET_ARM && TARGET_HARD_FLOAT && !TARGET_MAVERICK" + " + if (TARGET_MAVERICK) + { +@@ -3205,7 +3209,7 @@ + (define_expand "floatsidf2" + [(set (match_operand:DF 0 "s_register_operand" "") + (float:DF (match_operand:SI 1 "s_register_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT" ++ "TARGET_ARM && TARGET_HARD_FLOAT && !TARGET_MAVERICK" + " + if (TARGET_MAVERICK) + { +Index: gcc-4.2.4/gcc/config/arm/cirrus.md +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/cirrus.md 2009-08-19 04:47:30.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/cirrus.md 2009-09-07 23:50:17.000000000 +0100 +@@ -369,10 +369,13 @@ + ) + + ;; Convert Cirrus-SI to Cirrus-SF ++ ++; int->float conversions are disabled to avoid a GCC bug. See arm.md ++ + (define_insn "cirrus_floatsisf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (float:SF (match_operand:SI 1 "s_register_operand" "r")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfmv64lr%?\\t%Z0, %1\;cfcvt32s%?\\t%V0, %Y0" + [(set_attr "type" "f_cvt") + (set_attr "length" "8") +@@ -382,7 +385,7 @@ + (define_insn "cirrus_floatsidf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (float:DF (match_operand:SI 1 "s_register_operand" "r")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfmv64lr%?\\t%Z0, %1\;cfcvt32d%?\\t%V0, %Y0" + [(set_attr "type" "f_cvt") + (set_attr "length" "8") diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-eabi-ieee754-endian-littleword-littlebyte.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-eabi-ieee754-endian-littleword-littlebyte.patch new file mode 100644 index 0000000000..33b5a55eb9 --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-eabi-ieee754-endian-littleword-littlebyte.patch @@ -0,0 +1,17 @@ +Define Maverick floating point word order in libgcc's assemble support routines + +Index: gcc-4.2.4/gcc/config/arm/ieee754-df.S +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/ieee754-df.S 2007-01-09 10:11:53.000000000 +0000 ++++ gcc-4.2.4/gcc/config/arm/ieee754-df.S 2009-08-09 15:45:27.000000000 +0100 +@@ -42,8 +42,9 @@ + + + @ For FPA, float words are always big-endian. ++@ For MAVERICK, float words are always little-endian. + @ For VFP, floats words follow the memory system mode. +-#if defined(__VFP_FP__) && !defined(__ARMEB__) ++#if ((defined(__VFP_FP__) && !defined(__ARMEB__)) || defined(__MAVERICK__)) + #define xl r0 + #define xh r1 + #define yl r2 diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-eabi-mvf0-scratch-ieee754.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-eabi-mvf0-scratch-ieee754.patch new file mode 100644 index 0000000000..0a8f1845ec --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-eabi-mvf0-scratch-ieee754.patch @@ -0,0 +1,85 @@ +Don't try to copy results into an FPA register when compiling for Maverick + +Index: gcc-4.2.4/gcc/config/arm/ieee754-df.S +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/ieee754-df.S 2009-08-09 15:43:45.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/ieee754-df.S 2009-08-09 15:43:45.000000000 +0100 +@@ -451,12 +451,12 @@ + ARM_FUNC_ALIAS aeabi_ul2d floatundidf + + orrs r2, r0, r1 +-#if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if !defined (__VFP_FP__) && !defined (__MAVERICK__) && !defined(__SOFTFP__) + mvfeqd f0, #0.0 + #endif + RETc(eq) + +-#if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if !defined (__VFP_FP__) && !defined (__MAVERICK__) && !defined(__SOFTFP__) + @ For hard FPA code we want to return via the tail below so that + @ we can return the result in f0 as well as in r0/r1 for backwards + @ compatibility. +@@ -473,12 +473,12 @@ + ARM_FUNC_ALIAS aeabi_l2d floatdidf + + orrs r2, r0, r1 +-#if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if !defined (__VFP_FP__) && !defined (__MAVERICK__) && !defined(__SOFTFP__) + mvfeqd f0, #0.0 + #endif + RETc(eq) + +-#if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if !defined (__VFP_FP__) && !defined (__MAVERICK__) && !defined(__SOFTFP__) + @ For hard FPA code we want to return via the tail below so that + @ we can return the result in f0 as well as in r0/r1 for backwards + @ compatibility. +@@ -522,7 +522,7 @@ + add r4, r4, r2 + b LSYM(Lad_p) + +-#if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if !defined (__VFP_FP__) && !defined (__MAVERICK__) && !defined(__SOFTFP__) + + @ Legacy code expects the result to be returned in f0. Copy it + @ there as well. +Index: gcc-4.2.4/gcc/config/arm/ieee754-sf.S +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/ieee754-sf.S 2005-08-06 14:26:35.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/ieee754-sf.S 2009-08-09 15:43:45.000000000 +0100 +@@ -301,7 +301,7 @@ + ARM_FUNC_ALIAS aeabi_ul2f floatundisf + + orrs r2, r0, r1 +-#if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if !defined (__VFP_FP__) && !defined (__MAVERICK__) && !defined(__SOFTFP__) + mvfeqs f0, #0.0 + #endif + RETc(eq) +@@ -313,7 +313,7 @@ + ARM_FUNC_ALIAS aeabi_l2f floatdisf + + orrs r2, r0, r1 +-#if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if !defined (__VFP_FP__) && !defined (__MAVERICK__) && !defined(__SOFTFP__) + mvfeqs f0, #0.0 + #endif + RETc(eq) +@@ -323,7 +323,7 @@ + rsbs al, al, #0 + rsc ah, ah, #0 + 1: +-#if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if !defined (__VFP_FP__) && !defined (__MAVERICK__) && !defined(__SOFTFP__) + @ For hard FPA code we want to return via the tail below so that + @ we can return the result in f0 as well as in r0 for backwards + @ compatibility. +@@ -384,7 +384,7 @@ + biceq r0, r0, ip, lsr #31 + RET + +-#if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if !defined (__VFP_FP__) && !defined (__MAVERICK__) && !defined(__SOFTFP__) + + LSYM(f0_ret): + str r0, [sp, #-4]! diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-fix-64bit-const-offsets.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-fix-64bit-const-offsets.patch new file mode 100644 index 0000000000..78cf42690b --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-fix-64bit-const-offsets.patch @@ -0,0 +1,27 @@ +Fixup possible address offsets for constant double integers +also when using Maverick to handle 64-bit integers. + +Index: gcc-4.2.4/gcc/config/arm/arm.c +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.c 2009-08-09 15:43:44.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.c 2009-08-09 15:45:20.000000000 +0100 +@@ -3516,7 +3516,8 @@ + + use_ldrd = (TARGET_LDRD + && (mode == DImode +- || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP)))); ++ || (mode == DFmode ++ && (TARGET_SOFT_FLOAT || TARGET_VFP || TARGET_MAVERICK)))); + + if (code == POST_INC || code == PRE_DEC + || ((code == PRE_INC || code == POST_DEC) +@@ -4021,7 +4022,8 @@ + /* VFP addressing modes actually allow greater offsets, but for + now we just stick with the lowest common denominator. */ + if (mode == DImode +- || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode)) ++ || (mode == DFmode ++ && (TARGET_SOFT_FLOAT || TARGET_VFP || TARGET_MAVERICK))) + { + low_n = n & 0x0f; + n &= ~0x0f; diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-fix-cirrus-reorg7.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-fix-cirrus-reorg7.patch new file mode 100644 index 0000000000..05e2bfeb49 --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-fix-cirrus-reorg7.patch @@ -0,0 +1,328 @@ +This patch: +- maps branch-cirrus_insn to branch-nop-nop-cirrus_insn +- maps branch-noncirrus-cirrus to branch-noncirrus-nop-cirrus +- inserts a nop in load rN - load/store64 mvX,[rN] sequences to avoid an + undocumented hardware bug. +- always fixes up invalid code sequences when compiling hard Maverick insns + and removes the -mcirrus-fix-invalid-insns flag because chip development + has stopped and all existing silicon has these bugs, while the extra code + that claimed to do other things for the extra bugs in the old revision D0 + silicon was complete junk. +- Takes the cirrus checking out of the main arm_reorg loop, to remove the + speed penalty it caused when not compiling for Maverick. + + Martin Guy <martinwguy@yahoo.it> 3 March 2009 + +Index: gcc-4.2.4/gcc/config/arm/arm.c +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.c 2009-08-09 16:06:45.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.c 2009-08-09 16:08:04.000000000 +0100 +@@ -132,7 +132,7 @@ + static int arm_address_cost (rtx); + static bool arm_memory_load_p (rtx); + static bool arm_cirrus_insn_p (rtx); +-static void cirrus_reorg (rtx); ++static void cirrus_reorg (void); + static void arm_init_builtins (void); + static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); + static void arm_init_iwmmxt_builtins (void); +@@ -5491,6 +5491,9 @@ + + body = PATTERN (insn); + ++ if (GET_CODE (body) == COND_EXEC) ++ body = COND_EXEC_CODE (body); ++ + if (GET_CODE (body) != SET) + return false; + +@@ -5533,122 +5536,118 @@ + + /* Cirrus reorg for invalid instruction combinations. */ + static void +-cirrus_reorg (rtx first) ++cirrus_reorg (void) + { +- enum attr_cirrus attr; +- rtx body = PATTERN (first); +- rtx t; +- int nops; +- +- /* Any branch must be followed by 2 non Cirrus instructions. */ +- if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN) +- { +- nops = 0; +- t = next_nonnote_insn (first); +- +- if (arm_cirrus_insn_p (t)) +- ++ nops; +- +- if (arm_cirrus_insn_p (next_nonnote_insn (t))) +- ++ nops; +- +- while (nops --) +- emit_insn_after (gen_nop (), first); +- +- return; +- } +- +- /* (float (blah)) is in parallel with a clobber. */ +- if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) +- body = XVECEXP (body, 0, 0); +- +- if (GET_CODE (body) == SET) +- { +- rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1); ++ rtx insn, body; + +- /* cfldrd, cfldr64, cfstrd, cfstr64 must +- be followed by a non Cirrus insn. */ +- if (get_attr_cirrus (first) == CIRRUS_DOUBLE) +- { +- if (arm_cirrus_insn_p (next_nonnote_insn (first))) +- emit_insn_after (gen_nop (), first); +- +- return; +- } +- else if (arm_memory_load_p (first)) +- { +- unsigned int arm_regno; ++ /* Examine every instruction and see if it needs adjusting */ ++ for (insn = get_insns (); insn; insn = next_insn (insn)) ++ switch (GET_CODE (insn)) ++ { ++ case JUMP_INSN: ++ /* Any branch must be followed by 2 non Cirrus instructions. */ ++ body = PATTERN (insn); ++ if (GET_CODE (body) != RETURN) ++ { ++ rtx next = next_real_insn (insn); + +- /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr, +- ldr/cfmv64hr combination where the Rd field is the same +- in both instructions must be split with a non Cirrus +- insn. Example: ++ if (arm_cirrus_insn_p (next)) ++ { ++ emit_insn_after (gen_nop (), insn); ++ emit_insn_after (gen_nop (), insn); ++ } ++ else ++ if (arm_cirrus_insn_p (next_real_insn (next))) ++ emit_insn_after (gen_nop (), next); ++ } ++ break; + ++ case INSN: ++ /* Any ldr/cfstrd combination where the Rd field is the same ++ in both instructions must be split with a non Cirrus insn. ++ Example: + ldr r0, blah + nop +- cfmvsr mvf0, r0. */ +- +- /* Get Arm register number for ldr insn. */ +- if (GET_CODE (lhs) == REG) +- arm_regno = REGNO (lhs); +- else +- { +- gcc_assert (GET_CODE (rhs) == REG); +- arm_regno = REGNO (rhs); +- } +- +- /* Next insn. */ +- first = next_nonnote_insn (first); +- +- if (! arm_cirrus_insn_p (first)) +- return; +- +- body = PATTERN (first); ++ cfstrd mvd0, [r0] ++ otherwise the FPU stores to random memory locations. ++ */ ++ body = PATTERN (insn); ++ ++ /* Also applies to conditionally executed ldr */ ++ if (GET_CODE (body) == COND_EXEC) ++ body = COND_EXEC_CODE (body); + +- /* (float (blah)) is in parallel with a clobber. */ +- if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0)) +- body = XVECEXP (body, 0, 0); +- +- if (GET_CODE (body) == FLOAT) +- body = XEXP (body, 0); +- +- if (get_attr_cirrus (first) == CIRRUS_MOVE +- && GET_CODE (XEXP (body, 1)) == REG +- && arm_regno == REGNO (XEXP (body, 1))) +- emit_insn_after (gen_nop (), first); +- +- return; +- } +- } ++ /* If first insn is ldr rN, <mem>... */ ++ if (GET_CODE (body) == SET && arm_memory_load_p (insn)) ++ { ++ rtx next = next_real_insn (insn); + +- /* get_attr cannot accept USE or CLOBBER. */ +- if (!first +- || GET_CODE (first) != INSN +- || GET_CODE (PATTERN (first)) == USE +- || GET_CODE (PATTERN (first)) == CLOBBER) +- return; ++ /* ...and second is cirrus double word load or store... */ ++ if (arm_cirrus_insn_p (next) ++ && get_attr_cirrus (next) == CIRRUS_DOUBLE) ++ { ++ rtx nextbody = PATTERN (next); ++ rtx ldr_target; /* destination of ldr insn: rN */ ++ rtx arm_part; /* src or dest espression involving [rN] */ ++ unsigned int arm_regno; /* the arm reg in the [rN] part */ + +- attr = get_attr_cirrus (first); ++ ldr_target = XEXP (body, 0); ++ gcc_assert (GET_CODE (ldr_target) == REG); + +- /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...) +- must be followed by a non-coprocessor instruction. */ +- if (attr == CIRRUS_COMPARE) +- { +- nops = 0; ++ gcc_assert (GET_CODE (nextbody) == SET); + +- t = next_nonnote_insn (first); ++ /* Find the load or store address of the insn */ ++ switch (GET_CODE (XEXP (nextbody, 0))) ++ { ++ case MEM: /* it's cfstrd/64 */ ++ gcc_assert (GET_CODE (XEXP (nextbody, 1)) == REG); ++ arm_part = XEXP (XEXP (nextbody, 0), 0); ++ break; ++ ++ case REG: /* it's cfldrd/64 */ ++ if (GET_CODE (XEXP (nextbody, 1)) == MEM) ++ arm_part = XEXP (XEXP (nextbody, 1), 0); ++ else ++ /* It can also be const_double or const_int, which will ++ * turn into harmless [pc, #offset] in arm_reorg() */ ++ continue; ++ break; + +- if (arm_cirrus_insn_p (t)) +- ++ nops; ++ default: ++ gcc_unreachable (); ++ } + +- if (arm_cirrus_insn_p (next_nonnote_insn (t))) +- ++ nops; ++ /* Find the arm register number in the [rN] expression */ ++ arm_regno = 0; /* none */ ++ switch (GET_CODE (arm_part)) ++ { ++ case REG: /* it's [rN] */ ++ arm_regno = REGNO (arm_part); ++ break; ++ ++ case PLUS: /* it's [rN, #XXX] or [rN, -#YYY]. */ ++ case PRE_INC: ++ case POST_INC: ++ case PRE_DEC: ++ case POST_DEC: ++ gcc_assert (GET_CODE (XEXP (arm_part, 0)) == REG); ++ arm_regno = REGNO (XEXP (arm_part, 0)); ++ break; ++ ++ default: ++ /* Do nothing */ ++ continue; ++ } + +- while (nops --) +- emit_insn_after (gen_nop (), first); ++ if (arm_regno == REGNO (ldr_target)) ++ emit_insn_after (gen_nop (), insn); ++ } ++ } ++ break; + +- return; +- } ++ default: ++ break; ++ } + } + + /* Return TRUE if X references a SYMBOL_REF. */ +@@ -8227,6 +8226,10 @@ + + minipool_fix_head = minipool_fix_tail = NULL; + ++ /* Do cirrus_reorg() first as it may insert extra instructions */ ++ if (TARGET_MAVERICK && TARGET_HARD_FLOAT) ++ cirrus_reorg (); ++ + /* The first insn must always be a note, or the code below won't + scan it properly. */ + insn = get_insns (); +@@ -8236,12 +8239,6 @@ + /* Scan all the insns and record the operands that will need fixing. */ + for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn)) + { +- if (TARGET_CIRRUS_FIX_INVALID_INSNS +- && (arm_cirrus_insn_p (insn) +- || GET_CODE (insn) == JUMP_INSN +- || arm_memory_load_p (insn))) +- cirrus_reorg (insn); +- + if (GET_CODE (insn) == BARRIER) + push_minipool_barrier (insn, address); + else if (INSN_P (insn)) +Index: gcc-4.2.4/gcc/config/arm/arm.opt +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.opt 2009-08-09 16:06:46.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.opt 2009-08-09 16:07:39.000000000 +0100 +@@ -63,10 +63,6 @@ + Target Report Mask(CALLER_INTERWORKING) + Thumb: Assume function pointers may go to non-Thumb aware code + +-mcirrus-fix-invalid-insns +-Target Report Mask(CIRRUS_FIX_INVALID_INSNS) +-Cirrus: Place NOPs to avoid invalid instruction combinations +- + mcpu= + Target RejectNegative Joined + Specify the name of the target CPU +Index: gcc-4.2.4/gcc/doc/invoke.texi +=================================================================== +--- gcc-4.2.4.orig/gcc/doc/invoke.texi 2009-08-09 16:06:45.000000000 +0100 ++++ gcc-4.2.4/gcc/doc/invoke.texi 2009-08-09 16:07:39.000000000 +0100 +@@ -417,7 +417,6 @@ + -msingle-pic-base -mno-single-pic-base @gol + -mpic-register=@var{reg} @gol + -mnop-fun-dllimport @gol +--mcirrus-fix-invalid-insns -mno-cirrus-fix-invalid-insns @gol + -mieee @gol + -mpoke-function-name @gol + -mthumb -marm @gol +@@ -7771,18 +7770,6 @@ + Specify the register to be used for PIC addressing. The default is R10 + unless stack-checking is enabled, when R9 is used. + +-@item -mcirrus-fix-invalid-insns +-@opindex mcirrus-fix-invalid-insns +-@opindex mno-cirrus-fix-invalid-insns +-Insert NOPs into the instruction stream to in order to work around +-problems with invalid Maverick instruction combinations. This option +-is only valid if the @option{-mcpu=ep9312} option has been used to +-enable generation of instructions for the Cirrus Maverick floating +-point co-processor. This option is not enabled by default, since the +-problem is only present in older Maverick implementations. The default +-can be re-enabled by use of the @option{-mno-cirrus-fix-invalid-insns} +-switch. +- + @item -mieee + When compiling for the Maverick FPU, disable the instructions that fail + to honor denormalized values. As these include floating point add, sub, diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-floatsi-no-scratch.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-floatsi-no-scratch.patch new file mode 100644 index 0000000000..23fb7241bc --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-floatsi-no-scratch.patch @@ -0,0 +1,36 @@ +When converting from 32-bit integers (in ARM registers) to single and double +precision floating points (in Maverick registers), transfer the 32-bit value +straight to the destination register and convert it in place there, +instead of pointlessly using an extra Maverick register. + + Martin Guy <martinwguy@yahoo.it> 15 Nov 2008 + +Index: gcc-4.2.4/gcc/config/arm/cirrus.md +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/cirrus.md 2009-08-09 15:43:46.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/cirrus.md 2009-08-09 15:45:12.000000000 +0100 +@@ -300,20 +300,18 @@ + ;; Convert Cirrus-SI to Cirrus-SF + (define_insn "cirrus_floatsisf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") +- (float:SF (match_operand:SI 1 "s_register_operand" "r"))) +- (clobber (match_scratch:DF 2 "=v"))] ++ (float:SF (match_operand:SI 1 "s_register_operand" "r")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" +- "cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2" ++ "cfmv64lr%?\\t%Z0, %1\;cfcvt32s%?\\t%V0, %Y0" + [(set_attr "length" "8") + (set_attr "cirrus" "move")] + ) + + (define_insn "cirrus_floatsidf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") +- (float:DF (match_operand:SI 1 "s_register_operand" "r"))) +- (clobber (match_scratch:DF 2 "=v"))] ++ (float:DF (match_operand:SI 1 "s_register_operand" "r")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" +- "cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2" ++ "cfmv64lr%?\\t%Z0, %1\;cfcvt32d%?\\t%V0, %Y0" + [(set_attr "length" "8") + (set_attr "cirrus" "move")] + ) diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-fp_consts.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-fp_consts.patch new file mode 100644 index 0000000000..e48f6b859c --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-fp_consts.patch @@ -0,0 +1,17 @@ +Maverick does not have immediate FP constants. + +Index: gcc-4.2.4/gcc/config/arm/arm.c +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.c 2009-08-09 15:43:45.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.c 2009-08-09 15:45:10.000000000 +0100 +@@ -5266,7 +5266,9 @@ + int i; + REAL_VALUE_TYPE r; + +- if (TARGET_VFP) ++ if (TARGET_MAVERICK) ++ fp_consts_inited = 0; ++ else if (TARGET_VFP) + fp_consts_inited = 1; + else + fp_consts_inited = 8; diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-mieee.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-mieee.patch new file mode 100644 index 0000000000..e8a9d84b49 --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-mieee.patch @@ -0,0 +1,277 @@ +This patch adds an -mieee flag to GCC for ARM, that only has any effect when +hard MaverickCrunch FPU code generation is selected. +It disables the buggy instructions that do not recognise or do not generate +denormalized values when they should: + add, sub, neg, abs and float<->double conversions. +That leaves only floating point multiplication, comparison, conversions to/from +integers and the 64-bit integer operations. + + Martin Guy <martinwguy@yahoo.it>, December 2008 + +Index: gcc-4.2.4/gcc/doc/invoke.texi +=================================================================== +--- gcc-4.2.4.orig/gcc/doc/invoke.texi 2008-05-12 19:04:51.000000000 +0100 ++++ gcc-4.2.4/gcc/doc/invoke.texi 2009-08-09 15:44:55.000000000 +0100 +@@ -418,6 +418,7 @@ + -mpic-register=@var{reg} @gol + -mnop-fun-dllimport @gol + -mcirrus-fix-invalid-insns -mno-cirrus-fix-invalid-insns @gol ++-mieee @gol + -mpoke-function-name @gol + -mthumb -marm @gol + -mtpcs-frame -mtpcs-leaf-frame @gol +@@ -7782,6 +7783,15 @@ + can be re-enabled by use of the @option{-mno-cirrus-fix-invalid-insns} + switch. + ++@item -mieee ++When compiling for the Maverick FPU, disable the instructions that fail ++to honor denormalized values. As these include floating point add, sub, ++neg, abs and float<->double conversions, it incurs a severe speed penalty. ++This option only has an effect if the ++@option{-mcpu=ep9312} @option{-mfpu=maverick} options have been used and is ++disabled by default. ++The default can be re-enabled by use of the @option{-mno-ieee} switch. ++ + @item -mpoke-function-name + @opindex mpoke-function-name + Write the name of each function into the text section, directly +Index: gcc-4.2.4/gcc/config/arm/arm.opt +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.opt 2007-09-01 16:28:30.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.opt 2009-08-09 15:44:55.000000000 +0100 +@@ -93,6 +93,10 @@ + Target RejectNegative + Alias for -mfloat-abi=hard + ++mieee ++Target Report Mask(IEEE) ++Cirrus: Enable denormalized values by disabling buggy Maverick instructions ++ + mlittle-endian + Target Report RejectNegative InverseMask(BIG_END) + Assume target CPU is configured as little endian +Index: gcc-4.2.4/gcc/config/arm/arm.c +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.c 2009-08-09 15:43:46.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.c 2009-08-09 15:45:00.000000000 +0100 +@@ -858,6 +858,10 @@ + target_float_abi_name = "hard"; + return true; + ++ case OPT_mieee: ++ target_flags |= MASK_IEEE; ++ return true; ++ + case OPT_msoft_float: + target_float_abi_name = "soft"; + return true; +Index: gcc-4.2.4/gcc/config/arm/arm.md +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.md 2009-08-09 15:43:46.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.md 2009-08-09 15:44:59.000000000 +0100 +@@ -808,7 +808,7 @@ + [(set (match_operand:SF 0 "s_register_operand" "") + (plus:SF (match_operand:SF 1 "s_register_operand" "") + (match_operand:SF 2 "arm_float_add_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT" ++ "TARGET_ARM && TARGET_HARD_FLOAT && !(TARGET_MAVERICK && TARGET_IEEE)" + " + if (TARGET_MAVERICK + && !cirrus_fp_register (operands[2], SFmode)) +@@ -819,7 +819,7 @@ + [(set (match_operand:DF 0 "s_register_operand" "") + (plus:DF (match_operand:DF 1 "s_register_operand" "") + (match_operand:DF 2 "arm_float_add_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT" ++ "TARGET_ARM && TARGET_HARD_FLOAT && !(TARGET_MAVERICK && TARGET_IEEE)" + " + if (TARGET_MAVERICK + && !cirrus_fp_register (operands[2], DFmode)) +@@ -1031,7 +1031,7 @@ + [(set (match_operand:SF 0 "s_register_operand" "") + (minus:SF (match_operand:SF 1 "arm_float_rhs_operand" "") + (match_operand:SF 2 "arm_float_rhs_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT" ++ "TARGET_ARM && TARGET_HARD_FLOAT && !(TARGET_MAVERICK && TARGET_IEEE)" + " + if (TARGET_MAVERICK) + { +@@ -1046,7 +1046,7 @@ + [(set (match_operand:DF 0 "s_register_operand" "") + (minus:DF (match_operand:DF 1 "arm_float_rhs_operand" "") + (match_operand:DF 2 "arm_float_rhs_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT" ++ "TARGET_ARM && TARGET_HARD_FLOAT && !(TARGET_MAVERICK && TARGET_IEEE)" + " + if (TARGET_MAVERICK) + { +@@ -3047,7 +3047,7 @@ + (neg:SF (match_operand:SF 1 "s_register_operand" "")))] + "TARGET_ARM && TARGET_HARD_FLOAT + && (TARGET_FPA || TARGET_VFP +- || (TARGET_MAVERICK && ! HONOR_SIGNED_ZEROS(SFmode))" ++ || (TARGET_MAVERICK && ! HONOR_SIGNED_ZEROS(SFmode) && ! TARGET_IEEE))" + "" + ) + +@@ -3056,7 +3056,7 @@ + (neg:DF (match_operand:DF 1 "s_register_operand" "")))] + "TARGET_ARM && TARGET_HARD_FLOAT + && (TARGET_FPA || TARGET_VFP +- || (TARGET_MAVERICK && ! HONOR_SIGNED_ZEROS(DFmode))" ++ || (TARGET_MAVERICK && ! HONOR_SIGNED_ZEROS(DFmode) && ! TARGET_IEEE))" + "") + + ;; abssi2 doesn't really clobber the condition codes if a different register +@@ -3103,13 +3103,13 @@ + (define_expand "abssf2" + [(set (match_operand:SF 0 "s_register_operand" "") + (abs:SF (match_operand:SF 1 "s_register_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT" ++ "TARGET_ARM && TARGET_HARD_FLOAT && !(TARGET_MAVERICK && TARGET_IEEE)" + "") + + (define_expand "absdf2" + [(set (match_operand:DF 0 "s_register_operand" "") + (abs:DF (match_operand:DF 1 "s_register_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT" ++ "TARGET_ARM && TARGET_HARD_FLOAT && !(TARGET_MAVERICK && TARGET_IEEE)" + "") + + (define_expand "sqrtsf2" +@@ -3247,7 +3247,7 @@ + [(set (match_operand:SF 0 "s_register_operand" "") + (float_truncate:SF + (match_operand:DF 1 "s_register_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT" ++ "TARGET_ARM && TARGET_HARD_FLOAT && !(TARGET_MAVERICK && TARGET_IEEE)" + "" + ) + +@@ -4084,7 +4084,7 @@ + (define_expand "extendsfdf2" + [(set (match_operand:DF 0 "s_register_operand" "") + (float_extend:DF (match_operand:SF 1 "s_register_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT" ++ "TARGET_ARM && TARGET_HARD_FLOAT && !(TARGET_MAVERICK && TARGET_IEEE)" + "" + ) + +Index: gcc-4.2.4/gcc/config/arm/cirrus.md +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/cirrus.md 2009-08-09 15:43:47.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/cirrus.md 2009-08-09 15:44:57.000000000 +0100 +@@ -101,11 +101,12 @@ + (set_attr "cirrus" "normal")] + ) + ++; Cirrus hardware bug: denormalized values on input are truncated to zero + (define_insn "*cirrus_addsf3" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (plus:SF (match_operand:SF 1 "cirrus_fp_register" "v") + (match_operand:SF 2 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && ! TARGET_IEEE" + "cfadds%?\\t%V0, %V1, %V2" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -115,7 +116,7 @@ + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (plus:DF (match_operand:DF 1 "cirrus_fp_register" "v") + (match_operand:DF 2 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && ! TARGET_IEEE" + "cfaddd%?\\t%V0, %V1, %V2" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -145,7 +146,7 @@ + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (minus:SF (match_operand:SF 1 "cirrus_fp_register" "v") + (match_operand:SF 2 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && ! TARGET_IEEE" + "cfsubs%?\\t%V0, %V1, %V2" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -155,7 +156,7 @@ + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (minus:DF (match_operand:DF 1 "cirrus_fp_register" "v") + (match_operand:DF 2 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && ! TARGET_IEEE" + "cfsubd%?\\t%V0, %V1, %V2" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -316,10 +317,12 @@ + ) + + ; Cirrus hardware bug: neg 0 -> 0 instead of -0 ++; Cirrus hardware bug: denormalized values on input are truncated to zero + (define_insn "*cirrus_negsf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (neg:SF (match_operand:SF 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && ! HONOR_SIGNED_ZEROS (SFmode)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK ++ && ! HONOR_SIGNED_ZEROS (SFmode) && ! TARGET_IEEE" + "cfnegs%?\\t%V0, %V1" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -328,7 +331,8 @@ + (define_insn "*cirrus_negdf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (neg:DF (match_operand:DF 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && ! HONOR_SIGNED_ZEROS (DFmode)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK ++ && ! HONOR_SIGNED_ZEROS (DFmode) && ! TARGET_IEEE" + "cfnegd%?\\t%V0, %V1" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -345,10 +349,11 @@ + (set_attr "cirrus" "normal")] + ) + ++; Cirrus hardware bug: denormalized values on input are truncated to zero + (define_insn "*cirrus_abssf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (abs:SF (match_operand:SF 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && ! TARGET_IEEE" + "cfabss%?\\t%V0, %V1" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -357,7 +362,7 @@ + (define_insn "*cirrus_absdf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (abs:DF (match_operand:DF 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && ! TARGET_IEEE" + "cfabsd%?\\t%V0, %V1" + [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] +@@ -423,20 +428,23 @@ + (set_attr "length" "8")] + ) + ++; Cirrus hardware bugs: denormalized values on input are truncated to zero ++; and double-to-single float never produces denormalized values. + (define_insn "*cirrus_truncdfsf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (float_truncate:SF + (match_operand:DF 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && ! TARGET_IEEE" + "cfcvtds%?\\t%V0, %V1" + [(set_attr "type" "f_cvt") + (set_attr "cirrus" "normal")] + ) + ++; Cirrus hardware bug: denormalized values on input are truncated to zero + (define_insn "*cirrus_extendsfdf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (float_extend:DF (match_operand:SF 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && ! TARGET_IEEE" + "cfcvtsd%?\\t%V0, %V1" + [(set_attr "type" "f_cvt") + (set_attr "cirrus" "normal")] diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-movsf-movdf-Uy.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-movsf-movdf-Uy.patch new file mode 100644 index 0000000000..c127f4d369 --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-movsf-movdf-Uy.patch @@ -0,0 +1,66 @@ +This is a rewriting of the OE patch of the same name. + +The OE patch is different to this in that it: +- reorders the constraints (we keep them in the same order) +- its definition of attr "type" seem not to correspond to the insns it uses + (so here we define them to what seems right) +- in movdf, it replaces operand 1 "general_operand" with "soft_df_operand" and + removes the first two clauses (r<->Q = memory indexed by base register) + +Index: gcc-4.2.4/gcc/config/arm/cirrus.md +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/cirrus.md 2009-08-09 15:43:46.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/cirrus.md 2009-08-09 15:45:08.000000000 +0100 +@@ -403,8 +403,8 @@ + ;; on HARD_REGNO_MODE_OK. + + (define_insn "*cirrus_movsf_hard_insn" +- [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m") +- (match_operand:SF 1 "general_operand" "v,mE,r,v,v,r,mE,r"))] ++ [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v ,v,r,Uy,r,r,m") ++ (match_operand:SF 1 "general_operand" "v,UyE,r,v,v ,r,mE,r"))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK + && (GET_CODE (operands[0]) != MEM + || register_operand (operands[1], SFmode))" +@@ -414,19 +414,18 @@ + cfmvsr%?\\t%V0, %1 + cfmvrs%?\\t%0, %V1 + cfstrs%?\\t%V1, %0 +- mov%?\\t%0, %1 ++ mov%?\\t%0, %1\\t%@ float + ldr%?\\t%0, %1\\t%@ float + str%?\\t%1, %0\\t%@ float" +- [(set_attr "length" " *, *, *, *, *, 4, 4, 4") +- (set_attr "type" " *, load1, *, *,store1, *,load1,store1") +- (set_attr "pool_range" " *, 1020, *, *, *, *,4096, *") +- (set_attr "neg_pool_range" " *, 1008, *, *, *, *,4084, *") ++ [(set_attr "type" "ffarith,f_loads,r_2_f,f_2_r,f_stores,*,load1,store1") ++ (set_attr "pool_range" " *, 1020, *, *, *, *,4096, *") ++ (set_attr "neg_pool_range" " *, 1008, *, *, *, *,4080, *") + (set_attr "cirrus" "normal,normal,move,normal,normal,not, not, not")] + ) + + (define_insn "*cirrus_movdf_hard_insn" +- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m") +- (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,mF,r,v,v"))] ++ [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r ,v,v ,v,r,Uy") ++ (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,UyF,r,v,v"))] + "TARGET_ARM + && TARGET_HARD_FLOAT && TARGET_MAVERICK + && (GET_CODE (operands[0]) != MEM +@@ -447,10 +446,10 @@ + default: gcc_unreachable (); + } + }" +- [(set_attr "type" "load1,store2, *,store2,load1, *, load1, *, *,store2") +- (set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4") +- (set_attr "pool_range" " *, *, *, *, 252, *, 1020, *, *, *") +- (set_attr "neg_pool_range" " *, *, *, *, 244, *, 1008, *, *, *") +- (set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")] ++ [(set_attr "type" "load2,store2, *,store2,load2,ffarith,f_loadd,r_2_f,f_2_r,store2") ++ (set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4") ++ (set_attr "pool_range" " *, *, *, *, 1020, *, 1020, *, *, *") ++ (set_attr "neg_pool_range" " *, *, *, *, 1008, *, 1008, *, *, *") ++ (set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")] + ) + diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-neg-enable.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-neg-enable.patch new file mode 100644 index 0000000000..0156594794 --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-neg-enable.patch @@ -0,0 +1,33 @@ +In arm.md, enable expansion for neg[sd]f for Maverick - the instructions are +already already defined in cirrus.md + +Without this patch for some reason it still manages to produce cfnegd +instructions but not cfnegs, presumably via some optimization path. + + Martin Guy <martinwguy@yahoo.it> December 2008 + +Index: gcc-4.2.4/gcc/config/arm/arm.md +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.md 2009-08-09 15:43:45.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.md 2009-08-09 15:45:15.000000000 +0100 +@@ -3046,14 +3046,18 @@ + (define_expand "negsf2" + [(set (match_operand:SF 0 "s_register_operand" "") + (neg:SF (match_operand:SF 1 "s_register_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP ++ || (TARGET_MAVERICK && ! HONOR_SIGNED_ZEROS(SFmode))" + "" + ) + + (define_expand "negdf2" + [(set (match_operand:DF 0 "s_register_operand" "") + (neg:DF (match_operand:DF 1 "s_register_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT ++ && (TARGET_FPA || TARGET_VFP ++ || (TARGET_MAVERICK && ! HONOR_SIGNED_ZEROS(DFmode))" + "") + + ;; abssi2 doesn't really clobber the condition codes if a different register diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-neg-protect.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-neg-protect.patch new file mode 100644 index 0000000000..a675d4b07a --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-neg-protect.patch @@ -0,0 +1,35 @@ +The Crunch cfnegs and cfnegd instructions have a hardware bug in all silicon +revisions (D0 to E2) whereby neg(0) returns 0 (not -0). See erratum 12. + +For ieee-correctness, and to pass another case in GCC's IEEE testsuite, +we disable the instruction and do it in software unless +-funsafe-math-optimizations (included in -ffast-math) is given. + + Martin Guy <martinwguy@yahoo.it>, September 2008 + +Index: gcc-4.2.4/gcc/config/arm/cirrus.md +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/cirrus.md 2007-09-01 16:28:30.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/cirrus.md 2009-08-09 15:45:13.000000000 +0100 +@@ -254,10 +254,11 @@ + [(set_attr "cirrus" "normal")] + ) + ++; Cirrus hardware bug: neg 0 -> 0 instead of -0 + (define_insn "*cirrus_negsf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (neg:SF (match_operand:SF 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && ! HONOR_SIGNED_ZEROS (SFmode)" + "cfnegs%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) +@@ -265,7 +266,7 @@ + (define_insn "*cirrus_negdf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (neg:DF (match_operand:DF 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && ! HONOR_SIGNED_ZEROS (DFmode)" + "cfnegd%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-pipeline.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-pipeline.patch new file mode 100644 index 0000000000..a8c4286ec3 --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-pipeline.patch @@ -0,0 +1,464 @@ +Patch to add description of MaverickCrunch pipelines. + +This increases the speed as measured by the fftw benchmark from +5.4 to 5.8 mflops and reduced LAME's execution time from 2m30 to 2m20. + +I don't know who wrote this - I got it from Hasjim Williams. + + -martinwguy + +Index: gcc-4.2.4/gcc/config/arm/arm.md +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.md 2009-08-09 15:43:46.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.md 2009-08-09 15:45:07.000000000 +0100 +@@ -223,12 +223,9 @@ + ; store2 store 2 words + ; store3 store 3 words + ; store4 store 4 (or more) words +-; Additions for Cirrus Maverick co-processor: +-; mav_farith Floating point arithmetic (4 cycle) +-; mav_dmult Double multiplies (7 cycle) + ; + (define_attr "type" +- "alu,alu_shift,alu_shift_reg,mult,block,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith,f_flag,float_em,f_load,f_store,f_loads,f_loadd,f_stores,f_stored,f_mem_r,r_mem_f,f_2_r,r_2_f,f_cvt,branch,call,load_byte,load1,load2,load3,load4,store1,store2,store3,store4,mav_farith,mav_dmult" ++ "alu,alu_shift,alu_shift_reg,mult,block,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith,f_flag,float_em,f_load,f_store,f_loads,f_loadd,f_stores,f_stored,f_mem_r,r_mem_f,f_2_r,r_2_f,f_cvt,branch,call,load_byte,load1,load2,load3,load4,store1,store2,store3,store4" + (if_then_else + (eq_attr "insn" "smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals") + (const_string "mult") +@@ -6967,7 +6964,7 @@ + (match_operand:SF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfcmps%?\\tr15, %V0, %V1" +- [(set_attr "type" "mav_farith") ++ [(set_attr "type" "farith") + (set_attr "cirrus" "compare")] + ) + +@@ -6978,7 +6975,7 @@ + (match_operand:DF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfcmpd%?\\tr15, %V0, %V1" +- [(set_attr "type" "mav_farith") ++ [(set_attr "type" "farith") + (set_attr "cirrus" "compare")] + ) + +@@ -7001,7 +6998,7 @@ + (match_operand:DI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK & 0" + "cfcmp64%?\\tr15, %V0, %V1" +- [(set_attr "type" "mav_farith") ++ [(set_attr "type" "farith") + (set_attr "cirrus" "compare")] + ) + +Index: gcc-4.2.4/gcc/config/arm/cirrus.md +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/cirrus.md 2009-08-09 15:43:46.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/cirrus.md 2009-08-09 15:45:04.000000000 +0100 +@@ -19,6 +19,58 @@ + ;; along with GCC; see the file COPYING3. If not see + ;; <http://www.gnu.org/licenses/>. + ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; Pipeline description ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ ++(define_automaton "crunch") ++ ++;; There are 2 pipelines in the CRUNCH unit. ++;; ++;; - A 8/9-stage? FMAC pipeline (7/8? execute + writeback) ++;; ++;; - A 4-stage LS pipeline (execute + 2 memory + writeback) with forward from ++;; second memory stage for loads. ++ ++(define_cpu_unit "crunch_fmac" "crunch") ++ ++(define_cpu_unit "crunch_ls" "crunch") ++ ++;; The CRUNCH "type" attributes differ from those used in the FPA and VFP model. ++;; ffarith Fast floating point insns. ++;; farith Most arithmetic insns. ++;; fmul Double precision multiply. ++;; f_load[sd] Floating point load from memory. ++;; f_store[sd] Floating point store to memory. ++;; f_2_r Transfer crunch to arm reg. ++;; r_2_f Transfer arm to crunch reg. ++;; f_cvt Convert floating<->integral ++ ++(define_insn_reservation "crunch_ffarith" 18 ++ (and (eq_attr "fpu" "maverick") ++ (eq_attr "type" "ffarith")) ++ "crunch_fmac") ++ ++(define_insn_reservation "crunch_farith" 18 ++ (and (eq_attr "fpu" "maverick") ++ (eq_attr "type" "farith,f_cvt")) ++ "crunch_fmac") ++ ++(define_insn_reservation "crunch_fmul" 30 ++ (and (eq_attr "fpu" "maverick") ++ (eq_attr "type" "fmul")) ++ "crunch_fmac*2") ++ ++;; Moves to/from arm regs also use the load/store pipeline. ++(define_insn_reservation "crunch_fload" 8 ++ (and (eq_attr "fpu" "maverick") ++ (eq_attr "type" "f_loads,f_loadd,r_2_f")) ++ "crunch_ls") ++ ++(define_insn_reservation "crunch_fstore" 8 ++ (and (eq_attr "fpu" "maverick") ++ (eq_attr "type" "f_stores,f_stored,f_2_r")) ++ "crunch_ls") + + ; Cirrus types for invalid insn combinations + ; not Not a cirrus insn +@@ -35,7 +87,7 @@ + (match_operand:DI 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfadd64%?\\t%V0, %V1, %V2" +- [(set_attr "type" "mav_farith") ++ [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] + ) + +@@ -45,7 +97,7 @@ + (match_operand:SI 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfadd32%?\\t%V0, %V1, %V2" +- [(set_attr "type" "mav_farith") ++ [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] + ) + +@@ -55,7 +107,7 @@ + (match_operand:SF 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfadds%?\\t%V0, %V1, %V2" +- [(set_attr "type" "mav_farith") ++ [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] + ) + +@@ -65,7 +117,7 @@ + (match_operand:DF 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfaddd%?\\t%V0, %V1, %V2" +- [(set_attr "type" "mav_farith") ++ [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] + ) + +@@ -75,7 +127,7 @@ + (match_operand:DI 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfsub64%?\\t%V0, %V1, %V2" +- [(set_attr "type" "mav_farith") ++ [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] + ) + +@@ -85,7 +137,7 @@ + (match_operand:SI 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfsub32%?\\t%V0, %V1, %V2" +- [(set_attr "type" "mav_farith") ++ [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] + ) + +@@ -95,7 +147,7 @@ + (match_operand:SF 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfsubs%?\\t%V0, %V1, %V2" +- [(set_attr "type" "mav_farith") ++ [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] + ) + +@@ -105,7 +157,7 @@ + (match_operand:DF 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfsubd%?\\t%V0, %V1, %V2" +- [(set_attr "type" "mav_farith") ++ [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] + ) + +@@ -115,7 +167,7 @@ + (match_operand:SI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfmul32%?\\t%V0, %V1, %V2" +- [(set_attr "type" "mav_farith") ++ [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] + ) + +@@ -125,7 +177,7 @@ + (match_operand:DI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfmul64%?\\t%V0, %V1, %V2" +- [(set_attr "type" "mav_dmult") ++ [(set_attr "type" "fmul") + (set_attr "cirrus" "normal")] + ) + +@@ -137,7 +189,7 @@ + (match_operand:SI 3 "cirrus_fp_register" "0")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfmac32%?\\t%V0, %V1, %V2" +- [(set_attr "type" "mav_farith") ++ [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] + ) + +@@ -150,7 +202,7 @@ + (match_operand:SI 3 "cirrus_fp_register" "v"))))] + "0 && TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfmsc32%?\\t%V0, %V2, %V3" +- [(set_attr "type" "mav_farith") ++ [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] + ) + +@@ -160,7 +212,7 @@ + (match_operand:SF 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfmuls%?\\t%V0, %V1, %V2" +- [(set_attr "type" "mav_farith") ++ [(set_attr "type" "farith") + (set_attr "cirrus" "normal")] + ) + +@@ -170,7 +222,7 @@ + (match_operand:DF 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfmuld%?\\t%V0, %V1, %V2" +- [(set_attr "type" "mav_dmult") ++ [(set_attr "type" "fmul") + (set_attr "cirrus" "normal")] + ) + +@@ -180,7 +232,8 @@ + (match_operand:SI 2 "cirrus_shift_const" "")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfsh32%?\\t%V0, %V1, #%s2" +- [(set_attr "cirrus" "normal")] ++ [(set_attr "type" "farith") ++ (set_attr "cirrus" "normal")] + ) + + (define_insn "cirrus_ashiftrt_const" +@@ -189,7 +242,8 @@ + (match_operand:SI 2 "cirrus_shift_const" "")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfsh32%?\\t%V0, %V1, #-%s2" +- [(set_attr "cirrus" "normal")] ++ [(set_attr "type" "farith") ++ (set_attr "cirrus" "normal")] + ) + + (define_insn "cirrus_ashlsi3" +@@ -198,7 +252,8 @@ + (match_operand:SI 2 "register_operand" "r")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfrshl32%?\\t%V1, %V0, %s2" +- [(set_attr "cirrus" "normal")] ++ [(set_attr "type" "farith") ++ (set_attr "cirrus" "normal")] + ) + + (define_insn "ashldi3_cirrus" +@@ -207,7 +262,8 @@ + (match_operand:SI 2 "register_operand" "r")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfrshl64%?\\t%V1, %V0, %s2" +- [(set_attr "cirrus" "normal")] ++ [(set_attr "type" "farith") ++ (set_attr "cirrus" "normal")] + ) + + (define_insn "cirrus_ashldi_const" +@@ -216,7 +272,8 @@ + (match_operand:SI 2 "cirrus_shift_const" "")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfsh64%?\\t%V0, %V1, #%s2" +- [(set_attr "cirrus" "normal")] ++ [(set_attr "type" "farith") ++ (set_attr "cirrus" "normal")] + ) + + (define_insn "cirrus_ashiftrtdi_const" +@@ -225,7 +282,8 @@ + (match_operand:SI 2 "cirrus_shift_const" "")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfsh64%?\\t%V0, %V1, #-%s2" +- [(set_attr "cirrus" "normal")] ++ [(set_attr "type" "farith") ++ (set_attr "cirrus" "normal")] + ) + + (define_insn "*cirrus_absdi2" +@@ -233,7 +291,8 @@ + (abs:DI (match_operand:DI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfabs64%?\\t%V0, %V1" +- [(set_attr "cirrus" "normal")] ++ [(set_attr "type" "farith") ++ (set_attr "cirrus" "normal")] + ) + + ;; This doesn't really clobber ``cc''. Fixme: aldyh. +@@ -243,7 +302,8 @@ + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfneg64%?\\t%V0, %V1" +- [(set_attr "cirrus" "normal")] ++ [(set_attr "type" "farith") ++ (set_attr "cirrus" "normal")] + ) + + (define_insn "*cirrus_negsi2" +@@ -251,7 +311,8 @@ + (neg:SI (match_operand:SI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfneg32%?\\t%V0, %V1" +- [(set_attr "cirrus" "normal")] ++ [(set_attr "type" "farith") ++ (set_attr "cirrus" "normal")] + ) + + ; Cirrus hardware bug: neg 0 -> 0 instead of -0 +@@ -260,7 +321,8 @@ + (neg:SF (match_operand:SF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && ! HONOR_SIGNED_ZEROS (SFmode)" + "cfnegs%?\\t%V0, %V1" +- [(set_attr "cirrus" "normal")] ++ [(set_attr "type" "farith") ++ (set_attr "cirrus" "normal")] + ) + + (define_insn "*cirrus_negdf2" +@@ -268,7 +330,8 @@ + (neg:DF (match_operand:DF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && ! HONOR_SIGNED_ZEROS (DFmode)" + "cfnegd%?\\t%V0, %V1" +- [(set_attr "cirrus" "normal")] ++ [(set_attr "type" "farith") ++ (set_attr "cirrus" "normal")] + ) + + ;; This doesn't really clobber the condition codes either. +@@ -278,7 +341,8 @@ + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfabs32%?\\t%V0, %V1" +- [(set_attr "cirrus" "normal")] ++ [(set_attr "type" "farith") ++ (set_attr "cirrus" "normal")] + ) + + (define_insn "*cirrus_abssf2" +@@ -286,7 +350,8 @@ + (abs:SF (match_operand:SF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfabss%?\\t%V0, %V1" +- [(set_attr "cirrus" "normal")] ++ [(set_attr "type" "farith") ++ (set_attr "cirrus" "normal")] + ) + + (define_insn "*cirrus_absdf2" +@@ -294,7 +359,8 @@ + (abs:DF (match_operand:DF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfabsd%?\\t%V0, %V1" +- [(set_attr "cirrus" "normal")] ++ [(set_attr "type" "farith") ++ (set_attr "cirrus" "normal")] + ) + + ;; Convert Cirrus-SI to Cirrus-SF +@@ -303,7 +369,8 @@ + (float:SF (match_operand:SI 1 "s_register_operand" "r")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfmv64lr%?\\t%Z0, %1\;cfcvt32s%?\\t%V0, %Y0" +- [(set_attr "length" "8") ++ [(set_attr "type" "f_cvt") ++ (set_attr "length" "8") + (set_attr "cirrus" "move")] + ) + +@@ -312,7 +379,8 @@ + (float:DF (match_operand:SI 1 "s_register_operand" "r")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfmv64lr%?\\t%Z0, %1\;cfcvt32d%?\\t%V0, %Y0" +- [(set_attr "length" "8") ++ [(set_attr "type" "f_cvt") ++ (set_attr "length" "8") + (set_attr "cirrus" "move")] + ) + +@@ -321,14 +389,18 @@ + (float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfcvt64s%?\\t%V0, %V1" +- [(set_attr "cirrus" "normal")]) ++ [(set_attr "type" "f_cvt") ++ (set_attr "cirrus" "normal")] ++) + + (define_insn "floatdidf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfcvt64d%?\\t%V0, %V1" +- [(set_attr "cirrus" "normal")]) ++ [(set_attr "type" "f_cvt") ++ (set_attr "cirrus" "normal")] ++) + + (define_insn "cirrus_truncsfsi2" + [(set (match_operand:SI 0 "s_register_operand" "=r") +@@ -336,7 +408,8 @@ + (clobber (match_scratch:DF 2 "=v"))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" +- [(set_attr "length" "8") ++ [(set_attr "type" "f_cvt") ++ (set_attr "length" "8") + (set_attr "cirrus" "normal")] + ) + +@@ -346,7 +419,8 @@ + (clobber (match_scratch:DF 2 "=v"))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" +- [(set_attr "length" "8")] ++ [(set_attr "type" "f_cvt") ++ (set_attr "length" "8")] + ) + + (define_insn "*cirrus_truncdfsf2" +@@ -355,7 +429,8 @@ + (match_operand:DF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfcvtds%?\\t%V0, %V1" +- [(set_attr "cirrus" "normal")] ++ [(set_attr "type" "f_cvt") ++ (set_attr "cirrus" "normal")] + ) + + (define_insn "*cirrus_extendsfdf2" +@@ -363,7 +438,8 @@ + (float_extend:DF (match_operand:SF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cfcvtsd%?\\t%V0, %V1" +- [(set_attr "cirrus" "normal")] ++ [(set_attr "type" "f_cvt") ++ (set_attr "cirrus" "normal")] + ) + + (define_insn "*cirrus_arm_movdi" diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-readme.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-readme.patch new file mode 100644 index 0000000000..8e07712b48 --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-readme.patch @@ -0,0 +1,109 @@ +Index: gcc-4.2.4/gcc/config/arm/README-Maverick +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ gcc-4.2.4/gcc/config/arm/README-Maverick 2009-08-09 15:43:44.000000000 +0100 +@@ -0,0 +1,104 @@ ++Cirrus Logic MaverickCrunch FPU support ++======================================= ++ ++The MaverickCrunch is an FPU coprocessor that only exists in combination ++with an arm920t (ARMv4t arch) integer core in the 200MHz EP93xx devices. ++Code generation for it is usually selected with ++ -mcpu=ep9312 -mfpu=maverick (and most likely -mfloat-abi=softfp) ++ ++Within GCC, the names "cirrus" "maverick" and "crunch" are used randomly ++in filenames and identifiers, but they all refer to the same thing. ++ ++Initial support was mainlined by RedHat in gcc-3 but this never generated ++working code. Cirrus Logic funded the company Nucleusys to produce a modified ++GCC for it, but this never worked either. The first set of patches to pass ++the testsuite were made by Hasjim Williams for Open Embedded, though they ++did this by disabling various features and optimisations, therby incurring ++a small negative impact on regular ARM code generation. ++The OE ideas were reimplemented by Martin Guy to produce a working compiler ++with no negwative impact on regular code generation. ++ ++The FPU's characteristics ++------------------------- ++Like most ARM coprocessors, it runs in parallel with the ARM though its ++instructions are inserted into the regular ARM instructions stream. ++It has 16 64-bit registers that can be operated as 32-bit or 64-bit integers ++or as 32-bit or 64-bit floats, three 72-bit saturating multiplier-accumulators. ++It can add, sub, mul, cmp, abs and neg these types, convert between them and ++transfer values between its registers and the ARM registers or main memory. ++ ++Comparisons performed in the Maverick unit set the condition codes differently ++from the ARM/FPA/VFP instructions: ++ ++ ARM/FPA/VFP - (cmp*): MaverickCrunch - (cfcmp*): ++ N Z C V N Z C V ++ A == B 0 1 1 0 A == B 0 1 0 0 ++ A < B 1 0 0 0 A < B 1 0 0 0 ++ A > B 0 0 1 0 A > B 1 0 0 1 ++ unord 0 0 1 1 unord 0 0 0 0 ++ ++which means that the same conditions have to be tested for with different ARM ++conditions after a Maverick comparison. Furthermore, some conditions cannot ++be tested with a single condition. ++This was already true on ARM/FPA/VFP for conditions UNEQ and LTGT; ++on Maverick comparisons it is GE UNLT ORDERED and UNORDERED that cannot. ++(GE after a floating point comparison, that is, not after an integer comarison) ++ ++GCC's use of the Maverick unit ++------------------------------ ++GCC only uses the 32-bit and 64-bit floating point modes and the 64-bit ++integer mode. It does not use the 72-bit accumulators or the 32-bit integer ++mode because, from "GCC Machine Descriptions": ++ "It is obligatory to support floating point `movm' instructions ++ into and out of any registers that can hold fixed point values, ++ because unions and structures (which have modes SImode or DImode) ++ can be in those registers and they may have floating point members." ++(search also for "grief" in arm.c). ++ ++It does not use the 64-bit integer comparison instruction because it can only ++do a signed or an unsigned comparison, while GCC expect the comparison to set ++the conditions codes for both modes and then to use the signed or unsigned ++mode when the condition code bits are tested. ++ ++The different setting of the condition codes is tracked with an additional ++CCMAV mode for the condition code register, set when a comparison is performed ++in the Maverick unit. This always indicates a floating point comparison since ++the Maverick's 64-bit comparison is not used. ++ ++Hardware bugs and workarounds ++----------------------------- ++All silicon implementations of the FPU have a dozen hardware bugs, mostly ++timing-dependent bugs that can write garbage into registers or memory or get ++conditional tests wrong, as well as a widespread failure to respect ++denormalised values. See http://wiki.debian.org/ArmEabiMaverickCrunch ++ ++There used to be a -mcirrus-fix-invalid-instructions flag that claimed ++to avoid bugs in revision D0 silicon but its code was broken junk. ++Currently GCC always avoids the timing bugs in revision D1 to E2 silicon, ++while the many extra timing bugs in the now rare revision D0 are not handled. ++ ++By default, the instructions that drop denoermalized values are enabled ++so as to obtain maximum speed at lower precision. By default, the cfnegs ++and cfnegd instrutions are disabled, since they also fail to produce negative ++zero. They can be enabled with -fno-signed-zeros. ++ ++When -mfpu=maverick is selected, an additional -mieee flag is active that ++gives full IEEE precision by performs all the non-denorm-respecting ++floating point instructions in the softfloat library routines or in the ++integer registers. ++ ++The 64-bit integer support is still buggy so it is disabled unless the ++-mcirrus-di flag is supplied. As well as the having unidentified ++hardware bugs which make openssl's testsuite fail in */sha/sha512.c and in ++*/bn/bn_adm.c, 64-bit shifts only work up to 31 places left or 32 right. ++ ++Other bugs ++---------- ++There seems to be no way to configure GCC to select Maverick code generation ++as the default. ++ ++--with-arch=ep9312 the assembler barfs saying that ep9312 is not a ++recognised architecture. ++--with-arch=armv4t the build fails when it tries to compile hard FPA ++instructions into libgcc, ++--with-cpu=ep9312 it compiles armv5t instructions into libgcc diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-repair-truncxfsi.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-repair-truncxfsi.patch new file mode 100644 index 0000000000..c5b22824f7 --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-repair-truncxfsi.patch @@ -0,0 +1,31 @@ +Fix two bugs in the Maverick trunc[sd]fsi expansions: +- the target of cirrus_truncsfsi2 is an ARM register, not a Maverick register. +- a typo in both descriptions transfers info for operand 0 into operand 1 + + Martin Guy <martinwguy"yahoo.it> 15 Nov 2008 + +Index: gcc-4.2.4/gcc/config/arm/arm.md +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.md 2009-08-09 15:43:45.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.md 2009-08-09 15:45:08.000000000 +0100 +@@ -3221,10 +3221,8 @@ + " + if (TARGET_MAVERICK) + { +- if (!cirrus_fp_register (operands[0], SImode)) +- operands[0] = force_reg (SImode, operands[0]); + if (!cirrus_fp_register (operands[1], SFmode)) +- operands[1] = force_reg (SFmode, operands[0]); ++ operands[1] = force_reg (SFmode, operands[1]); + emit_insn (gen_cirrus_truncsfsi2 (operands[0], operands[1])); + DONE; + } +@@ -3238,7 +3236,7 @@ + if (TARGET_MAVERICK) + { + if (!cirrus_fp_register (operands[1], DFmode)) +- operands[1] = force_reg (DFmode, operands[0]); ++ operands[1] = force_reg (DFmode, operands[1]); + emit_insn (gen_cirrus_truncdfsi2 (operands[0], operands[1])); + DONE; + } diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-saveregs.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-saveregs.patch new file mode 100644 index 0000000000..1ddde6568a --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-saveregs.patch @@ -0,0 +1,90 @@ +Save Maverick registers on function entry and restore them on exit if they +are modified within the function and are among those that must be preserved +across function calls. + +Also check whether Maverick registers need restoring when deciding whether to +return directly from the middle of a function without an epilogue. + +This combines futaris' [saveregs] and [use_return_insn] patches. + +Index: gcc-4.2.4/gcc/config/arm/arm.c +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.c 2007-09-01 16:28:30.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.c 2009-08-09 15:45:22.000000000 +0100 +@@ -1577,6 +1577,12 @@ + if (regs_ever_live[regno] && !call_used_regs[regno]) + return 0; + ++ /* Likewise Maverick regs. */ ++ if (TARGET_HARD_FLOAT && TARGET_MAVERICK) ++ for (regno = FIRST_CIRRUS_FP_REGNUM; regno <= LAST_CIRRUS_FP_REGNUM; regno++) ++ if (regs_ever_live[regno] && !call_used_regs[regno]) ++ return 0; ++ + if (TARGET_REALLY_IWMMXT) + for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++) + if (regs_ever_live[regno] && ! call_used_regs [regno]) +@@ -9889,6 +9895,17 @@ + reg, FP_REGNUM, floats_offset - vfp_offset); + } + } ++ else if (arm_fpu_arch == FPUTYPE_MAVERICK) ++ { ++ for (reg = LAST_CIRRUS_FP_REGNUM; reg >= FIRST_CIRRUS_FP_REGNUM; reg--) ++ if (regs_ever_live[reg] && !call_used_regs[reg]) ++ { ++ floats_offset += 8; ++ asm_fprintf (f, "\tcfldrd\tmvd%d, [%r, #-%d]\n", ++ reg - FIRST_CIRRUS_FP_REGNUM, FP_REGNUM, ++ floats_offset - vfp_offset); ++ } ++ } + else + { + start_reg = LAST_FPA_REGNUM; +@@ -10035,6 +10052,13 @@ + asm_fprintf (f, "\tldfe\t%r, [%r], #12\n", + reg, SP_REGNUM); + } ++ else if (arm_fpu_arch == FPUTYPE_MAVERICK) ++ { ++ for (reg = FIRST_CIRRUS_FP_REGNUM; reg <= LAST_CIRRUS_FP_REGNUM; reg++) ++ if (regs_ever_live[reg] && !call_used_regs[reg]) ++ asm_fprintf (f, "\tcfldrd\tmvd%u, [%r], #8\n", ++ reg - FIRST_CIRRUS_FP_REGNUM, SP_REGNUM); ++ } + else + { + start_reg = FIRST_FPA_REGNUM; +@@ -10529,6 +10553,11 @@ + func_type = arm_current_func_type (); + if (! IS_VOLATILE (func_type)) + { ++ /* Space for saved MAVERICK registers. */ ++ for (regno = FIRST_CIRRUS_FP_REGNUM; regno <= LAST_CIRRUS_FP_REGNUM; regno++) ++ if (regs_ever_live[regno] && ! call_used_regs[regno]) ++ saved += 8; ++ + /* Space for saved FPA registers. */ + for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) + if (regs_ever_live[regno] && ! call_used_regs[regno]) +@@ -10837,6 +10866,19 @@ + saved_regs += 12; + } + } ++ else if (arm_fpu_arch == FPUTYPE_MAVERICK) ++ { ++ for (reg = LAST_CIRRUS_FP_REGNUM; reg >= FIRST_CIRRUS_FP_REGNUM; reg--) ++ if (regs_ever_live[reg] && !call_used_regs[reg]) ++ { ++ insn = gen_rtx_PRE_DEC (DFmode, stack_pointer_rtx); ++ insn = gen_rtx_MEM (DFmode, insn); ++ insn = emit_insn (gen_rtx_SET (VOIDmode, insn, ++ gen_rtx_REG (DFmode, reg))); ++ RTX_FRAME_RELATED_P (insn) = 1; ++ saved_regs += 8; ++ } ++ } + else + { + start_reg = LAST_FPA_REGNUM; diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-scratch.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-scratch.patch new file mode 100644 index 0000000000..7782f61a5e --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-crunch-scratch.patch @@ -0,0 +1,26 @@ +Increase the number of Cirrus scratch registers from 4 to 8 (ie half of them) + +Index: gcc-4.2.4/gcc/config/arm/arm.h +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.h 2007-09-01 16:28:30.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.h 2009-08-09 15:45:06.000000000 +0100 +@@ -562,8 +562,8 @@ + + /* + mvf0 Cirrus floating point result +- mvf1-mvf3 Cirrus floating point scratch +- mvf4-mvf15 S Cirrus floating point variable. */ ++ mvf1-mvf7 Cirrus floating point scratch ++ mvf8-mvf15 S Cirrus floating point variable. */ + + /* s0-s15 VFP scratch (aka d0-d7). + s16-s31 S VFP variable (aka d8-d15). +@@ -680,7 +680,7 @@ + regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \ + { \ + fixed_regs[regno] = 0; \ +- call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \ ++ call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 8; \ + } \ + } \ + if (TARGET_VFP) \ diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-prologue_use-length.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-prologue_use-length.patch new file mode 100644 index 0000000000..26a60d413c --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-prologue_use-length.patch @@ -0,0 +1,12 @@ +Index: gcc-4.2.4/gcc/config/arm/arm.md +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.md 2009-08-09 15:43:47.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.md 2009-08-09 15:44:52.000000000 +0100 +@@ -10509,6 +10509,7 @@ + [(unspec:SI [(match_operand:SI 0 "register_operand" "")] UNSPEC_PROLOGUE_USE)] + "" + "%@ %0 needed for prologue" ++ [(set_attr "length" "0")] + ) + + diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/arm-size-bugfix.patch b/recipes/gcc/gcc-4.2.4/ep93xx/arm-size-bugfix.patch new file mode 100644 index 0000000000..86daf146f7 --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/arm-size-bugfix.patch @@ -0,0 +1,27 @@ +Fix an obvious bug in GCC-4.3.2's ARM code generator. + +PR target/37668 + * arm.c (arm_size_rtx_costs, case NEG): Don't fall through if the + result will be in an FPU register. + +This has been applied in gcc-4.4.0 + + Martin Guy <martinwguy@yahoo.it> + +Index: gcc-4.2.4/gcc/config/arm/arm.c +=================================================================== +--- gcc-4.2.4.orig/gcc/config/arm/arm.c 2009-08-09 15:43:47.000000000 +0100 ++++ gcc-4.2.4/gcc/config/arm/arm.c 2009-08-09 15:44:55.000000000 +0100 +@@ -4771,7 +4771,11 @@ + + case NEG: + if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) +- *total = COSTS_N_INSNS (1); ++ { ++ *total = COSTS_N_INSNS (1); ++ return false; ++ } ++ + /* Fall through */ + case NOT: + *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); diff --git a/recipes/gcc/gcc-4.2.4/ep93xx/series b/recipes/gcc/gcc-4.2.4/ep93xx/series new file mode 100644 index 0000000000..626cf54314 --- /dev/null +++ b/recipes/gcc/gcc-4.2.4/ep93xx/series @@ -0,0 +1,26 @@ +arm-crunch-readme.patch +arm-crunch-saveregs.patch +arm-crunch-scratch.patch +arm-crunch-eabi-ieee754-endian-littleword-littlebyte.patch +arm-crunch-eabi-mvf0-scratch-ieee754.patch +arm-crunch-20000320.patch +arm-crunch-disable-cmpdi.patch +arm-crunch-fix-64bit-const-offsets.patch +arm-crunch-fp_consts.patch +arm-crunch-neg-enable.patch +arm-crunch-neg-protect.patch +arm-crunch-repair-truncxfsi.patch +arm-crunch-floatsi-no-scratch.patch +arm-crunch-movsf-movdf-Uy.patch +arm-crunch-drop-thumb2.patch +arm-crunch-arm_dbx_register_number.patch +arm-crunch-pipeline.patch +arm-crunch-ccmav-mode.patch +arm-crunch-cfcpy-with-cfsh64.patch +arm-crunch-mieee.patch +arm-size-bugfix.patch +arm-prologue_use-length.patch +arm-crunch-cftruncd32-attr.patch +arm-crunch-fix-cirrus-reorg7.patch +arm-crunch-cirrus-di-flag.patch +arm-crunch-disable-floatsi.patch diff --git a/recipes/gcc/gcc-4.3.3.inc b/recipes/gcc/gcc-4.3.3.inc index 4a3cb49496..9dd46ec16c 100644 --- a/recipes/gcc/gcc-4.3.3.inc +++ b/recipes/gcc/gcc-4.3.3.inc @@ -7,7 +7,7 @@ LICENSE = "GPLv3" DEPENDS = "mpfr gmp" -INC_PR = "r6" +INC_PR = "r7" SRC_URI = "${GNU_MIRROR}/gcc/gcc-${PV}/gcc-${PV}.tar.bz2 \ file://fedora/gcc43-c++-builtin-redecl.patch;patch=1;pnum=0 \ @@ -88,8 +88,9 @@ SRC_URI_append_ep93xx = " \ file://ep93xx/arm-size-bugfix.patch;patch=1 \ file://ep93xx/arm-prologue_use-length.patch;patch=1 \ file://ep93xx/arm-crunch-cftruncd32-attr.patch;patch=1 \ - file://ep93xx/arm-crunch-fix-cirrus-reorg5.patch;patch=1 \ + file://ep93xx/arm-crunch-fix-cirrus-reorg7.patch;patch=1 \ file://ep93xx/arm-crunch-cirrus-di-flag.patch;patch=1 \ + file://ep93xx/arm-crunch-disable-floatsi.patch;patch=1 \ " # Language Overrides FORTRAN = "" diff --git a/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-disable-floatsi.patch b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-disable-floatsi.patch new file mode 100644 index 0000000000..d7512ba042 --- /dev/null +++ b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-disable-floatsi.patch @@ -0,0 +1,64 @@ +int->float instructions cfcvt32s and cfcvt32d do seem to work but if they are +enabled, the vorbis testsuite (file lib/vorbisenc.c) fail and lame to segfault +on nonstandard bit rate wav files such as 11050 bps (file libmp3lame/util.c). + +Until someone wants to figure out what the real problem is we just disable these +two insns because then everything seems to work. + +Index: gcc-4.3.4/gcc/config/arm/arm.md +=================================================================== +--- gcc-4.3.4.orig/gcc/config/arm/arm.md 2009-09-11 11:39:37.000000000 +0100 ++++ gcc-4.3.4/gcc/config/arm/arm.md 2009-09-11 11:42:49.000000000 +0100 +@@ -3543,10 +3543,14 @@ + + ;; Fixed <--> Floating conversion insns + ++; Maverick int->float conversion insns seem to work but tickle an optimization ++; bug in GCC 4.[123].* so we paper over it to get working code :-/ ++; It may be the same as http://gcc.gnu.org/bugzilla/show_bug.cgi?id=39501 ++ + (define_expand "floatsisf2" + [(set (match_operand:SF 0 "s_register_operand" "") + (float:SF (match_operand:SI 1 "s_register_operand" "")))] +- "TARGET_32BIT && TARGET_HARD_FLOAT" ++ "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_MAVERICK" + " + if (TARGET_MAVERICK) + { +@@ -3558,7 +3562,7 @@ + (define_expand "floatsidf2" + [(set (match_operand:DF 0 "s_register_operand" "") + (float:DF (match_operand:SI 1 "s_register_operand" "")))] +- "TARGET_32BIT && TARGET_HARD_FLOAT" ++ "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_MAVERICK" + " + if (TARGET_MAVERICK) + { +Index: gcc-4.3.4/gcc/config/arm/cirrus.md +=================================================================== +--- gcc-4.3.4.orig/gcc/config/arm/cirrus.md 2009-09-11 11:39:47.000000000 +0100 ++++ gcc-4.3.4/gcc/config/arm/cirrus.md 2009-09-11 11:44:04.000000000 +0100 +@@ -359,10 +359,13 @@ + ) + + ;; Convert Cirrus-SI to Cirrus-SF ++ ++; int->float conversions are disabled to avoid a GCC bug. See arm.md ++ + (define_insn "cirrus_floatsisf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (float:SF (match_operand:SI 1 "s_register_operand" "r")))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfmv64lr%?\\t%Z0, %1\;cfcvt32s%?\\t%V0, %Y0" + [(set_attr "type" "f_cvt") + (set_attr "length" "8") +@@ -372,7 +375,7 @@ + (define_insn "cirrus_floatsidf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (float:DF (match_operand:SI 1 "s_register_operand" "r")))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfmv64lr%?\\t%Z0, %1\;cfcvt32d%?\\t%V0, %Y0" + [(set_attr "type" "f_cvt") + (set_attr "length" "8") diff --git a/recipes/gcc/gcc-4.3.4/ep93xx/arm-crunch-fix-cirrus-reorg5.patch b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-fix-cirrus-reorg7.patch index 313b7001bd..1be8499643 100644 --- a/recipes/gcc/gcc-4.3.4/ep93xx/arm-crunch-fix-cirrus-reorg5.patch +++ b/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-fix-cirrus-reorg7.patch @@ -13,8 +13,10 @@ This patch: Martin Guy <martinwguy@yahoo.it> 3 March 2009 ---- gcc-4.3.2/gcc/config/arm/arm.c.orig 2009-02-18 14:59:22.000000000 +0000 -+++ gcc-4.3.2/gcc/config/arm/arm.c 2009-03-10 09:32:31.000000000 +0000 +Index: gcc-4.3.4/gcc/config/arm/arm.c +=================================================================== +--- gcc-4.3.4.orig/gcc/config/arm/arm.c 2009-08-09 14:46:51.000000000 +0100 ++++ gcc-4.3.4/gcc/config/arm/arm.c 2009-08-09 14:47:11.000000000 +0100 @@ -134,7 +134,7 @@ static int arm_address_cost (rtx); static bool arm_memory_load_p (rtx); @@ -24,7 +26,17 @@ This patch: static void arm_init_builtins (void); static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); static void arm_init_iwmmxt_builtins (void); -@@ -6580,122 +6580,122 @@ +@@ -6538,6 +6538,9 @@ + + body = PATTERN (insn); + ++ if (GET_CODE (body) == COND_EXEC) ++ body = COND_EXEC_CODE (body); ++ + if (GET_CODE (body) != SET) + return false; + +@@ -6580,122 +6583,118 @@ /* Cirrus reorg for invalid instruction combinations. */ static void @@ -61,15 +73,15 @@ This patch: - if (GET_CODE (body) == SET) - { - rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1); -- ++ rtx insn, body; + - /* cfldrd, cfldr64, cfstrd, cfstr64 must - be followed by a non Cirrus insn. */ - if (get_attr_cirrus (first) == CIRRUS_DOUBLE) - { - if (arm_cirrus_insn_p (next_nonnote_insn (first))) - emit_insn_after (gen_nop (), first); -+ rtx insn, body; - +- - return; - } - else if (arm_memory_load_p (first)) @@ -117,14 +129,18 @@ This patch: - gcc_assert (GET_CODE (rhs) == REG); - arm_regno = REGNO (rhs); - } +- +- /* Next insn. */ +- first = next_nonnote_insn (first); + cfstrd mvd0, [r0] + otherwise the FPU stores to random memory locations. + */ + body = PATTERN (insn); ++ ++ /* Also applies to conditionally executed ldr */ ++ if (GET_CODE (body) == COND_EXEC) ++ body = COND_EXEC_CODE (body); -- /* Next insn. */ -- first = next_nonnote_insn (first); -- - if (! arm_cirrus_insn_p (first)) - return; + /* If first insn is ldr rN, <mem>... */ @@ -206,16 +222,6 @@ This patch: - if (arm_cirrus_insn_p (t)) - ++ nops; + case PLUS: /* it's [rN, #XXX] or [rN, -#YYY]. */ -+ if (GET_CODE (XEXP (arm_part, 0)) == REG) -+ arm_regno = REGNO (XEXP (arm_part, 0)); /* usual case */ -+ else if (GET_CODE (XEXP (arm_part, 1)) == REG) -+ arm_regno = REGNO (XEXP (arm_part, 1)); /* inverted */ -+ else -+ gcc_unreachable(); -+ break; - -- if (arm_cirrus_insn_p (next_nonnote_insn (t))) -- ++ nops; + case PRE_INC: + case POST_INC: + case PRE_DEC: @@ -224,28 +230,30 @@ This patch: + arm_regno = REGNO (XEXP (arm_part, 0)); + break; -- while (nops --) -- emit_insn_after (gen_nop (), first); +- if (arm_cirrus_insn_p (next_nonnote_insn (t))) +- ++ nops; + default: + /* Do nothing */ + continue; + } -- return; -- } +- while (nops --) +- emit_insn_after (gen_nop (), first); + if (arm_regno == REGNO (ldr_target)) + emit_insn_after (gen_nop (), insn); + } + } + break; -+ + +- return; +- } + default: + break; + } } /* Return TRUE if X references a SYMBOL_REF. */ -@@ -9293,6 +9296,10 @@ +@@ -9293,6 +9292,10 @@ minipool_fix_head = minipool_fix_tail = NULL; @@ -256,7 +264,7 @@ This patch: /* The first insn must always be a note, or the code below won't scan it properly. */ insn = get_insns (); -@@ -9302,12 +9309,6 @@ +@@ -9302,12 +9305,6 @@ /* Scan all the insns and record the operands that will need fixing. */ for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn)) { @@ -269,8 +277,10 @@ This patch: if (GET_CODE (insn) == BARRIER) push_minipool_barrier (insn, address); else if (INSN_P (insn)) ---- gcc-4.3.2/gcc/config/arm/arm.opt.orig 2009-03-02 10:17:08.000000000 +0000 -+++ gcc-4.3.2/gcc/config/arm/arm.opt 2009-03-02 10:27:30.000000000 +0000 +Index: gcc-4.3.4/gcc/config/arm/arm.opt +=================================================================== +--- gcc-4.3.4.orig/gcc/config/arm/arm.opt 2009-08-09 14:46:51.000000000 +0100 ++++ gcc-4.3.4/gcc/config/arm/arm.opt 2009-08-09 14:47:11.000000000 +0100 @@ -63,10 +63,6 @@ Target Report Mask(CALLER_INTERWORKING) Thumb: Assume function pointers may go to non-Thumb aware code @@ -282,8 +292,10 @@ This patch: mcpu= Target RejectNegative Joined Specify the name of the target CPU ---- gcc-4.3.2/gcc/doc/invoke.texi.old 2008-12-04 11:48:54.000000000 +0000 -+++ gcc-4.3.2/gcc/doc/invoke.texi 2009-03-02 10:26:45.000000000 +0000 +Index: gcc-4.3.4/gcc/doc/invoke.texi +=================================================================== +--- gcc-4.3.4.orig/gcc/doc/invoke.texi 2009-08-09 14:46:51.000000000 +0100 ++++ gcc-4.3.4/gcc/doc/invoke.texi 2009-08-09 14:47:12.000000000 +0100 @@ -429,7 +429,6 @@ -msingle-pic-base -mno-single-pic-base @gol -mpic-register=@var{reg} @gol @@ -292,7 +304,7 @@ This patch: -mieee @gol -mpoke-function-name @gol -mthumb -marm @gol -@@ -8671,18 +8671,6 @@ +@@ -8673,18 +8672,6 @@ Specify the register to be used for PIC addressing. The default is R10 unless stack-checking is enabled, when R9 is used. diff --git a/recipes/gcc/gcc-4.3.3/ep93xx/series b/recipes/gcc/gcc-4.3.3/ep93xx/series index e6bfe421f1..626cf54314 100644 --- a/recipes/gcc/gcc-4.3.3/ep93xx/series +++ b/recipes/gcc/gcc-4.3.3/ep93xx/series @@ -16,10 +16,11 @@ arm-crunch-drop-thumb2.patch arm-crunch-arm_dbx_register_number.patch arm-crunch-pipeline.patch arm-crunch-ccmav-mode.patch -arm-crunch-cfcpy-with-cfsh64.patch -arm-crunch-mieee.patch +arm-crunch-cfcpy-with-cfsh64.patch +arm-crunch-mieee.patch arm-size-bugfix.patch arm-prologue_use-length.patch arm-crunch-cftruncd32-attr.patch -arm-crunch-fix-cirrus-reorg5.patch +arm-crunch-fix-cirrus-reorg7.patch arm-crunch-cirrus-di-flag.patch +arm-crunch-disable-floatsi.patch diff --git a/recipes/gcc/gcc-4.3.4.inc b/recipes/gcc/gcc-4.3.4.inc index 90cda07e07..2b1054c0f5 100644 --- a/recipes/gcc/gcc-4.3.4.inc +++ b/recipes/gcc/gcc-4.3.4.inc @@ -7,7 +7,7 @@ LICENSE = "GPLv3" DEPENDS = "mpfr gmp" -INC_PR = "r6" +INC_PR = "r7" SRC_URI = "${GNU_MIRROR}/gcc/gcc-${PV}/gcc-${PV}.tar.bz2 \ file://fedora/gcc43-c++-builtin-redecl.patch;patch=1;pnum=0 \ @@ -88,8 +88,9 @@ SRC_URI_append_ep93xx = " \ file://ep93xx/arm-size-bugfix.patch;patch=1 \ file://ep93xx/arm-prologue_use-length.patch;patch=1 \ file://ep93xx/arm-crunch-cftruncd32-attr.patch;patch=1 \ - file://ep93xx/arm-crunch-fix-cirrus-reorg5.patch;patch=1 \ + file://ep93xx/arm-crunch-fix-cirrus-reorg7.patch;patch=1 \ file://ep93xx/arm-crunch-cirrus-di-flag.patch;patch=1 \ + file://ep93xx/arm-crunch-disable-floatsi.patch;patch=1 \ " # Language Overrides FORTRAN = "" diff --git a/recipes/gcc/gcc-4.3.4/ep93xx/arm-crunch-disable-floatsi.patch b/recipes/gcc/gcc-4.3.4/ep93xx/arm-crunch-disable-floatsi.patch new file mode 100644 index 0000000000..d7512ba042 --- /dev/null +++ b/recipes/gcc/gcc-4.3.4/ep93xx/arm-crunch-disable-floatsi.patch @@ -0,0 +1,64 @@ +int->float instructions cfcvt32s and cfcvt32d do seem to work but if they are +enabled, the vorbis testsuite (file lib/vorbisenc.c) fail and lame to segfault +on nonstandard bit rate wav files such as 11050 bps (file libmp3lame/util.c). + +Until someone wants to figure out what the real problem is we just disable these +two insns because then everything seems to work. + +Index: gcc-4.3.4/gcc/config/arm/arm.md +=================================================================== +--- gcc-4.3.4.orig/gcc/config/arm/arm.md 2009-09-11 11:39:37.000000000 +0100 ++++ gcc-4.3.4/gcc/config/arm/arm.md 2009-09-11 11:42:49.000000000 +0100 +@@ -3543,10 +3543,14 @@ + + ;; Fixed <--> Floating conversion insns + ++; Maverick int->float conversion insns seem to work but tickle an optimization ++; bug in GCC 4.[123].* so we paper over it to get working code :-/ ++; It may be the same as http://gcc.gnu.org/bugzilla/show_bug.cgi?id=39501 ++ + (define_expand "floatsisf2" + [(set (match_operand:SF 0 "s_register_operand" "") + (float:SF (match_operand:SI 1 "s_register_operand" "")))] +- "TARGET_32BIT && TARGET_HARD_FLOAT" ++ "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_MAVERICK" + " + if (TARGET_MAVERICK) + { +@@ -3558,7 +3562,7 @@ + (define_expand "floatsidf2" + [(set (match_operand:DF 0 "s_register_operand" "") + (float:DF (match_operand:SI 1 "s_register_operand" "")))] +- "TARGET_32BIT && TARGET_HARD_FLOAT" ++ "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_MAVERICK" + " + if (TARGET_MAVERICK) + { +Index: gcc-4.3.4/gcc/config/arm/cirrus.md +=================================================================== +--- gcc-4.3.4.orig/gcc/config/arm/cirrus.md 2009-09-11 11:39:47.000000000 +0100 ++++ gcc-4.3.4/gcc/config/arm/cirrus.md 2009-09-11 11:44:04.000000000 +0100 +@@ -359,10 +359,13 @@ + ) + + ;; Convert Cirrus-SI to Cirrus-SF ++ ++; int->float conversions are disabled to avoid a GCC bug. See arm.md ++ + (define_insn "cirrus_floatsisf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (float:SF (match_operand:SI 1 "s_register_operand" "r")))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfmv64lr%?\\t%Z0, %1\;cfcvt32s%?\\t%V0, %Y0" + [(set_attr "type" "f_cvt") + (set_attr "length" "8") +@@ -372,7 +375,7 @@ + (define_insn "cirrus_floatsidf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (float:DF (match_operand:SI 1 "s_register_operand" "r")))] +- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfmv64lr%?\\t%Z0, %1\;cfcvt32d%?\\t%V0, %Y0" + [(set_attr "type" "f_cvt") + (set_attr "length" "8") diff --git a/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-fix-cirrus-reorg5.patch b/recipes/gcc/gcc-4.3.4/ep93xx/arm-crunch-fix-cirrus-reorg7.patch index 313b7001bd..1be8499643 100644 --- a/recipes/gcc/gcc-4.3.3/ep93xx/arm-crunch-fix-cirrus-reorg5.patch +++ b/recipes/gcc/gcc-4.3.4/ep93xx/arm-crunch-fix-cirrus-reorg7.patch @@ -13,8 +13,10 @@ This patch: Martin Guy <martinwguy@yahoo.it> 3 March 2009 ---- gcc-4.3.2/gcc/config/arm/arm.c.orig 2009-02-18 14:59:22.000000000 +0000 -+++ gcc-4.3.2/gcc/config/arm/arm.c 2009-03-10 09:32:31.000000000 +0000 +Index: gcc-4.3.4/gcc/config/arm/arm.c +=================================================================== +--- gcc-4.3.4.orig/gcc/config/arm/arm.c 2009-08-09 14:46:51.000000000 +0100 ++++ gcc-4.3.4/gcc/config/arm/arm.c 2009-08-09 14:47:11.000000000 +0100 @@ -134,7 +134,7 @@ static int arm_address_cost (rtx); static bool arm_memory_load_p (rtx); @@ -24,7 +26,17 @@ This patch: static void arm_init_builtins (void); static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); static void arm_init_iwmmxt_builtins (void); -@@ -6580,122 +6580,122 @@ +@@ -6538,6 +6538,9 @@ + + body = PATTERN (insn); + ++ if (GET_CODE (body) == COND_EXEC) ++ body = COND_EXEC_CODE (body); ++ + if (GET_CODE (body) != SET) + return false; + +@@ -6580,122 +6583,118 @@ /* Cirrus reorg for invalid instruction combinations. */ static void @@ -61,15 +73,15 @@ This patch: - if (GET_CODE (body) == SET) - { - rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1); -- ++ rtx insn, body; + - /* cfldrd, cfldr64, cfstrd, cfstr64 must - be followed by a non Cirrus insn. */ - if (get_attr_cirrus (first) == CIRRUS_DOUBLE) - { - if (arm_cirrus_insn_p (next_nonnote_insn (first))) - emit_insn_after (gen_nop (), first); -+ rtx insn, body; - +- - return; - } - else if (arm_memory_load_p (first)) @@ -117,14 +129,18 @@ This patch: - gcc_assert (GET_CODE (rhs) == REG); - arm_regno = REGNO (rhs); - } +- +- /* Next insn. */ +- first = next_nonnote_insn (first); + cfstrd mvd0, [r0] + otherwise the FPU stores to random memory locations. + */ + body = PATTERN (insn); ++ ++ /* Also applies to conditionally executed ldr */ ++ if (GET_CODE (body) == COND_EXEC) ++ body = COND_EXEC_CODE (body); -- /* Next insn. */ -- first = next_nonnote_insn (first); -- - if (! arm_cirrus_insn_p (first)) - return; + /* If first insn is ldr rN, <mem>... */ @@ -206,16 +222,6 @@ This patch: - if (arm_cirrus_insn_p (t)) - ++ nops; + case PLUS: /* it's [rN, #XXX] or [rN, -#YYY]. */ -+ if (GET_CODE (XEXP (arm_part, 0)) == REG) -+ arm_regno = REGNO (XEXP (arm_part, 0)); /* usual case */ -+ else if (GET_CODE (XEXP (arm_part, 1)) == REG) -+ arm_regno = REGNO (XEXP (arm_part, 1)); /* inverted */ -+ else -+ gcc_unreachable(); -+ break; - -- if (arm_cirrus_insn_p (next_nonnote_insn (t))) -- ++ nops; + case PRE_INC: + case POST_INC: + case PRE_DEC: @@ -224,28 +230,30 @@ This patch: + arm_regno = REGNO (XEXP (arm_part, 0)); + break; -- while (nops --) -- emit_insn_after (gen_nop (), first); +- if (arm_cirrus_insn_p (next_nonnote_insn (t))) +- ++ nops; + default: + /* Do nothing */ + continue; + } -- return; -- } +- while (nops --) +- emit_insn_after (gen_nop (), first); + if (arm_regno == REGNO (ldr_target)) + emit_insn_after (gen_nop (), insn); + } + } + break; -+ + +- return; +- } + default: + break; + } } /* Return TRUE if X references a SYMBOL_REF. */ -@@ -9293,6 +9296,10 @@ +@@ -9293,6 +9292,10 @@ minipool_fix_head = minipool_fix_tail = NULL; @@ -256,7 +264,7 @@ This patch: /* The first insn must always be a note, or the code below won't scan it properly. */ insn = get_insns (); -@@ -9302,12 +9309,6 @@ +@@ -9302,12 +9305,6 @@ /* Scan all the insns and record the operands that will need fixing. */ for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn)) { @@ -269,8 +277,10 @@ This patch: if (GET_CODE (insn) == BARRIER) push_minipool_barrier (insn, address); else if (INSN_P (insn)) ---- gcc-4.3.2/gcc/config/arm/arm.opt.orig 2009-03-02 10:17:08.000000000 +0000 -+++ gcc-4.3.2/gcc/config/arm/arm.opt 2009-03-02 10:27:30.000000000 +0000 +Index: gcc-4.3.4/gcc/config/arm/arm.opt +=================================================================== +--- gcc-4.3.4.orig/gcc/config/arm/arm.opt 2009-08-09 14:46:51.000000000 +0100 ++++ gcc-4.3.4/gcc/config/arm/arm.opt 2009-08-09 14:47:11.000000000 +0100 @@ -63,10 +63,6 @@ Target Report Mask(CALLER_INTERWORKING) Thumb: Assume function pointers may go to non-Thumb aware code @@ -282,8 +292,10 @@ This patch: mcpu= Target RejectNegative Joined Specify the name of the target CPU ---- gcc-4.3.2/gcc/doc/invoke.texi.old 2008-12-04 11:48:54.000000000 +0000 -+++ gcc-4.3.2/gcc/doc/invoke.texi 2009-03-02 10:26:45.000000000 +0000 +Index: gcc-4.3.4/gcc/doc/invoke.texi +=================================================================== +--- gcc-4.3.4.orig/gcc/doc/invoke.texi 2009-08-09 14:46:51.000000000 +0100 ++++ gcc-4.3.4/gcc/doc/invoke.texi 2009-08-09 14:47:12.000000000 +0100 @@ -429,7 +429,6 @@ -msingle-pic-base -mno-single-pic-base @gol -mpic-register=@var{reg} @gol @@ -292,7 +304,7 @@ This patch: -mieee @gol -mpoke-function-name @gol -mthumb -marm @gol -@@ -8671,18 +8671,6 @@ +@@ -8673,18 +8672,6 @@ Specify the register to be used for PIC addressing. The default is R10 unless stack-checking is enabled, when R9 is used. diff --git a/recipes/gcc/gcc-4.3.4/ep93xx/series b/recipes/gcc/gcc-4.3.4/ep93xx/series index e6bfe421f1..626cf54314 100644 --- a/recipes/gcc/gcc-4.3.4/ep93xx/series +++ b/recipes/gcc/gcc-4.3.4/ep93xx/series @@ -16,10 +16,11 @@ arm-crunch-drop-thumb2.patch arm-crunch-arm_dbx_register_number.patch arm-crunch-pipeline.patch arm-crunch-ccmav-mode.patch -arm-crunch-cfcpy-with-cfsh64.patch -arm-crunch-mieee.patch +arm-crunch-cfcpy-with-cfsh64.patch +arm-crunch-mieee.patch arm-size-bugfix.patch arm-prologue_use-length.patch arm-crunch-cftruncd32-attr.patch -arm-crunch-fix-cirrus-reorg5.patch +arm-crunch-fix-cirrus-reorg7.patch arm-crunch-cirrus-di-flag.patch +arm-crunch-disable-floatsi.patch |