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authorCliff Brake <cbrake@bec-systems.com>2009-02-16 10:03:32 -0500
committerCliff Brake <cbrake@bec-systems.com>2009-02-16 10:03:32 -0500
commitd512927cbf42dc9a3302ecac790a18d397ea012f (patch)
tree2d624d29a763e5f9ae9b618148cfc6063e6cd50e /packages/u-boot/u-boot-1.3.2/boc01/013-090206-FIX_OOB_8BITS_LARGEPAGE_NAND.patch
parent68e1ea7aeddc4f7efc621558dfd424cd2fe22674 (diff)
parent3fe1150b7afa91ee59dfa6346c1f7387638b7817 (diff)
Merge branch 'org.openembedded.dev' of git@git.openembedded.net:openembedded into org.openembedded.dev
Diffstat (limited to 'packages/u-boot/u-boot-1.3.2/boc01/013-090206-FIX_OOB_8BITS_LARGEPAGE_NAND.patch')
-rw-r--r--packages/u-boot/u-boot-1.3.2/boc01/013-090206-FIX_OOB_8BITS_LARGEPAGE_NAND.patch29
1 files changed, 29 insertions, 0 deletions
diff --git a/packages/u-boot/u-boot-1.3.2/boc01/013-090206-FIX_OOB_8BITS_LARGEPAGE_NAND.patch b/packages/u-boot/u-boot-1.3.2/boc01/013-090206-FIX_OOB_8BITS_LARGEPAGE_NAND.patch
new file mode 100644
index 0000000000..803b46d8e9
--- /dev/null
+++ b/packages/u-boot/u-boot-1.3.2/boc01/013-090206-FIX_OOB_8BITS_LARGEPAGE_NAND.patch
@@ -0,0 +1,29 @@
+Index: u-boot-1.3.2/drivers/mtd/nand/nand_bbt.c
+===================================================================
+--- u-boot-1.3.2.orig/drivers/mtd/nand/nand_bbt.c 2008-03-09 16:20:02.000000000 +0100
++++ u-boot-1.3.2/drivers/mtd/nand/nand_bbt.c 2009-02-06 14:50:35.000000000 +0100
+@@ -914,10 +914,11 @@
+ .pattern = scan_ff_pattern
+ };
+
++//Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048.
+ static struct nand_bbt_descr largepage_memorybased = {
+ .options = 0,
+ .offs = 0,
+- .len = 2,
++ .len = 1,
+ .pattern = scan_ff_pattern
+ };
+
+Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h
+===================================================================
+--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h 2009-02-06 15:42:07.000000000 +0100
++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h 2009-02-06 15:42:45.000000000 +0100
+@@ -205,6 +205,7 @@
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V ) /* valid */
+ #define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
++ | OR_FCM_PGS \
+ | OR_FCM_CSCT \
+ | OR_FCM_CST \
+ | OR_FCM_CHT \