linux-2.6.23: add NAND flash driver for mpc8323e-rdb, fix NOR mapping

3 files changed, 1823 insertions, 4 deletions

diff --git a/packages/linux/linux-2.6.23/mpc8313e-rdb/defconfig b/packages/linux/linux-2.6.23/mpc8313e-rdb/defconfig
index 39a8d23638..82ba1ceb9c 100644
--- a/packages/linux/linux-2.6.23/mpc8313e-rdb/defconfig
+++ b/packages/linux/linux-2.6.23/mpc8313e-rdb/defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.23
-# Wed Nov 28 10:52:11 2007
+# Wed Nov 28 19:45:49 2007
 #
 # CONFIG_PPC64 is not set
 
@@ -618,7 +618,7 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_PHYSMAP_START=0xfe000000
-CONFIG_MTD_PHYSMAP_LEN=0x1000000
+CONFIG_MTD_PHYSMAP_LEN=0x0800000
 CONFIG_MTD_PHYSMAP_BANKWIDTH=2
 # CONFIG_MTD_PHYSMAP_OF is not set
 # CONFIG_MTD_PLATRAM is not set
@@ -640,7 +640,16 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_NAND is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+CONFIG_MTD_NAND_FSL_ELBC=y
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
 # CONFIG_MTD_ONENAND is not set
 
 #
diff --git a/packages/linux/linux-2.6.23/mpc8313e-rdb/mpc831x-nand.patch b/packages/linux/linux-2.6.23/mpc8313e-rdb/mpc831x-nand.patch
new file mode 100644
index 0000000000..efff29bca1
--- /dev/null
+++ b/packages/linux/linux-2.6.23/mpc8313e-rdb/mpc831x-nand.patch
@@ -0,0 +1,1807 @@
+diff -urN linux-2.6.23.orig/arch/powerpc/boot/dts/mpc8313erdb.dts linux-2.6.23/arch/powerpc/boot/dts/mpc8313erdb.dts
+--- linux-2.6.23.orig/arch/powerpc/boot/dts/mpc8313erdb.dts	2007-10-09 22:31:38.000000000 +0200
++++ linux-2.6.23/arch/powerpc/boot/dts/mpc8313erdb.dts	2007-11-28 20:36:57.000000000 +0100
+@@ -37,6 +37,12 @@
+ 		device_type = "memory";
+ 		reg = <00000000 08000000>;	// 128MB at 0
+ 	};
++	
++	nand0 {
++		device_type = "nand";
++		compatible = "fsl-nand";
++		reg = <e2800000 00000200>;
++	};
+ 
+ 	soc8313@e0000000 {
+ 		#address-cells = <1>;
+@@ -210,5 +216,15 @@
+ 			built-in;
+ 			device_type = "ipic";
+ 		};
++
++		elbc@5000 {
++			device_type = "elbc";
++			compatible = "fsl-elbc";
++			reg = <5000 1000>;
++			interrupts = <4d 8>;
++			interrupt-parent = < &ipic >;
++			allow-direct-device-sleep;
++		};
++
+ 	};
+ };
+diff -urN linux-2.6.23.orig/arch/powerpc/sysdev/fsl_soc.c linux-2.6.23/arch/powerpc/sysdev/fsl_soc.c
+--- linux-2.6.23.orig/arch/powerpc/sysdev/fsl_soc.c	2007-10-09 22:31:38.000000000 +0200
++++ linux-2.6.23/arch/powerpc/sysdev/fsl_soc.c	2007-11-28 20:36:39.000000000 +0100
+@@ -6,6 +6,12 @@
+  * 2006 (c) MontaVista Software, Inc.
+  * Vitaly Bordug <vbordug@ru.mvista.com>
+  *
++ * Change log:
++ * Copyright (C) 2006 Freescale Semiconductor, Inc.
++ * 2006: Lo Wilson (r43300@freescale.com)
++ *	     Added support for Enhanced Local Bus Controller
++ *	     Added support for USB UTMI mode on-chip PHY
++ *
+  * This program is free software; you can redistribute  it and/or modify it
+  * under  the terms of  the GNU General  Public License as published by the
+  * Free Software Foundation;  either version 2 of the  License, or (at your
+@@ -27,6 +33,8 @@
+ #include <linux/fsl_devices.h>
+ #include <linux/fs_enet_pd.h>
+ #include <linux/fs_uart_pd.h>
++#include <linux/mtd/nand.h>
++#include <linux/mtd/fsl_elbc.h>
+ 
+ #include <asm/system.h>
+ #include <asm/atomic.h>
+@@ -648,6 +656,75 @@
+ 
+ arch_initcall(fsl_usb_of_init);
+ 
++static int __init fsl_elbc_of_init(void)
++{
++	struct device_node *np;
++	unsigned int i;
++	struct platform_device *elbc_dev = NULL;
++	struct platform_device *nand_dev = NULL;
++	int ret;
++
++	/* find and register the enhanced local bus controller */
++	for (np = NULL, i = 0;
++	     (np = of_find_compatible_node(np, "elbc", "fsl-elbc")) != NULL;
++	     i++) {
++		struct resource r[2];
++
++		memset(&r, 0, sizeof(r));
++
++		ret = of_address_to_resource(np, 0, &r[0]);
++		if (ret)
++			goto err;
++
++		r[1].start = r[1].end = irq_of_parse_and_map(np, 0);
++		r[1].flags = IORESOURCE_IRQ;
++
++		elbc_dev =
++		    platform_device_register_simple("fsl-elbc", i, r, 2);
++		if (IS_ERR(elbc_dev)) {
++			ret = PTR_ERR(elbc_dev);
++			goto err;
++		}
++	}
++
++	/* find and register NAND memories if the eLBC was found */
++	for (np = NULL, i = 0;
++	     elbc_dev &&
++	     (np = of_find_compatible_node(np, "nand", "fsl-nand")) != NULL;
++	     i++) {
++		struct resource r;
++		struct platform_fsl_nand_chip chip_data;
++
++		memset(&r, 0, sizeof(r));
++		memset(&chip_data, 0, sizeof(chip_data));
++
++		ret = of_address_to_resource(np, 0, &r);
++		if (ret)
++			goto err;
++
++		nand_dev =
++		    platform_device_register_simple("fsl-nand", i, &r, 1);
++		if (IS_ERR(nand_dev)) {
++			ret = PTR_ERR(nand_dev);
++			goto err;
++		}
++
++		chip_data.name = get_property(np, "name", NULL);
++		chip_data.partitions_str = get_property(np, "partitions", NULL);
++
++		ret = platform_device_add_data(nand_dev, &chip_data,
++					sizeof(struct platform_fsl_nand_chip));
++		if (ret)
++			goto err;
++	}
++	return 0;
++
++err:
++	return ret;
++}
++
++arch_initcall(fsl_elbc_of_init);
++
+ #ifdef CONFIG_CPM2
+ 
+ extern void init_scc_ioports(struct fs_uart_platform_info*);
+diff -urN linux-2.6.23.orig/drivers/mtd/nand/fsl_elbc.c linux-2.6.23/drivers/mtd/nand/fsl_elbc.c
+--- linux-2.6.23.orig/drivers/mtd/nand/fsl_elbc.c	1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.23/drivers/mtd/nand/fsl_elbc.c	2007-11-28 20:36:39.000000000 +0100
+@@ -0,0 +1,1325 @@
++/* linux/drivers/mtd/nand/fsl_elbc.c
++ *
++ * Copyright (C) 2006 Freescale Semiconductor, Inc.
++ *
++ * Freescale Enhanced Local Bus Controller NAND driver
++ *
++ * Author: Nick Spence <Nick.Spence@freescale.com>
++ * Maintainer: Tony Li <Tony.Li@freescale.com>
++ *
++ * Changelog:
++ *      2006-12 Tony Li <Tony.Li@freescale.com>
++ *              Adopt to MPC8313ERDB board
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
++*/
++
++//#ifdef CONFIG_MTD_NAND_DEBUG
++//#define DEBUG
++//#endif
++//#define DEBUG
++
++#include <linux/module.h>
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/string.h>
++#include <linux/ioport.h>
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/device.h>
++#include <linux/fsl_devices.h>
++
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/nand.h>
++#include <linux/mtd/nand_ecc.h>
++#include <linux/mtd/partitions.h>
++
++#include <asm/io.h>
++#include <asm/mpc83xx.h>
++#include <linux/mtd/fsl_elbc.h>
++
++#define PFX "fsl-elbc: "
++
++#undef CFG_FCM_DEBUG
++#define CFG_FCM_DEBUG_LVL 3
++#ifdef CFG_FCM_DEBUG
++static int fcm_debug_level = CFG_FCM_DEBUG_LVL;
++#define FCM_DEBUG(n, args...)			\
++	do {					\
++		if (n <= fcm_debug_level)	\
++			printk(args);		\
++	} while(0)
++#else /* CONFIG_FCM_DEBUG */
++#define FCM_DEBUG(n, args...) do { } while(0)
++#endif
++
++#define FCM_SIZE (8 * 1024)
++
++#define MAX_BANKS (8)
++
++/* use interrupt instead of busy waiting TODO */
++#define FCM_USE_INTERRUPT
++
++#define MIN(x, y)		((x < y) ? x : y)
++
++#define ERR_BYTE 0xFF	/* Value returned for read bytes when read failed */
++
++#define FCM_TIMEOUT_MSECS 100 /* Maximum number of mSecs to wait for FCM */
++
++
++
++struct fsl_elbc_ctrl;
++
++/* mtd information per set */
++
++struct fsl_elbc_mtd {
++	struct mtd_info		mtd;
++	struct nand_chip	chip;
++	struct platform_fsl_nand_chip pl_chip;
++	struct fsl_elbc_ctrl	*ctrl;
++
++	struct device		*device;
++//	int			nr_chips;       /* Number of chips in set    */
++//	int			nr_partitions;  /* Number of partitions or 0 */
++	char			*name;          /* Name of set (optional)    */
++	int			*nr_map;        /* Physical chip num (option)*/
++//	struct mtd_partition	*partitions;    /* MTD partition list (option*/
++//	struct nand_ecclayout   *ecclayout;
++	unsigned int		options;
++	struct resource		*area;
++	int			bank;	/* Chip select bank number           */
++	unsigned int		pbase;	/* Chip select base physical address */
++	unsigned int		vbase;	/* Chip select base virtual address  */
++	int			pgs;	/* NAND page size (0=512, 1=2048)    */
++	unsigned int		fmr;	/* FCM Flash Mode Register value     */
++};
++
++/* overview of the fsl elbc controller */
++
++struct fsl_elbc_ctrl {
++	struct nand_hw_control		controller;
++	struct fsl_elbc_mtd		*nmtd[MAX_BANKS];
++
++	/* device info */
++	atomic_t	childs_active;
++	struct device	*device;
++	struct resource	*area;
++	lbus83xx_t	*regs;
++	int		irq;
++	wait_queue_head_t irq_wait;
++	unsigned int	irq_status; /* status read from LTESR by irq handler */
++	u_char	       *addr;       /* Address of assigned FCM buffer        */
++	unsigned int	page;       /* Last page written to / read from      */
++	unsigned int	read_bytes; /* Number of bytes read during command   */
++	unsigned int	index;      /* Pointer to next byte to 'read'        */
++	unsigned int	status;     /* status read from LTESR after last op  */
++	int		oobbuf;     /* Pointer to OOB block                  */
++	unsigned int	mdr;        /* UPM/FCM Data Register value           */
++	unsigned int	use_mdr;    /* Non zero if the MDR is to be set      */
++};
++
++struct fsl_elbc_ctrl elbc_ctrl;
++
++/* These map to the positions used by the FCM hardware ECC generator */
++
++/* Small Page FLASH with FMR[ECCM] = 0 */
++static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = { /* TODO */
++//TODO	.useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */
++	.eccbytes = 3,
++	.eccpos = {6, 7, 8},
++	.oobfree = { {0, 5}, {9, 7} }
++};
++
++/* Small Page FLASH with FMR[ECCM] = 1 */
++static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = { /* TODO */
++//TODO	.useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */
++	.eccbytes = 3,
++	.eccpos = {8, 9, 10},
++	.oobfree = { {0, 5}, {6, 2}, {11, 5} }
++};
++
++/* Large Page FLASH with FMR[ECCM] = 0 */
++static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
++//TODO	.useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */
++	.eccbytes = 12,
++	.eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
++	.oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} }
++};
++
++/* Large Page FLASH with FMR[ECCM] = 1 */
++static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
++//TODO	.useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */
++	.eccbytes = 12,
++	.eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
++	.oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} }
++};
++
++/*=================================*/
++
++/*
++ * Set up the FCM hardware block and page address fields, and the fcm
++ * structure addr field to point to the correct FCM buffer in memory
++ */
++static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
++{
++	struct nand_chip *chip = mtd->priv;
++	struct fsl_elbc_mtd *nmtd = chip->priv;
++	struct fsl_elbc_ctrl *ctrl = nmtd->ctrl;
++	volatile lbus83xx_t *lbc = ctrl->regs;
++	int buf_num;
++
++	ctrl->page = page_addr;
++
++	lbc->fbar = page_addr >> (chip->phys_erase_shift - chip->page_shift);
++	if (nmtd->pgs) {
++		lbc->fpar = ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
++			    ( oob ? FPAR_LP_MS : 0) |
++			      column;
++		buf_num = (page_addr & 1) << 2;
++	} else {
++		lbc->fpar = ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
++			    ( oob ? FPAR_SP_MS : 0) |
++			      column;
++		buf_num = page_addr & 7;
++	}
++	ctrl->addr = (unsigned char*)(nmtd->vbase + (buf_num * 1024));
++
++	/* for OOB data point to the second half of the buffer */
++	if (oob) {
++		ctrl->addr += (nmtd->pgs ? 2048 : 512);
++	}
++	FCM_DEBUG(2,"set_addr: bank=%d, ctrl->addr=0x%p (0x%08x)\n", buf_num, ctrl->addr, nmtd->vbase);
++}
++
++/*
++ * execute FCM command and wait for it to complete
++ */
++static int fsl_elbc_run_command(struct mtd_info *mtd)
++{
++	struct nand_chip *chip = mtd->priv;
++	struct fsl_elbc_mtd *nmtd = chip->priv;
++	struct fsl_elbc_ctrl *ctrl = nmtd->ctrl;
++	volatile lbus83xx_t *lbc = ctrl->regs;
++	/* Setup the FMR[OP] to execute without write protection */
++	lbc->fmr = nmtd->fmr | 3;
++	if (ctrl->use_mdr)
++		lbc->mdr = ctrl->mdr;
++
++	FCM_DEBUG(5,"fsl_elbc_run_command: fmr= %08X fir= %08X fcr= %08X\n",
++		lbc->fmr, lbc->fir, lbc->fcr);
++	FCM_DEBUG(5,"fsl_elbc_run_command: fbar=%08X fpar=%08X fbcr=%08X bank=%d\n",
++		lbc->fbar, lbc->fpar, lbc->fbcr, nmtd->bank);
++
++	/* clear event registers */
++	lbc->lteatr = 0;
++	lbc->ltesr |= (LTESR_FCT | LTESR_PAR | LTESR_CC);
++
++	/* execute special operation */
++	lbc->lsor = nmtd->bank;
++
++	/* wait for FCM complete flag or timeout */
++/* TODO */
++#ifdef FCM_USE_INTERRUPT
++	ctrl->status = ctrl->irq_status = 0;
++	wait_event_timeout(ctrl->irq_wait, ctrl->irq_status, FCM_TIMEOUT_MSECS * HZ/1000);
++	ctrl->status = ctrl->irq_status;
++#else
++	{
++	unsigned long timeout;
++	unsigned long now;
++	now = jiffies_to_msecs(jiffies);
++	timeout = now + FCM_TIMEOUT_MSECS;
++	while (time_before(now, timeout)) {
++		ctrl->status = lbc->ltesr & (LTESR_FCT | LTESR_PAR | LTESR_CC);
++		if (ctrl->status)
++			break;
++		now = jiffies_to_msecs(jiffies);
++	}
++	}
++#endif
++
++	/* store mdr value in case it was needed */
++	if (ctrl->use_mdr)
++		ctrl->mdr = lbc->mdr;
++
++	ctrl->use_mdr = 0;
++
++	FCM_DEBUG(5,"fsl_elbc_run_command: stat=%08X mdr= %08X fmr= %08X\n",
++		ctrl->status, ctrl->mdr, lbc->fmr);
++
++	/* returns 0 on success otherwise non-zero) */
++	return (ctrl->status == LTESR_CC ? 0 : EFAULT);
++}
++
++/* cmdfunc send commands to the FCM */
++static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned command,
++			int column, int page_addr)
++{
++	struct nand_chip *chip = mtd->priv;
++	struct fsl_elbc_mtd *nmtd = chip->priv;
++	struct fsl_elbc_ctrl *ctrl = nmtd->ctrl;
++	volatile lbus83xx_t *lbc = ctrl->regs;
++
++	ctrl->use_mdr = 0;
++
++	/* clear the read buffer */
++	ctrl->read_bytes = 0;
++	if (command != NAND_CMD_PAGEPROG) {
++		ctrl->index = 0;
++		ctrl->oobbuf = -1;
++	}
++
++	switch (command) {
++	/* READ0 and READ1 read the entire buffer to use hardware ECC */
++	case NAND_CMD_READ1:
++		FCM_DEBUG(2,"fsl_elbc_cmdfunc: NAND_CMD_READ1, page_addr:"
++			    " 0x%x, column: 0x%x.\n", page_addr, column);
++		ctrl->index = column + 256;
++		goto read0;
++	case NAND_CMD_READ0:
++		FCM_DEBUG(2,"fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
++			    " 0x%x, column: 0x%x.\n", page_addr, column);
++		ctrl->index = column;
++read0:
++		if (nmtd->pgs) {
++			lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) |
++				   (FIR_OP_CA  << FIR_OP1_SHIFT) |
++				   (FIR_OP_PA  << FIR_OP2_SHIFT) |
++				   (FIR_OP_CW1 << FIR_OP3_SHIFT) |
++				   (FIR_OP_RBW << FIR_OP4_SHIFT);
++		} else {
++			lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) |
++				   (FIR_OP_CA  << FIR_OP1_SHIFT) |
++				   (FIR_OP_PA  << FIR_OP2_SHIFT) |
++				   (FIR_OP_RBW << FIR_OP3_SHIFT);
++		}
++		lbc->fcr = (NAND_CMD_READ0     << FCR_CMD0_SHIFT) |
++			   (NAND_CMD_READSTART << FCR_CMD1_SHIFT);
++		lbc->fbcr = 0; /* read entire page to enable ECC */
++		set_addr(mtd, 0, page_addr, 0);
++		ctrl->read_bytes = mtd->writesize + mtd->oobsize;
++		goto write_cmd2;
++	/* READOOB read only the OOB becasue no ECC is performed */
++	case NAND_CMD_READOOB:
++		FCM_DEBUG(2,"fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
++			    " 0x%x, column: 0x%x.\n", page_addr, column);
++		if (nmtd->pgs) {
++			lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) |
++				   (FIR_OP_CA  << FIR_OP1_SHIFT) |
++				   (FIR_OP_PA  << FIR_OP2_SHIFT) |
++				   (FIR_OP_CW1 << FIR_OP3_SHIFT) |
++				   (FIR_OP_RBW << FIR_OP4_SHIFT);
++			lbc->fcr = (NAND_CMD_READ0     << FCR_CMD0_SHIFT) |
++				   (NAND_CMD_READSTART << FCR_CMD1_SHIFT);
++		} else {
++			lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) |
++				   (FIR_OP_CA  << FIR_OP1_SHIFT) |
++				   (FIR_OP_PA  << FIR_OP2_SHIFT) |
++				   (FIR_OP_RBW << FIR_OP3_SHIFT);
++			lbc->fcr = (NAND_CMD_READOOB << FCR_CMD0_SHIFT);
++		}
++		lbc->fbcr = mtd->oobsize - column;
++		set_addr(mtd, column, page_addr, 1);
++		ctrl->read_bytes = mtd->oobsize;
++		ctrl->index = column;
++		goto write_cmd2;
++	/* READID must read all 5 possible bytes while CEB is active */
++	case NAND_CMD_READID:
++		FCM_DEBUG(2,"fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
++		lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) |
++			   (FIR_OP_UA  << FIR_OP1_SHIFT) |
++			   (FIR_OP_RBW << FIR_OP2_SHIFT);
++		lbc->fcr = (NAND_CMD_READID << FCR_CMD0_SHIFT);
++		lbc->fbcr = 5; /* 5 bytes for manuf, device and exts */
++		ctrl->use_mdr = 1;
++		ctrl->mdr = 0;
++		goto write_cmd0;
++	/* ERASE1 stores the block and page address */
++	case NAND_CMD_ERASE1:
++		FCM_DEBUG(2,"fsl_elbc_cmdfunc: NAND_CMD_ERASE1, page_addr:"
++			    " 0x%x.\n", page_addr);
++		set_addr(mtd, 0, page_addr, 0);
++		goto end;
++	/* ERASE2 uses the block and page address from ERASE1 */
++	case NAND_CMD_ERASE2:
++		FCM_DEBUG(2,"fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
++		lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) |
++			   (FIR_OP_PA  << FIR_OP1_SHIFT) |
++			   (FIR_OP_CM1 << FIR_OP2_SHIFT);
++		lbc->fcr = (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
++			   (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT);
++		lbc->fbcr = 0;
++		goto write_cmd1;
++	/* SEQIN sets up the addr buffer and all registers except the length */
++	case NAND_CMD_SEQIN:
++		FCM_DEBUG(2,"fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr:"
++			    " 0x%x, column: 0x%x.\n", page_addr, column);
++		if (column == 0) {
++			lbc->fbcr = 0; /* write entire page to enable ECC */
++		} else {
++			lbc->fbcr = 1; /* mark as partial page so no HW ECC */
++		}
++		if (nmtd->pgs) {
++			/* always use READ0 for large page devices */
++			lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) |
++				   (FIR_OP_CA  << FIR_OP1_SHIFT) |
++				   (FIR_OP_PA  << FIR_OP2_SHIFT) |
++				   (FIR_OP_WB  << FIR_OP3_SHIFT) |
++				   (FIR_OP_CW1 << FIR_OP4_SHIFT);
++			lbc->fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) |
++				   (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT);
++			set_addr(mtd, column, page_addr, 0);
++		} else {
++			lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) |
++				   (FIR_OP_CM2 << FIR_OP1_SHIFT) |
++				   (FIR_OP_CA  << FIR_OP2_SHIFT) |
++				   (FIR_OP_PA  << FIR_OP3_SHIFT) |
++				   (FIR_OP_WB  << FIR_OP4_SHIFT) |
++				   (FIR_OP_CW1 << FIR_OP5_SHIFT);
++			if (column >= mtd->writesize) {
++				/* OOB area --> READOOB */
++				column -= mtd->writesize;
++				lbc->fcr = (NAND_CMD_READOOB << FCR_CMD0_SHIFT)
++					 | (NAND_CMD_PAGEPROG<< FCR_CMD1_SHIFT)
++					 | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
++				set_addr(mtd, column, page_addr, 1);
++			} else if (column < 256) {
++				/* First 256 bytes --> READ0 */
++				lbc->fcr = (NAND_CMD_READ0 << FCR_CMD0_SHIFT)
++					 | (NAND_CMD_PAGEPROG<< FCR_CMD1_SHIFT)
++					 | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
++				set_addr(mtd, column, page_addr, 0);
++			} else {
++				/* Second 256 bytes --> READ1 */
++				column -= 256;
++				lbc->fcr = (NAND_CMD_READ1 << FCR_CMD0_SHIFT)
++					 | (NAND_CMD_PAGEPROG<< FCR_CMD1_SHIFT)
++					 | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
++				set_addr(mtd, column, page_addr, 0);
++			}
++		}
++		goto end;
++	/* PAGEPROG reuses all of the setup from SEQIN and adds the length */
++	case NAND_CMD_PAGEPROG:
++		FCM_DEBUG(2,"fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG"
++			    " writing %d bytes.\n",ctrl->index);
++		/* if the write did not start at 0 or is not a full page */
++		/* then set the exact length, otherwise use a full page  */
++		/* write so the HW generates the ECC. */
++		if (lbc->fbcr ||
++		   (ctrl->index != (mtd->writesize + mtd->oobsize)))
++			lbc->fbcr = ctrl->index;
++		goto write_cmd2;
++	/* CMD_STATUS must read the status byte while CEB is active */
++	/* Note - it does not wait for the ready line */
++	case NAND_CMD_STATUS:
++		FCM_DEBUG(2,"fsl_elbc_cmdfunc: NAND_CMD_STATUS.\n");
++		lbc->fir = (FIR_OP_CM0 << FIR_OP0_SHIFT) |
++			   (FIR_OP_RBW << FIR_OP1_SHIFT);
++		lbc->fcr = (NAND_CMD_STATUS << FCR_CMD0_SHIFT);
++		lbc->fbcr = 1;
++		goto write_cmd0;
++	/* RESET without waiting for the ready line */
++	case NAND_CMD_RESET:
++		FCM_DEBUG(2,"fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
++		lbc->fir = (FIR_OP_CM0 << FIR_OP0_SHIFT);
++		lbc->fcr = (NAND_CMD_RESET << FCR_CMD0_SHIFT);
++		lbc->fbcr = 0;
++		goto write_cmd0;
++	default:
++		printk("fsl_elbc_cmdfunc: error, unsupported command.\n");
++		goto end;
++	}
++
++	/* Short cuts fall through to save code */
++ write_cmd0:
++	set_addr(mtd, 0, 0, 0);
++ write_cmd1:
++	ctrl->read_bytes = lbc->fbcr;
++ write_cmd2:
++	fsl_elbc_run_command(mtd);
++
++#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
++	/* if we wrote a page then read back the oob to get the ECC */
++	if ((command == NAND_CMD_PAGEPROG) &&
++	    (chip->ecc.mode > NAND_ECC_SOFT) &&
++	    (lbc->fbcr == 0) &&
++	    (ctrl->oobbuf != 0) &&
++	    (ctrl->oobbuf != -1)) {
++		int i;
++		uint *oob_config;
++		unsigned char *oob_buf;
++
++		i = ctrl->page;
++		oob_buf = (unsigned char*) ctrl->oobbuf;
++		oob_config = chip->ecc.layout->eccpos;
++
++		/* wait for the write to complete and check it passed */
++		if (!(chip->waitfunc(mtd, chip) & 0x01)) {
++			/* read back the OOB */
++			fsl_elbc_cmdfunc(mtd, NAND_CMD_READOOB, 0, i);
++			/* if it succeeded then copy the ECC bytes */
++			if (ctrl->status == LTESR_CC) {
++				for (i=0; i < chip->ecc.layout->eccbytes; i++) {
++					oob_buf[oob_config[i]] =
++						ctrl->addr[oob_config[i]];
++				}
++			}
++		}
++	}
++#endif
++
++ end:
++	return;
++}
++
++/* select chip */
++
++static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
++{
++}
++
++/* fsl_elbc_cmd_ctrl
++ *
++ * Issue command and address cycles to the chip
++*/
++
++static void fsl_elbc_cmd_ctrl(struct mtd_info *mtd, int dat,
++				    unsigned int ctrl)
++{
++}
++
++/* fsl_elbc_dev_ready()
++ *
++ * returns 0 if the nand is busy, 1 if it is ready
++*/
++
++static int fsl_elbc_dev_ready(struct mtd_info *mtd)
++{
++	return 0;
++}
++
++/*
++ * FCM does not support 16 bit data busses
++ */
++static u16 fsl_elbc_read_word(struct mtd_info *mtd)
++{
++	struct nand_chip *chip = mtd->priv;
++	struct fsl_elbc_ctrl *ctrl = (struct fsl_elbc_ctrl *) chip->controller;
++
++	dev_err(ctrl->device, "fsl_elbc_read_word: UNIMPLEMENTED.\n");
++	return 0;
++}
++
++/*
++ * Write buf to the FCM Controller Data Buffer
++ */
++static void fsl_elbc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
++{
++	struct nand_chip *chip = mtd->priv;
++	struct fsl_elbc_mtd *nmtd = chip->priv;
++	struct fsl_elbc_ctrl *ctrl = nmtd->ctrl;
++
++	FCM_DEBUG(3,"fsl_elbc_write_buf: writing %d bytes starting with 0x%lx"
++		    " at %d.\n", len, *((unsigned long*) buf), ctrl->index);
++
++	/* If armed catch the address of the OOB buffer so that it can be */
++	/* updated with the real signature after the program comletes */
++	if (!ctrl->oobbuf)
++		ctrl->oobbuf = (int) buf;
++
++	/* copy the data into the FCM hardware buffer and update the index */
++	memcpy(&(ctrl->addr[ctrl->index]), buf, len);
++	ctrl->index += len;
++	return;
++}
++
++
++/*
++ * read a byte from either the FCM hardware buffer if it has any data left
++ * otherwise issue a command to read a single byte.
++ */
++static u_char fsl_elbc_read_byte(struct mtd_info *mtd)
++{
++	struct nand_chip *chip = mtd->priv;
++	struct fsl_elbc_mtd *nmtd = chip->priv;
++	struct fsl_elbc_ctrl *ctrl = nmtd->ctrl;
++	volatile lbus83xx_t *lbc = ctrl->regs;
++	unsigned char byte;
++
++	/* If there are still bytes in the FCM then use the next byte */
++	if(ctrl->index < ctrl->read_bytes) {
++		byte = ctrl->addr[(ctrl->index)++];
++		FCM_DEBUG(4,"fsl_elbc_read_byte: byte %u (%02X): %d of %d.\n",
++			  byte, byte, ctrl->index-1, ctrl->read_bytes);
++	} else {
++		/* otherwise issue a command to read 1 byte */
++		lbc->fir = (FIR_OP_RSW << FIR_OP0_SHIFT);
++		ctrl->use_mdr = 1;
++		ctrl->read_bytes = 0;
++		ctrl->index = 0;
++		ctrl->read_bytes = 0;
++		ctrl->index = 0;
++		byte = fsl_elbc_run_command(mtd) ? ERR_BYTE : ctrl->mdr & 0xff;
++		FCM_DEBUG(4,"fsl_elbc_read_byte: byte %u (%02X) from bus.\n",
++			  byte, byte);
++	}
++
++	return byte;
++}
++
++/*
++ * Read from the FCM Controller Data Buffer
++ */
++static void fsl_elbc_read_buf(struct mtd_info *mtd, u_char* buf, int len)
++{
++	struct nand_chip *chip = mtd->priv;
++	struct fsl_elbc_mtd *nmtd = chip->priv;
++	struct fsl_elbc_ctrl *ctrl = nmtd->ctrl;
++	int i;
++	int rest;
++	unsigned long old_status;
++
++	FCM_DEBUG(3,"fsl_elbc_read_buf: reading %d bytes.\n", len);
++
++	/* see how much is still in the FCM buffer */
++	i = min((unsigned int)len, (ctrl->read_bytes - ctrl->index));
++	rest = len - i;
++	len = i;
++
++	/* copying bytes even if there was an error so that the oob works */
++	memcpy(buf, &(ctrl->addr[(ctrl->index)]), len);
++	ctrl->index += len;
++
++	/* If more data is needed then issue another block read */
++	if (rest) {
++		FCM_DEBUG(3,"fsl_elbc_read_buf: getting %d more bytes.\n",
++			    rest);
++
++		buf += len;
++
++		/* keep last status in case it was an error */
++		old_status = ctrl->status;
++
++		/* read full next page to use HW ECC if enabled */
++		fsl_elbc_cmdfunc(mtd, NAND_CMD_READ0, 0, ctrl->page + 1);
++
++		/* preserve the worst status code */
++		if (ctrl->status == LTESR_CC)
++			ctrl->status = old_status;
++
++		fsl_elbc_read_buf(mtd, buf, rest);
++	}
++	return;
++}
++
++
++/*
++ * Verify buffer against the FCM Controller Data Buffer
++ */
++static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
++{
++	struct nand_chip *chip = mtd->priv;
++	struct fsl_elbc_mtd *nmtd = chip->priv;
++	struct fsl_elbc_ctrl *ctrl = nmtd->ctrl;
++	int i;
++	int rest;
++
++	FCM_DEBUG(3,"fsl_elbc_verify_buf: checking %d bytes starting with 0x%02lx.\n",
++		len, *((unsigned long*) buf));
++
++	/* If last read failed then return error bytes */
++	if (ctrl->status != LTESR_CC) {
++		return EFAULT;
++	}
++
++	/* see how much is still in the FCM buffer */
++	i = min((unsigned int)len, (ctrl->read_bytes - ctrl->index));
++	rest = len - i;
++	len = i;
++
++	if (memcmp(buf,	&(ctrl->addr[(ctrl->index)]), len)) {
++		return EFAULT;
++	}
++
++	ctrl->index += len;
++	if (rest) {
++		FCM_DEBUG(3,"fsl_elbc_verify_buf: getting %d more bytes.\n", rest);
++		buf += len;
++
++		/* read full next page to use HW ECC if enabled */
++		fsl_elbc_cmdfunc(mtd, NAND_CMD_READ0, 0, ctrl->page + 1);
++
++		return fsl_elbc_verify_buf(mtd, buf, rest);
++	}
++	return 0;
++}
++
++/* this function is called after Program and Erase Operations to
++ * check for success or failure */
++static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *this)
++{
++	struct nand_chip *chip = mtd->priv;
++	struct fsl_elbc_mtd *nmtd = chip->priv;
++	struct fsl_elbc_ctrl *ctrl = nmtd->ctrl;
++	volatile lbus83xx_t *lbc = ctrl->regs;
++
++	if (ctrl->status != LTESR_CC) {
++		return(0x1); /* Status Read error */
++	}
++
++	/* Use READ_STATUS command, but wait for the device to be ready */
++	ctrl->use_mdr = 0;
++	ctrl->oobbuf = -1;
++	lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) |
++		   (FIR_OP_RBW << FIR_OP1_SHIFT);
++	lbc->fcr = (NAND_CMD_STATUS << FCR_CMD0_SHIFT);
++	set_addr(mtd, 0, 0, 0);
++	lbc->fbcr = 1;
++	ctrl->index = 0;
++	ctrl->read_bytes = lbc->fbcr;
++	fsl_elbc_run_command(mtd);
++	if (ctrl->status != LTESR_CC) {
++		return(0x1); /* Status Read error */
++	}
++	return chip->read_byte(mtd);
++}
++
++/* ECC handling functions */
++
++/*
++ * fsl_elbc_enable_hwecc - start ECC generation
++ */
++static void fsl_elbc_enable_hwecc(struct mtd_info *mtd, int mode)
++{
++	return;
++}
++
++/*
++ * fsl_elbc_calculate_ecc - Calculate the ECC bytes
++ * This is done by hardware during the write process, so we use this
++ * to arm the oob buf capture on the next write_buf() call. The ECC bytes
++ * only need to be captured if CONFIG_MTD_NAND_VERIFY_WRITE is defined which
++ * reads back the pages and checks they match the data and oob buffers.
++ */
++static int fsl_elbc_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
++{
++#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
++	struct nand_chip *chip = mtd->priv;
++	struct fsl_elbc_mtd *nmtd = chip->priv;
++	struct fsl_elbc_ctrl *ctrl = nmtd->ctrl;
++
++	/* arm capture of oob buf ptr on next write_buf */
++	ctrl->oobbuf = 0;
++#endif
++	return 0;
++}
++
++/*
++ * fsl_elbc_correct_data - Detect and correct bit error(s)
++ * The detection and correction is done automatically by the hardware,
++ * if the complete page was read. If the status code is okay then there
++ * was no error, otherwise we return an error code indicating an uncorrectable
++ * error.
++ */
++static int fsl_elbc_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
++{
++	struct nand_chip *chip = mtd->priv;
++	struct fsl_elbc_mtd *nmtd = chip->priv;
++	struct fsl_elbc_ctrl *ctrl = nmtd->ctrl;
++
++	/* No errors */
++	if (ctrl->status == LTESR_CC)
++		return 0;
++
++	return -1; /* uncorrectable error */
++}
++
++/*************************************************************************/
++/*                     Chip setup and control functions                  */
++/*************************************************************************/
++
++/*
++ * Dummy scan_bbt to complete setup of the FMR based on NAND size
++ */
++static int fsl_elbc_chip_init_tail (struct mtd_info *mtd)
++{
++	struct nand_chip *chip = mtd->priv;
++	struct fsl_elbc_mtd *nmtd = chip->priv;
++	struct fsl_elbc_ctrl *ctrl = nmtd->ctrl;
++	volatile lbus83xx_t *lbc = ctrl->regs;
++	unsigned int i;
++	unsigned int al;
++
++	/* calculate FMR Address Length field */
++	al = 0;
++	for (i = chip->pagemask >> 16; i ; i >>= 8) {
++		al++;
++	}
++
++	/* add to ECCM mode set in fsl_elbc_init */
++	nmtd->fmr |= 12 << FMR_CWTO_SHIFT |  /* Timeout > 12 mSecs */
++		     al << FMR_AL_SHIFT;
++
++	FCM_DEBUG(1,"fsl_elbc_init: nand->options  =   %08X\n", chip->options);
++	FCM_DEBUG(1,"fsl_elbc_init: nand->numchips = %10d\n", chip->numchips);
++	FCM_DEBUG(1,"fsl_elbc_init: nand->chipsize = %10ld\n", chip->chipsize);
++	FCM_DEBUG(1,"fsl_elbc_init: nand->pagemask = %10X\n", chip->pagemask);
++	FCM_DEBUG(1,"fsl_elbc_init: nand->chip_delay = %8d\n", chip->chip_delay);
++	FCM_DEBUG(1,"fsl_elbc_init: nand->badblockpos = %7d\n", chip->badblockpos);
++	FCM_DEBUG(1,"fsl_elbc_init: nand->chip_shift = %8d\n", chip->chip_shift);
++	FCM_DEBUG(1,"fsl_elbc_init: nand->page_shift = %8d\n", chip->page_shift);
++	FCM_DEBUG(1,"fsl_elbc_init: nand->phys_erase_shift = %2d\n",
++						      chip->phys_erase_shift);
++	FCM_DEBUG(1,"fsl_elbc_init: nand->ecclayout= %10p\n", chip->ecclayout);
++	FCM_DEBUG(1,"fsl_elbc_init: nand->eccmode  = %10d\n", chip->ecc.mode );
++	FCM_DEBUG(1,"fsl_elbc_init: nand->eccsteps = %10d\n", chip->ecc.steps);
++	FCM_DEBUG(1,"fsl_elbc_init: nand->eccsize  = %10d\n", chip->ecc.size );
++	FCM_DEBUG(1,"fsl_elbc_init: nand->eccbytes = %10d\n", chip->ecc.bytes);
++	FCM_DEBUG(1,"fsl_elbc_init: nand->ecctotal = %10d\n", chip->ecc.total);
++	FCM_DEBUG(1,"fsl_elbc_init: nand->ecclayout= %10p\n", chip->ecc.layout);
++	FCM_DEBUG(1,"fsl_elbc_init: mtd->flags     =   %08X\n", mtd->flags);
++	FCM_DEBUG(1,"fsl_elbc_init: mtd->size      = %10d\n", mtd->size);
++	FCM_DEBUG(1,"fsl_elbc_init: mtd->erasesize = %10d\n", mtd->erasesize);
++	FCM_DEBUG(1,"fsl_elbc_init: mtd->writesize = %10d\n", mtd->writesize);
++	FCM_DEBUG(1,"fsl_elbc_init: mtd->oobsize   = %10d\n", mtd->oobsize);
++	FCM_DEBUG(1,"fsl_elbc_init: mtd->ecctype   = %10d\n", mtd->ecctype);
++	FCM_DEBUG(1,"fsl_elbc_init: mtd->eccsize   = %10d\n", mtd->eccsize);
++
++	/* adjust Option Register and ECC to match Flash page size */
++	if (mtd->writesize == 512)
++		lbc->bank[nmtd->bank].or &= ~(OR_FCM_PGS);
++	else if (mtd->writesize == 2048) {
++		lbc->bank[nmtd->bank].or |= OR_FCM_PGS;
++		/* adjust ecc setup if needed */
++		if ( (lbc->bank[nmtd->bank].br & BR_DECC) == BR_DECC_CHK_GEN) {
++			chip->ecc.size = 2048;
++			chip->ecc.steps = 1;
++//TODO			chip->ecc.bytes += 9;
++//TODO			chip->ecc.total += 9;
++			chip->ecc.layout = (nmtd->fmr & FMR_ECCM) ?
++					&fsl_elbc_oob_lp_eccm1 : &fsl_elbc_oob_lp_eccm0;
++			mtd->ecclayout = chip->ecc.layout;
++		}
++	}
++	else {
++		printk("fsl_elbc_init: page size %d is not supported\n",
++			mtd->writesize);
++		return -1;
++	}
++	nmtd->pgs = (lbc->bank[nmtd->bank].or>>OR_FCM_PGS_SHIFT) & 1;
++
++	/* fix up the oobavail size in case the layout was changed */
++	chip->ecc.layout->oobavail = 0;
++	for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
++		chip->ecc.layout->oobavail +=
++			chip->ecc.layout->oobfree[i].length;
++
++	/* return to the default bbt_scan_routine */