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| author | Stelios Koroneos <skoroneos@digital-opsis.com> | 2008-05-04 21:26:34 +0000 |
|---|---|---|
| committer | Stelios Koroneos <skoroneos@digital-opsis.com> | 2008-05-04 21:26:34 +0000 |
| commit | db61d94094937dfc3504e15424c099f4a608acf3 (patch) | |
| tree | 1fd2f1d6a231adea9ef15377e856b59ae100f922 /packages/linux/linux-omap2-git/beagleboard/l2-cache.patch | |
| parent | 0eb94e44bd4b64ad754d8c837d512e7000abd016 (diff) | |
| parent | 1c67f708c41671468cdf2489d267d79ec30d5507 (diff) | |
propagate from branch 'org.openembedded.oplinux' (head d9363ecbe581bf473057c4e79b0a93b7487d52e9)
to branch 'org.openembedded.dev' (head e6f495f12f6c3af3e3758acd3b907f88e88523ae)
Diffstat (limited to 'packages/linux/linux-omap2-git/beagleboard/l2-cache.patch')
| -rw-r--r-- | packages/linux/linux-omap2-git/beagleboard/l2-cache.patch | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/packages/linux/linux-omap2-git/beagleboard/l2-cache.patch b/packages/linux/linux-omap2-git/beagleboard/l2-cache.patch new file mode 100644 index 0000000000..7e93c29036 --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/l2-cache.patch @@ -0,0 +1,38 @@ +diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig +index 15066c2..70f85c1 100644 +--- a/arch/arm/mm/Kconfig ++++ b/arch/arm/mm/Kconfig +@@ -665,6 +665,12 @@ config CPU_CACHE_ROUND_ROBIN + Say Y here to use the predictable round-robin cache replacement + policy. Unless you specifically require this or are unsure, say N. + ++config CPU_L2CACHE_DISABLE ++ bool "Disable level 2 cache" ++ depends on CPU_V7 ++ help ++ Say Y here to disable the level 2 cache. If unsure, say N. ++ + config CPU_BPREDICT_DISABLE + bool "Disable branch prediction" + depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7 +diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S +index a1d7331..432ddab 100644 +--- a/arch/arm/mm/proc-v7.S ++++ b/arch/arm/mm/proc-v7.S +@@ -181,6 +181,16 @@ __v7_setup: + mcr p15, 0, r4, c2, c0, 1 @ load TTB1 + mov r10, #0x1f @ domains 0, 1 = manager + mcr p15, 0, r10, c3, c0, 0 @ load domain access register ++#ifndef CONFIG_CPU_L2CACHE_DISABLE ++ @ L2 cache configuration in the L2 aux control register ++ mrc p15, 1, r10, c9, c0, 2 ++ bic r10, r10, #(1 << 16) @ L2 outer cache ++ mcr p15, 1, r10, c9, c0, 2 ++ @ L2 cache is enabled in the aux control register ++ mrc p15, 0, r10, c1, c0, 1 ++ orr r10, r10, #2 ++ mcr p15, 0, r10, c1, c0, 1 ++#endif + #endif + adr r5, v7_crval + ldmia r5, {r5, r6} |