rename packages/ to recipes/ per earlier agreement

See links below for more details:
http://thread.gmane.org/gmane.comp.handhelds.openembedded/21326
http://thread.gmane.org/gmane.comp.handhelds.openembedded/21816

Signed-off-by: Denys Dmytriyenko <denis@denix.org>
Acked-by: Mike Westerhof <mwester@dls.net>
Acked-by: Philip Balister <philip@balister.org>
Acked-by: Khem Raj <raj.khem@gmail.com>
Acked-by: Marcin Juszkiewicz <hrw@openembedded.org>
Acked-by: Koen Kooi <koen@openembedded.org>
Acked-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>

1 files changed, 0 insertions, 464 deletions

diff --git a/packages/linux/linux-efika-2.6.20/0022-MPC52xx-PCI-now-working-on-lite5200.-ugly-but-working.txt b/packages/linux/linux-efika-2.6.20/0022-MPC52xx-PCI-now-working-on-lite5200.-ugly-but-working.txt
deleted file mode 100644
index dbf61629fc..0000000000
--- a/packages/linux/linux-efika-2.6.20/0022-MPC52xx-PCI-now-working-on-lite5200.-ugly-but-working.txt
+++ /dev/null
@@ -1,464 +0,0 @@
-From c4c2f5cb57335b1b47aa8007b0cfce48cc46fa06 Mon Sep 17 00:00:00 2001
-From: Grant Likely <grant.likely@secretlab.ca>
-Date: Tue, 21 Nov 2006 14:41:59 -0700
-Subject: [PATCH] [MPC52xx] PCI now working on lite5200... ugly, but working
-
-Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
----
- arch/powerpc/platforms/52xx/mpc52xx_pci.c |  334 +++++++++++++++++++++++++++++
- arch/powerpc/platforms/52xx/mpc52xx_pci.h |  104 +++++++++
- 2 files changed, 438 insertions(+), 0 deletions(-)
-
-diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pci.c b/arch/powerpc/platforms/52xx/mpc52xx_pci.c
-new file mode 100644
-index 0000000..07dce3c
---- /dev/null
-+++ b/arch/powerpc/platforms/52xx/mpc52xx_pci.c
-@@ -0,0 +1,334 @@
-+/*
-+ * PCI code for the Freescale MPC52xx embedded CPU.
-+ *
-+ * Copyright (C) 2004 Secret Lab Technologies Ltd.
-+ *                        Grant Likely <grant.likely@secretlab.ca>
-+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
-+ *
-+ * This file is licensed under the terms of the GNU General Public License
-+ * version 2. This program is licensed "as is" without any warranty of any
-+ * kind, whether express or implied.
-+ */
-+
-+#define DEBUG
-+
-+#include <asm/pci.h>
-+#include <asm/mpc52xx.h>
-+#include "mpc52xx_pci.h"
-+#include <asm/delay.h>
-+#include <asm/machdep.h>
-+#include <linux/kernel.h>
-+
-+
-+/* This macro is defined to activate the workaround for the bug
-+   435 of the MPC5200 (L25R). With it activated, we don't do any
-+   32 bits configuration access during type-1 cycles */
-+#define MPC5200_BUG_435_WORKAROUND
-+
-+
-+static int
-+mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
-+				int offset, int len, u32 *val)
-+{
-+	struct pci_controller *hose = bus->sysdata;
-+	u32 value;
-+
-+	if (ppc_md.pci_exclude_device)
-+		if (ppc_md.pci_exclude_device(bus->number, devfn))
-+			return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	out_be32(hose->cfg_addr,
-+		(1 << 31) |
-+		((bus->number - hose->bus_offset) << 16) |
-+		(devfn << 8) |
-+		(offset & 0xfc));
-+	mb();
-+
-+#ifdef MPC5200_BUG_435_WORKAROUND
-+	if (bus->number != hose->bus_offset) {
-+		switch (len) {
-+		      case 1:
-+			value = in_8(((u8 __iomem *)hose->cfg_data) +
-+			             (offset & 3));
-+			break;
-+		      case 2:
-+			value = in_le16(((u16 __iomem *)hose->cfg_data) +
-+			                ((offset>>1) & 1));
-+			break;
-+
-+		      default:
-+			value = in_le16((u16 __iomem *)hose->cfg_data) |
-+				(in_le16(((u16 __iomem *)hose->cfg_data) + 1) << 16);
-+			break;
-+		}
-+	}
-+	else
-+#endif
-+	{
-+		value = in_le32(hose->cfg_data);
-+
-+		if (len != 4) {
-+			value >>= ((offset & 0x3) << 3);
-+			value &= 0xffffffff >> (32 - (len << 3));
-+		}
-+	}
-+
-+	*val = value;
-+
-+	out_be32(hose->cfg_addr, 0);
-+	mb();
-+
-+	return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int
-+mpc52xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
-+				int offset, int len, u32 val)
-+{
-+	struct pci_controller *hose = bus->sysdata;
-+	u32 value, mask;
-+
-+	if (ppc_md.pci_exclude_device)
-+		if (ppc_md.pci_exclude_device(bus->number, devfn))
-+			return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+	out_be32(hose->cfg_addr,
-+		(1 << 31) |
-+		((bus->number - hose->bus_offset) << 16) |
-+		(devfn << 8) |
-+		(offset & 0xfc));
-+	mb();
-+
-+#ifdef MPC5200_BUG_435_WORKAROUND
-+	if (bus->number != hose->bus_offset) {
-+		switch (len) {
-+		      case 1:
-+			out_8(((u8 __iomem *)hose->cfg_data) +
-+				(offset & 3), val);
-+			break;
-+		      case 2:
-+			out_le16(((u16 __iomem *)hose->cfg_data) +
-+				((offset>>1) & 1), val);
-+			break;
-+
-+		      default:
-+			out_le16((u16 __iomem *)hose->cfg_data,
-+				(u16)val);
-+			out_le16(((u16 __iomem *)hose->cfg_data) + 1,
-+				(u16)(val>>16));
-+			break;
-+		}
-+	}
-+	else
-+#endif
-+	{
-+		if (len != 4) {
-+			value = in_le32(hose->cfg_data);
-+
-+			offset = (offset & 0x3) << 3;
-+			mask = (0xffffffff >> (32 - (len << 3)));
-+			mask <<= offset;
-+
-+			value &= ~mask;
-+			val = value | ((val << offset) & mask);
-+		}
-+
-+		out_le32(hose->cfg_data, val);
-+	}
-+	mb();
-+
-+	out_be32(hose->cfg_addr, 0);
-+	mb();
-+
-+	return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static struct pci_ops mpc52xx_pci_ops = {
-+	.read  = mpc52xx_pci_read_config,
-+	.write = mpc52xx_pci_write_config
-+};
-+
-+
-+static void __init
-+mpc52xx_pci_setup(struct pci_controller *hose,
-+                  struct mpc52xx_pci __iomem *pci_regs)
-+{
-+	struct resource *res;
-+	u32 tmp;
-+	int iwcr0 = 0, iwcr1 = 0, iwcr2 = 0;
-+
-+	pr_debug("mpc52xx_pci_setup()\n");
-+
-+	pr_debug("iw0btar=%x iw1btar=%x iw2btar=%x iwcr=%x\n",
-+	         in_be32(&pci_regs->iw0btar), in_be32(&pci_regs->iw1btar),
-+	         in_be32(&pci_regs->iw2btar), in_be32(&pci_regs->iwcr));
-+	pr_debug("tbatr0=%x tbatr1=%x tcr=%x gscr=%x\n",
-+	         in_be32(&pci_regs->tbatr0), in_be32(&pci_regs->tbatr1),
-+	         in_be32(&pci_regs->tcr), in_be32(&pci_regs->gscr));
-+
-+	/* Setup control regs */
-+	tmp = in_be32(&pci_regs->scr);
-+	tmp |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-+	out_be32(&pci_regs->scr, tmp);
-+
-+	/* Setup windows */
-+	res = &hose->mem_resources[0];
-+	if (res->flags) {
-+		pr_debug("mem_resource[0] = {.start=%x, .end=%x, .flags=%lx}\n",
-+		         res->start, res->end, res->flags);
-+		out_be32(&pci_regs->iw0btar,
-+		         MPC52xx_PCI_IWBTAR_TRANSLATION(res->start, res->start,
-+		                  res->end - res->start + 1));
-+		iwcr0 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_MEM;
-+		if (res->flags & IORESOURCE_PREFETCH)
-+			iwcr0 |= MPC52xx_PCI_IWCR_READ_MULTI;
-+		else
-+			iwcr0 |= MPC52xx_PCI_IWCR_READ;
-+	}
-+
-+	res = &hose->mem_resources[1];
-+	if (res->flags) {
-+		pr_debug("mem_resource[1] = {.start=%x, .end=%x, .flags=%lx}\n",
-+		         res->start, res->end, res->flags);
-+		out_be32(&pci_regs->iw1btar,
-+		         MPC52xx_PCI_IWBTAR_TRANSLATION(res->start, res->start,
-+		                  res->end - res->start + 1));
-+		iwcr1 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_MEM;
-+		if (res->flags & IORESOURCE_PREFETCH)
-+			iwcr1 |= MPC52xx_PCI_IWCR_READ_MULTI;
-+		else
-+			iwcr1 |= MPC52xx_PCI_IWCR_READ;
-+	}
-+
-+	res = &hose->io_resource;
-+	if (!res) {
-+		printk(KERN_ERR "%s: Didn't find IO resources\n", __FILE__);
-+		return;
-+	}
-+	pr_debug(".io_resource={.start=%x,.end=%x,.flags=%lx} "
-+	         ".io_base_phys=%lx\n",
-+	         res->start, res->end, res->flags, hose->io_base_phys);
-+	out_be32(&pci_regs->iw2btar,
-+	         MPC52xx_PCI_IWBTAR_TRANSLATION(hose->io_base_phys,
-+	                                        res->start,
-+	                                        res->end - res->start + 1));
-+	iwcr2 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_IO;
-+
-+	pr_debug("iwcr0=%x iwcr1=%x iwcr2=%x iwcr=%x old_iwcr=%x\n",
-+		 iwcr0, iwcr1, iwcr2,
-+		 MPC52xx_PCI_IWCR_PACK(iwcr0, iwcr1, iwcr2),
-+		 in_be32(&pci_regs->iwcr));
-+	out_be32(&pci_regs->iwcr, MPC52xx_PCI_IWCR_PACK(iwcr0, iwcr1, iwcr2));
-+
-+	out_be32(&pci_regs->tbatr0,
-+		MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_IO );
-+	out_be32(&pci_regs->tbatr1,
-+		MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_MEM );
-+
-+	out_be32(&pci_regs->tcr, MPC52xx_PCI_TCR_LD);
-+
-+	/* Reset the exteral bus ( internal PCI controller is NOT resetted ) */
-+	/* Not necessary and can be a bad thing if for example the bootloader
-+	   is displaying a splash screen or ... Just left here for
-+	   documentation purpose if anyone need it */
-+	tmp = in_be32(&pci_regs->gscr);
-+#if 0
-+	out_be32(&pci_regs->gscr, tmp | MPC52xx_PCI_GSCR_PR);
-+	udelay(50);
-+#endif
-+	out_be32(&pci_regs->gscr, tmp & ~MPC52xx_PCI_GSCR_PR);
-+
-+	pr_debug("iw0btar=%x iw1btar=%x iw2btar=%x iwcr=%x\n",
-+	         in_be32(&pci_regs->iw0btar), in_be32(&pci_regs->iw1btar),
-+	         in_be32(&pci_regs->iw2btar), in_be32(&pci_regs->iwcr));
-+	pr_debug("tbatr0=%x tbatr1=%x tcr=%x gscr=%x\n",
-+	         in_be32(&pci_regs->tbatr0), in_be32(&pci_regs->tbatr1),
-+	         in_be32(&pci_regs->tcr), in_be32(&pci_regs->gscr));
-+}
-+
-+static void
-+mpc52xx_pci_fixup_resources(struct pci_dev *dev)
-+{
-+	int i;
-+
-+	pr_debug("mpc52xx_pci_fixup_resources() %.4x:%.4x\n",
-+	         dev->vendor, dev->device);
-+
-+	/* We don't rely on boot loader for PCI and resets all
-+	   devices */
-+	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
-+		struct resource *res = &dev->resource[i];
-+		if (res->end > res->start) {	/* Only valid resources */
-+			res->end -= res->start;
-+			res->start = 0;
-+			res->flags |= IORESOURCE_UNSET;
-+		}
-+	}
-+
-+	/* The PCI Host bridge of MPC52xx has a prefetch memory resource
-+	   fixed to 1Gb. Doesn't fit in the resource system so we remove it */
-+	if ( (dev->vendor == PCI_VENDOR_ID_MOTOROLA) &&
-+	     (   dev->device == PCI_DEVICE_ID_MOTOROLA_MPC5200
-+	      || dev->device == PCI_DEVICE_ID_MOTOROLA_MPC5200B) ) {
-+		struct resource *res = &dev->resource[1];
-+		res->start = res->end = res->flags = 0;
-+	}
-+}
-+
-+int __init
-+mpc52xx_add_bridge(struct device_node *node)
-+{
-+	int len;
-+	struct mpc52xx_pci __iomem *pci_regs;
-+	struct pci_controller *hose;
-+	const int *bus_range;
-+	struct resource rsrc;
-+
-+	pr_debug("Adding PCI host bridge %s\n", node->full_name);
-+
-+	pci_assign_all_buses = 1;
-+
-+	if (of_address_to_resource(node, 0, &rsrc) != 0) {
-+		printk(KERN_ERR "Can't get %s resources\n", node->full_name);
-+		return -EINVAL;
-+	}
-+
-+	bus_range = get_property(node, "bus-range", &len);
-+	if (bus_range == NULL || len < 2 * sizeof(int)) {
-+		printk(KERN_WARNING "Can't get bus-range for %s, assume"
-+		        " bus 0\n", node->full_name);
-+	}
-+
-+	hose = pcibios_alloc_controller();
-+	if (!hose)
-+		return -ENOMEM;
-+
-+	ppc_md.pcibios_fixup_resources = mpc52xx_pci_fixup_resources;
-+
-+	hose->arch_data = node;
-+	hose->set_cfg_type = 1;
-+
-+	hose->first_busno = bus_range ? bus_range[0] : 0;
-+	hose->last_busno = bus_range ? bus_range[1] : 0xff;
-+
-+	hose->bus_offset = 0;
-+	hose->ops = &mpc52xx_pci_ops;
-+
-+	pci_regs = ioremap(rsrc.start, rsrc.end - rsrc.start + 1);
-+	if (!pci_regs)
-+		return -ENOMEM;
-+
-+	pci_process_bridge_OF_ranges(hose, node, 0);
-+
-+	hose->cfg_addr = &pci_regs->car;
-+
-+	hose->cfg_data = hose->io_base_virt;
-+	hose->io_base_virt = ioremap(hose->io_base_phys,
-+	                             hose->io_resource.end + 1 -
-+	                             hose->io_resource.start);
-+	isa_io_base = (unsigned long) hose->io_base_virt;
-+
-+	mpc52xx_pci_setup(hose, pci_regs);
-+
-+	return 0;
-+}
-diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pci.h b/arch/powerpc/platforms/52xx/mpc52xx_pci.h
-new file mode 100644
-index 0000000..07a659e
---- /dev/null
-+++ b/arch/powerpc/platforms/52xx/mpc52xx_pci.h
-@@ -0,0 +1,104 @@
-+/*
-+ * PCI Include file the Freescale MPC52xx embedded cpu chips
-+ *
-+ * Inspired from code written by Dale Farnsworth <dfarnsworth@mvista.com>
-+ * for the 2.4 kernel.
-+ *
-+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
-+ * Copyright (C) 2003 MontaVista, Software, Inc.
-+ *
-+ * This file is licensed under the terms of the GNU General Public License
-+ * version 2. This program is licensed "as is" without any warranty of any
-+ * kind, whether express or implied.
-+ */
-+
-+#ifndef __SYSLIB_MPC52xx_PCI_H__
-+#define __SYSLIB_MPC52xx_PCI_H__
-+
-+/* ======================================================================== */
-+/* PCI windows config                                                       */
-+/* ======================================================================== */
-+
-+#define MPC52xx_PCI_TARGET_IO	0xf0000000
-+#define MPC52xx_PCI_TARGET_MEM	0x00000000
-+
-+
-+/* ======================================================================== */
-+/* Structures mapping & Defines for PCI Unit                                */
-+/* ======================================================================== */
-+
-+#define MPC52xx_PCI_GSCR_BM		0x40000000
-+#define MPC52xx_PCI_GSCR_PE		0x20000000
-+#define MPC52xx_PCI_GSCR_SE		0x10000000
-+#define MPC52xx_PCI_GSCR_XLB2PCI_MASK	0x07000000
-+#define MPC52xx_PCI_GSCR_XLB2PCI_SHIFT	24
-+#define MPC52xx_PCI_GSCR_IPG2PCI_MASK	0x00070000
-+#define MPC52xx_PCI_GSCR_IPG2PCI_SHIFT	16
-+#define MPC52xx_PCI_GSCR_BME		0x00004000
-+#define MPC52xx_PCI_GSCR_PEE		0x00002000
-+#define MPC52xx_PCI_GSCR_SEE		0x00001000
-+#define MPC52xx_PCI_GSCR_PR		0x00000001
-+
-+
-+#define MPC52xx_PCI_IWBTAR_TRANSLATION(proc_ad,pci_ad,size)	  \
-+		( ( (proc_ad) & 0xff000000 )			| \
-+		  ( (((size) - 1) >> 8) & 0x00ff0000 )		| \
-+		  ( ((pci_ad) >> 16) & 0x0000ff00 ) )
-+
-+#define MPC52xx_PCI_IWCR_PACK(win0,win1,win2)	(((win0) << 24) | \
-+						 ((win1) << 16) | \
-+						 ((win2) <<  8))
-+
-+#define MPC52xx_PCI_IWCR_DISABLE	0x0
-+#define MPC52xx_PCI_IWCR_ENABLE		0x1
-+#define MPC52xx_PCI_IWCR_READ		0x0
-+#define MPC52xx_PCI_IWCR_READ_LINE	0x2
-+#define MPC52xx_PCI_IWCR_READ_MULTI	0x4
-+#define MPC52xx_PCI_IWCR_MEM		0x0
-+#define MPC52xx_PCI_IWCR_IO		0x8
-+
-+#define MPC52xx_PCI_TCR_P		0x01000000
-+#define MPC52xx_PCI_TCR_LD		0x00010000
-+
-+#define MPC52xx_PCI_TBATR_DISABLE	0x0
-+#define MPC52xx_PCI_TBATR_ENABLE	0x1
-+
-+
-+#ifndef __ASSEMBLY__
-+
-+struct mpc52xx_pci {
-+	u32	idr;		/* PCI + 0x00 */
-+	u32	scr;		/* PCI + 0x04 */
-+	u32	ccrir;		/* PCI + 0x08 */
-+	u32	cr1;		/* PCI + 0x0C */
-+	u32	bar0;		/* PCI + 0x10 */
-+	u32	bar1;		/* PCI + 0x14 */
-+	u8	reserved1[16];	/* PCI + 0x18 */
-+	u32	ccpr;		/* PCI + 0x28 */
-+	u32	sid;		/* PCI + 0x2C */
-+	u32	erbar;		/* PCI + 0x30 */
-+	u32	cpr;		/* PCI + 0x34 */
-+	u8	reserved2[4];	/* PCI + 0x38 */
-+	u32	cr2;		/* PCI + 0x3C */
-+	u8	reserved3[32];	/* PCI + 0x40 */
-+	u32	gscr;		/* PCI + 0x60 */
-+	u32	tbatr0;		/* PCI + 0x64 */
-+	u32	tbatr1;		/* PCI + 0x68 */
-+	u32	tcr;		/* PCI + 0x6C */
-+	u32	iw0btar;	/* PCI + 0x70 */
-+	u32	iw1btar;	/* PCI + 0x74 */
-+	u32	iw2btar;	/* PCI + 0x78 */
-+	u8	reserved4[4];	/* PCI + 0x7C */
-+	u32	iwcr;		/* PCI + 0x80 */
-+	u32	icr;		/* PCI + 0x84 */
-+	u32	isr;		/* PCI + 0x88 */
-+	u32	arb;		/* PCI + 0x8C */
-+	u8	reserved5[104];	/* PCI + 0x90 */
-+	u32	car;		/* PCI + 0xF8 */
-+	u8	reserved6[4];	/* PCI + 0xFC */
-+};
-+
-+#endif  /* __ASSEMBLY__ */
-+
-+
-+#endif  /* __SYSLIB_MPC52xx_PCI_H__ */
--- 
-1.4.4.2
-