merge of '4ea5971c2dd26e9c357b906128f0e339d80e3d50'

     and 'e651c4fa9a5d1fc6120cc2309e9cba1388cecc52'

18 files changed, 531 insertions, 14 deletions

diff --git a/packages/gcc/files/gcc4-mtune-compat.patch b/packages/gcc/files/gcc4-mtune-compat.patch
new file mode 100644
index 0000000000..0da2811d37
--- /dev/null
+++ b/packages/gcc/files/gcc4-mtune-compat.patch
@@ -0,0 +1,14 @@
+Patch for gcc3 to support gcc4-compatible (and consistent) values for -mtune= option.
+
+--- gcc-3.4.4/gcc/config/arm/arm.c.org	2007-12-15 23:58:35.000000000 +0200
++++ gcc-3.4.4/gcc/config/arm/arm.c	2007-12-16 00:20:39.000000000 +0200
+@@ -432,7 +432,9 @@
+   {"arm10tdmi",	                         FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED             | FL_ARCH5 },
+   {"arm1020t",	                         FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED             | FL_ARCH5 },
+   {"arm926ejs",                          FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB                          | FL_ARCH5 | FL_ARCH5E },
++  {"arm926ej-s",                         FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB                          | FL_ARCH5 | FL_ARCH5E },
+   {"arm1026ejs",                         FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB                          | FL_ARCH5 | FL_ARCH5E },
++  {"arm1026ej-s",                        FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB                          | FL_ARCH5 | FL_ARCH5E },
+   {"xscale",                             FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE },
+   {"iwmmxt",                             FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT },
+   /* V6 Architecture Processors */
diff --git a/packages/gcc/gcc-4.2.2/fortran-cross-compile-hack.patch b/packages/gcc/gcc-4.2.2/fortran-cross-compile-hack.patch
new file mode 100644
index 0000000000..b3d38ad983
--- /dev/null
+++ b/packages/gcc/gcc-4.2.2/fortran-cross-compile-hack.patch
@@ -0,0 +1,30 @@
+* Fortran would have searched for arm-angstrom-gnueabi-gfortran but would have used
+  used gfortan. For gcc_4.2.2.bb we want to use the gfortran compiler from our cross
+  directory.
+
+diff --git a/libgfortran/configure b/libgfortran/configure
+index f7d86fb..d0966ec 100755
+--- a/libgfortran/configure
++++ b/libgfortran/configure
+@@ -4475,6 +4475,6 @@ exec 5>>./config.log
+ 
+ # We need gfortran to compile parts of the library
+ #AC_PROG_FC(gfortran)
+-FC="$GFORTRAN"
++#FC="$GFORTRAN"
+ ac_ext=${FC_SRCEXT-f}
+ ac_compile='$FC -c $FCFLAGS $FCFLAGS_SRCEXT conftest.$ac_ext >&5'
+\ No newline at end of file
+diff --git a/libgfortran/configure.ac b/libgfortran/configure.ac
+index 4661306..9f83e55 100644
+--- a/libgfortran/configure.ac
++++ b/libgfortran/configure.ac
+@@ -140,7 +140,7 @@ AC_SUBST(enable_static)
+ 
+ # We need gfortran to compile parts of the library
+ #AC_PROG_FC(gfortran)
+-FC="$GFORTRAN"
++#FC="$GFORTRAN"
+ AC_PROG_FC(gfortran)
+ 
+ # extra LD Flags which are required for targets
diff --git a/packages/gcc/gcc-4.2.2/fortran-static-linking.patch b/packages/gcc/gcc-4.2.2/fortran-static-linking.patch
new file mode 100644
index 0000000000..3dd6321dc3
--- /dev/null
+++ b/packages/gcc/gcc-4.2.2/fortran-static-linking.patch
@@ -0,0 +1,48 @@
+f951 (fortran) links to MPFR and GMP of our staging area but when executing
+the command the libs can not be found. Use rpath like all the other apps in
+our staging bin/ directory.
+
+Patch the configure to avoid the regeneration...
+
+Index: gcc-4.2.2/configure
+===================================================================
+--- gcc-4.2.2.orig/configure	2008-01-15 23:23:41.000000000 +0100
++++ gcc-4.2.2/configure	2008-01-15 23:25:20.000000000 +0100
+@@ -2278,14 +2278,14 @@
+ 
+ 
+ if test "x$with_mpfr" != x; then
+-  gmplibs="-L$with_mpfr/lib $gmplibs"
++  gmplibs="-static -L$with_mpfr/lib $gmplibs"
+   gmpinc="-I$with_mpfr/include"
+ fi
+ if test "x$with_mpfr_include" != x; then
+   gmpinc="-I$with_mpfr_include"
+ fi
+ if test "x$with_mpfr_lib" != x; then
+-  gmplibs="-L$with_mpfr_lib $gmplibs"
++  gmplibs="-static -L$with_mpfr_lib $gmplibs"
+ fi
+ 
+ # Specify a location for gmp
+Index: gcc-4.2.2/configure.in
+===================================================================
+--- gcc-4.2.2.orig/configure.in	2008-01-15 23:23:41.000000000 +0100
++++ gcc-4.2.2/configure.in	2008-01-15 23:24:36.000000000 +0100
+@@ -1066,14 +1066,14 @@
+ AC_ARG_WITH(mpfr_lib, [  --with-mpfr-lib=PATH    Specify the directory for the installed MPFR library])
+ 
+ if test "x$with_mpfr" != x; then
+-  gmplibs="-L$with_mpfr/lib $gmplibs"
++  gmplibs="-static -L$with_mpfr/lib $gmplibs"
+   gmpinc="-I$with_mpfr/include"
+ fi
+ if test "x$with_mpfr_include" != x; then
+   gmpinc="-I$with_mpfr_include"
+ fi
+ if test "x$with_mpfr_lib" != x; then
+-  gmplibs="-L$with_mpfr_lib $gmplibs"
++  gmplibs="-static -L$with_mpfr_lib $gmplibs"
+ fi
+ 
+ # Specify a location for gmp
diff --git a/packages/gcc/gcc-4.2.2/gcc-4.0.2-e300c2c3.patch b/packages/gcc/gcc-4.2.2/gcc-4.0.2-e300c2c3.patch
new file mode 100644
index 0000000000..736ac4b6b6
--- /dev/null
+++ b/packages/gcc/gcc-4.2.2/gcc-4.0.2-e300c2c3.patch
@@ -0,0 +1,311 @@
+Adds support for Freescale Power architecture e300c2 and e300c3 cores.
+http://www.bitshrine.org/gpp/tc-fsl-x86lnx-e300c3-nptl-4.0.2-2.src.rpm
+
+Leon Woestenberg <leonw@mailcan.com>
+
+Index: gcc-4.1.2/gcc/config/rs6000/e300c2c3.md
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ gcc-4.1.2/gcc/config/rs6000/e300c2c3.md	2007-10-18 15:32:51.000000000 +0200
+@@ -0,0 +1,189 @@
++;; Pipeline description for Motorola PowerPC e300c3 core.
++;;   Copyright (C) 2003 Free Software Foundation, Inc.
++;;
++;; This file is part of GCC.
++
++;; GCC is free software; you can redistribute it and/or modify it
++;; under the terms of the GNU General Public License as published
++;; by the Free Software Foundation; either version 2, or (at your
++;; option) any later version.
++
++;; GCC is distributed in the hope that it will be useful, but WITHOUT
++;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++;; License for more details.
++
++;; You should have received a copy of the GNU General Public License
++;; along with GCC; see the file COPYING.  If not, write to the
++;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
++;; MA 02111-1307, USA.
++
++(define_automaton "ppce300c3_most,ppce300c3_long,ppce300c3_retire")
++(define_cpu_unit "ppce300c3_decode_0,ppce300c3_decode_1" "ppce300c3_most")
++
++;; We don't simulate general issue queue (GIC).  If we have SU insn
++;; and then SU1 insn, they can not be issued on the same cycle
++;; (although SU1 insn and then SU insn can be issued) because the SU
++;; insn will go to SU1 from GIC0 entry.  Fortunately, the first cycle
++;; multipass insn scheduling will find the situation and issue the SU1
++;; insn and then the SU insn.
++(define_cpu_unit "ppce300c3_issue_0,ppce300c3_issue_1"   "ppce300c3_most")
++
++;; We could describe completion buffers slots in combination with the
++;; retirement units and the order of completion but the result
++;; automaton would behave in the same way because we can not describe
++;; real latency time with taking in order completion into account.
++;; Actually we could define the real latency time by querying reserved
++;; automaton units but the current scheduler uses latency time before
++;; issuing insns and making any reservations.
++;;
++;; So our description is aimed to achieve a insn schedule in which the
++;; insns would not wait in the completion buffer.
++(define_cpu_unit "ppce300c3_retire_0,ppce300c3_retire_1" "ppce300c3_retire")
++
++;; Branch unit:
++(define_cpu_unit "ppce300c3_bu" "ppce300c3_most")
++
++;; IU:
++(define_cpu_unit "ppce300c3_iu0_stage0,ppce300c3_iu1_stage0" "ppce300c3_most")
++
++;; IU: This used to describe non-pipelined division.
++(define_cpu_unit "ppce300c3_mu_div" "ppce300c3_long")
++
++;; SRU:
++(define_cpu_unit "ppce300c3_sru_stage0" "ppce300c3_most")
++
++;; Here we simplified LSU unit description not describing the stages.
++(define_cpu_unit "ppce300c3_lsu" "ppce300c3_most")
++
++;; FPU:
++(define_cpu_unit "ppce300c3_fpu" "ppce300c3_most")
++
++;; The following units are used to make automata deterministic
++(define_cpu_unit "present_ppce300c3_decode_0" "ppce300c3_most")
++(define_cpu_unit "present_ppce300c3_issue_0" "ppce300c3_most")
++(define_cpu_unit "present_ppce300c3_retire_0" "ppce300c3_retire")
++(define_cpu_unit "present_ppce300c3_iu0_stage0" "ppce300c3_most")
++
++;; The following sets to make automata deterministic when option ndfa is used.
++(presence_set "present_ppce300c3_decode_0" "ppce300c3_decode_0")
++(presence_set "present_ppce300c3_issue_0" "ppce300c3_issue_0")
++(presence_set "present_ppce300c3_retire_0" "ppce300c3_retire_0")
++(presence_set "present_ppce300c3_iu0_stage0" "ppce300c3_iu0_stage0")
++
++;; Some useful abbreviations.
++(define_reservation "ppce300c3_decode"
++    "ppce300c3_decode_0|ppce300c3_decode_1+present_ppce300c3_decode_0")
++(define_reservation "ppce300c3_issue"
++    "ppce300c3_issue_0|ppce300c3_issue_1+present_ppce300c3_issue_0")
++(define_reservation "ppce300c3_retire"
++   "ppce300c3_retire_0|ppce300c3_retire_1+present_ppce300c3_retire_0")
++(define_reservation "ppce300c3_iu_stage0"
++   "ppce300c3_iu0_stage0|ppce300c3_iu1_stage0+present_ppce300c3_iu0_stage0")
++
++;; Compares can be executed either one of the IU or SRU
++(define_insn_reservation "ppce300c3_cmp" 1
++  (and (eq_attr "type" "cmp,compare,delayed_compare,fast_compare")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \
++        +ppce300c3_retire")
++
++;; Other one cycle IU insns
++(define_insn_reservation "ppce300c3_iu" 1
++  (and (eq_attr "type" "integer,insert_word")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
++
++;; Branch.  Actually this latency time is not used by the scheduler.
++(define_insn_reservation "ppce300c3_branch" 1
++  (and (eq_attr "type" "jmpreg,branch")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_bu,ppce300c3_retire")
++
++;; Multiply is non-pipelined but can be executed in any IU
++(define_insn_reservation "ppce300c3_multiply" 2
++  (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \
++   ppce300c3_iu_stage0+ppce300c3_retire")
++
++;; Divide.  We use the average latency time here.  We omit reserving a
++;; retire unit because of the result automata will be huge.
++(define_insn_reservation "ppce300c3_divide" 20
++  (and (eq_attr "type" "idiv")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\
++   ppce300c3_mu_div*19")
++
++;; CR logical
++(define_insn_reservation "ppce300c3_cr_logical" 1
++  (and (eq_attr "type" "cr_logical,delayed_cr")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
++
++;; Mfcr
++(define_insn_reservation "ppce300c3_mfcr" 1
++  (and (eq_attr "type" "mfcr")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
++
++;; Mtcrf
++(define_insn_reservation "ppce300c3_mtcrf" 1
++  (and (eq_attr "type" "mtcr")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
++
++;; Mtjmpr
++(define_insn_reservation "ppce300c3_mtjmpr" 1
++  (and (eq_attr "type" "mtjmpr,mfjmpr")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
++
++;; Float point instructions
++(define_insn_reservation "ppce300c3_fpcompare" 3
++  (and (eq_attr "type" "fpcompare")
++       (eq_attr "cpu" "ppce300c3"))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
++
++(define_insn_reservation "ppce300c3_fp" 3
++  (and (eq_attr "type" "fp")
++       (eq_attr "cpu" "ppce300c3"))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
++
++(define_insn_reservation "ppce300c3_dmul" 4
++  (and (eq_attr "type" "dmul")
++       (eq_attr "cpu" "ppce300c3"))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu,nothing,ppce300c3_retire")
++
++; Divides are not pipelined
++(define_insn_reservation "ppce300c3_sdiv" 18
++  (and (eq_attr "type" "sdiv")
++       (eq_attr "cpu" "ppce300c3"))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*17")
++
++(define_insn_reservation "ppce300c3_ddiv" 33
++  (and (eq_attr "type" "ddiv")
++       (eq_attr "cpu" "ppce300c3"))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*32")
++
++;; Loads
++(define_insn_reservation "ppce300c3_load" 2
++  (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
++
++(define_insn_reservation "ppce300c3_fpload" 2
++  (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
++       (eq_attr "cpu" "ppce300c3"))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
++
++;; Stores.
++(define_insn_reservation "ppce300c3_store" 2
++  (and (eq_attr "type" "store,store_ux,store_u")
++       (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
++
++(define_insn_reservation "ppce300c3_fpstore" 2
++  (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
++       (eq_attr "cpu" "ppce300c3"))
++  "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
+Index: gcc-4.1.2/gcc/config/rs6000/rs6000.c
+===================================================================
+--- gcc-4.1.2.orig/gcc/config/rs6000/rs6000.c	2006-12-16 20:24:56.000000000 +0100
++++ gcc-4.1.2/gcc/config/rs6000/rs6000.c	2007-10-18 15:34:26.000000000 +0200
+@@ -557,6 +557,21 @@
+   COSTS_N_INSNS (29),   /* ddiv */
+ };
+ 
++/* Instruction costs on E300C2 and E300C3 cores.  */
++static const
++struct processor_costs ppce300c2c3_cost = {
++  COSTS_N_INSNS (4),    /* mulsi */
++  COSTS_N_INSNS (4),    /* mulsi_const */
++  COSTS_N_INSNS (4),    /* mulsi_const9 */
++  COSTS_N_INSNS (4),    /* muldi */
++  COSTS_N_INSNS (19),   /* divsi */
++  COSTS_N_INSNS (19),   /* divdi */
++  COSTS_N_INSNS (3),    /* fp */
++  COSTS_N_INSNS (4),    /* dmul */
++  COSTS_N_INSNS (18),   /* sdiv */
++  COSTS_N_INSNS (33),   /* ddiv */
++};
++
+ /* Instruction costs on POWER4 and POWER5 processors.  */
+ static const
+ struct processor_costs power4_cost = {
+@@ -1140,6 +1155,8 @@
+ 	 /* 8548 has a dummy entry for now.  */
+ 	 {"8548", PROCESSOR_PPC8540,
+ 	  POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_STRICT_ALIGN},
++ 	 {"e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
++ 	 {"e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK},
+ 	 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
+ 	 {"970", PROCESSOR_POWER4,
+ 	  POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
+@@ -1529,6 +1546,11 @@
+ 	rs6000_cost = &ppc8540_cost;
+ 	break;
+ 
++      case PROCESSOR_PPCE300C2:
++      case PROCESSOR_PPCE300C3:
++	rs6000_cost = &ppce300c2c3_cost;
++	break;
++
+       case PROCESSOR_POWER4:
+       case PROCESSOR_POWER5:
+ 	rs6000_cost = &power4_cost;
+@@ -16647,6 +16669,8 @@
+   case CPU_PPC750:
+   case CPU_PPC7400:
+   case CPU_PPC8540:
++  case CPU_PPCE300C2:
++  case CPU_PPCE300C3:
+     return 2;
+   case CPU_RIOS2:
+   case CPU_PPC604:
+Index: gcc-4.1.2/gcc/config/rs6000/rs6000.h
+===================================================================
+--- gcc-4.1.2.orig/gcc/config/rs6000/rs6000.h	2006-11-18 01:25:49.000000000 +0100
++++ gcc-4.1.2/gcc/config/rs6000/rs6000.h	2007-10-18 15:32:51.000000000 +0200
+@@ -111,6 +111,8 @@
+ %{mcpu=970: -mpower4 -maltivec} \
+ %{mcpu=G5: -mpower4 -maltivec} \
+ %{mcpu=8540: -me500} \
++%{mcpu=e300c2: -mppc} \
++%{mcpu=e300c3: -mppc -mpmr} \
+ %{maltivec: -maltivec} \
+ -many"
+ 
+@@ -211,6 +213,8 @@
+    PROCESSOR_PPC7400,
+    PROCESSOR_PPC7450,
+    PROCESSOR_PPC8540,
++   PROCESSOR_PPCE300C2,
++   PROCESSOR_PPCE300C3,
+    PROCESSOR_POWER4,
+    PROCESSOR_POWER5
+ };
+Index: gcc-4.1.2/gcc/config/rs6000/rs6000.md
+===================================================================
+--- gcc-4.1.2.orig/gcc/config/rs6000/rs6000.md	2006-12-16 20:24:56.000000000 +0100
++++ gcc-4.1.2/gcc/config/rs6000/rs6000.md	2007-10-18 15:32:51.000000000 +0200
+@@ -103,7 +103,7 @@
+ ;; Processor type -- this attribute must exactly match the processor_type
+ ;; enumeration in rs6000.h.
+ 
+-(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
++(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,power4,power5"
+   (const (symbol_ref "rs6000_cpu_attr")))
+ 
+ (automata_option "ndfa")
+@@ -119,6 +119,7 @@
+ (include "7xx.md")
+ (include "7450.md")
+ (include "8540.md")
++(include "e300c2c3.md")
+ (include "power4.md")
+ (include "power5.md")
+ 
+Index: gcc-4.1.2/gcc/config.gcc
+===================================================================
+--- gcc-4.1.2.orig/gcc/config.gcc	2007-10-18 15:26:23.000000000 +0200
++++ gcc-4.1.2/gcc/config.gcc	2007-10-18 15:32:51.000000000 +0200
+@@ -2710,7 +2710,7 @@
+ 			| rios | rios1 | rios2 | rsc | rsc1 | rs64a \
+ 			| 401 | 403 | 405 | 405fp | 440 | 440fp | 505 \
+ 			| 601 | 602 | 603 | 603e | ec603e | 604 \
+-			| 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \
++			| 604e | 620 | 630 | 740 | 750 | 7400 | 7450 | e300c[23] \
+ 			| 854[08] | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5)
+ 				# OK
+ 				;;
diff --git a/packages/gcc/gcc-cross-kernel-3.3.4_3.3.4.bb b/packages/gcc/gcc-cross-kernel-3.3.4_3.3.4.bb
index 7f274bee30..ba89452187 100644
--- a/packages/gcc/gcc-cross-kernel-3.3.4_3.3.4.bb
+++ b/packages/gcc/gcc-cross-kernel-3.3.4_3.3.4.bb
@@ -12,6 +12,6 @@ do_install () {
 
 do_stage () {
 	cd gcc
-	oe_runmake install-common install-headers install-libgcc
+	oe_runmake install-libgcc install-common install-headers
 	install -m 0755 xgcc ${CROSS_DIR}/bin/${TARGET_PREFIX}gcc-${PV}
 }
diff --git a/packages/gcc/gcc-cross-sdk_3.4.4.bb b/packages/gcc/gcc-cross-sdk_3.4.4.bb
index a8e9a67a96..038d39040b 100644
--- a/packages/gcc/gcc-cross-sdk_3.4.4.bb
+++ b/packages/gcc/gcc-cross-sdk_3.4.4.bb
@@ -3,7 +3,7 @@ HOMEPAGE = "http://www.gnu.org/software/gcc/"
 SECTION = "devel"
 LICENSE = "GPL"
 require gcc_${PV}.bb
-PR = "r1"
+PR = "r2"
 
 inherit sdk
 
diff --git a/packages/gcc/gcc-cross-sdk_4.2.2.bb b/packages/gcc/gcc-cross-sdk_4.2.2.bb
new file mode 100644
index 0000000000..2fdaa7dc27
--- /dev/null
+++ b/packages/gcc/gcc-cross-sdk_4.2.2.bb
@@ -0,0 +1,21 @@
+DESCRIPTION = "The GNU cc and gcc C compilers."
+HOMEPAGE = "http://www.gnu.org/software/gcc/"
+SECTION = "devel"
+LICENSE = "GPL"
+PR = "r2"
+
+inherit sdk
+
+FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/gcc-${PV}"
+
+PACKAGES = "${PN}"
+
+require gcc_${PV}.bb
+require gcc4-build-sdk.inc
+require gcc-package-sdk.inc
+
+DEPENDS = "virtual/${TARGET_PREFIX}binutils virtual/${TARGET_PREFIX}libc-for-gcc gmp-native mpfr-native"
+
+EXTRA_OECONF += "--disable-libunwind-exceptions --disable-libssp \
+		--disable-libgomp --disable-libmudflap \
+		--with-mpfr=${STAGING_DIR_NATIVE}${layout_exec_prefix}"
diff --git a/packages/gcc/gcc-cross_3.4.4.bb b/packages/gcc/gcc-cross_3.4.4.bb
index 7021b0fdd3..83c0055017 100644
--- a/packages/gcc/gcc-cross_3.4.4.bb
+++ b/packages/gcc/gcc-cross_3.4.4.bb
@@ -5,7 +5,7 @@ inherit cross
 FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/gcc-${PV}"
 # NOTE: split PR.  If the main .oe changes something that affects its *build*
 # remember to increment this one too.
-PR = "r6"
+PR = "r7"
 
 DEPENDS = "virtual/${TARGET_PREFIX}binutils virtual/${TARGET_PREFIX}libc-for-gcc"
 PROVIDES = "virtual/${TARGET_PREFIX}gcc virtual/${TARGET_PREFIX}g++"
diff --git a/packages/gcc/gcc-cross_4.1.2.bb b/packages/gcc/gcc-cross_4.1.2.bb
index 0f63487f2c..306cf9539c 100644
--- a/packages/gcc/gcc-cross_4.1.2.bb
+++ b/packages/gcc/gcc-cross_4.1.2.bb
@@ -17,4 +17,6 @@ require gcc-package-cross.inc
 
 SRC_URI_append_fail-fast = " file://zecke-no-host-includes.patch;patch=1 "
 
+EXTRA_OECONF_append_avr32= "  --disable-libmudflap "
+
 EXTRA_OECONF += "--disable-libunwind-exceptions --with-mpfr=${STAGING_DIR_NATIVE}${layout_exec_prefix}"
diff --git a/packages/gcc/gcc-cross_4.2.2.bb b/packages/gcc/gcc-cross_4.2.2.bb
index ec169072af..daf0e65003 100644
--- a/packages/gcc/gcc-cross_4.2.2.bb
+++ b/packages/gcc/gcc-cross_4.2.2.bb
@@ -5,7 +5,7 @@ inherit cross
 FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/gcc-${PV}"
 # NOTE: split PR.  If the main .oe changes something that affects its *build*
 # remember to increment this one too.
-PR = "r2"
+PR = "r3"
 
 DEPENDS = "virtual/${TARGET_PREFIX}binutils virtual/${TARGET_PREFIX}libc-for-gcc gmp-native mpfr-native"
 PROVIDES = "virtual/${TARGET_PREFIX}gcc virtual/${TARGET_PREFIX}g++"
diff --git a/packages/gcc/gcc-native.inc b/packages/gcc/gcc-native.inc
new file mode 100644
index 0000000000..3cf20a4589
--- /dev/null
+++ b/packages/gcc/gcc-native.inc
@@ -0,0 +1,28 @@
+DEPENDS = ""
+PACKAGES = ""
+PROVIDES = "gcc-native-${PV}"
+
+inherit native
+
+FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/gcc-${PV}"
+
+# This is intended to be a -very- basic config
+EXTRA_OECONF = "--with-local-prefix=${STAGING_DIR_TARGET}${layout_prefix} \
+		--with-newlib \
+		--disable-shared \
+		--disable-threads \
+		--disable-multilib \
+		--disable-__cxa_atexit \
+		--enable-languages=c \
+		--enable-target-optspace \
+		--program-prefix=${TARGET_PREFIX}"
+
+do_install () {
+	:
+}
+
+do_stage () {
+	cd gcc
+	oe_runmake install-common install-headers install-libgcc
+	install -m 0755 xgcc ${STAGING_BINDIR}/gcc-${PV}
+}
diff --git a/packages/gcc/gcc-native_3.4.4.bb b/packages/gcc/gcc-native_3.4.4.bb
new file mode 100644
index 0000000000..d70a4f5464
--- /dev/null
+++ b/packages/gcc/gcc-native_3.4.4.bb
@@ -0,0 +1,3 @@
+require gcc_${PV}.bb
+require gcc-native.inc
+PROVIDES += "gcc3-native"
diff --git a/packages/gcc/gcc-package-cross.inc b/packages/gcc/gcc-package-cross.inc
index 5c6b370d82..51a45cd633 100644
--- a/packages/gcc/gcc-package-cross.inc
+++ b/packages/gcc/gcc-package-cross.inc
@@ -43,12 +43,12 @@ do_install () {
                 # Already in the right location
                 :
         elif [ -f ${D}${prefix}/lib/libgcc_s.so.? ]; then
-                mv -f ${D}${prefix}/lib/libgcc_s.so* ${D}${target_base_libdir}
+                mv -f ${D}${prefix}/lib/libgcc_s.so* ${D}${target_base_libdir} || true
 
         elif [  -f ${D}${prefix}/*/lib/nof/libgcc_s.so.? ]; then
                 mv -f ${D}${prefix}/*/lib/nof/libgcc_s.so* ${D}${target_base_libdir}
         else
-                mv -f ${D}${prefix}/*/lib/libgcc_s.so* ${D}${target_base_libdir}
+                mv -f ${D}${prefix}/*/lib/libgcc_s.so* ${D}${target_base_libdir} || true 
         fi
 
 
@@ -58,12 +58,12 @@ do_install () {
 
         if [ -f ${D}${prefix}/*/lib/nof/libstdc++.so ]; then
 
-           mv -f ${D}${prefix}/*/lib/nof/libstdc++.so* ${D}${target_libdir}
+           mv -f ${D}${prefix}/*/lib/nof/libstdc++.so* ${D}${target_libdir} || true
            mv -f ${D}${prefix}/*/lib/nof/libg2c.so* ${D}${target_libdir} || true
            mv -f ${D}${prefix}/*/lib/nof/libgfortran*.so* ${D}${target_libdir} || true
 
         else
-           mv -f ${D}${prefix}/*/lib/libstdc++.so* ${D}${target_libdir}
+           mv -f ${D}${prefix}/*/lib/libstdc++.so* ${D}${target_libdir} || true
            mv -f ${D}${prefix}/*/lib/libg2c.so* ${D}${target_libdir} || true
            mv -f ${D}${prefix}/*/lib/libgfortran*.so* ${D}${target_libdir} || true
         fi
@@ -75,7 +75,7 @@ do_install () {
        if [ "x${OLD_INHIBIT_PACKAGE_STRIP}" != "x1" ]; then
                ${TARGET_PREFIX}strip ${D}${target_libdir}/libstdc++.so.*
                ${TARGET_PREFIX}strip ${D}${target_libdir}/libg2c.so.* || true
-               ${TARGET_PREFIX}strip ${D}${target_base_libdir}/libgcc_s.so.*
+               ${TARGET_PREFIX}strip ${D}${target_base_libdir}/libgcc_s.so.* || true
                ${TARGET_PREFIX}strip ${D}${target_libdir}/libgfortran*.so* || true
 	fi
      
diff --git a/packages/gcc/gcc-package.inc b/packages/gcc/gcc-package.inc
index 96f1604997..d1b4607de5 100644
--- a/packages/gcc/gcc-package.inc
+++ b/packages/gcc/gcc-package.inc
@@ -92,7 +92,11 @@ do_install () {
 
 	# Move libgcc_s into /lib
 	mkdir -p ${D}${base_libdir}
-	mv ${D}${libdir}/libgcc_s.so.* ${D}${base_libdir}
+	if [ -f ${D}${libdir}/nof/libgcc_s.so ]; then
+		mv ${D}${libdir}/nof/libgcc_s.so.* ${D}${base_libdir}
+	else
+		mv ${D}${libdir}/libgcc_s.so.* ${D}${base_libdir}
+	fi
 	rm -f ${D}${libdir}/libgcc_s.so
 	ln -sf `echo ${libdir}/gcc/${TARGET_SYS}/${BINV} \
 		| tr -s / \
diff --git a/packages/gcc/gcc_3.4.4.bb b/packages/gcc/gcc_3.4.4.bb
index e9e073b1ae..4694d3ac5e 100644
--- a/packages/gcc/gcc_3.4.4.bb
+++ b/packages/gcc/gcc_3.4.4.bb
@@ -1,4 +1,4 @@
-PR = "r6"
+PR = "r7"
 DESCRIPTION = "The GNU cc and gcc C compilers."
 HOMEPAGE = "http://www.gnu.org/software/gcc/"
 SECTION = "devel"
@@ -23,7 +23,8 @@ SRC_URI = "${GNU_MIRROR}/gcc/gcc-${PV}/gcc-${PV}.tar.bz2 \
 	   file://15342.patch;patch=1 \
 	   file://always-fixincperm.patch;patch=1 \
 	   file://GCOV_PREFIX_STRIP-cross-profile_3.4.patch;patch=1 \
-	   file://zecke-xgcc-cpp.patch;patch=1 "
+	   file://zecke-xgcc-cpp.patch;patch=1 \
+	   file://gcc4-mtune-compat.patch;patch=1"
 
 SRC_URI += "file://gcc34-configure.in.patch;patch=1"
 SRC_URI += "file://gcc34-thumb-support.patch;patch=1"
diff --git a/packages/gcc/gcc_4.1.2.bb b/packages/gcc/gcc_4.1.2.bb
index e0801d3c7f..b3eb0100e8 100644
--- a/packages/gcc/gcc_4.1.2.bb
+++ b/packages/gcc/gcc_4.1.2.bb
@@ -39,6 +39,25 @@ SRC_URI = "ftp://ftp.gnu.org/pub/gnu/gcc/gcc-4.1.2/gcc-4.1.2.tar.bz2 \
 
 SRC_URI_append_sh3  = " file://sh3-installfix-fixheaders.patch;patch=1 "
 
+SRC_URI_avr32 = "http://www.angstrom-distribution.org/unstable/sources/gcc-4.1.2-atmel.1.1.0.tar.gz \
+#           file://100-uclibc-conf.patch;patch=1 \
+#           file://200-uclibc-locale.patch;patch=1 \
+#           file://300-libstdc++-pic.patch;patch=1 \
+           file://301-missing-execinfo_h.patch;patch=1 \
+           file://302-c99-snprintf.patch;patch=1 \
+           file://303-c99-complex-ugly-hack.patch;patch=1 \
+           file://304-index_macro.patch;patch=1 \
+           file://602-sdk-libstdc++-includes.patch;patch=1 \
+           file://gcc41-configure.in.patch;patch=1 \
+           file://ldflags.patch;patch=1 \
+           file://zecke-xgcc-cpp.patch;patch=1 \
+           file://cache-amnesia.patch;patch=1 \
+           "
+
+do_compile_prepend_avr32() {
+       ln -sf ${S}/libstdc++-v3/config/os/uclibc/ ${S}/libstdc++-v3/config/os/uclibc-linux
+}
+
 #Set the fortran bits
 # ',fortran' or '', not 'f77' like gcc3 had
 FORTRAN = ""
diff --git a/packages/gcc/gcc_4.2.1.bb b/packages/gcc/gcc_4.2.1.bb
index 5d049398e4..688ccdaeb8 100644
--- a/packages/gcc/gcc_4.2.1.bb
+++ b/packages/gcc/gcc_4.2.1.bb
@@ -42,6 +42,32 @@ SRC_URI = "ftp://ftp.gnu.org/pub/gnu/gcc/gcc-${PV}/gcc-${PV}.tar.bz2 \
         file://pr34130.patch;patch=1 \
 "
 
+SRC_URI_avr32 = " http://ewi546.ewi.utwente.nl/tmp/avr32-gcc-4.2.1-atmel.1.0.1.tar.gz \
+        file://100-uclibc-conf.patch;patch=1 \
+        file://103-uclibc-conf-noupstream.patch;patch=1 \
+        file://200-uclibc-locale.patch;patch=1 \
+        file://203-uclibc-locale-no__x.patch;patch=1 \
+        file://204-uclibc-locale-wchar_fix.patch;patch=1 \
+        file://205-uclibc-locale-update.patch;patch=1 \
+        file://300-libstdc++-pic.patch;patch=1 \
+        file://301-missing-execinfo_h.patch;patch=1 \
+        file://302-c99-snprintf.patch;patch=1 \
+        file://303-c99-complex-ugly-hack.patch;patch=1 \
+        file://304-index_macro.patch;patch=1 \
+        file://305-libmudflap-susv3-legacy.patch;patch=1 \
+        file://306-libstdc++-namespace.patch;patch=1 \
+        file://307-locale_facets.patch;patch=1 \
+        file://402-libbackend_dep_gcov-iov.h.patch;patch=1 \
+        file://602-sdk-libstdc++-includes.patch;patch=1 \
+        file://740-sh-pr24836.patch;patch=1 \
+        file://904-flatten-switch-stmt-00.patch;patch=1 \
+        file://gcc41-configure.in.patch;patch=1 \
+        file://ldflags.patch;patch=1 \
+        file://zecke-xgcc-cpp.patch;patch=1 \
+        file://cache-amnesia.patch;patch=1 \
+        file://gfortran.patch;patch=1 \
+"
+
 SRC_URI_append_ep93xx = " \
         file://arm-crunch-saveregs.patch;patch=1 \
         file://arm-crunch-20000320.patch;patch=1 \
@@ -80,5 +106,5 @@ require gcc3-build.inc
 ARCH_FLAGS_FOR_TARGET=-isystem${STAGING_INCDIR}
 
 
-EXTRA_OECONF += " --disable-libssp --disable-bootstrap "
+EXTRA_OECONF += " --disable-libgomp --disable-libssp --disable-bootstrap "
 
diff --git a/packages/gcc/gcc_4.2.2.bb b/packages/gcc/gcc_4.2.2.bb
index de3b65ce7f..15a25c9c6a 100644
--- a/packages/gcc/gcc_4.2.2.bb
+++ b/packages/gcc/gcc_4.2.2.bb
@@ -1,4 +1,4 @@
-PR = "r2"
+PR = "r3"
 DESCRIPTION = "The GNU cc and gcc C compilers."
 HOMEPAGE = "http://www.gnu.org/software/gcc/"
 SECTION = "devel"
@@ -39,7 +39,9 @@ SRC_URI = "ftp://ftp.gnu.org/pub/gnu/gcc/gcc-${PV}/gcc-${PV}.tar.bz2 \
         file://fix-ICE-in-arm_unwind_emit_set.diff;patch=1 \
 	file://cache-amnesia.patch;patch=1 \
         file://gfortran.patch;patch=1 \
+        file://gcc-4.0.2-e300c2c3.patch;patch=1 \
         file://pr34130.patch;patch=1 \
+        file://fortran-static-linking.patch;patch=1 \
 "
 
 SRC_URI_append_ep93xx = " \
@@ -71,6 +73,8 @@ SRC_URI_append_sh3  = " file://sh3-installfix-fixheaders.patch;patch=1 "
 FORTRAN = ""
 FORTRAN_linux-gnueabi = ",fortran"
 
+DEPENDS += " gmp mpfr "
+
 #Set the java bits
 JAVA = ""
 JAVA_arm = ""
@@ -82,3 +86,9 @@ ARCH_FLAGS_FOR_TARGET=-isystem${STAGING_INCDIR}
 
 EXTRA_OECONF += " --disable-libssp --disable-bootstrap "
 
+# We know some one is including us, but we only want to apply this fortran hack for the real gcc
+python __anonymous () {
+    import bb
+    if bb.data.getVar('PN', d, True) == "gcc":
+        bb.data.setVar('SRC_URI_append', ' file://fortran-cross-compile-hack.patch;patch=1', d)
+}