diff options
| author | Michael Lauer <mickey@vanille-media.de> | 2007-08-30 22:36:16 +0000 |
|---|---|---|
| committer | Michael Lauer <mickey@vanille-media.de> | 2007-08-30 22:36:16 +0000 |
| commit | 295f0eb481ce73f976bc46031fa33551375d77cf (patch) | |
| tree | 05128354e9e08c744377763a48f95398c5dfa8fd /packages/gcc/gcc-4.1.2 | |
| parent | 328141d34f35516a988d7525f704064c6c55737d (diff) | |
| parent | d7d57f3e05feab6e49a2264f6e81902c28682049 (diff) | |
merge of '16ddc63cc58ab4f6ac83a2e1d653c740ffdd6f87'
and '76b3eaaf78af7bef8ae185d70ad72a4c8f9a3af7'
Diffstat (limited to 'packages/gcc/gcc-4.1.2')
47 files changed, 12852 insertions, 0 deletions
diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-20000320.patch b/packages/gcc/gcc-4.1.2/arm-crunch-20000320.patch new file mode 100644 index 0000000000..3fb0da7670 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-20000320.patch @@ -0,0 +1,11 @@ +--- gcc-4.1.2/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c.original 2007-06-07 16:33:44.000000000 +1000 ++++ gcc-4.1.2/gcc/testsuite/gcc.c-torture/execute/ieee/20000320-1.c 2007-06-07 16:34:05.000000000 +1000 +@@ -49,7 +49,7 @@ + exit (0); + + c(0x3690000000000000ULL, 0x00000000U); +-#if (defined __arm__ || defined __thumb__) && ! (defined __ARMEB__ || defined __VFP_FP__) ++#if (defined __arm__ || defined __thumb__) && ! (defined __ARMEB__ || defined __VFP_FP__) && ! (defined __MAVERICK__) + /* The ARM always stores FP numbers in big-wordian format, + even when running in little-byteian mode. */ + c(0x0000000136900000ULL, 0x00000001U); diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-32bit-disable.patch b/packages/gcc/gcc-4.1.2/arm-crunch-32bit-disable.patch new file mode 100644 index 0000000000..88eaee322d --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-32bit-disable.patch @@ -0,0 +1,85 @@ +--- gcc-4.1.2/gcc/config/arm/cirrus.md-integer 2007-06-15 09:01:37.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-15 09:04:45.000000000 +1000 +@@ -149,7 +149,7 @@ + (match_operand:SI 1 "cirrus_fp_register" "0") + (mult:SI (match_operand:SI 2 "cirrus_fp_register" "v") + (match_operand:SI 3 "cirrus_fp_register" "v"))))] +- "0 && TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "0 && TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfmsc32%?\\t%V0, %V2, %V3" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] +@@ -305,7 +305,7 @@ + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (float:SF (match_operand:SI 1 "s_register_operand" "r"))) + (clobber (match_scratch:DF 2 "=v"))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2" + [(set_attr "length" "8") + (set_attr "cirrus" "move")] +@@ -315,7 +315,7 @@ + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (float:DF (match_operand:SI 1 "s_register_operand" "r"))) + (clobber (match_scratch:DF 2 "=v"))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2" + [(set_attr "length" "8") + (set_attr "cirrus" "move")] +@@ -339,7 +339,7 @@ + [(set (match_operand:SI 0 "s_register_operand" "=r") + (fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register" "v")))) + (clobber (match_scratch:DF 2 "=v"))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" + [(set_attr "length" "8") + (set_attr "cirrus" "normal")] +@@ -349,7 +349,7 @@ + [(set (match_operand:SI 0 "s_register_operand" "=r") + (fix:SI (fix:DF (match_operand:DF 1 "cirrus_fp_register" "v")))) + (clobber (match_scratch:DF 2 "=v"))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" + [(set_attr "length" "8") + (set_attr "cirrus" "normal")] +--- gcc-4.1.2/gcc/config/arm/arm.md-trunc 2007-06-15 10:56:13.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-15 11:01:22.000000000 +1000 +@@ -3130,7 +3130,7 @@ + (float:SF (match_operand:SI 1 "s_register_operand" "")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + " +- if (TARGET_MAVERICK) ++ if (TARGET_MAVERICK && 0) + { + emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1])); + DONE; +@@ -3142,7 +3142,7 @@ + (float:DF (match_operand:SI 1 "s_register_operand" "")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + " +- if (TARGET_MAVERICK) ++ if (TARGET_MAVERICK && 0) + { + emit_insn (gen_cirrus_floatsidf2 (operands[0], operands[1])); + DONE; +@@ -3154,7 +3154,7 @@ + (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))] + "TARGET_ARM && TARGET_HARD_FLOAT" + " +- if (TARGET_MAVERICK) ++ if (TARGET_MAVERICK && 0) + { + if (!cirrus_fp_register (operands[0], SImode)) + operands[0] = force_reg (SImode, operands[0]); +@@ -3170,7 +3170,7 @@ + (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))] + "TARGET_ARM && TARGET_HARD_FLOAT" + " +- if (TARGET_MAVERICK) ++ if (TARGET_MAVERICK && 0) + { + if (!cirrus_fp_register (operands[1], DFmode)) + operands[1] = force_reg (DFmode, operands[0]); diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-64bit-disable.patch b/packages/gcc/gcc-4.1.2/arm-crunch-64bit-disable.patch new file mode 100644 index 0000000000..537fe2f746 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-64bit-disable.patch @@ -0,0 +1,189 @@ +--- gcc-4.1.2/gcc/config/arm/cirrus.md-integer 2007-06-15 09:01:37.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-15 09:04:45.000000000 +1000 +@@ -34,7 +34,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (plus:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:DI 2 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfadd64%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] +@@ -74,7 +74,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (minus:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:DI 2 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfsub64%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] +@@ -124,7 +124,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (mult:DI (match_operand:DI 2 "cirrus_fp_register" "v") + (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfmul64%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_dmult") + (set_attr "cirrus" "normal")] +@@ -206,7 +206,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "register_operand" "r")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfrshl64%?\\t%V1, %V0, %s2" + [(set_attr "cirrus" "normal")] + ) +@@ -215,7 +215,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "cirrus_shift_const" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfsh64%?\\t%V0, %V1, #%s2" + [(set_attr "cirrus" "normal")] + ) +@@ -224,7 +224,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (ashiftrt:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "cirrus_shift_const" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfsh64%?\\t%V0, %V1, #-%s2" + [(set_attr "cirrus" "normal")] + ) +@@ -232,7 +232,7 @@ + (define_insn "*cirrus_absdi2" + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (abs:DI (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfabs64%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) +@@ -238,11 +238,12 @@ + ) + + ;; This doesn't really clobber ``cc''. Fixme: aldyh. ++;; maybe buggy? + (define_insn "*cirrus_negdi2" + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (neg:DI (match_operand:DI 1 "cirrus_fp_register" "v"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfneg64%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) +@@ -324,14 +324,14 @@ + (define_insn "floatdisf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfcvt64s%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")]) + + (define_insn "floatdidf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfcvt64d%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")]) + +@@ -376,7 +376,7 @@ + (define_insn "*cirrus_arm_movdi" + [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v") + (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "* + { + switch (which_alternative) +--- gcc-4.1.2/gcc/config/arm/arm.md-64 2007-06-15 11:37:42.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-15 11:40:45.000000000 +1000 +@@ -357,7 +357,7 @@ + (clobber (reg:CC CC_REGNUM))])] + "TARGET_EITHER" + " +- if (TARGET_HARD_FLOAT && TARGET_MAVERICK) ++ if (TARGET_HARD_FLOAT && TARGET_MAVERICK && 0) + { + if (!cirrus_fp_register (operands[0], DImode)) + operands[0] = force_reg (DImode, operands[0]); +@@ -393,7 +393,7 @@ + (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0") + (match_operand:DI 2 "s_register_operand" "r, 0"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" ++ "TARGET_ARM" + "#" + "TARGET_ARM && reload_completed" + [(parallel [(set (reg:CC_C CC_REGNUM) +@@ -421,7 +421,7 @@ + (match_operand:SI 2 "s_register_operand" "r,r")) + (match_operand:DI 1 "s_register_operand" "r,0"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" ++ "TARGET_ARM" + "#" + "TARGET_ARM && reload_completed" + [(parallel [(set (reg:CC_C CC_REGNUM) +@@ -450,7 +450,7 @@ + (match_operand:SI 2 "s_register_operand" "r,r")) + (match_operand:DI 1 "s_register_operand" "r,0"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" ++ "TARGET_ARM" + "#" + "TARGET_ARM && reload_completed" + [(parallel [(set (reg:CC_C CC_REGNUM) +@@ -838,7 +838,7 @@ + if (TARGET_HARD_FLOAT && TARGET_MAVERICK + && TARGET_ARM + && cirrus_fp_register (operands[0], DImode) +- && cirrus_fp_register (operands[1], DImode)) ++ && cirrus_fp_register (operands[1], DImode) && 0) + { + emit_insn (gen_cirrus_subdi3 (operands[0], operands[1], operands[2])); + DONE; +@@ -2599,7 +2599,7 @@ + values to iwmmxt regs and back. */ + FAIL; + } +- else if (!TARGET_REALLY_IWMMXT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)) ++ else if (!TARGET_REALLY_IWMMXT) + FAIL; + " + ) +@@ -4097,7 +4097,7 @@ + [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m") + (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))] + "TARGET_ARM +- && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP)) ++ && !(TARGET_HARD_FLOAT && (TARGET_VFP)) + && !TARGET_IWMMXT" + "* + switch (which_alternative) +@@ -4215,7 +4215,6 @@ + [(set (match_operand:DI 0 "nonimmediate_operand" "=l,l,l,l,>,l, m,*r") + (match_operand:DI 1 "general_operand" "l, I,J,>,l,mi,l,*r"))] + "TARGET_THUMB +- && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) + && ( register_operand (operands[0], DImode) + || register_operand (operands[1], DImode))" + "* +--- gcc-4.1.2/gcc/config/arm/arm.c-original 2007-06-26 15:08:04.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-06-26 15:08:41.000000000 +1000 +@@ -12036,7 +12036,7 @@ + upper 32 bits. This causes gcc all sorts of grief. We can't + even split the registers into pairs because Cirrus SI values + get sign extended to 64bits-- aldyh. */ +- return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode); ++ return (GET_MODE_CLASS (mode) == MODE_FLOAT); + + if (TARGET_HARD_FLOAT && TARGET_VFP + && IS_VFP_REGNUM (regno)) diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-64bit-disable0.patch b/packages/gcc/gcc-4.1.2/arm-crunch-64bit-disable0.patch new file mode 100644 index 0000000000..95abf68a60 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-64bit-disable0.patch @@ -0,0 +1,47 @@ +diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.md gcc-4.1.2/gcc/config/arm/arm.md +--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.md 2006-09-28 03:10:22.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-15 09:53:21.000000000 +1000 +@@ -6865,10 +6877,12 @@ + ) + + ;; Cirrus DI compare instruction ++;; This is disabled and left go through ARM core registers, because currently ++;; Crunch coprocessor does only signed comparison. + (define_expand "cmpdi" + [(match_operand:DI 0 "cirrus_fp_register" "") + (match_operand:DI 1 "cirrus_fp_register" "")] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK & 0" + "{ + arm_compare_op0 = operands[0]; + arm_compare_op1 = operands[1]; +@@ -6879,7 +6893,7 @@ + [(set (reg:CC CC_REGNUM) + (compare:CC (match_operand:DI 0 "cirrus_fp_register" "v") + (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK & 0" + "cfcmp64%?\\tr15, %V0, %V1" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "compare")] +@@ -10105,6 +10119,7 @@ + [(unspec:SI [(match_operand:SI 0 "register_operand" "")] UNSPEC_PROLOGUE_USE)] + "" + "%@ %0 needed for prologue" ++ [(set_attr "length" "0")] + ) + + +diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/cirrus.md gcc-4.1.2/gcc/config/arm/cirrus.md +--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/cirrus.md 2005-06-25 11:22:41.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-05-15 09:55:29.000000000 +1000 +@@ -348,7 +348,8 @@ + (clobber (match_scratch:DF 2 "=v"))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" + "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" +- [(set_attr "length" "8")] ++ [(set_attr "length" "8") ++ (set_attr "cirrus" "normal")] + ) + + (define_insn "*cirrus_truncdfsf2" diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-Uy.patch b/packages/gcc/gcc-4.1.2/arm-crunch-Uy.patch new file mode 100644 index 0000000000..227e1cfe04 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-Uy.patch @@ -0,0 +1,35 @@ +--- gcc-4.1.2/gcc/config/arm/cirrus.md-original 2007-06-28 13:26:41.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-28 13:28:25.000000000 +1000 +@@ -378,8 +378,8 @@ + ) + + (define_insn "*cirrus_arm_movdi" +- [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v") +- (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))] ++ [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,Uy,v") ++ (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,Uyi,v,v"))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "* + { +@@ -436,8 +436,8 @@ + ) + + (define_insn "*cirrus_movsf_hard_insn" +- [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m") +- (match_operand:SF 1 "general_operand" "v,mE,r,v,v,r,mE,r"))] ++ [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,Uy,r,r,m") ++ (match_operand:SF 1 "general_operand" "v,UyE,r,v,v,r,mE,r"))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK + && (GET_CODE (operands[0]) != MEM + || register_operand (operands[1], SFmode))" +@@ -458,8 +458,8 @@ + ) + + (define_insn "*cirrus_movdf_hard_insn" +- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m") +- (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,mF,r,v,v"))] ++ [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,Uy") ++ (match_operand:DF 1 "general_operand" "Q,r,r,r,UyF,v,mF,r,v,v"))] + "TARGET_ARM + && TARGET_HARD_FLOAT && TARGET_MAVERICK + && (GET_CODE (operands[0]) != MEM diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-and-or.patch b/packages/gcc/gcc-4.1.2/arm-crunch-and-or.patch new file mode 100644 index 0000000000..24357d316e --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-and-or.patch @@ -0,0 +1,67 @@ +--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-13 17:16:38.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-13 17:35:19.000000000 +1000 +@@ -8455,7 +8455,7 @@ + (and:SI (match_operator:SI 1 "arm_comparison_operator" + [(match_operand 3 "cc_register" "") (const_int 0)]) + (match_operand:SI 2 "s_register_operand" "r")))] +- "TARGET_ARM" ++ "TARGET_ARM && !TARGET_MAVERICK" + "mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1" + [(set_attr "conds" "use") + (set_attr "length" "8")] +@@ -8466,7 +8466,7 @@ + (ior:SI (match_operator:SI 2 "arm_comparison_operator" + [(match_operand 3 "cc_register" "") (const_int 0)]) + (match_operand:SI 1 "s_register_operand" "0,?r")))] +- "TARGET_ARM" ++ "TARGET_ARM && !TARGET_MAVERICK" + "@ + orr%d2\\t%0, %1, #1 + mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1" +@@ -8734,7 +8734,8 @@ + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM + && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_OR_Y) +- != CCmode)" ++ != CCmode) ++ && !TARGET_MAVERICK" + "#" + "TARGET_ARM && reload_completed" + [(set (match_dup 7) +@@ -8765,7 +8766,7 @@ + (set (match_operand:SI 7 "s_register_operand" "=r") + (ior:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)]) + (match_op_dup 6 [(match_dup 4) (match_dup 5)])))] +- "TARGET_ARM" ++ "TARGET_ARM && !TARGET_MAVERICK" + "#" + "TARGET_ARM && reload_completed" + [(set (match_dup 0) +@@ -8790,7 +8791,8 @@ + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM + && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) +- != CCmode)" ++ != CCmode) ++ && !TARGET_MAVERICK" + "#" + "TARGET_ARM && reload_completed + && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) +@@ -8823,7 +8825,7 @@ + (set (match_operand:SI 7 "s_register_operand" "=r") + (and:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)]) + (match_op_dup 6 [(match_dup 4) (match_dup 5)])))] +- "TARGET_ARM" ++ "TARGET_ARM && !TARGET_MAVERICK" + "#" + "TARGET_ARM && reload_completed" + [(set (match_dup 0) +@@ -8850,7 +8852,7 @@ + [(match_operand:SI 4 "s_register_operand" "r,r,r") + (match_operand:SI 5 "arm_add_operand" "rIL,rIL,rIL")]))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM ++ "TARGET_ARM && !TARGET_MAVERICK + && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) + == CCmode)" + "#" diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-cfabs-disable.patch b/packages/gcc/gcc-4.1.2/arm-crunch-cfabs-disable.patch new file mode 100644 index 0000000000..01bebf3867 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-cfabs-disable.patch @@ -0,0 +1,20 @@ +--- gcc-4.1.2/gcc/config/arm/cirrus.md-original 2007-07-03 10:53:06.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-07-03 10:53:19.000000000 +1000 +@@ -287,7 +287,7 @@ + (define_insn "*cirrus_abssf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (abs:SF (match_operand:SF 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfabss%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) +@@ -295,7 +295,7 @@ + (define_insn "*cirrus_absdf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (abs:DF (match_operand:DF 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfabsd%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-cfcvt64-disable.patch b/packages/gcc/gcc-4.1.2/arm-crunch-cfcvt64-disable.patch new file mode 100644 index 0000000000..f9280b18b5 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-cfcvt64-disable.patch @@ -0,0 +1,19 @@ +--- gcc-4.2.0/gcc/config/arm/cirrus.md-original 2007-06-25 15:32:01.000000000 +1000 ++++ gcc-4.2.0/gcc/config/arm/cirrus.md 2007-06-25 15:32:14.000000000 +1000 +@@ -325,14 +325,14 @@ + (define_insn "floatdisf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfcvt64s%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")]) + + (define_insn "floatdidf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfcvt64d%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")]) + diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-cfcvtds-disable.patch b/packages/gcc/gcc-4.1.2/arm-crunch-cfcvtds-disable.patch new file mode 100644 index 0000000000..ec09ea16a1 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-cfcvtds-disable.patch @@ -0,0 +1,32 @@ +--- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-15 10:06:24.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-15 10:07:21.000000000 +1000 +@@ -355,11 +355,12 @@ + (set_attr "cirrus" "normal")] + ) + ++; appears to be buggy - causes 20000320-1.c to fail in execute/ieee + (define_insn "*cirrus_truncdfsf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (float_truncate:SF + (match_operand:DF 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfcvtds%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) +--- gcc-4.1.2/gcc/config/arm/arm.md-truncdfsf2 2007-06-15 10:25:43.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-15 10:27:01.000000000 +1000 +@@ -3181,11 +3181,12 @@ + + ;; Truncation insns + ++;; Maverick Crunch truncdfsf2 is buggy - see cirrus.md + (define_expand "truncdfsf2" + [(set (match_operand:SF 0 "s_register_operand" "") + (float_truncate:SF + (match_operand:DF 1 "s_register_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "" + ) + diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-cfldr-disable.patch b/packages/gcc/gcc-4.1.2/arm-crunch-cfldr-disable.patch new file mode 100644 index 0000000000..502902df83 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-cfldr-disable.patch @@ -0,0 +1,68 @@ +--- gcc-4.1.2/gcc/config/arm/cirrus.md-original 2007-06-28 12:04:15.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-28 12:09:09.000000000 +1000 +@@ -436,30 +436,29 @@ + ) + + (define_insn "*cirrus_movsf_hard_insn" +- [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m") +- (match_operand:SF 1 "general_operand" "v,mE,r,v,v,r,mE,r"))] ++ [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,r,m,r,r,m") ++ (match_operand:SF 1 "general_operand" "v,r,v,v,r,mE,r"))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK + && (GET_CODE (operands[0]) != MEM + || register_operand (operands[1], SFmode))" + "@ + cfcpys%?\\t%V0, %V1 +- cfldrs%?\\t%V0, %1 + cfmvsr%?\\t%V0, %1 + cfmvrs%?\\t%0, %V1 + cfstrs%?\\t%V1, %0 + mov%?\\t%0, %1 + ldr%?\\t%0, %1\\t%@ float + str%?\\t%1, %0\\t%@ float" +- [(set_attr "length" " *, *, *, *, *, 4, 4, 4") +- (set_attr "type" " *, load1, *, *,store1, *,load1,store1") +- (set_attr "pool_range" " *, 1020, *, *, *, *,4096, *") +- (set_attr "neg_pool_range" " *, 1008, *, *, *, *,4084, *") +- (set_attr "cirrus" "normal,normal,move,normal,normal,not, not, not")] ++ [(set_attr "length" " *, *, *, *, 4, 4, 4") ++ (set_attr "type" " *, *, *,store1, *,load1,store1") ++ (set_attr "pool_range" " *, *, *, *, *,4096, *") ++ (set_attr "neg_pool_range" " *, *, *, *, *,4084, *") ++ (set_attr "cirrus" "normal,move,normal,normal,not, not, not")] + ) + + (define_insn "*cirrus_movdf_hard_insn" +- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m") +- (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,mF,r,v,v"))] ++ [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,r,m") ++ (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,r,v,v"))] + "TARGET_ARM + && TARGET_HARD_FLOAT && TARGET_MAVERICK + && (GET_CODE (operands[0]) != MEM +@@ -473,17 +472,16 @@ + case 2: return \"#\"; + case 3: case 4: return output_move_double (operands); + case 5: return \"cfcpyd%?\\t%V0, %V1\"; +- case 6: return \"cfldrd%?\\t%V0, %1\"; +- case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\"; +- case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\"; +- case 9: return \"cfstrd%?\\t%V1, %0\"; ++ case 6: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\"; ++ case 7: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\"; ++ case 8: return \"cfstrd%?\\t%V1, %0\"; + default: gcc_unreachable (); + } + }" +- [(set_attr "type" "load1,store2, *,store2,load1, *, load1, *, *,store2") +- (set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4") +- (set_attr "pool_range" " *, *, *, *, 252, *, 1020, *, *, *") +- (set_attr "neg_pool_range" " *, *, *, *, 244, *, 1008, *, *, *") +- (set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")] ++ [(set_attr "type" "load1,store2, *,store2,load1, *, *, *,store2") ++ (set_attr "length" " 4, 4, 8, 8, 8, 4, 8, 8, 4") ++ (set_attr "pool_range" " *, *, *, *, 252, *, *, *, *") ++ (set_attr "neg_pool_range" " *, *, *, *, 244, *, *, *, *") ++ (set_attr "cirrus" " not, not,not, not, not,normal,move,normal,double")] + ) + diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-cfldrstr-disable.patch b/packages/gcc/gcc-4.1.2/arm-crunch-cfldrstr-disable.patch new file mode 100644 index 0000000000..ae762e97a7 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-cfldrstr-disable.patch @@ -0,0 +1,67 @@ +--- gcc-4.1.2/gcc/config/arm/cirrus.md-original 2007-06-28 12:04:15.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-28 12:21:57.000000000 +1000 +@@ -436,30 +436,28 @@ + ) + + (define_insn "*cirrus_movsf_hard_insn" +- [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m") +- (match_operand:SF 1 "general_operand" "v,mE,r,v,v,r,mE,r"))] ++ [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,r,r,r,m") ++ (match_operand:SF 1 "general_operand" "v,r,v,r,mE,r"))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK + && (GET_CODE (operands[0]) != MEM + || register_operand (operands[1], SFmode))" + "@ + cfcpys%?\\t%V0, %V1 +- cfldrs%?\\t%V0, %1 + cfmvsr%?\\t%V0, %1 + cfmvrs%?\\t%0, %V1 +- cfstrs%?\\t%V1, %0 + mov%?\\t%0, %1 + ldr%?\\t%0, %1\\t%@ float + str%?\\t%1, %0\\t%@ float" +- [(set_attr "length" " *, *, *, *, *, 4, 4, 4") +- (set_attr "type" " *, load1, *, *,store1, *,load1,store1") +- (set_attr "pool_range" " *, 1020, *, *, *, *,4096, *") +- (set_attr "neg_pool_range" " *, 1008, *, *, *, *,4084, *") +- (set_attr "cirrus" "normal,normal,move,normal,normal,not, not, not")] ++ [(set_attr "length" " *, *, *, 4, 4, 4") ++ (set_attr "type" " *, *, *, *,load1,store1") ++ (set_attr "pool_range" " *, *, *, *,4096, *") ++ (set_attr "neg_pool_range" " *, *, *, *,4084, *") ++ (set_attr "cirrus" "normal,move,normal,not, not, not")] + ) + + (define_insn "*cirrus_movdf_hard_insn" +- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m") +- (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,mF,r,v,v"))] ++ [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,r,m") ++ (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,r,v,v"))] + "TARGET_ARM + && TARGET_HARD_FLOAT && TARGET_MAVERICK + && (GET_CODE (operands[0]) != MEM +@@ -473,17 +471,15 @@ + case 2: return \"#\"; + case 3: case 4: return output_move_double (operands); + case 5: return \"cfcpyd%?\\t%V0, %V1\"; +- case 6: return \"cfldrd%?\\t%V0, %1\"; +- case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\"; +- case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\"; +- case 9: return \"cfstrd%?\\t%V1, %0\"; ++ case 6: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\"; ++ case 7: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\"; + default: gcc_unreachable (); + } + }" +- [(set_attr "type" "load1,store2, *,store2,load1, *, load1, *, *,store2") +- (set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4") +- (set_attr "pool_range" " *, *, *, *, 252, *, 1020, *, *, *") +- (set_attr "neg_pool_range" " *, *, *, *, 244, *, 1008, *, *, *") +- (set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")] ++ [(set_attr "type" "load1,store2, *,store2,load1, *, *, *") ++ (set_attr "length" " 4, 4, 8, 8, 8, 4, 8, 8") ++ (set_attr "pool_range" " *, *, *, *, 252, *, *, *") ++ (set_attr "neg_pool_range" " *, *, *, *, 244, *, *, *") ++ (set_attr "cirrus" " not, not,not, not, not,normal,move,normal")] + ) + diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-cirrus-bugfixes.patch b/packages/gcc/gcc-4.1.2/arm-crunch-cirrus-bugfixes.patch new file mode 100644 index 0000000000..cb0af8546d --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-cirrus-bugfixes.patch @@ -0,0 +1,573 @@ +diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.c gcc-4.1.2/gcc/config/arm/arm.c +--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.c 2007-05-09 16:32:29.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-15 09:39:41.000000000 +1000 +@@ -4,6 +4,7 @@ + Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) + and Martin Simmons (@harleqn.co.uk). + More major hacks by Richard Earnshaw (rearnsha@arm.com). ++ Cirrus Crunch bugfixes by Vladimir Ivanov (vladit@nucleusys.com) + + This file is part of GCC. + +@@ -131,9 +132,17 @@ + static bool arm_xscale_rtx_costs (rtx, int, int, int *); + static bool arm_9e_rtx_costs (rtx, int, int, int *); + static int arm_address_cost (rtx); +-static bool arm_memory_load_p (rtx); ++// static bool arm_memory_load_p (rtx); + static bool arm_cirrus_insn_p (rtx); +-static void cirrus_reorg (rtx); ++// static void cirrus_reorg (rtx); ++static bool arm_mem_access_p (rtx); ++static bool cirrus_dest_regn_p (rtx, int); ++static rtx cirrus_prev_next_mach_insn (rtx, int *, int); ++static rtx cirrus_prev_mach_insn (rtx, int *); ++static rtx cirrus_next_mach_insn (rtx, int *); ++static void cirrus_reorg_branch (rtx); ++static void cirrus_reorg_bug1 (rtx); ++static void cirrus_reorg_bug10_12 (rtx); + static void arm_init_builtins (void); + static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); + static void arm_init_iwmmxt_builtins (void); +@@ -5399,41 +5412,6 @@ + || TREE_CODE (valtype) == COMPLEX_TYPE)); + } + +-/* Returns TRUE if INSN is an "LDR REG, ADDR" instruction. +- Use by the Cirrus Maverick code which has to workaround +- a hardware bug triggered by such instructions. */ +-static bool +-arm_memory_load_p (rtx insn) +-{ +- rtx body, lhs, rhs;; +- +- if (insn == NULL_RTX || GET_CODE (insn) != INSN) +- return false; +- +- body = PATTERN (insn); +- +- if (GET_CODE (body) != SET) +- return false; +- +- lhs = XEXP (body, 0); +- rhs = XEXP (body, 1); +- +- lhs = REG_OR_SUBREG_RTX (lhs); +- +- /* If the destination is not a general purpose +- register we do not have to worry. */ +- if (GET_CODE (lhs) != REG +- || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS) +- return false; +- +- /* As well as loads from memory we also have to react +- to loads of invalid constants which will be turned +- into loads from the minipool. */ +- return (GET_CODE (rhs) == MEM +- || GET_CODE (rhs) == SYMBOL_REF +- || note_invalid_constants (insn, -1, false)); +-} +- + /* Return TRUE if INSN is a Cirrus instruction. */ + static bool + arm_cirrus_insn_p (rtx insn) +@@ -5452,124 +5433,218 @@ + return attr != CIRRUS_NOT; + } + +-/* Cirrus reorg for invalid instruction combinations. */ +-static void +-cirrus_reorg (rtx first) ++/* Return TRUE if ISN does memory access. */ ++static bool ++arm_mem_access_p (rtx insn) + { +- enum attr_cirrus attr; +- rtx body = PATTERN (first); +- rtx t; +- int nops; ++ enum attr_type attr; + +- /* Any branch must be followed by 2 non Cirrus instructions. */ +- if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN) +- { +- nops = 0; +- t = next_nonnote_insn (first); ++ /* get_attr aborts on USE and CLOBBER. */ ++ if (!insn ++ || GET_CODE (insn) != INSN ++ || GET_CODE (PATTERN (insn)) == USE ++ || GET_CODE (PATTERN (insn)) == CLOBBER) ++ return 0; + +- if (arm_cirrus_insn_p (t)) +- ++ nops; ++ attr = get_attr_type (insn); + +- if (arm_cirrus_insn_p (next_nonnote_insn (t))) +- ++ nops; ++ return attr == TYPE_LOAD_BYTE ++ || attr == TYPE_LOAD1 || attr == TYPE_LOAD2 || attr == TYPE_LOAD3 || attr == TYPE_LOAD4 ++ || attr == TYPE_F_CVT ++ || attr == TYPE_F_MEM_R || attr == TYPE_R_MEM_F || attr == TYPE_F_2_R || attr == TYPE_R_2_F ++ || attr == TYPE_F_LOAD || attr == TYPE_F_LOADS || attr == TYPE_F_LOADD ++ || attr == TYPE_F_STORE || attr == TYPE_F_STORES || attr == TYPE_F_STORED ++ || attr == TYPE_STORE1 || attr == TYPE_STORE2 || attr == TYPE_STORE3 || attr == TYPE_STORE4; ++ ++} + +- while (nops --) +- emit_insn_after (gen_nop (), first); ++/* Return TRUE if destination is certain Cirrus register. */ ++static bool ++cirrus_dest_regn_p (rtx body, int regn) ++{ ++ rtx lhs; ++ int reg; ++ lhs = XEXP (body, 0); ++ if (GET_CODE (lhs) != REG) ++ return 0; + +- return; +- } ++ reg = REGNO (lhs); ++ if (REGNO_REG_CLASS (reg) != CIRRUS_REGS) ++ return 0; + +- /* (float (blah)) is in parallel with a clobber. */ +- if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) +- body = XVECEXP (body, 0, 0); ++ return reg == regn; ++} ++ ++/* Get previous/next machine instruction during Cirrus workaround scans. ++ Assume worst case (for the purpose of Cirrus workarounds) ++ for JUMP / CALL instructions. */ ++static rtx ++cirrus_prev_next_mach_insn (rtx insn, int *len, int next) ++{ ++ rtx t; ++ int l = 0; + +- if (GET_CODE (body) == SET) ++ /* It seems that we can count only on INSN length. */ ++ for ( ; ; ) + { +- rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1); ++ if (next) ++ insn = NEXT_INSN (insn); ++ else ++ insn = PREV_INSN (insn); ++ if (!insn) ++ break; + +- /* cfldrd, cfldr64, cfstrd, cfstr64 must +- be followed by a non Cirrus insn. */ +- if (get_attr_cirrus (first) == CIRRUS_DOUBLE) +- { +- if (arm_cirrus_insn_p (next_nonnote_insn (first))) +- emit_insn_after (gen_nop (), first); ++ if (GET_CODE (insn) == INSN) ++ { ++ l = get_attr_length (insn) / 4; ++ if (l) ++ break; ++ } ++ else if (GET_CODE (insn) == JUMP_INSN) ++ { ++ l = 1; ++ t = is_jump_table (insn); ++ if (t) ++ l += get_jump_table_size (t) / 4; ++ break; ++ } ++ else if (GET_CODE (insn) == CALL_INSN) ++ { ++ l = 1; ++ break; ++ } ++ } + +- return; +- } +- else if (arm_memory_load_p (first)) +- { +- unsigned int arm_regno; ++ if (len) ++ *len = l; + +- /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr, +- ldr/cfmv64hr combination where the Rd field is the same +- in both instructions must be split with a non Cirrus +- insn. Example: +- +- ldr r0, blah +- nop +- cfmvsr mvf0, r0. */ +- +- /* Get Arm register number for ldr insn. */ +- if (GET_CODE (lhs) == REG) +- arm_regno = REGNO (lhs); +- else +- { +- gcc_assert (GET_CODE (rhs) == REG); +- arm_regno = REGNO (rhs); +- } ++ return insn; ++} + +- /* Next insn. */ +- first = next_nonnote_insn (first); ++static rtx ++cirrus_prev_mach_insn (rtx insn, int *len) ++{ ++ return cirrus_prev_next_mach_insn (insn, len, 0); ++} + +- if (! arm_cirrus_insn_p (first)) +- return; ++static rtx ++cirrus_next_mach_insn (rtx insn, int *len) ++{ ++ return cirrus_prev_next_mach_insn (insn, len, 1); ++} + +- body = PATTERN (first); ++/* Cirrus reorg for branch slots. */ ++static void ++cirrus_reorg_branch (rtx insn) ++{ ++ rtx t; ++ int nops, l; + +- /* (float (blah)) is in parallel with a clobber. */ +- if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0)) +- body = XVECEXP (body, 0, 0); +- +- if (GET_CODE (body) == FLOAT) +- body = XEXP (body, 0); +- +- if (get_attr_cirrus (first) == CIRRUS_MOVE +- && GET_CODE (XEXP (body, 1)) == REG +- && arm_regno == REGNO (XEXP (body, 1))) +- emit_insn_after (gen_nop (), first); ++ /* TODO: handle jump-tables. */ ++ t = is_jump_table (insn); ++ if (t) ++ return; ++ ++ /* Any branch must be followed by 2 non Cirrus instructions. */ ++ t = insn; ++ for (nops = 2; nops > 0; ) ++ { ++ if (!cirrus_next_mach_insn (t, 0)) ++ { ++ insn = t; ++ break; ++ } ++ t = cirrus_next_mach_insn (t, &l); ++ if (arm_cirrus_insn_p (t)) ++ break; ++ nops -= l; + +- return; +- } + } + +- /* get_attr cannot accept USE or CLOBBER. */ +- if (!first +- || GET_CODE (first) != INSN +- || GET_CODE (PATTERN (first)) == USE +- || GET_CODE (PATTERN (first)) == CLOBBER) +- return; ++ while (nops-- > 0) ++ emit_insn_after (gen_nop (), insn); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */ ++} + +- attr = get_attr_cirrus (first); ++/* Cirrus reorg for bug #1 (cirrus + cfcmpxx). */ ++static void ++cirrus_reorg_bug1 (rtx insn) ++{ ++ rtx body = PATTERN (insn), body2; ++ rtx t; ++ int i, nops, l; ++ enum attr_cirrus attr; + +- /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...) +- must be followed by a non-coprocessor instruction. */ +- if (attr == CIRRUS_COMPARE) ++ /* Check if destination or clobber is Cirrus register. */ ++ if (GET_CODE (body) == PARALLEL) + { +- nops = 0; +- +- t = next_nonnote_insn (first); ++ for (i = 0; i < XVECLEN (body, 0); i++) ++ { ++ body2 = XVECEXP (body, 0, i); ++ if (GET_CODE (body2) == SET) ++ { ++ if (cirrus_dest_regn_p (body2, LAST_CIRRUS_FP_REGNUM)) ++ { ++ nops = 5; ++ goto fix; ++ } ++ } ++ else if (GET_CODE (body2) == CLOBBER) ++ { ++ if (cirrus_dest_regn_p (body2, LAST_CIRRUS_FP_REGNUM)) ++ { ++ nops = 4; ++ goto fix; ++ } ++ } ++ } ++ } ++ else if (GET_CODE (body) == SET) ++ { ++ if (cirrus_dest_regn_p (body, LAST_CIRRUS_FP_REGNUM)) ++ { ++ nops = 5; ++ goto fix; ++ } ++ } ++ return; + +- if (arm_cirrus_insn_p (t)) +- ++ nops; ++fix: ++ t = insn; ++ for ( ; nops > 0; ) ++ { ++ t = cirrus_next_mach_insn (t, &l); ++ if (!t) ++ break; ++ if (GET_CODE (t) == JUMP_INSN ++ || GET_CODE (t) == CALL_INSN) ++ { ++ nops -= l; ++ break; ++ } ++ else if (arm_cirrus_insn_p (t)) ++ { ++ attr = get_attr_cirrus (t); ++ if (attr == CIRRUS_COMPARE) ++ break; ++ } ++ nops -= l; ++ } + +- if (arm_cirrus_insn_p (next_nonnote_insn (t))) +- ++ nops; ++ while (nops-- > 0) ++ emit_insn_after (gen_nop (), insn); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */ ++} + +- while (nops --) +- emit_insn_after (gen_nop (), first); ++/* Cirrus reorg for bugs #10 and #12 (data aborts). */ ++static void ++cirrus_reorg_bug10_12 (rtx insn) ++{ ++ rtx t; + +- return; +- } ++ t = cirrus_next_mach_insn (insn, 0); ++ if (arm_cirrus_insn_p (t)) ++ if (TARGET_CIRRUS_D0 || ++ get_attr_cirrus (t) == CIRRUS_DOUBLE) ++ emit_insn_after (gen_nop (), insn); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */ + } + + /* Return TRUE if X references a SYMBOL_REF. */ +@@ -7727,7 +7796,7 @@ + { + Mnode * mp; + Mnode * nmp; +- int align64 = 0; ++ int align64 = 0, stuffnop = 0; + + if (ARM_DOUBLEWORD_ALIGN) + for (mp = minipool_vector_head; mp != NULL; mp = mp->next) +@@ -7742,8 +7811,27 @@ + ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n", + INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4); + ++ /* Check if branch before minipool is already stuffed with nops. */ ++ if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1) ++ { ++ rtx t; ++ ++ t = prev_active_insn (scan); ++ if (GET_CODE (t) != INSN ++ || PATTERN (t) != const0_rtx) ++ stuffnop = 1; ++ } + scan = emit_label_after (gen_label_rtx (), scan); + scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan); ++ /* Last instruction was branch, so put two non-Cirrus opcodes. */ ++ if (stuffnop) ++ { ++#if TARGET_CIRRUS /* This is doubling up on nops, so I don't think this is a good idea */ ++ emit_insn_before (gen_nop (), scan); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */ ++ emit_insn_before (gen_nop (), scan); /* WARNING: this appears to cause "bad immediate value for offset" errors in the assembler */ ++#endif ++ } ++ + scan = emit_label_after (minipool_vector_label, scan); + + for (mp = minipool_vector_head; mp != NULL; mp = nmp) +@@ -8151,15 +8239,38 @@ + gcc_assert (GET_CODE (insn) == NOTE); + minipool_pad = 0; + ++#if TARGET_CIRRUS /* I think this is a double-up */ ++ /* Scan all the insn and fix Cirrus issues. */ ++ if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1) ++ { ++ rtx t, s; ++ ++ for (t = cirrus_next_mach_insn (insn, 0); t; t = cirrus_next_mach_insn (t, 0)) ++ if (arm_mem_access_p (t)) ++ cirrus_reorg_bug10_12 (t); ++ ++ if (TARGET_CIRRUS_D0) ++ for (t = cirrus_next_mach_insn (insn, 0); t; t = cirrus_next_mach_insn (t, 0)) ++ if (arm_cirrus_insn_p (t)) ++ cirrus_reorg_bug1 (t); ++ ++ /* Find last insn. */ ++ for (t = insn; ; t = s) ++ { ++ s = cirrus_next_mach_insn (t, 0); ++ if (!s) ++ break; ++ } ++ /* Scan backward and fix branches. - WARNING: appears to cause "bad immediate value for offset" problems! */ ++ for ( ; t; t = cirrus_prev_mach_insn (t, 0)) ++ if (GET_CODE (t) == JUMP_INSN ++ || GET_CODE (t) == CALL_INSN) ++ cirrus_reorg_branch (t); ++ } ++#endif + /* Scan all the insns and record the operands that will need fixing. */ + for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn)) + { +- if (TARGET_CIRRUS_FIX_INVALID_INSNS +- && (arm_cirrus_insn_p (insn) +- || GET_CODE (insn) == JUMP_INSN +- || arm_memory_load_p (insn))) +- cirrus_reorg (insn); +- + if (GET_CODE (insn) == BARRIER) + push_minipool_barrier (insn, address); + else if (INSN_P (insn)) +@@ -11755,16 +11910,10 @@ + || get_attr_conds (this_insn) != CONDS_NOCOND) + fail = TRUE; + +- /* A conditional cirrus instruction must be followed by +- a non Cirrus instruction. However, since we +- conditionalize instructions in this function and by +- the time we get here we can't add instructions +- (nops), because shorten_branches() has already been +- called, we will disable conditionalizing Cirrus +- instructions to be safe. */ +- if (GET_CODE (scanbody) != USE +- && GET_CODE (scanbody) != CLOBBER +- && get_attr_cirrus (this_insn) != CIRRUS_NOT) ++ /* To avoid erratic behaviour, we avoid conditional Cirrus ++ instructions when doing workarounds. */ ++ if (arm_cirrus_insn_p(this_insn) ++ && (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1)) + fail = TRUE; + break; + +diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.h gcc-4.1.2/gcc/config/arm/arm.h +--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.h 2005-11-05 01:02:51.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.h 2007-05-15 10:15:05.000000000 +1000 +@@ -5,6 +5,7 @@ + and Martin Simmons (@harleqn.co.uk). + More major hacks by Richard Earnshaw (rearnsha@arm.com) + Minor hacks by Nick Clifton (nickc@cygnus.com) ++ Cirrus Crunch fixes by Vladimir Ivanov (vladitx@nucleusys.com) + + This file is part of GCC. + +@@ -140,7 +141,9 @@ + %{msoft-float:%{mhard-float: \ + %e-msoft-float and -mhard_float may not be used together}} \ + %{mbig-endian:%{mlittle-endian: \ +- %e-mbig-endian and -mlittle-endian may not be used together}}" ++ %e-mbig-endian and -mlittle-endian may not be used together}} \ ++%{mfix-crunch-d0:%{mfix-crunch-d1: \ ++ %e-mfix-crunch-d0 and -mfix-crunch-d1 may not be used together}}" + + #ifndef CC1_SPEC + #define CC1_SPEC "" +@@ -179,6 +182,9 @@ + #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) + #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA) + #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK) ++#define TARGET_CIRRUS (arm_arch_cirrus) ++#define TARGET_CIRRUS_D0 0 /* (target_flags & ARM_FLAG_CIRRUS_D0) */ ++#define TARGET_CIRRUS_D1 1 /* (target_flags & ARM_FLAG_CIRRUS_D1) */ + #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP) + #define TARGET_IWMMXT (arm_arch_iwmmxt) + #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM) +diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.opt gcc-4.1.2/gcc/config/arm/arm.opt +--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.opt 2005-11-05 01:02:51.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.opt 2007-05-15 10:09:31.000000000 +1000 +@@ -68,6 +68,14 @@ + Target Report Mask(CIRRUS_FIX_INVALID_INSNS) + Cirrus: Place NOPs to avoid invalid instruction combinations + ++fix-crunch-d0 ++Target Report Mask(ARM_FLAG_CIRRUS_D0) ++Cirrus: workarounds for Crunch coprocessor revision D0 ++ ++fix-crunch-d1 ++Target Report Mask(ARM_FLAG_CIRRUS_D1) ++Cirrus: workarounds for Crunch coprocessor revision D1 ++ + mcpu= + Target RejectNegative Joined + Specify the name of the target CPU +diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/doc/invoke.texi gcc-4.1.2/gcc/doc/invoke.texi +--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/doc/invoke.texi 2006-09-26 07:21:58.000000000 +1000 ++++ gcc-4.1.2/gcc/doc/invoke.texi 2007-05-15 10:07:04.000000000 +1000 +@@ -408,7 +408,7 @@ + -msingle-pic-base -mno-single-pic-base @gol + -mpic-register=@var{reg} @gol + -mnop-fun-dllimport @gol +--mcirrus-fix-invalid-insns -mno-cirrus-fix-invalid-insns @gol ++-mfix-crunch-d0 -mfix-crunch-d1 @gol + -mpoke-function-name @gol + -mthumb -marm @gol + -mtpcs-frame -mtpcs-leaf-frame @gol +@@ -7435,17 +7435,12 @@ + Specify the register to be used for PIC addressing. The default is R10 + unless stack-checking is enabled, when R9 is used. + +-@item -mcirrus-fix-invalid-insns +-@opindex mcirrus-fix-invalid-insns +-@opindex mno-cirrus-fix-invalid-insns +-Insert NOPs into the instruction stream to in order to work around +-problems with invalid Maverick instruction combinations. This option +-is only valid if the @option{-mcpu=ep9312} option has been used to +-enable generation of instructions for the Cirrus Maverick floating +-point co-processor. This option is not enabled by default, since the +-problem is only present in older Maverick implementations. The default +-can be re-enabled by use of the @option{-mno-cirrus-fix-invalid-insns} +-switch. ++@item -mfix-crunch-d0 ++@itemx -mfix-crunch-d1 ++@opindex mfix-crunch-d0 ++@opindex mfix-crunch-d1 ++Enable workarounds for the Cirrus MaverickCrunch coprocessor revisions ++D0 and D1 respectively. + + @item -mpoke-function-name + @opindex mpoke-function-name diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-compare-geu.patch b/packages/gcc/gcc-4.1.2/arm-crunch-compare-geu.patch new file mode 100644 index 0000000000..3d27cc1d9d --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-compare-geu.patch @@ -0,0 +1,48 @@ +--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-08 06:39:41.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-08 06:41:00.000000000 +1000 +@@ -7125,6 +7125,22 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match GEU for MAVERICK. ++(define_insn "*arm_bgeu" ++ [(set (pc) ++ (if_then_else (geu (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && (TARGET_MAVERICK)" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ if (get_attr_cirrus (prev_active_insn(insn)) == CIRRUS_COMPARE) ++ return \"beq\\t%l0\;bvs\\t%l0\"; else return \"bge\\t%l0\;nop\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ + ; Special pattern to match UNLT for MAVERICK - UGLY since we need to test for Z=0 && V=0. + (define_insn "*arm_bunlt" + [(set (pc) +@@ -7240,6 +7256,22 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match reversed GEU for MAVERICK. ++(define_insn "*arm_bgeu_reversed" ++ [(set (pc) ++ (if_then_else (geu (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && (TARGET_MAVERICK)" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ + ; Special pattern to match reversed UNLT for MAVERICK. + (define_insn "*arm_bunlt_reversed" + [(set (pc) diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-compare-new.patch b/packages/gcc/gcc-4.1.2/arm-crunch-compare-new.patch new file mode 100644 index 0000000000..101288375f --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-compare-new.patch @@ -0,0 +1,400 @@ +diff -urN gcc-4.1.2/gcc/config/arm/arm.c ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.c +--- gcc-4.1.2/gcc/config/arm/arm.c 2007-05-31 12:39:48.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-29 17:19:38.000000000 +1000 +@@ -11427,26 +11427,53 @@ + /* These encodings assume that AC=1 in the FPA system control + byte. This allows us to handle all cases except UNEQ and + LTGT. */ +- switch (comp_code) +- { +- case GE: return ARM_GE; +- case GT: return ARM_GT; +- case LE: return ARM_LS; +- case LT: return ARM_MI; +- case NE: return ARM_NE; +- case EQ: return ARM_EQ; +- case ORDERED: return ARM_VC; +- case UNORDERED: return ARM_VS; +- case UNLT: return ARM_LT; +- case UNLE: return ARM_LE; +- case UNGT: return ARM_HI; +- case UNGE: return ARM_PL; +- /* UNEQ and LTGT do not have a representation. */ +- case UNEQ: /* Fall through. */ +- case LTGT: /* Fall through. */ +- default: gcc_unreachable (); +- } +- ++ if (!TARGET_MAVERICK) ++ { ++ switch (comp_code) ++ { ++ case GE: return ARM_GE; ++ case GT: return ARM_GT; ++ case LE: return ARM_LS; ++ case LT: return ARM_MI; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case ORDERED: return ARM_VC; ++ case UNORDERED: return ARM_VS; ++ case UNLT: return ARM_LT; ++ case UNLE: return ARM_LE; ++ case UNGT: return ARM_HI; ++ case UNGE: return ARM_PL; ++ /* UNEQ and LTGT do not have a representation. */ ++ case UNEQ: /* Fall through. */ ++ case LTGT: /* Fall through. */ ++ default: gcc_unreachable (); ++ } ++ } ++ else ++ { ++ /* CIRRUS */ ++ switch (comp_code) ++ { ++#if 1 ++ case GT: return ARM_VS; ++ case LE: return ARM_LE; ++ case LT: return ARM_LT; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case UNLE: return ARM_VC; ++ case UNGT: return ARM_GT; ++ case UNGE: return ARM_GE; ++ case UNEQ: return ARM_PL; ++ case LTGT: return ARM_MI; ++ /* These do not have a representation. */ ++ case GE: /* Fall through. -UNGE wrong atm */ ++ case UNLT: /* Fall through. -LT wrong atm */ ++ case ORDERED: /* Fall through. -AL wrong atm */ ++ case UNORDERED: /* Fall through. -AL wrong atm */ ++#endif ++ default: gcc_unreachable (); ++ } ++ } + case CC_SWPmode: + switch (comp_code) + { +diff -urN gcc-4.1.2/gcc/config/arm/arm.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.md +--- gcc-4.1.2/gcc/config/arm/arm.md 2007-05-31 12:39:48.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-29 15:17:18.000000000 +1000 +@@ -6952,10 +6952,11 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++;broken on cirrus + (define_expand "bge" + [(set (pc) + (if_then_else (ge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM" ++ "TARGET_ARM" ;; && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +@@ -6988,6 +6989,7 @@ + "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" + ) + ++; broken on cirrus? + (define_expand "bgeu" + [(set (pc) + (if_then_else (geu (match_dup 1) (const_int 0)) +@@ -7031,14 +7033,15 @@ + (if_then_else (ungt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);" + ) + +-(define_expand "bunlt" ++; broken for cirrus ++(define_expand "bunlt" + [(set (pc) + (if_then_else (unlt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);" +@@ -7049,7 +7052,7 @@ + (if_then_else (unge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7058,7 +7061,7 @@ + (if_then_else (unle (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7069,7 +7072,7 @@ + (if_then_else (uneq (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7078,7 +7081,7 @@ + (if_then_else (ltgt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7086,7 +7089,7 @@ + ;; Patterns to match conditional branch insns. + ;; + +-; Special pattern to match UNEQ. ++; Special pattern to match UNEQ for FPA and VFP. + (define_insn "*arm_buneq" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7102,7 +7105,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match LTGT. ++; Special pattern to match LTGT for FPA and VFP. + (define_insn "*arm_bltgt" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7118,6 +7121,38 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match GE for MAVERICK. ++(define_insn "*arm_bge" ++ [(set (pc) ++ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ if (get_attr_cirrus (prev_active_insn(insn)) == CIRRUS_COMPARE) ++ return \"beq\\t%l0\;bvs\\t%l0\"; else return \"bge\\t%l0\;nop\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++; Special pattern to match UNLT for MAVERICK - UGLY since we need to test for Z=0 && V=0. ++(define_insn "*arm_bunlt" ++ [(set (pc) ++ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ + (define_insn "*arm_cond_branch" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7137,7 +7172,7 @@ + (set_attr "type" "branch")] + ) + +-; Special pattern to match reversed UNEQ. ++; Special pattern to match reversed UNEQ for FPA and VFP. + (define_insn "*arm_buneq_reversed" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7153,7 +7188,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match reversed LTGT. ++; Special pattern to match reversed LTGT for FPA and VFP. + (define_insn "*arm_bltgt_reversed" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7169,6 +7204,39 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match reversed GE for MAVERICK - UGLY since we need to tst for Z=0 && N=0. ++(define_insn "*arm_bge_reversed" ++ [(set (pc) ++ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ if (get_attr_cirrus (prev_active_insn(insn)) == CIRRUS_COMPARE) ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; else return \"bge\\t.+12\;b\\t%l0\;nop\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ ++; Special pattern to match reversed UNLT for MAVERICK. ++(define_insn "*arm_bunlt_reversed" ++ [(set (pc) ++ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++ + (define_insn "*arm_cond_branch_reversed" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7220,8 +7288,9 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++;; broken for cirrus - definitely + (define_expand "sge" + [(set (match_operand:SI 0 "s_register_operand" "") + (ge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM" ++ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +@@ -7227,6 +7296,14 @@ + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SGE these can not be represented with MAVERICK ++; (define_expand "sge" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "slt" + [(set (match_operand:SI 0 "s_register_operand" "") + (lt:SI (match_dup 1) (const_int 0)))] +@@ -7248,6 +7325,7 @@ + "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" + ) + ++;; broken for cirrus - maybe + (define_expand "sgeu" + [(set (match_operand:SI 0 "s_register_operand" "") + (geu:SI (match_dup 1) (const_int 0)))] +@@ -7255,6 +7333,14 @@ + "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SGEU these may not be represented with MAVERICK? ++; (define_expand "sgeu" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "sltu" + [(set (match_operand:SI 0 "s_register_operand" "") + (ltu:SI (match_dup 1) (const_int 0)))] +@@ -7281,7 +7367,7 @@ + (define_expand "sungt" + [(set (match_operand:SI 0 "s_register_operand" "") + (ungt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7289,23 +7375,32 @@ + (define_expand "sunge" + [(set (match_operand:SI 0 "s_register_operand" "") + (unge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, + arm_compare_op1);" + ) + ++; broken for cirrus + (define_expand "sunlt" + [(set (match_operand:SI 0 "s_register_operand" "") + (unlt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, + arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SUNLT these can't be represented with MAVERICK ++; (define_expand "sunlt" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (unlt:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "sunle" + [(set (match_operand:SI 0 "s_register_operand" "") + (unle:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7371,7 +7466,7 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) + FAIL; + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); +@@ -7390,7 +7485,8 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) ++ + FAIL; + + /* When compiling for SOFT_FLOAT, ensure both arms are in registers. +@@ -7409,13 +7505,13 @@ + (if_then_else:DF (match_operand 1 "arm_comparison_operator" "") + (match_operand:DF 2 "s_register_operand" "") + (match_operand:DF 3 "arm_float_add_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + " + { + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code==GE || code == UNLT || code == ORDERED || code == UNORDERED))) + FAIL; + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-compare-new2.patch b/packages/gcc/gcc-4.1.2/arm-crunch-compare-new2.patch new file mode 100644 index 0000000000..466da338d4 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-compare-new2.patch @@ -0,0 +1,400 @@ +diff -urN gcc-4.1.2/gcc/config/arm/arm.c ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.c +--- gcc-4.1.2/gcc/config/arm/arm.c 2007-05-31 12:39:48.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-29 17:19:38.000000000 +1000 +@@ -11427,26 +11427,53 @@ + /* These encodings assume that AC=1 in the FPA system control + byte. This allows us to handle all cases except UNEQ and + LTGT. */ +- switch (comp_code) +- { +- case GE: return ARM_GE; +- case GT: return ARM_GT; +- case LE: return ARM_LS; +- case LT: return ARM_MI; +- case NE: return ARM_NE; +- case EQ: return ARM_EQ; +- case ORDERED: return ARM_VC; +- case UNORDERED: return ARM_VS; +- case UNLT: return ARM_LT; +- case UNLE: return ARM_LE; +- case UNGT: return ARM_HI; +- case UNGE: return ARM_PL; +- /* UNEQ and LTGT do not have a representation. */ +- case UNEQ: /* Fall through. */ +- case LTGT: /* Fall through. */ +- default: gcc_unreachable (); +- } +- ++ if ((!TARGET_MAVERICK) || (get_attr_cirrus (comparison) != CIRRUS_COMPARE)) ++ { ++ switch (comp_code) ++ { ++ case GE: return ARM_GE; ++ case GT: return ARM_GT; ++ case LE: return ARM_LS; ++ case LT: return ARM_MI; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case ORDERED: return ARM_VC; ++ case UNORDERED: return ARM_VS; ++ case UNLT: return ARM_LT; ++ case UNLE: return ARM_LE; ++ case UNGT: return ARM_HI; ++ case UNGE: return ARM_PL; ++ /* UNEQ and LTGT do not have a representation. */ ++ case UNEQ: /* Fall through. */ ++ case LTGT: /* Fall through. */ ++ default: gcc_unreachable (); ++ } ++ } ++ else ++ { ++ /* CIRRUS */ ++ switch (comp_code) ++ { ++#if 1 ++ case GT: return ARM_VS; ++ case LE: return ARM_LE; ++ case LT: return ARM_LT; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case UNLE: return ARM_VC; ++ case UNGT: return ARM_GT; ++ case UNGE: return ARM_GE; ++ case UNEQ: return ARM_PL; ++ case LTGT: return ARM_MI; ++ /* These do not have a representation. */ ++ case GE: /* Fall through. -UNGE wrong atm */ ++ case UNLT: /* Fall through. -LT wrong atm */ ++ case ORDERED: /* Fall through. -AL wrong atm */ ++ case UNORDERED: /* Fall through. -AL wrong atm */ ++#endif ++ default: gcc_unreachable (); ++ } ++ } + case CC_SWPmode: + switch (comp_code) + { +diff -urN gcc-4.1.2/gcc/config/arm/arm.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.md +--- gcc-4.1.2/gcc/config/arm/arm.md 2007-05-31 12:39:48.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-29 15:17:18.000000000 +1000 +@@ -6952,10 +6952,11 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++;broken on cirrus + (define_expand "bge" + [(set (pc) + (if_then_else (ge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM" ++ "TARGET_ARM" ;; && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +@@ -6988,6 +6989,7 @@ + "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" + ) + ++; broken on cirrus? + (define_expand "bgeu" + [(set (pc) + (if_then_else (geu (match_dup 1) (const_int 0)) +@@ -7031,14 +7033,15 @@ + (if_then_else (ungt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);" + ) + +-(define_expand "bunlt" ++; broken for cirrus ++(define_expand "bunlt" + [(set (pc) + (if_then_else (unlt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);" +@@ -7049,7 +7052,7 @@ + (if_then_else (unge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7058,7 +7061,7 @@ + (if_then_else (unle (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7069,7 +7072,7 @@ + (if_then_else (uneq (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7078,7 +7081,7 @@ + (if_then_else (ltgt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7086,7 +7089,7 @@ + ;; Patterns to match conditional branch insns. + ;; + +-; Special pattern to match UNEQ. ++; Special pattern to match UNEQ for FPA and VFP. + (define_insn "*arm_buneq" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7102,7 +7105,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match LTGT. ++; Special pattern to match LTGT for FPA and VFP. + (define_insn "*arm_bltgt" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7118,6 +7121,38 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match GE for MAVERICK. ++(define_insn "*arm_bge" ++ [(set (pc) ++ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++; Special pattern to match UNLT for MAVERICK - UGLY since we need to test for Z=0 && V=0. ++(define_insn "*arm_bunlt" ++ [(set (pc) ++ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ + (define_insn "*arm_cond_branch" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7137,7 +7172,7 @@ + (set_attr "type" "branch")] + ) + +-; Special pattern to match reversed UNEQ. ++; Special pattern to match reversed UNEQ for FPA and VFP. + (define_insn "*arm_buneq_reversed" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7153,7 +7188,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match reversed LTGT. ++; Special pattern to match reversed LTGT for FPA and VFP. + (define_insn "*arm_bltgt_reversed" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7169,6 +7204,39 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match reversed GE for MAVERICK - UGLY since we need to tst for Z=0 && N=0. ++(define_insn "*arm_bge_reversed" ++ [(set (pc) ++ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && (get_attr_cirrus (prev_active_insn(insn)) == CIRRUS_COMPARE)" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ ++; Special pattern to match reversed UNLT for MAVERICK. ++(define_insn "*arm_bunlt_reversed" ++ [(set (pc) ++ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++ + (define_insn "*arm_cond_branch_reversed" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7220,8 +7288,9 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++;; broken for cirrus - definitely + (define_expand "sge" + [(set (match_operand:SI 0 "s_register_operand" "") + (ge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM" ++ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +@@ -7227,6 +7296,14 @@ + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SGE these can not be represented with MAVERICK ++; (define_expand "sge" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "slt" + [(set (match_operand:SI 0 "s_register_operand" "") + (lt:SI (match_dup 1) (const_int 0)))] +@@ -7248,6 +7325,7 @@ + "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" + ) + ++;; broken for cirrus - maybe + (define_expand "sgeu" + [(set (match_operand:SI 0 "s_register_operand" "") + (geu:SI (match_dup 1) (const_int 0)))] +@@ -7255,6 +7333,14 @@ + "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SGEU these may not be represented with MAVERICK? ++; (define_expand "sgeu" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "sltu" + [(set (match_operand:SI 0 "s_register_operand" "") + (ltu:SI (match_dup 1) (const_int 0)))] +@@ -7281,7 +7367,7 @@ + (define_expand "sungt" + [(set (match_operand:SI 0 "s_register_operand" "") + (ungt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7289,23 +7375,32 @@ + (define_expand "sunge" + [(set (match_operand:SI 0 "s_register_operand" "") + (unge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, + arm_compare_op1);" + ) + ++; broken for cirrus + (define_expand "sunlt" + [(set (match_operand:SI 0 "s_register_operand" "") + (unlt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, + arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SUNLT these can't be represented with MAVERICK ++; (define_expand "sunlt" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (unlt:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "sunle" + [(set (match_operand:SI 0 "s_register_operand" "") + (unle:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7371,7 +7466,7 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) + FAIL; + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); +@@ -7390,7 +7485,8 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) ++ + FAIL; + + /* When compiling for SOFT_FLOAT, ensure both arms are in registers. +@@ -7409,13 +7505,13 @@ + (if_then_else:DF (match_operand 1 "arm_comparison_operator" "") + (match_operand:DF 2 "s_register_operand" "") + (match_operand:DF 3 "arm_float_add_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + " + { + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code==GE || code == UNLT || code == ORDERED || code == UNORDERED))) + FAIL; + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-compare-new3.patch b/packages/gcc/gcc-4.1.2/arm-crunch-compare-new3.patch new file mode 100644 index 0000000000..49bd517d21 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-compare-new3.patch @@ -0,0 +1,400 @@ +diff -urN gcc-4.1.2/gcc/config/arm/arm.c ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.c +--- gcc-4.1.2/gcc/config/arm/arm.c 2007-05-31 12:39:48.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-29 17:19:38.000000000 +1000 +@@ -11427,26 +11427,53 @@ + /* These encodings assume that AC=1 in the FPA system control + byte. This allows us to handle all cases except UNEQ and + LTGT. */ +- switch (comp_code) +- { +- case GE: return ARM_GE; +- case GT: return ARM_GT; +- case LE: return ARM_LS; +- case LT: return ARM_MI; +- case NE: return ARM_NE; +- case EQ: return ARM_EQ; +- case ORDERED: return ARM_VC; +- case UNORDERED: return ARM_VS; +- case UNLT: return ARM_LT; +- case UNLE: return ARM_LE; +- case UNGT: return ARM_HI; +- case UNGE: return ARM_PL; +- /* UNEQ and LTGT do not have a representation. */ +- case UNEQ: /* Fall through. */ +- case LTGT: /* Fall through. */ +- default: gcc_unreachable (); +- } +- ++ if ((!TARGET_MAVERICK) || (get_attr_cirrus (prev_active_insn(comparison)) != CIRRUS_COMPARE)) ++ { ++ switch (comp_code) ++ { ++ case GE: return ARM_GE; ++ case GT: return ARM_GT; ++ case LE: return ARM_LS; ++ case LT: return ARM_MI; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case ORDERED: return ARM_VC; ++ case UNORDERED: return ARM_VS; ++ case UNLT: return ARM_LT; ++ case UNLE: return ARM_LE; ++ case UNGT: return ARM_HI; ++ case UNGE: return ARM_PL; ++ /* UNEQ and LTGT do not have a representation. */ ++ case UNEQ: /* Fall through. */ ++ case LTGT: /* Fall through. */ ++ default: gcc_unreachable (); ++ } ++ } ++ else ++ { ++ /* CIRRUS */ ++ switch (comp_code) ++ { ++#if 1 ++ case GT: return ARM_VS; ++ case LE: return ARM_LE; ++ case LT: return ARM_LT; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case UNLE: return ARM_VC; ++ case UNGT: return ARM_GT; ++ case UNGE: return ARM_GE; ++ case UNEQ: return ARM_PL; ++ case LTGT: return ARM_MI; ++ /* These do not have a representation. */ ++ case GE: /* Fall through. -UNGE wrong atm */ ++ case UNLT: /* Fall through. -LT wrong atm */ ++ case ORDERED: /* Fall through. -AL wrong atm */ ++ case UNORDERED: /* Fall through. -AL wrong atm */ ++#endif ++ default: gcc_unreachable (); ++ } ++ } + case CC_SWPmode: + switch (comp_code) + { +diff -urN gcc-4.1.2/gcc/config/arm/arm.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.md +--- gcc-4.1.2/gcc/config/arm/arm.md 2007-05-31 12:39:48.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-29 15:17:18.000000000 +1000 +@@ -6952,10 +6952,11 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++;broken on cirrus + (define_expand "bge" + [(set (pc) + (if_then_else (ge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM" ++ "TARGET_ARM" ;; && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +@@ -6988,6 +6989,7 @@ + "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" + ) + ++; broken on cirrus? + (define_expand "bgeu" + [(set (pc) + (if_then_else (geu (match_dup 1) (const_int 0)) +@@ -7031,14 +7033,15 @@ + (if_then_else (ungt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);" + ) + +-(define_expand "bunlt" ++; broken for cirrus ++(define_expand "bunlt" + [(set (pc) + (if_then_else (unlt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);" +@@ -7049,7 +7052,7 @@ + (if_then_else (unge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7058,7 +7061,7 @@ + (if_then_else (unle (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7069,7 +7072,7 @@ + (if_then_else (uneq (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7078,7 +7081,7 @@ + (if_then_else (ltgt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7086,7 +7089,7 @@ + ;; Patterns to match conditional branch insns. + ;; + +-; Special pattern to match UNEQ. ++; Special pattern to match UNEQ for FPA and VFP. + (define_insn "*arm_buneq" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7102,7 +7105,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match LTGT. ++; Special pattern to match LTGT for FPA and VFP. + (define_insn "*arm_bltgt" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7118,6 +7121,38 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match GE for MAVERICK. ++(define_insn "*arm_bge" ++ [(set (pc) ++ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ if (get_attr_cirrus (prev_active_insn(insn)) == CIRRUS_COMPARE) ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++; Special pattern to match UNLT for MAVERICK - UGLY since we need to test for Z=0 && V=0. ++(define_insn "*arm_bunlt" ++ [(set (pc) ++ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ + (define_insn "*arm_cond_branch" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7137,7 +7172,7 @@ + (set_attr "type" "branch")] + ) + +-; Special pattern to match reversed UNEQ. ++; Special pattern to match reversed UNEQ for FPA and VFP. + (define_insn "*arm_buneq_reversed" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7153,7 +7188,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match reversed LTGT. ++; Special pattern to match reversed LTGT for FPA and VFP. + (define_insn "*arm_bltgt_reversed" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7169,6 +7204,39 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match reversed GE for MAVERICK - UGLY since we need to tst for Z=0 && N=0. ++(define_insn "*arm_bge_reversed" ++ [(set (pc) ++ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ if (get_attr_cirrus (prev_active_insn(insn)) == CIRRUS_COMPARE) ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ ++; Special pattern to match reversed UNLT for MAVERICK. ++(define_insn "*arm_bunlt_reversed" ++ [(set (pc) ++ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++ + (define_insn "*arm_cond_branch_reversed" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7220,8 +7288,9 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++;; broken for cirrus - definitely + (define_expand "sge" + [(set (match_operand:SI 0 "s_register_operand" "") + (ge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM" ++ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +@@ -7227,6 +7296,14 @@ + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SGE these can not be represented with MAVERICK ++; (define_expand "sge" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "slt" + [(set (match_operand:SI 0 "s_register_operand" "") + (lt:SI (match_dup 1) (const_int 0)))] +@@ -7248,6 +7325,7 @@ + "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" + ) + ++;; broken for cirrus - maybe + (define_expand "sgeu" + [(set (match_operand:SI 0 "s_register_operand" "") + (geu:SI (match_dup 1) (const_int 0)))] +@@ -7255,6 +7333,14 @@ + "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SGEU these may not be represented with MAVERICK? ++; (define_expand "sgeu" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "sltu" + [(set (match_operand:SI 0 "s_register_operand" "") + (ltu:SI (match_dup 1) (const_int 0)))] +@@ -7281,7 +7367,7 @@ + (define_expand "sungt" + [(set (match_operand:SI 0 "s_register_operand" "") + (ungt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7289,23 +7375,32 @@ + (define_expand "sunge" + [(set (match_operand:SI 0 "s_register_operand" "") + (unge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, + arm_compare_op1);" + ) + ++; broken for cirrus + (define_expand "sunlt" + [(set (match_operand:SI 0 "s_register_operand" "") + (unlt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, + arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SUNLT these can't be represented with MAVERICK ++; (define_expand "sunlt" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (unlt:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "sunle" + [(set (match_operand:SI 0 "s_register_operand" "") + (unle:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7371,7 +7466,7 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) + FAIL; + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); +@@ -7390,7 +7485,8 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) ++ + FAIL; + + /* When compiling for SOFT_FLOAT, ensure both arms are in registers. +@@ -7409,13 +7505,13 @@ + (if_then_else:DF (match_operand 1 "arm_comparison_operator" "") + (match_operand:DF 2 "s_register_operand" "") + (match_operand:DF 3 "arm_float_add_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + " + { + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code==GE || code == UNLT || code == ORDERED || code == UNORDERED))) + FAIL; + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-compare-new4.patch b/packages/gcc/gcc-4.1.2/arm-crunch-compare-new4.patch new file mode 100644 index 0000000000..e4a2789068 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-compare-new4.patch @@ -0,0 +1,400 @@ +diff -urN gcc-4.1.2/gcc/config/arm/arm.c ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.c +--- gcc-4.1.2/gcc/config/arm/arm.c 2007-05-31 12:39:48.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-29 17:19:38.000000000 +1000 +@@ -11427,26 +11427,53 @@ + /* These encodings assume that AC=1 in the FPA system control + byte. This allows us to handle all cases except UNEQ and + LTGT. */ +- switch (comp_code) +- { +- case GE: return ARM_GE; +- case GT: return ARM_GT; +- case LE: return ARM_LS; +- case LT: return ARM_MI; +- case NE: return ARM_NE; +- case EQ: return ARM_EQ; +- case ORDERED: return ARM_VC; +- case UNORDERED: return ARM_VS; +- case UNLT: return ARM_LT; +- case UNLE: return ARM_LE; +- case UNGT: return ARM_HI; +- case UNGE: return ARM_PL; +- /* UNEQ and LTGT do not have a representation. */ +- case UNEQ: /* Fall through. */ +- case LTGT: /* Fall through. */ +- default: gcc_unreachable (); +- } +- ++ if (!TARGET_MAVERICK) ++ { ++ switch (comp_code) ++ { ++ case GE: return ARM_GE; ++ case GT: return ARM_GT; ++ case LE: return ARM_LS; ++ case LT: return ARM_MI; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case ORDERED: return ARM_VC; ++ case UNORDERED: return ARM_VS; ++ case UNLT: return ARM_LT; ++ case UNLE: return ARM_LE; ++ case UNGT: return ARM_HI; ++ case UNGE: return ARM_PL; ++ /* UNEQ and LTGT do not have a representation. */ ++ case UNEQ: /* Fall through. */ ++ case LTGT: /* Fall through. */ ++ default: gcc_unreachable (); ++ } ++ } ++ else ++ { ++ /* CIRRUS */ ++ switch (comp_code) ++ { ++#if 1 ++ case GT: return ARM_VS; ++ case LE: return ARM_LE; ++ case LT: return ARM_LT; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case UNLE: return ARM_VC; ++ case UNGT: return ARM_GT; ++ case UNGE: return ARM_GE; ++ case UNEQ: return ARM_PL; ++ case LTGT: return ARM_MI; ++ /* These do not have a representation. */ ++ case GE: /* Fall through. -UNGE wrong atm */ ++ case UNLT: /* Fall through. -LT wrong atm */ ++ case ORDERED: /* Fall through. -AL wrong atm */ ++ case UNORDERED: /* Fall through. -AL wrong atm */ ++#endif ++ default: gcc_unreachable (); ++ } ++ } + case CC_SWPmode: + switch (comp_code) + { +diff -urN gcc-4.1.2/gcc/config/arm/arm.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.md +--- gcc-4.1.2/gcc/config/arm/arm.md 2007-05-31 12:39:48.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-29 15:17:18.000000000 +1000 +@@ -6952,10 +6952,11 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++;broken on cirrus + (define_expand "bge" + [(set (pc) + (if_then_else (ge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM" ++ "TARGET_ARM" ;; && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +@@ -6988,6 +6989,7 @@ + "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" + ) + ++; broken on cirrus? + (define_expand "bgeu" + [(set (pc) + (if_then_else (geu (match_dup 1) (const_int 0)) +@@ -7031,14 +7033,15 @@ + (if_then_else (ungt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);" + ) + +-(define_expand "bunlt" ++; broken for cirrus ++(define_expand "bunlt" + [(set (pc) + (if_then_else (unlt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);" +@@ -7049,7 +7052,7 @@ + (if_then_else (unge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7058,7 +7061,7 @@ + (if_then_else (unle (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7069,7 +7072,7 @@ + (if_then_else (uneq (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7078,7 +7081,7 @@ + (if_then_else (ltgt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7086,7 +7089,7 @@ + ;; Patterns to match conditional branch insns. + ;; + +-; Special pattern to match UNEQ. ++; Special pattern to match UNEQ for FPA and VFP. + (define_insn "*arm_buneq" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7102,7 +7105,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match LTGT. ++; Special pattern to match LTGT for FPA and VFP. + (define_insn "*arm_bltgt" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7118,6 +7121,38 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match GE for MAVERICK. ++(define_insn "*arm_bge" ++ [(set (pc) ++ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ if (get_attr_cirrus (prev_active_insn(insn)) == CIRRUS_COMPARE) ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++; Special pattern to match UNLT for MAVERICK - UGLY since we need to test for Z=0 && V=0. ++(define_insn "*arm_bunlt" ++ [(set (pc) ++ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ + (define_insn "*arm_cond_branch" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7137,7 +7172,7 @@ + (set_attr "type" "branch")] + ) + +-; Special pattern to match reversed UNEQ. ++; Special pattern to match reversed UNEQ for FPA and VFP. + (define_insn "*arm_buneq_reversed" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7153,7 +7188,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match reversed LTGT. ++; Special pattern to match reversed LTGT for FPA and VFP. + (define_insn "*arm_bltgt_reversed" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7169,6 +7204,39 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match reversed GE for MAVERICK - UGLY since we need to tst for Z=0 && N=0. ++(define_insn "*arm_bge_reversed" ++ [(set (pc) ++ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ if (get_attr_cirrus (prev_active_insn(insn)) == CIRRUS_COMPARE) ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ ++; Special pattern to match reversed UNLT for MAVERICK. ++(define_insn "*arm_bunlt_reversed" ++ [(set (pc) ++ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++ + (define_insn "*arm_cond_branch_reversed" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7220,8 +7288,9 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++;; broken for cirrus - definitely + (define_expand "sge" + [(set (match_operand:SI 0 "s_register_operand" "") + (ge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM" ++ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +@@ -7227,6 +7296,14 @@ + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SGE these can not be represented with MAVERICK ++; (define_expand "sge" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "slt" + [(set (match_operand:SI 0 "s_register_operand" "") + (lt:SI (match_dup 1) (const_int 0)))] +@@ -7248,6 +7325,7 @@ + "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" + ) + ++;; broken for cirrus - maybe + (define_expand "sgeu" + [(set (match_operand:SI 0 "s_register_operand" "") + (geu:SI (match_dup 1) (const_int 0)))] +@@ -7255,6 +7333,14 @@ + "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SGEU these may not be represented with MAVERICK? ++; (define_expand "sgeu" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "sltu" + [(set (match_operand:SI 0 "s_register_operand" "") + (ltu:SI (match_dup 1) (const_int 0)))] +@@ -7281,7 +7367,7 @@ + (define_expand "sungt" + [(set (match_operand:SI 0 "s_register_operand" "") + (ungt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7289,23 +7375,32 @@ + (define_expand "sunge" + [(set (match_operand:SI 0 "s_register_operand" "") + (unge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, + arm_compare_op1);" + ) + ++; broken for cirrus + (define_expand "sunlt" + [(set (match_operand:SI 0 "s_register_operand" "") + (unlt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, + arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SUNLT these can't be represented with MAVERICK ++; (define_expand "sunlt" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (unlt:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "sunle" + [(set (match_operand:SI 0 "s_register_operand" "") + (unle:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7371,7 +7466,7 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) + FAIL; + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); +@@ -7390,7 +7485,8 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) ++ + FAIL; + + /* When compiling for SOFT_FLOAT, ensure both arms are in registers. +@@ -7409,13 +7505,13 @@ + (if_then_else:DF (match_operand 1 "arm_comparison_operator" "") + (match_operand:DF 2 "s_register_operand" "") + (match_operand:DF 3 "arm_float_add_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + " + { + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code==GE || code == UNLT || code == ORDERED || code == UNORDERED))) + FAIL; + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-compare-new5.patch b/packages/gcc/gcc-4.1.2/arm-crunch-compare-new5.patch new file mode 100644 index 0000000000..78880b35be --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-compare-new5.patch @@ -0,0 +1,432 @@ +diff -urN gcc-4.1.2/gcc/config/arm/arm.c ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.c +--- gcc-4.1.2/gcc/config/arm/arm.c 2007-05-31 12:39:48.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-29 17:19:38.000000000 +1000 +@@ -11427,26 +11427,53 @@ + /* These encodings assume that AC=1 in the FPA system control + byte. This allows us to handle all cases except UNEQ and + LTGT. */ +- switch (comp_code) +- { +- case GE: return ARM_GE; +- case GT: return ARM_GT; +- case LE: return ARM_LS; +- case LT: return ARM_MI; +- case NE: return ARM_NE; +- case EQ: return ARM_EQ; +- case ORDERED: return ARM_VC; +- case UNORDERED: return ARM_VS; +- case UNLT: return ARM_LT; +- case UNLE: return ARM_LE; +- case UNGT: return ARM_HI; +- case UNGE: return ARM_PL; +- /* UNEQ and LTGT do not have a representation. */ +- case UNEQ: /* Fall through. */ +- case LTGT: /* Fall through. */ +- default: gcc_unreachable (); +- } +- ++ if (!TARGET_MAVERICK) ++ { ++ switch (comp_code) ++ { ++ case GE: return ARM_GE; ++ case GT: return ARM_GT; ++ case LE: return ARM_LS; ++ case LT: return ARM_MI; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case ORDERED: return ARM_VC; ++ case UNORDERED: return ARM_VS; ++ case UNLT: return ARM_LT; ++ case UNLE: return ARM_LE; ++ case UNGT: return ARM_HI; ++ case UNGE: return ARM_PL; ++ /* UNEQ and LTGT do not have a representation. */ ++ case UNEQ: /* Fall through. */ ++ case LTGT: /* Fall through. */ ++ default: gcc_unreachable (); ++ } ++ } ++ else ++ { ++ /* CIRRUS */ ++ switch (comp_code) ++ { ++#if 1 ++ case GT: return ARM_VS; ++ case LE: return ARM_LE; ++ case LT: return ARM_LT; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case UNLE: return ARM_VC; ++ case UNGT: return ARM_GT; ++ case UNGE: return ARM_GE; ++ case UNEQ: return ARM_PL; ++ case LTGT: return ARM_MI; ++ /* These do not have a representation. */ ++ case GE: /* Fall through. -UNGE wrong atm */ ++ case UNLT: /* Fall through. -LT wrong atm */ ++ case ORDERED: /* Fall through. -AL wrong atm */ ++ case UNORDERED: /* Fall through. -AL wrong atm */ ++#endif ++ default: gcc_unreachable (); ++ } ++ } + case CC_SWPmode: + switch (comp_code) + { +diff -urN gcc-4.1.2/gcc/config/arm/arm.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.md +--- gcc-4.1.2/gcc/config/arm/arm.md 2007-05-31 12:39:48.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-29 15:17:18.000000000 +1000 +@@ -6952,10 +6952,11 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++;broken on cirrus + (define_expand "bge" + [(set (pc) + (if_then_else (ge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM" ++ "TARGET_ARM" + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +@@ -6988,6 +6989,7 @@ + "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" + ) + ++; broken on cirrus? + (define_expand "bgeu" + [(set (pc) + (if_then_else (geu (match_dup 1) (const_int 0)) +@@ -7031,14 +7033,15 @@ + (if_then_else (ungt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);" + ) + +-(define_expand "bunlt" ++; broken for cirrus ++(define_expand "bunlt" + [(set (pc) + (if_then_else (unlt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);" +@@ -7049,7 +7052,7 @@ + (if_then_else (unge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7058,7 +7061,7 @@ + (if_then_else (unle (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7069,7 +7072,7 @@ + (if_then_else (uneq (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7078,7 +7081,7 @@ + (if_then_else (ltgt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7086,7 +7089,7 @@ + ;; Patterns to match conditional branch insns. + ;; + +-; Special pattern to match UNEQ. ++; Special pattern to match UNEQ for FPA and VFP. + (define_insn "*arm_buneq" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7102,7 +7105,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match LTGT. ++; Special pattern to match LTGT for FPA and VFP. + (define_insn "*arm_bltgt" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7118,6 +7121,54 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match GE for MAVERICK. ++(define_insn "*arm_bge_sf" ++ [(set (pc) ++ (if_then_else (ge:SF (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++; Special pattern to match GE for MAVERICK. ++(define_insn "*arm_bge_df" ++ [(set (pc) ++ (if_then_else (ge:DF (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++; Special pattern to match UNLT for MAVERICK - UGLY since we need to test for Z=0 && V=0. ++(define_insn "*arm_bunlt" ++ [(set (pc) ++ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ + (define_insn "*arm_cond_branch" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7137,7 +7172,7 @@ + (set_attr "type" "branch")] + ) + +-; Special pattern to match reversed UNEQ. ++; Special pattern to match reversed UNEQ for FPA and VFP. + (define_insn "*arm_buneq_reversed" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7153,7 +7188,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match reversed LTGT. ++; Special pattern to match reversed LTGT for FPA and VFP. + (define_insn "*arm_bltgt_reversed" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7169,6 +7204,39 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match reversed GE for MAVERICK - UGLY since we need to tst for Z=0 && N=0. ++(define_insn "*arm_bge_reversed" ++ [(set (pc) ++ (if_then_else (ge:SF (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ ++; Special pattern to match reversed GE for MAVERICK - UGLY since we need to tst for Z=0 && N=0. ++(define_insn "*arm_bge_reversed_df" ++ [(set (pc) ++ (if_then_else (ge:DF (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ ++; Special pattern to match reversed UNLT for MAVERICK. ++(define_insn "*arm_bunlt_reversed" ++ [(set (pc) ++ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++ + (define_insn "*arm_cond_branch_reversed" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7220,8 +7288,9 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++;; broken for cirrus - definitely + (define_expand "sge" + [(set (match_operand:SI 0 "s_register_operand" "") + (ge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM" ++ "TARGET_ARM" + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +@@ -7227,6 +7296,14 @@ + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SGE these can not be represented with MAVERICK ++; (define_expand "sge" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "slt" + [(set (match_operand:SI 0 "s_register_operand" "") + (lt:SI (match_dup 1) (const_int 0)))] +@@ -7248,6 +7325,7 @@ + "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" + ) + ++;; broken for cirrus - maybe + (define_expand "sgeu" + [(set (match_operand:SI 0 "s_register_operand" "") + (geu:SI (match_dup 1) (const_int 0)))] +@@ -7255,6 +7333,14 @@ + "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SGEU these may not be represented with MAVERICK? ++; (define_expand "sgeu" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "sltu" + [(set (match_operand:SI 0 "s_register_operand" "") + (ltu:SI (match_dup 1) (const_int 0)))] +@@ -7281,7 +7367,7 @@ + (define_expand "sungt" + [(set (match_operand:SI 0 "s_register_operand" "") + (ungt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7289,23 +7375,32 @@ + (define_expand "sunge" + [(set (match_operand:SI 0 "s_register_operand" "") + (unge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, + arm_compare_op1);" + ) + ++; broken for cirrus + (define_expand "sunlt" + [(set (match_operand:SI 0 "s_register_operand" "") + (unlt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, + arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SUNLT these can't be represented with MAVERICK ++; (define_expand "sunlt" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (unlt:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "sunle" + [(set (match_operand:SI 0 "s_register_operand" "") + (unle:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7371,7 +7466,7 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) + FAIL; + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); +@@ -7390,7 +7485,8 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) ++ + FAIL; + + /* When compiling for SOFT_FLOAT, ensure both arms are in registers. +@@ -7409,13 +7505,13 @@ + (if_then_else:DF (match_operand 1 "arm_comparison_operator" "") + (match_operand:DF 2 "s_register_operand" "") + (match_operand:DF 3 "arm_float_add_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + " + { + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code==GE || code == UNLT || code == ORDERED || code == UNORDERED))) + FAIL; + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-compare-new6.patch b/packages/gcc/gcc-4.1.2/arm-crunch-compare-new6.patch new file mode 100644 index 0000000000..303c844d4d --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-compare-new6.patch @@ -0,0 +1,400 @@ +diff -urN gcc-4.1.2/gcc/config/arm/arm.c ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.c +--- gcc-4.1.2/gcc/config/arm/arm.c 2007-05-31 12:39:48.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-29 17:19:38.000000000 +1000 +@@ -11427,26 +11427,53 @@ + /* These encodings assume that AC=1 in the FPA system control + byte. This allows us to handle all cases except UNEQ and + LTGT. */ +- switch (comp_code) +- { +- case GE: return ARM_GE; +- case GT: return ARM_GT; +- case LE: return ARM_LS; +- case LT: return ARM_MI; +- case NE: return ARM_NE; +- case EQ: return ARM_EQ; +- case ORDERED: return ARM_VC; +- case UNORDERED: return ARM_VS; +- case UNLT: return ARM_LT; +- case UNLE: return ARM_LE; +- case UNGT: return ARM_HI; +- case UNGE: return ARM_PL; +- /* UNEQ and LTGT do not have a representation. */ +- case UNEQ: /* Fall through. */ +- case LTGT: /* Fall through. */ +- default: gcc_unreachable (); +- } +- ++ if (!TARGET_MAVERICK) ++ { ++ switch (comp_code) ++ { ++ case GE: return ARM_GE; ++ case GT: return ARM_GT; ++ case LE: return ARM_LS; ++ case LT: return ARM_MI; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case ORDERED: return ARM_VC; ++ case UNORDERED: return ARM_VS; ++ case UNLT: return ARM_LT; ++ case UNLE: return ARM_LE; ++ case UNGT: return ARM_HI; ++ case UNGE: return ARM_PL; ++ /* UNEQ and LTGT do not have a representation. */ ++ case UNEQ: /* Fall through. */ ++ case LTGT: /* Fall through. */ ++ default: gcc_unreachable (); ++ } ++ } ++ else ++ { ++ /* CIRRUS */ ++ switch (comp_code) ++ { ++#if 1 ++ case GT: return ARM_VS; ++ case LE: return ARM_LE; ++ case LT: return ARM_LT; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case UNLE: return ARM_VC; ++ case UNGT: return ARM_GT; ++ case UNGE: return ARM_GE; ++ case UNEQ: return ARM_PL; ++ case LTGT: return ARM_MI; ++ /* These do not have a representation. */ ++ case GE: /* Fall through. -UNGE wrong atm */ ++ case UNLT: /* Fall through. -LT wrong atm */ ++ case ORDERED: /* Fall through. -AL wrong atm */ ++ case UNORDERED: /* Fall through. -AL wrong atm */ ++#endif ++ default: gcc_unreachable (); ++ } ++ } + case CC_SWPmode: + switch (comp_code) + { +diff -urN gcc-4.1.2/gcc/config/arm/arm.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.md +--- gcc-4.1.2/gcc/config/arm/arm.md 2007-05-31 12:39:48.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-29 15:17:18.000000000 +1000 +@@ -6952,10 +6952,11 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++;broken on cirrus + (define_expand "bge" + [(set (pc) + (if_then_else (ge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM" ++ "TARGET_ARM" ;; && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +@@ -6988,6 +6989,7 @@ + "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" + ) + ++; broken on cirrus? + (define_expand "bgeu" + [(set (pc) + (if_then_else (geu (match_dup 1) (const_int 0)) +@@ -7031,14 +7033,15 @@ + (if_then_else (ungt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);" + ) + +-(define_expand "bunlt" ++; broken for cirrus ++(define_expand "bunlt" + [(set (pc) + (if_then_else (unlt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);" +@@ -7049,7 +7052,7 @@ + (if_then_else (unge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7058,7 +7061,7 @@ + (if_then_else (unle (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7069,7 +7072,7 @@ + (if_then_else (uneq (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7078,7 +7081,7 @@ + (if_then_else (ltgt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7086,7 +7089,7 @@ + ;; Patterns to match conditional branch insns. + ;; + +-; Special pattern to match UNEQ. ++; Special pattern to match UNEQ for FPA and VFP. + (define_insn "*arm_buneq" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7102,7 +7105,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match LTGT. ++; Special pattern to match LTGT for FPA and VFP. + (define_insn "*arm_bltgt" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7118,6 +7121,38 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match GE for MAVERICK. ++(define_insn "*arm_bge" ++ [(set (pc) ++ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ if (get_attr_cirrus (prev_active_insn(insn)) == CIRRUS_COMPARE) ++ return \"beq\\t%l0\;bvs\\t%l0\"; else return \"bge\\t%l0\;nop\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++; Special pattern to match UNLT for MAVERICK - UGLY since we need to test for Z=0 && V=0. ++(define_insn "*arm_bunlt" ++ [(set (pc) ++ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ + (define_insn "*arm_cond_branch" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7137,7 +7172,7 @@ + (set_attr "type" "branch")] + ) + +-; Special pattern to match reversed UNEQ. ++; Special pattern to match reversed UNEQ for FPA and VFP. + (define_insn "*arm_buneq_reversed" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7153,7 +7188,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match reversed LTGT. ++; Special pattern to match reversed LTGT for FPA and VFP. + (define_insn "*arm_bltgt_reversed" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7169,6 +7204,39 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match reversed GE for MAVERICK - UGLY since we need to tst for Z=0 && N=0. ++(define_insn "*arm_bge_reversed" ++ [(set (pc) ++ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ if (get_attr_cirrus (prev_active_insn(insn)) == CIRRUS_COMPARE) ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; else return \"bge\\t.+12\;b\\t%l0\;nop\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ ++; Special pattern to match reversed UNLT for MAVERICK. ++(define_insn "*arm_bunlt_reversed" ++ [(set (pc) ++ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++ + (define_insn "*arm_cond_branch_reversed" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7220,8 +7288,9 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++;; broken for cirrus - definitely + (define_expand "sge" + [(set (match_operand:SI 0 "s_register_operand" "") + (ge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM" ++ "TARGET_ARM" + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +@@ -7227,6 +7296,14 @@ + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SGE these can not be represented with MAVERICK ++; (define_expand "sge" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "slt" + [(set (match_operand:SI 0 "s_register_operand" "") + (lt:SI (match_dup 1) (const_int 0)))] +@@ -7248,6 +7325,7 @@ + "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" + ) + ++;; broken for cirrus - maybe + (define_expand "sgeu" + [(set (match_operand:SI 0 "s_register_operand" "") + (geu:SI (match_dup 1) (const_int 0)))] +@@ -7255,6 +7333,14 @@ + "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SGEU these may not be represented with MAVERICK? ++; (define_expand "sgeu" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "sltu" + [(set (match_operand:SI 0 "s_register_operand" "") + (ltu:SI (match_dup 1) (const_int 0)))] +@@ -7281,7 +7367,7 @@ + (define_expand "sungt" + [(set (match_operand:SI 0 "s_register_operand" "") + (ungt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7289,23 +7375,32 @@ + (define_expand "sunge" + [(set (match_operand:SI 0 "s_register_operand" "") + (unge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, + arm_compare_op1);" + ) + ++; broken for cirrus + (define_expand "sunlt" + [(set (match_operand:SI 0 "s_register_operand" "") + (unlt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, + arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SUNLT these can't be represented with MAVERICK ++; (define_expand "sunlt" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (unlt:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "sunle" + [(set (match_operand:SI 0 "s_register_operand" "") + (unle:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7371,7 +7466,7 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) + FAIL; + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); +@@ -7390,7 +7485,8 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) ++ + FAIL; + + /* When compiling for SOFT_FLOAT, ensure both arms are in registers. +@@ -7409,13 +7505,13 @@ + (if_then_else:DF (match_operand 1 "arm_comparison_operator" "") + (match_operand:DF 2 "s_register_operand" "") + (match_operand:DF 3 "arm_float_add_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + " + { + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code==GE || code == UNLT || code == ORDERED || code == UNORDERED))) + FAIL; + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-compare-new7.patch b/packages/gcc/gcc-4.1.2/arm-crunch-compare-new7.patch new file mode 100644 index 0000000000..1e35151416 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-compare-new7.patch @@ -0,0 +1,400 @@ +diff -urN gcc-4.1.2/gcc/config/arm/arm.c ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.c +--- gcc-4.1.2/gcc/config/arm/arm.c 2007-05-31 12:39:48.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-29 17:19:38.000000000 +1000 +@@ -11427,26 +11427,53 @@ + /* These encodings assume that AC=1 in the FPA system control + byte. This allows us to handle all cases except UNEQ and + LTGT. */ +- switch (comp_code) +- { +- case GE: return ARM_GE; +- case GT: return ARM_GT; +- case LE: return ARM_LS; +- case LT: return ARM_MI; +- case NE: return ARM_NE; +- case EQ: return ARM_EQ; +- case ORDERED: return ARM_VC; +- case UNORDERED: return ARM_VS; +- case UNLT: return ARM_LT; +- case UNLE: return ARM_LE; +- case UNGT: return ARM_HI; +- case UNGE: return ARM_PL; +- /* UNEQ and LTGT do not have a representation. */ +- case UNEQ: /* Fall through. */ +- case LTGT: /* Fall through. */ +- default: gcc_unreachable (); +- } +- ++ if (!TARGET_MAVERICK) ++ { ++ switch (comp_code) ++ { ++ case GE: return ARM_GE; ++ case GT: return ARM_GT; ++ case LE: return ARM_LS; ++ case LT: return ARM_MI; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case ORDERED: return ARM_VC; ++ case UNORDERED: return ARM_VS; ++ case UNLT: return ARM_LT; ++ case UNLE: return ARM_LE; ++ case UNGT: return ARM_HI; ++ case UNGE: return ARM_PL; ++ /* UNEQ and LTGT do not have a representation. */ ++ case UNEQ: /* Fall through. */ ++ case LTGT: /* Fall through. */ ++ default: gcc_unreachable (); ++ } ++ } ++ else ++ { ++ /* CIRRUS */ ++ switch (comp_code) ++ { ++#if 1 ++ case GT: return ARM_VS; ++ case LE: return ARM_LE; ++ case LT: return ARM_LT; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case UNLE: return ARM_VC; ++ case UNGT: return ARM_GT; ++ case UNGE: return ARM_GE; ++ case UNEQ: return ARM_PL; ++ case LTGT: return ARM_MI; ++ /* These do not have a representation. */ ++ case GE: /* Fall through. -UNGE wrong atm */ ++ case UNLT: /* Fall through. -LT wrong atm */ ++ case ORDERED: /* Fall through. -AL wrong atm */ ++ case UNORDERED: /* Fall through. -AL wrong atm */ ++#endif ++ default: gcc_unreachable (); ++ } ++ } + case CC_SWPmode: + switch (comp_code) + { +diff -urN gcc-4.1.2/gcc/config/arm/arm.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.md +--- gcc-4.1.2/gcc/config/arm/arm.md 2007-05-31 12:39:48.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-29 15:17:18.000000000 +1000 +@@ -6952,10 +6952,11 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++;broken on cirrus + (define_expand "bge" + [(set (pc) + (if_then_else (ge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM" ++ "TARGET_ARM" ;; && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +@@ -6988,6 +6989,7 @@ + "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" + ) + ++; broken on cirrus? + (define_expand "bgeu" + [(set (pc) + (if_then_else (geu (match_dup 1) (const_int 0)) +@@ -7031,14 +7033,15 @@ + (if_then_else (ungt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);" + ) + +-(define_expand "bunlt" ++; broken for cirrus ++(define_expand "bunlt" + [(set (pc) + (if_then_else (unlt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);" +@@ -7049,7 +7052,7 @@ + (if_then_else (unge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7058,7 +7061,7 @@ + (if_then_else (unle (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7069,7 +7072,7 @@ + (if_then_else (uneq (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7078,7 +7081,7 @@ + (if_then_else (ltgt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7086,7 +7089,7 @@ + ;; Patterns to match conditional branch insns. + ;; + +-; Special pattern to match UNEQ. ++; Special pattern to match UNEQ for FPA and VFP. + (define_insn "*arm_buneq" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7102,7 +7105,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match LTGT. ++; Special pattern to match LTGT for FPA and VFP. + (define_insn "*arm_bltgt" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7118,6 +7121,38 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match GE for MAVERICK. ++(define_insn "*arm_bge" ++ [(set (pc) ++ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ if (get_attr_cirrus (prev_active_insn(insn)) != CIRRUS_COMPARE) ++ return \"bge\\t%l0\;nop\"; else return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++; Special pattern to match UNLT for MAVERICK - UGLY since we need to test for Z=0 && V=0. ++(define_insn "*arm_bunlt" ++ [(set (pc) ++ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ + (define_insn "*arm_cond_branch" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7137,7 +7172,7 @@ + (set_attr "type" "branch")] + ) + +-; Special pattern to match reversed UNEQ. ++; Special pattern to match reversed UNEQ for FPA and VFP. + (define_insn "*arm_buneq_reversed" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7153,7 +7188,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match reversed LTGT. ++; Special pattern to match reversed LTGT for FPA and VFP. + (define_insn "*arm_bltgt_reversed" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7169,6 +7204,39 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match reversed GE for MAVERICK - UGLY since we need to tst for Z=0 && N=0. ++(define_insn "*arm_bge_reversed" ++ [(set (pc) ++ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ if (get_attr_cirrus (prev_active_insn(insn)) != CIRRUS_COMPARE) ++ return \"bge\\t.+12\;b\\t%l0\;nop\"; else return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ ++; Special pattern to match reversed UNLT for MAVERICK. ++(define_insn "*arm_bunlt_reversed" ++ [(set (pc) ++ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++ + (define_insn "*arm_cond_branch_reversed" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7220,8 +7288,9 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++;; broken for cirrus - definitely + (define_expand "sge" + [(set (match_operand:SI 0 "s_register_operand" "") + (ge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM" ++ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +@@ -7227,6 +7296,14 @@ + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SGE these can not be represented with MAVERICK ++; (define_expand "sge" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "slt" + [(set (match_operand:SI 0 "s_register_operand" "") + (lt:SI (match_dup 1) (const_int 0)))] +@@ -7248,6 +7325,7 @@ + "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" + ) + ++;; broken for cirrus - maybe + (define_expand "sgeu" + [(set (match_operand:SI 0 "s_register_operand" "") + (geu:SI (match_dup 1) (const_int 0)))] +@@ -7255,6 +7333,14 @@ + "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SGEU these may not be represented with MAVERICK? ++; (define_expand "sgeu" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "sltu" + [(set (match_operand:SI 0 "s_register_operand" "") + (ltu:SI (match_dup 1) (const_int 0)))] +@@ -7281,7 +7367,7 @@ + (define_expand "sungt" + [(set (match_operand:SI 0 "s_register_operand" "") + (ungt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7289,23 +7375,32 @@ + (define_expand "sunge" + [(set (match_operand:SI 0 "s_register_operand" "") + (unge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, + arm_compare_op1);" + ) + ++; broken for cirrus + (define_expand "sunlt" + [(set (match_operand:SI 0 "s_register_operand" "") + (unlt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, + arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SUNLT these can't be represented with MAVERICK ++; (define_expand "sunlt" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (unlt:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "sunle" + [(set (match_operand:SI 0 "s_register_operand" "") + (unle:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7371,7 +7466,7 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) + FAIL; + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); +@@ -7390,7 +7485,8 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) ++ + FAIL; + + /* When compiling for SOFT_FLOAT, ensure both arms are in registers. +@@ -7409,13 +7505,13 @@ + (if_then_else:DF (match_operand 1 "arm_comparison_operator" "") + (match_operand:DF 2 "s_register_operand" "") + (match_operand:DF 3 "arm_float_add_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + " + { + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code==GE || code == UNLT || code == ORDERED || code == UNORDERED))) + FAIL; + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-compare-old.patch b/packages/gcc/gcc-4.1.2/arm-crunch-compare-old.patch new file mode 100644 index 0000000000..1170f13845 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-compare-old.patch @@ -0,0 +1,400 @@ +diff -urN gcc-4.1.2/gcc/config/arm/arm.c ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.c +--- gcc-4.1.2/gcc/config/arm/arm.c 2007-05-31 12:39:48.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-29 17:19:38.000000000 +1000 +@@ -11427,26 +11427,53 @@ + /* These encodings assume that AC=1 in the FPA system control + byte. This allows us to handle all cases except UNEQ and + LTGT. */ +- switch (comp_code) +- { +- case GE: return ARM_GE; +- case GT: return ARM_GT; +- case LE: return ARM_LS; +- case LT: return ARM_MI; +- case NE: return ARM_NE; +- case EQ: return ARM_EQ; +- case ORDERED: return ARM_VC; +- case UNORDERED: return ARM_VS; +- case UNLT: return ARM_LT; +- case UNLE: return ARM_LE; +- case UNGT: return ARM_HI; +- case UNGE: return ARM_PL; +- /* UNEQ and LTGT do not have a representation. */ +- case UNEQ: /* Fall through. */ +- case LTGT: /* Fall through. */ +- default: gcc_unreachable (); +- } +- ++ if (!TARGET_MAVERICK) ++ { ++ switch (comp_code) ++ { ++ case GE: return ARM_GE; ++ case GT: return ARM_GT; ++ case LE: return ARM_LS; ++ case LT: return ARM_MI; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case ORDERED: return ARM_VC; ++ case UNORDERED: return ARM_VS; ++ case UNLT: return ARM_LT; ++ case UNLE: return ARM_LE; ++ case UNGT: return ARM_HI; ++ case UNGE: return ARM_PL; ++ /* UNEQ and LTGT do not have a representation. */ ++ case UNEQ: /* Fall through. */ ++ case LTGT: /* Fall through. */ ++ default: gcc_unreachable (); ++ } ++ } ++ else ++ { ++ /* CIRRUS */ ++ switch (comp_code) ++ { ++#if 1 ++ case GT: return ARM_VS; ++ case LE: return ARM_LE; ++ case LT: return ARM_LT; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case UNLE: return ARM_VC; ++ case UNGT: return ARM_GT; ++ case UNGE: return ARM_GE; ++ case UNEQ: return ARM_PL; ++ case LTGT: return ARM_MI; ++ /* These do not have a representation. */ ++ case GE: /* Fall through. -UNGE wrong atm */ ++ case UNLT: /* Fall through. -LT wrong atm */ ++ case ORDERED: /* Fall through. -AL wrong atm */ ++ case UNORDERED: /* Fall through. -AL wrong atm */ ++#endif ++ default: gcc_unreachable (); ++ } ++ } + case CC_SWPmode: + switch (comp_code) + { +diff -urN gcc-4.1.2/gcc/config/arm/arm.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.md +--- gcc-4.1.2/gcc/config/arm/arm.md 2007-05-31 12:39:48.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-29 15:17:18.000000000 +1000 +@@ -6952,10 +6952,11 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++;broken on cirrus + (define_expand "bge" + [(set (pc) + (if_then_else (ge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM" ++ "TARGET_ARM" ;; && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +@@ -6988,6 +6989,7 @@ + "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" + ) + ++; broken on cirrus? + (define_expand "bgeu" + [(set (pc) + (if_then_else (geu (match_dup 1) (const_int 0)) +@@ -7031,14 +7033,15 @@ + (if_then_else (ungt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);" + ) + +-(define_expand "bunlt" ++; broken for cirrus ++(define_expand "bunlt" + [(set (pc) + (if_then_else (unlt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);" +@@ -7049,7 +7052,7 @@ + (if_then_else (unge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7058,7 +7061,7 @@ + (if_then_else (unle (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7069,7 +7072,7 @@ + (if_then_else (uneq (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7078,7 +7081,7 @@ + (if_then_else (ltgt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7086,7 +7089,7 @@ + ;; Patterns to match conditional branch insns. + ;; + +-; Special pattern to match UNEQ. ++; Special pattern to match UNEQ for FPA and VFP. + (define_insn "*arm_buneq" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7102,7 +7105,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match LTGT. ++; Special pattern to match LTGT for FPA and VFP. + (define_insn "*arm_bltgt" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7118,6 +7121,38 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match GE for MAVERICK. ++(define_insn "*arm_bge" ++ [(set (pc) ++ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++; Special pattern to match UNLT for MAVERICK - UGLY since we need to test for Z=0 && V=0. ++(define_insn "*arm_bunlt" ++ [(set (pc) ++ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ + (define_insn "*arm_cond_branch" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7137,7 +7172,7 @@ + (set_attr "type" "branch")] + ) + +-; Special pattern to match reversed UNEQ. ++; Special pattern to match reversed UNEQ for FPA and VFP. + (define_insn "*arm_buneq_reversed" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7153,7 +7188,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match reversed LTGT. ++; Special pattern to match reversed LTGT for FPA and VFP. + (define_insn "*arm_bltgt_reversed" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7169,6 +7204,39 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match reversed GE for MAVERICK - UGLY since we need to tst for Z=0 && N=0. ++(define_insn "*arm_bge_reversed" ++ [(set (pc) ++ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ ++; Special pattern to match reversed UNLT for MAVERICK. ++(define_insn "*arm_bunlt_reversed" ++ [(set (pc) ++ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++ + (define_insn "*arm_cond_branch_reversed" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7220,8 +7288,9 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++;; broken for cirrus - definitely + (define_expand "sge" + [(set (match_operand:SI 0 "s_register_operand" "") + (ge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM" ++ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +@@ -7227,6 +7296,14 @@ + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SGE these can not be represented with MAVERICK ++; (define_expand "sge" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "slt" + [(set (match_operand:SI 0 "s_register_operand" "") + (lt:SI (match_dup 1) (const_int 0)))] +@@ -7248,6 +7325,7 @@ + "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" + ) + ++;; broken for cirrus - maybe + (define_expand "sgeu" + [(set (match_operand:SI 0 "s_register_operand" "") + (geu:SI (match_dup 1) (const_int 0)))] +@@ -7255,6 +7333,14 @@ + "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SGEU these may not be represented with MAVERICK? ++; (define_expand "sgeu" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "sltu" + [(set (match_operand:SI 0 "s_register_operand" "") + (ltu:SI (match_dup 1) (const_int 0)))] +@@ -7281,7 +7367,7 @@ + (define_expand "sungt" + [(set (match_operand:SI 0 "s_register_operand" "") + (ungt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7289,23 +7375,32 @@ + (define_expand "sunge" + [(set (match_operand:SI 0 "s_register_operand" "") + (unge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, + arm_compare_op1);" + ) + ++; broken for cirrus + (define_expand "sunlt" + [(set (match_operand:SI 0 "s_register_operand" "") + (unlt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, + arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SUNLT these can't be represented with MAVERICK ++; (define_expand "sunlt" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (unlt:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "sunle" + [(set (match_operand:SI 0 "s_register_operand" "") + (unle:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7371,7 +7466,7 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) + FAIL; + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); +@@ -7390,7 +7485,8 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) ++ + FAIL; + + /* When compiling for SOFT_FLOAT, ensure both arms are in registers. +@@ -7409,13 +7505,13 @@ + (if_then_else:DF (match_operand 1 "arm_comparison_operator" "") + (match_operand:DF 2 "s_register_operand" "") + (match_operand:DF 3 "arm_float_add_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + " + { + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code==GE || code == UNLT || code == ORDERED || code == UNORDERED))) + FAIL; + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-compare-unordered.patch b/packages/gcc/gcc-4.1.2/arm-crunch-compare-unordered.patch new file mode 100644 index 0000000000..c4fcdb3746 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-compare-unordered.patch @@ -0,0 +1,98 @@ +--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-07 14:45:22.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-07 15:13:58.000000000 +1000 +@@ -7001,16 +7001,16 @@ + (if_then_else (unordered (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0, + arm_compare_op1);" + ) + + (define_expand "bordered" + [(set (pc) + (if_then_else (ordered (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0, + arm_compare_op1);" +@@ -7141,6 +7141,38 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match UNORDERED for MAVERICK - UGLY since we need to test for Z=0 && N=0. ++(define_insn "*arm_bunordered" ++ [(set (pc) ++ (if_then_else (unordered (match_operand:CCFP 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bmi\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ ++; Special pattern to match ORDERED for MAVERICK. ++(define_insn "*arm_bordered" ++ [(set (pc) ++ (if_then_else (ordered (match_operand:CCFP 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bmi\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ + (define_insn "*arm_cond_branch" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7224,6 +7256,37 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match reversed UNORDERED for MAVERICK. ++(define_insn "*arm_bunordered_reversed" ++ [(set (pc) ++ (if_then_else (unordered (match_operand:CCFP 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bmi\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++; Special pattern to match reversed ORDERED for MAVERICK - UGLY since we need to test for Z=0 && N=0. ++(define_insn "*arm_bordered_reversed" ++ [(set (pc) ++ (if_then_else (ordered (match_operand:CCFP 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bmi\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) + + (define_insn "*arm_cond_branch_reversed" + [(set (pc) diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-compare-unordered.patch-z-eq b/packages/gcc/gcc-4.1.2/arm-crunch-compare-unordered.patch-z-eq new file mode 100644 index 0000000000..715fb95086 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-compare-unordered.patch-z-eq @@ -0,0 +1,98 @@ +--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-07 14:45:22.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-07 15:13:58.000000000 +1000 +@@ -7001,16 +7001,16 @@ + (if_then_else (unordered (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0, + arm_compare_op1);" + ) + + (define_expand "bordered" + [(set (pc) + (if_then_else (ordered (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0, + arm_compare_op1);" +@@ -7141,6 +7141,38 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match UNORDERED for MAVERICK - UGLY since we need to test for C=0 && N=0 ++(define_insn "*arm_bunordered" ++ [(set (pc) ++ (if_then_else (unordered (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"bcs\\t.+12\;bmi\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ ++; Special pattern to match ORDERED for MAVERICK. ++(define_insn "*arm_bordered" ++ [(set (pc) ++ (if_then_else (ordered (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"bcs\\t%l0\;bmi\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ + (define_insn "*arm_cond_branch" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7224,6 +7256,37 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match reversed UNORDERED for MAVERICK. ++(define_insn "*arm_bunordered_reversed" ++ [(set (pc) ++ (if_then_else (unordered (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"bcs\\t%l0\;bmi\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++; Special pattern to match reversed ORDERED for MAVERICK - UGLY since we need to test for C=0 && N=0 ++(define_insn "*arm_bordered_reversed" ++ [(set (pc) ++ (if_then_else (ordered (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"bcs\\t.+12\;bmi\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) + + (define_insn "*arm_cond_branch_reversed" + [(set (pc) diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-compare.patch b/packages/gcc/gcc-4.1.2/arm-crunch-compare.patch new file mode 100644 index 0000000000..ccbb4854c3 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-compare.patch @@ -0,0 +1,400 @@ +diff -urN gcc-4.1.2/gcc/config/arm/arm.c ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.c +--- gcc-4.1.2/gcc/config/arm/arm.c 2007-05-31 12:39:48.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-29 17:19:38.000000000 +1000 +@@ -11427,26 +11427,53 @@ + /* These encodings assume that AC=1 in the FPA system control + byte. This allows us to handle all cases except UNEQ and + LTGT. */ +- switch (comp_code) +- { +- case GE: return ARM_GE; +- case GT: return ARM_GT; +- case LE: return ARM_LS; +- case LT: return ARM_MI; +- case NE: return ARM_NE; +- case EQ: return ARM_EQ; +- case ORDERED: return ARM_VC; +- case UNORDERED: return ARM_VS; +- case UNLT: return ARM_LT; +- case UNLE: return ARM_LE; +- case UNGT: return ARM_HI; +- case UNGE: return ARM_PL; +- /* UNEQ and LTGT do not have a representation. */ +- case UNEQ: /* Fall through. */ +- case LTGT: /* Fall through. */ +- default: gcc_unreachable (); +- } +- ++ if (!TARGET_MAVERICK) ++ { ++ switch (comp_code) ++ { ++ case GE: return ARM_GE; ++ case GT: return ARM_GT; ++ case LE: return ARM_LS; ++ case LT: return ARM_MI; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case ORDERED: return ARM_VC; ++ case UNORDERED: return ARM_VS; ++ case UNLT: return ARM_LT; ++ case UNLE: return ARM_LE; ++ case UNGT: return ARM_HI; ++ case UNGE: return ARM_PL; ++ /* UNEQ and LTGT do not have a representation. */ ++ case UNEQ: /* Fall through. */ ++ case LTGT: /* Fall through. */ ++ default: gcc_unreachable (); ++ } ++ } ++ else ++ { ++ /* CIRRUS */ ++ switch (comp_code) ++ { ++#if 1 ++ case GT: return ARM_VS; ++ case LE: return ARM_LE; ++ case LT: return ARM_LT; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case UNLE: return ARM_VC; ++ case UNGT: return ARM_GT; ++ case UNGE: return ARM_GE; ++ case UNEQ: return ARM_PL; ++ case LTGT: return ARM_MI; ++ /* These do not have a representation. */ ++ case GE: /* Fall through. -UNGE wrong atm */ ++ case UNLT: /* Fall through. -LT wrong atm */ ++ case ORDERED: /* Fall through. -AL wrong atm */ ++ case UNORDERED: /* Fall through. -AL wrong atm */ ++#endif ++ default: gcc_unreachable (); ++ } ++ } + case CC_SWPmode: + switch (comp_code) + { +diff -urN gcc-4.1.2/gcc/config/arm/arm.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.md +--- gcc-4.1.2/gcc/config/arm/arm.md 2007-05-31 12:39:48.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-29 15:17:18.000000000 +1000 +@@ -6952,10 +6952,11 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++;broken on cirrus + (define_expand "bge" + [(set (pc) + (if_then_else (ge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM" ++ "TARGET_ARM" ;; && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +@@ -6988,6 +6989,7 @@ + "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" + ) + ++; broken on cirrus? + (define_expand "bgeu" + [(set (pc) + (if_then_else (geu (match_dup 1) (const_int 0)) +@@ -7031,14 +7033,15 @@ + (if_then_else (ungt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);" + ) + +-(define_expand "bunlt" ++; broken for cirrus ++(define_expand "bunlt" + [(set (pc) + (if_then_else (unlt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);" +@@ -7049,7 +7052,7 @@ + (if_then_else (unge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7058,7 +7061,7 @@ + (if_then_else (unle (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7069,7 +7072,7 @@ + (if_then_else (uneq (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7078,7 +7081,7 @@ + (if_then_else (ltgt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7086,7 +7089,7 @@ + ;; Patterns to match conditional branch insns. + ;; + +-; Special pattern to match UNEQ. ++; Special pattern to match UNEQ for FPA and VFP. + (define_insn "*arm_buneq" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7102,7 +7105,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match LTGT. ++; Special pattern to match LTGT for FPA and VFP. + (define_insn "*arm_bltgt" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7118,6 +7121,38 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match GE for MAVERICK. ++(define_insn "*arm_bge" ++ [(set (pc) ++ (if_then_else (ge (match_operand:CCFP 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++; Special pattern to match UNLT for MAVERICK - UGLY since we need to test for Z=0 && V=0. ++(define_insn "*arm_bunlt" ++ [(set (pc) ++ (if_then_else (unlt (match_operand:CCFP 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ + (define_insn "*arm_cond_branch" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7137,7 +7172,7 @@ + (set_attr "type" "branch")] + ) + +-; Special pattern to match reversed UNEQ. ++; Special pattern to match reversed UNEQ for FPA and VFP. + (define_insn "*arm_buneq_reversed" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7153,7 +7188,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match reversed LTGT. ++; Special pattern to match reversed LTGT for FPA and VFP. + (define_insn "*arm_bltgt_reversed" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7169,6 +7204,39 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match reversed GE for MAVERICK - UGLY since we need to tst for Z=0 && N=0. ++(define_insn "*arm_bge_reversed" ++ [(set (pc) ++ (if_then_else (ge (match_operand:CCFP 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t.+12\;bvs\\t.+8\;b\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "12")] ++) ++ ++; Special pattern to match reversed UNLT for MAVERICK. ++(define_insn "*arm_bunlt_reversed" ++ [(set (pc) ++ (if_then_else (unlt (match_operand:CCFP 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++ + (define_insn "*arm_cond_branch_reversed" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7220,8 +7288,9 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++;; broken for cirrus - definitely + (define_expand "sge" + [(set (match_operand:SI 0 "s_register_operand" "") + (ge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM" ++ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +@@ -7227,6 +7296,14 @@ + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SGE these can not be represented with MAVERICK ++; (define_expand "sge" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "slt" + [(set (match_operand:SI 0 "s_register_operand" "") + (lt:SI (match_dup 1) (const_int 0)))] +@@ -7248,6 +7325,7 @@ + "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" + ) + ++;; broken for cirrus - maybe + (define_expand "sgeu" + [(set (match_operand:SI 0 "s_register_operand" "") + (geu:SI (match_dup 1) (const_int 0)))] +@@ -7255,6 +7333,14 @@ + "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SGEU these may not be represented with MAVERICK? ++; (define_expand "sgeu" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "sltu" + [(set (match_operand:SI 0 "s_register_operand" "") + (ltu:SI (match_dup 1) (const_int 0)))] +@@ -7281,7 +7367,7 @@ + (define_expand "sungt" + [(set (match_operand:SI 0 "s_register_operand" "") + (ungt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7289,23 +7375,32 @@ + (define_expand "sunge" + [(set (match_operand:SI 0 "s_register_operand" "") + (unge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, + arm_compare_op1);" + ) + ++; broken for cirrus + (define_expand "sunlt" + [(set (match_operand:SI 0 "s_register_operand" "") + (unlt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, + arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SUNLT these can't be represented with MAVERICK ++; (define_expand "sunlt" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (unlt:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "sunle" + [(set (match_operand:SI 0 "s_register_operand" "") + (unle:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7371,7 +7466,7 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) + FAIL; + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); +@@ -7390,7 +7485,8 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) ++ + FAIL; + + /* When compiling for SOFT_FLOAT, ensure both arms are in registers. +@@ -7409,13 +7505,13 @@ + (if_then_else:DF (match_operand 1 "arm_comparison_operator" "") + (match_operand:DF 2 "s_register_operand" "") + (match_operand:DF 3 "arm_float_add_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + " + { + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code==GE || code == UNLT || code == ORDERED || code == UNORDERED))) + FAIL; + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-compare.patch-z-eq b/packages/gcc/gcc-4.1.2/arm-crunch-compare.patch-z-eq new file mode 100644 index 0000000000..bc40411be4 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-compare.patch-z-eq @@ -0,0 +1,400 @@ +diff -urN gcc-4.1.2/gcc/config/arm/arm.c ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.c +--- gcc-4.1.2/gcc/config/arm/arm.c 2007-05-31 12:39:48.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-29 17:19:38.000000000 +1000 +@@ -11427,26 +11427,53 @@ + /* These encodings assume that AC=1 in the FPA system control + byte. This allows us to handle all cases except UNEQ and + LTGT. */ +- switch (comp_code) +- { +- case GE: return ARM_GE; +- case GT: return ARM_GT; +- case LE: return ARM_LS; +- case LT: return ARM_MI; +- case NE: return ARM_NE; +- case EQ: return ARM_EQ; +- case ORDERED: return ARM_VC; +- case UNORDERED: return ARM_VS; +- case UNLT: return ARM_LT; +- case UNLE: return ARM_LE; +- case UNGT: return ARM_HI; +- case UNGE: return ARM_PL; +- /* UNEQ and LTGT do not have a representation. */ +- case UNEQ: /* Fall through. */ +- case LTGT: /* Fall through. */ +- default: gcc_unreachable (); +- } +- ++ if (!TARGET_MAVERICK) ++ { ++ switch (comp_code) ++ { ++ case GE: return ARM_GE; ++ case GT: return ARM_GT; ++ case LE: return ARM_LS; ++ case LT: return ARM_MI; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case ORDERED: return ARM_VC; ++ case UNORDERED: return ARM_VS; ++ case UNLT: return ARM_LT; ++ case UNLE: return ARM_LE; ++ case UNGT: return ARM_HI; ++ case UNGE: return ARM_PL; ++ /* UNEQ and LTGT do not have a representation. */ ++ case UNEQ: /* Fall through. */ ++ case LTGT: /* Fall through. */ ++ default: gcc_unreachable (); ++ } ++ } ++ else ++ { ++ /* CIRRUS */ ++ switch (comp_code) ++ { ++#if 1 ++ case GT: return ARM_VS; ++ case LE: return ARM_LE; ++ case LT: return ARM_LT; ++ case NE: return ARM_NE; ++ case EQ: return ARM_EQ; ++ case UNLE: return ARM_VC; ++ case UNGT: return ARM_GT; ++ case UNGE: return ARM_GE; ++ case UNEQ: return ARM_PL; ++ case LTGT: return ARM_MI; ++ /* These do not have a representation. */ ++ case GE: /* Fall through. -UNGE wrong atm */ ++ case UNLT: /* Fall through. -LT wrong atm */ ++ case ORDERED: /* Fall through. -AL wrong atm */ ++ case UNORDERED: /* Fall through. -AL wrong atm */ ++#endif ++ default: gcc_unreachable (); ++ } ++ } + case CC_SWPmode: + switch (comp_code) + { +diff -urN gcc-4.1.2/gcc/config/arm/arm.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/arm.md +--- gcc-4.1.2/gcc/config/arm/arm.md 2007-05-31 12:39:48.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-05-29 15:17:18.000000000 +1000 +@@ -6952,10 +6952,11 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++;broken on cirrus + (define_expand "bge" + [(set (pc) + (if_then_else (ge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM" ++ "TARGET_ARM" + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +@@ -6988,6 +6989,7 @@ + "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" + ) + ++; broken on cirrus? + (define_expand "bgeu" + [(set (pc) + (if_then_else (geu (match_dup 1) (const_int 0)) +@@ -7031,14 +7033,15 @@ + (if_then_else (ungt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);" + ) + +-(define_expand "bunlt" ++; broken for cirrus ++(define_expand "bunlt" + [(set (pc) + (if_then_else (unlt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);" +@@ -7049,7 +7052,7 @@ + (if_then_else (unge (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7058,7 +7061,7 @@ + (if_then_else (unle (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7069,7 +7072,7 @@ + (if_then_else (uneq (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK + "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7078,7 +7081,7 @@ + (if_then_else (ltgt (match_dup 1) (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ;; || TARGET_MAVERICK + "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7086,7 +7089,7 @@ + ;; Patterns to match conditional branch insns. + ;; + +-; Special pattern to match UNEQ. ++; Special pattern to match UNEQ for FPA and VFP. + (define_insn "*arm_buneq" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7102,7 +7105,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match LTGT. ++; Special pattern to match LTGT for FPA and VFP. + (define_insn "*arm_bltgt" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7118,6 +7121,38 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match GE for MAVERICK. ++(define_insn "*arm_bge" ++ [(set (pc) ++ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && (TARGET_MAVERICK)" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++; Special pattern to match UNLT for MAVERICK. ++(define_insn "*arm_bunlt" ++ [(set (pc) ++ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0)) ++ (label_ref (match_operand 0 "" "")) ++ (pc)))] ++ "TARGET_ARM && (TARGET_MAVERICK)" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"bne\\t%l0\;bvc\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ + (define_insn "*arm_cond_branch" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7137,7 +7172,7 @@ + (set_attr "type" "branch")] + ) + +-; Special pattern to match reversed UNEQ. ++; Special pattern to match reversed UNEQ for FPA and VFP. + (define_insn "*arm_buneq_reversed" + [(set (pc) + (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7153,7 +7188,7 @@ + (set_attr "length" "8")] + ) + +-; Special pattern to match reversed LTGT. ++; Special pattern to match reversed LTGT for FPA and VFP. + (define_insn "*arm_bltgt_reversed" + [(set (pc) + (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) +@@ -7169,6 +7204,39 @@ + (set_attr "length" "8")] + ) + ++; Special pattern to match reversed GE for MAVERICK. ++(define_insn "*arm_bge_reversed" ++ [(set (pc) ++ (if_then_else (ge (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && (TARGET_MAVERICK)" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"bne\\t%l0\;bvc\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++; Special pattern to match reversed UNLT for MAVERICK. ++(define_insn "*arm_bunlt_reversed" ++ [(set (pc) ++ (if_then_else (unlt (match_operand 1 "cc_register" "") (const_int 0)) ++ (pc) ++ (label_ref (match_operand 0 "" ""))))] ++ "TARGET_ARM && (TARGET_MAVERICK)" ++ "* ++ gcc_assert (!arm_ccfsm_state); ++ ++ return \"beq\\t%l0\;bvs\\t%l0\"; ++ " ++ [(set_attr "conds" "jump_clob") ++ (set_attr "length" "8")] ++) ++ ++ + (define_insn "*arm_cond_branch_reversed" + [(set (pc) + (if_then_else (match_operator 1 "arm_comparison_operator" +@@ -7220,8 +7288,9 @@ + "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" + ) + ++;; broken for cirrus - definitely + (define_expand "sge" + [(set (match_operand:SI 0 "s_register_operand" "") + (ge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM" ++ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +@@ -7227,6 +7296,14 @@ + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SGE these can not be represented with MAVERICK ++; (define_expand "sge" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "slt" + [(set (match_operand:SI 0 "s_register_operand" "") + (lt:SI (match_dup 1) (const_int 0)))] +@@ -7248,6 +7325,7 @@ + "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" + ) + ++;; broken for cirrus - maybe + (define_expand "sgeu" + [(set (match_operand:SI 0 "s_register_operand" "") + (geu:SI (match_dup 1) (const_int 0)))] +@@ -7255,6 +7333,14 @@ + "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SGEU these may not be represented with MAVERICK? ++; (define_expand "sgeu" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "sltu" + [(set (match_operand:SI 0 "s_register_operand" "") + (ltu:SI (match_dup 1) (const_int 0)))] +@@ -7281,7 +7367,7 @@ + (define_expand "sungt" + [(set (match_operand:SI 0 "s_register_operand" "") + (ungt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7289,23 +7375,32 @@ + (define_expand "sunge" + [(set (match_operand:SI 0 "s_register_operand" "") + (unge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, + arm_compare_op1);" + ) + ++; broken for cirrus + (define_expand "sunlt" + [(set (match_operand:SI 0 "s_register_operand" "") + (unlt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, + arm_compare_op1);" + ) + ++;;; DO NOT add patterns for SUNLT these can't be represented with MAVERICK ++; (define_expand "sunlt" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (unlt:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && (TARGET_MAVERICK)" ++; "gcc_unreachable ();" ++; ) ++ + (define_expand "sunle" + [(set (match_operand:SI 0 "s_register_operand" "") + (unle:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7371,7 +7466,7 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if (code == UNEQ || code == LTGT || code == GE || code == UNLT || code == ORDERED || code == UNORDERED) + FAIL; + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); +@@ -7390,7 +7485,8 @@ + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if (code == UNEQ || code == LTGT || code == GE || code == UNLT || code == ORDERED || code == UNORDERED) ++ + FAIL; + + /* When compiling for SOFT_FLOAT, ensure both arms are in registers. +@@ -7409,13 +7505,13 @@ + (if_then_else:DF (match_operand 1 "arm_comparison_operator" "") + (match_operand:DF 2 "s_register_operand" "") + (match_operand:DF 3 "arm_float_add_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + " + { + enum rtx_code code = GET_CODE (operands[1]); + rtx ccreg; + +- if (code == UNEQ || code == LTGT) ++ if (code == UNEQ || code == LTGT || code == GE || code == UNLT || code == ORDERED || code == UNORDERED) + FAIL; + + ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-condexec-disable.patch b/packages/gcc/gcc-4.1.2/arm-crunch-condexec-disable.patch new file mode 100644 index 0000000000..6bb4370c63 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-condexec-disable.patch @@ -0,0 +1,5547 @@ +--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-27 16:41:36.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-27 17:28:11.000000000 +1000 +@@ -778,18 +778,18 @@ + [(set_attr "conds" "use")] + ) + +-(define_insn "incscc" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (plus:SI (match_operator:SI 2 "arm_comparison_operator" +- [(match_operand:CC 3 "cc_register" "") (const_int 0)]) +- (match_operand:SI 1 "s_register_operand" "0,?r")))] +- "TARGET_ARM" +- "@ +- add%d2\\t%0, %1, #1 +- mov%D2\\t%0, %1\;add%d2\\t%0, %1, #1" +- [(set_attr "conds" "use") +- (set_attr "length" "4,8")] +-) ++;(define_insn "incscc" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++; (plus:SI (match_operator:SI 2 "arm_comparison_operator" ++; [(match_operand:CC 3 "cc_register" "") (const_int 0)]) ++; (match_operand:SI 1 "s_register_operand" "0,?r")))] ++; "TARGET_ARM" ++; "@ ++; add%d2\\t%0, %1, #1 ++; mov%D2\\t%0, %1\;add%d2\\t%0, %1, #1" ++; [(set_attr "conds" "use") ++; (set_attr "length" "4,8")] ++;) + + ; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant. + (define_split +@@ -1015,18 +1015,18 @@ + [(set_attr "conds" "set")] + ) + +-(define_insn "decscc" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r") +- (match_operator:SI 2 "arm_comparison_operator" +- [(match_operand 3 "cc_register" "") (const_int 0)])))] +- "TARGET_ARM" +- "@ +- sub%d2\\t%0, %1, #1 +- mov%D2\\t%0, %1\;sub%d2\\t%0, %1, #1" +- [(set_attr "conds" "use") +- (set_attr "length" "*,8")] +-) ++;(define_insn "decscc" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++; (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r") ++; (match_operator:SI 2 "arm_comparison_operator" ++; [(match_operand 3 "cc_register" "") (const_int 0)])))] ++; "TARGET_ARM" ++; "@ ++; sub%d2\\t%0, %1, #1 ++; mov%D2\\t%0, %1\;sub%d2\\t%0, %1, #1" ++; [(set_attr "conds" "use") ++; (set_attr "length" "*,8")] ++;) + + (define_expand "subsf3" + [(set (match_operand:SF 0 "s_register_operand" "") +@@ -5729,1091 +5729,1091 @@ + ;; For a 'b' pos_range = 2046, neg_range = -2048 giving (-2040->2048). + ;; For a 'b<cond>' pos_range = 254, neg_range = -256 giving (-250 ->256). + +-(define_expand "cbranchsi4" +- [(set (pc) (if_then_else +- (match_operator 0 "arm_comparison_operator" +- [(match_operand:SI 1 "s_register_operand" "") +- (match_operand:SI 2 "nonmemory_operand" "")]) +- (label_ref (match_operand 3 "" "")) +- (pc)))] +- "TARGET_THUMB" +- " +- if (thumb_cmpneg_operand (operands[2], SImode)) +- { +- emit_jump_insn (gen_cbranchsi4_scratch (NULL, operands[1], operands[2], +- operands[3], operands[0])); +- DONE; +- } +- if (!thumb_cmp_operand (operands[2], SImode)) +- operands[2] = force_reg (SImode, operands[2]); +- ") ++;(define_expand "cbranchsi4" ++; [(set (pc) (if_then_else ++; (match_operator 0 "arm_comparison_operator" ++; [(match_operand:SI 1 "s_register_operand" "") ++; (match_operand:SI 2 "nonmemory_operand" "")]) ++; (label_ref (match_operand 3 "" "")) ++; (pc)))] ++; "TARGET_THUMB" ++; " ++; if (thumb_cmpneg_operand (operands[2], SImode)) ++; { ++; emit_jump_insn (gen_cbranchsi4_scratch (NULL, operands[1], operands[2], ++; operands[3], operands[0])); ++; DONE; ++; } ++; if (!thumb_cmp_operand (operands[2], SImode)) ++; operands[2] = force_reg (SImode, operands[2]); ++; ") ++ ++;(define_insn "*cbranchsi4_insn" ++; [(set (pc) (if_then_else ++; (match_operator 0 "arm_comparison_operator" ++; [(match_operand:SI 1 "s_register_operand" "l,*h") ++; (match_operand:SI 2 "thumb_cmp_operand" "lI*h,*r")]) ++; (label_ref (match_operand 3 "" "")) ++; (pc)))] ++; "TARGET_THUMB" ++; "* ++; output_asm_insn (\"cmp\\t%1, %2\", operands); ++; ++; switch (get_attr_length (insn)) ++; { ++; case 4: return \"b%d0\\t%l3\"; ++; case 6: return \"b%D0\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; ++; default: return \"b%D0\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; ++; } ++; " ++; [(set (attr "far_jump") ++; (if_then_else ++; (eq_attr "length" "8") ++; (const_string "yes") ++; (const_string "no"))) ++; (set (attr "length") ++; (if_then_else ++; (and (ge (minus (match_dup 3) (pc)) (const_int -250)) ++; (le (minus (match_dup 3) (pc)) (const_int 256))) ++; (const_int 4) ++; (if_then_else ++; (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) ++; (le (minus (match_dup 3) (pc)) (const_int 2048))) ++; (const_int 6) ++; (const_int 8))))] ++;) + +-(define_insn "*cbranchsi4_insn" +- [(set (pc) (if_then_else +- (match_operator 0 "arm_comparison_operator" +- [(match_operand:SI 1 "s_register_operand" "l,*h") +- (match_operand:SI 2 "thumb_cmp_operand" "lI*h,*r")]) +- (label_ref (match_operand 3 "" "")) +- (pc)))] +- "TARGET_THUMB" +- "* +- output_asm_insn (\"cmp\\t%1, %2\", operands); ++;(define_insn "cbranchsi4_scratch" ++; [(set (pc) (if_then_else ++; (match_operator 4 "arm_comparison_operator" ++; [(match_operand:SI 1 "s_register_operand" "l,0") ++; (match_operand:SI 2 "thumb_cmpneg_operand" "L,J")]) ++; (label_ref (match_operand 3 "" "")) ++; (pc))) ++; (clobber (match_scratch:SI 0 "=l,l"))] ++; "TARGET_THUMB" ++; "* ++; output_asm_insn (\"add\\t%0, %1, #%n2\", operands); ++; ++; switch (get_attr_length (insn)) ++; { ++; case 4: return \"b%d4\\t%l3\"; ++; case 6: return \"b%D4\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; ++; default: return \"b%D4\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; ++; } ++; " ++; [(set (attr "far_jump") ++; (if_then_else ++; (eq_attr "length" "8") ++; (const_string "yes") ++; (const_string "no"))) ++; (set (attr "length") ++; (if_then_else ++; (and (ge (minus (match_dup 3) (pc)) (const_int -250)) ++; (le (minus (match_dup 3) (pc)) (const_int 256))) ++; (const_int 4) ++; (if_then_else ++; (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) ++; (le (minus (match_dup 3) (pc)) (const_int 2048))) ++; (const_int 6) ++; (const_int 8))))] ++;) ++;(define_insn "*movsi_cbranchsi4" ++; [(set (pc) ++; (if_then_else ++; (match_operator 3 "arm_comparison_operator" ++; [(match_operand:SI 1 "s_register_operand" "0,l,l,l") ++; (const_int 0)]) ++; (label_ref (match_operand 2 "" "")) ++; (pc))) ++; (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,l,*h,*m") ++; (match_dup 1))] ++; "TARGET_THUMB" ++; "*{ ++; if (which_alternative == 0) ++; output_asm_insn (\"cmp\t%0, #0\", operands); ++; else if (which_alternative == 1) ++; output_asm_insn (\"sub\t%0, %1, #0\", operands); ++; else ++; { ++; output_asm_insn (\"cmp\t%1, #0\", operands); ++; if (which_alternative == 2) ++; output_asm_insn (\"mov\t%0, %1\", operands); ++; else ++; output_asm_insn (\"str\t%1, %0\", operands); ++; } ++; switch (get_attr_length (insn) - ((which_alternative > 1) ? 2 : 0)) ++; { ++; case 4: return \"b%d3\\t%l2\"; ++; case 6: return \"b%D3\\t.LCB%=\;b\\t%l2\\t%@long jump\\n.LCB%=:\"; ++; default: return \"b%D3\\t.LCB%=\;bl\\t%l2\\t%@far jump\\n.LCB%=:\"; ++; } ++; }" ++; [(set (attr "far_jump") ++; (if_then_else ++; (ior (and (gt (symbol_ref ("which_alternative")) ++; (const_int 1)) ++; (eq_attr "length" "8")) ++; (eq_attr "length" "10")) ++; (const_string "yes") ++; (const_string "no"))) ++; (set (attr "length") ++; (if_then_else ++; (le (symbol_ref ("which_alternative")) ++; (const_int 1)) ++; (if_then_else ++; (and (ge (minus (match_dup 2) (pc)) (const_int -250)) ++; (le (minus (match_dup 2) (pc)) (const_int 256))) ++; (const_int 4) ++; (if_then_else ++; (and (ge (minus (match_dup 2) (pc)) (const_int -2040)) ++; (le (minus (match_dup 2) (pc)) (const_int 2048))) ++; (const_int 6) ++; (const_int 8))) ++; (if_then_else ++; (and (ge (minus (match_dup 2) (pc)) (const_int -248)) ++; (le (minus (match_dup 2) (pc)) (const_int 256))) ++; (const_int 6) ++; (if_then_else ++; (and (ge (minus (match_dup 2) (pc)) (const_int -2038)) ++; (le (minus (match_dup 2) (pc)) (const_int 2048))) ++; (const_int 8) ++; (const_int 10)))))] ++;) + +- switch (get_attr_length (insn)) +- { +- case 4: return \"b%d0\\t%l3\"; +- case 6: return \"b%D0\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; +- default: return \"b%D0\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; +- } +- " +- [(set (attr "far_jump") +- (if_then_else +- (eq_attr "length" "8") +- (const_string "yes") +- (const_string "no"))) +- (set (attr "length") +- (if_then_else +- (and (ge (minus (match_dup 3) (pc)) (const_int -250)) +- (le (minus (match_dup 3) (pc)) (const_int 256))) +- (const_int 4) +- (if_then_else +- (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) +- (le (minus (match_dup 3) (pc)) (const_int 2048))) +- (const_int 6) +- (const_int 8))))] +-) +- +-(define_insn "cbranchsi4_scratch" +- [(set (pc) (if_then_else +- (match_operator 4 "arm_comparison_operator" +- [(match_operand:SI 1 "s_register_operand" "l,0") +- (match_operand:SI 2 "thumb_cmpneg_operand" "L,J")]) +- (label_ref (match_operand 3 "" "")) +- (pc))) +- (clobber (match_scratch:SI 0 "=l,l"))] +- "TARGET_THUMB" +- "* +- output_asm_insn (\"add\\t%0, %1, #%n2\", operands); ++;(define_insn "*negated_cbranchsi4" ++; [(set (pc) ++; (if_then_else ++; (match_operator 0 "equality_operator" ++; [(match_operand:SI 1 "s_register_operand" "l") ++; (neg:SI (match_operand:SI 2 "s_register_operand" "l"))]) ++; (label_ref (match_operand 3 "" "")) ++; (pc)))] ++; "TARGET_THUMB" ++; "* ++; output_asm_insn (\"cmn\\t%1, %2\", operands); ++; switch (get_attr_length (insn)) ++; { ++; case 4: return \"b%d0\\t%l3\"; ++; case 6: return \"b%D0\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; ++; default: return \"b%D0\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; ++; } ++; " ++; [(set (attr "far_jump") ++; (if_then_else ++; (eq_attr "length" "8") ++; (const_string "yes") ++; (const_string "no"))) ++; (set (attr "length") ++; (if_then_else ++; (and (ge (minus (match_dup 3) (pc)) (const_int -250)) ++; (le (minus (match_dup 3) (pc)) (const_int 256))) ++; (const_int 4) ++; (if_then_else ++; (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) ++; (le (minus (match_dup 3) (pc)) (const_int 2048))) ++; (const_int 6) ++; (const_int 8))))] ++;) + +- switch (get_attr_length (insn)) +- { +- case 4: return \"b%d4\\t%l3\"; +- case 6: return \"b%D4\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; +- default: return \"b%D4\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; +- } +- " +- [(set (attr "far_jump") +- (if_then_else +- (eq_attr "length" "8") +- (const_string "yes") +- (const_string "no"))) +- (set (attr "length") +- (if_then_else +- (and (ge (minus (match_dup 3) (pc)) (const_int -250)) +- (le (minus (match_dup 3) (pc)) (const_int 256))) +- (const_int 4) +- (if_then_else +- (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) +- (le (minus (match_dup 3) (pc)) (const_int 2048))) +- (const_int 6) +- (const_int 8))))] +-) +-(define_insn "*movsi_cbranchsi4" +- [(set (pc) +- (if_then_else +- (match_operator 3 "arm_comparison_operator" +- [(match_operand:SI 1 "s_register_operand" "0,l,l,l") +- (const_int 0)]) +- (label_ref (match_operand 2 "" "")) +- (pc))) +- (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,l,*h,*m") +- (match_dup 1))] +- "TARGET_THUMB" +- "*{ +- if (which_alternative == 0) +- output_asm_insn (\"cmp\t%0, #0\", operands); +- else if (which_alternative == 1) +- output_asm_insn (\"sub\t%0, %1, #0\", operands); +- else +- { +- output_asm_insn (\"cmp\t%1, #0\", operands); +- if (which_alternative == 2) +- output_asm_insn (\"mov\t%0, %1\", operands); +- else +- output_asm_insn (\"str\t%1, %0\", operands); +- } +- switch (get_attr_length (insn) - ((which_alternative > 1) ? 2 : 0)) +- { +- case 4: return \"b%d3\\t%l2\"; +- case 6: return \"b%D3\\t.LCB%=\;b\\t%l2\\t%@long jump\\n.LCB%=:\"; +- default: return \"b%D3\\t.LCB%=\;bl\\t%l2\\t%@far jump\\n.LCB%=:\"; +- } +- }" +- [(set (attr "far_jump") +- (if_then_else +- (ior (and (gt (symbol_ref ("which_alternative")) +- (const_int 1)) +- (eq_attr "length" "8")) +- (eq_attr "length" "10")) +- (const_string "yes") +- (const_string "no"))) +- (set (attr "length") +- (if_then_else +- (le (symbol_ref ("which_alternative")) +- (const_int 1)) +- (if_then_else +- (and (ge (minus (match_dup 2) (pc)) (const_int -250)) +- (le (minus (match_dup 2) (pc)) (const_int 256))) +- (const_int 4) +- (if_then_else +- (and (ge (minus (match_dup 2) (pc)) (const_int -2040)) +- (le (minus (match_dup 2) (pc)) (const_int 2048))) +- (const_int 6) +- (const_int 8))) +- (if_then_else +- (and (ge (minus (match_dup 2) (pc)) (const_int -248)) +- (le (minus (match_dup 2) (pc)) (const_int 256))) +- (const_int 6) +- (if_then_else +- (and (ge (minus (match_dup 2) (pc)) (const_int -2038)) +- (le (minus (match_dup 2) (pc)) (const_int 2048))) +- (const_int 8) +- (const_int 10)))))] +-) ++;(define_insn "*tbit_cbranch" ++; [(set (pc) ++; (if_then_else ++; (match_operator 0 "equality_operator" ++; [(zero_extract:SI (match_operand:SI 1 "s_register_operand" "l") ++; (const_int 1) ++; (match_operand:SI 2 "const_int_operand" "i")) ++; (const_int 0)]) ++; (label_ref (match_operand 3 "" "")) ++; (pc))) ++; (clobber (match_scratch:SI 4 "=l"))] ++; "TARGET_THUMB" ++; "* ++; { ++; rtx op[3]; ++; op[0] = operands[4]; ++; op[1] = operands[1]; ++; op[2] = GEN_INT (32 - 1 - INTVAL (operands[2])); ++; ++; output_asm_insn (\"lsl\\t%0, %1, %2\", op); ++; switch (get_attr_length (insn)) ++; { ++; case 4: return \"b%d0\\t%l3\"; ++; case 6: return \"b%D0\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; ++; default: return \"b%D0\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; ++; } ++; }" ++; [(set (attr "far_jump") ++; (if_then_else ++; (eq_attr "length" "8") ++; (const_string "yes") ++; (const_string "no"))) ++; (set (attr "length") ++; (if_then_else ++; (and (ge (minus (match_dup 3) (pc)) (const_int -250)) ++; (le (minus (match_dup 3) (pc)) (const_int 256))) ++; (const_int 4) ++; (if_then_else ++; (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) ++; (le (minus (match_dup 3) (pc)) (const_int 2048))) ++; (const_int 6) ++; (const_int 8))))] ++;) ++ ++;(define_insn "*tstsi3_cbranch" ++; [(set (pc) ++; (if_then_else ++; (match_operator 3 "equality_operator" ++; [(and:SI (match_operand:SI 0 "s_register_operand" "%l") ++; (match_operand:SI 1 "s_register_operand" "l")) ++; (const_int 0)]) ++; (label_ref (match_operand 2 "" "")) ++; (pc)))] ++; "TARGET_THUMB" ++; "* ++; { ++; output_asm_insn (\"tst\\t%0, %1\", operands); ++; switch (get_attr_length (insn)) ++; { ++; case 4: return \"b%d3\\t%l2\"; ++; case 6: return \"b%D3\\t.LCB%=\;b\\t%l2\\t%@long jump\\n.LCB%=:\"; ++; default: return \"b%D3\\t.LCB%=\;bl\\t%l2\\t%@far jump\\n.LCB%=:\"; ++; } ++; }" ++; [(set (attr "far_jump") ++; (if_then_else ++; (eq_attr "length" "8") ++; (const_string "yes") ++; (const_string "no"))) ++; (set (attr "length") ++; (if_then_else ++; (and (ge (minus (match_dup 2) (pc)) (const_int -250)) ++; (le (minus (match_dup 2) (pc)) (const_int 256))) ++; (const_int 4) ++; (if_then_else ++; (and (ge (minus (match_dup 2) (pc)) (const_int -2040)) ++; (le (minus (match_dup 2) (pc)) (const_int 2048))) ++; (const_int 6) ++; (const_int 8))))] ++;) ++ ++;(define_insn "*andsi3_cbranch" ++; [(set (pc) ++; (if_then_else ++; (match_operator 5 "equality_operator" ++; [(and:SI (match_operand:SI 2 "s_register_operand" "%0,1,1,1") ++; (match_operand:SI 3 "s_register_operand" "l,l,l,l")) ++; (const_int 0)]) ++; (label_ref (match_operand 4 "" "")) ++; (pc))) ++; (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") ++; (and:SI (match_dup 2) (match_dup 3))) ++; (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] ++; "TARGET_THUMB" ++; "* ++; { ++; if (which_alternative == 0) ++; output_asm_insn (\"and\\t%0, %3\", operands); ++; else if (which_alternative == 1) ++; { ++; output_asm_insn (\"and\\t%1, %3\", operands); ++; output_asm_insn (\"mov\\t%0, %1\", operands); ++; } ++; else ++; { ++; output_asm_insn (\"and\\t%1, %3\", operands); ++; output_asm_insn (\"str\\t%1, %0\", operands); ++; } ++; ++; switch (get_attr_length (insn) - (which_alternative ? 2 : 0)) ++; { ++; case 4: return \"b%d5\\t%l4\"; ++; case 6: return \"b%D5\\t.LCB%=\;b\\t%l4\\t%@long jump\\n.LCB%=:\"; ++; default: return \"b%D5\\t.LCB%=\;bl\\t%l4\\t%@far jump\\n.LCB%=:\"; ++; } ++; }" ++; [(set (attr "far_jump") ++; (if_then_else ++; (ior (and (eq (symbol_ref ("which_alternative")) ++; (const_int 0)) ++; (eq_attr "length" "8")) ++; (eq_attr "length" "10")) ++; (const_string "yes") ++; (const_string "no"))) ++; (set (attr "length") ++; (if_then_else ++; (eq (symbol_ref ("which_alternative")) ++; (const_int 0)) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -250)) ++; (le (minus (match_dup 4) (pc)) (const_int 256))) ++; (const_int 4) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -2040)) ++; (le (minus (match_dup 4) (pc)) (const_int 2048))) ++; (const_int 6) ++; (const_int 8))) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -248)) ++; (le (minus (match_dup 4) (pc)) (const_int 256))) ++; (const_int 6) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) ++; (le (minus (match_dup 4) (pc)) (const_int 2048))) ++; (const_int 8) ++; (const_int 10)))))] ++;) + +-(define_insn "*negated_cbranchsi4" +- [(set (pc) +- (if_then_else +- (match_operator 0 "equality_operator" +- [(match_operand:SI 1 "s_register_operand" "l") +- (neg:SI (match_operand:SI 2 "s_register_operand" "l"))]) +- (label_ref (match_operand 3 "" "")) +- (pc)))] +- "TARGET_THUMB" +- "* +- output_asm_insn (\"cmn\\t%1, %2\", operands); +- switch (get_attr_length (insn)) +- { +- case 4: return \"b%d0\\t%l3\"; +- case 6: return \"b%D0\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; +- default: return \"b%D0\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; +- } +- " +- [(set (attr "far_jump") +- (if_then_else +- (eq_attr "length" "8") +- (const_string "yes") +- (const_string "no"))) +- (set (attr "length") +- (if_then_else +- (and (ge (minus (match_dup 3) (pc)) (const_int -250)) +- (le (minus (match_dup 3) (pc)) (const_int 256))) +- (const_int 4) +- (if_then_else +- (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) +- (le (minus (match_dup 3) (pc)) (const_int 2048))) +- (const_int 6) +- (const_int 8))))] +-) ++;(define_insn "*orrsi3_cbranch_scratch" ++; [(set (pc) ++; (if_then_else ++; (match_operator 4 "equality_operator" ++; [(ior:SI (match_operand:SI 1 "s_register_operand" "%0") ++; (match_operand:SI 2 "s_register_operand" "l")) ++; (const_int 0)]) ++; (label_ref (match_operand 3 "" "")) ++; (pc))) ++; (clobber (match_scratch:SI 0 "=l"))] ++; "TARGET_THUMB" ++; "* ++; { ++; output_asm_insn (\"orr\\t%0, %2\", operands); ++; switch (get_attr_length (insn)) ++; { ++; case 4: return \"b%d4\\t%l3\"; ++; case 6: return \"b%D4\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; ++; default: return \"b%D4\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; ++; } ++; }" ++; [(set (attr "far_jump") ++; (if_then_else ++; (eq_attr "length" "8") ++; (const_string "yes") ++; (const_string "no"))) ++; (set (attr "length") ++; (if_then_else ++; (and (ge (minus (match_dup 3) (pc)) (const_int -250)) ++; (le (minus (match_dup 3) (pc)) (const_int 256))) ++; (const_int 4) ++; (if_then_else ++; (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) ++; (le (minus (match_dup 3) (pc)) (const_int 2048))) ++; (const_int 6) ++; (const_int 8))))] ++;) ++ ++;(define_insn "*orrsi3_cbranch" ++; [(set (pc) ++; (if_then_else ++; (match_operator 5 "equality_operator" ++; [(ior:SI (match_operand:SI 2 "s_register_operand" "%0,1,1,1") ++; (match_operand:SI 3 "s_register_operand" "l,l,l,l")) ++; (const_int 0)]) ++; (label_ref (match_operand 4 "" "")) ++; (pc))) ++; (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") ++; (ior:SI (match_dup 2) (match_dup 3))) ++; (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] ++; "TARGET_THUMB" ++; "* ++; { ++; if (which_alternative == 0) ++; output_asm_insn (\"orr\\t%0, %3\", operands); ++; else if (which_alternative == 1) ++; { ++; output_asm_insn (\"orr\\t%1, %3\", operands); ++; output_asm_insn (\"mov\\t%0, %1\", operands); ++; } ++; else ++; { ++; output_asm_insn (\"orr\\t%1, %3\", operands); ++; output_asm_insn (\"str\\t%1, %0\", operands); ++; } ++; ++; switch (get_attr_length (insn) - (which_alternative ? 2 : 0)) ++; { ++; case 4: return \"b%d5\\t%l4\"; ++; case 6: return \"b%D5\\t.LCB%=\;b\\t%l4\\t%@long jump\\n.LCB%=:\"; ++; default: return \"b%D5\\t.LCB%=\;bl\\t%l4\\t%@far jump\\n.LCB%=:\"; ++; } ++; }" ++; [(set (attr "far_jump") ++; (if_then_else ++; (ior (and (eq (symbol_ref ("which_alternative")) ++; (const_int 0)) ++; (eq_attr "length" "8")) ++; (eq_attr "length" "10")) ++; (const_string "yes") ++; (const_string "no"))) ++; (set (attr "length") ++; (if_then_else ++; (eq (symbol_ref ("which_alternative")) ++; (const_int 0)) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -250)) ++; (le (minus (match_dup 4) (pc)) (const_int 256))) ++; (const_int 4) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -2040)) ++; (le (minus (match_dup 4) (pc)) (const_int 2048))) ++; (const_int 6) ++; (const_int 8))) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -248)) ++; (le (minus (match_dup 4) (pc)) (const_int 256))) ++; (const_int 6) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) ++; (le (minus (match_dup 4) (pc)) (const_int 2048))) ++; (const_int 8) ++; (const_int 10)))))] ++;) + +-(define_insn "*tbit_cbranch" +- [(set (pc) +- (if_then_else +- (match_operator 0 "equality_operator" +- [(zero_extract:SI (match_operand:SI 1 "s_register_operand" "l") +- (const_int 1) +- (match_operand:SI 2 "const_int_operand" "i")) +- (const_int 0)]) +- (label_ref (match_operand 3 "" "")) +- (pc))) +- (clobber (match_scratch:SI 4 "=l"))] +- "TARGET_THUMB" +- "* +- { +- rtx op[3]; +- op[0] = operands[4]; +- op[1] = operands[1]; +- op[2] = GEN_INT (32 - 1 - INTVAL (operands[2])); +- +- output_asm_insn (\"lsl\\t%0, %1, %2\", op); +- switch (get_attr_length (insn)) +- { +- case 4: return \"b%d0\\t%l3\"; +- case 6: return \"b%D0\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; +- default: return \"b%D0\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; +- } +- }" +- [(set (attr "far_jump") +- (if_then_else +- (eq_attr "length" "8") +- (const_string "yes") +- (const_string "no"))) +- (set (attr "length") +- (if_then_else +- (and (ge (minus (match_dup 3) (pc)) (const_int -250)) +- (le (minus (match_dup 3) (pc)) (const_int 256))) +- (const_int 4) +- (if_then_else +- (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) +- (le (minus (match_dup 3) (pc)) (const_int 2048))) +- (const_int 6) +- (const_int 8))))] +-) ++;(define_insn "*xorsi3_cbranch_scratch" ++; [(set (pc) ++; (if_then_else ++; (match_operator 4 "equality_operator" ++; [(xor:SI (match_operand:SI 1 "s_register_operand" "%0") ++; (match_operand:SI 2 "s_register_operand" "l")) ++; (const_int 0)]) ++; (label_ref (match_operand 3 "" "")) ++; (pc))) ++; (clobber (match_scratch:SI 0 "=l"))] ++; "TARGET_THUMB" ++; "* ++; { ++; output_asm_insn (\"eor\\t%0, %2\", operands); ++; switch (get_attr_length (insn)) ++; { ++; case 4: return \"b%d4\\t%l3\"; ++; case 6: return \"b%D4\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; ++; default: return \"b%D4\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; ++; } ++; }" ++; [(set (attr "far_jump") ++; (if_then_else ++; (eq_attr "length" "8") ++; (const_string "yes") ++; (const_string "no"))) ++; (set (attr "length") ++; (if_then_else ++; (and (ge (minus (match_dup 3) (pc)) (const_int -250)) ++; (le (minus (match_dup 3) (pc)) (const_int 256))) ++; (const_int 4) ++; (if_then_else ++; (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) ++; (le (minus (match_dup 3) (pc)) (const_int 2048))) ++; (const_int 6) ++; (const_int 8))))] ++;) + +-(define_insn "*tstsi3_cbranch" +- [(set (pc) +- (if_then_else +- (match_operator 3 "equality_operator" +- [(and:SI (match_operand:SI 0 "s_register_operand" "%l") +- (match_operand:SI 1 "s_register_operand" "l")) +- (const_int 0)]) +- (label_ref (match_operand 2 "" "")) +- (pc)))] +- "TARGET_THUMB" +- "* +- { +- output_asm_insn (\"tst\\t%0, %1\", operands); +- switch (get_attr_length (insn)) +- { +- case 4: return \"b%d3\\t%l2\"; +- case 6: return \"b%D3\\t.LCB%=\;b\\t%l2\\t%@long jump\\n.LCB%=:\"; +- default: return \"b%D3\\t.LCB%=\;bl\\t%l2\\t%@far jump\\n.LCB%=:\"; +- } +- }" +- [(set (attr "far_jump") +- (if_then_else +- (eq_attr "length" "8") +- (const_string "yes") +- (const_string "no"))) +- (set (attr "length") +- (if_then_else +- (and (ge (minus (match_dup 2) (pc)) (const_int -250)) +- (le (minus (match_dup 2) (pc)) (const_int 256))) +- (const_int 4) +- (if_then_else +- (and (ge (minus (match_dup 2) (pc)) (const_int -2040)) +- (le (minus (match_dup 2) (pc)) (const_int 2048))) +- (const_int 6) +- (const_int 8))))] +-) ++;(define_insn "*xorsi3_cbranch" ++; [(set (pc) ++; (if_then_else ++; (match_operator 5 "equality_operator" ++; [(xor:SI (match_operand:SI 2 "s_register_operand" "%0,1,1,1") ++; (match_operand:SI 3 "s_register_operand" "l,l,l,l")) ++; (const_int 0)]) ++; (label_ref (match_operand 4 "" "")) ++; (pc))) ++; (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") ++; (xor:SI (match_dup 2) (match_dup 3))) ++; (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] ++; "TARGET_THUMB" ++; "* ++; { ++; if (which_alternative == 0) ++; output_asm_insn (\"eor\\t%0, %3\", operands); ++; else if (which_alternative == 1) ++; { ++; output_asm_insn (\"eor\\t%1, %3\", operands); ++; output_asm_insn (\"mov\\t%0, %1\", operands); ++; } ++; else ++; { ++; output_asm_insn (\"eor\\t%1, %3\", operands); ++; output_asm_insn (\"str\\t%1, %0\", operands); ++; } ++; ++; switch (get_attr_length (insn) - (which_alternative ? 2 : 0)) ++; { ++; case 4: return \"b%d5\\t%l4\"; ++; case 6: return \"b%D5\\t.LCB%=\;b\\t%l4\\t%@long jump\\n.LCB%=:\"; ++; default: return \"b%D5\\t.LCB%=\;bl\\t%l4\\t%@far jump\\n.LCB%=:\"; ++; } ++; }" ++; [(set (attr "far_jump") ++; (if_then_else ++; (ior (and (eq (symbol_ref ("which_alternative")) ++; (const_int 0)) ++; (eq_attr "length" "8")) ++; (eq_attr "length" "10")) ++; (const_string "yes") ++; (const_string "no"))) ++; (set (attr "length") ++; (if_then_else ++; (eq (symbol_ref ("which_alternative")) ++; (const_int 0)) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -250)) ++; (le (minus (match_dup 4) (pc)) (const_int 256))) ++; (const_int 4) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -2040)) ++; (le (minus (match_dup 4) (pc)) (const_int 2048))) ++; (const_int 6) ++; (const_int 8))) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -248)) ++; (le (minus (match_dup 4) (pc)) (const_int 256))) ++; (const_int 6) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) ++; (le (minus (match_dup 4) (pc)) (const_int 2048))) ++; (const_int 8) ++; (const_int 10)))))] ++;) ++ ++;(define_insn "*bicsi3_cbranch_scratch" ++; [(set (pc) ++; (if_then_else ++; (match_operator 4 "equality_operator" ++; [(and:SI (not:SI (match_operand:SI 2 "s_register_operand" "l")) ++; (match_operand:SI 1 "s_register_operand" "0")) ++; (const_int 0)]) ++; (label_ref (match_operand 3 "" "")) ++; (pc))) ++; (clobber (match_scratch:SI 0 "=l"))] ++; "TARGET_THUMB" ++; "* ++; { ++; output_asm_insn (\"bic\\t%0, %2\", operands); ++; switch (get_attr_length (insn)) ++; { ++; case 4: return \"b%d4\\t%l3\"; ++; case 6: return \"b%D4\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; ++; default: return \"b%D4\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; ++; } ++; }" ++; [(set (attr "far_jump") ++; (if_then_else ++; (eq_attr "length" "8") ++; (const_string "yes") ++; (const_string "no"))) ++; (set (attr "length") ++; (if_then_else ++; (and (ge (minus (match_dup 3) (pc)) (const_int -250)) ++; (le (minus (match_dup 3) (pc)) (const_int 256))) ++; (const_int 4) ++; (if_then_else ++; (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) ++; (le (minus (match_dup 3) (pc)) (const_int 2048))) ++; (const_int 6) ++; (const_int 8))))] ++;) + +-(define_insn "*andsi3_cbranch" +- [(set (pc) +- (if_then_else +- (match_operator 5 "equality_operator" +- [(and:SI (match_operand:SI 2 "s_register_operand" "%0,1,1,1") +- (match_operand:SI 3 "s_register_operand" "l,l,l,l")) +- (const_int 0)]) +- (label_ref (match_operand 4 "" "")) +- (pc))) +- (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") +- (and:SI (match_dup 2) (match_dup 3))) +- (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] +- "TARGET_THUMB" +- "* +- { +- if (which_alternative == 0) +- output_asm_insn (\"and\\t%0, %3\", operands); +- else if (which_alternative == 1) +- { +- output_asm_insn (\"and\\t%1, %3\", operands); +- output_asm_insn (\"mov\\t%0, %1\", operands); +- } +- else +- { +- output_asm_insn (\"and\\t%1, %3\", operands); +- output_asm_insn (\"str\\t%1, %0\", operands); +- } ++;(define_insn "*bicsi3_cbranch" ++; [(set (pc) ++; (if_then_else ++; (match_operator 5 "equality_operator" ++; [(and:SI (not:SI (match_operand:SI 3 "s_register_operand" "l,l,l,l,l")) ++; (match_operand:SI 2 "s_register_operand" "0,1,1,1,1")) ++; (const_int 0)]) ++; (label_ref (match_operand 4 "" "")) ++; (pc))) ++; (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=!l,l,*?h,*?m,*?m") ++; (and:SI (not:SI (match_dup 3)) (match_dup 2))) ++; (clobber (match_scratch:SI 1 "=X,l,l,&l,&l"))] ++; "TARGET_THUMB" ++; "* ++; { ++; if (which_alternative == 0) ++; output_asm_insn (\"bic\\t%0, %3\", operands); ++; else if (which_alternative <= 2) ++; { ++; output_asm_insn (\"bic\\t%1, %3\", operands); ++; /* It's ok if OP0 is a lo-reg, even though the mov will set the ++; conditions again, since we're only testing for equality. */ ++; output_asm_insn (\"mov\\t%0, %1\", operands); ++; } ++; else ++; { ++; output_asm_insn (\"bic\\t%1, %3\", operands); ++; output_asm_insn (\"str\\t%1, %0\", operands); ++; } ++; ++; switch (get_attr_length (insn) - (which_alternative ? 2 : 0)) ++; { ++; case 4: return \"b%d5\\t%l4\"; ++; case 6: return \"b%D5\\t.LCB%=\;b\\t%l4\\t%@long jump\\n.LCB%=:\"; ++; default: return \"b%D5\\t.LCB%=\;bl\\t%l4\\t%@far jump\\n.LCB%=:\"; ++; } ++; }" ++; [(set (attr "far_jump") ++; (if_then_else ++; (ior (and (eq (symbol_ref ("which_alternative")) ++; (const_int 0)) ++; (eq_attr "length" "8")) ++; (eq_attr "length" "10")) ++; (const_string "yes") ++; (const_string "no"))) ++; (set (attr "length") ++; (if_then_else ++; (eq (symbol_ref ("which_alternative")) ++; (const_int 0)) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -250)) ++; (le (minus (match_dup 4) (pc)) (const_int 256))) ++; (const_int 4) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -2040)) ++; (le (minus (match_dup 4) (pc)) (const_int 2048))) ++; (const_int 6) ++; (const_int 8))) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -248)) ++; (le (minus (match_dup 4) (pc)) (const_int 256))) ++; (const_int 6) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) ++; (le (minus (match_dup 4) (pc)) (const_int 2048))) ++; (const_int 8) ++; (const_int 10)))))] ++;) + +- switch (get_attr_length (insn) - (which_alternative ? 2 : 0)) +- { +- case 4: return \"b%d5\\t%l4\"; +- case 6: return \"b%D5\\t.LCB%=\;b\\t%l4\\t%@long jump\\n.LCB%=:\"; +- default: return \"b%D5\\t.LCB%=\;bl\\t%l4\\t%@far jump\\n.LCB%=:\"; +- } ++;(define_insn "*cbranchne_decr1" ++; [(set (pc) ++; (if_then_else (match_operator 3 "equality_operator" ++; [(match_operand:SI 2 "s_register_operand" "l,l,1,l") ++; (const_int 0)]) ++; (label_ref (match_operand 4 "" "")) ++; (pc))) ++; (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") ++; (plus:SI (match_dup 2) (const_int -1))) ++; (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] ++; "TARGET_THUMB" ++; "* ++; { ++; rtx cond[2]; ++; cond[0] = gen_rtx_fmt_ee ((GET_CODE (operands[3]) == NE ++; ? GEU : LTU), ++; VOIDmode, operands[2], const1_rtx); ++; cond[1] = operands[4]; ++; ++; if (which_alternative == 0) ++; output_asm_insn (\"sub\\t%0, %2, #1\", operands); ++; else if (which_alternative == 1) ++; { ++; /* We must provide an alternative for a hi reg because reload ++; cannot handle output reloads on a jump instruction, but we ++; can't subtract into that. Fortunately a mov from lo to hi ++; does not clobber the condition codes. */ ++; output_asm_insn (\"sub\\t%1, %2, #1\", operands); ++; output_asm_insn (\"mov\\t%0, %1\", operands); ++; } ++; else ++; { ++; /* Similarly, but the target is memory. */ ++; output_asm_insn (\"sub\\t%1, %2, #1\", operands); ++; output_asm_insn (\"str\\t%1, %0\", operands); ++; } ++; ++; switch (get_attr_length (insn) - (which_alternative ? 2 : 0)) ++; { ++; case 4: ++; output_asm_insn (\"b%d0\\t%l1\", cond); ++; return \"\"; ++; case 6: ++; output_asm_insn (\"b%D0\\t.LCB%=\", cond); ++; return \"b\\t%l4\\t%@long jump\\n.LCB%=:\"; ++; default: ++; output_asm_insn (\"b%D0\\t.LCB%=\", cond); ++; return \"bl\\t%l4\\t%@far jump\\n.LCB%=:\"; ++; } ++; } ++; " ++; [(set (attr "far_jump") ++; (if_then_else ++; (ior (and (eq (symbol_ref ("which_alternative")) ++; (const_int 0)) ++; (eq_attr "length" "8")) ++; (eq_attr "length" "10")) ++; (const_string "yes") ++; (const_string "no"))) ++; (set_attr_alternative "length" ++; [ ++; ;; Alternative 0 ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -250)) ++; (le (minus (match_dup 4) (pc)) (const_int 256))) ++; (const_int 4) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -2040)) ++; (le (minus (match_dup 4) (pc)) (const_int 2048))) ++; (const_int 6) ++; (const_int 8))) ++; ;; Alternative 1 ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -248)) ++; (le (minus (match_dup 4) (pc)) (const_int 256))) ++; (const_int 6) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) ++; (le (minus (match_dup 4) (pc)) (const_int 2048))) ++; (const_int 8) ++; (const_int 10))) ++; ;; Alternative 2 ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -248)) ++; (le (minus (match_dup 4) (pc)) (const_int 256))) ++; (const_int 6) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) ++; (le (minus (match_dup 4) (pc)) (const_int 2048))) ++; (const_int 8) ++; (const_int 10))) ++; ;; Alternative 3 ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -248)) ++; (le (minus (match_dup 4) (pc)) (const_int 256))) ++; (const_int 6) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) ++; (le (minus (match_dup 4) (pc)) (const_int 2048))) ++; (const_int 8) ++; (const_int 10)))])] ++;) ++ ++;(define_insn "*addsi3_cbranch" ++; [(set (pc) ++; (if_then_else ++; (match_operator 4 "comparison_operator" ++; [(plus:SI ++; (match_operand:SI 2 "s_register_operand" "%l,0,*0,1,1,1") ++; (match_operand:SI 3 "reg_or_int_operand" "lL,IJ,*r,lIJ,lIJ,lIJ")) ++; (const_int 0)]) ++; (label_ref (match_operand 5 "" "")) ++; (pc))) ++; (set ++; (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,l,*!h,*?h,*?m,*?m") ++; (plus:SI (match_dup 2) (match_dup 3))) ++; (clobber (match_scratch:SI 1 "=X,X,X,l,&l,&l"))] ++; "TARGET_THUMB ++; && (GET_CODE (operands[4]) == EQ ++; || GET_CODE (operands[4]) == NE ++; || GET_CODE (operands[4]) == GE ++; || GET_CODE (operands[4]) == LT)" ++; "* ++; { ++; rtx cond[3]; ++; ++; ++; cond[0] = (which_alternative < 3) ? operands[0] : operands[1]; ++; cond[1] = operands[2]; ++; cond[2] = operands[3]; ++; ++; if (GET_CODE (cond[2]) == CONST_INT && INTVAL (cond[2]) < 0) ++; output_asm_insn (\"sub\\t%0, %1, #%n2\", cond); ++; else ++; output_asm_insn (\"add\\t%0, %1, %2\", cond); ++; ++; if (which_alternative >= 3 ++; && which_alternative < 4) ++; output_asm_insn (\"mov\\t%0, %1\", operands); ++; else if (which_alternative >= 4) ++; output_asm_insn (\"str\\t%1, %0\", operands); ++; ++; switch (get_attr_length (insn) - ((which_alternative >= 3) ? 2 : 0)) ++; { ++; case 4: ++; return \"b%d4\\t%l5\"; ++; case 6: ++; return \"b%D4\\t.LCB%=\;b\\t%l5\\t%@long jump\\n.LCB%=:\"; ++; default: ++; return \"b%D4\\t.LCB%=\;bl\\t%l5\\t%@far jump\\n.LCB%=:\"; ++; } ++; } ++; " ++; [(set (attr "far_jump") ++; (if_then_else ++; (ior (and (lt (symbol_ref ("which_alternative")) ++; (const_int 3)) ++; (eq_attr "length" "8")) ++; (eq_attr "length" "10")) ++; (const_string "yes") ++; (const_string "no"))) ++; (set (attr "length") ++; (if_then_else ++; (lt (symbol_ref ("which_alternative")) ++; (const_int 3)) ++; (if_then_else ++; (and (ge (minus (match_dup 5) (pc)) (const_int -250)) ++; (le (minus (match_dup 5) (pc)) (const_int 256))) ++; (const_int 4) ++; (if_then_else ++; (and (ge (minus (match_dup 5) (pc)) (const_int -2040)) ++; (le (minus (match_dup 5) (pc)) (const_int 2048))) ++; (const_int 6) ++; (const_int 8))) ++; (if_then_else ++; (and (ge (minus (match_dup 5) (pc)) (const_int -248)) ++; (le (minus (match_dup 5) (pc)) (const_int 256))) ++; (const_int 6) ++; (if_then_else ++; (and (ge (minus (match_dup 5) (pc)) (const_int -2038)) ++; (le (minus (match_dup 5) (pc)) (const_int 2048))) ++; (const_int 8) ++; (const_int 10)))))] ++;) ++ ++;(define_insn "*addsi3_cbranch_scratch" ++; [(set (pc) ++; (if_then_else ++; (match_operator 3 "comparison_operator" ++; [(plus:SI ++; (match_operand:SI 1 "s_register_operand" "%l,l,l,0") ++; (match_operand:SI 2 "reg_or_int_operand" "J,l,L,IJ")) ++; (const_int 0)]) ++; (label_ref (match_operand 4 "" "")) ++; (pc))) ++; (clobber (match_scratch:SI 0 "=X,X,l,l"))] ++; "TARGET_THUMB ++; && (GET_CODE (operands[3]) == EQ ++; || GET_CODE (operands[3]) == NE ++; || GET_CODE (operands[3]) == GE ++; || GET_CODE (operands[3]) == LT)" ++; "* ++; { ++; switch (which_alternative) ++; { ++; case 0: ++; output_asm_insn (\"cmp\t%1, #%n2\", operands); ++; break; ++; case 1: ++; output_asm_insn (\"cmn\t%1, %2\", operands); ++; break; ++; case 2: ++; if (INTVAL (operands[2]) < 0) ++; output_asm_insn (\"sub\t%0, %1, %2\", operands); ++; else ++; output_asm_insn (\"add\t%0, %1, %2\", operands); ++; break; ++; case 3: ++; if (INTVAL (operands[2]) < 0) ++; output_asm_insn (\"sub\t%0, %0, %2\", operands); ++; else ++; output_asm_insn (\"add\t%0, %0, %2\", operands); ++; break; ++; } ++; ++; switch (get_attr_length (insn)) ++; { ++; case 4: ++; return \"b%d3\\t%l4\"; ++; case 6: ++; return \"b%D3\\t.LCB%=\;b\\t%l4\\t%@long jump\\n.LCB%=:\"; ++; default: ++; return \"b%D3\\t.LCB%=\;bl\\t%l4\\t%@far jump\\n.LCB%=:\"; ++; } ++; } ++; " ++; [(set (attr "far_jump") ++; (if_then_else ++; (eq_attr "length" "8") ++; (const_string "yes") ++; (const_string "no"))) ++; (set (attr "length") ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -250)) ++; (le (minus (match_dup 4) (pc)) (const_int 256))) ++; (const_int 4) ++; (if_then_else ++; (and (ge (minus (match_dup 4) (pc)) (const_int -2040)) ++; (le (minus (match_dup 4) (pc)) (const_int 2048))) ++; (const_int 6) ++; (const_int 8))))] ++;) ++ ++;(define_insn "*subsi3_cbranch" ++; [(set (pc) ++; (if_then_else ++; (match_operator 4 "comparison_operator" ++; [(minus:SI ++; (match_operand:SI 2 "s_register_operand" "l,l,1,l") ++; (match_operand:SI 3 "s_register_operand" "l,l,l,l")) ++; (const_int 0)]) ++; (label_ref (match_operand 5 "" "")) ++; (pc))) ++; (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") ++; (minus:SI (match_dup 2) (match_dup 3))) ++; (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] ++; "TARGET_THUMB ++; && (GET_CODE (operands[4]) == EQ ++; || GET_CODE (operands[4]) == NE ++; || GET_CODE (operands[4]) == GE ++; || GET_CODE (operands[4]) == LT)" ++; "* ++; { ++; if (which_alternative == 0) ++; output_asm_insn (\"sub\\t%0, %2, %3\", operands); ++; else if (which_alternative == 1) ++; { ++; /* We must provide an alternative for a hi reg because reload ++; cannot handle output reloads on a jump instruction, but we ++; can't subtract into that. Fortunately a mov from lo to hi ++; does not clobber the condition codes. */ ++; output_asm_insn (\"sub\\t%1, %2, %3\", operands); ++; output_asm_insn (\"mov\\t%0, %1\", operands); ++; } ++; else ++; { ++; /* Similarly, but the target is memory. */ ++; output_asm_insn (\"sub\\t%1, %2, %3\", operands); ++; output_asm_insn (\"str\\t%1, %0\", operands); ++; } ++; ++; switch (get_attr_length (insn) - ((which_alternative != 0) ? 2 : 0)) ++; { ++; case 4: ++; return \"b%d4\\t%l5\"; ++; case 6: ++; return \"b%D4\\t.LCB%=\;b\\t%l5\\t%@long jump\\n.LCB%=:\"; ++; default: ++; return \"b%D4\\t.LCB%=\;bl\\t%l5\\t%@far jump\\n.LCB%=:\"; ++; } ++; } ++; " ++; [(set (attr "far_jump") ++; (if_then_else ++; (ior (and (eq (symbol_ref ("which_alternative")) ++; (const_int 0)) ++; (eq_attr "length" "8")) ++; (eq_attr "length" "10")) ++; (const_string "yes") ++; (const_string "no"))) ++; (set (attr "length") ++; (if_then_else ++; (eq (symbol_ref ("which_alternative")) ++; (const_int 0)) ++; (if_then_else ++; (and (ge (minus (match_dup 5) (pc)) (const_int -250)) ++; (le (minus (match_dup 5) (pc)) (const_int 256))) ++; (const_int 4) ++; (if_then_else ++; (and (ge (minus (match_dup 5) (pc)) (const_int -2040)) ++; (le (minus (match_dup 5) (pc)) (const_int 2048))) ++; (const_int 6) ++; (const_int 8))) ++; (if_then_else ++; (and (ge (minus (match_dup 5) (pc)) (const_int -248)) ++; (le (minus (match_dup 5) (pc)) (const_int 256))) ++; (const_int 6) ++; (if_then_else ++; (and (ge (minus (match_dup 5) (pc)) (const_int -2038)) ++; (le (minus (match_dup 5) (pc)) (const_int 2048))) ++; (const_int 8) ++; (const_int 10)))))] ++;) ++ ++;(define_insn "*subsi3_cbranch_scratch" ++; [(set (pc) ++; (if_then_else ++; (match_operator 0 "arm_comparison_operator" ++; [(minus:SI (match_operand:SI 1 "register_operand" "l") ++; (match_operand:SI 2 "nonmemory_operand" "l")) ++; (const_int 0)]) ++; (label_ref (match_operand 3 "" "")) ++; (pc)))] ++; "TARGET_THUMB ++; && (GET_CODE (operands[0]) == EQ ++; || GET_CODE (operands[0]) == NE ++; || GET_CODE (operands[0]) == GE ++; || GET_CODE (operands[0]) == LT)" ++; "* ++; output_asm_insn (\"cmp\\t%1, %2\", operands); ++; switch (get_attr_length (insn)) ++; { ++; case 4: return \"b%d0\\t%l3\"; ++; case 6: return \"b%D0\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; ++; default: return \"b%D0\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; ++; } ++; " ++; [(set (attr "far_jump") ++; (if_then_else ++; (eq_attr "length" "8") ++; (const_string "yes") ++; (const_string "no"))) ++; (set (attr "length") ++; (if_then_else ++; (and (ge (minus (match_dup 3) (pc)) (const_int -250)) ++; (le (minus (match_dup 3) (pc)) (const_int 256))) ++; (const_int 4) ++; (if_then_else ++; (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) ++; (le (minus (match_dup 3) (pc)) (const_int 2048))) ++; (const_int 6) ++; (const_int 8))))] ++;) ++ ++;; Comparison and test insns ++ ++(define_expand "cmpsi" ++ [(match_operand:SI 0 "s_register_operand" "") ++ (match_operand:SI 1 "arm_add_operand" "")] ++ "TARGET_ARM" ++ "{ ++ arm_compare_op0 = operands[0]; ++ arm_compare_op1 = operands[1]; ++ DONE; + }" +- [(set (attr "far_jump") +- (if_then_else +- (ior (and (eq (symbol_ref ("which_alternative")) +- (const_int 0)) +- (eq_attr "length" "8")) +- (eq_attr "length" "10")) +- (const_string "yes") +- (const_string "no"))) +- (set (attr "length") +- (if_then_else +- (eq (symbol_ref ("which_alternative")) +- (const_int 0)) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -250)) +- (le (minus (match_dup 4) (pc)) (const_int 256))) +- (const_int 4) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -2040)) +- (le (minus (match_dup 4) (pc)) (const_int 2048))) +- (const_int 6) +- (const_int 8))) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -248)) +- (le (minus (match_dup 4) (pc)) (const_int 256))) +- (const_int 6) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) +- (le (minus (match_dup 4) (pc)) (const_int 2048))) +- (const_int 8) +- (const_int 10)))))] + ) + +-(define_insn "*orrsi3_cbranch_scratch" +- [(set (pc) +- (if_then_else +- (match_operator 4 "equality_operator" +- [(ior:SI (match_operand:SI 1 "s_register_operand" "%0") +- (match_operand:SI 2 "s_register_operand" "l")) +- (const_int 0)]) +- (label_ref (match_operand 3 "" "")) +- (pc))) +- (clobber (match_scratch:SI 0 "=l"))] +- "TARGET_THUMB" +- "* +- { +- output_asm_insn (\"orr\\t%0, %2\", operands); +- switch (get_attr_length (insn)) +- { +- case 4: return \"b%d4\\t%l3\"; +- case 6: return \"b%D4\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; +- default: return \"b%D4\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; +- } +- }" +- [(set (attr "far_jump") +- (if_then_else +- (eq_attr "length" "8") +- (const_string "yes") +- (const_string "no"))) +- (set (attr "length") +- (if_then_else +- (and (ge (minus (match_dup 3) (pc)) (const_int -250)) +- (le (minus (match_dup 3) (pc)) (const_int 256))) +- (const_int 4) +- (if_then_else +- (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) +- (le (minus (match_dup 3) (pc)) (const_int 2048))) +- (const_int 6) +- (const_int 8))))] ++(define_expand "cmpsf" ++ [(match_operand:SF 0 "s_register_operand" "") ++ (match_operand:SF 1 "arm_float_compare_operand" "")] ++ "TARGET_ARM && TARGET_HARD_FLOAT" ++ " ++ arm_compare_op0 = operands[0]; ++ arm_compare_op1 = operands[1]; ++ DONE; ++ " + ) +- +-(define_insn "*orrsi3_cbranch" +- [(set (pc) +- (if_then_else +- (match_operator 5 "equality_operator" +- [(ior:SI (match_operand:SI 2 "s_register_operand" "%0,1,1,1") +- (match_operand:SI 3 "s_register_operand" "l,l,l,l")) +- (const_int 0)]) +- (label_ref (match_operand 4 "" "")) +- (pc))) +- (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") +- (ior:SI (match_dup 2) (match_dup 3))) +- (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] +- "TARGET_THUMB" +- "* +- { +- if (which_alternative == 0) +- output_asm_insn (\"orr\\t%0, %3\", operands); +- else if (which_alternative == 1) +- { +- output_asm_insn (\"orr\\t%1, %3\", operands); +- output_asm_insn (\"mov\\t%0, %1\", operands); +- } +- else +- { +- output_asm_insn (\"orr\\t%1, %3\", operands); +- output_asm_insn (\"str\\t%1, %0\", operands); +- } + +- switch (get_attr_length (insn) - (which_alternative ? 2 : 0)) +- { +- case 4: return \"b%d5\\t%l4\"; +- case 6: return \"b%D5\\t.LCB%=\;b\\t%l4\\t%@long jump\\n.LCB%=:\"; +- default: return \"b%D5\\t.LCB%=\;bl\\t%l4\\t%@far jump\\n.LCB%=:\"; +- } +- }" +- [(set (attr "far_jump") +- (if_then_else +- (ior (and (eq (symbol_ref ("which_alternative")) +- (const_int 0)) +- (eq_attr "length" "8")) +- (eq_attr "length" "10")) +- (const_string "yes") +- (const_string "no"))) +- (set (attr "length") +- (if_then_else +- (eq (symbol_ref ("which_alternative")) +- (const_int 0)) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -250)) +- (le (minus (match_dup 4) (pc)) (const_int 256))) +- (const_int 4) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -2040)) +- (le (minus (match_dup 4) (pc)) (const_int 2048))) +- (const_int 6) +- (const_int 8))) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -248)) +- (le (minus (match_dup 4) (pc)) (const_int 256))) +- (const_int 6) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) +- (le (minus (match_dup 4) (pc)) (const_int 2048))) +- (const_int 8) +- (const_int 10)))))] ++(define_expand "cmpdf" ++ [(match_operand:DF 0 "s_register_operand" "") ++ (match_operand:DF 1 "arm_float_compare_operand" "")] ++ "TARGET_ARM && TARGET_HARD_FLOAT" ++ " ++ arm_compare_op0 = operands[0]; ++ arm_compare_op1 = operands[1]; ++ DONE; ++ " + ) + +-(define_insn "*xorsi3_cbranch_scratch" +- [(set (pc) +- (if_then_else +- (match_operator 4 "equality_operator" +- [(xor:SI (match_operand:SI 1 "s_register_operand" "%0") +- (match_operand:SI 2 "s_register_operand" "l")) +- (const_int 0)]) +- (label_ref (match_operand 3 "" "")) +- (pc))) +- (clobber (match_scratch:SI 0 "=l"))] +- "TARGET_THUMB" +- "* +- { +- output_asm_insn (\"eor\\t%0, %2\", operands); +- switch (get_attr_length (insn)) +- { +- case 4: return \"b%d4\\t%l3\"; +- case 6: return \"b%D4\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; +- default: return \"b%D4\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; +- } +- }" +- [(set (attr "far_jump") +- (if_then_else +- (eq_attr "length" "8") +- (const_string "yes") +- (const_string "no"))) +- (set (attr "length") +- (if_then_else +- (and (ge (minus (match_dup 3) (pc)) (const_int -250)) +- (le (minus (match_dup 3) (pc)) (const_int 256))) +- (const_int 4) +- (if_then_else +- (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) +- (le (minus (match_dup 3) (pc)) (const_int 2048))) +- (const_int 6) +- (const_int 8))))] ++(define_insn "*arm_cmpsi_insn" ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_operand:SI 0 "s_register_operand" "r,r") ++ (match_operand:SI 1 "arm_add_operand" "rI,L")))] ++ "TARGET_ARM" ++ "@ ++ cmp%?\\t%0, %1 ++ cmn%?\\t%0, #%n1" ++ [(set_attr "conds" "set")] + ) +- +-(define_insn "*xorsi3_cbranch" +- [(set (pc) +- (if_then_else +- (match_operator 5 "equality_operator" +- [(xor:SI (match_operand:SI 2 "s_register_operand" "%0,1,1,1") +- (match_operand:SI 3 "s_register_operand" "l,l,l,l")) +- (const_int 0)]) +- (label_ref (match_operand 4 "" "")) +- (pc))) +- (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") +- (xor:SI (match_dup 2) (match_dup 3))) +- (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] +- "TARGET_THUMB" +- "* +- { +- if (which_alternative == 0) +- output_asm_insn (\"eor\\t%0, %3\", operands); +- else if (which_alternative == 1) +- { +- output_asm_insn (\"eor\\t%1, %3\", operands); +- output_asm_insn (\"mov\\t%0, %1\", operands); +- } +- else +- { +- output_asm_insn (\"eor\\t%1, %3\", operands); +- output_asm_insn (\"str\\t%1, %0\", operands); +- } + +- switch (get_attr_length (insn) - (which_alternative ? 2 : 0)) +- { +- case 4: return \"b%d5\\t%l4\"; +- case 6: return \"b%D5\\t.LCB%=\;b\\t%l4\\t%@long jump\\n.LCB%=:\"; +- default: return \"b%D5\\t.LCB%=\;bl\\t%l4\\t%@far jump\\n.LCB%=:\"; +- } +- }" +- [(set (attr "far_jump") +- (if_then_else +- (ior (and (eq (symbol_ref ("which_alternative")) +- (const_int 0)) +- (eq_attr "length" "8")) +- (eq_attr "length" "10")) +- (const_string "yes") +- (const_string "no"))) +- (set (attr "length") +- (if_then_else +- (eq (symbol_ref ("which_alternative")) +- (const_int 0)) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -250)) +- (le (minus (match_dup 4) (pc)) (const_int 256))) +- (const_int 4) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -2040)) +- (le (minus (match_dup 4) (pc)) (const_int 2048))) +- (const_int 6) +- (const_int 8))) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -248)) +- (le (minus (match_dup 4) (pc)) (const_int 256))) +- (const_int 6) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) +- (le (minus (match_dup 4) (pc)) (const_int 2048))) +- (const_int 8) +- (const_int 10)))))] +-) +- +-(define_insn "*bicsi3_cbranch_scratch" +- [(set (pc) +- (if_then_else +- (match_operator 4 "equality_operator" +- [(and:SI (not:SI (match_operand:SI 2 "s_register_operand" "l")) +- (match_operand:SI 1 "s_register_operand" "0")) +- (const_int 0)]) +- (label_ref (match_operand 3 "" "")) +- (pc))) +- (clobber (match_scratch:SI 0 "=l"))] +- "TARGET_THUMB" +- "* +- { +- output_asm_insn (\"bic\\t%0, %2\", operands); +- switch (get_attr_length (insn)) +- { +- case 4: return \"b%d4\\t%l3\"; +- case 6: return \"b%D4\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; +- default: return \"b%D4\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; +- } +- }" +- [(set (attr "far_jump") +- (if_then_else +- (eq_attr "length" "8") +- (const_string "yes") +- (const_string "no"))) +- (set (attr "length") +- (if_then_else +- (and (ge (minus (match_dup 3) (pc)) (const_int -250)) +- (le (minus (match_dup 3) (pc)) (const_int 256))) +- (const_int 4) +- (if_then_else +- (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) +- (le (minus (match_dup 3) (pc)) (const_int 2048))) +- (const_int 6) +- (const_int 8))))] +-) +- +-(define_insn "*bicsi3_cbranch" +- [(set (pc) +- (if_then_else +- (match_operator 5 "equality_operator" +- [(and:SI (not:SI (match_operand:SI 3 "s_register_operand" "l,l,l,l,l")) +- (match_operand:SI 2 "s_register_operand" "0,1,1,1,1")) +- (const_int 0)]) +- (label_ref (match_operand 4 "" "")) +- (pc))) +- (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=!l,l,*?h,*?m,*?m") +- (and:SI (not:SI (match_dup 3)) (match_dup 2))) +- (clobber (match_scratch:SI 1 "=X,l,l,&l,&l"))] +- "TARGET_THUMB" +- "* +- { +- if (which_alternative == 0) +- output_asm_insn (\"bic\\t%0, %3\", operands); +- else if (which_alternative <= 2) +- { +- output_asm_insn (\"bic\\t%1, %3\", operands); +- /* It's ok if OP0 is a lo-reg, even though the mov will set the +- conditions again, since we're only testing for equality. */ +- output_asm_insn (\"mov\\t%0, %1\", operands); +- } +- else +- { +- output_asm_insn (\"bic\\t%1, %3\", operands); +- output_asm_insn (\"str\\t%1, %0\", operands); +- } +- +- switch (get_attr_length (insn) - (which_alternative ? 2 : 0)) +- { +- case 4: return \"b%d5\\t%l4\"; +- case 6: return \"b%D5\\t.LCB%=\;b\\t%l4\\t%@long jump\\n.LCB%=:\"; +- default: return \"b%D5\\t.LCB%=\;bl\\t%l4\\t%@far jump\\n.LCB%=:\"; +- } +- }" +- [(set (attr "far_jump") +- (if_then_else +- (ior (and (eq (symbol_ref ("which_alternative")) +- (const_int 0)) +- (eq_attr "length" "8")) +- (eq_attr "length" "10")) +- (const_string "yes") +- (const_string "no"))) +- (set (attr "length") +- (if_then_else +- (eq (symbol_ref ("which_alternative")) +- (const_int 0)) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -250)) +- (le (minus (match_dup 4) (pc)) (const_int 256))) +- (const_int 4) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -2040)) +- (le (minus (match_dup 4) (pc)) (const_int 2048))) +- (const_int 6) +- (const_int 8))) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -248)) +- (le (minus (match_dup 4) (pc)) (const_int 256))) +- (const_int 6) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) +- (le (minus (match_dup 4) (pc)) (const_int 2048))) +- (const_int 8) +- (const_int 10)))))] +-) +- +-(define_insn "*cbranchne_decr1" +- [(set (pc) +- (if_then_else (match_operator 3 "equality_operator" +- [(match_operand:SI 2 "s_register_operand" "l,l,1,l") +- (const_int 0)]) +- (label_ref (match_operand 4 "" "")) +- (pc))) +- (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") +- (plus:SI (match_dup 2) (const_int -1))) +- (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] +- "TARGET_THUMB" +- "* +- { +- rtx cond[2]; +- cond[0] = gen_rtx_fmt_ee ((GET_CODE (operands[3]) == NE +- ? GEU : LTU), +- VOIDmode, operands[2], const1_rtx); +- cond[1] = operands[4]; +- +- if (which_alternative == 0) +- output_asm_insn (\"sub\\t%0, %2, #1\", operands); +- else if (which_alternative == 1) +- { +- /* We must provide an alternative for a hi reg because reload +- cannot handle output reloads on a jump instruction, but we +- can't subtract into that. Fortunately a mov from lo to hi +- does not clobber the condition codes. */ +- output_asm_insn (\"sub\\t%1, %2, #1\", operands); +- output_asm_insn (\"mov\\t%0, %1\", operands); +- } +- else +- { +- /* Similarly, but the target is memory. */ +- output_asm_insn (\"sub\\t%1, %2, #1\", operands); +- output_asm_insn (\"str\\t%1, %0\", operands); +- } +- +- switch (get_attr_length (insn) - (which_alternative ? 2 : 0)) +- { +- case 4: +- output_asm_insn (\"b%d0\\t%l1\", cond); +- return \"\"; +- case 6: +- output_asm_insn (\"b%D0\\t.LCB%=\", cond); +- return \"b\\t%l4\\t%@long jump\\n.LCB%=:\"; +- default: +- output_asm_insn (\"b%D0\\t.LCB%=\", cond); +- return \"bl\\t%l4\\t%@far jump\\n.LCB%=:\"; +- } +- } +- " +- [(set (attr "far_jump") +- (if_then_else +- (ior (and (eq (symbol_ref ("which_alternative")) +- (const_int 0)) +- (eq_attr "length" "8")) +- (eq_attr "length" "10")) +- (const_string "yes") +- (const_string "no"))) +- (set_attr_alternative "length" +- [ +- ;; Alternative 0 +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -250)) +- (le (minus (match_dup 4) (pc)) (const_int 256))) +- (const_int 4) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -2040)) +- (le (minus (match_dup 4) (pc)) (const_int 2048))) +- (const_int 6) +- (const_int 8))) +- ;; Alternative 1 +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -248)) +- (le (minus (match_dup 4) (pc)) (const_int 256))) +- (const_int 6) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) +- (le (minus (match_dup 4) (pc)) (const_int 2048))) +- (const_int 8) +- (const_int 10))) +- ;; Alternative 2 +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -248)) +- (le (minus (match_dup 4) (pc)) (const_int 256))) +- (const_int 6) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) +- (le (minus (match_dup 4) (pc)) (const_int 2048))) +- (const_int 8) +- (const_int 10))) +- ;; Alternative 3 +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -248)) +- (le (minus (match_dup 4) (pc)) (const_int 256))) +- (const_int 6) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) +- (le (minus (match_dup 4) (pc)) (const_int 2048))) +- (const_int 8) +- (const_int 10)))])] +-) +- +-(define_insn "*addsi3_cbranch" +- [(set (pc) +- (if_then_else +- (match_operator 4 "comparison_operator" +- [(plus:SI +- (match_operand:SI 2 "s_register_operand" "%l,0,*0,1,1,1") +- (match_operand:SI 3 "reg_or_int_operand" "lL,IJ,*r,lIJ,lIJ,lIJ")) +- (const_int 0)]) +- (label_ref (match_operand 5 "" "")) +- (pc))) +- (set +- (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,l,*!h,*?h,*?m,*?m") +- (plus:SI (match_dup 2) (match_dup 3))) +- (clobber (match_scratch:SI 1 "=X,X,X,l,&l,&l"))] +- "TARGET_THUMB +- && (GET_CODE (operands[4]) == EQ +- || GET_CODE (operands[4]) == NE +- || GET_CODE (operands[4]) == GE +- || GET_CODE (operands[4]) == LT)" +- "* +- { +- rtx cond[3]; +- +- +- cond[0] = (which_alternative < 3) ? operands[0] : operands[1]; +- cond[1] = operands[2]; +- cond[2] = operands[3]; +- +- if (GET_CODE (cond[2]) == CONST_INT && INTVAL (cond[2]) < 0) +- output_asm_insn (\"sub\\t%0, %1, #%n2\", cond); +- else +- output_asm_insn (\"add\\t%0, %1, %2\", cond); +- +- if (which_alternative >= 3 +- && which_alternative < 4) +- output_asm_insn (\"mov\\t%0, %1\", operands); +- else if (which_alternative >= 4) +- output_asm_insn (\"str\\t%1, %0\", operands); +- +- switch (get_attr_length (insn) - ((which_alternative >= 3) ? 2 : 0)) +- { +- case 4: +- return \"b%d4\\t%l5\"; +- case 6: +- return \"b%D4\\t.LCB%=\;b\\t%l5\\t%@long jump\\n.LCB%=:\"; +- default: +- return \"b%D4\\t.LCB%=\;bl\\t%l5\\t%@far jump\\n.LCB%=:\"; +- } +- } +- " +- [(set (attr "far_jump") +- (if_then_else +- (ior (and (lt (symbol_ref ("which_alternative")) +- (const_int 3)) +- (eq_attr "length" "8")) +- (eq_attr "length" "10")) +- (const_string "yes") +- (const_string "no"))) +- (set (attr "length") +- (if_then_else +- (lt (symbol_ref ("which_alternative")) +- (const_int 3)) +- (if_then_else +- (and (ge (minus (match_dup 5) (pc)) (const_int -250)) +- (le (minus (match_dup 5) (pc)) (const_int 256))) +- (const_int 4) +- (if_then_else +- (and (ge (minus (match_dup 5) (pc)) (const_int -2040)) +- (le (minus (match_dup 5) (pc)) (const_int 2048))) +- (const_int 6) +- (const_int 8))) +- (if_then_else +- (and (ge (minus (match_dup 5) (pc)) (const_int -248)) +- (le (minus (match_dup 5) (pc)) (const_int 256))) +- (const_int 6) +- (if_then_else +- (and (ge (minus (match_dup 5) (pc)) (const_int -2038)) +- (le (minus (match_dup 5) (pc)) (const_int 2048))) +- (const_int 8) +- (const_int 10)))))] +-) +- +-(define_insn "*addsi3_cbranch_scratch" +- [(set (pc) +- (if_then_else +- (match_operator 3 "comparison_operator" +- [(plus:SI +- (match_operand:SI 1 "s_register_operand" "%l,l,l,0") +- (match_operand:SI 2 "reg_or_int_operand" "J,l,L,IJ")) +- (const_int 0)]) +- (label_ref (match_operand 4 "" "")) +- (pc))) +- (clobber (match_scratch:SI 0 "=X,X,l,l"))] +- "TARGET_THUMB +- && (GET_CODE (operands[3]) == EQ +- || GET_CODE (operands[3]) == NE +- || GET_CODE (operands[3]) == GE +- || GET_CODE (operands[3]) == LT)" +- "* +- { +- switch (which_alternative) +- { +- case 0: +- output_asm_insn (\"cmp\t%1, #%n2\", operands); +- break; +- case 1: +- output_asm_insn (\"cmn\t%1, %2\", operands); +- break; +- case 2: +- if (INTVAL (operands[2]) < 0) +- output_asm_insn (\"sub\t%0, %1, %2\", operands); +- else +- output_asm_insn (\"add\t%0, %1, %2\", operands); +- break; +- case 3: +- if (INTVAL (operands[2]) < 0) +- output_asm_insn (\"sub\t%0, %0, %2\", operands); +- else +- output_asm_insn (\"add\t%0, %0, %2\", operands); +- break; +- } +- +- switch (get_attr_length (insn)) +- { +- case 4: +- return \"b%d3\\t%l4\"; +- case 6: +- return \"b%D3\\t.LCB%=\;b\\t%l4\\t%@long jump\\n.LCB%=:\"; +- default: +- return \"b%D3\\t.LCB%=\;bl\\t%l4\\t%@far jump\\n.LCB%=:\"; +- } +- } +- " +- [(set (attr "far_jump") +- (if_then_else +- (eq_attr "length" "8") +- (const_string "yes") +- (const_string "no"))) +- (set (attr "length") +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -250)) +- (le (minus (match_dup 4) (pc)) (const_int 256))) +- (const_int 4) +- (if_then_else +- (and (ge (minus (match_dup 4) (pc)) (const_int -2040)) +- (le (minus (match_dup 4) (pc)) (const_int 2048))) +- (const_int 6) +- (const_int 8))))] +-) +- +-(define_insn "*subsi3_cbranch" +- [(set (pc) +- (if_then_else +- (match_operator 4 "comparison_operator" +- [(minus:SI +- (match_operand:SI 2 "s_register_operand" "l,l,1,l") +- (match_operand:SI 3 "s_register_operand" "l,l,l,l")) +- (const_int 0)]) +- (label_ref (match_operand 5 "" "")) +- (pc))) +- (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") +- (minus:SI (match_dup 2) (match_dup 3))) +- (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] +- "TARGET_THUMB +- && (GET_CODE (operands[4]) == EQ +- || GET_CODE (operands[4]) == NE +- || GET_CODE (operands[4]) == GE +- || GET_CODE (operands[4]) == LT)" +- "* +- { +- if (which_alternative == 0) +- output_asm_insn (\"sub\\t%0, %2, %3\", operands); +- else if (which_alternative == 1) +- { +- /* We must provide an alternative for a hi reg because reload +- cannot handle output reloads on a jump instruction, but we +- can't subtract into that. Fortunately a mov from lo to hi +- does not clobber the condition codes. */ +- output_asm_insn (\"sub\\t%1, %2, %3\", operands); +- output_asm_insn (\"mov\\t%0, %1\", operands); +- } +- else +- { +- /* Similarly, but the target is memory. */ +- output_asm_insn (\"sub\\t%1, %2, %3\", operands); +- output_asm_insn (\"str\\t%1, %0\", operands); +- } +- +- switch (get_attr_length (insn) - ((which_alternative != 0) ? 2 : 0)) +- { +- case 4: +- return \"b%d4\\t%l5\"; +- case 6: +- return \"b%D4\\t.LCB%=\;b\\t%l5\\t%@long jump\\n.LCB%=:\"; +- default: +- return \"b%D4\\t.LCB%=\;bl\\t%l5\\t%@far jump\\n.LCB%=:\"; +- } +- } +- " +- [(set (attr "far_jump") +- (if_then_else +- (ior (and (eq (symbol_ref ("which_alternative")) +- (const_int 0)) +- (eq_attr "length" "8")) +- (eq_attr "length" "10")) +- (const_string "yes") +- (const_string "no"))) +- (set (attr "length") +- (if_then_else +- (eq (symbol_ref ("which_alternative")) +- (const_int 0)) +- (if_then_else +- (and (ge (minus (match_dup 5) (pc)) (const_int -250)) +- (le (minus (match_dup 5) (pc)) (const_int 256))) +- (const_int 4) +- (if_then_else +- (and (ge (minus (match_dup 5) (pc)) (const_int -2040)) +- (le (minus (match_dup 5) (pc)) (const_int 2048))) +- (const_int 6) +- (const_int 8))) +- (if_then_else +- (and (ge (minus (match_dup 5) (pc)) (const_int -248)) +- (le (minus (match_dup 5) (pc)) (const_int 256))) +- (const_int 6) +- (if_then_else +- (and (ge (minus (match_dup 5) (pc)) (const_int -2038)) +- (le (minus (match_dup 5) (pc)) (const_int 2048))) +- (const_int 8) +- (const_int 10)))))] +-) +- +-(define_insn "*subsi3_cbranch_scratch" +- [(set (pc) +- (if_then_else +- (match_operator 0 "arm_comparison_operator" +- [(minus:SI (match_operand:SI 1 "register_operand" "l") +- (match_operand:SI 2 "nonmemory_operand" "l")) +- (const_int 0)]) +- (label_ref (match_operand 3 "" "")) +- (pc)))] +- "TARGET_THUMB +- && (GET_CODE (operands[0]) == EQ +- || GET_CODE (operands[0]) == NE +- || GET_CODE (operands[0]) == GE +- || GET_CODE (operands[0]) == LT)" +- "* +- output_asm_insn (\"cmp\\t%1, %2\", operands); +- switch (get_attr_length (insn)) +- { +- case 4: return \"b%d0\\t%l3\"; +- case 6: return \"b%D0\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; +- default: return \"b%D0\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; +- } +- " +- [(set (attr "far_jump") +- (if_then_else +- (eq_attr "length" "8") +- (const_string "yes") +- (const_string "no"))) +- (set (attr "length") +- (if_then_else +- (and (ge (minus (match_dup 3) (pc)) (const_int -250)) +- (le (minus (match_dup 3) (pc)) (const_int 256))) +- (const_int 4) +- (if_then_else +- (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) +- (le (minus (match_dup 3) (pc)) (const_int 2048))) +- (const_int 6) +- (const_int 8))))] +-) +- +-;; Comparison and test insns +- +-(define_expand "cmpsi" +- [(match_operand:SI 0 "s_register_operand" "") +- (match_operand:SI 1 "arm_add_operand" "")] +- "TARGET_ARM" +- "{ +- arm_compare_op0 = operands[0]; +- arm_compare_op1 = operands[1]; +- DONE; +- }" +-) +- +-(define_expand "cmpsf" +- [(match_operand:SF 0 "s_register_operand" "") +- (match_operand:SF 1 "arm_float_compare_operand" "")] +- "TARGET_ARM && TARGET_HARD_FLOAT" +- " +- arm_compare_op0 = operands[0]; +- arm_compare_op1 = operands[1]; +- DONE; +- " +-) +- +-(define_expand "cmpdf" +- [(match_operand:DF 0 "s_register_operand" "") +- (match_operand:DF 1 "arm_float_compare_operand" "")] +- "TARGET_ARM && TARGET_HARD_FLOAT" +- " +- arm_compare_op0 = operands[0]; +- arm_compare_op1 = operands[1]; +- DONE; +- " +-) +- +-(define_insn "*arm_cmpsi_insn" +- [(set (reg:CC CC_REGNUM) +- (compare:CC (match_operand:SI 0 "s_register_operand" "r,r") +- (match_operand:SI 1 "arm_add_operand" "rI,L")))] +- "TARGET_ARM" +- "@ +- cmp%?\\t%0, %1 +- cmn%?\\t%0, #%n1" +- [(set_attr "conds" "set")] +-) +- +-(define_insn "*cmpsi_shiftsi" +- [(set (reg:CC CC_REGNUM) +- (compare:CC (match_operand:SI 0 "s_register_operand" "r") +- (match_operator:SI 3 "shift_operator" +- [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "arm_rhs_operand" "rM")])))] +- "TARGET_ARM" +- "cmp%?\\t%0, %1%S3" +- [(set_attr "conds" "set") +- (set_attr "shift" "1") +- (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") +- (const_string "alu_shift") +- (const_string "alu_shift_reg")))] ++(define_insn "*cmpsi_shiftsi" ++ [(set (reg:CC CC_REGNUM) ++ (compare:CC (match_operand:SI 0 "s_register_operand" "r") ++ (match_operator:SI 3 "shift_operator" ++ [(match_operand:SI 1 "s_register_operand" "r") ++ (match_operand:SI 2 "arm_rhs_operand" "rM")])))] ++ "TARGET_ARM" ++ "cmp%?\\t%0, %1%S3" ++ [(set_attr "conds" "set") ++ (set_attr "shift" "1") ++ (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") ++ (const_string "alu_shift") ++ (const_string "alu_shift_reg")))] + ) + + (define_insn "*cmpsi_shiftsi_swp" +@@ -7315,41 +7315,41 @@ + + ; scc insns + +-(define_expand "seq" +- [(set (match_operand:SI 0 "s_register_operand" "") +- (eq:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM" +- "operands[1] = arm_gen_compare_reg (EQ, arm_compare_op0, arm_compare_op1);" +-) ++;(define_expand "seq" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (eq:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM" ++; "operands[1] = arm_gen_compare_reg (EQ, arm_compare_op0, arm_compare_op1);" ++;) + +-(define_expand "sne" +- [(set (match_operand:SI 0 "s_register_operand" "") +- (ne:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM" +- "operands[1] = arm_gen_compare_reg (NE, arm_compare_op0, arm_compare_op1);" +-) ++;(define_expand "sne" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ne:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM" ++; "operands[1] = arm_gen_compare_reg (NE, arm_compare_op0, arm_compare_op1);" ++;) + +-(define_expand "sgt" +- [(set (match_operand:SI 0 "s_register_operand" "") +- (gt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM" +- "operands[1] = arm_gen_compare_reg (GT, arm_compare_op0, arm_compare_op1);" +-) ++;(define_expand "sgt" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (gt:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM" ++; "operands[1] = arm_gen_compare_reg (GT, arm_compare_op0, arm_compare_op1);" ++;) + +-(define_expand "sle" +- [(set (match_operand:SI 0 "s_register_operand" "") +- (le:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM" +- "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" +-) ++;(define_expand "sle" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (le:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM" ++; "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" ++;) + + ;; broken for cirrus - definitely +-(define_expand "sge" +- [(set (match_operand:SI 0 "s_register_operand" "") +- (ge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" +- "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" +-) ++;(define_expand "sge" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" ++; "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" ++;) + + ;;; DO NOT add patterns for SGE these can not be represented with MAVERICK + ; (define_expand "sge" +@@ -7359,34 +7359,34 @@ + ; "gcc_unreachable ();" + ; ) + +-(define_expand "slt" +- [(set (match_operand:SI 0 "s_register_operand" "") +- (lt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM" +- "operands[1] = arm_gen_compare_reg (LT, arm_compare_op0, arm_compare_op1);" +-) ++;(define_expand "slt" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (lt:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM" ++; "operands[1] = arm_gen_compare_reg (LT, arm_compare_op0, arm_compare_op1);" ++;) + +-(define_expand "sgtu" +- [(set (match_operand:SI 0 "s_register_operand" "") +- (gtu:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM" +- "operands[1] = arm_gen_compare_reg (GTU, arm_compare_op0, arm_compare_op1);" +-) ++;(define_expand "sgtu" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (gtu:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM" ++; "operands[1] = arm_gen_compare_reg (GTU, arm_compare_op0, arm_compare_op1);" ++;) + +-(define_expand "sleu" +- [(set (match_operand:SI 0 "s_register_operand" "") +- (leu:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM" +- "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" +-) ++;(define_expand "sleu" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (leu:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM" ++; "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" ++;) + + ;; broken for cirrus - maybe +-(define_expand "sgeu" +- [(set (match_operand:SI 0 "s_register_operand" "") +- (geu:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM" +- "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);" +-) ++;(define_expand "sgeu" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (geu:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM" ++; "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);" ++;) + + ;;; DO NOT add patterns for SGEU these may not be represented with MAVERICK? + ; (define_expand "sgeu" +@@ -7396,53 +7396,53 @@ + ; "gcc_unreachable ();" + ; ) + +-(define_expand "sltu" +- [(set (match_operand:SI 0 "s_register_operand" "") +- (ltu:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM" +- "operands[1] = arm_gen_compare_reg (LTU, arm_compare_op0, arm_compare_op1);" +-) ++;(define_expand "sltu" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ltu:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM" ++; "operands[1] = arm_gen_compare_reg (LTU, arm_compare_op0, arm_compare_op1);" ++;) + +-(define_expand "sunordered" +- [(set (match_operand:SI 0 "s_register_operand" "") +- (unordered:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" +- "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0, +- arm_compare_op1);" +-) ++;(define_expand "sunordered" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (unordered:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++; "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0, ++; arm_compare_op1);" ++;) + +-(define_expand "sordered" +- [(set (match_operand:SI 0 "s_register_operand" "") +- (ordered:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" +- "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0, +- arm_compare_op1);" +-) ++;(define_expand "sordered" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ordered:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++; "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0, ++; arm_compare_op1);" ++;) + +-(define_expand "sungt" +- [(set (match_operand:SI 0 "s_register_operand" "") +- (ungt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" +- "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, +- arm_compare_op1);" +-) ++;(define_expand "sungt" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ungt:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" ++; "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, ++; arm_compare_op1);" ++;) + +-(define_expand "sunge" +- [(set (match_operand:SI 0 "s_register_operand" "") +- (unge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" +- "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, +- arm_compare_op1);" +-) ++;(define_expand "sunge" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (unge:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" ++; "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, ++; arm_compare_op1);" ++;) + + ; broken for cirrus +-(define_expand "sunlt" +- [(set (match_operand:SI 0 "s_register_operand" "") +- (unlt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" +- "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, +- arm_compare_op1);" +-) ++;(define_expand "sunlt" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (unlt:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++; "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, ++; arm_compare_op1);" ++;) + + ;;; DO NOT add patterns for SUNLT these can't be represented with MAVERICK + ; (define_expand "sunlt" +@@ -7452,13 +7452,13 @@ + ; "gcc_unreachable ();" + ; ) + +-(define_expand "sunle" +- [(set (match_operand:SI 0 "s_register_operand" "") +- (unle:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" +- "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, +- arm_compare_op1);" +-) ++;(define_expand "sunle" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (unle:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" ++; "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, ++; arm_compare_op1);" ++;) + + ;(define_expand "suneq" + ; [(set (match_operand:SI 0 "s_register_operand" "") +@@ -7493,136 +7493,136 @@ + ; "gcc_unreachable ();" + ; ) + +-(define_insn "*mov_scc" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (match_operator:SI 1 "arm_comparison_operator" +- [(match_operand 2 "cc_register" "") (const_int 0)]))] +- "TARGET_ARM" +- "mov%D1\\t%0, #0\;mov%d1\\t%0, #1" +- [(set_attr "conds" "use") +- (set_attr "length" "8")] +-) ++;(define_insn "*mov_scc" ++; [(set (match_operand:SI 0 "s_register_operand" "=r") ++; (match_operator:SI 1 "arm_comparison_operator" ++; [(match_operand 2 "cc_register" "") (const_int 0)]))] ++; "TARGET_ARM" ++; "mov%D1\\t%0, #0\;mov%d1\\t%0, #1" ++; [(set_attr "conds" "use") ++; (set_attr "length" "8")] ++;) + +-(define_insn "*mov_negscc" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (neg:SI (match_operator:SI 1 "arm_comparison_operator" +- [(match_operand 2 "cc_register" "") (const_int 0)])))] +- "TARGET_ARM" +- "mov%D1\\t%0, #0\;mvn%d1\\t%0, #0" +- [(set_attr "conds" "use") +- (set_attr "length" "8")] +-) ++;(define_insn "*mov_negscc" ++; [(set (match_operand:SI 0 "s_register_operand" "=r") ++; (neg:SI (match_operator:SI 1 "arm_comparison_operator" ++; [(match_operand 2 "cc_register" "") (const_int 0)])))] ++; "TARGET_ARM" ++; "mov%D1\\t%0, #0\;mvn%d1\\t%0, #0" ++; [(set_attr "conds" "use") ++; (set_attr "length" "8")] ++;) + +-(define_insn "*mov_notscc" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (not:SI (match_operator:SI 1 "arm_comparison_operator" +- [(match_operand 2 "cc_register" "") (const_int 0)])))] +- "TARGET_ARM" +- "mov%D1\\t%0, #0\;mvn%d1\\t%0, #1" +- [(set_attr "conds" "use") +- (set_attr "length" "8")] +-) ++;(define_insn "*mov_notscc" ++; [(set (match_operand:SI 0 "s_register_operand" "=r") ++; (not:SI (match_operator:SI 1 "arm_comparison_operator" ++; [(match_operand 2 "cc_register" "") (const_int 0)])))] ++; "TARGET_ARM" ++; "mov%D1\\t%0, #0\;mvn%d1\\t%0, #1" ++; [(set_attr "conds" "use") ++; (set_attr "length" "8")] ++;) + + + ;; Conditional move insns + +-(define_expand "movsicc" +- [(set (match_operand:SI 0 "s_register_operand" "") +- (if_then_else:SI (match_operand 1 "arm_comparison_operator" "") +- (match_operand:SI 2 "arm_not_operand" "") +- (match_operand:SI 3 "arm_not_operand" "")))] +- "TARGET_ARM" +- " +- { +- enum rtx_code code = GET_CODE (operands[1]); +- rtx ccreg; +- +- if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) +- FAIL; +- +- ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); +- operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); +- }" +-) +- +-(define_expand "movsfcc" +- [(set (match_operand:SF 0 "s_register_operand" "") +- (if_then_else:SF (match_operand 1 "arm_comparison_operator" "") +- (match_operand:SF 2 "s_register_operand" "") +- (match_operand:SF 3 "nonmemory_operand" "")))] +- "TARGET_ARM" +- " +- { +- enum rtx_code code = GET_CODE (operands[1]); +- rtx ccreg; +- +- if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) +- +- FAIL; +- +- /* When compiling for SOFT_FLOAT, ensure both arms are in registers. +- Otherwise, ensure it is a valid FP add operand */ +- if ((!(TARGET_HARD_FLOAT && TARGET_FPA)) +- || (!arm_float_add_operand (operands[3], SFmode))) +- operands[3] = force_reg (SFmode, operands[3]); +- +- ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); +- operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); +- }" +-) ++;(define_expand "movsicc" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (if_then_else:SI (match_operand 1 "arm_comparison_operator" "") ++; (match_operand:SI 2 "arm_not_operand" "") ++; (match_operand:SI 3 "arm_not_operand" "")))] ++; "TARGET_ARM" ++; " ++; { ++; enum rtx_code code = GET_CODE (operands[1]); ++; rtx ccreg; ++; ++; if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) ++; FAIL; ++; ++; ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); ++; operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); ++; }" ++;) + +-(define_expand "movdfcc" +- [(set (match_operand:DF 0 "s_register_operand" "") +- (if_then_else:DF (match_operand 1 "arm_comparison_operator" "") +- (match_operand:DF 2 "s_register_operand" "") +- (match_operand:DF 3 "arm_float_add_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" +- " +- { +- enum rtx_code code = GET_CODE (operands[1]); +- rtx ccreg; ++;(define_expand "movsfcc" ++; [(set (match_operand:SF 0 "s_register_operand" "") ++; (if_then_else:SF (match_operand 1 "arm_comparison_operator" "") ++; (match_operand:SF 2 "s_register_operand" "") ++; (match_operand:SF 3 "nonmemory_operand" "")))] ++; "TARGET_ARM" ++; " ++; { ++; enum rtx_code code = GET_CODE (operands[1]); ++; rtx ccreg; ++; ++; if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code == GE || code == UNLT || code == ORDERED || code == UNORDERED))) ++; ++; FAIL; ++; ++; /* When compiling for SOFT_FLOAT, ensure both arms are in registers. ++; Otherwise, ensure it is a valid FP add operand */ ++; if ((!(TARGET_HARD_FLOAT && TARGET_FPA)) ++; || (!arm_float_add_operand (operands[3], SFmode))) ++; operands[3] = force_reg (SFmode, operands[3]); ++; ++; ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); ++; operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); ++; }" ++;) + +- if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code==GE || code == UNLT || code == ORDERED || code == UNORDERED))) +- FAIL; ++;(define_expand "movdfcc" ++; [(set (match_operand:DF 0 "s_register_operand" "") ++; (if_then_else:DF (match_operand 1 "arm_comparison_operator" "") ++; (match_operand:DF 2 "s_register_operand" "") ++; (match_operand:DF 3 "arm_float_add_operand" "")))] ++; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" ++; " ++; { ++; enum rtx_code code = GET_CODE (operands[1]); ++; rtx ccreg; ++; ++; if ((code == UNEQ || code == LTGT) || (TARGET_MAVERICK && (code==GE || code == UNLT || code == ORDERED || code == UNORDERED))) ++; FAIL; ++; ++; ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); ++; operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); ++; }" ++;) + +- ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); +- operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); +- }" +-) ++;(define_insn "*movsicc_insn" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r") ++; (if_then_else:SI ++; (match_operator 3 "arm_comparison_operator" ++; [(match_operand 4 "cc_register" "") (const_int 0)]) ++; (match_operand:SI 1 "arm_not_operand" "0,0,rI,K,rI,rI,K,K") ++; (match_operand:SI 2 "arm_not_operand" "rI,K,0,0,rI,K,rI,K")))] ++; "TARGET_ARM" ++; "@ ++; mov%D3\\t%0, %2 ++; mvn%D3\\t%0, #%B2 ++; mov%d3\\t%0, %1 ++; mvn%d3\\t%0, #%B1 ++; mov%d3\\t%0, %1\;mov%D3\\t%0, %2 ++; mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2 ++; mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2 ++; mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2" ++; [(set_attr "length" "4,4,4,4,8,8,8,8") ++; (set_attr "conds" "use")] ++;) + +-(define_insn "*movsicc_insn" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r,r,r") +- (if_then_else:SI +- (match_operator 3 "arm_comparison_operator" +- [(match_operand 4 "cc_register" "") (const_int 0)]) +- (match_operand:SI 1 "arm_not_operand" "0,0,rI,K,rI,rI,K,K") +- (match_operand:SI 2 "arm_not_operand" "rI,K,0,0,rI,K,rI,K")))] +- "TARGET_ARM" +- "@ +- mov%D3\\t%0, %2 +- mvn%D3\\t%0, #%B2 +- mov%d3\\t%0, %1 +- mvn%d3\\t%0, #%B1 +- mov%d3\\t%0, %1\;mov%D3\\t%0, %2 +- mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2 +- mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2 +- mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2" +- [(set_attr "length" "4,4,4,4,8,8,8,8") +- (set_attr "conds" "use")] +-) +- +-(define_insn "*movsfcc_soft_insn" +- [(set (match_operand:SF 0 "s_register_operand" "=r,r") +- (if_then_else:SF (match_operator 3 "arm_comparison_operator" +- [(match_operand 4 "cc_register" "") (const_int 0)]) +- (match_operand:SF 1 "s_register_operand" "0,r") +- (match_operand:SF 2 "s_register_operand" "r,0")))] +- "TARGET_ARM && TARGET_SOFT_FLOAT" +- "@ +- mov%D3\\t%0, %2 +- mov%d3\\t%0, %1" +- [(set_attr "conds" "use")] +-) ++;(define_insn "*movsfcc_soft_insn" ++; [(set (match_operand:SF 0 "s_register_operand" "=r,r") ++; (if_then_else:SF (match_operator 3 "arm_comparison_operator" ++; [(match_operand 4 "cc_register" "") (const_int 0)]) ++; (match_operand:SF 1 "s_register_operand" "0,r") ++; (match_operand:SF 2 "s_register_operand" "r,0")))] ++; "TARGET_ARM && TARGET_SOFT_FLOAT" ++; "@ ++; mov%D3\\t%0, %2 ++; mov%d3\\t%0, %1" ++; [(set_attr "conds" "use")] ++;) + + + ;; Jump and linkage insns +@@ -8003,47 +8003,47 @@ + (set_attr "predicable" "yes")] + ) + +-(define_insn "*cond_return" +- [(set (pc) +- (if_then_else (match_operator 0 "arm_comparison_operator" +- [(match_operand 1 "cc_register" "") (const_int 0)]) +- (return) +- (pc)))] +- "TARGET_ARM && USE_RETURN_INSN (TRUE)" +- "* +- { +- if (arm_ccfsm_state == 2) +- { +- arm_ccfsm_state += 2; +- return \"\"; +- } +- return output_return_instruction (operands[0], TRUE, FALSE); +- }" +- [(set_attr "conds" "use") +- (set_attr "length" "12") +- (set_attr "type" "load1")] +-) ++;(define_insn "*cond_return" ++; [(set (pc) ++; (if_then_else (match_operator 0 "arm_comparison_operator" ++; [(match_operand 1 "cc_register" "") (const_int 0)]) ++; (return) ++; (pc)))] ++; "TARGET_ARM && USE_RETURN_INSN (TRUE)" ++; "* ++; { ++; if (arm_ccfsm_state == 2) ++; { ++; arm_ccfsm_state += 2; ++; return \"\"; ++; } ++; return output_return_instruction (operands[0], TRUE, FALSE); ++; }" ++; [(set_attr "conds" "use") ++; (set_attr "length" "12") ++; (set_attr "type" "load1")] ++;) + +-(define_insn "*cond_return_inverted" +- [(set (pc) +- (if_then_else (match_operator 0 "arm_comparison_operator" +- [(match_operand 1 "cc_register" "") (const_int 0)]) +- (pc) +- (return)))] +- "TARGET_ARM && USE_RETURN_INSN (TRUE)" +- "* +- { +- if (arm_ccfsm_state == 2) +- { +- arm_ccfsm_state += 2; +- return \"\"; +- } +- return output_return_instruction (operands[0], TRUE, TRUE); +- }" +- [(set_attr "conds" "use") +- (set_attr "length" "12") +- (set_attr "type" "load1")] +-) ++;(define_insn "*cond_return_inverted" ++; [(set (pc) ++; (if_then_else (match_operator 0 "arm_comparison_operator" ++; [(match_operand 1 "cc_register" "") (const_int 0)]) ++; (pc) ++; (return)))] ++; "TARGET_ARM && USE_RETURN_INSN (TRUE)" ++; "* ++; { ++; if (arm_ccfsm_state == 2) ++; { ++; arm_ccfsm_state += 2; ++; return \"\"; ++; } ++; return output_return_instruction (operands[0], TRUE, TRUE); ++; }" ++; [(set_attr "conds" "use") ++; (set_attr "length" "12") ++; (set_attr "type" "load1")] ++;) + + ;; Generate a sequence of instructions to determine if the processor is + ;; in 26-bit or 32-bit mode, and return the appropriate return address +@@ -8438,1203 +8438,1203 @@ + + + +-(define_insn "*and_scc" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (and:SI (match_operator:SI 1 "arm_comparison_operator" +- [(match_operand 3 "cc_register" "") (const_int 0)]) +- (match_operand:SI 2 "s_register_operand" "r")))] +- "TARGET_ARM" +- "mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1" +- [(set_attr "conds" "use") +- (set_attr "length" "8")] +-) +- +-(define_insn "*ior_scc" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (ior:SI (match_operator:SI 2 "arm_comparison_operator" +- [(match_operand 3 "cc_register" "") (const_int 0)]) +- (match_operand:SI 1 "s_register_operand" "0,?r")))] +- "TARGET_ARM" +- "@ +- orr%d2\\t%0, %1, #1 +- mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1" +- [(set_attr "conds" "use") +- (set_attr "length" "4,8")] +-) +- +-(define_insn "*compare_scc" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (match_operator:SI 1 "arm_comparison_operator" +- [(match_operand:SI 2 "s_register_operand" "r,r") +- (match_operand:SI 3 "arm_add_operand" "rI,L")])) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "* +- if (operands[3] == const0_rtx) +- { +- if (GET_CODE (operands[1]) == LT) +- return \"mov\\t%0, %2, lsr #31\"; +- +- if (GET_CODE (operands[1]) == GE) +- return \"mvn\\t%0, %2\;mov\\t%0, %0, lsr #31\"; +- +- if (GET_CODE (operands[1]) == EQ) +- return \"rsbs\\t%0, %2, #1\;movcc\\t%0, #0\"; +- } +- +- if (GET_CODE (operands[1]) == NE) +- { +- if (which_alternative == 1) +- return \"adds\\t%0, %2, #%n3\;movne\\t%0, #1\"; +- return \"subs\\t%0, %2, %3\;movne\\t%0, #1\"; +- } +- if (which_alternative == 1) +- output_asm_insn (\"cmn\\t%2, #%n3\", operands); +- else +- output_asm_insn (\"cmp\\t%2, %3\", operands); +- return \"mov%D1\\t%0, #0\;mov%d1\\t%0, #1\"; +- " +- [(set_attr "conds" "clob") +- (set_attr "length" "12")] +-) +- +-(define_insn "*cond_move" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") +- (if_then_else:SI (match_operator 3 "equality_operator" +- [(match_operator 4 "arm_comparison_operator" +- [(match_operand 5 "cc_register" "") (const_int 0)]) +- (const_int 0)]) +- (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI") +- (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))] +- "TARGET_ARM" +- "* +- if (GET_CODE (operands[3]) == NE) +- { +- if (which_alternative != 1) +- output_asm_insn (\"mov%D4\\t%0, %2\", operands); +- if (which_alternative != 0) +- output_asm_insn (\"mov%d4\\t%0, %1\", operands); +- return \"\"; +- } +- if (which_alternative != 0) +- output_asm_insn (\"mov%D4\\t%0, %1\", operands); +- if (which_alternative != 1) +- output_asm_insn (\"mov%d4\\t%0, %2\", operands); +- return \"\"; +- " +- [(set_attr "conds" "use") +- (set_attr "length" "4,4,8")] +-) +- +-(define_insn "*cond_arith" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (match_operator:SI 5 "shiftable_operator" +- [(match_operator:SI 4 "arm_comparison_operator" +- [(match_operand:SI 2 "s_register_operand" "r,r") +- (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]) +- (match_operand:SI 1 "s_register_operand" "0,?r")])) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "* +- if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx) +- return \"%i5\\t%0, %1, %2, lsr #31\"; +- +- output_asm_insn (\"cmp\\t%2, %3\", operands); +- if (GET_CODE (operands[5]) == AND) +- output_asm_insn (\"mov%D4\\t%0, #0\", operands); +- else if (GET_CODE (operands[5]) == MINUS) +- output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands); +- else if (which_alternative != 0) +- output_asm_insn (\"mov%D4\\t%0, %1\", operands); +- return \"%i5%d4\\t%0, %1, #1\"; +- " +- [(set_attr "conds" "clob") +- (set_attr "length" "12")] +-) ++;(define_insn "*and_scc" ++; [(set (match_operand:SI 0 "s_register_operand" "=r") ++; (and:SI (match_operator:SI 1 "arm_comparison_operator" ++; [(match_operand 3 "cc_register" "") (const_int 0)]) ++; (match_operand:SI 2 "s_register_operand" "r")))] ++; "TARGET_ARM" ++; "mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1" ++; [(set_attr "conds" "use") ++; (set_attr "length" "8")] ++;) + +-(define_insn "*cond_sub" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r") +- (match_operator:SI 4 "arm_comparison_operator" +- [(match_operand:SI 2 "s_register_operand" "r,r") +- (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "* +- output_asm_insn (\"cmp\\t%2, %3\", operands); +- if (which_alternative != 0) +- output_asm_insn (\"mov%D4\\t%0, %1\", operands); +- return \"sub%d4\\t%0, %1, #1\"; +- " +- [(set_attr "conds" "clob") +- (set_attr "length" "8,12")] +-) ++;(define_insn "*ior_scc" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++; (ior:SI (match_operator:SI 2 "arm_comparison_operator" ++; [(match_operand 3 "cc_register" "") (const_int 0)]) ++; (match_operand:SI 1 "s_register_operand" "0,?r")))] ++; "TARGET_ARM" ++; "@ ++; orr%d2\\t%0, %1, #1 ++; mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1" ++; [(set_attr "conds" "use") ++; (set_attr "length" "4,8")] ++;) + +-(define_insn "*cmp_ite0" +- [(set (match_operand 6 "dominant_cc_register" "") +- (compare +- (if_then_else:SI +- (match_operator 4 "arm_comparison_operator" +- [(match_operand:SI 0 "s_register_operand" "r,r,r,r") +- (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")]) +- (match_operator:SI 5 "arm_comparison_operator" +- [(match_operand:SI 2 "s_register_operand" "r,r,r,r") +- (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")]) +- (const_int 0)) +- (const_int 0)))] +- "TARGET_ARM" +- "* +- { +- static const char * const opcodes[4][2] = +- { +- {\"cmp\\t%2, %3\;cmp%d5\\t%0, %1\", +- \"cmp\\t%0, %1\;cmp%d4\\t%2, %3\"}, +- {\"cmp\\t%2, %3\;cmn%d5\\t%0, #%n1\", +- \"cmn\\t%0, #%n1\;cmp%d4\\t%2, %3\"}, +- {\"cmn\\t%2, #%n3\;cmp%d5\\t%0, %1\", +- \"cmp\\t%0, %1\;cmn%d4\\t%2, #%n3\"}, +- {\"cmn\\t%2, #%n3\;cmn%d5\\t%0, #%n1\", +- \"cmn\\t%0, #%n1\;cmn%d4\\t%2, #%n3\"} +- }; +- int swap = +- comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4])); ++;(define_insn "*compare_scc" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++; (match_operator:SI 1 "arm_comparison_operator" ++; [(match_operand:SI 2 "s_register_operand" "r,r") ++; (match_operand:SI 3 "arm_add_operand" "rI,L")])) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "* ++; if (operands[3] == const0_rtx) ++; { ++; if (GET_CODE (operands[1]) == LT) ++; return \"mov\\t%0, %2, lsr #31\"; ++; ++; if (GET_CODE (operands[1]) == GE) ++; return \"mvn\\t%0, %2\;mov\\t%0, %0, lsr #31\"; ++; ++; if (GET_CODE (operands[1]) == EQ) ++; return \"rsbs\\t%0, %2, #1\;movcc\\t%0, #0\"; ++; } ++; ++; if (GET_CODE (operands[1]) == NE) ++; { ++; if (which_alternative == 1) ++; return \"adds\\t%0, %2, #%n3\;movne\\t%0, #1\"; ++; return \"subs\\t%0, %2, %3\;movne\\t%0, #1\"; ++; } ++; if (which_alternative == 1) ++; output_asm_insn (\"cmn\\t%2, #%n3\", operands); ++; else ++; output_asm_insn (\"cmp\\t%2, %3\", operands); ++; return \"mov%D1\\t%0, #0\;mov%d1\\t%0, #1\"; ++; " ++; [(set_attr "conds" "clob") ++; (set_attr "length" "12")] ++;) + +- return opcodes[which_alternative][swap]; +- }" +- [(set_attr "conds" "set") +- (set_attr "length" "8")] +-) ++;(define_insn "*cond_move" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") ++; (if_then_else:SI (match_operator 3 "equality_operator" ++; [(match_operator 4 "arm_comparison_operator" ++; [(match_operand 5 "cc_register" "") (const_int 0)]) ++; (const_int 0)]) ++; (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI") ++; (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))] ++; "TARGET_ARM" ++; "* ++; if (GET_CODE (operands[3]) == NE) ++; { ++; if (which_alternative != 1) ++; output_asm_insn (\"mov%D4\\t%0, %2\", operands); ++; if (which_alternative != 0) ++; output_asm_insn (\"mov%d4\\t%0, %1\", operands); ++; return \"\"; ++; } ++; if (which_alternative != 0) ++; output_asm_insn (\"mov%D4\\t%0, %1\", operands); ++; if (which_alternative != 1) ++; output_asm_insn (\"mov%d4\\t%0, %2\", operands); ++; return \"\"; ++; " ++; [(set_attr "conds" "use") ++; (set_attr "length" "4,4,8")] ++;) + +-(define_insn "*cmp_ite1" +- [(set (match_operand 6 "dominant_cc_register" "") +- (compare +- (if_then_else:SI +- (match_operator 4 "arm_comparison_operator" +- [(match_operand:SI 0 "s_register_operand" "r,r,r,r") +- (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")]) +- (match_operator:SI 5 "arm_comparison_operator" +- [(match_operand:SI 2 "s_register_operand" "r,r,r,r") +- (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")]) +- (const_int 1)) +- (const_int 0)))] +- "TARGET_ARM" +- "* +- { +- static const char * const opcodes[4][2] = +- { +- {\"cmp\\t%0, %1\;cmp%d4\\t%2, %3\", +- \"cmp\\t%2, %3\;cmp%D5\\t%0, %1\"}, +- {\"cmn\\t%0, #%n1\;cmp%d4\\t%2, %3\", +- \"cmp\\t%2, %3\;cmn%D5\\t%0, #%n1\"}, +- {\"cmp\\t%0, %1\;cmn%d4\\t%2, #%n3\", +- \"cmn\\t%2, #%n3\;cmp%D5\\t%0, %1\"}, +- {\"cmn\\t%0, #%n1\;cmn%d4\\t%2, #%n3\", +- \"cmn\\t%2, #%n3\;cmn%D5\\t%0, #%n1\"} +- }; +- int swap = +- comparison_dominates_p (GET_CODE (operands[5]), +- reverse_condition (GET_CODE (operands[4]))); ++;(define_insn "*cond_arith" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++; (match_operator:SI 5 "shiftable_operator" ++; [(match_operator:SI 4 "arm_comparison_operator" ++; [(match_operand:SI 2 "s_register_operand" "r,r") ++; (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]) ++; (match_operand:SI 1 "s_register_operand" "0,?r")])) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "* ++; if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx) ++; return \"%i5\\t%0, %1, %2, lsr #31\"; ++; ++; output_asm_insn (\"cmp\\t%2, %3\", operands); ++; if (GET_CODE (operands[5]) == AND) ++; output_asm_insn (\"mov%D4\\t%0, #0\", operands); ++; else if (GET_CODE (operands[5]) == MINUS) ++; output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands); ++; else if (which_alternative != 0) ++; output_asm_insn (\"mov%D4\\t%0, %1\", operands); ++; return \"%i5%d4\\t%0, %1, #1\"; ++; " ++; [(set_attr "conds" "clob") ++; (set_attr "length" "12")] ++;) + +- return opcodes[which_alternative][swap]; +- }" +- [(set_attr "conds" "set") +- (set_attr "length" "8")] +-) ++;(define_insn "*cond_sub" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++; (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r") ++; (match_operator:SI 4 "arm_comparison_operator" ++; [(match_operand:SI 2 "s_register_operand" "r,r") ++; (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "* ++; output_asm_insn (\"cmp\\t%2, %3\", operands); ++; if (which_alternative != 0) ++; output_asm_insn (\"mov%D4\\t%0, %1\", operands); ++; return \"sub%d4\\t%0, %1, #1\"; ++; " ++; [(set_attr "conds" "clob") ++; (set_attr "length" "8,12")] ++;) + +-(define_insn "*cmp_and" +- [(set (match_operand 6 "dominant_cc_register" "") +- (compare +- (and:SI +- (match_operator 4 "arm_comparison_operator" +- [(match_operand:SI 0 "s_register_operand" "r,r,r,r") +- (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")]) +- (match_operator:SI 5 "arm_comparison_operator" +- [(match_operand:SI 2 "s_register_operand" "r,r,r,r") +- (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")])) +- (const_int 0)))] +- "TARGET_ARM" +- "* +- { +- static const char *const opcodes[4][2] = +- { +- {\"cmp\\t%2, %3\;cmp%d5\\t%0, %1\", +- \"cmp\\t%0, %1\;cmp%d4\\t%2, %3\"}, +- {\"cmp\\t%2, %3\;cmn%d5\\t%0, #%n1\", +- \"cmn\\t%0, #%n1\;cmp%d4\\t%2, %3\"}, +- {\"cmn\\t%2, #%n3\;cmp%d5\\t%0, %1\", +- \"cmp\\t%0, %1\;cmn%d4\\t%2, #%n3\"}, +- {\"cmn\\t%2, #%n3\;cmn%d5\\t%0, #%n1\", +- \"cmn\\t%0, #%n1\;cmn%d4\\t%2, #%n3\"} +- }; +- int swap = +- comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4])); ++;(define_insn "*cmp_ite0" ++; [(set (match_operand 6 "dominant_cc_register" "") ++; (compare ++; (if_then_else:SI ++; (match_operator 4 "arm_comparison_operator" ++; [(match_operand:SI 0 "s_register_operand" "r,r,r,r") ++; (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")]) ++; (match_operator:SI 5 "arm_comparison_operator" ++; [(match_operand:SI 2 "s_register_operand" "r,r,r,r") ++; (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")]) ++; (const_int 0)) ++; (const_int 0)))] ++; "TARGET_ARM" ++; "* ++; { ++; static const char * const opcodes[4][2] = ++; { ++; {\"cmp\\t%2, %3\;cmp%d5\\t%0, %1\", ++; \"cmp\\t%0, %1\;cmp%d4\\t%2, %3\"}, ++; {\"cmp\\t%2, %3\;cmn%d5\\t%0, #%n1\", ++; \"cmn\\t%0, #%n1\;cmp%d4\\t%2, %3\"}, ++; {\"cmn\\t%2, #%n3\;cmp%d5\\t%0, %1\", ++; \"cmp\\t%0, %1\;cmn%d4\\t%2, #%n3\"}, ++; {\"cmn\\t%2, #%n3\;cmn%d5\\t%0, #%n1\", ++; \"cmn\\t%0, #%n1\;cmn%d4\\t%2, #%n3\"} ++; }; ++; int swap = ++; comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4])); ++; ++; return opcodes[which_alternative][swap]; ++; }" ++; [(set_attr "conds" "set") ++; (set_attr "length" "8")] ++;) + +- return opcodes[which_alternative][swap]; +- }" +- [(set_attr "conds" "set") +- (set_attr "predicable" "no") +- (set_attr "length" "8")] +-) ++;(define_insn "*cmp_ite1" ++; [(set (match_operand 6 "dominant_cc_register" "") ++; (compare ++; (if_then_else:SI ++; (match_operator 4 "arm_comparison_operator" ++; [(match_operand:SI 0 "s_register_operand" "r,r,r,r") ++; (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")]) ++; (match_operator:SI 5 "arm_comparison_operator" ++; [(match_operand:SI 2 "s_register_operand" "r,r,r,r") ++; (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")]) ++; (const_int 1)) ++; (const_int 0)))] ++; "TARGET_ARM" ++; "* ++; { ++; static const char * const opcodes[4][2] = ++; { ++; {\"cmp\\t%0, %1\;cmp%d4\\t%2, %3\", ++; \"cmp\\t%2, %3\;cmp%D5\\t%0, %1\"}, ++; {\"cmn\\t%0, #%n1\;cmp%d4\\t%2, %3\", ++; \"cmp\\t%2, %3\;cmn%D5\\t%0, #%n1\"}, ++; {\"cmp\\t%0, %1\;cmn%d4\\t%2, #%n3\", ++; \"cmn\\t%2, #%n3\;cmp%D5\\t%0, %1\"}, ++; {\"cmn\\t%0, #%n1\;cmn%d4\\t%2, #%n3\", ++; \"cmn\\t%2, #%n3\;cmn%D5\\t%0, #%n1\"} ++; }; ++; int swap = ++; comparison_dominates_p (GET_CODE (operands[5]), ++; reverse_condition (GET_CODE (operands[4]))); ++; ++; return opcodes[which_alternative][swap]; ++; }" ++; [(set_attr "conds" "set") ++; (set_attr "length" "8")] ++;) + +-(define_insn "*cmp_ior" +- [(set (match_operand 6 "dominant_cc_register" "") +- (compare +- (ior:SI +- (match_operator 4 "arm_comparison_operator" +- [(match_operand:SI 0 "s_register_operand" "r,r,r,r") +- (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")]) +- (match_operator:SI 5 "arm_comparison_operator" +- [(match_operand:SI 2 "s_register_operand" "r,r,r,r") +- (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")])) +- (const_int 0)))] +- "TARGET_ARM" +- "* +-{ +- static const char *const opcodes[4][2] = +- { +- {\"cmp\\t%0, %1\;cmp%D4\\t%2, %3\", +- \"cmp\\t%2, %3\;cmp%D5\\t%0, %1\"}, +- {\"cmn\\t%0, #%n1\;cmp%D4\\t%2, %3\", +- \"cmp\\t%2, %3\;cmn%D5\\t%0, #%n1\"}, +- {\"cmp\\t%0, %1\;cmn%D4\\t%2, #%n3\", +- \"cmn\\t%2, #%n3\;cmp%D5\\t%0, %1\"}, +- {\"cmn\\t%0, #%n1\;cmn%D4\\t%2, #%n3\", +- \"cmn\\t%2, #%n3\;cmn%D5\\t%0, #%n1\"} +- }; +- int swap = +- comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4])); +- +- return opcodes[which_alternative][swap]; +-} +-" +- [(set_attr "conds" "set") +- (set_attr "length" "8")] +-) ++;(define_insn "*cmp_and" ++; [(set (match_operand 6 "dominant_cc_register" "") ++; (compare ++; (and:SI ++; (match_operator 4 "arm_comparison_operator" ++; [(match_operand:SI 0 "s_register_operand" "r,r,r,r") ++; (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")]) ++; (match_operator:SI 5 "arm_comparison_operator" ++; [(match_operand:SI 2 "s_register_operand" "r,r,r,r") ++; (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")])) ++; (const_int 0)))] ++; "TARGET_ARM" ++; "* ++; { ++; static const char *const opcodes[4][2] = ++; { ++; {\"cmp\\t%2, %3\;cmp%d5\\t%0, %1\", ++; \"cmp\\t%0, %1\;cmp%d4\\t%2, %3\"}, ++; {\"cmp\\t%2, %3\;cmn%d5\\t%0, #%n1\", ++; \"cmn\\t%0, #%n1\;cmp%d4\\t%2, %3\"}, ++; {\"cmn\\t%2, #%n3\;cmp%d5\\t%0, %1\", ++; \"cmp\\t%0, %1\;cmn%d4\\t%2, #%n3\"}, ++; {\"cmn\\t%2, #%n3\;cmn%d5\\t%0, #%n1\", ++; \"cmn\\t%0, #%n1\;cmn%d4\\t%2, #%n3\"} ++; }; ++; int swap = ++; comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4])); ++; ++; return opcodes[which_alternative][swap]; ++; }" ++; [(set_attr "conds" "set") ++; (set_attr "predicable" "no") ++; (set_attr "length" "8")] ++;) + +-(define_insn_and_split "*ior_scc_scc" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (ior:SI (match_operator:SI 3 "arm_comparison_operator" +- [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "arm_add_operand" "rIL")]) +- (match_operator:SI 6 "arm_comparison_operator" +- [(match_operand:SI 4 "s_register_operand" "r") +- (match_operand:SI 5 "arm_add_operand" "rIL")]))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM +- && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_OR_Y) +- != CCmode)" +- "#" +- "TARGET_ARM && reload_completed" +- [(set (match_dup 7) +- (compare +- (ior:SI +- (match_op_dup 3 [(match_dup 1) (match_dup 2)]) +- (match_op_dup 6 [(match_dup 4) (match_dup 5)])) +- (const_int 0))) +- (set (match_dup 0) (ne:SI (match_dup 7) (const_int 0)))] +- "operands[7] +- = gen_rtx_REG (arm_select_dominance_cc_mode (operands[3], operands[6], +- DOM_CC_X_OR_Y), +- CC_REGNUM);" +- [(set_attr "conds" "clob") +- (set_attr "length" "16")]) ++;(define_insn "*cmp_ior" ++; [(set (match_operand 6 "dominant_cc_register" "") ++; (compare ++; (ior:SI ++; (match_operator 4 "arm_comparison_operator" ++; [(match_operand:SI 0 "s_register_operand" "r,r,r,r") ++; (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")]) ++; (match_operator:SI 5 "arm_comparison_operator" ++; [(match_operand:SI 2 "s_register_operand" "r,r,r,r") ++; (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")])) ++; (const_int 0)))] ++; "TARGET_ARM" ++; "* ++;{ ++; static const char *const opcodes[4][2] = ++; { ++; {\"cmp\\t%0, %1\;cmp%D4\\t%2, %3\", ++; \"cmp\\t%2, %3\;cmp%D5\\t%0, %1\"}, ++; {\"cmn\\t%0, #%n1\;cmp%D4\\t%2, %3\", ++; \"cmp\\t%2, %3\;cmn%D5\\t%0, #%n1\"}, ++; {\"cmp\\t%0, %1\;cmn%D4\\t%2, #%n3\", ++; \"cmn\\t%2, #%n3\;cmp%D5\\t%0, %1\"}, ++; {\"cmn\\t%0, #%n1\;cmn%D4\\t%2, #%n3\", ++; \"cmn\\t%2, #%n3\;cmn%D5\\t%0, #%n1\"} ++; }; ++; int swap = ++; comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4])); ++; ++; return opcodes[which_alternative][swap]; ++;} ++;" ++; [(set_attr "conds" "set") ++; (set_attr "length" "8")] ++;) + +-; If the above pattern is followed by a CMP insn, then the compare is ++;(define_insn_and_split "*ior_scc_scc" ++; [(set (match_operand:SI 0 "s_register_operand" "=r") ++; (ior:SI (match_operator:SI 3 "arm_comparison_operator" ++; [(match_operand:SI 1 "s_register_operand" "r") ++; (match_operand:SI 2 "arm_add_operand" "rIL")]) ++; (match_operator:SI 6 "arm_comparison_operator" ++; [(match_operand:SI 4 "s_register_operand" "r") ++; (match_operand:SI 5 "arm_add_operand" "rIL")]))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM ++; && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_OR_Y) ++; != CCmode)" ++; "#" ++; "TARGET_ARM && reload_completed" ++; [(set (match_dup 7) ++; (compare ++; (ior:SI ++; (match_op_dup 3 [(match_dup 1) (match_dup 2)]) ++; (match_op_dup 6 [(match_dup 4) (match_dup 5)])) ++; (const_int 0))) ++; (set (match_dup 0) (ne:SI (match_dup 7) (const_int 0)))] ++; "operands[7] ++; = gen_rtx_REG (arm_select_dominance_cc_mode (operands[3], operands[6], ++; DOM_CC_X_OR_Y), ++; CC_REGNUM);" ++; [(set_attr "conds" "clob") ++; (set_attr "length" "16")]) ++; ++;; If the above pattern is followed by a CMP insn, then the compare is + ; redundant, since we can rework the conditional instruction that follows. +-(define_insn_and_split "*ior_scc_scc_cmp" +- [(set (match_operand 0 "dominant_cc_register" "") +- (compare (ior:SI (match_operator:SI 3 "arm_comparison_operator" +- [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "arm_add_operand" "rIL")]) +- (match_operator:SI 6 "arm_comparison_operator" +- [(match_operand:SI 4 "s_register_operand" "r") +- (match_operand:SI 5 "arm_add_operand" "rIL")])) +- (const_int 0))) +- (set (match_operand:SI 7 "s_register_operand" "=r") +- (ior:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)]) +- (match_op_dup 6 [(match_dup 4) (match_dup 5)])))] +- "TARGET_ARM" +- "#" +- "TARGET_ARM && reload_completed" +- [(set (match_dup 0) +- (compare +- (ior:SI +- (match_op_dup 3 [(match_dup 1) (match_dup 2)]) +- (match_op_dup 6 [(match_dup 4) (match_dup 5)])) +- (const_int 0))) +- (set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))] +- "" +- [(set_attr "conds" "set") +- (set_attr "length" "16")]) ++;(define_insn_and_split "*ior_scc_scc_cmp" ++; [(set (match_operand 0 "dominant_cc_register" "") ++; (compare (ior:SI (match_operator:SI 3 "arm_comparison_operator" ++; [(match_operand:SI 1 "s_register_operand" "r") ++; (match_operand:SI 2 "arm_add_operand" "rIL")]) ++; (match_operator:SI 6 "arm_comparison_operator" ++; [(match_operand:SI 4 "s_register_operand" "r") ++; (match_operand:SI 5 "arm_add_operand" "rIL")])) ++; (const_int 0))) ++; (set (match_operand:SI 7 "s_register_operand" "=r") ++; (ior:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)]) ++; (match_op_dup 6 [(match_dup 4) (match_dup 5)])))] ++; "TARGET_ARM" ++; "#" ++; "TARGET_ARM && reload_completed" ++; [(set (match_dup 0) ++; (compare ++; (ior:SI ++; (match_op_dup 3 [(match_dup 1) (match_dup 2)]) ++; (match_op_dup 6 [(match_dup 4) (match_dup 5)])) ++; (const_int 0))) ++; (set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))] ++; "" ++; [(set_attr "conds" "set") ++; (set_attr "length" "16")]) + +-(define_insn_and_split "*and_scc_scc" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (and:SI (match_operator:SI 3 "arm_comparison_operator" +- [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "arm_add_operand" "rIL")]) +- (match_operator:SI 6 "arm_comparison_operator" +- [(match_operand:SI 4 "s_register_operand" "r") +- (match_operand:SI 5 "arm_add_operand" "rIL")]))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM +- && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) +- != CCmode)" +- "#" +- "TARGET_ARM && reload_completed +- && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) +- != CCmode)" +- [(set (match_dup 7) +- (compare +- (and:SI +- (match_op_dup 3 [(match_dup 1) (match_dup 2)]) +- (match_op_dup 6 [(match_dup 4) (match_dup 5)])) +- (const_int 0))) +- (set (match_dup 0) (ne:SI (match_dup 7) (const_int 0)))] +- "operands[7] +- = gen_rtx_REG (arm_select_dominance_cc_mode (operands[3], operands[6], +- DOM_CC_X_AND_Y), +- CC_REGNUM);" +- [(set_attr "conds" "clob") +- (set_attr "length" "16")]) ++;(define_insn_and_split "*and_scc_scc" ++; [(set (match_operand:SI 0 "s_register_operand" "=r") ++; (and:SI (match_operator:SI 3 "arm_comparison_operator" ++; [(match_operand:SI 1 "s_register_operand" "r") ++; (match_operand:SI 2 "arm_add_operand" "rIL")]) ++; (match_operator:SI 6 "arm_comparison_operator" ++; [(match_operand:SI 4 "s_register_operand" "r") ++; (match_operand:SI 5 "arm_add_operand" "rIL")]))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM ++; && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) ++; != CCmode)" ++; "#" ++; "TARGET_ARM && reload_completed ++; && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) ++; != CCmode)" ++; [(set (match_dup 7) ++; (compare ++; (and:SI ++; (match_op_dup 3 [(match_dup 1) (match_dup 2)]) ++; (match_op_dup 6 [(match_dup 4) (match_dup 5)])) ++; (const_int 0))) ++; (set (match_dup 0) (ne:SI (match_dup 7) (const_int 0)))] ++; "operands[7] ++; = gen_rtx_REG (arm_select_dominance_cc_mode (operands[3], operands[6], ++; DOM_CC_X_AND_Y), ++; CC_REGNUM);" ++; [(set_attr "conds" "clob") ++; (set_attr "length" "16")]) + + ; If the above pattern is followed by a CMP insn, then the compare is + ; redundant, since we can rework the conditional instruction that follows. +-(define_insn_and_split "*and_scc_scc_cmp" +- [(set (match_operand 0 "dominant_cc_register" "") +- (compare (and:SI (match_operator:SI 3 "arm_comparison_operator" +- [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "arm_add_operand" "rIL")]) +- (match_operator:SI 6 "arm_comparison_operator" +- [(match_operand:SI 4 "s_register_operand" "r") +- (match_operand:SI 5 "arm_add_operand" "rIL")])) +- (const_int 0))) +- (set (match_operand:SI 7 "s_register_operand" "=r") +- (and:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)]) +- (match_op_dup 6 [(match_dup 4) (match_dup 5)])))] +- "TARGET_ARM" +- "#" +- "TARGET_ARM && reload_completed" +- [(set (match_dup 0) +- (compare +- (and:SI +- (match_op_dup 3 [(match_dup 1) (match_dup 2)]) +- (match_op_dup 6 [(match_dup 4) (match_dup 5)])) +- (const_int 0))) +- (set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))] +- "" +- [(set_attr "conds" "set") +- (set_attr "length" "16")]) +- +-;; If there is no dominance in the comparison, then we can still save an +-;; instruction in the AND case, since we can know that the second compare +-;; need only zero the value if false (if true, then the value is already +-;; correct). +-(define_insn_and_split "*and_scc_scc_nodom" +- [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r") +- (and:SI (match_operator:SI 3 "arm_comparison_operator" +- [(match_operand:SI 1 "s_register_operand" "r,r,0") +- (match_operand:SI 2 "arm_add_operand" "rIL,0,rIL")]) +- (match_operator:SI 6 "arm_comparison_operator" +- [(match_operand:SI 4 "s_register_operand" "r,r,r") +- (match_operand:SI 5 "arm_add_operand" "rIL,rIL,rIL")]))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM +- && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) +- == CCmode)" +- "#" +- "TARGET_ARM && reload_completed" +- [(parallel [(set (match_dup 0) +- (match_op_dup 3 [(match_dup 1) (match_dup 2)])) +- (clobber (reg:CC CC_REGNUM))]) +- (set (match_dup 7) (match_op_dup 8 [(match_dup 4) (match_dup 5)])) +- (set (match_dup 0) +- (if_then_else:SI (match_op_dup 6 [(match_dup 7) (const_int 0)]) +- (match_dup 0) +- (const_int 0)))] +- "operands[7] = gen_rtx_REG (SELECT_CC_MODE (GET_CODE (operands[6]), +- operands[4], operands[5]), +- CC_REGNUM); +- operands[8] = gen_rtx_COMPARE (GET_MODE (operands[7]), operands[4], +- operands[5]);" +- [(set_attr "conds" "clob") +- (set_attr "length" "20")]) +- +-(define_split +- [(set (reg:CC_NOOV CC_REGNUM) +- (compare:CC_NOOV (ior:SI +- (and:SI (match_operand:SI 0 "s_register_operand" "") +- (const_int 1)) +- (match_operator:SI 1 "comparison_operator" +- [(match_operand:SI 2 "s_register_operand" "") +- (match_operand:SI 3 "arm_add_operand" "")])) +- (const_int 0))) +- (clobber (match_operand:SI 4 "s_register_operand" ""))] +- "TARGET_ARM" +- [(set (match_dup 4) +- (ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) +- (match_dup 0))) +- (set (reg:CC_NOOV CC_REGNUM) +- (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1)) +- (const_int 0)))] +- "") +- +-(define_split +- [(set (reg:CC_NOOV CC_REGNUM) +- (compare:CC_NOOV (ior:SI +- (match_operator:SI 1 "comparison_operator" +- [(match_operand:SI 2 "s_register_operand" "") +- (match_operand:SI 3 "arm_add_operand" "")]) +- (and:SI (match_operand:SI 0 "s_register_operand" "") +- (const_int 1))) +- (const_int 0))) +- (clobber (match_operand:SI 4 "s_register_operand" ""))] +- "TARGET_ARM" +- [(set (match_dup 4) +- (ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) +- (match_dup 0))) +- (set (reg:CC_NOOV CC_REGNUM) +- (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1)) +- (const_int 0)))] +- "") +- +-(define_insn "*negscc" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (neg:SI (match_operator 3 "arm_comparison_operator" +- [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "arm_rhs_operand" "rI")]))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "* +- if (GET_CODE (operands[3]) == LT && operands[3] == const0_rtx) +- return \"mov\\t%0, %1, asr #31\"; +- +- if (GET_CODE (operands[3]) == NE) +- return \"subs\\t%0, %1, %2\;mvnne\\t%0, #0\"; +- +- if (GET_CODE (operands[3]) == GT) +- return \"subs\\t%0, %1, %2\;mvnne\\t%0, %0, asr #31\"; +- +- output_asm_insn (\"cmp\\t%1, %2\", operands); +- output_asm_insn (\"mov%D3\\t%0, #0\", operands); +- return \"mvn%d3\\t%0, #0\"; +- " +- [(set_attr "conds" "clob") +- (set_attr "length" "12")] +-) +- +-(define_insn "movcond" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") +- (if_then_else:SI +- (match_operator 5 "arm_comparison_operator" +- [(match_operand:SI 3 "s_register_operand" "r,r,r") +- (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")]) +- (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI") +- (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "* +- if (GET_CODE (operands[5]) == LT +- && (operands[4] == const0_rtx)) +- { +- if (which_alternative != 1 && GET_CODE (operands[1]) == REG) +- { +- if (operands[2] == const0_rtx) +- return \"and\\t%0, %1, %3, asr #31\"; +- return \"ands\\t%0, %1, %3, asr #32\;movcc\\t%0, %2\"; +- } +- else if (which_alternative != 0 && GET_CODE (operands[2]) == REG) +- { +- if (operands[1] == const0_rtx) +- return \"bic\\t%0, %2, %3, asr #31\"; +- return \"bics\\t%0, %2, %3, asr #32\;movcs\\t%0, %1\"; +- } +- /* The only case that falls through to here is when both ops 1 & 2 +- are constants. */ +- } +- +- if (GET_CODE (operands[5]) == GE +- && (operands[4] == const0_rtx)) +- { +- if (which_alternative != 1 && GET_CODE (operands[1]) == REG) +- { +- if (operands[2] == const0_rtx) +- return \"bic\\t%0, %1, %3, asr #31\"; +- return \"bics\\t%0, %1, %3, asr #32\;movcs\\t%0, %2\"; +- } +- else if (which_alternative != 0 && GET_CODE (operands[2]) == REG) +- { +- if (operands[1] == const0_rtx) +- return \"and\\t%0, %2, %3, asr #31\"; +- return \"ands\\t%0, %2, %3, asr #32\;movcc\\t%0, %1\"; +- } +- /* The only case that falls through to here is when both ops 1 & 2 +- are constants. */ +- } +- if (GET_CODE (operands[4]) == CONST_INT +- && !const_ok_for_arm (INTVAL (operands[4]))) +- output_asm_insn (\"cmn\\t%3, #%n4\", operands); +- else +- output_asm_insn (\"cmp\\t%3, %4\", operands); +- if (which_alternative != 0) +- output_asm_insn (\"mov%d5\\t%0, %1\", operands); +- if (which_alternative != 1) +- output_asm_insn (\"mov%D5\\t%0, %2\", operands); +- return \"\"; +- " +- [(set_attr "conds" "clob") +- (set_attr "length" "8,8,12")] +-) +- +-(define_insn "*ifcompare_plus_move" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (if_then_else:SI (match_operator 6 "arm_comparison_operator" +- [(match_operand:SI 4 "s_register_operand" "r,r") +- (match_operand:SI 5 "arm_add_operand" "rIL,rIL")]) +- (plus:SI +- (match_operand:SI 2 "s_register_operand" "r,r") +- (match_operand:SI 3 "arm_add_operand" "rIL,rIL")) +- (match_operand:SI 1 "arm_rhs_operand" "0,?rI"))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "#" +- [(set_attr "conds" "clob") +- (set_attr "length" "8,12")] +-) +- +-(define_insn "*if_plus_move" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") +- (if_then_else:SI +- (match_operator 4 "arm_comparison_operator" +- [(match_operand 5 "cc_register" "") (const_int 0)]) +- (plus:SI +- (match_operand:SI 2 "s_register_operand" "r,r,r,r") +- (match_operand:SI 3 "arm_add_operand" "rI,L,rI,L")) +- (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI")))] +- "TARGET_ARM" +- "@ +- add%d4\\t%0, %2, %3 +- sub%d4\\t%0, %2, #%n3 +- add%d4\\t%0, %2, %3\;mov%D4\\t%0, %1 +- sub%d4\\t%0, %2, #%n3\;mov%D4\\t%0, %1" +- [(set_attr "conds" "use") +- (set_attr "length" "4,4,8,8") +- (set_attr "type" "*,*,*,*")] +-) +- +-(define_insn "*ifcompare_move_plus" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (if_then_else:SI (match_operator 6 "arm_comparison_operator" +- [(match_operand:SI 4 "s_register_operand" "r,r") +- (match_operand:SI 5 "arm_add_operand" "rIL,rIL")]) +- (match_operand:SI 1 "arm_rhs_operand" "0,?rI") +- (plus:SI +- (match_operand:SI 2 "s_register_operand" "r,r") +- (match_operand:SI 3 "arm_add_operand" "rIL,rIL")))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "#" +- [(set_attr "conds" "clob") +- (set_attr "length" "8,12")] +-) +- +-(define_insn "*if_move_plus" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") +- (if_then_else:SI +- (match_operator 4 "arm_comparison_operator" +- [(match_operand 5 "cc_register" "") (const_int 0)]) +- (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI") +- (plus:SI +- (match_operand:SI 2 "s_register_operand" "r,r,r,r") +- (match_operand:SI 3 "arm_add_operand" "rI,L,rI,L"))))] +- "TARGET_ARM" +- "@ +- add%D4\\t%0, %2, %3 +- sub%D4\\t%0, %2, #%n3 +- add%D4\\t%0, %2, %3\;mov%d4\\t%0, %1 +- sub%D4\\t%0, %2, #%n3\;mov%d4\\t%0, %1" +- [(set_attr "conds" "use") +- (set_attr "length" "4,4,8,8") +- (set_attr "type" "*,*,*,*")] +-) +- +-(define_insn "*ifcompare_arith_arith" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (if_then_else:SI (match_operator 9 "arm_comparison_operator" +- [(match_operand:SI 5 "s_register_operand" "r") +- (match_operand:SI 6 "arm_add_operand" "rIL")]) +- (match_operator:SI 8 "shiftable_operator" +- [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "arm_rhs_operand" "rI")]) +- (match_operator:SI 7 "shiftable_operator" +- [(match_operand:SI 3 "s_register_operand" "r") +- (match_operand:SI 4 "arm_rhs_operand" "rI")]))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "#" +- [(set_attr "conds" "clob") +- (set_attr "length" "12")] +-) +- +-(define_insn "*if_arith_arith" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (if_then_else:SI (match_operator 5 "arm_comparison_operator" +- [(match_operand 8 "cc_register" "") (const_int 0)]) +- (match_operator:SI 6 "shiftable_operator" +- [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "arm_rhs_operand" "rI")]) +- (match_operator:SI 7 "shiftable_operator" +- [(match_operand:SI 3 "s_register_operand" "r") +- (match_operand:SI 4 "arm_rhs_operand" "rI")])))] +- "TARGET_ARM" +- "%I6%d5\\t%0, %1, %2\;%I7%D5\\t%0, %3, %4" +- [(set_attr "conds" "use") +- (set_attr "length" "8")] +-) +- +-(define_insn "*ifcompare_arith_move" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (if_then_else:SI (match_operator 6 "arm_comparison_operator" +- [(match_operand:SI 2 "s_register_operand" "r,r") +- (match_operand:SI 3 "arm_add_operand" "rIL,rIL")]) +- (match_operator:SI 7 "shiftable_operator" +- [(match_operand:SI 4 "s_register_operand" "r,r") +- (match_operand:SI 5 "arm_rhs_operand" "rI,rI")]) +- (match_operand:SI 1 "arm_rhs_operand" "0,?rI"))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "* +- /* If we have an operation where (op x 0) is the identity operation and +- the conditional operator is LT or GE and we are comparing against zero and +- everything is in registers then we can do this in two instructions. */ +- if (operands[3] == const0_rtx +- && GET_CODE (operands[7]) != AND +- && GET_CODE (operands[5]) == REG +- && GET_CODE (operands[1]) == REG +- && REGNO (operands[1]) == REGNO (operands[4]) +- && REGNO (operands[4]) != REGNO (operands[0])) +- { +- if (GET_CODE (operands[6]) == LT) +- return \"and\\t%0, %5, %2, asr #31\;%I7\\t%0, %4, %0\"; +- else if (GET_CODE (operands[6]) == GE) +- return \"bic\\t%0, %5, %2, asr #31\;%I7\\t%0, %4, %0\"; +- } +- if (GET_CODE (operands[3]) == CONST_INT +- && !const_ok_for_arm (INTVAL (operands[3]))) +- output_asm_insn (\"cmn\\t%2, #%n3\", operands); +- else +- output_asm_insn (\"cmp\\t%2, %3\", operands); +- output_asm_insn (\"%I7%d6\\t%0, %4, %5\", operands); +- if (which_alternative != 0) +- return \"mov%D6\\t%0, %1\"; +- return \"\"; +- " +- [(set_attr "conds" "clob") +- (set_attr "length" "8,12")] +-) +- +-(define_insn "*if_arith_move" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (if_then_else:SI (match_operator 4 "arm_comparison_operator" +- [(match_operand 6 "cc_register" "") (const_int 0)]) +- (match_operator:SI 5 "shiftable_operator" +- [(match_operand:SI 2 "s_register_operand" "r,r") +- (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]) +- (match_operand:SI 1 "arm_rhs_operand" "0,?rI")))] +- "TARGET_ARM" +- "@ +- %I5%d4\\t%0, %2, %3 +- %I5%d4\\t%0, %2, %3\;mov%D4\\t%0, %1" +- [(set_attr "conds" "use") +- (set_attr "length" "4,8") +- (set_attr "type" "*,*")] +-) +- +-(define_insn "*ifcompare_move_arith" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (if_then_else:SI (match_operator 6 "arm_comparison_operator" +- [(match_operand:SI 4 "s_register_operand" "r,r") +- (match_operand:SI 5 "arm_add_operand" "rIL,rIL")]) +- (match_operand:SI 1 "arm_rhs_operand" "0,?rI") +- (match_operator:SI 7 "shiftable_operator" +- [(match_operand:SI 2 "s_register_operand" "r,r") +- (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "* +- /* If we have an operation where (op x 0) is the identity operation and +- the conditional operator is LT or GE and we are comparing against zero and +- everything is in registers then we can do this in two instructions */ +- if (operands[5] == const0_rtx +- && GET_CODE (operands[7]) != AND +- && GET_CODE (operands[3]) == REG +- && GET_CODE (operands[1]) == REG +- && REGNO (operands[1]) == REGNO (operands[2]) +- && REGNO (operands[2]) != REGNO (operands[0])) +- { +- if (GET_CODE (operands[6]) == GE) +- return \"and\\t%0, %3, %4, asr #31\;%I7\\t%0, %2, %0\"; +- else if (GET_CODE (operands[6]) == LT) +- return \"bic\\t%0, %3, %4, asr #31\;%I7\\t%0, %2, %0\"; +- } +- +- if (GET_CODE (operands[5]) == CONST_INT +- && !const_ok_for_arm (INTVAL (operands[5]))) +- output_asm_insn (\"cmn\\t%4, #%n5\", operands); +- else +- output_asm_insn (\"cmp\\t%4, %5\", operands); +- +- if (which_alternative != 0) +- output_asm_insn (\"mov%d6\\t%0, %1\", operands); +- return \"%I7%D6\\t%0, %2, %3\"; +- " +- [(set_attr "conds" "clob") +- (set_attr "length" "8,12")] +-) ++;(define_insn_and_split "*and_scc_scc_cmp" ++; [(set (match_operand 0 "dominant_cc_register" "") ++; (compare (and:SI (match_operator:SI 3 "arm_comparison_operator" ++; [(match_operand:SI 1 "s_register_operand" "r") ++; (match_operand:SI 2 "arm_add_operand" "rIL")]) ++; (match_operator:SI 6 "arm_comparison_operator" ++; [(match_operand:SI 4 "s_register_operand" "r") ++; (match_operand:SI 5 "arm_add_operand" "rIL")])) ++; (const_int 0))) ++; (set (match_operand:SI 7 "s_register_operand" "=r") ++; (and:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)]) ++; (match_op_dup 6 [(match_dup 4) (match_dup 5)])))] ++; "TARGET_ARM" ++; "#" ++; "TARGET_ARM && reload_completed" ++; [(set (match_dup 0) ++; (compare ++; (and:SI ++; (match_op_dup 3 [(match_dup 1) (match_dup 2)]) ++; (match_op_dup 6 [(match_dup 4) (match_dup 5)])) ++; (const_int 0))) ++; (set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))] ++; "" ++; [(set_attr "conds" "set") ++; (set_attr "length" "16")]) ++; ++;;; If there is no dominance in the comparison, then we can still save an ++;;; instruction in the AND case, since we can know that the second compare ++;;; need only zero the value if false (if true, then the value is already ++;;; correct). ++;(define_insn_and_split "*and_scc_scc_nodom" ++; [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r") ++; (and:SI (match_operator:SI 3 "arm_comparison_operator" ++; [(match_operand:SI 1 "s_register_operand" "r,r,0") ++; (match_operand:SI 2 "arm_add_operand" "rIL,0,rIL")]) ++; (match_operator:SI 6 "arm_comparison_operator" ++; [(match_operand:SI 4 "s_register_operand" "r,r,r") ++; (match_operand:SI 5 "arm_add_operand" "rIL,rIL,rIL")]))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM ++; ;&& (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) ++; == CCmode)" ++; "#" ++; "TARGET_ARM && reload_completed" ++; [(parallel [(set (match_dup 0) ++; (match_op_dup 3 [(match_dup 1) (match_dup 2)])) ++; (clobber (reg:CC CC_REGNUM))]) ++; (set (match_dup 7) (match_op_dup 8 [(match_dup 4) (match_dup 5)])) ++; (set (match_dup 0) ++; (if_then_else:SI (match_op_dup 6 [(match_dup 7) (const_int 0)]) ++; (match_dup 0) ++; (const_int 0)))] ++; "operands[7] = gen_rtx_REG (SELECT_CC_MODE (GET_CODE (operands[6]), ++; operands[4], operands[5]), ++; CC_REGNUM); ++; operands[8] = gen_rtx_COMPARE (GET_MODE (operands[7]), operands[4], ++; operands[5]);" ++; [(set_attr "conds" "clob") ++; (set_attr "length" "20")]) ++ ++;(define_split ++; [(set (reg:CC_NOOV CC_REGNUM) ++; (compare:CC_NOOV (ior:SI ++; (and:SI (match_operand:SI 0 "s_register_operand" "") ++; (const_int 1)) ++; (match_operator:SI 1 "comparison_operator" ++; [(match_operand:SI 2 "s_register_operand" "") ++; (match_operand:SI 3 "arm_add_operand" "")])) ++; (const_int 0))) ++; (clobber (match_operand:SI 4 "s_register_operand" ""))] ++; "TARGET_ARM" ++; [(set (match_dup 4) ++; (ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) ++; (match_dup 0))) ++; (set (reg:CC_NOOV CC_REGNUM) ++; (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1)) ++; (const_int 0)))] ++; "") ++ ++;(define_split ++; [(set (reg:CC_NOOV CC_REGNUM) ++; (compare:CC_NOOV (ior:SI ++; (match_operator:SI 1 "comparison_operator" ++; [(match_operand:SI 2 "s_register_operand" "") ++; (match_operand:SI 3 "arm_add_operand" "")]) ++; (and:SI (match_operand:SI 0 "s_register_operand" "") ++; (const_int 1))) ++; (const_int 0))) ++; (clobber (match_operand:SI 4 "s_register_operand" ""))] ++; "TARGET_ARM" ++; [(set (match_dup 4) ++; (ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) ++; (match_dup 0))) ++; (set (reg:CC_NOOV CC_REGNUM) ++; (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1)) ++; (const_int 0)))] ++; "") ++ ++;(define_insn "*negscc" ++; [(set (match_operand:SI 0 "s_register_operand" "=r") ++; (neg:SI (match_operator 3 "arm_comparison_operator" ++; [(match_operand:SI 1 "s_register_operand" "r") ++; (match_operand:SI 2 "arm_rhs_operand" "rI")]))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "* ++; if (GET_CODE (operands[3]) == LT && operands[3] == const0_rtx) ++; return \"mov\\t%0, %1, asr #31\"; ++; ++; if (GET_CODE (operands[3]) == NE) ++; return \"subs\\t%0, %1, %2\;mvnne\\t%0, #0\"; ++; ++; if (GET_CODE (operands[3]) == GT) ++; return \"subs\\t%0, %1, %2\;mvnne\\t%0, %0, asr #31\"; ++; ++; output_asm_insn (\"cmp\\t%1, %2\", operands); ++; output_asm_insn (\"mov%D3\\t%0, #0\", operands); ++; return \"mvn%d3\\t%0, #0\"; ++; " ++; [(set_attr "conds" "clob") ++; (set_attr "length" "12")] ++;) + +-(define_insn "*if_move_arith" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (if_then_else:SI +- (match_operator 4 "arm_comparison_operator" +- [(match_operand 6 "cc_register" "") (const_int 0)]) +- (match_operand:SI 1 "arm_rhs_operand" "0,?rI") +- (match_operator:SI 5 "shiftable_operator" +- [(match_operand:SI 2 "s_register_operand" "r,r") +- (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))] +- "TARGET_ARM" +- "@ +- %I5%D4\\t%0, %2, %3 +- %I5%D4\\t%0, %2, %3\;mov%d4\\t%0, %1" +- [(set_attr "conds" "use") +- (set_attr "length" "4,8") +- (set_attr "type" "*,*")] +-) ++;(define_insn "movcond" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") ++; (if_then_else:SI ++; (match_operator 5 "arm_comparison_operator" ++; [(match_operand:SI 3 "s_register_operand" "r,r,r") ++; (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")]) ++; (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI") ++; (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "* ++; if (GET_CODE (operands[5]) == LT ++; && (operands[4] == const0_rtx)) ++; { ++; if (which_alternative != 1 && GET_CODE (operands[1]) == REG) ++; { ++; if (operands[2] == const0_rtx) ++; return \"and\\t%0, %1, %3, asr #31\"; ++; return \"ands\\t%0, %1, %3, asr #32\;movcc\\t%0, %2\"; ++; } ++; else if (which_alternative != 0 && GET_CODE (operands[2]) == REG) ++; { ++; if (operands[1] == const0_rtx) ++; return \"bic\\t%0, %2, %3, asr #31\"; ++; return \"bics\\t%0, %2, %3, asr #32\;movcs\\t%0, %1\"; ++; } ++; /* The only case that falls through to here is when both ops 1 & 2 ++; are constants. */ ++; } ++; ++; if (GET_CODE (operands[5]) == GE ++; && (operands[4] == const0_rtx)) ++; { ++; if (which_alternative != 1 && GET_CODE (operands[1]) == REG) ++; { ++; if (operands[2] == const0_rtx) ++; return \"bic\\t%0, %1, %3, asr #31\"; ++; return \"bics\\t%0, %1, %3, asr #32\;movcs\\t%0, %2\"; ++; } ++; else if (which_alternative != 0 && GET_CODE (operands[2]) == REG) ++; { ++; if (operands[1] == const0_rtx) ++; return \"and\\t%0, %2, %3, asr #31\"; ++; return \"ands\\t%0, %2, %3, asr #32\;movcc\\t%0, %1\"; ++; } ++; /* The only case that falls through to here is when both ops 1 & 2 ++; are constants. */ ++; } ++; if (GET_CODE (operands[4]) == CONST_INT ++; && !const_ok_for_arm (INTVAL (operands[4]))) ++; output_asm_insn (\"cmn\\t%3, #%n4\", operands); ++; else ++; output_asm_insn (\"cmp\\t%3, %4\", operands); ++; if (which_alternative != 0) ++; output_asm_insn (\"mov%d5\\t%0, %1\", operands); ++; if (which_alternative != 1) ++; output_asm_insn (\"mov%D5\\t%0, %2\", operands); ++; return \"\"; ++; " ++; [(set_attr "conds" "clob") ++; (set_attr "length" "8,8,12")] ++;) + +-(define_insn "*ifcompare_move_not" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (if_then_else:SI +- (match_operator 5 "arm_comparison_operator" +- [(match_operand:SI 3 "s_register_operand" "r,r") +- (match_operand:SI 4 "arm_add_operand" "rIL,rIL")]) +- (match_operand:SI 1 "arm_not_operand" "0,?rIK") +- (not:SI +- (match_operand:SI 2 "s_register_operand" "r,r")))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "#" +- [(set_attr "conds" "clob") +- (set_attr "length" "8,12")] +-) ++;(define_insn "*ifcompare_plus_move" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++; (if_then_else:SI (match_operator 6 "arm_comparison_operator" ++; [(match_operand:SI 4 "s_register_operand" "r,r") ++; (match_operand:SI 5 "arm_add_operand" "rIL,rIL")]) ++; (plus:SI ++; (match_operand:SI 2 "s_register_operand" "r,r") ++; (match_operand:SI 3 "arm_add_operand" "rIL,rIL")) ++; (match_operand:SI 1 "arm_rhs_operand" "0,?rI"))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "#" ++; [(set_attr "conds" "clob") ++; (set_attr "length" "8,12")] ++;) + +-(define_insn "*if_move_not" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") +- (if_then_else:SI +- (match_operator 4 "arm_comparison_operator" +- [(match_operand 3 "cc_register" "") (const_int 0)]) +- (match_operand:SI 1 "arm_not_operand" "0,?rI,K") +- (not:SI (match_operand:SI 2 "s_register_operand" "r,r,r"))))] +- "TARGET_ARM" +- "@ +- mvn%D4\\t%0, %2 +- mov%d4\\t%0, %1\;mvn%D4\\t%0, %2 +- mvn%d4\\t%0, #%B1\;mvn%D4\\t%0, %2" +- [(set_attr "conds" "use") +- (set_attr "length" "4,8,8")] +-) ++;(define_insn "*if_plus_move" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") ++; (if_then_else:SI ++; (match_operator 4 "arm_comparison_operator" ++; [(match_operand 5 "cc_register" "") (const_int 0)]) ++; (plus:SI ++; (match_operand:SI 2 "s_register_operand" "r,r,r,r") ++; (match_operand:SI 3 "arm_add_operand" "rI,L,rI,L")) ++; (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI")))] ++; "TARGET_ARM" ++; "@ ++; add%d4\\t%0, %2, %3 ++; sub%d4\\t%0, %2, #%n3 ++; add%d4\\t%0, %2, %3\;mov%D4\\t%0, %1 ++; sub%d4\\t%0, %2, #%n3\;mov%D4\\t%0, %1" ++; [(set_attr "conds" "use") ++; (set_attr "length" "4,4,8,8") ++; (set_attr "type" "*,*,*,*")] ++;) + +-(define_insn "*ifcompare_not_move" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (if_then_else:SI +- (match_operator 5 "arm_comparison_operator" +- [(match_operand:SI 3 "s_register_operand" "r,r") +- (match_operand:SI 4 "arm_add_operand" "rIL,rIL")]) +- (not:SI +- (match_operand:SI 2 "s_register_operand" "r,r")) +- (match_operand:SI 1 "arm_not_operand" "0,?rIK"))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "#" +- [(set_attr "conds" "clob") +- (set_attr "length" "8,12")] +-) ++;(define_insn "*ifcompare_move_plus" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++; (if_then_else:SI (match_operator 6 "arm_comparison_operator" ++; [(match_operand:SI 4 "s_register_operand" "r,r") ++; (match_operand:SI 5 "arm_add_operand" "rIL,rIL")]) ++; (match_operand:SI 1 "arm_rhs_operand" "0,?rI") ++; (plus:SI ++; (match_operand:SI 2 "s_register_operand" "r,r") ++; (match_operand:SI 3 "arm_add_operand" "rIL,rIL")))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "#" ++; [(set_attr "conds" "clob") ++; (set_attr "length" "8,12")] ++;) + +-(define_insn "*if_not_move" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") +- (if_then_else:SI +- (match_operator 4 "arm_comparison_operator" +- [(match_operand 3 "cc_register" "") (const_int 0)]) +- (not:SI (match_operand:SI 2 "s_register_operand" "r,r,r")) +- (match_operand:SI 1 "arm_not_operand" "0,?rI,K")))] +- "TARGET_ARM" +- "@ +- mvn%d4\\t%0, %2 +- mov%D4\\t%0, %1\;mvn%d4\\t%0, %2 +- mvn%D4\\t%0, #%B1\;mvn%d4\\t%0, %2" +- [(set_attr "conds" "use") +- (set_attr "length" "4,8,8")] +-) ++;(define_insn "*if_move_plus" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r") ++; (if_then_else:SI ++; (match_operator 4 "arm_comparison_operator" ++; [(match_operand 5 "cc_register" "") (const_int 0)]) ++; (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI") ++; (plus:SI ++; (match_operand:SI 2 "s_register_operand" "r,r,r,r") ++; (match_operand:SI 3 "arm_add_operand" "rI,L,rI,L"))))] ++; "TARGET_ARM" ++; "@ ++; add%D4\\t%0, %2, %3 ++; sub%D4\\t%0, %2, #%n3 ++; add%D4\\t%0, %2, %3\;mov%d4\\t%0, %1 ++; sub%D4\\t%0, %2, #%n3\;mov%d4\\t%0, %1" ++; [(set_attr "conds" "use") ++; (set_attr "length" "4,4,8,8") ++; (set_attr "type" "*,*,*,*")] ++;) + +-(define_insn "*ifcompare_shift_move" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (if_then_else:SI +- (match_operator 6 "arm_comparison_operator" +- [(match_operand:SI 4 "s_register_operand" "r,r") +- (match_operand:SI 5 "arm_add_operand" "rIL,rIL")]) +- (match_operator:SI 7 "shift_operator" +- [(match_operand:SI 2 "s_register_operand" "r,r") +- (match_operand:SI 3 "arm_rhs_operand" "rM,rM")]) +- (match_operand:SI 1 "arm_not_operand" "0,?rIK"))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "#" +- [(set_attr "conds" "clob") +- (set_attr "length" "8,12")] +-) ++;(define_insn "*ifcompare_arith_arith" ++; [(set (match_operand:SI 0 "s_register_operand" "=r") ++; (if_then_else:SI (match_operator 9 "arm_comparison_operator" ++; [(match_operand:SI 5 "s_register_operand" "r") ++; (match_operand:SI 6 "arm_add_operand" "rIL")]) ++; (match_operator:SI 8 "shiftable_operator" ++; [(match_operand:SI 1 "s_register_operand" "r") ++; (match_operand:SI 2 "arm_rhs_operand" "rI")]) ++; (match_operator:SI 7 "shiftable_operator" ++; [(match_operand:SI 3 "s_register_operand" "r") ++; (match_operand:SI 4 "arm_rhs_operand" "rI")]))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "#" ++; [(set_attr "conds" "clob") ++; (set_attr "length" "12")] ++;) + +-(define_insn "*if_shift_move" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") +- (if_then_else:SI +- (match_operator 5 "arm_comparison_operator" +- [(match_operand 6 "cc_register" "") (const_int 0)]) +- (match_operator:SI 4 "shift_operator" +- [(match_operand:SI 2 "s_register_operand" "r,r,r") +- (match_operand:SI 3 "arm_rhs_operand" "rM,rM,rM")]) +- (match_operand:SI 1 "arm_not_operand" "0,?rI,K")))] +- "TARGET_ARM" +- "@ +- mov%d5\\t%0, %2%S4 +- mov%D5\\t%0, %1\;mov%d5\\t%0, %2%S4 +- mvn%D5\\t%0, #%B1\;mov%d5\\t%0, %2%S4" +- [(set_attr "conds" "use") +- (set_attr "shift" "2") +- (set_attr "length" "4,8,8") +- (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") +- (const_string "alu_shift") +- (const_string "alu_shift_reg")))] +-) ++;(define_insn "*if_arith_arith" ++; [(set (match_operand:SI 0 "s_register_operand" "=r") ++; (if_then_else:SI (match_operator 5 "arm_comparison_operator" ++; [(match_operand 8 "cc_register" "") (const_int 0)]) ++; (match_operator:SI 6 "shiftable_operator" ++; [(match_operand:SI 1 "s_register_operand" "r") ++; (match_operand:SI 2 "arm_rhs_operand" "rI")]) ++; (match_operator:SI 7 "shiftable_operator" ++; [(match_operand:SI 3 "s_register_operand" "r") ++; (match_operand:SI 4 "arm_rhs_operand" "rI")])))] ++; "TARGET_ARM" ++; "%I6%d5\\t%0, %1, %2\;%I7%D5\\t%0, %3, %4" ++; [(set_attr "conds" "use") ++; (set_attr "length" "8")] ++;) + +-(define_insn "*ifcompare_move_shift" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (if_then_else:SI +- (match_operator 6 "arm_comparison_operator" +- [(match_operand:SI 4 "s_register_operand" "r,r") +- (match_operand:SI 5 "arm_add_operand" "rIL,rIL")]) +- (match_operand:SI 1 "arm_not_operand" "0,?rIK") +- (match_operator:SI 7 "shift_operator" +- [(match_operand:SI 2 "s_register_operand" "r,r") +- (match_operand:SI 3 "arm_rhs_operand" "rM,rM")]))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "#" +- [(set_attr "conds" "clob") +- (set_attr "length" "8,12")] +-) ++;(define_insn "*ifcompare_arith_move" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++; (if_then_else:SI (match_operator 6 "arm_comparison_operator" ++; [(match_operand:SI 2 "s_register_operand" "r,r") ++; (match_operand:SI 3 "arm_add_operand" "rIL,rIL")]) ++; (match_operator:SI 7 "shiftable_operator" ++; [(match_operand:SI 4 "s_register_operand" "r,r") ++; (match_operand:SI 5 "arm_rhs_operand" "rI,rI")]) ++; (match_operand:SI 1 "arm_rhs_operand" "0,?rI"))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "* ++; /* If we have an operation where (op x 0) is the identity operation and ++; the conditional operator is LT or GE and we are comparing against zero and ++; everything is in registers then we can do this in two instructions. */ ++; if (operands[3] == const0_rtx ++; && GET_CODE (operands[7]) != AND ++; && GET_CODE (operands[5]) == REG ++; && GET_CODE (operands[1]) == REG ++; && REGNO (operands[1]) == REGNO (operands[4]) ++; && REGNO (operands[4]) != REGNO (operands[0])) ++; { ++; if (GET_CODE (operands[6]) == LT) ++; return \"and\\t%0, %5, %2, asr #31\;%I7\\t%0, %4, %0\"; ++; else if (GET_CODE (operands[6]) == GE) ++; return \"bic\\t%0, %5, %2, asr #31\;%I7\\t%0, %4, %0\"; ++; } ++; if (GET_CODE (operands[3]) == CONST_INT ++; && !const_ok_for_arm (INTVAL (operands[3]))) ++; output_asm_insn (\"cmn\\t%2, #%n3\", operands); ++; else ++; output_asm_insn (\"cmp\\t%2, %3\", operands); ++; output_asm_insn (\"%I7%d6\\t%0, %4, %5\", operands); ++; if (which_alternative != 0) ++; return \"mov%D6\\t%0, %1\"; ++; return \"\"; ++; " ++; [(set_attr "conds" "clob") ++; (set_attr "length" "8,12")] ++;) + +-(define_insn "*if_move_shift" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") +- (if_then_else:SI +- (match_operator 5 "arm_comparison_operator" +- [(match_operand 6 "cc_register" "") (const_int 0)]) +- (match_operand:SI 1 "arm_not_operand" "0,?rI,K") +- (match_operator:SI 4 "shift_operator" +- [(match_operand:SI 2 "s_register_operand" "r,r,r") +- (match_operand:SI 3 "arm_rhs_operand" "rM,rM,rM")])))] +- "TARGET_ARM" +- "@ +- mov%D5\\t%0, %2%S4 +- mov%d5\\t%0, %1\;mov%D5\\t%0, %2%S4 +- mvn%d5\\t%0, #%B1\;mov%D5\\t%0, %2%S4" +- [(set_attr "conds" "use") +- (set_attr "shift" "2") +- (set_attr "length" "4,8,8") +- (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") +- (const_string "alu_shift") +- (const_string "alu_shift_reg")))] +-) ++;(define_insn "*if_arith_move" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++; (if_then_else:SI (match_operator 4 "arm_comparison_operator" ++; [(match_operand 6 "cc_register" "") (const_int 0)]) ++; (match_operator:SI 5 "shiftable_operator" ++; [(match_operand:SI 2 "s_register_operand" "r,r") ++; (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]) ++; (match_operand:SI 1 "arm_rhs_operand" "0,?rI")))] ++; "TARGET_ARM" ++; "@ ++; %I5%d4\\t%0, %2, %3 ++; %I5%d4\\t%0, %2, %3\;mov%D4\\t%0, %1" ++; [(set_attr "conds" "use") ++; (set_attr "length" "4,8") ++; (set_attr "type" "*,*")] ++;) + +-(define_insn "*ifcompare_shift_shift" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (if_then_else:SI +- (match_operator 7 "arm_comparison_operator" +- [(match_operand:SI 5 "s_register_operand" "r") +- (match_operand:SI 6 "arm_add_operand" "rIL")]) +- (match_operator:SI 8 "shift_operator" +- [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "arm_rhs_operand" "rM")]) +- (match_operator:SI 9 "shift_operator" +- [(match_operand:SI 3 "s_register_operand" "r") +- (match_operand:SI 4 "arm_rhs_operand" "rM")]))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "#" +- [(set_attr "conds" "clob") +- (set_attr "length" "12")] +-) ++;(define_insn "*ifcompare_move_arith" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++; (if_then_else:SI (match_operator 6 "arm_comparison_operator" ++; [(match_operand:SI 4 "s_register_operand" "r,r") ++; (match_operand:SI 5 "arm_add_operand" "rIL,rIL")]) ++; (match_operand:SI 1 "arm_rhs_operand" "0,?rI") ++; (match_operator:SI 7 "shiftable_operator" ++; [(match_operand:SI 2 "s_register_operand" "r,r") ++; (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "* ++; /* If we have an operation where (op x 0) is the identity operation and ++; the conditional operator is LT or GE and we are comparing against zero and ++; everything is in registers then we can do this in two instructions */ ++; if (operands[5] == const0_rtx ++; && GET_CODE (operands[7]) != AND ++; && GET_CODE (operands[3]) == REG ++; && GET_CODE (operands[1]) == REG ++; && REGNO (operands[1]) == REGNO (operands[2]) ++; && REGNO (operands[2]) != REGNO (operands[0])) ++; { ++; if (GET_CODE (operands[6]) == GE) ++; return \"and\\t%0, %3, %4, asr #31\;%I7\\t%0, %2, %0\"; ++; else if (GET_CODE (operands[6]) == LT) ++; return \"bic\\t%0, %3, %4, asr #31\;%I7\\t%0, %2, %0\"; ++; } ++; ++; if (GET_CODE (operands[5]) == CONST_INT ++; && !const_ok_for_arm (INTVAL (operands[5]))) ++; output_asm_insn (\"cmn\\t%4, #%n5\", operands); ++; else ++; output_asm_insn (\"cmp\\t%4, %5\", operands); ++; ++; if (which_alternative != 0) ++; output_asm_insn (\"mov%d6\\t%0, %1\", operands); ++; return \"%I7%D6\\t%0, %2, %3\"; ++; " ++; [(set_attr "conds" "clob") ++; (set_attr "length" "8,12")] ++;) + +-(define_insn "*if_shift_shift" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (if_then_else:SI +- (match_operator 5 "arm_comparison_operator" +- [(match_operand 8 "cc_register" "") (const_int 0)]) +- (match_operator:SI 6 "shift_operator" +- [(match_operand:SI 1 "s_register_operand" "r") +- (match_operand:SI 2 "arm_rhs_operand" "rM")]) +- (match_operator:SI 7 "shift_operator" +- [(match_operand:SI 3 "s_register_operand" "r") +- (match_operand:SI 4 "arm_rhs_operand" "rM")])))] +- "TARGET_ARM" +- "mov%d5\\t%0, %1%S6\;mov%D5\\t%0, %3%S7" +- [(set_attr "conds" "use") +- (set_attr "shift" "1") +- (set_attr "length" "8") +- (set (attr "type") (if_then_else +- (and (match_operand 2 "const_int_operand" "") +- (match_operand 4 "const_int_operand" "")) +- (const_string "alu_shift") +- (const_string "alu_shift_reg")))] +-) ++;(define_insn "*if_move_arith" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++; (if_then_else:SI ++; (match_operator 4 "arm_comparison_operator" ++; [(match_operand 6 "cc_register" "") (const_int 0)]) ++; (match_operand:SI 1 "arm_rhs_operand" "0,?rI") ++; (match_operator:SI 5 "shiftable_operator" ++; [(match_operand:SI 2 "s_register_operand" "r,r") ++; (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))] ++; "TARGET_ARM" ++; "@ ++; %I5%D4\\t%0, %2, %3 ++; %I5%D4\\t%0, %2, %3\;mov%d4\\t%0, %1" ++; [(set_attr "conds" "use") ++; (set_attr "length" "4,8") ++; (set_attr "type" "*,*")] ++;) + +-(define_insn "*ifcompare_not_arith" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (if_then_else:SI +- (match_operator 6 "arm_comparison_operator" +- [(match_operand:SI 4 "s_register_operand" "r") +- (match_operand:SI 5 "arm_add_operand" "rIL")]) +- (not:SI (match_operand:SI 1 "s_register_operand" "r")) +- (match_operator:SI 7 "shiftable_operator" +- [(match_operand:SI 2 "s_register_operand" "r") +- (match_operand:SI 3 "arm_rhs_operand" "rI")]))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "#" +- [(set_attr "conds" "clob") +- (set_attr "length" "12")] +-) ++;(define_insn "*ifcompare_move_not" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++; (if_then_else:SI ++; (match_operator 5 "arm_comparison_operator" ++; [(match_operand:SI 3 "s_register_operand" "r,r") ++; (match_operand:SI 4 "arm_add_operand" "rIL,rIL")]) ++; (match_operand:SI 1 "arm_not_operand" "0,?rIK") ++; (not:SI ++; (match_operand:SI 2 "s_register_operand" "r,r")))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "#" ++; [(set_attr "conds" "clob") ++; (set_attr "length" "8,12")] ++;) + +-(define_insn "*if_not_arith" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (if_then_else:SI +- (match_operator 5 "arm_comparison_operator" +- [(match_operand 4 "cc_register" "") (const_int 0)]) +- (not:SI (match_operand:SI 1 "s_register_operand" "r")) +- (match_operator:SI 6 "shiftable_operator" +- [(match_operand:SI 2 "s_register_operand" "r") +- (match_operand:SI 3 "arm_rhs_operand" "rI")])))] +- "TARGET_ARM" +- "mvn%d5\\t%0, %1\;%I6%D5\\t%0, %2, %3" +- [(set_attr "conds" "use") +- (set_attr "length" "8")] +-) ++;(define_insn "*if_move_not" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") ++; (if_then_else:SI ++; (match_operator 4 "arm_comparison_operator" ++; [(match_operand 3 "cc_register" "") (const_int 0)]) ++; (match_operand:SI 1 "arm_not_operand" "0,?rI,K") ++; (not:SI (match_operand:SI 2 "s_register_operand" "r,r,r"))))] ++; "TARGET_ARM" ++; "@ ++; mvn%D4\\t%0, %2 ++; mov%d4\\t%0, %1\;mvn%D4\\t%0, %2 ++; mvn%d4\\t%0, #%B1\;mvn%D4\\t%0, %2" ++; [(set_attr "conds" "use") ++; (set_attr "length" "4,8,8")] ++;) + +-(define_insn "*ifcompare_arith_not" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (if_then_else:SI +- (match_operator 6 "arm_comparison_operator" +- [(match_operand:SI 4 "s_register_operand" "r") +- (match_operand:SI 5 "arm_add_operand" "rIL")]) +- (match_operator:SI 7 "shiftable_operator" +- [(match_operand:SI 2 "s_register_operand" "r") +- (match_operand:SI 3 "arm_rhs_operand" "rI")]) +- (not:SI (match_operand:SI 1 "s_register_operand" "r")))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "#" +- [(set_attr "conds" "clob") +- (set_attr "length" "12")] +-) ++;(define_insn "*ifcompare_not_move" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++; (if_then_else:SI ++; (match_operator 5 "arm_comparison_operator" ++; [(match_operand:SI 3 "s_register_operand" "r,r") ++; (match_operand:SI 4 "arm_add_operand" "rIL,rIL")]) ++; (not:SI ++; (match_operand:SI 2 "s_register_operand" "r,r")) ++; (match_operand:SI 1 "arm_not_operand" "0,?rIK"))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "#" ++; [(set_attr "conds" "clob") ++; (set_attr "length" "8,12")] ++;) + +-(define_insn "*if_arith_not" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (if_then_else:SI +- (match_operator 5 "arm_comparison_operator" +- [(match_operand 4 "cc_register" "") (const_int 0)]) +- (match_operator:SI 6 "shiftable_operator" +- [(match_operand:SI 2 "s_register_operand" "r") +- (match_operand:SI 3 "arm_rhs_operand" "rI")]) +- (not:SI (match_operand:SI 1 "s_register_operand" "r"))))] +- "TARGET_ARM" +- "mvn%D5\\t%0, %1\;%I6%d5\\t%0, %2, %3" +- [(set_attr "conds" "use") +- (set_attr "length" "8")] +-) ++;(define_insn "*if_not_move" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") ++; (if_then_else:SI ++; (match_operator 4 "arm_comparison_operator" ++; [(match_operand 3 "cc_register" "") (const_int 0)]) ++; (not:SI (match_operand:SI 2 "s_register_operand" "r,r,r")) ++; (match_operand:SI 1 "arm_not_operand" "0,?rI,K")))] ++; "TARGET_ARM" ++; "@ ++; mvn%d4\\t%0, %2 ++; mov%D4\\t%0, %1\;mvn%d4\\t%0, %2 ++; mvn%D4\\t%0, #%B1\;mvn%d4\\t%0, %2" ++; [(set_attr "conds" "use") ++; (set_attr "length" "4,8,8")] ++;) + +-(define_insn "*ifcompare_neg_move" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (if_then_else:SI +- (match_operator 5 "arm_comparison_operator" +- [(match_operand:SI 3 "s_register_operand" "r,r") +- (match_operand:SI 4 "arm_add_operand" "rIL,rIL")]) +- (neg:SI (match_operand:SI 2 "s_register_operand" "r,r")) +- (match_operand:SI 1 "arm_not_operand" "0,?rIK"))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "#" +- [(set_attr "conds" "clob") +- (set_attr "length" "8,12")] +-) ++;(define_insn "*ifcompare_shift_move" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++; (if_then_else:SI ++; (match_operator 6 "arm_comparison_operator" ++; [(match_operand:SI 4 "s_register_operand" "r,r") ++; (match_operand:SI 5 "arm_add_operand" "rIL,rIL")]) ++; (match_operator:SI 7 "shift_operator" ++; [(match_operand:SI 2 "s_register_operand" "r,r") ++; (match_operand:SI 3 "arm_rhs_operand" "rM,rM")]) ++; (match_operand:SI 1 "arm_not_operand" "0,?rIK"))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "#" ++; [(set_attr "conds" "clob") ++; (set_attr "length" "8,12")] ++;) + +-(define_insn "*if_neg_move" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") +- (if_then_else:SI +- (match_operator 4 "arm_comparison_operator" +- [(match_operand 3 "cc_register" "") (const_int 0)]) +- (neg:SI (match_operand:SI 2 "s_register_operand" "r,r,r")) +- (match_operand:SI 1 "arm_not_operand" "0,?rI,K")))] +- "TARGET_ARM" +- "@ +- rsb%d4\\t%0, %2, #0 +- mov%D4\\t%0, %1\;rsb%d4\\t%0, %2, #0 +- mvn%D4\\t%0, #%B1\;rsb%d4\\t%0, %2, #0" +- [(set_attr "conds" "use") +- (set_attr "length" "4,8,8")] +-) ++;(define_insn "*if_shift_move" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") ++; (if_then_else:SI ++; (match_operator 5 "arm_comparison_operator" ++; [(match_operand 6 "cc_register" "") (const_int 0)]) ++; (match_operator:SI 4 "shift_operator" ++; [(match_operand:SI 2 "s_register_operand" "r,r,r") ++; (match_operand:SI 3 "arm_rhs_operand" "rM,rM,rM")]) ++; (match_operand:SI 1 "arm_not_operand" "0,?rI,K")))] ++; "TARGET_ARM" ++; "@ ++; mov%d5\\t%0, %2%S4 ++; mov%D5\\t%0, %1\;mov%d5\\t%0, %2%S4 ++; mvn%D5\\t%0, #%B1\;mov%d5\\t%0, %2%S4" ++; [(set_attr "conds" "use") ++; (set_attr "shift" "2") ++; (set_attr "length" "4,8,8") ++; (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") ++; (const_string "alu_shift") ++; (const_string "alu_shift_reg")))] ++;) + +-(define_insn "*ifcompare_move_neg" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (if_then_else:SI +- (match_operator 5 "arm_comparison_operator" +- [(match_operand:SI 3 "s_register_operand" "r,r") +- (match_operand:SI 4 "arm_add_operand" "rIL,rIL")]) +- (match_operand:SI 1 "arm_not_operand" "0,?rIK") +- (neg:SI (match_operand:SI 2 "s_register_operand" "r,r")))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "#" +- [(set_attr "conds" "clob") +- (set_attr "length" "8,12")] +-) ++;(define_insn "*ifcompare_move_shift" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++; (if_then_else:SI ++; (match_operator 6 "arm_comparison_operator" ++; [(match_operand:SI 4 "s_register_operand" "r,r") ++; (match_operand:SI 5 "arm_add_operand" "rIL,rIL")]) ++; (match_operand:SI 1 "arm_not_operand" "0,?rIK") ++; (match_operator:SI 7 "shift_operator" ++; [(match_operand:SI 2 "s_register_operand" "r,r") ++; (match_operand:SI 3 "arm_rhs_operand" "rM,rM")]))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "#" ++; [(set_attr "conds" "clob") ++; (set_attr "length" "8,12")] ++;) + +-(define_insn "*if_move_neg" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") +- (if_then_else:SI +- (match_operator 4 "arm_comparison_operator" +- [(match_operand 3 "cc_register" "") (const_int 0)]) +- (match_operand:SI 1 "arm_not_operand" "0,?rI,K") +- (neg:SI (match_operand:SI 2 "s_register_operand" "r,r,r"))))] +- "TARGET_ARM" +- "@ +- rsb%D4\\t%0, %2, #0 +- mov%d4\\t%0, %1\;rsb%D4\\t%0, %2, #0 +- mvn%d4\\t%0, #%B1\;rsb%D4\\t%0, %2, #0" +- [(set_attr "conds" "use") +- (set_attr "length" "4,8,8")] +-) ++;(define_insn "*if_move_shift" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") ++; (if_then_else:SI ++; (match_operator 5 "arm_comparison_operator" ++; [(match_operand 6 "cc_register" "") (const_int 0)]) ++; (match_operand:SI 1 "arm_not_operand" "0,?rI,K") ++; (match_operator:SI 4 "shift_operator" ++; [(match_operand:SI 2 "s_register_operand" "r,r,r") ++; (match_operand:SI 3 "arm_rhs_operand" "rM,rM,rM")])))] ++; "TARGET_ARM" ++; "@ ++; mov%D5\\t%0, %2%S4 ++; mov%d5\\t%0, %1\;mov%D5\\t%0, %2%S4 ++; mvn%d5\\t%0, #%B1\;mov%D5\\t%0, %2%S4" ++; [(set_attr "conds" "use") ++; (set_attr "shift" "2") ++; (set_attr "length" "4,8,8") ++; (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") ++; (const_string "alu_shift") ++; (const_string "alu_shift_reg")))] ++;) + +-(define_insn "*arith_adjacentmem" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (match_operator:SI 1 "shiftable_operator" +- [(match_operand:SI 2 "memory_operand" "m") +- (match_operand:SI 3 "memory_operand" "m")])) +- (clobber (match_scratch:SI 4 "=r"))] +- "TARGET_ARM && adjacent_mem_locations (operands[2], operands[3])" +- "* +- { +- rtx ldm[3]; +- rtx arith[4]; +- rtx base_reg; +- HOST_WIDE_INT val1 = 0, val2 = 0; ++;(define_insn "*ifcompare_shift_shift" ++; [(set (match_operand:SI 0 "s_register_operand" "=r") ++; (if_then_else:SI ++; (match_operator 7 "arm_comparison_operator" ++; [(match_operand:SI 5 "s_register_operand" "r") ++; (match_operand:SI 6 "arm_add_operand" "rIL")]) ++; (match_operator:SI 8 "shift_operator" ++; [(match_operand:SI 1 "s_register_operand" "r") ++; (match_operand:SI 2 "arm_rhs_operand" "rM")]) ++; (match_operator:SI 9 "shift_operator" ++; [(match_operand:SI 3 "s_register_operand" "r") ++; (match_operand:SI 4 "arm_rhs_operand" "rM")]))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "#" ++; [(set_attr "conds" "clob") ++; (set_attr "length" "12")] ++;) + +- if (REGNO (operands[0]) > REGNO (operands[4])) +- { +- ldm[1] = operands[4]; +- ldm[2] = operands[0]; +- } +- else +- { +- ldm[1] = operands[0]; +- ldm[2] = operands[4]; +- } ++;(define_insn "*if_shift_shift" ++; [(set (match_operand:SI 0 "s_register_operand" "=r") ++; (if_then_else:SI ++; (match_operator 5 "arm_comparison_operator" ++; [(match_operand 8 "cc_register" "") (const_int 0)]) ++; (match_operator:SI 6 "shift_operator" ++; [(match_operand:SI 1 "s_register_operand" "r") ++; (match_operand:SI 2 "arm_rhs_operand" "rM")]) ++; (match_operator:SI 7 "shift_operator" ++; [(match_operand:SI 3 "s_register_operand" "r") ++; (match_operand:SI 4 "arm_rhs_operand" "rM")])))] ++; "TARGET_ARM" ++; "mov%d5\\t%0, %1%S6\;mov%D5\\t%0, %3%S7" ++; [(set_attr "conds" "use") ++; (set_attr "shift" "1") ++; (set_attr "length" "8") ++; (set (attr "type") (if_then_else ++; (and (match_operand 2 "const_int_operand" "") ++; (match_operand 4 "const_int_operand" "")) ++; (const_string "alu_shift") ++; (const_string "alu_shift_reg")))] ++;) + +- base_reg = XEXP (operands[2], 0); ++;(define_insn "*ifcompare_not_arith" ++; [(set (match_operand:SI 0 "s_register_operand" "=r") ++; (if_then_else:SI ++; (match_operator 6 "arm_comparison_operator" ++; [(match_operand:SI 4 "s_register_operand" "r") ++; (match_operand:SI 5 "arm_add_operand" "rIL")]) ++; (not:SI (match_operand:SI 1 "s_register_operand" "r")) ++; (match_operator:SI 7 "shiftable_operator" ++; [(match_operand:SI 2 "s_register_operand" "r") ++; (match_operand:SI 3 "arm_rhs_operand" "rI")]))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "#" ++; [(set_attr "conds" "clob") ++; (set_attr "length" "12")] ++;) + +- if (!REG_P (base_reg)) +- { +- val1 = INTVAL (XEXP (base_reg, 1)); +- base_reg = XEXP (base_reg, 0); +- } ++;(define_insn "*if_not_arith" ++; [(set (match_operand:SI 0 "s_register_operand" "=r") ++; (if_then_else:SI ++; (match_operator 5 "arm_comparison_operator" ++; [(match_operand 4 "cc_register" "") (const_int 0)]) ++; (not:SI (match_operand:SI 1 "s_register_operand" "r")) ++; (match_operator:SI 6 "shiftable_operator" ++; [(match_operand:SI 2 "s_register_operand" "r") ++; (match_operand:SI 3 "arm_rhs_operand" "rI")])))] ++; "TARGET_ARM" ++; "mvn%d5\\t%0, %1\;%I6%D5\\t%0, %2, %3" ++; [(set_attr "conds" "use") ++; (set_attr "length" "8")] ++;) + +- if (!REG_P (XEXP (operands[3], 0))) +- val2 = INTVAL (XEXP (XEXP (operands[3], 0), 1)); ++;(define_insn "*ifcompare_arith_not" ++; [(set (match_operand:SI 0 "s_register_operand" "=r") ++; (if_then_else:SI ++; (match_operator 6 "arm_comparison_operator" ++; [(match_operand:SI 4 "s_register_operand" "r") ++; (match_operand:SI 5 "arm_add_operand" "rIL")]) ++; (match_operator:SI 7 "shiftable_operator" ++; [(match_operand:SI 2 "s_register_operand" "r") ++; (match_operand:SI 3 "arm_rhs_operand" "rI")]) ++; (not:SI (match_operand:SI 1 "s_register_operand" "r")))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "#" ++; [(set_attr "conds" "clob") ++; (set_attr "length" "12")] ++;) + +- arith[0] = operands[0]; +- arith[3] = operands[1]; ++;(define_insn "*if_arith_not" ++; [(set (match_operand:SI 0 "s_register_operand" "=r") ++; (if_then_else:SI ++; (match_operator 5 "arm_comparison_operator" ++; [(match_operand 4 "cc_register" "") (const_int 0)]) ++; (match_operator:SI 6 "shiftable_operator" ++; [(match_operand:SI 2 "s_register_operand" "r") ++; (match_operand:SI 3 "arm_rhs_operand" "rI")]) ++; (not:SI (match_operand:SI 1 "s_register_operand" "r"))))] ++; "TARGET_ARM" ++; "mvn%D5\\t%0, %1\;%I6%d5\\t%0, %2, %3" ++; [(set_attr "conds" "use") ++; (set_attr "length" "8")] ++;) + +- if (val1 < val2) +- { +- arith[1] = ldm[1]; +- arith[2] = ldm[2]; +- } +- else +- { +- arith[1] = ldm[2]; +- arith[2] = ldm[1]; +- } ++;(define_insn "*ifcompare_neg_move" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++; (if_then_else:SI ++; (match_operator 5 "arm_comparison_operator" ++; [(match_operand:SI 3 "s_register_operand" "r,r") ++; (match_operand:SI 4 "arm_add_operand" "rIL,rIL")]) ++; (neg:SI (match_operand:SI 2 "s_register_operand" "r,r")) ++; (match_operand:SI 1 "arm_not_operand" "0,?rIK"))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "#" ++; [(set_attr "conds" "clob") ++; (set_attr "length" "8,12")] ++;) + +- ldm[0] = base_reg; +- if (val1 !=0 && val2 != 0) +- { +- rtx ops[3]; ++;(define_insn "*if_neg_move" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") ++; (if_then_else:SI ++; (match_operator 4 "arm_comparison_operator" ++; [(match_operand 3 "cc_register" "") (const_int 0)]) ++; (neg:SI (match_operand:SI 2 "s_register_operand" "r,r,r")) ++; (match_operand:SI 1 "arm_not_operand" "0,?rI,K")))] ++; "TARGET_ARM" ++; "@ ++; rsb%d4\\t%0, %2, #0 ++; mov%D4\\t%0, %1\;rsb%d4\\t%0, %2, #0 ++; mvn%D4\\t%0, #%B1\;rsb%d4\\t%0, %2, #0" ++; [(set_attr "conds" "use") ++; (set_attr "length" "4,8,8")] ++;) + +- if (val1 == 4 || val2 == 4) +- /* Other val must be 8, since we know they are adjacent and neither +- is zero. */ +- output_asm_insn (\"ldm%?ib\\t%0, {%1, %2}\", ldm); +- else if (const_ok_for_arm (val1) || const_ok_for_arm (-val1)) +- { +- ldm[0] = ops[0] = operands[4]; +- ops[1] = base_reg; +- ops[2] = GEN_INT (val1); +- output_add_immediate (ops); +- if (val1 < val2) +- output_asm_insn (\"ldm%?ia\\t%0, {%1, %2}\", ldm); +- else +- output_asm_insn (\"ldm%?da\\t%0, {%1, %2}\", ldm); +- } +- else +- { +- /* Offset is out of range for a single add, so use two ldr. */ +- ops[0] = ldm[1]; +- ops[1] = base_reg; +- ops[2] = GEN_INT (val1); +- output_asm_insn (\"ldr%?\\t%0, [%1, %2]\", ops); +- ops[0] = ldm[2]; +- ops[2] = GEN_INT (val2); +- output_asm_insn (\"ldr%?\\t%0, [%1, %2]\", ops); +- } +- } +- else if (val1 != 0) +- { +- if (val1 < val2) +- output_asm_insn (\"ldm%?da\\t%0, {%1, %2}\", ldm); +- else +- output_asm_insn (\"ldm%?ia\\t%0, {%1, %2}\", ldm); +- } +- else +- { +- if (val1 < val2) +- output_asm_insn (\"ldm%?ia\\t%0, {%1, %2}\", ldm); +- else +- output_asm_insn (\"ldm%?da\\t%0, {%1, %2}\", ldm); +- } +- output_asm_insn (\"%I3%?\\t%0, %1, %2\", arith); +- return \"\"; +- }" +- [(set_attr "length" "12") +- (set_attr "predicable" "yes") +- (set_attr "type" "load1")] +-) ++;(define_insn "*ifcompare_move_neg" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++; (if_then_else:SI ++; (match_operator 5 "arm_comparison_operator" ++; [(match_operand:SI 3 "s_register_operand" "r,r") ++; (match_operand:SI 4 "arm_add_operand" "rIL,rIL")]) ++; (match_operand:SI 1 "arm_not_operand" "0,?rIK") ++; (neg:SI (match_operand:SI 2 "s_register_operand" "r,r")))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "#" ++; [(set_attr "conds" "clob") ++; (set_attr "length" "8,12")] ++;) ++ ++;(define_insn "*if_move_neg" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") ++; (if_then_else:SI ++; (match_operator 4 "arm_comparison_operator" ++; [(match_operand 3 "cc_register" "") (const_int 0)]) ++; (match_operand:SI 1 "arm_not_operand" "0,?rI,K") ++; (neg:SI (match_operand:SI 2 "s_register_operand" "r,r,r"))))] ++; "TARGET_ARM" ++; "@ ++; rsb%D4\\t%0, %2, #0 ++; mov%d4\\t%0, %1\;rsb%D4\\t%0, %2, #0 ++; mvn%d4\\t%0, #%B1\;rsb%D4\\t%0, %2, #0" ++; [(set_attr "conds" "use") ++; (set_attr "length" "4,8,8")] ++;) ++ ++;(define_insn "*arith_adjacentmem" ++; [(set (match_operand:SI 0 "s_register_operand" "=r") ++; (match_operator:SI 1 "shiftable_operator" ++; [(match_operand:SI 2 "memory_operand" "m") ++; (match_operand:SI 3 "memory_operand" "m")])) ++; (clobber (match_scratch:SI 4 "=r"))] ++; "TARGET_ARM && adjacent_mem_locations (operands[2], operands[3])" ++; "* ++; { ++; rtx ldm[3]; ++; rtx arith[4]; ++; rtx base_reg; ++; HOST_WIDE_INT val1 = 0, val2 = 0; ++; ++; if (REGNO (operands[0]) > REGNO (operands[4])) ++; { ++; ldm[1] = operands[4]; ++; ldm[2] = operands[0]; ++; } ++; else ++; { ++; ldm[1] = operands[0]; ++; ldm[2] = operands[4]; ++; } ++; ++; base_reg = XEXP (operands[2], 0); ++; ++; if (!REG_P (base_reg)) ++; { ++; val1 = INTVAL (XEXP (base_reg, 1)); ++; base_reg = XEXP (base_reg, 0); ++; } ++; ++; if (!REG_P (XEXP (operands[3], 0))) ++; val2 = INTVAL (XEXP (XEXP (operands[3], 0), 1)); ++; ++; arith[0] = operands[0]; ++; arith[3] = operands[1]; ++; ++; if (val1 < val2) ++; { ++; arith[1] = ldm[1]; ++; arith[2] = ldm[2]; ++; } ++; else ++; { ++; arith[1] = ldm[2]; ++; arith[2] = ldm[1]; ++; } ++; ++; ldm[0] = base_reg; ++; if (val1 !=0 && val2 != 0) ++; { ++; rtx ops[3]; ++; ++; if (val1 == 4 || val2 == 4) ++; /* Other val must be 8, since we know they are adjacent and neither ++; is zero. */ ++; output_asm_insn (\"ldm%?ib\\t%0, {%1, %2}\", ldm); ++; else if (const_ok_for_arm (val1) || const_ok_for_arm (-val1)) ++; { ++; ldm[0] = ops[0] = operands[4]; ++; ops[1] = base_reg; ++; ops[2] = GEN_INT (val1); ++; output_add_immediate (ops); ++; if (val1 < val2) ++; output_asm_insn (\"ldm%?ia\\t%0, {%1, %2}\", ldm); ++; else ++; output_asm_insn (\"ldm%?da\\t%0, {%1, %2}\", ldm); ++; } ++; else ++; { ++; /* Offset is out of range for a single add, so use two ldr. */ ++; ops[0] = ldm[1]; ++; ops[1] = base_reg; ++; ops[2] = GEN_INT (val1); ++; output_asm_insn (\"ldr%?\\t%0, [%1, %2]\", ops); ++; ops[0] = ldm[2]; ++; ops[2] = GEN_INT (val2); ++; output_asm_insn (\"ldr%?\\t%0, [%1, %2]\", ops); ++; } ++; } ++; else if (val1 != 0) ++; { ++; if (val1 < val2) ++; output_asm_insn (\"ldm%?da\\t%0, {%1, %2}\", ldm); ++; else ++; output_asm_insn (\"ldm%?ia\\t%0, {%1, %2}\", ldm); ++; } ++; else ++; { ++; if (val1 < val2) ++; output_asm_insn (\"ldm%?ia\\t%0, {%1, %2}\", ldm); ++; else ++; output_asm_insn (\"ldm%?da\\t%0, {%1, %2}\", ldm); ++; } ++; output_asm_insn (\"%I3%?\\t%0, %1, %2\", arith); ++; return \"\"; ++; }" ++; [(set_attr "length" "12") ++; (set_attr "predicable" "yes") ++; (set_attr "type" "load1")] ++;) + + ; This pattern is never tried by combine, so do it as a peephole + +-(define_peephole2 +- [(set (match_operand:SI 0 "arm_general_register_operand" "") +- (match_operand:SI 1 "arm_general_register_operand" "")) +- (set (reg:CC CC_REGNUM) +- (compare:CC (match_dup 1) (const_int 0)))] +- "TARGET_ARM" +- [(parallel [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (const_int 0))) +- (set (match_dup 0) (match_dup 1))])] +- "" +-) ++;(define_peephole2 ++; [(set (match_operand:SI 0 "arm_general_register_operand" "") ++; (match_operand:SI 1 "arm_general_register_operand" "")) ++; (set (reg:CC CC_REGNUM) ++; (compare:CC (match_dup 1) (const_int 0)))] ++; "TARGET_ARM" ++; [(parallel [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (const_int 0))) ++; (set (match_dup 0) (match_dup 1))])] ++; "" ++;) + + ; Peepholes to spot possible load- and store-multiples, if the ordering is + ; reversed, check that the memory references aren't volatile. +@@ -9717,20 +9717,20 @@ + " + ) + +-(define_split +- [(set (match_operand:SI 0 "s_register_operand" "") +- (and:SI (ge:SI (match_operand:SI 1 "s_register_operand" "") +- (const_int 0)) +- (neg:SI (match_operator:SI 2 "arm_comparison_operator" +- [(match_operand:SI 3 "s_register_operand" "") +- (match_operand:SI 4 "arm_rhs_operand" "")])))) +- (clobber (match_operand:SI 5 "s_register_operand" ""))] +- "TARGET_ARM" +- [(set (match_dup 5) (not:SI (ashiftrt:SI (match_dup 1) (const_int 31)))) +- (set (match_dup 0) (and:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)]) +- (match_dup 5)))] +- "" +-) ++;(define_split ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (and:SI (ge:SI (match_operand:SI 1 "s_register_operand" "") ++; (const_int 0)) ++; (neg:SI (match_operator:SI 2 "arm_comparison_operator" ++; [(match_operand:SI 3 "s_register_operand" "") ++; (match_operand:SI 4 "arm_rhs_operand" "")])))) ++; (clobber (match_operand:SI 5 "s_register_operand" ""))] ++; "TARGET_ARM" ++; [(set (match_dup 5) (not:SI (ashiftrt:SI (match_dup 1) (const_int 31)))) ++; (set (match_dup 0) (and:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)]) ++; (match_dup 5)))] ++; "" ++;) + + ;; This split can be used because CC_Z mode implies that the following + ;; branch will be an equality, or an unsigned inequality, so the sign +@@ -9854,168 +9854,168 @@ + ;; some extent with the conditional data operations, so we have to split them + ;; up again here. + +-(define_split +- [(set (match_operand:SI 0 "s_register_operand" "") +- (if_then_else:SI (match_operator 1 "arm_comparison_operator" +- [(match_operand 2 "" "") (match_operand 3 "" "")]) +- (match_dup 0) +- (match_operand 4 "" ""))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM && reload_completed" +- [(set (match_dup 5) (match_dup 6)) +- (cond_exec (match_dup 7) +- (set (match_dup 0) (match_dup 4)))] +- " +- { +- enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]), +- operands[2], operands[3]); +- enum rtx_code rc = GET_CODE (operands[1]); +- +- operands[5] = gen_rtx_REG (mode, CC_REGNUM); +- operands[6] = gen_rtx_COMPARE (mode, operands[2], operands[3]); +- if (mode == CCFPmode || mode == CCFPEmode) +- rc = reverse_condition_maybe_unordered (rc); +- else +- rc = reverse_condition (rc); +- +- operands[7] = gen_rtx_fmt_ee (rc, VOIDmode, operands[5], const0_rtx); +- }" +-) +- +-(define_split +- [(set (match_operand:SI 0 "s_register_operand" "") +- (if_then_else:SI (match_operator 1 "arm_comparison_operator" +- [(match_operand 2 "" "") (match_operand 3 "" "")]) +- (match_operand 4 "" "") +- (match_dup 0))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM && reload_completed" +- [(set (match_dup 5) (match_dup 6)) +- (cond_exec (match_op_dup 1 [(match_dup 5) (const_int 0)]) +- (set (match_dup 0) (match_dup 4)))] +- " +- { +- enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]), +- operands[2], operands[3]); +- +- operands[5] = gen_rtx_REG (mode, CC_REGNUM); +- operands[6] = gen_rtx_COMPARE (mode, operands[2], operands[3]); +- }" +-) +- +-(define_split +- [(set (match_operand:SI 0 "s_register_operand" "") +- (if_then_else:SI (match_operator 1 "arm_comparison_operator" +- [(match_operand 2 "" "") (match_operand 3 "" "")]) +- (match_operand 4 "" "") +- (match_operand 5 "" ""))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM && reload_completed" +- [(set (match_dup 6) (match_dup 7)) +- (cond_exec (match_op_dup 1 [(match_dup 6) (const_int 0)]) +- (set (match_dup 0) (match_dup 4))) +- (cond_exec (match_dup 8) +- (set (match_dup 0) (match_dup 5)))] +- " +- { +- enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]), +- operands[2], operands[3]); +- enum rtx_code rc = GET_CODE (operands[1]); +- +- operands[6] = gen_rtx_REG (mode, CC_REGNUM); +- operands[7] = gen_rtx_COMPARE (mode, operands[2], operands[3]); +- if (mode == CCFPmode || mode == CCFPEmode) +- rc = reverse_condition_maybe_unordered (rc); +- else +- rc = reverse_condition (rc); ++;(define_split ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (if_then_else:SI (match_operator 1 "arm_comparison_operator" ++; [(match_operand 2 "" "") (match_operand 3 "" "")]) ++; (match_dup 0) ++; (match_operand 4 "" ""))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM && reload_completed" ++; [(set (match_dup 5) (match_dup 6)) ++; (cond_exec (match_dup 7) ++; (set (match_dup 0) (match_dup 4)))] ++; " ++; { ++; enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]), ++; operands[2], operands[3]); ++; enum rtx_code rc = GET_CODE (operands[1]); ++; ++; operands[5] = gen_rtx_REG (mode, CC_REGNUM); ++; operands[6] = gen_rtx_COMPARE (mode, operands[2], operands[3]); ++; if (mode == CCFPmode || mode == CCFPEmode) ++; rc = reverse_condition_maybe_unordered (rc); ++; else ++; rc = reverse_condition (rc); ++; ++; operands[7] = gen_rtx_fmt_ee (rc, VOIDmode, operands[5], const0_rtx); ++; }" ++;) + +- operands[8] = gen_rtx_fmt_ee (rc, VOIDmode, operands[6], const0_rtx); +- }" +-) ++;(define_split ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (if_then_else:SI (match_operator 1 "arm_comparison_operator" ++; [(match_operand 2 "" "") (match_operand 3 "" "")]) ++; (match_operand 4 "" "") ++; (match_dup 0))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM && reload_completed" ++; [(set (match_dup 5) (match_dup 6)) ++; (cond_exec (match_op_dup 1 [(match_dup 5) (const_int 0)]) ++; (set (match_dup 0) (match_dup 4)))] ++; " ++; { ++; enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]), ++; operands[2], operands[3]); ++; ++; operands[5] = gen_rtx_REG (mode, CC_REGNUM); ++; operands[6] = gen_rtx_COMPARE (mode, operands[2], operands[3]); ++; }" ++;) + +-(define_split +- [(set (match_operand:SI 0 "s_register_operand" "") +- (if_then_else:SI (match_operator 1 "arm_comparison_operator" +- [(match_operand:SI 2 "s_register_operand" "") +- (match_operand:SI 3 "arm_add_operand" "")]) +- (match_operand:SI 4 "arm_rhs_operand" "") +- (not:SI +- (match_operand:SI 5 "s_register_operand" "")))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM && reload_completed" +- [(set (match_dup 6) (match_dup 7)) +- (cond_exec (match_op_dup 1 [(match_dup 6) (const_int 0)]) +- (set (match_dup 0) (match_dup 4))) +- (cond_exec (match_dup 8) +- (set (match_dup 0) (not:SI (match_dup 5))))] +- " +- { +- enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]), +- operands[2], operands[3]); +- enum rtx_code rc = GET_CODE (operands[1]); +- +- operands[6] = gen_rtx_REG (mode, CC_REGNUM); +- operands[7] = gen_rtx_COMPARE (mode, operands[2], operands[3]); +- if (mode == CCFPmode || mode == CCFPEmode) +- rc = reverse_condition_maybe_unordered (rc); +- else +- rc = reverse_condition (rc); ++;(define_split ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (if_then_else:SI (match_operator 1 "arm_comparison_operator" ++; [(match_operand 2 "" "") (match_operand 3 "" "")]) ++; (match_operand 4 "" "") ++; (match_operand 5 "" ""))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM && reload_completed" ++; [(set (match_dup 6) (match_dup 7)) ++; (cond_exec (match_op_dup 1 [(match_dup 6) (const_int 0)]) ++; (set (match_dup 0) (match_dup 4))) ++; (cond_exec (match_dup 8) ++; (set (match_dup 0) (match_dup 5)))] ++; " ++; { ++; enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]), ++; operands[2], operands[3]); ++; enum rtx_code rc = GET_CODE (operands[1]); ++; ++; operands[6] = gen_rtx_REG (mode, CC_REGNUM); ++; operands[7] = gen_rtx_COMPARE (mode, operands[2], operands[3]); ++; if (mode == CCFPmode || mode == CCFPEmode) ++; rc = reverse_condition_maybe_unordered (rc); ++; else ++; rc = reverse_condition (rc); ++; ++; operands[8] = gen_rtx_fmt_ee (rc, VOIDmode, operands[6], const0_rtx); ++; }" ++;) + +- operands[8] = gen_rtx_fmt_ee (rc, VOIDmode, operands[6], const0_rtx); +- }" +-) ++;(define_split ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (if_then_else:SI (match_operator 1 "arm_comparison_operator" ++; [(match_operand:SI 2 "s_register_operand" "") ++; (match_operand:SI 3 "arm_add_operand" "")]) ++; (match_operand:SI 4 "arm_rhs_operand" "") ++; (not:SI ++; (match_operand:SI 5 "s_register_operand" "")))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM && reload_completed" ++; [(set (match_dup 6) (match_dup 7)) ++; (cond_exec (match_op_dup 1 [(match_dup 6) (const_int 0)]) ++; (set (match_dup 0) (match_dup 4))) ++; (cond_exec (match_dup 8) ++; (set (match_dup 0) (not:SI (match_dup 5))))] ++; " ++; { ++; enum machine_mode mode = SELECT_CC_MODE (GET_CODE (operands[1]), ++; operands[2], operands[3]); ++; enum rtx_code rc = GET_CODE (operands[1]); ++; ++; operands[6] = gen_rtx_REG (mode, CC_REGNUM); ++; operands[7] = gen_rtx_COMPARE (mode, operands[2], operands[3]); ++; if (mode == CCFPmode || mode == CCFPEmode) ++; rc = reverse_condition_maybe_unordered (rc); ++; else ++; rc = reverse_condition (rc); ++; ++; operands[8] = gen_rtx_fmt_ee (rc, VOIDmode, operands[6], const0_rtx); ++; }" ++;) + +-(define_insn "*cond_move_not" +- [(set (match_operand:SI 0 "s_register_operand" "=r,r") +- (if_then_else:SI (match_operator 4 "arm_comparison_operator" +- [(match_operand 3 "cc_register" "") (const_int 0)]) +- (match_operand:SI 1 "arm_rhs_operand" "0,?rI") +- (not:SI +- (match_operand:SI 2 "s_register_operand" "r,r"))))] +- "TARGET_ARM" +- "@ +- mvn%D4\\t%0, %2 +- mov%d4\\t%0, %1\;mvn%D4\\t%0, %2" +- [(set_attr "conds" "use") +- (set_attr "length" "4,8")] +-) ++;(define_insn "*cond_move_not" ++; [(set (match_operand:SI 0 "s_register_operand" "=r,r") ++; (if_then_else:SI (match_operator 4 "arm_comparison_operator" ++; [(match_operand 3 "cc_register" "") (const_int 0)]) ++; (match_operand:SI 1 "arm_rhs_operand" "0,?rI") ++; (not:SI ++; (match_operand:SI 2 "s_register_operand" "r,r"))))] ++; "TARGET_ARM" ++; "@ ++; mvn%D4\\t%0, %2 ++; mov%d4\\t%0, %1\;mvn%D4\\t%0, %2" ++; [(set_attr "conds" "use") ++; (set_attr "length" "4,8")] ++;) + + ;; The next two patterns occur when an AND operation is followed by a + ;; scc insn sequence + +-(define_insn "*sign_extract_onebit" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") +- (const_int 1) +- (match_operand:SI 2 "const_int_operand" "n"))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "* +- operands[2] = GEN_INT (1 << INTVAL (operands[2])); +- output_asm_insn (\"ands\\t%0, %1, %2\", operands); +- return \"mvnne\\t%0, #0\"; +- " +- [(set_attr "conds" "clob") +- (set_attr "length" "8")] +-) ++;(define_insn "*sign_extract_onebit" ++; [(set (match_operand:SI 0 "s_register_operand" "=r") ++; (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") ++; (const_int 1) ++; (match_operand:SI 2 "const_int_operand" "n"))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "* ++; operands[2] = GEN_INT (1 << INTVAL (operands[2])); ++; output_asm_insn (\"ands\\t%0, %1, %2\", operands); ++; return \"mvnne\\t%0, #0\"; ++; " ++; [(set_attr "conds" "clob") ++; (set_attr "length" "8")] ++;) + +-(define_insn "*not_signextract_onebit" +- [(set (match_operand:SI 0 "s_register_operand" "=r") +- (not:SI +- (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") +- (const_int 1) +- (match_operand:SI 2 "const_int_operand" "n")))) +- (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM" +- "* +- operands[2] = GEN_INT (1 << INTVAL (operands[2])); +- output_asm_insn (\"tst\\t%1, %2\", operands); +- output_asm_insn (\"mvneq\\t%0, #0\", operands); +- return \"movne\\t%0, #0\"; +- " +- [(set_attr "conds" "clob") +- (set_attr "length" "12")] +-) ++;(define_insn "*not_signextract_onebit" ++; [(set (match_operand:SI 0 "s_register_operand" "=r") ++; (not:SI ++; (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") ++; (const_int 1) ++; (match_operand:SI 2 "const_int_operand" "n")))) ++; (clobber (reg:CC CC_REGNUM))] ++; "TARGET_ARM" ++; "* ++; operands[2] = GEN_INT (1 << INTVAL (operands[2])); ++; output_asm_insn (\"tst\\t%1, %2\", operands); ++; output_asm_insn (\"mvneq\\t%0, #0\", operands); ++; return \"movne\\t%0, #0\"; ++; " ++; [(set_attr "conds" "clob") ++; (set_attr "length" "12")] ++;) + + ;; Push multiple registers to the stack. Registers are in parallel (use ...) + ;; expressions. For simplicity, the first register is also in the unspec +@@ -10405,11 +10405,11 @@ + ;) + +-(define_cond_exec +- [(match_operator 0 "maverick_comparison_operator" +- [(match_operand:CC 1 "cc_register" "") +- (const_int 0)])] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" +- "" +-) ++;(define_cond_exec ++; [(match_operator 0 "arm_comparison_operator" ++; [(match_operand:CC 1 "cc_register" "") ++; (const_int 0)])] ++; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++; "" ++;) + + ;; General predication pattern diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-dominance.patch b/packages/gcc/gcc-4.1.2/arm-crunch-dominance.patch new file mode 100644 index 0000000000..517ca8d80e --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-dominance.patch @@ -0,0 +1,12 @@ +--- gcc-4.1.2/gcc/config/arm/arm.c-original 2007-06-13 11:50:10.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-06-13 11:50:56.000000000 +1000 +@@ -6556,6 +6556,9 @@ + enum rtx_code cond1, cond2; + int swapped = 0; + ++ if (TARGET_MAVERICK) // Simple hack for MAVERICK ++ return CCmode; ++ + /* Currently we will probably get the wrong result if the individual + comparisons are not simple. This also ensures that it is safe to + reverse a comparison if necessary. */ diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-double-nop-before.patch b/packages/gcc/gcc-4.1.2/arm-crunch-double-nop-before.patch new file mode 100644 index 0000000000..bd09a047f5 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-double-nop-before.patch @@ -0,0 +1,459 @@ +--- arm.md-original 2007-06-28 10:25:37.000000000 +1000 ++++ arm.md 2007-06-28 10:27:22.000000000 +1000 +@@ -6852,7 +6852,7 @@ + (compare:CCFP (match_operand:SF 0 "cirrus_fp_register" "v") + (match_operand:SF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" +- "cfcmps%?\\tr15, %V0, %V1" ++ "nop\;nop\;cfcmps%?\\tr15, %V0, %V1" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "compare")] + ) +@@ -6863,7 +6863,7 @@ + (compare:CCFP (match_operand:DF 0 "cirrus_fp_register" "v") + (match_operand:DF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" +- "cfcmpd%?\\tr15, %V0, %V1" ++ "nop\;nop\;cfcmpd%?\\tr15, %V0, %V1" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "compare")] + ) +@@ -6886,7 +6886,7 @@ + (compare:CC (match_operand:DI 0 "cirrus_fp_register" "v") + (match_operand:DI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK & 0" +- "cfcmp64%?\\tr15, %V0, %V1" ++ "nop\;nop\;cfcmp64%?\\tr15, %V0, %V1" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "compare")] + ) +--- cirrus.md-original 2007-06-28 10:15:59.000000000 +1000 ++++ cirrus.md 2007-06-28 10:25:03.000000000 +1000 +@@ -35,7 +35,7 @@ + (plus:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:DI 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfadd64%?\\t%V0, %V1, %V2" ++ "nop\;nop\;cfadd64%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] + ) +@@ -45,7 +45,7 @@ + (plus:SI (match_operand:SI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfadd32%?\\t%V0, %V1, %V2" ++ "nop\;nop\;cfadd32%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] + ) +@@ -55,7 +55,7 @@ + (plus:SF (match_operand:SF 1 "cirrus_fp_register" "v") + (match_operand:SF 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" +- "cfadds%?\\t%V0, %V1, %V2" ++ "nop\;nop\;cfadds%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] + ) +@@ -65,7 +65,7 @@ + (plus:DF (match_operand:DF 1 "cirrus_fp_register" "v") + (match_operand:DF 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" +- "cfaddd%?\\t%V0, %V1, %V2" ++ "nop\;nop\;cfaddd%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] + ) +@@ -75,7 +75,7 @@ + (minus:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:DI 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfsub64%?\\t%V0, %V1, %V2" ++ "nop\;nop\;cfsub64%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] + ) +@@ -85,7 +85,7 @@ + (minus:SI (match_operand:SI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfsub32%?\\t%V0, %V1, %V2" ++ "nop\;nop\;cfsub32%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] + ) +@@ -95,7 +95,7 @@ + (minus:SF (match_operand:SF 1 "cirrus_fp_register" "v") + (match_operand:SF 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" +- "cfsubs%?\\t%V0, %V1, %V2" ++ "nop\;nop\;cfsubs%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] + ) +@@ -105,7 +105,7 @@ + (minus:DF (match_operand:DF 1 "cirrus_fp_register" "v") + (match_operand:DF 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" +- "cfsubd%?\\t%V0, %V1, %V2" ++ "nop\;nop\;cfsubd%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] + ) +@@ -115,7 +115,7 @@ + (mult:SI (match_operand:SI 2 "cirrus_fp_register" "v") + (match_operand:SI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfmul32%?\\t%V0, %V1, %V2" ++ "nop\;nop\;cfmul32%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] + ) +@@ -125,7 +125,7 @@ + (mult:DI (match_operand:DI 2 "cirrus_fp_register" "v") + (match_operand:DI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfmul64%?\\t%V0, %V1, %V2" ++ "nop\;nop\;cfmul64%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_dmult") + (set_attr "cirrus" "normal")] + ) +@@ -137,7 +137,7 @@ + (match_operand:SI 2 "cirrus_fp_register" "v")) + (match_operand:SI 3 "cirrus_fp_register" "0")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfmac32%?\\t%V0, %V1, %V2" ++ "nop\;nop\;cfmac32%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] + ) +@@ -150,7 +150,7 @@ + (mult:SI (match_operand:SI 2 "cirrus_fp_register" "v") + (match_operand:SI 3 "cirrus_fp_register" "v"))))] + "0 && TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" +- "cfmsc32%?\\t%V0, %V2, %V3" ++ "nop\;nop\;cfmsc32%?\\t%V0, %V2, %V3" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] + ) +@@ -160,7 +160,7 @@ + (mult:SF (match_operand:SF 1 "cirrus_fp_register" "v") + (match_operand:SF 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" +- "cfmuls%?\\t%V0, %V1, %V2" ++ "nop\;nop\;cfmuls%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] + ) +@@ -170,7 +170,7 @@ + (mult:DF (match_operand:DF 1 "cirrus_fp_register" "v") + (match_operand:DF 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" +- "cfmuld%?\\t%V0, %V1, %V2" ++ "nop\;nop\;cfmuld%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_dmult") + (set_attr "cirrus" "normal")] + ) +@@ -180,7 +180,7 @@ + (ashift:SI (match_operand:SI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "cirrus_shift_const" "")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfsh32%?\\t%V0, %V1, #%s2" ++ "nop\;nop\;cfsh32%?\\t%V0, %V1, #%s2" + [(set_attr "cirrus" "normal")] + ) + +@@ -189,7 +189,7 @@ + (ashiftrt:SI (match_operand:SI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "cirrus_shift_const" "")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfsh32%?\\t%V0, %V1, #-%s2" ++ "nop\;nop\;cfsh32%?\\t%V0, %V1, #-%s2" + [(set_attr "cirrus" "normal")] + ) + +@@ -198,7 +198,7 @@ + (ashift:SI (match_operand:SI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "register_operand" "r")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfrshl32%?\\t%V1, %V0, %s2" ++ "nop\;nop\;cfrshl32%?\\t%V1, %V0, %s2" + [(set_attr "cirrus" "normal")] + ) + +@@ -207,7 +207,7 @@ + (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "register_operand" "r")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfrshl64%?\\t%V1, %V0, %s2" ++ "nop\;nop\;cfrshl64%?\\t%V1, %V0, %s2" + [(set_attr "cirrus" "normal")] + ) + +@@ -216,7 +216,7 @@ + (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "cirrus_shift_const" "")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfsh64%?\\t%V0, %V1, #%s2" ++ "nop\;nop\;cfsh64%?\\t%V0, %V1, #%s2" + [(set_attr "cirrus" "normal")] + ) + +@@ -225,7 +225,7 @@ + (ashiftrt:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "cirrus_shift_const" "")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfsh64%?\\t%V0, %V1, #-%s2" ++ "nop\;nop\;cfsh64%?\\t%V0, %V1, #-%s2" + [(set_attr "cirrus" "normal")] + ) + +@@ -233,7 +233,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (abs:DI (match_operand:DI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfabs64%?\\t%V0, %V1" ++ "nop\;nop\;cfabs64%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) + +@@ -244,7 +244,7 @@ + (neg:DI (match_operand:DI 1 "cirrus_fp_register" "v"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfneg64%?\\t%V0, %V1" ++ "nop\;nop\;cfneg64%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) + +@@ -252,7 +252,7 @@ + [(set (match_operand:SI 0 "cirrus_fp_register" "=v") + (neg:SI (match_operand:SI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfneg32%?\\t%V0, %V1" ++ "nop\;nop\;cfneg32%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) + +@@ -261,7 +261,7 @@ + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (neg:SF (match_operand:SF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfnegs%?\\t%V0, %V1" ++ "nop\;nop\;cfnegs%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) + +@@ -270,7 +270,7 @@ + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (neg:DF (match_operand:DF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfnegd%?\\t%V0, %V1" ++ "nop\;nop\;cfnegd%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) + +@@ -280,7 +280,7 @@ + (abs:SI (match_operand:SI 1 "cirrus_fp_register" "v"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfabs32%?\\t%V0, %V1" ++ "nop\;nop\;cfabs32%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) + +@@ -288,7 +288,7 @@ + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (abs:SF (match_operand:SF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" +- "cfabss%?\\t%V0, %V1" ++ "nop\;nop\;cfabss%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) + +@@ -296,7 +296,7 @@ + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (abs:DF (match_operand:DF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" +- "cfabsd%?\\t%V0, %V1" ++ "nop\;nop\;cfabsd%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) + +@@ -307,7 +307,7 @@ + (float:SF (match_operand:SI 1 "s_register_operand" "r"))) + (clobber (match_scratch:DF 2 "=v"))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2" ++ "nop\;nop\;cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2" + [(set_attr "length" "8") + (set_attr "cirrus" "move")] + ) +@@ -318,7 +318,7 @@ + (float:DF (match_operand:SI 1 "s_register_operand" "r"))) + (clobber (match_scratch:DF 2 "=v"))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2" ++ "nop\;nop\;cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2" + [(set_attr "length" "8") + (set_attr "cirrus" "move")] + ) +@@ -327,14 +327,14 @@ + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfcvt64s%?\\t%V0, %V1" ++ "nop\;nop\;cfcvt64s%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")]) + + (define_insn "floatdidf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfcvt64d%?\\t%V0, %V1" ++ "nop\;nop\;cfcvt64d%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")]) + + ; appears to be buggy +@@ -343,7 +343,7 @@ + (fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register" "v")))) + (clobber (match_scratch:DF 2 "=v"))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" ++ "nop\;nop\;cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" + [(set_attr "length" "8") + (set_attr "cirrus" "normal")] + ) +@@ -354,7 +354,7 @@ + (fix:SI (fix:DF (match_operand:DF 1 "cirrus_fp_register" "v")))) + (clobber (match_scratch:DF 2 "=v"))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" ++ "nop\;nop\;cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" + [(set_attr "length" "8") + (set_attr "cirrus" "normal")] + ) +@@ -365,7 +365,7 @@ + (float_truncate:SF + (match_operand:DF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" +- "cfcvtds%?\\t%V0, %V1" ++ "nop\;nop\;cfcvtds%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) + +@@ -373,7 +373,7 @@ + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (float_extend:DF (match_operand:SF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" +- "cfcvtsd%?\\t%V0, %V1" ++ "nop\;nop\;cfcvtsd%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) + +@@ -391,19 +391,19 @@ + case 2: + return output_move_double (operands); + +- case 3: return \"cfmv64lr%?\\t%V0, %Q1\;cfmv64hr%?\\t%V0, %R1\"; +- case 4: return \"cfmvr64l%?\\t%Q0, %V1\;cfmvr64h%?\\t%R0, %V1\"; ++ case 3: return \"nop\;nop\;cfmv64lr%?\\t%V0, %Q1\;cfmv64hr%?\\t%V0, %R1\"; ++ case 4: return \"nop\;nop\;cfmvr64l%?\\t%Q0, %V1\;cfmvr64h%?\\t%R0, %V1\"; + +- case 5: return \"cfldr64%?\\t%V0, %1\"; +- case 6: return \"cfstr64%?\\t%V1, %0\"; ++ case 5: return \"nop\;nop\;cfldr64%?\\t%V0, %1\"; ++ case 6: return \"nop\;nop\;cfstr64%?\\t%V1, %0\"; + + /* Shifting by 0 will just copy %1 into %0. */ +- case 7: return \"cfsh64%?\\t%V0, %V1, #0\"; ++ case 7: return \"nop\;nop\;cfsh64%?\\t%V0, %V1, #0\"; + + default: gcc_unreachable (); + } + }" +- [(set_attr "length" " 8, 8, 8, 8, 8, 4, 4, 4") ++ [(set_attr "length" " 16, 16, 16, 16, 16, 12, 12, 12") + (set_attr "type" " *,load2,store2, *, *, load2,store2, *") + (set_attr "pool_range" " *,1020, *, *, *, 1020, *, *") + (set_attr "neg_pool_range" " *,1012, *, *, *, 1008, *, *") +@@ -420,15 +420,15 @@ + && (register_operand (operands[0], SImode) + || register_operand (operands[1], SImode))" + "@ +- mov%?\\t%0, %1 +- mvn%?\\t%0, #%B1 +- ldr%?\\t%0, %1 +- str%?\\t%1, %0 +- cfmv64lr%?\\t%Z0, %1 +- cfmvr64l%?\\t%0, %Z1 +- cfldr32%?\\t%V0, %1 +- cfstr32%?\\t%V1, %0 +- cfsh32%?\\t%V0, %V1, #0" ++ nop\;nop\;mov%?\\t%0, %1 ++ nop\;nop\;mvn%?\\t%0, #%B1 ++ nop\;nop\;ldr%?\\t%0, %1 ++ nop\;nop\;str%?\\t%1, %0 ++ nop\;nop\;cfmv64lr%?\\t%Z0, %1 ++ nop\;nop\;cfmvr64l%?\\t%0, %Z1 ++ nop\;nop\;cfldr32%?\\t%V0, %1 ++ nop\;nop\;cfstr32%?\\t%V1, %0 ++ nop\;nop\;cfsh32%?\\t%V0, %V1, #0" + [(set_attr "type" "*, *, load1,store1, *, *, load1,store1, *") + (set_attr "pool_range" "*, *, 4096, *, *, *, 1024, *, *") + (set_attr "neg_pool_range" "*, *, 4084, *, *, *, 1012, *, *") +@@ -442,15 +442,15 @@ + && (GET_CODE (operands[0]) != MEM + || register_operand (operands[1], SFmode))" + "@ +- cfcpys%?\\t%V0, %V1 +- cfldrs%?\\t%V0, %1 +- cfmvsr%?\\t%V0, %1 +- cfmvrs%?\\t%0, %V1 +- cfstrs%?\\t%V1, %0 +- mov%?\\t%0, %1 +- ldr%?\\t%0, %1\\t%@ float +- str%?\\t%1, %0\\t%@ float" +- [(set_attr "length" " *, *, *, *, *, 4, 4, 4") ++ nop\;nop\;cfcpys%?\\t%V0, %V1 ++ nop\;nop\;cfldrs%?\\t%V0, %1 ++ nop\;nop\;cfmvsr%?\\t%V0, %1 ++ nop\;nop\;cfmvrs%?\\t%0, %V1 ++ nop\;nop\;cfstrs%?\\t%V1, %0 ++ nop\;nop\;mov%?\\t%0, %1 ++ nop\;nop\;ldr%?\\t%0, %1\\t%@ float ++ nop\;nop\;str%?\\t%1, %0\\t%@ float" ++ [(set_attr "length" " *, *, *, *, *, 12, 12, 12") + (set_attr "type" " *, load1, *, *,store1, *,load1,store1") + (set_attr "pool_range" " *, 1020, *, *, *, *,4096, *") + (set_attr "neg_pool_range" " *, 1008, *, *, *, *,4084, *") +@@ -468,20 +468,20 @@ + { + switch (which_alternative) + { +- case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\"; +- case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\"; ++ case 0: return \"nop\;nop\;ldm%?ia\\t%m1, %M0\\t%@ double\"; ++ case 1: return \"nop\;nop\;stm%?ia\\t%m0, %M1\\t%@ double\"; + case 2: return \"#\"; + case 3: case 4: return output_move_double (operands); +- case 5: return \"cfcpyd%?\\t%V0, %V1\"; +- case 6: return \"cfldrd%?\\t%V0, %1\"; +- case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\"; +- case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\"; +- case 9: return \"cfstrd%?\\t%V1, %0\"; ++ case 5: return \"nop\;nop\;cfcpyd%?\\t%V0, %V1\"; ++ case 6: return \"nop\;nop\;cfldrd%?\\t%V0, %1\"; ++ case 7: return \"nop\;nop\;cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\"; ++ case 8: return \"nop\;nop\;cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\"; ++ case 9: return \"nop\;nop\;cfstrd%?\\t%V1, %0\"; + default: gcc_unreachable (); + } + }" + [(set_attr "type" "load1,store2, *,store2,load1, *, load1, *, *,store2") +- (set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4") ++ (set_attr "length" " 12, 12, 16, 16, 16, 12, 12, 16, 16, 12") + (set_attr "pool_range" " *, *, *, *, 252, *, 1020, *, *, *") + (set_attr "neg_pool_range" " *, *, *, *, 244, *, 1008, *, *, *") + (set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")] diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-eabi-ieee754-div.patch b/packages/gcc/gcc-4.1.2/arm-crunch-eabi-ieee754-div.patch new file mode 100644 index 0000000000..940f4a65ae --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-eabi-ieee754-div.patch @@ -0,0 +1,139 @@ +--- gcc-4.1.2/gcc/config/arm/ieee754-df-original.S 2007-06-25 10:22:06.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/ieee754-df.S 2007-06-25 10:27:17.000000000 +1000 +@@ -717,6 +717,10 @@ + cmn r4, #(53 + 1) + movle xl, #0 + bicle xh, xh, #0x7fffffff ++#ifdef __MAVERICK__ ++ cfmvdlr mvd0, xl ++ cfmvdhr mvd0, xh ++#endif + RETLDM "r4, r5, r6" le + + @ Find out proper shift value. +@@ -738,6 +742,10 @@ + adc xh, r2, xh, lsr r4 + orrs lr, lr, r3, lsl #1 + biceq xl, xl, r3, lsr #31 ++#ifdef __MAVERICK__ ++ cfmvdlr mvd0, xl ++ cfmvdhr mvd0, xh ++#endif + RETLDM "r4, r5, r6" + + @ shift result right of 21 to 31 bits, or left 11 to 1 bits after +@@ -752,6 +760,10 @@ + adc xh, xh, #0 + orrs lr, lr, r3, lsl #1 + biceq xl, xl, r3, lsr #31 ++#ifdef __MAVERICK__ ++ cfmvdlr mvd0, xl ++ cfmvdhr mvd0, xh ++#endif + RETLDM "r4, r5, r6" + + @ Shift value right of 32 to 64 bits, or 0 to 32 bits after a switch +@@ -766,6 +778,10 @@ + add xl, xl, r3, lsr #31 + orrs lr, lr, r3, lsl #1 + biceq xl, xl, r3, lsr #31 ++#ifdef __MAVERICK__ ++ cfmvdlr mvd0, xl ++ cfmvdhr mvd0, xh ++#endif + RETLDM "r4, r5, r6" + + @ One or both arguments are denormalized. +@@ -808,6 +824,10 @@ + eor xh, xh, yh + bic xh, xh, #0x7fffffff + mov xl, #0 ++#ifdef __MAVERICK__ ++ cfmvdlr mvd0, xl ++ cfmvdhr mvd0, xh ++#endif + RETLDM "r4, r5, r6" + + 1: @ One or both args are INF or NAN. +@@ -837,12 +857,20 @@ + orr xh, xh, #0x7f000000 + orr xh, xh, #0x00f00000 + mov xl, #0 ++#ifdef __MAVERICK__ ++ cfmvdlr mvd0, xl ++ cfmvdhr mvd0, xh ++#endif + RETLDM "r4, r5, r6" + + @ Return a quiet NAN. + LSYM(Lml_n): + orr xh, xh, #0x7f000000 + orr xh, xh, #0x00f80000 ++#ifdef __MAVERICK__ ++ cfmvdlr mvd0, xl ++ cfmvdhr mvd0, xh ++#endif + RETLDM "r4, r5, r6" + + FUNC_END aeabi_dmul +--- gcc-4.1.2/gcc/config/arm/ieee754-sf-original.S 2007-06-25 10:18:52.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/ieee754-sf.S 2007-06-25 10:40:25.000000000 +1000 +@@ -518,6 +518,9 @@ + @ Check if denormalized result is possible, otherwise return signed 0. + cmn r2, #(24 + 1) + bicle r0, r0, #0x7fffffff ++#ifdef __MAVERICK__ ++ cfmvsr mvf0, r0 ++#endif + RETc(le) + + @ Shift value right, round, etc. +@@ -530,6 +533,9 @@ + adc r0, r0, #0 + orrs r3, r3, ip, lsl #1 + biceq r0, r0, ip, lsr #31 ++#ifdef __MAVERICK__ ++ cfmvsr mvf0, r0 ++#endif + RET + + @ One or both arguments are denormalized. +@@ -567,6 +573,9 @@ + LSYM(Lml_z): + eor r0, r0, r1 + bic r0, r0, #0x7fffffff ++#ifdef __MAVERICK__ ++ cfmvsr mvf0, r0 ++#endif + RET + + 1: @ One or both args are INF or NAN. +@@ -595,12 +604,18 @@ + and r0, r0, #0x80000000 + orr r0, r0, #0x7f000000 + orr r0, r0, #0x00800000 ++#ifdef __MAVERICK__ ++ cfmvsr mvf0, r0 ++#endif + RET + + @ Return a quiet NAN. + LSYM(Lml_n): + orr r0, r0, #0x7f000000 + orr r0, r0, #0x00c00000 ++#ifdef __MAVERICK__ ++ cfmvsr mvf0, r0 ++#endif + RET + + FUNC_END aeabi_fmul +@@ -677,6 +692,9 @@ + adds r2, r2, #127 + rsbgts r3, r2, #255 + orrgt r0, r0, r2, lsl #23 ++#ifdef __MAVERICK__ ++ cfmvsr mvf0, r0 ++#endif + RETc(gt) + + orr r0, r0, #0x00800000 diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-eabi-ieee754.patch b/packages/gcc/gcc-4.1.2/arm-crunch-eabi-ieee754.patch new file mode 100644 index 0000000000..e4929fa20e --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-eabi-ieee754.patch @@ -0,0 +1,100 @@ +--- ../gcc-cross-4.1.2-r4-unpatched/gcc-4.1.2/gcc/config/arm/ieee754-df.S 2007-06-07 13:06:52.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/ieee754-df.S 2007-06-07 13:15:49.000000000 +1000 +@@ -42,8 +42,9 @@ + + + @ For FPA, float words are always big-endian. ++@ For MAVERICK, float words are always little-endian. + @ For VFP, floats words follow the memory system mode. +-#if defined(__VFP_FP__) && !defined(__ARMEB__) ++#if ((defined(__VFP_FP__) && !defined(__ARMEB__)) || defined(__MAVERICK__)) + #define xl r0 + #define xh r1 + #define yl r2 +@@ -451,8 +452,13 @@ + + orrs r2, r0, r1 + #if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if defined (__FPA_FP__) + mvfeqd f0, #0.0 + #endif ++#if defined (__MAVERICK__) ++ cfstrd mvd0, #0.0 ++#endif ++#endif + RETc(eq) + + #if !defined (__VFP_FP__) && !defined(__SOFTFP__) +@@ -473,8 +479,13 @@ + + orrs r2, r0, r1 + #if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if defined (__FPA_FP__) + mvfeqd f0, #0.0 + #endif ++#if defined (__MAVERICK__) ++ cfstrd mvd0, #0.0 ++#endif ++#endif + RETc(eq) + + #if !defined (__VFP_FP__) && !defined(__SOFTFP__) +@@ -526,8 +537,14 @@ + @ Legacy code expects the result to be returned in f0. Copy it + @ there as well. + LSYM(f0_ret): ++#if defined (__FPA_FP__) + stmfd sp!, {r0, r1} + ldfd f0, [sp], #8 ++#endif ++#if defined (__MAVERICK__) ++ cfmvdlr mvd0, xl ++ cfmvdhr mvd0, xh ++#endif + RETLDM + + #endif +--- ../gcc-cross-4.1.2-r4-unpatched/gcc-4.1.2/gcc/config/arm/ieee754-sf.S 2007-06-07 13:06:52.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/ieee754-sf.S 2007-06-07 13:21:43.000000000 +1000 +@@ -302,8 +302,13 @@ + + orrs r2, r0, r1 + #if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if defined (__FPA_FP__) + mvfeqs f0, #0.0 + #endif ++#if defined (__MAVERICK__) ++ cfmvsr mvf0, #0.0 ++#endif ++#endif + RETc(eq) + + mov r3, #0 +@@ -314,8 +319,13 @@ + + orrs r2, r0, r1 + #if !defined (__VFP_FP__) && !defined(__SOFTFP__) ++#if defined (__FPA_FP__) + mvfeqs f0, #0.0 + #endif ++#if defined (__MAVERICK__) ++ cfmvsr mvf0, #0.0 ++#endif ++#endif + RETc(eq) + + ands r3, ah, #0x80000000 @ sign bit in r3 +@@ -387,8 +397,13 @@ + #if !defined (__VFP_FP__) && !defined(__SOFTFP__) + + LSYM(f0_ret): ++#if defined (__FPA_FP__) + str r0, [sp, #-4]! + ldfs f0, [sp], #4 ++#endif ++#if defined (__MAVERICK__) ++ cfmvsr mvf0, r0 ++#endif + RETLDM + + #endif diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-eabi.patch b/packages/gcc/gcc-4.1.2/arm-crunch-eabi.patch new file mode 100644 index 0000000000..f8992ed499 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-eabi.patch @@ -0,0 +1,64 @@ +--- /home/hwilliams/original/gcc-4.1.2/gcc/config/arm/t-linux-eabi 2005-10-10 11:04:31.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/t-linux-eabi 2007-05-15 13:53:05.000000000 +1000 +@@ -1,11 +1,21 @@ + # These functions are included in shared libraries. + TARGET_LIBGCC2_CFLAGS = -fPIC ++TARGET_LIBGCC2_CFLAGS += -mcpu=ep9312 -mfpu=maverick ++LIBGCC2_DEBUG_CFLAGS = -g0 + + # We do not build a Thumb multilib for Linux because the definition of + # CLEAR_INSN_CACHE in linux-gas.h does not work in Thumb mode. + MULTILIB_OPTIONS = + MULTILIB_DIRNAMES = + ++LIB1ASMSRC = arm/lib1funcs.asm ++LIB1ASMFUNCS += _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx \ ++ _negdf2 _addsubdf3 _muldivdf3 _cmpdf2 _unorddf2 _fixdfsi _fixunsdfsi \ ++ _truncdfsf2 _negsf2 _addsubsf3 _muldivsf3 _cmpsf2 _unordsf2 \ ++ _fixsfsi _fixunssfsi ++ ++CRTSTUFF_T_CFLAGS += -mcpu=ep9312 -mfpu=maverick ++ + # Use a version of div0 which raises SIGFPE. + LIB1ASMFUNCS := $(filter-out _dvmd_tls,$(LIB1ASMFUNCS)) _dvmd_lnx + +diff -ruN arm/elf.h gcc-3.4.3/gcc/config/arm/elf.h +--- ../gcc-4.1.2-orig/gcc/config/arm/elf.h 2004-02-24 16:25:22.000000000 +0200 ++++ gcc-4.1.2/gcc/config/arm/elf.h 2005-02-10 00:31:28.000000000 +0200 +@@ -46,7 +46,7 @@ + + #ifndef SUBTARGET_ASM_FLOAT_SPEC + #define SUBTARGET_ASM_FLOAT_SPEC "\ +-%{mapcs-float:-mfloat}" ++%{mapcs-float:-mfloat} %{msoft-float:-mfpu=softfpa} %{mcpu=ep9312:-mfpu=maverick}" + #endif + + #ifndef ASM_SPEC +diff -ruN t-linux gcc-4.1.2/gcc/config/arm/t-linux +--- t-linux 2007-05-09 16:32:28.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/t-linux 2007-05-25 11:02:17.000000000 +1000 +@@ -1,19 +1,22 @@ + # Just for these, we omit the frame pointer since it makes such a big + # difference. It is then pointless adding debugging. + TARGET_LIBGCC2_CFLAGS = -fomit-frame-pointer -fPIC ++TARGET_LIBGCC2_CFLAGS += -mcpu=ep9312 -mfpu=maverick -mfloat-abi=softfp -D__MAVERICK__ + LIBGCC2_DEBUG_CFLAGS = -g0 + + LIB1ASMSRC = arm/lib1funcs.asm + LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx \ + _negdf2 _addsubdf3 _muldivdf3 _cmpdf2 _unorddf2 _fixdfsi _fixunsdfsi \ + _truncdfsf2 _negsf2 _addsubsf3 _muldivsf3 _cmpsf2 _unordsf2 \ +- _call_via_rX \ +- _fixsfsi _fixunssfsi _floatdidf _floatdisf ++ _fixsfsi _fixunssfsi + + # MULTILIB_OPTIONS = mhard-float/msoft-float + # MULTILIB_DIRNAMES = hard-float soft-float + + # EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o + ++# EXTRA_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o ++CRTSTUFF_T_CFLAGS += -mcpu=ep9312 -mfpu=maverick -mfloat-abi=softfp -D__MAVERICK__ ++ + # LIBGCC = stmp-multilib + # INSTALL_LIBGCC = install-multilib diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-floatsi-disable-single.patch b/packages/gcc/gcc-4.1.2/arm-crunch-floatsi-disable-single.patch new file mode 100644 index 0000000000..cdd52244a6 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-floatsi-disable-single.patch @@ -0,0 +1,38 @@ +--- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-25 12:12:39.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-25 12:16:13.000000000 +1000 +@@ -301,13 +301,14 @@ + ) + + ;; Convert Cirrus-SI to Cirrus-SF ++; appears to be buggy + (define_insn "cirrus_floatsisf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (float:SF (match_operand:SI 1 "s_register_operand" "r"))) + (clobber (match_scratch:DF 2 "=v"))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2" + [(set_attr "length" "8") + (set_attr "cirrus" "move")] + ) + +--- gcc-4.1.2/gcc/config/arm/arm.md-cfcvt 2007-06-25 12:16:53.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-25 12:18:20.000000000 +1000 +@@ -3125,14 +3125,15 @@ + + ;; Fixed <--> Floating conversion insns + ++;; Maverick Crunch floatsisf2 is buggy - see cirrus.md + (define_expand "floatsisf2" + [(set (match_operand:SF 0 "s_register_operand" "") + (float:SF (match_operand:SI 1 "s_register_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + " +- if (TARGET_MAVERICK) ++ if (TARGET_MAVERICK && 0) + { + emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1])); + DONE; + } + ") diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-floatsi-disable.patch b/packages/gcc/gcc-4.1.2/arm-crunch-floatsi-disable.patch new file mode 100644 index 0000000000..aa54ec3e04 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-floatsi-disable.patch @@ -0,0 +1,61 @@ +--- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-25 12:12:39.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-25 12:16:13.000000000 +1000 +@@ -301,21 +301,23 @@ + ) + + ;; Convert Cirrus-SI to Cirrus-SF ++; appears to be buggy + (define_insn "cirrus_floatsisf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (float:SF (match_operand:SI 1 "s_register_operand" "r"))) + (clobber (match_scratch:DF 2 "=v"))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2" + [(set_attr "length" "8") + (set_attr "cirrus" "move")] + ) + ++;appears to be buggy + (define_insn "cirrus_floatsidf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (float:DF (match_operand:SI 1 "s_register_operand" "r"))) + (clobber (match_scratch:DF 2 "=v"))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2" + [(set_attr "length" "8") + (set_attr "cirrus" "move")] +--- gcc-4.1.2/gcc/config/arm/arm.md-cfcvt 2007-06-25 12:16:53.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-25 12:18:20.000000000 +1000 +@@ -3125,24 +3125,26 @@ + + ;; Fixed <--> Floating conversion insns + ++;; Maverick Crunch floatsisf2 is buggy - see cirrus.md + (define_expand "floatsisf2" + [(set (match_operand:SF 0 "s_register_operand" "") + (float:SF (match_operand:SI 1 "s_register_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + " +- if (TARGET_MAVERICK) ++ if (TARGET_MAVERICK && 0) + { + emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1])); + DONE; + } + ") + ++;; Maverick Crunch floatsidf2 is buggy - see cirrus.md + (define_expand "floatsidf2" + [(set (match_operand:DF 0 "s_register_operand" "") + (float:DF (match_operand:SI 1 "s_register_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + " +- if (TARGET_MAVERICK) ++ if (TARGET_MAVERICK && 0) + { + emit_insn (gen_cirrus_floatsidf2 (operands[0], operands[1])); + DONE; diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-floatunsidf.patch b/packages/gcc/gcc-4.1.2/arm-crunch-floatunsidf.patch new file mode 100644 index 0000000000..2fe2254db9 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-floatunsidf.patch @@ -0,0 +1,37 @@ +--- gcc-4.1.2/gcc/config/arm/ieee754-df-original.S 2007-06-25 14:05:35.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/ieee754-df.S 2007-06-25 14:08:03.000000000 +1000 +@@ -382,6 +382,8 @@ + FUNC_END aeabi_dadd + FUNC_END adddf3 + ++#ifndef __MAVERICK__ /* THIS IS A BAD HACK */ ++ + ARM_FUNC_START floatunsidf + ARM_FUNC_ALIAS aeabi_ui2d floatunsidf + +@@ -401,8 +403,14 @@ + FUNC_END aeabi_ui2d + FUNC_END floatunsidf + ++#endif ++ + ARM_FUNC_START floatsidf + ARM_FUNC_ALIAS aeabi_i2d floatsidf ++#ifdef __MAVERICK__ /* THIS IS A BAD HACK */ ++ARM_FUNC_ALIAS floatunsidf floatsidf ++ARM_FUNC_ALIAS aeabi_ui2d floatsidf ++#endif + + teq r0, #0 + moveq r1, #0 +@@ -418,6 +426,10 @@ + mov xh, #0 + b LSYM(Lad_l) + ++#ifdef __MAVERICK__ /* THIS IS A BAD HACK */ ++ FUNC_END aeabi_ui2d floatsidf ++ FUNC_END floatunsidf floatsidf ++#endif + FUNC_END aeabi_i2d + FUNC_END floatsidf + diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-fp_consts.patch b/packages/gcc/gcc-4.1.2/arm-crunch-fp_consts.patch new file mode 100644 index 0000000000..5f289bbebe --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-fp_consts.patch @@ -0,0 +1,13 @@ +--- gcc-4.1.2/gcc/config/arm/arm.c-original 2007-06-12 16:17:14.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-06-12 16:17:28.000000000 +1000 +@@ -5218,7 +5218,9 @@ + int i; + REAL_VALUE_TYPE r; + ++ if (TARGET_MAVERICK) ++ fp_consts_inited = 0; +- if (TARGET_VFP) ++ else if (TARGET_VFP) + fp_consts_inited = 1; + else + fp_consts_inited = 8; diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-neg.patch b/packages/gcc/gcc-4.1.2/arm-crunch-neg.patch new file mode 100644 index 0000000000..f14ae0190e --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-neg.patch @@ -0,0 +1,30 @@ +WARNING: adding this patch causes copysign1.c and mzero3.c to fail... +diff -urN gcc-4.1.2/gcc/config/arm/arm.md-original gcc-4.1.2/gcc/config/arm/arm.md +--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-12 12:48:14.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-12 12:49:53.000000000 +1000 +@@ -2985,14 +2985,14 @@ + (define_expand "negsf2" + [(set (match_operand:SF 0 "s_register_operand" "") + (neg:SF (match_operand:SF 1 "s_register_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "" + ) + + (define_expand "negdf2" + [(set (match_operand:DF 0 "s_register_operand" "") + (neg:DF (match_operand:DF 1 "s_register_operand" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "") + + ;; abssi2 doesn't really clobber the condition codes if a different register +@@ -4097,7 +4097,7 @@ + [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m") + (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))] + "TARGET_ARM +- && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP)) ++ && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP || TARGET_MAVERICK)) + && !TARGET_IWMMXT" + "* + switch (which_alternative) diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-neg2.patch b/packages/gcc/gcc-4.1.2/arm-crunch-neg2.patch new file mode 100644 index 0000000000..4fd91f3215 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-neg2.patch @@ -0,0 +1,25 @@ +--- gcc-4.1.2/gcc/config/arm/cirrus.md-original 2007-06-12 17:01:24.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-12 17:03:26.000000000 +1000 +@@ -255,18 +256,20 @@ + [(set_attr "cirrus" "normal")] + ) + ++;; appears to be buggy: neg 0 != -0 + (define_insn "*cirrus_negsf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (neg:SF (match_operand:SF 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfnegs%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) + ++;; appears to be buggy: neg 0 != -0 + (define_insn "*cirrus_negdf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (neg:DF (match_operand:DF 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfnegd%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-offset.patch b/packages/gcc/gcc-4.1.2/arm-crunch-offset.patch new file mode 100644 index 0000000000..3a40f0d224 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-offset.patch @@ -0,0 +1,20 @@ +--- gcc-4.1.2/gcc/config/arm/arm.c-original 2007-06-12 14:46:20.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-06-12 14:48:06.000000000 +1000 +@@ -3460,7 +3460,7 @@ + + use_ldrd = (TARGET_LDRD + && (mode == DImode +- || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP)))); ++ || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_MAVERICK || TARGET_VFP)))); + + if (code == POST_INC || code == PRE_DEC + || ((code == PRE_INC || code == POST_DEC) +@@ -3960,7 +3960,7 @@ + /* VFP addressing modes actually allow greater offsets, but for + now we just stick with the lowest common denominator. */ + if (mode == DImode +- || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode)) ++ || ((TARGET_SOFT_FLOAT || TARGET_MAVERICK || TARGET_VFP) && mode == DFmode)) + { + low_n = n & 0x0f; + n &= ~0x0f; diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-predicates.patch b/packages/gcc/gcc-4.1.2/arm-crunch-predicates.patch new file mode 100644 index 0000000000..4841ff8178 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-predicates.patch @@ -0,0 +1,20 @@ +diff -urN gcc-4.1.2/gcc/config/arm/predicates.md ../../../../old-tmp/work/arm-oabi-angstrom-linux/gcc-cross-4.1.2-backup/gcc-4.1.2/gcc/config/arm/predicates.md +--- gcc-4.1.2/gcc/config/arm/predicates.md 2005-09-11 17:38:02.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/predicates.md 2007-05-30 12:15:54.000000000 +1000 +@@ -171,8 +171,14 @@ + (match_code "eq,ne")) + + ;; True for comparisons other than LTGT or UNEQ. ++(define_special_predicate "arm_comparison_operator" ++; (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt")) ;; original - no LTGT or UNEQ ++; (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltgt,ltu,unordered,ordered,uneq,unlt,unle,unge,ungt")) ;; everything? ++;; True for comparisons other than GE, GEU, UNLT, unordered or ordered. - Cirrus Version - must include ge? +-(define_special_predicate "arm_comparison_operator" ++;(define_special_predicate "arm_comparison_operator" +- (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt")) ++(match_code "eq,ne,le,lt,ge,geu,gt,gtu,leu,ltgt,ltu,uneq,unle,unge,ungt")) ;; bad codes removed? ++;(match_code "eq,ne,le,lt,gt,gtu,leu,ltgt,ltu,uneq,unle,unge,ungt")) ;; bad codes removed + ge / geu removed ++ + + (define_special_predicate "minmax_operator" + (and (match_code "smin,smax,umin,umax") diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-predicates2.patch b/packages/gcc/gcc-4.1.2/arm-crunch-predicates2.patch new file mode 100644 index 0000000000..3e01158fe1 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-predicates2.patch @@ -0,0 +1,10 @@ +--- gcc-4.1.2/gcc/config/arm/predicates.md-original 2007-06-13 12:25:35.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/predicates.md 2007-06-13 12:25:42.000000000 +1000 +@@ -206,7 +206,6 @@ + || mode == CC_DEQmode + || mode == CC_DLEmode + || mode == CC_DLTmode +- || mode == CC_DGEmode + || mode == CC_DGTmode + || mode == CC_DLEUmode + || mode == CC_DLTUmode diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-predicates3.patch b/packages/gcc/gcc-4.1.2/arm-crunch-predicates3.patch new file mode 100644 index 0000000000..99e1e6c88c --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-predicates3.patch @@ -0,0 +1,116 @@ +diff -urN ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/arm.md gcc-4.1.2/gcc/config/arm/arm.md +--- ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/arm.md 2007-06-14 11:50:53.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-14 11:43:17.000000000 +1000 +@@ -7488,6 +7488,22 @@ + arm_compare_op1);" + ) + ++;(define_expand "suneq" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (uneq:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" ++; "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, ++; arm_compare_op1);" ++;) ++ ++;(define_expand "sltgt" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ltgt:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" ++; "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, ++; arm_compare_op1);" ++;) ++ + ;;; DO NOT add patterns for SUNEQ or SLTGT, these can't be represented with + ;;; simple ARM instructions. + ; +@@ -10284,13 +10284,73 @@ + "TARGET_ARM && arm_arch5e" + "pld\\t%a0") + ++;; Special predication pattern for Maverick Crunch floating-point ++ ++(define_cond_exec ++ [(match_operator 0 "maverick_comparison_operator" ++ [(match_operand:CCFP 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++;; Special predication pattern for Maverick Crunch - !CCFP ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_NOOV 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_Z 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_SWP 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_C 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_N 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ + ;; General predication pattern + + (define_cond_exec + [(match_operator 0 "arm_comparison_operator" + [(match_operand 1 "cc_register" "") + (const_int 0)])] +- "TARGET_ARM" ++ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" + "" + ) + +diff -urN ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/predicates.md gcc-4.1.2/gcc/config/arm/predicates.md +--- ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/predicates.md 2005-09-11 17:38:02.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/predicates.md 2007-06-14 11:46:13.000000000 +1000 +@@ -172,7 +172,11 @@ + + ;; True for comparisons other than LTGT or UNEQ. + (define_special_predicate "arm_comparison_operator" + (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt")) ++ ++;; True for comparisons other than GE, GEU, UNLT, UNORDERED or ORDERED - TODO add LTGT and UNEQ - needs extra support elsewhere ++(define_special_predicate "maverick_comparison_operator" ++(match_code "eq,ne,le,lt,gt,gtu,leu,ltu,unle,unge,ungt")) + + (define_special_predicate "minmax_operator" + (and (match_code "smin,smax,umin,umax") diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-predicates4-no_cond_exec.patch b/packages/gcc/gcc-4.1.2/arm-crunch-predicates4-no_cond_exec.patch new file mode 100644 index 0000000000..9272b304cf --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-predicates4-no_cond_exec.patch @@ -0,0 +1,196 @@ +diff -urN ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/arm.md gcc-4.1.2/gcc/config/arm/arm.md +--- ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/arm.md 2007-06-14 11:50:53.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-14 11:43:17.000000000 +1000 +@@ -7488,6 +7488,22 @@ + arm_compare_op1);" + ) + ++;(define_expand "suneq" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (uneq:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" ++; "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, ++; arm_compare_op1);" ++;) ++ ++;(define_expand "sltgt" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ltgt:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" ++; "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, ++; arm_compare_op1);" ++;) ++ + ;;; DO NOT add patterns for SUNEQ or SLTGT, these can't be represented with + ;;; simple ARM instructions. + ; +@@ -10284,13 +10284,153 @@ + "TARGET_ARM && arm_arch5e" + "pld\\t%a0") + ++;; Special predication pattern for Maverick Crunch floating-point ++ ++;(define_cond_exec ++; [(match_operator 0 "maverick_comparison_operator" ++; [(match_operand:CCFP 1 "cc_register" "") ++; (const_int 0)])] ++; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++; "" ++;) ++ ++;; Special predication pattern for Maverick Crunch - !CCFP ++ ++;(define_cond_exec ++; [(match_operator 0 "arm_comparison_operator" ++; [(match_operand:CC_NOOV 1 "cc_register" "") ++; (const_int 0)])] ++; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++; "" ++;) ++ ++;(define_cond_exec ++; [(match_operator 0 "arm_comparison_operator" ++; [(match_operand:CC_Z 1 "cc_register" "") ++; (const_int 0)])] ++; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++; "" ++;) ++ ++;(define_cond_exec ++; [(match_operator 0 "arm_comparison_operator" ++; [(match_operand:CC_SWP 1 "cc_register" "") ++; (const_int 0)])] ++; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++; "" ++;) ++ ++;(define_cond_exec ++; [(match_operator 0 "arm_comparison_operator" ++; [(match_operand:CC_DNE 1 "cc_register" "") ++; (const_int 0)])] ++; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++; "" ++;) ++ ++;(define_cond_exec ++; [(match_operator 0 "arm_comparison_operator" ++; [(match_operand:CC_DEQ 1 "cc_register" "") ++; (const_int 0)])] ++; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++; "" ++;) ++ ++;(define_cond_exec ++; [(match_operator 0 "arm_comparison_operator" ++; [(match_operand:CC_DLE 1 "cc_register" "") ++; (const_int 0)])] ++; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++; "" ++;) ++ ++;(define_cond_exec ++; [(match_operator 0 "arm_comparison_operator" ++; [(match_operand:CC_DLT 1 "cc_register" "") ++; (const_int 0)])] ++; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++; "" ++;) ++ ++;(define_cond_exec ++; [(match_operator 0 "arm_comparison_operator" ++; [(match_operand:CC_DGE 1 "cc_register" "") ++; (const_int 0)])] ++; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++; "" ++;) ++ ++;(define_cond_exec ++; [(match_operator 0 "arm_comparison_operator" ++; [(match_operand:CC_DGT 1 "cc_register" "") ++; (const_int 0)])] ++; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++; "" ++;) ++ ++;(define_cond_exec ++; [(match_operator 0 "arm_comparison_operator" ++; [(match_operand:CC_DLEU 1 "cc_register" "") ++; (const_int 0)])] ++; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++; "" ++;) ++ ++;(define_cond_exec ++; [(match_operator 0 "arm_comparison_operator" ++; [(match_operand:CC_DLTU 1 "cc_register" "") ++; (const_int 0)])] ++; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++; "" ++;) ++ ++;(define_cond_exec ++; [(match_operator 0 "arm_comparison_operator" ++; [(match_operand:CC_DGEU 1 "cc_register" "") ++; (const_int 0)])] ++; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++; "" ++;) ++ ++;(define_cond_exec ++; [(match_operator 0 "arm_comparison_operator" ++; [(match_operand:CC_DGTU 1 "cc_register" "") ++; (const_int 0)])] ++; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++; "" ++;) ++ ++;(define_cond_exec ++; [(match_operator 0 "arm_comparison_operator" ++; [(match_operand:CC_C 1 "cc_register" "") ++; (const_int 0)])] ++; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++; "" ++;) ++ ++;(define_cond_exec ++; [(match_operator 0 "arm_comparison_operator" ++; [(match_operand:CC_N 1 "cc_register" "") ++; (const_int 0)])] ++; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++; "" ++;) ++ ++(define_cond_exec ++ [(match_operator 0 "maverick_comparison_operator" ++ [(match_operand:CC 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ + ;; General predication pattern + + (define_cond_exec + [(match_operator 0 "arm_comparison_operator" + [(match_operand 1 "cc_register" "") + (const_int 0)])] +- "TARGET_ARM" ++ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" + "" + ) + +diff -urN ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/predicates.md gcc-4.1.2/gcc/config/arm/predicates.md +--- ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/predicates.md 2005-09-11 17:38:02.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/predicates.md 2007-06-14 11:46:13.000000000 +1000 +@@ -172,7 +172,11 @@ + + ;; True for comparisons other than LTGT or UNEQ. + (define_special_predicate "arm_comparison_operator" + (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt")) ++ ++;; True for comparisons other than GE, GEU, UNLT, UNORDERED or ORDERED - TODO add LTGT and UNEQ - needs extra support elsewhere ++(define_special_predicate "maverick_comparison_operator" ++(match_code "eq,ne,le,lt,gt,gtu,leu,ltu,unle,unge,ungt")) + + (define_special_predicate "minmax_operator" + (and (match_code "smin,smax,umin,umax") diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-predicates4.patch b/packages/gcc/gcc-4.1.2/arm-crunch-predicates4.patch new file mode 100644 index 0000000000..3327dd5d37 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-predicates4.patch @@ -0,0 +1,196 @@ +diff -urN ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/arm.md gcc-4.1.2/gcc/config/arm/arm.md +--- ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/arm.md 2007-06-14 11:50:53.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-14 11:43:17.000000000 +1000 +@@ -7488,6 +7488,22 @@ + arm_compare_op1);" + ) + ++;(define_expand "suneq" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (uneq:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" ++; "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, ++; arm_compare_op1);" ++;) ++ ++;(define_expand "sltgt" ++; [(set (match_operand:SI 0 "s_register_operand" "") ++; (ltgt:SI (match_dup 1) (const_int 0)))] ++; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_MAVERICK)" ++; "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, ++; arm_compare_op1);" ++;) ++ + ;;; DO NOT add patterns for SUNEQ or SLTGT, these can't be represented with + ;;; simple ARM instructions. + ; +@@ -10284,13 +10284,153 @@ + "TARGET_ARM && arm_arch5e" + "pld\\t%a0") + ++;; Special predication pattern for Maverick Crunch floating-point ++ ++(define_cond_exec ++ [(match_operator 0 "maverick_comparison_operator" ++ [(match_operand:CCFP 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++;; Special predication pattern for Maverick Crunch - !CCFP ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_NOOV 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_Z 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_SWP 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_DNE 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_DEQ 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_DLE 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_DLT 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_DGE 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_DGT 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_DLEU 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_DLTU 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_DGEU 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_DGTU 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_C 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC_N 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ ++(define_cond_exec ++ [(match_operator 0 "arm_comparison_operator" ++ [(match_operand:CC 1 "cc_register" "") ++ (const_int 0)])] ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "" ++) ++ + ;; General predication pattern + + (define_cond_exec + [(match_operator 0 "arm_comparison_operator" + [(match_operand 1 "cc_register" "") + (const_int 0)])] +- "TARGET_ARM" ++ "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" + "" + ) + +diff -urN ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/predicates.md gcc-4.1.2/gcc/config/arm/predicates.md +--- ../gcc-cross-4.1.2-r4/gcc-4.1.2/gcc/config/arm/predicates.md 2005-09-11 17:38:02.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/predicates.md 2007-06-14 11:46:13.000000000 +1000 +@@ -172,7 +172,11 @@ + + ;; True for comparisons other than LTGT or UNEQ. + (define_special_predicate "arm_comparison_operator" + (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,ordered,unlt,unle,unge,ungt")) ++ ++;; True for comparisons other than GE, GEU, UNLT, UNORDERED or ORDERED - TODO add LTGT and UNEQ - needs extra support elsewhere ++(define_special_predicate "maverick_comparison_operator" ++(match_code "eq,ne,le,lt,gt,gtu,leu,ltu,unle,unge,ungt")) + + (define_special_predicate "minmax_operator" + (and (match_code "smin,smax,umin,umax") diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-saveregs.patch b/packages/gcc/gcc-4.1.2/arm-crunch-saveregs.patch new file mode 100644 index 0000000000..531ae86610 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-saveregs.patch @@ -0,0 +1,153 @@ +diff -ruN /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.c gcc-4.1.2/gcc/config/arm/arm.c +--- /home/hwilliams/openembedded/build/tmp/work/ep9312-angstrom-linux-gnueabi/gcc-cross-4.1.2-r0/gcc-4.1.2/gcc/config/arm/arm.c 2007-05-09 16:32:29.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.c 2007-05-15 09:39:41.000000000 +1000 +@@ -426,7 +435,7 @@ + #define FL_STRONG (1 << 8) /* StrongARM */ + #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ + #define FL_XSCALE (1 << 10) /* XScale */ +-#define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */ ++#define FL_CIRRUS (1 << 11) /* Cirrus Crunch coprocessor. */ + #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds + media instructions. */ + #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */ +@@ -490,7 +499,7 @@ + /* Nonzero if this chip is a StrongARM. */ + int arm_tune_strongarm = 0; + +-/* Nonzero if this chip is a Cirrus variant. */ ++/* Nonzero if this chip supports Cirrus Crunch coprocessor. */ + int arm_arch_cirrus = 0; + + /* Nonzero if this chip supports Intel Wireless MMX technology. */ +@@ -1184,7 +1193,8 @@ + else + */ + if (arm_arch_cirrus) +- arm_fpu_arch = FPUTYPE_MAVERICK; ++ /* Cirrus crunch coprocessor still requires soft-float division. */ ++ arm_fpu_arch = FPUTYPE_MAVERICK; + else + arm_fpu_arch = FPUTYPE_FPA_EMU2; + #endif +@@ -1567,6 +1577,9 @@ + if (regs_ever_live[regno] && !call_used_regs[regno]) + return 0; + ++ if (TARGET_MAVERICK) ++ return 0; ++ + if (TARGET_REALLY_IWMMXT) + for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++) + if (regs_ever_live[regno] && ! call_used_regs [regno]) +@@ -9775,7 +9886,19 @@ + /* This variable is for the Virtual Frame Pointer, not VFP regs. */ + int vfp_offset = offsets->frame; + +- if (arm_fpu_arch == FPUTYPE_FPA_EMU2) ++ if (arm_fpu_arch == FPUTYPE_MAVERICK) ++ { ++ for (reg = LAST_CIRRUS_FP_REGNUM; reg >= FIRST_CIRRUS_FP_REGNUM; reg--) ++ if (regs_ever_live[reg] && !call_used_regs[reg]) ++ { ++ floats_offset += 8; /* more problems - futaris? */ ++ /* if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1) */ ++ asm_fprintf (f, "\tnop\n"); ++ asm_fprintf (f, "\tcfldrd\tmvd%d, [%r, #-%d]\n", ++ reg - FIRST_CIRRUS_FP_REGNUM, FP_REGNUM, floats_offset - vfp_offset); ++ } ++ } ++ else if (arm_fpu_arch == FPUTYPE_FPA_EMU2) + { + for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) + if (regs_ever_live[reg] && !call_used_regs[reg]) +@@ -9924,7 +10047,18 @@ + output_add_immediate (operands); + } + +- if (arm_fpu_arch == FPUTYPE_FPA_EMU2) ++ if (arm_fpu_arch == FPUTYPE_MAVERICK) ++ { /* order changed - futaris */ ++ for (reg = FIRST_CIRRUS_FP_REGNUM; reg <= LAST_CIRRUS_FP_REGNUM; reg++) ++ if (regs_ever_live[reg] && !call_used_regs[reg]) ++ { ++ /* if (TARGET_CIRRUS_D0 || TARGET_CIRRUS_D1) */ ++ asm_fprintf (f, "\tnop\n"); ++ asm_fprintf (f, "\tcfldrd\tmvd%u, [%r], #8\n", ++ reg - FIRST_CIRRUS_FP_REGNUM, SP_REGNUM); ++ } /* reg problems - futaris */ ++ } ++ else if (arm_fpu_arch == FPUTYPE_FPA_EMU2) + { + for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) + if (regs_ever_live[reg] && !call_used_regs[reg]) +@@ -10429,9 +10563,19 @@ + if (! IS_VOLATILE (func_type)) + { ++ /* Space for saved MAVERICK registers. */ ++ if (arm_fpu_arch == FPUTYPE_MAVERICK) ++ { ++ for (regno = FIRST_CIRRUS_FP_REGNUM; regno <= LAST_CIRRUS_FP_REGNUM; regno++) ++ if (regs_ever_live[regno] && !call_used_regs[regno]) ++ saved += 8; // 8 in 3.4.3 patch - futaris; ++ } ++ else + /* Space for saved FPA registers. */ ++ { + for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) + if (regs_ever_live[regno] && ! call_used_regs[regno]) + saved += 12; ++ } + + /* Space for saved VFP registers. */ + if (TARGET_HARD_FLOAT && TARGET_VFP) +@@ -10739,7 +10882,19 @@ + + /* Save any floating point call-saved registers used by this + function. */ +- if (arm_fpu_arch == FPUTYPE_FPA_EMU2) ++ if (arm_fpu_arch == FPUTYPE_MAVERICK) ++ { ++ for (reg = LAST_CIRRUS_FP_REGNUM; reg >= FIRST_CIRRUS_FP_REGNUM; reg--) ++ if (regs_ever_live[reg] && !call_used_regs[reg]) ++ { ++ insn = gen_rtx_PRE_DEC (DFmode, stack_pointer_rtx); /* think these causes problems */ ++ insn = gen_rtx_MEM (DFmode, insn); ++ insn = emit_insn (gen_rtx_SET (VOIDmode, insn, ++ gen_rtx_REG (DFmode, reg))); ++ RTX_FRAME_RELATED_P (insn) = 1; saved_regs += 8; /* added by futaris */ ++ } ++ } ++ else if (arm_fpu_arch == FPUTYPE_FPA_EMU2) + { + for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) + if (regs_ever_live[reg] && !call_used_regs[reg]) +@@ -15179,6 +15331,9 @@ + if (IS_FPA_REGNUM (regno)) + return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM; + ++ if (IS_CIRRUS_REGNUM (regno)) ++ return 28 + regno - FIRST_CIRRUS_FP_REGNUM; ++ + if (IS_VFP_REGNUM (regno)) + return 64 + regno - FIRST_VFP_REGNUM; + +--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-28 15:42:36.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-28 15:42:48.000000000 +1000 +@@ -9800,7 +9800,7 @@ + return arm_output_epilogue (next_nonnote_insn (insn)); + " + ;; Length is absolute worst case +- [(set_attr "length" "44") ++ [(set_attr "length" "108") + (set_attr "type" "block") + ;; We don't clobber the conditions, but the potential length of this + ;; operation is sufficient to make conditionalizing the sequence +@@ -9818,7 +9818,7 @@ + return thumb_unexpanded_epilogue (); + " + ; Length is absolute worst case +- [(set_attr "length" "44") ++ [(set_attr "length" "108") + (set_attr "type" "block") + ;; We don't clobber the conditions, but the potential length of this + ;; operation is sufficient to make conditionalizing the sequence diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-scc.patch b/packages/gcc/gcc-4.1.2/arm-crunch-scc.patch new file mode 100644 index 0000000000..d1330f2543 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-scc.patch @@ -0,0 +1,38 @@ +--- gcc-4.1.2/gcc/config/arm/arm.md-original 2007-06-13 12:38:06.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-13 12:40:07.000000000 +1000 +@@ -7375,7 +7375,7 @@ + (define_expand "sge" + [(set (match_operand:SI 0 "s_register_operand" "") + (ge:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" ++ "TARGET_ARM" + "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" + ) + +@@ -7434,7 +7434,7 @@ + (define_expand "sunordered" + [(set (match_operand:SI 0 "s_register_operand" "") + (unordered:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7442,7 +7442,7 @@ + (define_expand "sordered" + [(set (match_operand:SI 0 "s_register_operand" "") + (ordered:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0, + arm_compare_op1);" + ) +@@ -7467,7 +7467,7 @@ + (define_expand "sunlt" + [(set (match_operand:SI 0 "s_register_operand" "") + (unlt:SI (match_dup 1) (const_int 0)))] +- "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP || TARGET_MAVERICK)" + "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, + arm_compare_op1);" + ) diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-truncsi-disable-new.patch b/packages/gcc/gcc-4.1.2/arm-crunch-truncsi-disable-new.patch new file mode 100644 index 0000000000..6dea43fa7c --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-truncsi-disable-new.patch @@ -0,0 +1,33 @@ +--- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-25 12:46:22.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-25 12:46:41.000000000 +1000 +@@ -337,13 +337,14 @@ + "cfcvt64d%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")]) + ++; appears to be buggy + (define_insn "cirrus_truncsfsi2" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register" "v")))) + (clobber (match_scratch:DF 2 "=v"))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" + [(set_attr "length" "8") + (set_attr "cirrus" "normal")] + ) + +--- gcc-4.1.2/gcc/config/arm/arm.md-cfcvt 2007-06-25 12:46:56.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-25 12:48:08.000000000 +1000 +@@ -3151,10 +3151,11 @@ + } + ") + ++; appears to be buggy for MAVERICK + (define_expand "fix_truncsfsi2" + [(set (match_operand:SI 0 "s_register_operand" "") + (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))] +- "TARGET_ARM && TARGET_HARD_FLOAT" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + " + if (TARGET_MAVERICK) + { diff --git a/packages/gcc/gcc-4.1.2/arm-crunch-truncsi-disable.patch b/packages/gcc/gcc-4.1.2/arm-crunch-truncsi-disable.patch new file mode 100644 index 0000000000..a5d791a0a4 --- /dev/null +++ b/packages/gcc/gcc-4.1.2/arm-crunch-truncsi-disable.patch @@ -0,0 +1,56 @@ +--- gcc-4.1.2/gcc/config/arm/cirrus.md-cfcvt 2007-06-25 12:46:22.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-25 12:46:41.000000000 +1000 +@@ -337,21 +337,23 @@ + "cfcvt64d%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")]) + ++; appears to be buggy + (define_insn "cirrus_truncsfsi2" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register" "v")))) + (clobber (match_scratch:DF 2 "=v"))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" + [(set_attr "length" "8") + (set_attr "cirrus" "normal")] + ) + ++; appears to be buggy + (define_insn "cirrus_truncdfsi2" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (fix:SI (fix:DF (match_operand:DF 1 "cirrus_fp_register" "v")))) + (clobber (match_scratch:DF 2 "=v"))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" + [(set_attr "length" "8") + (set_attr "cirrus" "normal")] +--- gcc-4.1.2/gcc/config/arm/arm.md-cfcvt 2007-06-25 12:46:56.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-25 12:48:08.000000000 +1000 +@@ -3151,10 +3151,11 @@ + } + ") + ++; appears to be buggy for MAVERICK + (define_expand "fix_truncsfsi2" + [(set (match_operand:SI 0 "s_register_operand" "") + (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))] +- "TARGET_ARM && TARGET_HARD_FLOAT" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + " + if (TARGET_MAVERICK) + { +@@ -3167,10 +3168,11 @@ + } + ") + ++; appears to be buggy for MAVERICK + (define_expand "fix_truncdfsi2" + [(set (match_operand:SI 0 "s_register_operand" "") + (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))] +- "TARGET_ARM && TARGET_HARD_FLOAT" ++ "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + " + if (TARGET_MAVERICK) + { |