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authorSylvain Miermont <smiermont@semtech.com>2013-09-19 15:46:06 +0200
committerSylvain Miermont <smiermont@semtech.com>2013-10-23 14:03:05 +0200
commitb922932d1c9869d82042b600db2382d8c15f63dc (patch)
treeb97b83a74f5b3faadb674867f6cc004b8426a8a9 /libloragw/library.cfg
parent68b8b7a70d9104888997174506fbbaa0abb12a4c (diff)
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Beta 7 (beta6 skipped)v1.b7
- API: change memory allocation for payload, they are now part of the struct for TX/RX, no need to malloc/free - reduced number of SPI transactions to fetch a packet (improved number a packets par second that can be downloaded from gateway) - streamlined build process, main target is now a static library: libloragw.a - All RX chains can use any of the two radios now - FSK is available and working in TX and RX (variable length mode) - Calibrated RSSI for FSK - lgw_connect now check the CHIP_ID - Added a license file and a changelog - Added a function returning a version string to allow identification of the version/options once compiled
Diffstat (limited to 'libloragw/library.cfg')
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diff --git a/libloragw/library.cfg b/libloragw/library.cfg
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+# / _____) _ | |
+# ( (____ _____ ____ _| |_ _____ ____| |__
+# \____ \| ___ | (_ _) ___ |/ ___) _ \
+# _____) ) ____| | | || |_| ____( (___| | | |
+# (______/|_____)_|_|_| \__)_____)\____)_| |_|
+# ©2013 Semtech-Cycleo
+#
+# Description:
+# Lora gateway Hardware Abstraction Layer library configuration
+
+
+# Set the DEBUG_* to 1 to activate debug mode in individual modules.
+# Warning: that makes the module *very verbose*, do not use for production
+FLAG_AUX= -D DEBUG_AUX=0
+FLAG_SPI= -D DEBUG_SPI=0
+FLAG_REG= -D DEBUG_REG=0
+FLAG_HAL= -D DEBUG_HAL=0
+
+# The flags bellow define which physical link to the nano board will be used
+# Pick one and comment the other(s)
+
+# Pcduino native SPI (Linux device in /dev)
+LGW_PHY= native
+
+# FTDI SPI-over-USB bridge
+#LGW_PHY= ftdi