From b922932d1c9869d82042b600db2382d8c15f63dc Mon Sep 17 00:00:00 2001 From: Sylvain Miermont Date: Thu, 19 Sep 2013 15:46:06 +0200 Subject: Beta 7 (beta6 skipped) - API: change memory allocation for payload, they are now part of the struct for TX/RX, no need to malloc/free - reduced number of SPI transactions to fetch a packet (improved number a packets par second that can be downloaded from gateway) - streamlined build process, main target is now a static library: libloragw.a - All RX chains can use any of the two radios now - FSK is available and working in TX and RX (variable length mode) - Calibrated RSSI for FSK - lgw_connect now check the CHIP_ID - Added a license file and a changelog - Added a function returning a version string to allow identification of the version/options once compiled --- libloragw/library.cfg | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 libloragw/library.cfg (limited to 'libloragw/library.cfg') diff --git a/libloragw/library.cfg b/libloragw/library.cfg new file mode 100644 index 0000000..ac24416 --- /dev/null +++ b/libloragw/library.cfg @@ -0,0 +1,26 @@ +# / _____) _ | | +# ( (____ _____ ____ _| |_ _____ ____| |__ +# \____ \| ___ | (_ _) ___ |/ ___) _ \ +# _____) ) ____| | | || |_| ____( (___| | | | +# (______/|_____)_|_|_| \__)_____)\____)_| |_| +# ©2013 Semtech-Cycleo +# +# Description: +# Lora gateway Hardware Abstraction Layer library configuration + + +# Set the DEBUG_* to 1 to activate debug mode in individual modules. +# Warning: that makes the module *very verbose*, do not use for production +FLAG_AUX= -D DEBUG_AUX=0 +FLAG_SPI= -D DEBUG_SPI=0 +FLAG_REG= -D DEBUG_REG=0 +FLAG_HAL= -D DEBUG_HAL=0 + +# The flags bellow define which physical link to the nano board will be used +# Pick one and comment the other(s) + +# Pcduino native SPI (Linux device in /dev) +LGW_PHY= native + +# FTDI SPI-over-USB bridge +#LGW_PHY= ftdi -- cgit v1.2.3