diff options
| author | Matthieu Leurent <mleurent@semtech.com> | 2015-03-11 20:15:40 +0100 |
|---|---|---|
| committer | Matthieu Leurent <mleurent@semtech.com> | 2015-03-11 20:15:40 +0100 |
| commit | 45be5ff473ad1f39829bfcebc641201ae46c1c80 (patch) | |
| tree | 5d0720fb06e9bb35ce2c8c2f0749b41a7b42c41a | |
| parent | be5c8ac770bc5b142e2c6a47702d9ac653141371 (diff) | |
| download | lora_gateway-45be5ff473ad1f39829bfcebc641201ae46c1c80.tar.gz lora_gateway-45be5ff473ad1f39829bfcebc641201ae46c1c80.tar.bz2 lora_gateway-45be5ff473ad1f39829bfcebc641201ae46c1c80.zip | |
- Added support for Kerlink 868 27dBm gateway
- Updated global_conf.eu868.json (in packet logger) to new LoRaWAN frequency plan
- Added version numbers to AGC, arbiter and calibration firmware (those versions are checked at startup)
- Added test_loragw_cal to test radio calibrations
- Fixed minor bug in error coverage in register read/write functions
/!\ warning: Kerlink 868 27dBm gateway includes a FPGA that MUST be programmed before running any application
| -rw-r--r-- | VERSION | 2 | ||||
| -rw-r--r-- | libloragw/Makefile | 12 | ||||
| -rw-r--r-- | libloragw/inc/loragw_hal.h | 2 | ||||
| -rw-r--r-- | libloragw/library.cfg | 1 | ||||
| -rw-r--r-- | libloragw/src/agc_fw.var | 350 | ||||
| -rw-r--r-- | libloragw/src/arb_fw.var | 98 | ||||
| -rw-r--r-- | libloragw/src/cal_fw.var | 734 | ||||
| -rw-r--r-- | libloragw/src/loragw_hal.c | 91 | ||||
| -rw-r--r-- | libloragw/src/loragw_reg.c | 8 | ||||
| -rw-r--r-- | libloragw/tst/test_loragw_cal.c | 700 | ||||
| -rw-r--r-- | readme.md | 10 | ||||
| -rw-r--r-- | util_pkt_logger/cfg/global_conf.eu868.json | 68 |
12 files changed, 1441 insertions, 635 deletions
@@ -1 +1 @@ -1.7.0
\ No newline at end of file +2.0.0
\ No newline at end of file diff --git a/libloragw/Makefile b/libloragw/Makefile index 2b2090e..4a1f5ca 100644 --- a/libloragw/Makefile +++ b/libloragw/Makefile @@ -99,6 +99,9 @@ else ifeq ($(CFG_BRD),ref_1301_433) else ifeq ($(CFG_BRD),kerlink_868) CFG_BRD_MSG := Kerlink LoRa 868MHz gateway CFG_BRD_OPT := CFG_BRD_KERLINK868 +else ifeq ($(CFG_BRD),kerlink_868_27dbm) + CFG_BRD_MSG := Kerlink LoRa 868MHz gateway with 27dBm capability + CFG_BRD_OPT := CFG_BRD_KERLINK868_27DBM else ifeq ($(CFG_BRD),kerlink_433) CFG_BRD_MSG := Kerlink LoRa 433MHz gateway CFG_BRD_OPT := CFG_BRD_KERLINK433 @@ -132,14 +135,14 @@ endif ### linking options ifeq ($(CFG_SPI),native) - LIBS := -lloragw -lrt + LIBS := -lloragw -lrt -lm else ifeq ($(CFG_SPI),ftdi) - LIBS := -lloragw -lrt -lmpsse + LIBS := -lloragw -lrt -lmpsse -lm endif ### general build targets -all: libloragw.a test_loragw_spi test_loragw_reg test_loragw_hal test_loragw_gps +all: libloragw.a test_loragw_spi test_loragw_reg test_loragw_hal test_loragw_gps test_loragw_cal clean: rm -f libloragw.a @@ -227,4 +230,7 @@ test_loragw_hal: tst/test_loragw_hal.c libloragw.a test_loragw_gps: tst/test_loragw_gps.c libloragw.a $(CC) $(CFLAGS) -L. $< -o $@ $(LIBS) +test_loragw_cal: tst/test_loragw_cal.c libloragw.a src/cal_fw.var + $(CC) $(CFLAGS) -L. $< -o $@ $(LIBS) + ### EOF
\ No newline at end of file diff --git a/libloragw/inc/loragw_hal.h b/libloragw/inc/loragw_hal.h index 1516b65..8196f70 100644 --- a/libloragw/inc/loragw_hal.h +++ b/libloragw/inc/loragw_hal.h @@ -141,7 +141,7 @@ Maintainer: Sylvain Miermont #if (CFG_BRD_NANO868 == 1) #define LGW_RF_TX_ENABLE { true, true} /* both radio A and B are usable in TX */ #define LGW_RF_CLKOUT { true, true} /* both radios have clkout enabled */ -#elif ((CFG_BRD_1301REF868 == 1) || (CFG_BRD_1301REF433 == 1) || (CFG_BRD_KERLINK868 == 1) || (CFG_BRD_KERLINK433 == 1)) +#elif ((CFG_BRD_1301REF868 == 1) || (CFG_BRD_1301REF433 == 1) || (CFG_BRD_KERLINK868 == 1) || (CFG_BRD_KERLINK868_27DBM == 1) || (CFG_BRD_KERLINK433 == 1)) #define LGW_RF_TX_ENABLE { true,false} /* radio B TX output is disconnected */ #define LGW_RF_CLKOUT {false, true} /* radio A clkout disabled for spur optimization */ #elif ((CFG_BRD_CISCO433 == 1) || (CFG_BRD_CISCO470 == 1) || (CFG_BRD_CISCO780 == 1)) diff --git a/libloragw/library.cfg b/libloragw/library.cfg index 52ca305..748aafb 100644 --- a/libloragw/library.cfg +++ b/libloragw/library.cfg @@ -42,6 +42,7 @@ CFG_BAND= eu868 # ref_1301_868 SX1301 reference board with SX1257 radios, 868 MHz filters # ref_1301_433 SX1301 reference board with SX1255 radios, 433 MHz filters # kerlink_868 Kerlink LoRa 868MHz gateway +# kerlink_868_27dbm Kerlink LoRa 868MHz gateway with 27dBm capability # kerlink_433 Kerlink LoRa 433MHz gateway # cisco_433 Cisco LoRa 433MHz gateway # cisco_470 Cisco LoRa 470MHz gateway diff --git a/libloragw/src/agc_fw.var b/libloragw/src/agc_fw.var index 626f172..5083a0e 100644 --- a/libloragw/src/agc_fw.var +++ b/libloragw/src/agc_fw.var @@ -16,186 +16,186 @@ Maintainer: Matthieu Leurent static uint8_t agc_firmware[MCU_AGC_FW_BYTE] = { 0x8A, 0x51, 0x11, 0x28, 0xFF, 0xBF, 0xFF, 0xBF, 0x80, 0x40, 0x03, 0x4E, 0x83, 0x52, 0x03, 0x53, 0xAC, 0x00, 0x04, 0x88, 0xAD, 0x40, 0x0A, 0xC8, 0xAE, 0x40, 0x01, 0x88, 0xAF, 0x80, 0x8A, 0x51, -0x13, 0x68, 0x8A, 0x51, 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0x88, 0x84, 0x0A, 0x82, 0x47, 0x00, 0xF4, +0x8A, 0x51, 0xAE, 0x6E, 0x00, 0xB0, 0x8A, 0xC0, 0x04, 0x88, 0x84, 0x0A, 0x82, 0x47, 0x00, 0xF4, 0x07, 0xB4, 0x06, 0x74, 0x05, 0x74, 0x04, 0x34, 0x03, 0x74, 0x02, 0x34, 0x01, 0x34, 0x00, 0xF4, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, @@ -222,54 +222,54 @@ static uint8_t arb_firmware[MCU_ARB_FW_BYTE] = { 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, -0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0x64, 0xC0, -0x80, 0x81, 0x84, 0x0A, 0x04, 0xC6, 0x03, 0x59, 0x00, 0xF4, 0x04, 0xC6, 0x88, 0xAE, 0xA1, 0x01, -0xA2, 0x01, 0xA3, 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+0x2A, 0x3E, 0x84, 0x80, 0x01, 0xF0, 0x80, 0x40, 0x59, 0xD5, 0x08, 0x40, 0xD8, 0x8A, 0xC0, 0xEF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, diff --git a/libloragw/src/cal_fw.var b/libloragw/src/cal_fw.var index 43b4c40..8c9389e 100644 --- a/libloragw/src/cal_fw.var +++ b/libloragw/src/cal_fw.var @@ -14,274 +14,262 @@ Maintainer: Matthieu Leurent */ static uint8_t cal_firmware[MCU_AGC_FW_BYTE] = { -0x8A, 0x51, 0x15, 0x68, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, -0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0x64, 0xC0, 0x80, 0x81, 0x84, 0x0A, -0x04, 0xC6, 0x03, 0x59, 0x00, 0xF4, 0x04, 0xC6, 0x0E, 0x68, 0xE5, 0x81, 0xE6, 0x81, 0x83, 0x93, -0x54, 0x70, 0x84, 0x80, 0x65, 0xB0, 0x8A, 0x51, 0x0D, 0x20, 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0x1B, 0xD3, 0x08, 0xF0, 0xD4, 0x8A, 0x54, 0x02, 0x03, 0x5C, 0x7F, 0x2F, +0x03, 0x30, 0xA1, 0xC0, 0x00, 0xB0, 0xA2, 0x01, 0xA2, 0x4A, 0x8A, 0x95, 0xF0, 0x27, 0x8A, 0x51, +0x18, 0x56, 0x18, 0x12, 0x8A, 0x95, 0x5B, 0x67, 0x8A, 0x51, 0xE4, 0xB0, 0xCE, 0x40, 0xF0, 0x6F, +0xF1, 0xAF, 0xCE, 0x0B, 0xEF, 0x2F, 0xF4, 0xAF, 0x00, 0x00, 0x0E, 0x70, 0x83, 0x52, 0x03, 0x53, +0xA1, 0xC0, 0x69, 0xB0, 0xA2, 0x01, 0x8A, 0x51, 0xA7, 0x23, 0x8A, 0x51, 0x9B, 0x57, 0xFF, 0x6F, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, @@ -427,103 +415,115 @@ static uint8_t cal_firmware[MCU_AGC_FW_BYTE] = { 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 0xFF, 0xBF, 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0x00, 0x48, 0xA1, 0xC0, 0x24, 0xC8, 0xA2, 0xC0, 0x0E, 0x70, 0xF0, 0x27, 0x8A, 0x95, +0x24, 0xC8, 0xA0, 0xFE, 0x84, 0x80, 0x00, 0x48, 0xA1, 0xC0, 0x24, 0xC8, 0xA2, 0xC0, 0x10, 0xF0, +0xF0, 0x27, 0x8A, 0x95, 0x02, 0xF0, 0xA4, 0x4A, 0x24, 0xC2, 0x03, 0x18, 0x08, 0x40, 0x5C, 0x6F, +0xA3, 0x00, 0x22, 0xC8, 0x03, 0x59, 0xFA, 0xEF, 0x21, 0xC8, 0x88, 0x80, 0x23, 0x08, 0x80, 0x38, +0x86, 0xC0, 0x08, 0x40, 0x21, 0xC8, 0x88, 0x80, 0x23, 0x08, 0x80, 0x38, 0x85, 0xC0, 0x08, 0x40 }; diff --git a/libloragw/src/loragw_hal.c b/libloragw/src/loragw_hal.c index 5dbdf45..302de3a 100644 --- a/libloragw/src/loragw_hal.c +++ b/libloragw/src/loragw_hal.c @@ -51,9 +51,12 @@ Maintainer: Sylvain Miermont #define MCU_ARB 0 #define MCU_AGC 1 - #define MCU_ARB_FW_BYTE 8192 /* size of the firmware IN BYTES (= twice the number of 14b words) */ #define MCU_AGC_FW_BYTE 8192 /* size of the firmware IN BYTES (= twice the number of 14b words) */ +#define FW_VERSION_ADDR 0x20 /* Address of firmware version in data memory */ +#define FW_VERSION_CAL 2 /* Expected version of calibration firmware */ +#define FW_VERSION_AGC 4 /* Expected version of AGC firmware */ +#define FW_VERSION_ARB 1 /* Expected version of arbiter firmware */ #define TX_METADATA_NB 16 #define RX_METADATA_NB 16 @@ -112,6 +115,8 @@ F_register(24bit) = F_rf (Hz) / F_step(Hz) #elif (CFG_BRD_1301REF868 == 1) #define RSSI_BOARD_OFFSET 166.0 #elif (CFG_BRD_KERLINK868 == 1) + #define RSSI_BOARD_OFFSET 167.0 +#elif (CFG_BRD_KERLINK868_27DBM == 1) #define RSSI_BOARD_OFFSET 165.0 #elif (CFG_BRD_1301REF433 == 1) #define RSSI_BOARD_OFFSET 176.5 @@ -258,6 +263,26 @@ typedef struct { { 3, 3, 13, 23},\ { 3, 3, 15, 24},\ }; /* calibrated */ +#elif (CFG_BRD_KERLINK868_27DBM == 1) + #define CUSTOM_TX_POW_TABLE 1 + const tx_pow_t tx_pow_table[TX_POW_LUT_SIZE] = {\ + { 0, 3, 8, -5},\ + { 0, 3, 11, -1},\ + { 0, 3, 12, 0},\ + { 1, 3, 9, 7},\ + { 1, 3, 10, 8},\ + { 1, 3, 12, 11},\ + { 1, 3, 13, 13},\ + { 1, 3, 14, 14},\ + { 2, 3, 9, 16},\ + { 2, 3, 11, 19},\ + { 3, 3, 7, 21},\ + { 3, 3, 8, 23},\ + { 3, 3, 9, 24},\ + { 3, 3, 10, 26},\ + { 3, 3, 11, 27},\ + { 3, 3, 12, 28},\ + }; /* calibrated */ #elif (CFG_BRD_KERLINK433 == 1) #define CUSTOM_TX_POW_TABLE 1 const tx_pow_t tx_pow_table[TX_POW_LUT_SIZE] = {\ @@ -413,6 +438,8 @@ typedef struct { #define CFG_BRD_STR "ref_1301_433" #elif (CFG_BRD_KERLINK868 == 1) #define CFG_BRD_STR "kerlink_868" +#elif (CFG_BRD_KERLINK868_27DBM == 1) + #define CFG_BRD_STR "kerlink_868_27dbm" #elif (CFG_BRD_KERLINK433 == 1) #define CFG_BRD_STR "kerlink_433" #elif (CFG_BRD_CISCO433 == 1) @@ -1008,7 +1035,7 @@ int lgw_start(void) { uint8_t radio_select; int32_t read_val; uint8_t load_val; - + uint8_t fw_version; uint8_t cal_cmd; uint16_t cal_time; uint8_t cal_status; @@ -1043,6 +1070,18 @@ int lgw_start(void) { setup_sx125x(0, rf_rx_freq[0]); setup_sx125x(1, rf_rx_freq[1]); + /* gives AGC control of GPIOs to enable Tx external digital filter */ + lgw_reg_w(LGW_GPIO_MODE,31); /* Set all GPIOs as output */ + lgw_reg_w(LGW_GPIO_SELECT_OUTPUT,2); + + /* GPIOs table : + DGPIO0 -> N/A + DGPIO1 -> N/A + DGPIO2 -> N/A + DGPIO3 -> TX digital filter ON + DGPIO4 -> TX ON + */ + /* select calibration command */ cal_cmd = 0; cal_cmd |= rf_enable[0] ? 0x01 : 0x00; /* Bit 0: Calibrate Rx IQ mismatch compensation on radio A */ @@ -1057,7 +1096,7 @@ int lgw_start(void) { cal_cmd |= 0x20; /* Bit 5: 0: SX1257, 1: SX1255 */ #endif - #if ((CFG_BRD_1301REF868 == 1) || (CFG_BRD_1301REF433 == 1) || (CFG_BRD_KERLINK868 == 1) || (CFG_BRD_KERLINK433 == 1) || (CFG_BRD_CISCO433 == 1) || (CFG_BRD_CISCO470 == 1) || (CFG_BRD_CISCO780 == 1)) + #if ((CFG_BRD_1301REF868 == 1) || (CFG_BRD_1301REF433 == 1) || (CFG_BRD_KERLINK868 == 1) || (CFG_BRD_KERLINK868_27DBM == 1) || (CFG_BRD_KERLINK433 == 1) || (CFG_BRD_CISCO433 == 1) || (CFG_BRD_CISCO470 == 1) || (CFG_BRD_CISCO780 == 1)) cal_cmd |= 0x00; /* Bit 6-7: Board type 0: ref, 1: FPGA, 3: board X */ cal_time = 2300; /* measured between 2.1 and 2.2 sec, because 1 TX only */ #elif (CFG_BRD_NANO868 == 1) @@ -1073,6 +1112,16 @@ int lgw_start(void) { lgw_reg_w(LGW_FORCE_HOST_RADIO_CTRL,0); /* gives to AGC MCU the control of the radios */ lgw_reg_w(LGW_RADIO_SELECT,cal_cmd); /* send calibration configuration word */ lgw_reg_w(LGW_MCU_RST_1,0); + + /* Check firmware version */ + lgw_reg_w(LGW_DBG_AGC_MCU_RAM_ADDR, FW_VERSION_ADDR); + lgw_reg_r(LGW_DBG_AGC_MCU_RAM_DATA, &read_val); + fw_version = (uint8_t)read_val; + if (fw_version != FW_VERSION_CAL) { + printf("ERROR: Version of calibration firmware not expected, actual:%d expected:%d\n", fw_version, FW_VERSION_CAL); + return -1; + } + lgw_reg_w(LGW_PAGE_REG,3); /* Calibration will start on this condition as soon as MCU can talk to concentrator registers */ lgw_reg_w(LGW_EMERGENCY_FORCE_HOST_CTRL,0); /* Give control of concentrator registers to MCU */ @@ -1248,6 +1297,22 @@ int lgw_start(void) { lgw_reg_w(LGW_MCU_RST_0, 0); lgw_reg_w(LGW_MCU_RST_1, 0); + /* Check firmware version */ + lgw_reg_w(LGW_DBG_AGC_MCU_RAM_ADDR, FW_VERSION_ADDR); + lgw_reg_r(LGW_DBG_AGC_MCU_RAM_DATA, &read_val); + fw_version = (uint8_t)read_val; + if (fw_version != FW_VERSION_AGC) { + DEBUG_PRINTF("ERROR: Version of AGC firmware not expected, actual:%d expected:%d\n", fw_version, FW_VERSION_AGC); + return LGW_HAL_ERROR; + } + lgw_reg_w(LGW_DBG_ARB_MCU_RAM_ADDR, FW_VERSION_ADDR); + lgw_reg_r(LGW_DBG_ARB_MCU_RAM_DATA, &read_val); + fw_version = (uint8_t)read_val; + if (fw_version != FW_VERSION_ARB) { + DEBUG_PRINTF("ERROR: Version of arbiter firmware not expected, actual:%d expected:%d\n", fw_version, FW_VERSION_ARB); + return LGW_HAL_ERROR; + } + DEBUG_MSG("Info: Initialising AGC firmware...\n"); wait_ms(1); @@ -1258,7 +1323,6 @@ int lgw_start(void) { } /* Update Tx gain LUT and start AGC */ - #if (CUSTOM_TX_POW_TABLE == 1) DEBUG_MSG("Info: loading custom TX gain table\n"); for(i=0; i<TX_POW_LUT_SIZE; ++i) { @@ -1314,17 +1378,6 @@ int lgw_start(void) { /* enable GPS event capture */ lgw_reg_w(LGW_GPS_EN,1); - /* enable LEDs */ - lgw_reg_w(LGW_GPIO_MODE,31); - // lgw_reg_w(LGW_GPIO_SELECT_OUTPUT,0); /* default 0 */ - /* LED table : - DGPIO0 -> packets waiting in the RX FIFO, ready to be fetched - DGPIO1 -> multi-SF RX LoRa modems activity (channels 0 to 7) - DGPIO2 -> stand-alone RX LoRa modem activity (channel 8)) - DGPIO3 -> FSK RX modem activity (channel 9) - DGPIO4 -> TX modem active (either LoRa or FSK) - */ - lgw_is_started = true; return LGW_HAL_SUCCESS; } @@ -1739,10 +1792,12 @@ int lgw_send(struct lgw_pkt_tx_s pkt_data) { buff[15] = 0; /* MSB of RF frequency is now used in AGC firmware to implement large/narrow filtering in SX1257/55 */ + buff[0] &= 0x3F; /* Unset 2 MSBs of frequency code */ if (pkt_data.bandwidth == BW_500KHZ) { - buff[0] |= 0x80; /* Enlarge filter for 500kHz BW */ - } else { - buff[0] &= 0x7F; + buff[0] |= 0x80; /* Set MSB bit to enlarge analog filter for 500kHz BW */ + } + else if (pkt_data.bandwidth == BW_125KHZ){ + buff[0] |= 0x40; /* Set MSB-1 bit to enable digital filter for 125kHz BW */ } } else if (pkt_data.modulation == MOD_FSK) { diff --git a/libloragw/src/loragw_reg.c b/libloragw/src/loragw_reg.c index 7f9ec40..9381e0a 100644 --- a/libloragw/src/loragw_reg.c +++ b/libloragw/src/loragw_reg.c @@ -680,7 +680,7 @@ int lgw_reg_r(uint16_t register_id, int32_t *reg_value) { /* Point to a register by name and do a burst write */ int lgw_reg_wb(uint16_t register_id, uint8_t *data, uint16_t size) { - int spi_stat; + int spi_stat = LGW_SPI_SUCCESS; struct lgw_reg_s r; /* check input parameters */ @@ -715,7 +715,7 @@ int lgw_reg_wb(uint16_t register_id, uint8_t *data, uint16_t size) { } /* do the burst write */ - spi_stat = lgw_spi_wb(lgw_spi_target, r.addr, data, size); + spi_stat += lgw_spi_wb(lgw_spi_target, r.addr, data, size); if (spi_stat != LGW_SPI_SUCCESS) { DEBUG_MSG("ERROR: SPI ERROR DURING REGISTER BURST WRITE\n"); @@ -729,7 +729,7 @@ int lgw_reg_wb(uint16_t register_id, uint8_t *data, uint16_t size) { /* Point to a register by name and do a burst read */ int lgw_reg_rb(uint16_t register_id, uint8_t *data, uint16_t size) { - int spi_stat; + int spi_stat = LGW_SPI_SUCCESS; struct lgw_reg_s r; /* check input parameters */ @@ -758,7 +758,7 @@ int lgw_reg_rb(uint16_t register_id, uint8_t *data, uint16_t size) { } /* do the burst read */ - spi_stat = lgw_spi_rb(lgw_spi_target, r.addr, data, size); + spi_stat += lgw_spi_rb(lgw_spi_target, r.addr, data, size); if (spi_stat != LGW_SPI_SUCCESS) { DEBUG_MSG("ERROR: SPI ERROR DURING REGISTER BURST READ\n"); diff --git a/libloragw/tst/test_loragw_cal.c b/libloragw/tst/test_loragw_cal.c new file mode 100644 index 0000000..da4f130 --- /dev/null +++ b/libloragw/tst/test_loragw_cal.c @@ -0,0 +1,700 @@ +/* + / _____) _ | | +( (____ _____ ____ _| |_ _____ ____| |__ + \____ \| ___ | (_ _) ___ |/ ___) _ \ + _____) ) ____| | | || |_| ____( (___| | | | +(______/|_____)_|_|_| \__)_____)\____)_| |_| + (C)2013 Semtech-Cycleo + +Description: + Minimum test program for the loragw_hal 'library' + +License: Revised BSD License, see LICENSE.TXT file include in the project +Maintainer: Sylvain Miermont +*/ + + +/* -------------------------------------------------------------------------- */ +/* --- DEPENDANCIES --------------------------------------------------------- */ + +/* fix an issue between POSIX and C99 */ +#if __STDC_VERSION__ >= 199901L + #define _XOPEN_SOURCE 600 +#else + #define _XOPEN_SOURCE 500 +#endif + +#include <stdint.h> /* C99 types */ +#include <stdbool.h> /* bool type */ +#include <stdio.h> /* printf */ +#include <string.h> /* memset */ +#include <signal.h> /* sigaction */ +#include <math.h> /* cos */ +#include <unistd.h> /* getopt access */ + +#include "loragw_hal.h" +#include "loragw_reg.h" +#include "loragw_aux.h" + +/* -------------------------------------------------------------------------- */ +/* --- PRIVATE MACROS ------------------------------------------------------- */ + +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +/* -------------------------------------------------------------------------- */ +/* --- PRIVATE CONSTANTS ---------------------------------------------------- */ + +#if ((CFG_BAND_868 == 1) || ((CFG_BAND_FULL == 1) && (CFG_RADIO_1257 == 1))) + #define F_RX_0 868500000 +#elif (CFG_BAND_915 == 1) + #define F_RX_0 915500000 +#elif ((CFG_BAND_470 == 1) || ((CFG_BAND_FULL == 1) && (CFG_RADIO_1255 == 1))) + #define F_RX_0 470500000 +#elif (CFG_BAND_433 == 1) + #define F_RX_0 433500000 +#elif (CFG_BAND_780 == 1) + #define F_RX_0 780500000 +#endif +#define NB_CAL_MAX 100 +#define MCU_AGC 1 +#define MCU_AGC_FW_BYTE 8192 /* size of the firmware IN BYTES (= twice the number of 14b words) */ +#define FW_VERSION_ADDR 0x20 +#define FW_VERSION_CAL 2 +#define RAM_SIZE 4096 +#define FREQ_SIG_NORM 0.078125 + +/* -------------------------------------------------------------------------- */ +/* --- PRIVATE VARIABLES ---------------------------------------------------- */ + +#include "../src/cal_fw.var" /* external definition of the variable */ + +/* -------------------------------------------------------------------------- */ +/* --- PRIVATE TYPES --------------------------------------------------------- */ + +struct cal_res_s { + int8_t amp_a; + int8_t phi_a; + int8_t amp_b; + int8_t phi_b; + int8_t offset_i_a [8]; + int8_t offset_q_a [8]; + int8_t offset_i_b [8]; + int8_t offset_q_b [8]; + uint8_t img_rej_a; + uint8_t img_rej_b; + uint8_t offset_rej_a [8]; + uint8_t offset_rej_b [8]; + uint8_t debug [8]; +}; + +/* -------------------------------------------------------------------------- */ +/* --- PRIVATE FUNCTIONS DECLARATION ---------------------------------------- */ + +int load_firmware(uint8_t target, uint8_t *firmware, uint16_t size); /* defined in loragw_hal.c */ + +void sx125x_write(uint8_t channel, uint8_t addr, uint8_t data); /* defined in loragw_hal.c */ + +uint8_t sx125x_read(uint8_t channel, uint8_t addr); /* defined in loragw_hal.c */ + +int setup_sx125x(uint8_t rf_chain, uint32_t freq_hz); /* defined in loragw_hal.c */ + +uint8_t sx125x_cal(uint8_t cal_cmd, struct cal_res_s *cal_res); + +int read_capture(int16_t *i, int16_t *q, int nb_samp); + +uint8_t get_img_rej(int16_t *sig_i, int16_t *sig_q, int nb_samp, double f_sig_norm); + +void usage (void); + +/* -------------------------------------------------------------------------- */ +/* --- PRIVATE FUNCTIONS DEFINITION ----------------------------------------- */ + +/* describe command line options */ +void usage(void) { + printf("Library version information: %s\n", lgw_version_info()); + printf( "Available options:\n"); + printf( " -h print this help\n"); + printf( " -a <float> Radio A frequency in MHz\n"); + printf( " -b <float> Radio B frequency in MHz\n"); + printf( " -n <uint> Number of calibration iterations\n"); +} + +/* -------------------------------------------------------------------------- */ +/* --- MAIN FUNCTION -------------------------------------------------------- */ + +int main(int argc, char **argv) +{ + int i, j, x; + int32_t read_val; + const struct lgw_conf_rxrf_s rfconf = {true, F_RX_0}; + uint8_t fw_version; + uint8_t cal_cmd; + uint8_t cal_status; + struct cal_res_s cal_res [NB_CAL_MAX]; + struct cal_res_s cal_res_max; + struct cal_res_s cal_res_min; + int16_t sig_i [RAM_SIZE]; + int16_t sig_q [RAM_SIZE]; + uint8_t img_rej_a [NB_CAL_MAX]; + uint8_t img_rej_b [NB_CAL_MAX]; + uint8_t img_rej_a_max; + uint8_t img_rej_a_min; + uint8_t img_rej_b_max; + uint8_t img_rej_b_min; + //FILE *file; + + /* command line options */ + int xi = 0; + double xd = 0.0; + uint32_t fa = F_RX_0; + uint32_t fb = F_RX_0 + 1000000; + int nb_cal = 5; + + /* parse command line options */ + while ((i = getopt (argc, argv, "ha:b:n:")) != -1) { + switch (i) { + case 'h': + usage(); + return -1; + break; + case 'a': /* -f <float> Radio A frequency in MHz */ + i = sscanf(optarg, "%lf", &xd); + fa = (uint32_t)((xd*1e6) + 0.5); /* .5 Hz offset to get rounding instead of truncating */ + break; + case 'b': /* -f <float> Radio B frequency in MHz */ + i = sscanf(optarg, "%lf", &xd); + fb = (uint32_t)((xd*1e6) + 0.5); /* .5 Hz offset to get rounding instead of truncating */ + break; + case 'n': /* -n <uint> Number of calibration iterations */ + i = sscanf(optarg, "%i", &xi); + if ((i != 1) || (xi > NB_CAL_MAX)) { + printf("ERROR: invalid number of calibration iterations (MAX %d)\n",NB_CAL_MAX); + usage(); + return -1; + } else { + nb_cal = xi; + } + break; + default: + printf("ERROR: argument parsing\n"); + usage(); + return -1; + } + } + + /* RF config */ + lgw_rxrf_setconf(0, rfconf); + lgw_rxrf_setconf(1, rfconf); + + /* Calibration command */ + cal_cmd = 0; + //cal_cmd |= 0x01; /* Bit 0: Calibrate Rx IQ mismatch compensation on radio A */ + //cal_cmd |= 0x02; /* Bit 1: Calibrate Rx IQ mismatch compensation on radio B */ + //cal_cmd |= 0x04; /* Bit 2: Calibrate Tx DC offset on radio A */ + //cal_cmd |= 0x08; /* Bit 3: Calibrate Tx DC offset on radio B */ + cal_cmd |= 0x10; /* Bit 4: 0: calibrate with DAC gain=2, 1: with DAC gain=3 (use 3) */ + + #if (CFG_RADIO_1257 == 1) + cal_cmd |= 0x00; /* Bit 5: 0: SX1257, 1: SX1255 */ + #elif (CFG_RADIO_1255 == 1) + cal_cmd |= 0x20; /* Bit 5: 0: SX1257, 1: SX1255 */ + #endif + + #if ((CFG_BRD_1301REF868 == 1) || (CFG_BRD_1301REF433 == 1) || (CFG_BRD_KERLINK868 == 1) || (CFG_BRD_KERLINK868_27DBM == 1) || (CFG_BRD_KERLINK433 == 1) || (CFG_BRD_CISCO433 == 1) || (CFG_BRD_CISCO470 == 1) || (CFG_BRD_CISCO780 == 1)) + cal_cmd |= 0x00; /* Bit 6-7: Board type 0: ref, 1: FPGA, 3: board X */ + #elif (CFG_BRD_NANO868 == 1) + cal_cmd |= 0x40; /* Bit 6-7: Board type 0: ref, 1: FPGA, 3: board X */ + #else + cal_cmd |= 0xC0; /* Bit 6-7: Board type 0: ref, 1: FPGA, 3: board X */ + #endif + + /* Recap parameters*/ + printf("Library version information: %s\n", lgw_version_info()); + printf("Radio A frequency: %f MHz\n",fa/1e6); + printf("Radio B frequency: %f MHz\n",fb/1e6); + printf("Number of calibration iterations: %d\n",nb_cal); + printf("Calibration command: brd: %d, chip: %d, dac: %d\n\n", cal_cmd >> 6, 1257-2*((cal_cmd & 0x20) >> 5), 2+((cal_cmd & 0x10) >> 4)); + + x = lgw_connect(); + if (x == -1) { + printf("ERROR: FAIL TO CONNECT BOARD\n"); + return -1; + } + + /* reset the registers (also shuts the radios down) */ + lgw_soft_reset(); + + /* ungate clocks (gated by default) */ + lgw_reg_w(LGW_GLOBAL_EN, 1); + + /* switch on and reset the radios (also starts the 32 MHz XTAL) */ + lgw_reg_w(LGW_RADIO_A_EN,1); + lgw_reg_w(LGW_RADIO_B_EN,1); + wait_ms(500); /* TODO: optimize */ + lgw_reg_w(LGW_RADIO_RST,1); + wait_ms(5); + lgw_reg_w(LGW_RADIO_RST,0); + + /* setup the radios */ + setup_sx125x(0, fa); + setup_sx125x(1, fb); + + /* Set GPIO 4 high for calibration */ + lgw_reg_w(LGW_GPIO_MODE,31); /* Set all GPIOs as output */ + lgw_reg_w(LGW_GPIO_SELECT_OUTPUT,2); /* AGC MCU drives GPIOs */ + + /* Load the calibration firmware */ + load_firmware(MCU_AGC, cal_firmware, MCU_AGC_FW_BYTE); + lgw_reg_w(LGW_MCU_RST_1,0); + lgw_reg_w(LGW_DBG_AGC_MCU_RAM_ADDR, FW_VERSION_ADDR); + lgw_reg_r(LGW_DBG_AGC_MCU_RAM_DATA, &read_val); + fw_version = (uint8_t)read_val; + if (fw_version != FW_VERSION_CAL) { + printf("ERROR: Version of calibration firmware not expected, actual:%d expected:%d\n", fw_version, FW_VERSION_CAL); + return -1; + } + + /* Run Rx A IQ mismatch calibration only */ + for (i=0; i<nb_cal; i++) { + cal_status = sx125x_cal(cal_cmd | 0x01, &cal_res[i]); + x = read_capture(sig_i, sig_q, RAM_SIZE); + /* + file = fopen("toto.txt","w"); + for (j=0; j<RAM_SIZE; j++) { + fprintf(file, "%d %d\n", sig_i[j], sig_q[j]); + } + fclose(file); + */ + img_rej_a[i] = get_img_rej(sig_i, sig_q, RAM_SIZE, FREQ_SIG_NORM); + + printf("Rx A IQ mismatch: Amp: %3d Phi: %3d Rej: %2d dB Status: %3d | Debug: Rej: %2d dB Lna: %1d BB: %2d Dec: %2d\n", cal_res[i].amp_a, cal_res[i].phi_a, cal_res[i].img_rej_a, cal_status, img_rej_a[i], cal_res[i].debug[0], cal_res[i].debug[1], cal_res[i].debug[2]); + } + + /* Run Rx B IQ mismatch calibation only */ + printf("\n"); + for (i=0; i<nb_cal; i++) { + cal_status = sx125x_cal(cal_cmd | 0x02, &cal_res[i]); + x = read_capture(sig_i, sig_q, RAM_SIZE); + img_rej_b[i] = get_img_rej(sig_i, sig_q, RAM_SIZE, FREQ_SIG_NORM); + + printf("Rx B IQ mismatch: Amp: %3d Phi: %3d Rej: %2d dB Status: %3d | Debug: Rej: %2d dB Lna: %1d BB: %2d Dec: %2d\n", cal_res[i].amp_b, cal_res[i].phi_b, cal_res[i].img_rej_b, cal_status, img_rej_b[i], cal_res[i].debug[0], cal_res[i].debug[1], cal_res[i].debug[2]); + } + + /* Run Tx A DC offset calibation only */ + printf("\n"); + for (i=0; i<nb_cal; i++) { + cal_status = sx125x_cal(cal_cmd | 0x04, &cal_res[i]); + + printf("Tx A DC offset I :"); + for (j=0; j<8; j++) { + printf(" %3d", cal_res[i].offset_i_a[j]); + } + printf("\n"); + printf("Tx A DC offset Q :"); + for (j=0; j<8; j++) { + printf(" %3d", cal_res[i].offset_q_a[j]); + } + printf("\n"); + printf("Tx A DC rejection:"); + for (j=0; j<8; j++) { + printf(" %3d", cal_res[i].offset_rej_a[j]); + } + printf("\n"); + printf("Tx A DC debug BB :"); + for (j=0; j<8; j++) { + printf(" %3d", (cal_res[i].debug[j] & 0xF0) >> 4); + } + printf("\n"); + printf("Tx A DC debug Dec:"); + for (j=0; j<8; j++) { + printf(" %3d", cal_res[i].debug[j] & 0x0F); + } + printf("\n"); + printf("Tx A DC Status : %3d\n", cal_status); + } + + /* Run Tx B DC offset calibation only */ + #if !((CFG_BRD_1301REF868 == 1) || (CFG_BRD_1301REF433 == 1) || (CFG_BRD_KERLINK868 == 1) || (CFG_BRD_KERLINK868_27DBM == 1) || (CFG_BRD_KERLINK433 == 1) || (CFG_BRD_CISCO433 == 1) || (CFG_BRD_CISCO470 == 1) || (CFG_BRD_CISCO780 == 1)) + printf("\n"); + for (i=0; i<nb_cal; i++) { + cal_status = sx125x_cal(cal_cmd | 0x08, &cal_res[i]); + + printf("Tx B DC offset I :"); + for (j=0; j<8; j++) { + printf(" %3d", cal_res[i].offset_i_b[j]); + } + printf("\n"); + printf("Tx B DC offset Q :"); + for (j=0; j<8; j++) { + printf(" %3d", cal_res[i].offset_q_b[j]); + } + printf("\n"); + printf("Tx B DC rejection:"); + for (j=0; j<8; j++) { + printf(" %3d", cal_res[i].offset_rej_b[j]); + } + printf("\n"); + printf("Tx B DC debug BB :"); + for (j=0; j<8; j++) { + printf(" %3d", (cal_res[i].debug[j] & 0xF0) >> 4); + } + printf("\n"); + printf("Tx B DC debug Dec:"); + for (j=0; j<8; j++) { + printf(" %3d", cal_res[i].debug[j] & 0x0F); + } + printf("\n"); + printf("Tx B DC Status : %3d\n", cal_status); + } + #endif + + /* Compute statistics */ + cal_res_max.amp_a = -128; + cal_res_max.phi_a = -128; + cal_res_max.amp_b = -128; + cal_res_max.phi_b = -128; + cal_res_max.img_rej_a = 0; + cal_res_max.img_rej_b = 0; + for (j=0; j<8; j++) { + cal_res_max.offset_i_a[j] = -128; + cal_res_max.offset_q_a[j] = -128; + cal_res_max.offset_i_b[j] = -128; + cal_res_max.offset_q_b[j] = -128; + cal_res_max.offset_rej_a[j] = 0; + cal_res_max.offset_rej_b[j] = 0; + } + + cal_res_min.amp_a = 127; + cal_res_min.phi_a = 127; + cal_res_min.amp_b = 127; + cal_res_min.phi_b = 127; + cal_res_min.img_rej_a = 255; + cal_res_min.img_rej_b = 255; + for (j=0; j<8; j++) { + cal_res_min.offset_i_a[j] = 127; + cal_res_min.offset_q_a[j] = 127; + cal_res_min.offset_i_b[j] = 127; + cal_res_min.offset_q_b[j] = 127; + cal_res_min.offset_rej_a[j] = 255; + cal_res_min.offset_rej_b[j] = 255; + } + + img_rej_a_max = 0; + img_rej_a_min = 255; + img_rej_b_max = 0; + img_rej_b_min = 255; + + for (i=0; i<nb_cal; i++) { + if (cal_res[i].amp_a > cal_res_max.amp_a) { + cal_res_max.amp_a = cal_res[i].amp_a; + } + if (cal_res[i].phi_a > cal_res_max.phi_a) { + cal_res_max.phi_a = cal_res[i].phi_a; + } + if (cal_res[i].amp_b > cal_res_max.amp_b) { + cal_res_max.amp_b = cal_res[i].amp_b; + } + if (cal_res[i].phi_b > cal_res_max.phi_b) { + cal_res_max.phi_b = cal_res[i].phi_b; + } + if (cal_res[i].phi_b > cal_res_max.phi_b) { + cal_res_max.phi_b = cal_res[i].phi_b; + } + if (cal_res[i].img_rej_a > cal_res_max.img_rej_a) { + cal_res_max.img_rej_a = cal_res[i].img_rej_a; + } + if (cal_res[i].img_rej_b > cal_res_max.img_rej_b) { + cal_res_max.img_rej_b = cal_res[i].img_rej_b; + } + for (j=0; j<8; j++) { + if (cal_res[i].offset_i_a[j] > cal_res_max.offset_i_a[j]) { + cal_res_max.offset_i_a[j] = cal_res[i].offset_i_a[j]; + } + if (cal_res[i].offset_q_a[j] > cal_res_max.offset_q_a[j]) { + cal_res_max.offset_q_a[j] = cal_res[i].offset_q_a[j]; + } + if (cal_res[i].offset_i_b[j] > cal_res_max.offset_i_b[j]) { + cal_res_max.offset_i_b[j] = cal_res[i].offset_i_b[j]; + } + if (cal_res[i].offset_q_b[j] > cal_res_max.offset_q_b[j]) { + cal_res_max.offset_q_b[j] = cal_res[i].offset_q_b[j]; + } + if (cal_res[i].offset_rej_a[j] > cal_res_max.offset_rej_a[j]) { + cal_res_max.offset_rej_a[j] = cal_res[i].offset_rej_a[j]; + } + if (cal_res[i].offset_rej_b[j] > cal_res_max.offset_rej_b[j]) { + cal_res_max.offset_rej_b[j] = cal_res[i].offset_rej_b[j]; + } + } + + if (cal_res[i].amp_a < cal_res_min.amp_a) { + cal_res_min.amp_a = cal_res[i].amp_a; + } + if (cal_res[i].phi_a < cal_res_min.phi_a) { + cal_res_min.phi_a = cal_res[i].phi_a; + } + if (cal_res[i].amp_b < cal_res_min.amp_b) { + cal_res_min.amp_b = cal_res[i].amp_b; + } + if (cal_res[i].phi_b < cal_res_min.phi_b) { + cal_res_min.phi_b = cal_res[i].phi_b; + } + if (cal_res[i].phi_b < cal_res_min.phi_b) { + cal_res_min.phi_b = cal_res[i].phi_b; + } + if (cal_res[i].img_rej_a < cal_res_min.img_rej_a) { + cal_res_min.img_rej_a = cal_res[i].img_rej_a; + } + if (cal_res[i].img_rej_b < cal_res_min.img_rej_b) { + cal_res_min.img_rej_b = cal_res[i].img_rej_b; + } + for (j=0; j<8; j++) { + if (cal_res[i].offset_i_a[j] < cal_res_min.offset_i_a[j]) { + cal_res_min.offset_i_a[j] = cal_res[i].offset_i_a[j]; + } + if (cal_res[i].offset_q_a[j] < cal_res_min.offset_q_a[j]) { + cal_res_min.offset_q_a[j] = cal_res[i].offset_q_a[j]; + } + if (cal_res[i].offset_i_b[j] < cal_res_min.offset_i_b[j]) { + cal_res_min.offset_i_b[j] = cal_res[i].offset_i_b[j]; + } + if (cal_res[i].offset_q_b[j] < cal_res_min.offset_q_b[j]) { + cal_res_min.offset_q_b[j] = cal_res[i].offset_q_b[j]; + } + if (cal_res[i].offset_rej_a[j] < cal_res_min.offset_rej_a[j]) { + cal_res_min.offset_rej_a[j] = cal_res[i].offset_rej_a[j]; + } + if (cal_res[i].offset_rej_b[j] < cal_res_min.offset_rej_b[j]) { + cal_res_min.offset_rej_b[j] = cal_res[i].offset_rej_b[j]; + } + } + + if (img_rej_a[i] > img_rej_a_max) { + img_rej_a_max = img_rej_a[i]; + } + if (img_rej_a[i] < img_rej_a_min) { + img_rej_a_min = img_rej_a[i]; + } + if (img_rej_b[i] > img_rej_b_max) { + img_rej_b_max = img_rej_b[i]; + } + if (img_rej_b[i] < img_rej_b_min) { + img_rej_b_min = img_rej_b[i]; + } + } + + /* Print statistics */ + printf("\n"); + printf("Rx A IQ mismatch calibration statistics on %3d iterations (min, max):\n", nb_cal); + printf("Amp: %3d %3d Phi: %3d %3d Rej: %2d %2d dB (capt.: %2d %2d dB)\n", cal_res_min.amp_a, cal_res_max.amp_a, cal_res_min.phi_a, cal_res_max.phi_a, cal_res_min.img_rej_a, cal_res_max.img_rej_a, img_rej_a_min, img_rej_a_max); + + printf("\n"); + printf("Rx B IQ mismatch calibration statistics on %3d iterations (min, max):\n", nb_cal); + printf("Amp: %3d %3d Phi: %3d %3d Rej: %2d %2d dB (capt.: %2d %2d dB)\n", cal_res_min.amp_b, cal_res_max.amp_b, cal_res_min.phi_b, cal_res_max.phi_b, cal_res_min.img_rej_b, cal_res_max.img_rej_b, img_rej_b_min, img_rej_b_max); + + printf("\n"); + printf("Tx A DC offset calibration statistics on %3d iterations (min, max):\n", nb_cal); + for (j=0; j<8; j++) { + printf(" Mix gain %2d: I: %3d %3d Q: %3d %3d Rej: %2d %2d dB\n", 8+j, cal_res_min.offset_i_a[j], cal_res_max.offset_i_a[j], cal_res_min.offset_q_a[j], cal_res_max.offset_q_a[j], cal_res_min.offset_rej_a[j], cal_res_max.offset_rej_a[j]); + } + + #if !((CFG_BRD_1301REF868 == 1) || (CFG_BRD_1301REF433 == 1) || (CFG_BRD_KERLINK868 == 1) || (CFG_BRD_KERLINK868_27DBM == 1) || (CFG_BRD_KERLINK433 == 1) || (CFG_BRD_CISCO433 == 1) || (CFG_BRD_CISCO470 == 1) || (CFG_BRD_CISCO780 == 1)) + printf("\n"); + printf("Tx B DC offset calibration statistics on %3d iterations (min, max):\n", nb_cal); + for (j=0; j<8; j++) { + printf(" Mix gain %2d: I: %3d %3d Q: %3d %3d Rej: %2d %2d dB\n", 8+j, cal_res_min.offset_i_b[j], cal_res_max.offset_i_b[j], cal_res_min.offset_q_b[j], cal_res_max.offset_q_b[j], cal_res_min.offset_rej_b[j], cal_res_max.offset_rej_b[j]); + } + #endif + + lgw_stop(); + + printf("\nEnd of radio calibration test\n"); + + return 0; +} + +/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ + +uint8_t sx125x_cal(uint8_t cal_cmd, struct cal_res_s *cal_res) { + + int i; + int32_t read_val; + uint8_t cal_status; + + lgw_reg_w(LGW_FORCE_HOST_RADIO_CTRL,0); /* gives to AGC MCU the control of the radios */ + lgw_reg_w(LGW_RADIO_SELECT,cal_cmd); /* send calibration configuration word */ + lgw_reg_w(LGW_MCU_RST_1,1); + lgw_reg_w(LGW_MCU_RST_1,0); + lgw_reg_w(LGW_PAGE_REG,3); /* Calibration will start on this condition as soon as MCU can talk to concentrator registers */ + lgw_reg_w(LGW_EMERGENCY_FORCE_HOST_CTRL,0); /* Give control of concentrator registers to MCU */ + + wait_ms(2000); /* Wait for end of calibration */ + + lgw_reg_w(LGW_EMERGENCY_FORCE_HOST_CTRL,1); /* Take back control */ + + /* Get calibration status */ + lgw_reg_r(LGW_MCU_AGC_STATUS, &read_val); + cal_status = (uint8_t)read_val; + + /* Check calibration flags + bit 0: could access SX1301 registers + bit 1: could access radio A registers + bit 2: could access radio B registers + bit 3: radio A RX image rejection successful + bit 4: radio B RX image rejection successful + bit 5: radio A TX imbalance correction successful + bit 6: radio B TX imbalance correction successful + bit 7: calibration finished */ + + if ((cal_status & 0x01) == 0) { + printf("WARNING: calibration could not access SX1301 registers\n"); + } + if ((cal_status & 0x02) == 0) { + printf("WARNING: calibration could not access radio A\n"); + } + if ((cal_status & 0x04) == 0) { + printf("WARNING: calibration could not access radio B\n"); + } + if ((cal_cmd & 0x01) && ((cal_status & 0x08) == 0)) { + printf("WARNING: problem in calibration of radio A for image rejection\n"); + } + if ((cal_cmd & 0x02) && ((cal_status & 0x10) == 0)) { + printf("WARNING: problem in calibration of radio B for image rejection\n"); + } + if ((cal_cmd & 0x04) && ((cal_status & 0x20) == 0)) { + printf("WARNING: problem in calibration of radio A for TX imbalance\n"); + } + if ((cal_cmd & 0x08) && ((cal_status & 0x40) == 0)) { + printf("WARNING: problem in calibration of radio B for TX imbalance\n"); + } + if ((cal_status & 0x80) == 0) { + printf("WARNING: Calibration not finished\n"); + } + + /* Get calibration results */ + if (cal_cmd & 0x01) { + lgw_reg_r(LGW_IQ_MISMATCH_A_AMP_COEFF, &read_val); + (*cal_res).amp_a = (int8_t)((read_val > 31) ? read_val - 64 : read_val); + lgw_reg_r(LGW_IQ_MISMATCH_A_PHI_COEFF, &read_val); + (*cal_res).phi_a = (int8_t)((read_val > 31) ? read_val - 64 : read_val); + lgw_reg_w(LGW_DBG_AGC_MCU_RAM_ADDR, 0xD0); + lgw_reg_r(LGW_DBG_AGC_MCU_RAM_DATA, &read_val); + (*cal_res).img_rej_a = (uint8_t)read_val; + lgw_reg_w(LGW_DBG_AGC_MCU_RAM_ADDR, 0xD2); + lgw_reg_r(LGW_DBG_AGC_MCU_RAM_DATA, &read_val); + (*cal_res).debug[0] = (uint8_t)read_val; + lgw_reg_w(LGW_DBG_AGC_MCU_RAM_ADDR, 0xD3); + lgw_reg_r(LGW_DBG_AGC_MCU_RAM_DATA, &read_val); + (*cal_res).debug[1] = (uint8_t)read_val; + lgw_reg_w(LGW_DBG_AGC_MCU_RAM_ADDR, 0xD4); + lgw_reg_r(LGW_DBG_AGC_MCU_RAM_DATA, &read_val); + (*cal_res).debug[2] = (uint8_t)read_val; + } + if (cal_cmd & 0x02) { + lgw_reg_r(LGW_IQ_MISMATCH_B_AMP_COEFF, &read_val); + (*cal_res).amp_b = (int8_t)((read_val > 31) ? read_val - 64 : read_val); + lgw_reg_r(LGW_IQ_MISMATCH_B_PHI_COEFF, &read_val); + (*cal_res).phi_b = (int8_t)((read_val > 31) ? read_val - 64 : read_val); + lgw_reg_w(LGW_DBG_AGC_MCU_RAM_ADDR, 0xD1); + lgw_reg_r(LGW_DBG_AGC_MCU_RAM_DATA, &read_val); + (*cal_res).img_rej_b = (uint8_t)read_val; + lgw_reg_w(LGW_DBG_AGC_MCU_RAM_ADDR, 0xD2); + lgw_reg_r(LGW_DBG_AGC_MCU_RAM_DATA, &read_val); + (*cal_res).debug[0] = (uint8_t)read_val; + lgw_reg_w(LGW_DBG_AGC_MCU_RAM_ADDR, 0xD3); + lgw_reg_r(LGW_DBG_AGC_MCU_RAM_DATA, &read_val); + (*cal_res).debug[1] = (uint8_t)read_val; + lgw_reg_w(LGW_DBG_AGC_MCU_RAM_ADDR, 0xD4); + lgw_reg_r(LGW_DBG_AGC_MCU_RAM_DATA, &read_val); + (*cal_res).debug[2] = (uint8_t)read_val; + } + if (cal_cmd & 0x04) { + for (i=0; i<=7; ++i) { + lgw_reg_w(LGW_DBG_AGC_MCU_RAM_ADDR, 0xA0+i); + lgw_reg_r(LGW_DBG_AGC_MCU_RAM_DATA, &read_val); + (*cal_res).offset_i_a[i] = (int8_t)read_val; + lgw_reg_w(LGW_DBG_AGC_MCU_RAM_ADDR, 0xA8+i); + lgw_reg_r(LGW_DBG_AGC_MCU_RAM_DATA, &read_val); + (*cal_res).offset_q_a[i] = (int8_t)read_val; + lgw_reg_w(LGW_DBG_AGC_MCU_RAM_ADDR, 0xC0+i); + lgw_reg_r(LGW_DBG_AGC_MCU_RAM_DATA, &read_val); + (*cal_res).offset_rej_a[i] = (uint8_t)read_val; + lgw_reg_w(LGW_DBG_AGC_MCU_RAM_ADDR, 0xD2+i); + lgw_reg_r(LGW_DBG_AGC_MCU_RAM_DATA, &read_val); + (*cal_res).debug[i] = (uint8_t)read_val; + } + } + if (cal_cmd & 0x08) { + for (i=0; i<=7; ++i) { + lgw_reg_w(LGW_DBG_AGC_MCU_RAM_ADDR, 0xB0+i); + lgw_reg_r(LGW_DBG_AGC_MCU_RAM_DATA, &read_val); + (*cal_res).offset_i_b[i] = (int8_t)read_val; + lgw_reg_w(LGW_DBG_AGC_MCU_RAM_ADDR, 0xB8+i); + lgw_reg_r(LGW_DBG_AGC_MCU_RAM_DATA, &read_val); + (*cal_res).offset_q_b[i] = (int8_t)read_val; + lgw_reg_w(LGW_DBG_AGC_MCU_RAM_ADDR, 0xC8+i); + lgw_reg_r(LGW_DBG_AGC_MCU_RAM_DATA, &read_val); + (*cal_res).offset_rej_b[i] = (uint8_t)read_val; + lgw_reg_w(LGW_DBG_AGC_MCU_RAM_ADDR, 0xD2+i); + lgw_reg_r(LGW_DBG_AGC_MCU_RAM_DATA, &read_val); + (*cal_res).debug[i] = (uint8_t)read_val; + } + } + + return cal_status; +} + +/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ + +int read_capture(int16_t *sig_i, int16_t *sig_q, int nb_samp) { + + uint8_t read_burst[4]; + uint16_t data_i_c2; + uint16_t data_q_c2; + int i; + + lgw_reg_w(LGW_CAPTURE_RAM_ADDR, 0); + for (i=0 ; i<nb_samp ; i++) { + lgw_reg_rb(LGW_CAPTURE_RAM_DATA, read_burst, 4); + data_i_c2 = ((uint16_t)read_burst[3] << 4) + ((uint16_t)read_burst[2] >> 4); + data_q_c2 = ((uint16_t)read_burst[1] << 4) + ((uint16_t)read_burst[0] >> 4); + sig_i[i] = (int16_t)((data_i_c2 > 2047) ? data_i_c2 - 4096 : data_i_c2); + sig_q[i] = (int16_t)((data_q_c2 > 2047) ? data_q_c2 - 4096 : data_q_c2); + } + + return 0; +} + +/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ + +uint8_t get_img_rej(int16_t *sig_i, int16_t *sig_q, int nb_samp, double f_sig_norm) { + + int i; + double phase; + double corr_sig_i, corr_sig_q, corr_sig_abs; + double corr_img_i, corr_img_q, corr_img_abs; + double img_rej; + + corr_sig_i = 0; + corr_sig_q = 0; + corr_img_i = 0; + corr_img_q = 0; + + for (i=0 ; i<nb_samp ; i++) { + phase = 6.28318530717959*i*f_sig_norm; + corr_sig_i += (double)sig_i[i]*cos( phase) - (double)sig_q[i]*sin( phase); + corr_sig_q += (double)sig_q[i]*cos( phase) + (double)sig_i[i]*sin( phase); + corr_img_i += (double)sig_i[i]*cos(-phase) - (double)sig_q[i]*sin(-phase); + corr_img_q += (double)sig_q[i]*cos(-phase) + (double)sig_i[i]*sin(-phase); + } + + corr_sig_abs = sqrt( corr_sig_i*corr_sig_i + corr_sig_q*corr_sig_q ); + corr_img_abs = sqrt( corr_img_i*corr_img_i + corr_img_q*corr_img_q ); + + img_rej = 20*log10(corr_sig_abs/corr_img_abs); + + return (uint8_t)img_rej; +} + + +/* --- EOF ------------------------------------------------------------------ */ @@ -56,6 +56,16 @@ gateways as receivers. 3. Changelog ------------- +### v2.0.0 ### + +* Added support for Kerlink 868 27dBm gateway +* Updated global_conf.eu868.json (in packet logger) to new LoRaWAN frequency plan +* Added version numbers to AGC, arbiter and calibration firmware (those versions are checked at startup) +* Added test_loragw_cal to test radio calibrations +* Fixed minor bug in error coverage in register read/write functions + +/!\ warning: Kerlink 868 27dBm gateway includes a FPGA that MUST be programmed before running any application + ### v1.7.0 ### * Added TX “start delay” compensation for timestamp mode (fix time window alignment issue at low SF and/or high BW) diff --git a/util_pkt_logger/cfg/global_conf.eu868.json b/util_pkt_logger/cfg/global_conf.eu868.json index 2d7ae96..9dbf2f9 100644 --- a/util_pkt_logger/cfg/global_conf.eu868.json +++ b/util_pkt_logger/cfg/global_conf.eu868.json @@ -2,41 +2,75 @@ "SX1301_conf": { "radio_0": { "enable": true, - "freq": 868200000 + "freq": 867500000 + }, + "radio_1": { + "enable": true, + "freq": 868500000 }, "chan_multiSF_0": { - /* LoRa MAC channel, 125kHz, all SF, 868.1 MHz */ + /* Lora MAC channel, 125kHz, all SF, 868.1 MHz */ "enable": true, - "radio": 0, - "if": -100000 + "radio": 1, + "if": -400000 }, "chan_multiSF_1": { - /* LoRa MAC channel, 125kHz, all SF, 868.3 MHz */ + /* Lora MAC channel, 125kHz, all SF, 868.3 MHz */ "enable": true, - "radio": 0, - "if": 100000 + "radio": 1, + "if": -200000 }, "chan_multiSF_2": { - /* LoRa MAC channel, 125kHz, all SF, 868.5 MHz */ + /* Lora MAC channel, 125kHz, all SF, 868.5 MHz */ + "enable": true, + "radio": 1, + "if": 0 + }, + "chan_multiSF_3": { + /* Lora MAC channel, 125kHz, all SF, 867.1 MHz */ "enable": true, "radio": 0, - "if": 300000 + "if": -400000 }, - "chan_Lora_std": { - /* LoRa MAC channel, 250kHz, SF7, 868.3 MHz */ + "chan_multiSF_4": { + /* Lora MAC channel, 125kHz, all SF, 867.3 MHz */ "enable": true, "radio": 0, - "if": 100000, + "if": -200000 + }, + "chan_multiSF_5": { + /* Lora MAC channel, 125kHz, all SF, 867.5 MHz */ + "enable": true, + "radio": 0, + "if": 0 + }, + "chan_multiSF_6": { + /* Lora MAC channel, 125kHz, all SF, 867.7 MHz */ + "enable": true, + "radio": 0, + "if": 200000 + }, + "chan_multiSF_7": { + /* Lora MAC channel, 125kHz, all SF, 867.9 MHz */ + "enable": true, + "radio": 0, + "if": 400000 + }, + "chan_Lora_std": { + /* Lora MAC channel, 250kHz, SF7, 868.3 MHz */ + "enable": true, + "radio": 1, + "if": -200000, "bandwidth": 250000, "spread_factor": 7 }, "chan_FSK": { - /* FSK 100kbps channel, 868.3 MHz */ + /* FSK 50kbps channel, 868.8 MHz */ "enable": true, - "radio": 0, - "if": 100000, - "bandwidth": 250000, - "datarate": 100000 + "radio": 1, + "if": 300000, + "datarate": 50000, + "freq_deviation": 25000 } }, "gateway_conf": { |