diff options
| -rw-r--r-- | multitech/recipes/vizzini/vizzini-0.76/vizzini-0.76-enable-cts.patch | 30 | ||||
| -rw-r--r-- | multitech/recipes/vizzini/vizzini_0.76.bb | 3 |
2 files changed, 32 insertions, 1 deletions
diff --git a/multitech/recipes/vizzini/vizzini-0.76/vizzini-0.76-enable-cts.patch b/multitech/recipes/vizzini/vizzini-0.76/vizzini-0.76-enable-cts.patch new file mode 100644 index 0000000..d4b1211 --- /dev/null +++ b/multitech/recipes/vizzini/vizzini-0.76/vizzini-0.76-enable-cts.patch @@ -0,0 +1,30 @@ +--- a/vizzini.c 2013-03-28 16:37:49.863760786 -0500 ++++ b/vizzini.c 2013-03-28 16:38:57.353205784 -0500 +@@ -95,6 +95,9 @@ + #define READ_URB_RUNNING 0 + #define READ_URB_STOPPED 1 + ++#define UART_PIN_RTS 0x020 ++#define UART_GPIO_DIR 0x01b ++ + static int debug; + + +@@ -559,6 +562,17 @@ + + vizzini_set_reg(port, block, UART_FLOW, flow); + vizzini_set_reg(port, block, UART_GPIO_MODE, gpio_mode); ++ /* if flow control hasn't been turned on, enable RTS for modem-like functionality */ ++ if (flow == UART_FLOW_MODE_NONE) { ++ char value; ++ vizzini_get_reg(port, block, UART_GPIO_DIR, &value); ++ value |= UART_PIN_RTS; ++ vizzini_set_reg(port, block, UART_GPIO_DIR, value); ++ vizzini_get_reg(port, block, UART_GPIO_CLR, &value); ++ value |= UART_PIN_RTS; ++ vizzini_set_reg(port, block, UART_GPIO_CLR, value); ++ } ++ + + if (portdata->trans9) { + /* Turn on wide mode if we're 9-bit transparent. */ diff --git a/multitech/recipes/vizzini/vizzini_0.76.bb b/multitech/recipes/vizzini/vizzini_0.76.bb index d1cc653..52f168e 100644 --- a/multitech/recipes/vizzini/vizzini_0.76.bb +++ b/multitech/recipes/vizzini/vizzini_0.76.bb @@ -1,11 +1,12 @@ require vizzini.inc -LOCAL_PR = "${INC_PR}.1" +LOCAL_PR = "${INC_PR}.2" MACHINE_KERNEL_PR_append = "${LOCAL_PR}" SRC_URI += "file://xr21v141x-lnx-3.0-pak.tar.gz \ file://vizzini-0.76-rs485.patch \ file://vizzini-0.76-flow-control.patch \ + file://vizzini-0.76-enable-cts.patch \ " S = "${WORKDIR}/xr21v141x-lnx-3.0-pak" |