diff options
author | Mike Fiore <mfiore@multitech.com> | 2013-04-24 15:42:30 -0500 |
---|---|---|
committer | Mike Fiore <mfiore@multitech.com> | 2013-04-24 15:42:30 -0500 |
commit | 894f5b81ade2057d43ca2867182b566f669e77a2 (patch) | |
tree | 1596f90582dcbc23ad3940f68a5bddfd2ff49c9e | |
parent | 1bb7b3ba294c40018b069cfac77a78e9450bb62b (diff) | |
parent | a85ef99b6816c1b072dcd2ac0f73fb078d100801 (diff) |
Merge branch 'master' of git.multitech.net:corecdp
8 files changed, 161 insertions, 71 deletions
diff --git a/multitech/conf/machine/mtocgd3.conf b/multitech/conf/machine/mtocgd3.conf index 4eab275..0960870 100644 --- a/multitech/conf/machine/mtocgd3.conf +++ b/multitech/conf/machine/mtocgd3.conf @@ -15,7 +15,7 @@ UBOOT_MACHINE = "at91sam9x5ek_nandflash_config" PREFERRED_VERSION_u-boot = "2012.10" AT91BOOTSTRAP_BOARD = "at91sam9x5eknf_uboot" -PREFERRED_VERSION_at91bootstrap = "3.5.2" +PREFERRED_VERSION_at91bootstrap = "3.5.3" #don't try to access tty1 USE_VT = "0" diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/mtocgd3/at91bootstrap-3.5.2-mtocgd3.patch b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/mtocgd3/at91bootstrap-3.5.2-mtocgd3.patch deleted file mode 100644 index 97ae327..0000000 --- a/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/mtocgd3/at91bootstrap-3.5.2-mtocgd3.patch +++ /dev/null @@ -1,65 +0,0 @@ -Index: at91bootstrap-3.5.2/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig -=================================================================== ---- at91bootstrap-3.5.2.orig/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig 2013-02-08 14:05:34.034501648 -0600 -+++ at91bootstrap-3.5.2/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig 2013-02-08 14:07:19.010677033 -0600 -@@ -42,7 +42,8 @@ - ALLOW_PIO3=y - CONFIG_HAS_PIO3=y - CPU_HAS_PMECC=y --CONFIG_LOAD_ONE_WIRE=y -+# MTS: don't load one wire -+# CONFIG_LOAD_ONE_WIRE is not set - - # - # Memory selection -@@ -102,4 +103,5 @@ - # CONFIG_USER_HW_INIT is not set - CONFIG_THUMB=y - CONFIG_SCLK=y --CONFIG_DISABLE_WATCHDOG=y -+# MTS: don't disable watchdog -+# CONFIG_DISABLE_WATCHDOG is not set -Index: at91bootstrap-3.5.2/board/at91sam9x5ek/at91sam9x5ek.h -=================================================================== ---- at91bootstrap-3.5.2.orig/board/at91sam9x5ek/at91sam9x5ek.h 2013-02-08 14:03:42.050364515 -0600 -+++ at91bootstrap-3.5.2/board/at91sam9x5ek/at91sam9x5ek.h 2013-02-08 14:07:56.500399983 -0600 -@@ -95,7 +95,8 @@ - #define CONFIG_SYS_NAND_CLE_PIN AT91C_PIN_PD(3) - #define CONFIG_SYS_NAND_ENABLE_PIN AT91C_PIN_PD(4) - --#define PMECC_ERROR_CORR_BITS 2 -+/* MTS: use 4-bit PMECC */ -+#define PMECC_ERROR_CORR_BITS 4 - #define PMECC_SECTOR_SIZE 512 - - #define CONFIG_LOOKUP_TABLE_ALPHA_OFFSET 0xC000 -Index: at91bootstrap-3.5.2/board/at91sam9x5ek/at91sam9x5ek.c -=================================================================== ---- at91bootstrap-3.5.2.orig/board/at91sam9x5ek/at91sam9x5ek.c 2013-02-08 14:03:57.562179405 -0600 -+++ at91bootstrap-3.5.2/board/at91sam9x5ek/at91sam9x5ek.c 2013-02-08 14:11:56.477737850 -0600 -@@ -268,10 +268,9 @@ - - reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA); - reg |= AT91C_EBI_CS3A_SM; -- if ((get_cm_rev() == 'A') && (get_cm_vendor() == VENDOR_EMBEST)) -- reg &= ~AT91C_EBI_NFD0_ON_D16; -- else -- reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16); -+ /* MTR2 Rev A NAND is on D0-D7, DDR_MP_EN must be disabled */ -+ reg &= ~AT91C_EBI_NFD0_ON_D16; -+ reg &= ~AT91C_EBI_DDR_MP_EN; - - reg &= ~AT91C_EBI_DRV; - writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA); -@@ -300,10 +299,7 @@ - | AT91_SMC_TDF_(1)), - AT91C_BASE_SMC + SMC_CTRL3); - -- /* Configure the PIO controller */ -- if ((get_cm_rev() == 'A') && (get_cm_vendor() == VENDOR_EMBEST)) -- pio_configure(nand_pins_lo); -- else -+ /* MTR2 */ - pio_configure(nand_pins_hi); - - writel((1 << AT91C_ID_PIOC_D), (PMC_PCER + AT91C_BASE_PMC)); diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/at91bootstrap-3.5.2-add-install.patch b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-add-install.patch index 6f007b9..6f007b9 100644 --- a/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/at91bootstrap-3.5.2-add-install.patch +++ b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-add-install.patch diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-onetime-slow-clock-switch.patch b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-onetime-slow-clock-switch.patch new file mode 100644 index 0000000..98ccd41 --- /dev/null +++ b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-onetime-slow-clock-switch.patch @@ -0,0 +1,91 @@ +Index: at91bootstrap-3.5.2/driver/at91_slowclk.c +=================================================================== +--- at91bootstrap-3.5.2.orig/driver/at91_slowclk.c 2013-01-30 04:01:20.000000000 -0600 ++++ at91bootstrap-3.5.2/driver/at91_slowclk.c 2013-04-24 11:35:44.369827054 -0500 +@@ -33,12 +33,17 @@ + { + unsigned int reg; + +- /* +- * Enable the 32768 Hz oscillator by setting the bit OSC32EN to 1 +- */ ++ + reg = readl(AT91C_BASE_SCKCR); +- reg |= AT91C_SLCKSEL_OSC32EN; +- writel(reg, AT91C_BASE_SCKCR); ++ ++ /* Only enable 32768 Hz oscillator if needed */ ++ if ( !(reg & AT91C_SLCKSEL_OSC32EN) ) { ++ /* ++ * Enable the 32768 Hz oscillator by setting the bit OSC32EN to 1 ++ */ ++ reg |= AT91C_SLCKSEL_OSC32EN; ++ writel(reg, AT91C_BASE_SCKCR); ++ } + + /* start a internal timer */ + start_interval_timer(); +@@ -50,32 +55,40 @@ + { + unsigned int reg; + +- /* +- * Wait 32768 Hz Startup Time for clock stabilization (software loop) +- * wait about 1s (1000ms) +- */ +- wait_interval_timer(1000); +- +- /* +- * Switching from internal 32kHz RC oscillator to 32768 Hz oscillator +- * by setting the bit OSCSEL to 1 +- */ + reg = readl(AT91C_BASE_SCKCR); +- reg |= AT91C_SLCKSEL_OSCSEL; +- writel(reg, AT91C_BASE_SCKCR); + +- /* +- * Waiting 5 slow clock cycles for internal resynchronization +- * 5 slow clock cycles = ~153 us (5 / 32768) +- */ +- udelay(153); +- +- /* +- * Disable the 32kHz RC oscillator by setting the bit RCEN to 0 +- */ ++ /* Only switch clock source if needed */ ++ if ( !(reg & AT91C_SLCKSEL_OSCSEL) ) { ++ dbgu_print("Switching slow clock to external oscillator...\n\r"); ++ /* ++ * Wait 32768 Hz Startup Time for clock stabilization (software loop) ++ * wait about 1s (1000ms) ++ */ ++ wait_interval_timer(1000); ++ ++ /* ++ * Switching from internal 32kHz RC oscillator to 32768 Hz oscillator ++ * by setting the bit OSCSEL to 1 ++ */ ++ reg |= AT91C_SLCKSEL_OSCSEL; ++ writel(reg, AT91C_BASE_SCKCR); ++ ++ /* ++ * Waiting 5 slow clock cycles for internal resynchronization ++ * 5 slow clock cycles = ~153 us (5 / 32768) ++ */ ++ udelay(153); ++ } ++ ++ /* Only disable internal RC oscillator if needed */ + reg = readl(AT91C_BASE_SCKCR); +- reg &= ~AT91C_SLCKSEL_RCEN; +- writel(reg, AT91C_BASE_SCKCR); ++ if (reg | AT91C_SLCKSEL_RCEN) { ++ /* ++ * Disable the 32kHz RC oscillator by setting the bit RCEN to 0 ++ */ ++ reg &= ~AT91C_SLCKSEL_RCEN; ++ writel(reg, AT91C_BASE_SCKCR); ++ } + + return 0; + } diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/at91sam9x5_4bit_pmecc_header.bin b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/at91sam9x5_4bit_pmecc_header.bin index f8d6073..f8d6073 100644 --- a/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/at91sam9x5_4bit_pmecc_header.bin +++ b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/at91sam9x5_4bit_pmecc_header.bin diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/create_4bit_pmecc_header.rb b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/create_4bit_pmecc_header.rb index 780d728..780d728 100755 --- a/multitech/recipes/at91bootstrap/at91bootstrap-3.5.2/create_4bit_pmecc_header.rb +++ b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/create_4bit_pmecc_header.rb diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/mtocgd3/at91bootstrap-3.5.3-mtocgd3.patch b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/mtocgd3/at91bootstrap-3.5.3-mtocgd3.patch new file mode 100644 index 0000000..4e3aac0 --- /dev/null +++ b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/mtocgd3/at91bootstrap-3.5.3-mtocgd3.patch @@ -0,0 +1,63 @@ +Index: at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig +=================================================================== +--- at91bootstrap-3.5.3.orig/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig 2013-04-11 05:07:35.000000000 -0500 ++++ at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig 2013-04-24 11:49:10.237842512 -0500 +@@ -42,7 +42,8 @@ + ALLOW_PIO3=y + CONFIG_HAS_PIO3=y + CPU_HAS_PMECC=y +-CONFIG_LOAD_ONE_WIRE=y ++# MTS: don't load one wire ++# CONFIG_LOAD_ONE_WIRE is not set + # CONFIG_MMC_SUPPORT is not set + + # +@@ -81,8 +82,8 @@ + # + # PMECC Configuration + # +-CONFIG_PMECC_CORRECT_BITS_2=y +-# CONFIG_PMECC_CORRECT_BITS_4 is not set ++# CONFIG_PMECC_CORRECT_BITS_2 is not set ++CONFIG_PMECC_CORRECT_BITS_4=y + # CONFIG_PMECC_CORRECT_BITS_8 is not set + # CONFIG_PMECC_CORRECT_BITS_12 is not set + # CONFIG_PMECC_CORRECT_BITS_24 is not set +@@ -116,4 +117,5 @@ + # CONFIG_USER_HW_INIT is not set + CONFIG_THUMB=y + CONFIG_SCLK=y +-CONFIG_DISABLE_WATCHDOG=y ++# MTS: don't disable watchdog ++# CONFIG_DISABLE_WATCHDOG is not set +Index: at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c +=================================================================== +--- at91bootstrap-3.5.3.orig/board/at91sam9x5ek/at91sam9x5ek.c 2013-04-11 05:07:35.000000000 -0500 ++++ at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c 2013-04-24 11:53:09.981847111 -0500 +@@ -312,10 +312,9 @@ + + reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA); + reg |= AT91C_EBI_CS3A_SM; +- if (get_cm_rev() == 'A') +- reg &= ~AT91C_EBI_NFD0_ON_D16; +- else +- reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16); ++ /* MTR2 Rev A NAND is on D0-D7, DDR_MP_EN must be disabled */ ++ reg &= ~AT91C_EBI_NFD0_ON_D16; ++ reg &= ~AT91C_EBI_DDR_MP_EN; + + reg &= ~AT91C_EBI_DRV; + writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA); +@@ -345,10 +344,8 @@ + AT91C_BASE_SMC + SMC_CTRL3); + + /* Configure the PIO controller */ +- if (get_cm_rev() == 'A') +- pio_configure(nand_pins_lo); +- else +- pio_configure(nand_pins_hi); ++ /* MTR2 */ ++ pio_configure(nand_pins_lo); + + writel((1 << AT91C_ID_PIOC_D), (PMC_PCER + AT91C_BASE_PMC)); + } diff --git a/multitech/recipes/at91bootstrap/at91bootstrap_3.5.2.bb b/multitech/recipes/at91bootstrap/at91bootstrap_3.5.3.bb index 0957496..7fa01bc 100644 --- a/multitech/recipes/at91bootstrap/at91bootstrap_3.5.2.bb +++ b/multitech/recipes/at91bootstrap/at91bootstrap_3.5.3.bb @@ -2,15 +2,16 @@ require at91bootstrap_3.5.inc PR = "r0" -SRC_URI = "https://github.com/linux4sam/at91bootstrap/archive/v3.5.2.tar.gz \ - file://at91bootstrap-3.5.2-add-install.patch" +SRC_URI = "https://github.com/linux4sam/at91bootstrap/archive/v3.5.3.tar.gz \ + file://at91bootstrap-3.5.2-add-install.patch \ + file://at91bootstrap-3.5.2-onetime-slow-clock-switch.patch" -SRC_URI_append_mtocgd3 = " file://at91bootstrap-3.5.2-mtocgd3.patch \ +SRC_URI_append_mtocgd3 = " file://at91bootstrap-3.5.3-mtocgd3.patch \ file://at91sam9x5_4bit_pmecc_header.bin \ " -SRC_URI[md5sum] = "5f818dcd0d4d0fe1f0447b35d3f050eb" -SRC_URI[sha256sum] = "cea3d75470000f1eff64e1f9dd356a1d7264b0a33b8af9e9461ab64653a6b6fb" +SRC_URI[md5sum] = "7379726f686f5b9c8f4a2012676b79fc" +SRC_URI[sha256sum] = "6c2289671f1c3cf317114b2e82955f98e860dda8c706d5c1e80c0bbebc6c5b12" # generate a bootstrap file padded with the header needed for 4-bit PMECC # The padded file can be flashed via u-boot without any need to set the PMECC header using SAM-BA |