at91bootstrap: add 3.5.3 with onetime-slow-clock-switch patch

Added patch to only switch slow clock to external oscillator if needed.

This improves the reliability of starting up the board.

6 files changed, 206 insertions, 0 deletions

diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-add-install.patch b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-add-install.patch
new file mode 100644
index 0000000..6f007b9
--- /dev/null
+++ b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-add-install.patch
@@ -0,0 +1,20 @@
+Index: at91bootstrap-3.5.2/Makefile
+===================================================================
+--- at91bootstrap-3.5.2.orig/Makefile	2013-02-08 14:38:40.660054339 -0600
++++ at91bootstrap-3.5.2/Makefile	2013-02-08 14:41:30.626272862 -0600
+@@ -359,4 +359,15 @@
+ 
+ PHONY+=tarball tarballx
+ 
++install:
++	-install -d $(DESTDIR)
++	install $(AT91BOOTSTRAP) $(DESTDIR)/$(IMAGE)
++	-rm -f $(DESTDIR)/$(SYMLINK)
++	(cd ${DESTDIR} ; \
++	ln -sf ${IMAGE} ${SYMLINK} \
++	)
++
++
++PHONY+=install
++
+ .PHONY: $(PHONY)
diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-onetime-slow-clock-switch.patch b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-onetime-slow-clock-switch.patch
new file mode 100644
index 0000000..98ccd41
--- /dev/null
+++ b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/at91bootstrap-3.5.2-onetime-slow-clock-switch.patch
@@ -0,0 +1,91 @@
+Index: at91bootstrap-3.5.2/driver/at91_slowclk.c
+===================================================================
+--- at91bootstrap-3.5.2.orig/driver/at91_slowclk.c	2013-01-30 04:01:20.000000000 -0600
++++ at91bootstrap-3.5.2/driver/at91_slowclk.c	2013-04-24 11:35:44.369827054 -0500
+@@ -33,12 +33,17 @@
+ {
+ 	unsigned int reg;
+ 
+-	/*
+-	 * Enable the 32768 Hz oscillator by setting the bit OSC32EN to 1
+-	 */
++
+ 	reg = readl(AT91C_BASE_SCKCR);
+-	reg |= AT91C_SLCKSEL_OSC32EN;
+-	writel(reg, AT91C_BASE_SCKCR);
++
++	/* Only enable 32768 Hz oscillator if needed */
++	if ( !(reg & AT91C_SLCKSEL_OSC32EN) ) {
++		/*
++	 	 * Enable the 32768 Hz oscillator by setting the bit OSC32EN to 1
++	 	 */
++		reg |= AT91C_SLCKSEL_OSC32EN;
++		writel(reg, AT91C_BASE_SCKCR);
++	}
+ 
+ 	/* start a internal timer */
+ 	start_interval_timer();
+@@ -50,32 +55,40 @@
+ {
+ 	unsigned int reg;
+ 
+-	/*
+-	 * Wait 32768 Hz Startup Time for clock stabilization (software loop)
+-	 * wait about 1s (1000ms)
+-	 */
+-	wait_interval_timer(1000);
+-
+-	/*
+-	 * Switching from internal 32kHz RC oscillator to 32768 Hz oscillator
+-	 * by setting the bit OSCSEL to 1
+-	 */
+ 	reg = readl(AT91C_BASE_SCKCR);
+-	reg |= AT91C_SLCKSEL_OSCSEL;
+-	writel(reg, AT91C_BASE_SCKCR);
+ 
+-	/*
+-	 * Waiting 5 slow clock cycles for internal resynchronization
+-	 * 5 slow clock cycles = ~153 us (5 / 32768)
+-	 */
+-	udelay(153);
+-
+-	/*
+-	 * Disable the 32kHz RC oscillator by setting the bit RCEN to 0
+-	 */
++	/* Only switch clock source if needed */
++	if ( !(reg & AT91C_SLCKSEL_OSCSEL) ) {
++		dbgu_print("Switching slow clock to external oscillator...\n\r");
++		/*
++		 * Wait 32768 Hz Startup Time for clock stabilization (software loop)
++		 * wait about 1s (1000ms)
++		 */
++		wait_interval_timer(1000);
++
++		/*
++		 * Switching from internal 32kHz RC oscillator to 32768 Hz oscillator
++		 * by setting the bit OSCSEL to 1
++		 */
++		reg |= AT91C_SLCKSEL_OSCSEL;
++		writel(reg, AT91C_BASE_SCKCR);
++
++		/*
++		 * Waiting 5 slow clock cycles for internal resynchronization
++		 * 5 slow clock cycles = ~153 us (5 / 32768)
++		 */
++		udelay(153);
++	}
++
++	/* Only disable internal RC oscillator if needed */
+ 	reg = readl(AT91C_BASE_SCKCR);
+-	reg &= ~AT91C_SLCKSEL_RCEN;
+-	writel(reg, AT91C_BASE_SCKCR);
++	if (reg | AT91C_SLCKSEL_RCEN) {
++		/*
++		 * Disable the 32kHz RC oscillator by setting the bit RCEN to 0
++		 */
++		reg &= ~AT91C_SLCKSEL_RCEN;
++		writel(reg, AT91C_BASE_SCKCR);
++	}
+ 
+ 	return 0;
+ }
diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/at91sam9x5_4bit_pmecc_header.bin b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/at91sam9x5_4bit_pmecc_header.bin
new file mode 100644
index 0000000..f8d6073
--- /dev/null
+++ b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/at91sam9x5_4bit_pmecc_header.bin
@@ -0,0 +1 @@
+$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��$��
\ No newline at end of file
diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/create_4bit_pmecc_header.rb b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/create_4bit_pmecc_header.rb
new file mode 100755
index 0000000..780d728
--- /dev/null
+++ b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/create_4bit_pmecc_header.rb
@@ -0,0 +1,5 @@
+#!/usr/bin/env ruby
+
+52.times do 
+	print ["052490c0"].pack('H*')
+end
diff --git a/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/mtocgd3/at91bootstrap-3.5.3-mtocgd3.patch b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/mtocgd3/at91bootstrap-3.5.3-mtocgd3.patch
new file mode 100644
index 0000000..4e3aac0
--- /dev/null
+++ b/multitech/recipes/at91bootstrap/at91bootstrap-3.5.3/mtocgd3/at91bootstrap-3.5.3-mtocgd3.patch
@@ -0,0 +1,63 @@
+Index: at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig
+===================================================================
+--- at91bootstrap-3.5.3.orig/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig	2013-04-11 05:07:35.000000000 -0500
++++ at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5eknf_uboot_defconfig	2013-04-24 11:49:10.237842512 -0500
+@@ -42,7 +42,8 @@
+ ALLOW_PIO3=y
+ CONFIG_HAS_PIO3=y
+ CPU_HAS_PMECC=y
+-CONFIG_LOAD_ONE_WIRE=y
++# MTS: don't load one wire
++# CONFIG_LOAD_ONE_WIRE is not set
+ # CONFIG_MMC_SUPPORT is not set
+ 
+ #
+@@ -81,8 +82,8 @@
+ #
+ # PMECC Configuration
+ #
+-CONFIG_PMECC_CORRECT_BITS_2=y
+-# CONFIG_PMECC_CORRECT_BITS_4 is not set
++# CONFIG_PMECC_CORRECT_BITS_2 is not set
++CONFIG_PMECC_CORRECT_BITS_4=y
+ # CONFIG_PMECC_CORRECT_BITS_8 is not set
+ # CONFIG_PMECC_CORRECT_BITS_12 is not set
+ # CONFIG_PMECC_CORRECT_BITS_24 is not set
+@@ -116,4 +117,5 @@
+ # CONFIG_USER_HW_INIT is not set
+ CONFIG_THUMB=y
+ CONFIG_SCLK=y
+-CONFIG_DISABLE_WATCHDOG=y
++# MTS: don't disable watchdog
++# CONFIG_DISABLE_WATCHDOG is not set
+Index: at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c
+===================================================================
+--- at91bootstrap-3.5.3.orig/board/at91sam9x5ek/at91sam9x5ek.c	2013-04-11 05:07:35.000000000 -0500
++++ at91bootstrap-3.5.3/board/at91sam9x5ek/at91sam9x5ek.c	2013-04-24 11:53:09.981847111 -0500
+@@ -312,10 +312,9 @@
+ 
+ 	reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
+ 	reg |= AT91C_EBI_CS3A_SM;
+-	if (get_cm_rev() == 'A')
+-		reg &= ~AT91C_EBI_NFD0_ON_D16;
+-	else
+-		reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
++	/* MTR2 Rev A NAND is on D0-D7, DDR_MP_EN must be disabled */
++	reg &= ~AT91C_EBI_NFD0_ON_D16;
++	reg &= ~AT91C_EBI_DDR_MP_EN;
+ 
+ 	reg &= ~AT91C_EBI_DRV;
+ 	writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
+@@ -345,10 +344,8 @@
+ 		AT91C_BASE_SMC + SMC_CTRL3);
+ 
+ 	/* Configure the PIO controller */
+-	if (get_cm_rev() == 'A')
+-		pio_configure(nand_pins_lo);
+-	else
+-		pio_configure(nand_pins_hi);
++	/* MTR2 */
++	pio_configure(nand_pins_lo);
+ 
+ 	writel((1 << AT91C_ID_PIOC_D), (PMC_PCER + AT91C_BASE_PMC));
+ }
diff --git a/multitech/recipes/at91bootstrap/at91bootstrap_3.5.3.bb b/multitech/recipes/at91bootstrap/at91bootstrap_3.5.3.bb
new file mode 100644
index 0000000..7fa01bc
--- /dev/null
+++ b/multitech/recipes/at91bootstrap/at91bootstrap_3.5.3.bb
@@ -0,0 +1,26 @@
+require at91bootstrap_3.5.inc
+
+PR = "r0"
+
+SRC_URI = "https://github.com/linux4sam/at91bootstrap/archive/v3.5.3.tar.gz \
+		file://at91bootstrap-3.5.2-add-install.patch \
+		file://at91bootstrap-3.5.2-onetime-slow-clock-switch.patch"
+
+SRC_URI_append_mtocgd3 = " file://at91bootstrap-3.5.3-mtocgd3.patch \
+                      file://at91sam9x5_4bit_pmecc_header.bin \
+		      "
+
+SRC_URI[md5sum] = "7379726f686f5b9c8f4a2012676b79fc"
+SRC_URI[sha256sum] = "6c2289671f1c3cf317114b2e82955f98e860dda8c706d5c1e80c0bbebc6c5b12"
+
+# generate a bootstrap file padded with the header needed for 4-bit PMECC
+# The padded file can be flashed via u-boot without any need to set the PMECC header using SAM-BA
+do_pad_4bit_pmecc() {
+	cp -f ${WORKDIR}/at91sam9x5_4bit_pmecc_header.bin ${DEPLOY_DIR_IMAGE}/at91bootstrap_pmecc_padded.bin
+	cat ${DEPLOY_DIR_IMAGE}/at91bootstrap.bin >> ${DEPLOY_DIR_IMAGE}/at91bootstrap_pmecc_padded.bin
+}
+
+do_install_append_mtocgd3() {
+	do_pad_4bit_pmecc
+}
+