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-rw-r--r--meta/classes/siteinfo.bbclass50
1 files changed, 36 insertions, 14 deletions
diff --git a/meta/classes/siteinfo.bbclass b/meta/classes/siteinfo.bbclass
index 1b3906c1a0..2c33732be3 100644
--- a/meta/classes/siteinfo.bbclass
+++ b/meta/classes/siteinfo.bbclass
@@ -36,7 +36,11 @@ def siteinfo_data(d):
"mips": "endian-big bit-32 mips-common",
"mips64": "endian-big bit-64 mips-common",
"mips64el": "endian-little bit-64 mips-common",
+ "mipsisa64r6": "endian-big bit-64 mips-common",
+ "mipsisa64r6el": "endian-little bit-64 mips-common",
"mipsel": "endian-little bit-32 mips-common",
+ "mipsisa32r6": "endian-big bit-32 mips-common",
+ "mipsisa32r6el": "endian-little bit-32 mips-common",
"powerpc": "endian-big bit-32 powerpc-common",
"nios2": "endian-little bit-32 nios2-common",
"powerpc64": "endian-big bit-64 powerpc-common",
@@ -71,6 +75,8 @@ def siteinfo_data(d):
targetinfo = {
"aarch64-linux-gnu": "aarch64-linux",
"aarch64_be-linux-gnu": "aarch64_be-linux",
+ "aarch64-linux-musl": "aarch64-linux",
+ "aarch64_be-linux-musl": "aarch64_be-linux",
"arm-linux-gnueabi": "arm-linux",
"arm-linux-musleabi": "arm-linux",
"arm-linux-uclibceabi": "arm-linux-uclibc",
@@ -79,10 +85,12 @@ def siteinfo_data(d):
"armeb-linux-musleabi": "armeb-linux",
"mips-linux-musl": "mips-linux",
"mipsel-linux-musl": "mipsel-linux",
- "mips64-linux-musl": "mips-linux",
- "mips64el-linux-musl": "mipsel-linux",
+ "mips64-linux-musl": "mips64-linux",
+ "mips64el-linux-musl": "mips64el-linux",
"mips64-linux-gnun32": "mips-linux bit-32",
"mips64el-linux-gnun32": "mipsel-linux bit-32",
+ "mipsisa64r6-linux-gnun32": "mipsisa32r6-linux bit-32",
+ "mipsisa64r6el-linux-gnun32": "mipsisa32r6el-linux bit-32",
"powerpc-linux": "powerpc32-linux",
"powerpc-linux-musl": "powerpc-linux powerpc32-linux",
"powerpc-linux-uclibc": "powerpc-linux powerpc32-linux",
@@ -92,6 +100,7 @@ def siteinfo_data(d):
"powerpc64-linux-gnuspe": "powerpc-linux powerpc64-linux",
"powerpc64-linux-muslspe": "powerpc-linux powerpc64-linux",
"powerpc64-linux": "powerpc-linux",
+ "powerpc64-linux-musl": "powerpc-linux",
"x86_64-cygwin": "bit-64",
"x86_64-darwin": "bit-64",
"x86_64-darwin9": "bit-64",
@@ -104,8 +113,16 @@ def siteinfo_data(d):
"x86_64-mingw32": "bit-64",
}
- hostarch = d.getVar("HOST_ARCH", True)
- hostos = d.getVar("HOST_OS", True)
+ # Add in any extra user supplied data which may come from a BSP layer, removing the
+ # need to always change this class directly
+ extra_siteinfo = (d.getVar("SITEINFO_EXTRA_DATAFUNCS") or "").split()
+ for m in extra_siteinfo:
+ call = m + "(archinfo, osinfo, targetinfo, d)"
+ locs = { "archinfo" : archinfo, "osinfo" : osinfo, "targetinfo" : targetinfo, "d" : d}
+ archinfo, osinfo, targetinfo = bb.utils.better_eval(call, locs)
+
+ hostarch = d.getVar("HOST_ARCH")
+ hostos = d.getVar("HOST_OS")
target = "%s-%s" % (hostarch, hostos)
sitedata = []
@@ -129,7 +146,7 @@ python () {
d.setVar("SITEINFO_ENDIANNESS", "be")
else:
bb.error("Unable to determine endianness for architecture '%s'" %
- d.getVar("HOST_ARCH", True))
+ d.getVar("HOST_ARCH"))
bb.fatal("Please add your architecture to siteinfo.bbclass")
if "bit-32" in sitedata:
@@ -138,32 +155,37 @@ python () {
d.setVar("SITEINFO_BITS", "64")
else:
bb.error("Unable to determine bit size for architecture '%s'" %
- d.getVar("HOST_ARCH", True))
+ d.getVar("HOST_ARCH"))
bb.fatal("Please add your architecture to siteinfo.bbclass")
}
-def siteinfo_get_files(d, no_cache = False):
+def siteinfo_get_files(d, aclocalcache = False):
sitedata = siteinfo_data(d)
sitefiles = ""
- for path in d.getVar("BBPATH", True).split(":"):
+ for path in d.getVar("BBPATH").split(":"):
for element in sitedata:
filename = os.path.join(path, "site", element)
if os.path.exists(filename):
sitefiles += filename + " "
- if no_cache: return sitefiles
+ if not aclocalcache:
+ return sitefiles
- # Now check for siteconfig cache files
- # Use the files copied to the aclocal cache generated by autotools.bbclass
- # to avoid races
- path_siteconfig = d.getVar('ACLOCALDIR', True)
+ # Now check for siteconfig cache files in the directory setup by autotools.bbclass to
+ # avoid races.
+ #
+ # ACLOCALDIR may or may not exist so cache should only be set to True from autotools.bbclass
+ # after files have been copied into this location. To do otherwise risks parsing/signature
+ # issues and the directory being created/removed whilst this code executes. This can happen
+ # when a multilib recipe is parsed along with its base variant which may be running at the time
+ # causing rare but nasty failures
+ path_siteconfig = d.getVar('ACLOCALDIR')
if path_siteconfig and os.path.isdir(path_siteconfig):
for i in os.listdir(path_siteconfig):
if not i.endswith("_config"):
continue
filename = os.path.join(path_siteconfig, i)
sitefiles += filename + " "
-
return sitefiles
#