Add initial cmx270 2.6.17 kernel

git-svn-id: https://svn.o-hand.com/repos/poky/trunk@528 311d38ba-8fff-0310-9ca6-ca027cbcb966

7 files changed, 4627 insertions, 0 deletions

diff --git a/openembedded/packages/linux/linux-cmx270-2.6.17/add_2700g_plat-r0.patch b/openembedded/packages/linux/linux-cmx270-2.6.17/add_2700g_plat-r0.patch
new file mode 100644
index 0000000000..b4a33e2cf7
--- /dev/null
+++ b/openembedded/packages/linux/linux-cmx270-2.6.17/add_2700g_plat-r0.patch
@@ -0,0 +1,126 @@
+Index: linux-2.6.17/arch/arm/mach-pxa/cm-x270.c
+===================================================================
+--- linux-2.6.17.orig/arch/arm/mach-pxa/cm-x270.c	2006-07-18 15:40:10.000000000 +0100
++++ linux-2.6.17/arch/arm/mach-pxa/cm-x270.c	2006-07-20 20:25:22.000000000 +0100
+@@ -11,6 +11,7 @@
+ #include <linux/pm.h>
+ #include <linux/fb.h>
+ #include <linux/rtc-v3020.h>
++#include <linux/mbxfb.h>
+ 
+ #include <asm/types.h>
+ #include <asm/setup.h>
+@@ -396,10 +397,113 @@
+ 	.resource = dm9000_resources,
+ };
+ 
++/* 2700G graphics */
++static u64 fb_dma_mask = ~(u64)0;
++
++static struct resource cmx270_2700G_resource[] = {
++       /* frame buffer memory including ODFB and External SDRAM */
++       [0] = {
++               .start = MARATHON_PHYS,
++               .end   = MARATHON_PHYS + 0x02000000,
++               .flags = IORESOURCE_MEM,
++       },
++       /* Marathon registers */
++       [1] = {
++               .start = MARATHON_PHYS + 0x03fe0000,
++               .end   = MARATHON_PHYS + 0x03ffffff,
++               .flags = IORESOURCE_MEM,
++       },
++};
++
++static unsigned long save_lcd_regs[10];
++
++/* if 2700G is used, disable PCI throttle */
++#define LB_TROTTLE_OFF (PXA_CS1_PHYS | (1 << 25))
++#define LB_TROTTLE_MAX (PXA_CS1_PHYS | (1 << 25) | (1 << 22))
++static int cmx270_marathon_probe(struct fb_info *fb)
++{
++       volatile unsigned long *cpld;
++       
++       cpld = (volatile unsigned long*)ioremap(LB_TROTTLE_OFF, 4);
++       if ( !cpld ) {
++               return -ENODEV;
++       }
++       *cpld = 0;
++       iounmap((void*)cpld);
++
++       /* save PXA-270 pin settings before enabling 2700G */
++       save_lcd_regs[0] = GPDR1;
++       save_lcd_regs[1] = GPDR2;
++       save_lcd_regs[2] = GAFR1_U;
++       save_lcd_regs[3] = GAFR2_L;
++       save_lcd_regs[4] = GAFR2_U;
++
++       /* Disable PXA-270 on-chip controller driving pins */
++       GPDR1 &= ~(0xfc000000);
++       GPDR2 &= ~(0x00c03fff);
++       GAFR1_U &= ~(0xfff00000);
++       GAFR2_L &= ~(0x0fffffff);
++       GAFR2_U &= ~(0x0000f000);
++       return 0;
++}
++
++static int cmx270_marathon_remove(struct fb_info *fb)
++{
++       volatile unsigned long *cpld;
++       cpld = (volatile unsigned long*)ioremap(LB_TROTTLE_MAX, 4);
++       
++       if ( !cpld ) {
++               return -ENODEV;
++       }
++       *cpld = 0;
++       iounmap((void*)cpld);
++
++       GPDR1 =   save_lcd_regs[0];
++       GPDR2 =   save_lcd_regs[1];
++       GAFR1_U = save_lcd_regs[2];
++       GAFR2_L = save_lcd_regs[3];
++       GAFR2_U = save_lcd_regs[4];
++       return 0;
++}
++
++static struct mbxfb_platform_data cmx270_2700G_data = {
++       .xres = {
++               .min = 240,
++               .max = 1200,
++               .defval = 640,
++       },
++       .yres = { 
++               .min = 240,
++               .max = 1200,
++               .defval = 480,
++       },
++       .bpp = {
++               .min = 16,
++               .max = 32,
++               .defval = 16,
++       },
++       .memsize = 8*1024*1024,
++       .probe = cmx270_marathon_probe,
++       .remove = cmx270_marathon_remove,
++};
++
++static struct platform_device cmx270_2700G = {
++       .name           = "mbx-fb",
++       .dev            = {
++               .platform_data  = &cmx270_2700G_data,
++               .dma_mask       = &fb_dma_mask,
++               .coherent_dma_mask = 0xffffffff,
++       },
++       .num_resources  = ARRAY_SIZE(cmx270_2700G_resource),
++       .resource       = cmx270_2700G_resource,
++       .id             = -1,
++};
++
+ static struct platform_device *platform_devices[] __initdata = {\
+ 	&cmx270_audio_device,
+ 	&v3020_rtc_device,
+ 	&dm9000_device,
++	&cmx270_2700G,
+ };
+ 
+ static int cmx270_ohci_init(struct device *dev)
diff --git a/openembedded/packages/linux/linux-cmx270-2.6.17/cm_x2xx_mbx.patch b/openembedded/packages/linux/linux-cmx270-2.6.17/cm_x2xx_mbx.patch
new file mode 100644
index 0000000000..d33f4522f8
--- /dev/null
+++ b/openembedded/packages/linux/linux-cmx270-2.6.17/cm_x2xx_mbx.patch
@@ -0,0 +1,1566 @@
+ drivers/video/Kconfig        |   10 +
+ drivers/video/Makefile       |    1 
+ drivers/video/mbx/Makefile   |    3 
+ drivers/video/mbx/mbxfb.c    |  646 ++++++++++++++++++++++++++++++++++++++++++
+ drivers/video/mbx/mbxsysfs.c |  129 ++++++++
+ drivers/video/mbx/reg_bits.h |  489 ++++++++++++++++++++++++++++++++
+ drivers/video/mbx/regs.h     |  192 ++++++++++++
+ include/linux/mbxfb.h        |   28 ++
+ 8 files changed, 1498 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
+index 17de4c8..3f472d4 100644
+--- a/drivers/video/Kconfig
++++ b/drivers/video/Kconfig
+@@ -1518,6 +1518,16 @@ config FB_PXA_PARAMETERS
+ 
+ 	  <file:Documentation/fb/pxafb.txt> describes the available parameters.
+ 
++config FB_MBX
++	tristate "2700G LCD framebuffer support"
++	depends on FB && ARCH_PXA
++	select FB_CFB_FILLRECT
++	select FB_CFB_COPYAREA
++	select FB_CFB_IMAGEBLIT
++	---help---
++
++	  If unsure, say N.
++
+ config FB_W100
+ 	tristate "W100 frame buffer support"
+ 	depends on FB && PXA_SHARPSL
+diff --git a/drivers/video/Makefile b/drivers/video/Makefile
+index c335e9b..eabb5be 100644
+--- a/drivers/video/Makefile
++++ b/drivers/video/Makefile
+@@ -38,6 +38,7 @@ obj-$(CONFIG_FB_SIS)		  += sis/
+ obj-$(CONFIG_FB_KYRO)             += kyro/
+ obj-$(CONFIG_FB_SAVAGE)		  += savage/
+ obj-$(CONFIG_FB_GEODE)		  += geode/
++obj-$(CONFIG_FB_MBX)		  += mbx/
+ obj-$(CONFIG_FB_I810)             += vgastate.o
+ obj-$(CONFIG_FB_NEOMAGIC)         += neofb.o vgastate.o
+ obj-$(CONFIG_FB_VIRGE)            += virgefb.o
+diff --git a/drivers/video/mbx/Makefile b/drivers/video/mbx/Makefile
+new file mode 100644
+index 0000000..ad042f5
+--- /dev/null
++++ b/drivers/video/mbx/Makefile
+@@ -0,0 +1,3 @@
++# Makefile for the 2700G controller driver.
++
++obj-$(CONFIG_FB_MBX)	+= mbxfb.o
+diff --git a/drivers/video/mbx/mbxfb.c b/drivers/video/mbx/mbxfb.c
+new file mode 100644
+index 0000000..fcf164f
+--- /dev/null
++++ b/drivers/video/mbx/mbxfb.c
+@@ -0,0 +1,646 @@
++/*
++ *  linux/drivers/video/mbx/mbxfb.c
++ *
++ *  Copyright (C) 2006 Compulab, Ltd.
++ *  Mike Rapoport <mike@compulab.co.il>
++ *
++ *   Based on pxafb.c
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file COPYING in the main directory of this archive for
++ * more details.
++ *
++ *   Intel 2700G (Marathon) Graphics Accelerator Frame Buffer Driver
++ *
++ */
++
++#include <linux/config.h>
++#include <linux/module.h>
++#include <linux/fb.h>
++#include <linux/delay.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/mbxfb.h>
++
++#include <asm/io.h>
++
++/* use defines from asm-arm/arch-pxa/bitfields.h for now */
++/* review (and maybe rework) all bitfields access later */
++#define UData(Data)	((unsigned long) (Data))
++#define Fld(Size, Shft)	(((Size) << 16) + (Shft))
++#define FSize(Field)	((Field) >> 16)
++#define FShft(Field)	((Field) & 0x0000FFFF)
++#define FMsk(Field)	(((UData (1) << FSize (Field)) - 1) << FShft (Field))
++#define FAlnMsk(Field)	((UData (1) << FSize (Field)) - 1)
++#define F1stBit(Field)	(UData (1) << FShft (Field))
++
++static unsigned long virt_base_2700;
++#include "regs.h"
++#include "reg_bits.h"
++
++#define MIN_XRES	16
++#define MIN_YRES	16
++#define MAX_XRES	2048
++#define MAX_YRES	2048
++
++/* FIXME: take care of different chip reivsions with different sizes
++   of ODFB */
++#define MEMORY_OFFSET	0x60000
++
++struct mbxfb_info {
++		struct device *dev;
++		
++		struct resource *fb_res;
++		struct resource *fb_req;
++
++		struct resource *reg_res;
++		struct resource *reg_req;
++
++		void __iomem *fb_virt_addr;
++		unsigned long fb_phys_addr;
++
++		void __iomem *reg_virt_addr;
++		unsigned long reg_phys_addr;
++
++		int (*platform_probe)(struct fb_info *fb);
++		int (*platform_remove)(struct fb_info *fb);
++};
++
++static struct fb_var_screeninfo mbxfb_default = {
++	.xres =		640,
++	.yres =		480,
++	.xres_virtual =	640,
++	.yres_virtual =	480,
++	.bits_per_pixel = 16,
++	.red =		{ 11, 5, 0 },
++      	.green =	{ 5, 6, 0 },
++      	.blue =		{ 0, 5, 0 },
++      	.activate =	FB_ACTIVATE_TEST,
++      	.height =	-1,
++      	.width =	-1,
++      	.pixclock =	40000,
++      	.left_margin =	48,
++      	.right_margin =	16,
++      	.upper_margin =	33,
++      	.lower_margin =	10,
++      	.hsync_len =	96,
++      	.vsync_len =	2,
++      	.vmode =	FB_VMODE_NONINTERLACED,
++	.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++};
++
++static struct fb_fix_screeninfo mbxfb_fix = {
++	.id =		"MBX",
++	.type =		FB_TYPE_PACKED_PIXELS,
++	.visual =	FB_VISUAL_TRUECOLOR,
++	.xpanstep =	0,
++	.ypanstep =	0,
++	.ywrapstep =	0,
++	.accel =	FB_ACCEL_NONE,
++};
++
++struct pixclock_div {
++	u8 m;
++	u8 n;
++	u8 p;
++};
++
++static unsigned int mbxfb_get_pixclock(unsigned int pixclock_ps, struct pixclock_div *div)
++{
++	u8  m, n, p;
++	unsigned int err = 0;
++	unsigned int min_err = ~0x0;
++	unsigned int clk;
++	unsigned int best_clk = 0;
++	unsigned int ref_clk = 13000; /* FIXME: take from platform data */
++	unsigned int pixclock;
++
++	/* convert pixclock to KHz */
++	pixclock = PICOS2KHZ(pixclock_ps);
++
++	for ( m = 1; m < 64; m++ ) {
++		for ( n = 1; n < 8; n++ ) {
++			for ( p = 0; p < 8; p++ ) {
++				clk = (ref_clk * m) / (n * (1 << p));
++				err = (clk > pixclock) ? (clk - pixclock) : 
++					(pixclock - clk);
++				if ( err < min_err ) {
++					min_err = err;
++					best_clk = clk;
++					div->m = m;
++					div->n = n;
++					div->p = p;
++				}
++			}
++		}
++	}
++	return KHZ2PICOS(best_clk);
++}
++
++static int
++mbxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
++		   u_int trans, struct fb_info *info)
++{
++	uint val, ret = 1;
++
++	if ( regno < 255 ) {
++		val = (red & 0xff) << 16;
++		val |= (green & 0xff) << 8;
++		val |= (blue & 0xff) << 0;
++		GPLUT = Gplut_Lutadr(regno) | Gplut_Lutdata(val);
++		udelay(1000);
++		ret = 0;
++	}
++	return ret;
++}
++
++static int mbxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
++{
++	struct pixclock_div div;
++	
++	var->pixclock = mbxfb_get_pixclock(var->pixclock, &div);
++
++	if (var->xres < MIN_XRES)
++		var->xres = MIN_XRES;
++	if (var->yres < MIN_YRES)
++		var->yres = MIN_YRES;
++	if (var->xres > MAX_XRES)
++		var->xres = MAX_XRES;
++	if (var->yres > MAX_YRES)
++		var->yres = MAX_YRES;
++	var->xres_virtual =
++		max(var->xres_virtual, var->xres);
++	var->yres_virtual =
++		max(var->yres_virtual, var->yres);
++
++	switch (var->bits_per_pixel) {
++	/* FIXME: implement 8 bits-per-pixel */
++	case 8:
++		var->bits_per_pixel = 16;
++	case 16:
++		var->green.length = (var->green.length == 5) ? 5 : 6;
++		var->red.length = 5;
++		var->blue.length = 5;
++		var->transp.length = 6 - var->green.length;
++		var->blue.offset = 0;
++		var->green.offset = 5;
++		var->red.offset = 5 + var->green.length;
++		var->transp.offset =  (5 + var->red.offset) & 15;
++		break;
++	case 24:	/* RGB 888   */
++	case 32:	/* RGBA 8888 */
++		var->red.offset = 16;
++		var->red.length = 8;
++		var->green.offset = 8;
++		var->green.length = 8;
++		var->blue.offset = 0;
++		var->blue.length = 8;
++		var->transp.length = var->bits_per_pixel - 24;
++		var->transp.offset = (var->transp.length) ? 24 : 0;
++		break;
++	}
++	var->red.msb_right = 0;
++	var->green.msb_right = 0;
++	var->blue.msb_right = 0;
++	var->transp.msb_right = 0;
++
++	return 0;
++}
++
++static int mbxfb_set_par(struct fb_info *info)
++{
++	struct fb_var_screeninfo *var = &info->var;
++	struct pixclock_div div;
++	ushort hbps, ht, hfps, has;
++	ushort vbps, vt, vfps, vas;
++
++	info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
++	
++	/* setup color mode */
++	GSCTRL &= ~(FMsk(GSCTRL_GPIXFMT));
++	/* FIXME: add *WORKING* support for 8-bits per color */
++	if ( info->var.bits_per_pixel == 8 ) {
++		GSCTRL |= GSCTRL_GPIXFMT_INDEXED;
++		GSCTRL |= GSCTRL_LUT_EN;
++		GSCTRL &= ~GSCTRL_GAMMA_EN;
++		info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
++		fb_alloc_cmap(&info->cmap, 1<<info->var.bits_per_pixel, 0);
++	}
++	else {
++		fb_dealloc_cmap(&info->cmap);
++		GSCTRL &= ~GSCTRL_LUT_EN;
++		info->fix.visual = FB_VISUAL_TRUECOLOR;
++		switch ( info->var.bits_per_pixel ) {
++			case 16:
++				if ( info->var.green.length == 5 )
++					GSCTRL |= GSCTRL_GPIXFMT_ARGB1555;
++				else
++					GSCTRL |= GSCTRL_GPIXFMT_RGB565;
++				break;
++			case 24:
++				GSCTRL |= GSCTRL_GPIXFMT_RGB888;
++				break;
++			case 32:
++				GSCTRL |= GSCTRL_GPIXFMT_ARGB8888;
++				break;
++		}
++	}
++
++	/* setup resolution */
++	GSCTRL &= ~(FMsk(GSCTRL_GSWIDTH) | FMsk(GSCTRL_GSHEIGHT));
++	GSCTRL |= Gsctrl_Width(info->var.xres - 1) |
++		Gsctrl_Height(info->var.yres - 1);
++	
++	GSADR &= ~(FMsk(GSADR_SRCSTRIDE)); udelay(1000);
++	GSADR |=  Gsadr_Srcstride(info->var.xres * info->var.bits_per_pixel / (8 * 16) - 1); udelay(1000);
++
++	/* setup timings */
++	var->pixclock = mbxfb_get_pixclock(info->var.pixclock, &div);
++
++	DISPPLL = Disp_Pll_M(div.m) | Disp_Pll_N(div.n) | Disp_Pll_P(div.p) | DISP_PLL_EN;
++	
++	hbps = var->hsync_len;
++	has = hbps + var->left_margin;
++	hfps = has + var->xres;
++	ht = hfps + var->right_margin;
++
++	vbps = var->vsync_len;
++	vas = vbps + var->upper_margin;
++	vfps = vas + var->yres;
++	vt = vfps + var->lower_margin;
++
++	DHT01 = Dht01_Hbps(hbps) | Dht01_Ht(ht);
++ 	DHT02 = Dht02_Hlbs(has) | Dht02_Has(has);
++	DHT03 = Dht03_Hfps(hfps) | Dht03_Hrbs(hfps);
++	DHDET = Dhdet_Hdes(has) | Dhdet_Hdef(hfps);
++	
++	DVT01 = Dvt01_Vbps(vbps) | Dvt01_Vt(vt);
++	DVT02 = Dvt02_Vtbs(vas) | Dvt02_Vas(vas);
++	DVT03 = Dvt03_Vfps(vfps) | Dvt03_Vbbs(vfps);
++	DVDET = Dvdet_Vdes(vas) | Dvdet_Vdef(vfps);
++	DVECTRL = Dvectrl_Vevent(vfps) | Dvectrl_Vfetch(vbps);
++	DSCTRL |= DSCTRL_SYNCGEN_EN;
++
++	return 0;
++}
++
++static int mbxfb_blank(int blank, struct fb_info *info)
++{
++	switch (blank) {
++	case FB_BLANK_POWERDOWN:
++	case FB_BLANK_VSYNC_SUSPEND:
++	case FB_BLANK_HSYNC_SUSPEND:
++	case FB_BLANK_NORMAL:
++		DSCTRL &= ~DSCTRL_SYNCGEN_EN; udelay(1000);
++		PIXCLK &= ~PIXCLK_EN; udelay(1000);
++		VOVRCLK &= ~VOVRCLK_EN; udelay(1000);
++		break;
++	case FB_BLANK_UNBLANK:
++		DSCTRL |= DSCTRL_SYNCGEN_EN; udelay(1000);
++		PIXCLK |= PIXCLK_EN; udelay(1000);
++		break;
++	}
++	return 0;
++}
++
++static struct fb_ops mbxfb_ops = {
++	.owner		= THIS_MODULE,
++	.fb_check_var	= mbxfb_check_var,
++	.fb_set_par	= mbxfb_set_par,
++	.fb_setcolreg	= mbxfb_setcolreg,
++	.fb_fillrect	= cfb_fillrect,
++	.fb_copyarea	= cfb_copyarea,
++	.fb_imageblit	= cfb_imageblit,
++	.fb_blank	= mbxfb_blank,
++};
++
++/*
++   Enable external SDRAM controller. Assume that all clocks are active
++   by now. 
++*/
++static void setup_memc(struct fb_info *fbi)
++{
++	unsigned long tmp;
++
++	/* FIXME: use platfrom specific parameters */
++	/* setup SDRAM controller */
++	LMCFG = LMCFG_LMC_DS | LMCFG_LMC_TS | LMCFG_LMD_TS | LMCFG_LMA_TS;
++	udelay(1000);
++	LMPWR = LMPWR_MC_PWR_ACT;
++	udelay(1000);
++	/* setup SDRAM timings */
++	LMTIM = Lmtim_Tras(7) | Lmtim_Trp(3) | Lmtim_Trcd(3) | Lmtim_Trc(9) |
++		Lmtim_Tdpl(2);
++	udelay(1000);
++	/* setup SDRAM refresh rate */
++	LMREFRESH = 0xc2b;
++	udelay(1000);
++	/* setup SDRAM type parameters */
++	LMTYPE = LMTYPE_CASLAT_3 | LMTYPE_BKSZ_2 | LMTYPE_ROWSZ_11 | 
++		LMTYPE_COLSZ_8;
++	udelay(1000);
++	/* enable memory controller */
++	LMPWR = LMPWR_MC_PWR_ACT;
++	udelay(1000);
++
++	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
++	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
++	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
++	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
++	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
++	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
++	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
++	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
++	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
++	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
++	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
++}
++
++static void enable_clocks(struct fb_info* fbi)
++{
++	/* enable clocks */
++	SYSCLKSRC = SYSCLKSRC_PLL_2; udelay(1000);
++	PIXCLKSRC = PIXCLKSRC_PLL_1; udelay(1000);
++	CLKSLEEP = 0x00000000; udelay(1000);
++	COREPLL = Core_Pll_M(0x17) | Core_Pll_N(0x3) | Core_Pll_P(0x0) | CORE_PLL_EN; udelay(1000);
++	DISPPLL = Disp_Pll_M(0x1b) | Disp_Pll_N(0x7) | Disp_Pll_P(0x1) | DISP_PLL_EN;
++
++	VOVRCLK = 0x00000000; udelay(1000);
++	PIXCLK = PIXCLK_EN; udelay(1000);
++	MEMCLK = MEMCLK_EN; udelay(1000);
++	M24CLK = 0x00000006; udelay(1000);
++	MBXCLK = 0x00000006; udelay(1000);
++	SDCLK = SDCLK_EN; udelay(1000);
++	PIXCLKDIV = 0x00000001; udelay(1000);
++}
++
++static void setup_graphics(struct fb_info* fbi)
++{
++	unsigned long gsctrl;
++
++	gsctrl = GSCTRL_GAMMA_EN | Gsctrl_Width(fbi->var.xres-1) |
++		Gsctrl_Height(fbi->var.yres-1);
++	switch ( fbi->var.bits_per_pixel ) {
++		case 16:
++			if ( fbi->var.green.length == 5 )
++				gsctrl |= GSCTRL_GPIXFMT_ARGB1555;
++			else
++				gsctrl |= GSCTRL_GPIXFMT_RGB565;
++			break;
++		case 24: gsctrl |= GSCTRL_GPIXFMT_RGB888; break;
++		case 32: gsctrl |= GSCTRL_GPIXFMT_ARGB8888; break;
++	}
++
++	GSCTRL = gsctrl; udelay(1000);
++	GBBASE = 0x00000000; udelay(1000);
++	GDRCTRL = 0x00ffffff; udelay(1000);
++	GSCADR = GSCADR_STR_EN | Gscadr_Gbase_Adr(0x6000); udelay(1000);
++	GPLUT = 0x00000000; udelay(1000);
++}
++
++static void setup_display(struct fb_info* fbi)
++{
++	unsigned long dsctrl = 0;
++ 
++	dsctrl = DSCTRL_BLNK_POL;
++	if ( fbi->var.sync & FB_SYNC_HOR_HIGH_ACT )
++		dsctrl |= DSCTRL_HS_POL;
++	if ( fbi->var.sync & FB_SYNC_VERT_HIGH_ACT )
++		dsctrl |= DSCTRL_VS_POL;
++	DSCTRL = dsctrl; udelay(1000);
++	DMCTRL = 0xd0303010; udelay(1000);
++	DSCTRL |= DSCTRL_SYNCGEN_EN;
++}
++
++static void enable_controller(struct fb_info* fbi)
++{
++	SYSRST = SYSRST_RST;
++	udelay(1000);
++
++	enable_clocks(fbi);
++	setup_memc(fbi);	
++	setup_graphics(fbi);
++	setup_display(fbi);
++}
++
++
++#ifdef CONFIG_PM
++/*
++ * Power management hooks.  Note that we won't be called from IRQ context,
++ * unlike the blank functions above, so we may sleep.
++ */
++static int mbxfb_suspend(struct platform_device *dev, pm_message_t state)
++{
++	/* make frame buffer memory enter self-refresh mode */
++	LMPWR = LMPWR_MC_PWR_SRM;
++	while ( LMPWRSTAT != LMPWRSTAT_MC_PWR_SRM );
++
++	/* reset the device, since it's initial state is 'mostly sleeping' */
++	SYSRST = SYSRST_RST;
++	return 0;
++}
++
++static int mbxfb_resume(struct platform_device *dev)
++{
++	struct fb_info *fbi = (struct fb_info*)platform_get_drvdata(dev);
++
++	enable_clocks(fbi);
++/* 	setup_graphics(fbi); */
++/* 	setup_display(fbi); */
++
++	DSCTRL |= DSCTRL_SYNCGEN_EN;
++	return 0;
++}
++#else
++#define mbxfb_suspend	NULL
++#define mbxfb_resume	NULL
++#endif
++
++#include "mbxsysfs.c"
++
++#define res_size(_r) (((_r)->end - (_r)->start) + 1)
++
++static int mbxfb_probe(struct platform_device *dev)
++{
++	int ret;
++	struct fb_info *fbi;
++	struct mbxfb_info *mfbi;
++	struct mbxfb_platform_data *pdata;
++
++	dev_dbg(dev, "mbxfb_probe\n");
++
++	fbi = framebuffer_alloc(sizeof(struct mbxfb_info), &dev->dev);
++	if ( fbi == NULL ) {
++		dev_err(&dev->dev, "framebuffer_alloc failed\n");
++		return -ENOMEM;
++	}
++
++	mfbi = fbi->par;
++	pdata = dev->dev.platform_data;
++	if ( pdata->probe )
++		mfbi->platform_probe = pdata->probe;
++	if ( pdata->remove )
++		mfbi->platform_remove = pdata->remove;
++
++	mfbi->fb_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
++	mfbi->reg_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
++
++	if ( !mfbi->fb_res || !mfbi->reg_res ) {
++		dev_err(&dev->dev, "no resources found\n");
++		ret = -ENODEV;
++		goto err1;
++	}
++
++	mfbi->fb_req = request_mem_region(mfbi->fb_res->start,
++					  res_size(mfbi->fb_res),
++					  dev->name);
++	if ( mfbi->fb_req == NULL ) {
++		dev_err(&dev->dev, "failed to claim framebuffer memory\n");
++		ret = -EINVAL;
++		goto err1;
++	}
++	mfbi->fb_phys_addr = mfbi->fb_res->start;
++
++	mfbi->reg_req = request_mem_region(mfbi->reg_res->start,
++					  res_size(mfbi->reg_res),
++					   dev->name);
++	if ( mfbi->reg_req == NULL ) {
++		dev_err(&dev->dev, "failed to claim Marathon registers\n");
++		ret = -EINVAL;
++		goto err2;
++	}
++	mfbi->reg_phys_addr = mfbi->reg_res->start;
++
++	mfbi->reg_virt_addr = ioremap_nocache(mfbi->reg_phys_addr,
++					      res_size(mfbi->reg_req));
++	if ( !mfbi->reg_virt_addr ) {
++		dev_err(&dev->dev, "failed to ioremap Marathon registers\n");
++		ret = -EINVAL;
++		goto err3;
++	}
++	virt_base_2700 = (unsigned long)mfbi->reg_virt_addr;
++
++	mfbi->fb_virt_addr = ioremap_nocache(mfbi->fb_phys_addr,
++					     res_size(mfbi->fb_req));
++	if ( !mfbi->reg_virt_addr ) {
++		dev_err(&dev->dev, "failed to ioremap frame buffer\n");
++		ret = -EINVAL;
++		goto err4;
++	}
++
++	fbi->screen_base = (char __iomem *)(mfbi->fb_virt_addr + 0x60000); /* FIXME: */
++	fbi->screen_size = 8*1024*1024; /* 8 Megs */ /* FIXME: get from platform */
++	fbi->fbops = &mbxfb_ops;
++
++	fbi->var = mbxfb_default;
++	fbi->fix = mbxfb_fix;
++	fbi->fix.smem_start = mfbi->fb_phys_addr + 0x60000;
++	fbi->fix.smem_len = 8*1024*1024;
++	fbi->fix.line_length = 640*2;
++
++	ret = fb_alloc_cmap(&fbi->cmap, 256, 0);
++	if (ret < 0) {
++		dev_err(&dev->dev, "fb_alloc_cmap failed\n");
++		ret = -EINVAL;
++		goto err5;
++	}
++
++	ret = register_framebuffer(fbi);
++	if (ret < 0) {
++		dev_err(&dev->dev, "register_framebuffer failed\n");
++		ret = -EINVAL;
++		goto err6;
++	}
++
++	platform_set_drvdata(dev, fbi);
++
++	printk(KERN_INFO "fb%d: mbx frame buffer device\n", fbi->node);
++
++	if ( mfbi->platform_probe )
++		mfbi->platform_probe(fbi);
++
++	enable_controller(fbi);
++
++	mbxfb_sysfs_register(fbi);
++
++	return 0;
++
++  err6:
++	fb_dealloc_cmap(&fbi->cmap);
++  err5:
++	iounmap(mfbi->fb_virt_addr);
++  err4:
++	iounmap(mfbi->reg_virt_addr);
++  err3:
++	release_mem_region(mfbi->reg_res->start,
++			   res_size(mfbi->reg_res));
++  err2:
++	release_mem_region(mfbi->fb_res->start,
++			   res_size(mfbi->fb_res));
++  err1:
++	framebuffer_release(fbi);
++
++	return ret;
++}
++
++static int mbxfb_remove(struct platform_device *dev)
++{
++	struct fb_info *fbi = (struct fb_info*)platform_get_drvdata(dev);
++
++	SYSRST = SYSRST_RST;
++	udelay(1000);
++
++	if (fbi) {
++		struct mbxfb_info *mfbi = fbi->par;
++
++		unregister_framebuffer(fbi);
++		if ( mfbi ) {
++			if ( mfbi->platform_remove )
++				mfbi->platform_remove(fbi);
++
++			if ( mfbi->fb_virt_addr )
++				iounmap(mfbi->fb_virt_addr);
++			if ( mfbi->reg_virt_addr )
++				iounmap(mfbi->reg_virt_addr);
++			if ( mfbi->reg_req ) 
++				release_mem_region(mfbi->reg_req->start,
++						   res_size(mfbi->reg_req));
++			if ( mfbi->fb_req ) 
++				release_mem_region(mfbi->fb_req->start,
++						   res_size(mfbi->fb_req));
++		}
++		framebuffer_release(fbi);
++	}
++
++	return 0;
++}
++
++static struct platform_driver mbxfb_driver = {
++	.probe		= mbxfb_probe,
++	.remove		= mbxfb_remove,
++
++#ifdef CONFIG_PM
++	.suspend	= mbxfb_suspend,
++	.resume		= mbxfb_resume,
++#endif
++	.driver		= {
++		.name	= "mbx-fb",
++	},
++};
++
++int __devinit mbxfb_init(void)
++{
++	return platform_driver_register(&mbxfb_driver);
++}
++
++static void __exit mbxfb_exit(void)
++{
++	platform_driver_unregister(&mbxfb_driver);
++}
++
++module_init(mbxfb_init);
++module_exit(mbxfb_exit);
++
++MODULE_DESCRIPTION("loadable framebuffer driver for Marathon device");
++MODULE_AUTHOR("Mike Rapoport, Compulab");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/video/mbx/mbxsysfs.c b/drivers/video/mbx/mbxsysfs.c
+new file mode 100644
+index 0000000..4b9571a
+--- /dev/null
++++ b/drivers/video/mbx/mbxsysfs.c
+@@ -0,0 +1,129 @@
++static ssize_t sysconf_show(struct class_device * subsys, char * buf)
++{
++	char * s = buf;
++
++	s += sprintf(s, "SYSCFG = %08lx\n", SYSCFG);
++	s += sprintf(s, "PFBASE = %08lx\n", PFBASE);
++	s += sprintf(s, "PFCEIL = %08lx\n", PFCEIL);
++	s += sprintf(s, "POLLFLAG = %08lx\n", POLLFLAG);
++	s += sprintf(s, "SYSRST = %08lx\n", SYSRST);
++	return (s - buf);
++}
++
++static ssize_t sysconf_store(struct class_device * subsys, const char * buf, size_t n)
++{
++	return n;
++}
++
++static ssize_t gsctl_show(struct class_device * subsys, char * buf)
++{
++	char * s = buf;
++
++	s += sprintf(s, "GSCTRL = %08lx\n", GSCTRL);
++	s += sprintf(s, "VSCTRL = %08lx\n", VSCTRL);
++	s += sprintf(s, "GBBASE = %08lx\n", GBBASE);
++	s += sprintf(s, "VBBASE = %08lx\n", VBBASE);
++	s += sprintf(s, "GDRCTRL = %08lx\n", GDRCTRL);
++	s += sprintf(s, "VCMSK = %08lx\n", VCMSK);
++	s += sprintf(s, "GSCADR = %08lx\n", GSCADR);
++	s += sprintf(s, "VSCADR = %08lx\n", VSCADR);
++	s += sprintf(s, "VUBASE = %08lx\n", VUBASE);
++	s += sprintf(s, "VVBASE = %08lx\n", VVBASE);
++	s += sprintf(s, "GSADR = %08lx\n", GSADR);
++	s += sprintf(s, "VSADR = %08lx\n", VSADR);
++	s += sprintf(s, "HCCTRL = %08lx\n", HCCTRL);
++	s += sprintf(s, "HCSIZE = %08lx\n", HCSIZE);
++	s += sprintf(s, "HCPOS = %08lx\n", HCPOS);
++	s += sprintf(s, "HCBADR = %08lx\n", HCBADR);
++	s += sprintf(s, "HCCKMSK = %08lx\n", HCCKMSK);
++	s += sprintf(s, "GPLUT = %08lx\n", GPLUT);
++	return (s - buf);
++}
++
++static ssize_t gsctl_store(struct class_device * subsys, const char * buf, size_t n)
++{
++	return n;
++}
++
++static ssize_t display_show(struct class_device * subsys, char * buf)
++{
++	char * s = buf;
++
++	s += sprintf(s, "DSCTRL = %08lx\n", DSCTRL);
++	s += sprintf(s, "DHT01 = %08lx\n", DHT01);
++	s += sprintf(s, "DHT02 = %08lx\n", DHT02);
++	s += sprintf(s, "DHT03 = %08lx\n", DHT03);
++	s += sprintf(s, "DVT01 = %08lx\n", DVT01);
++	s += sprintf(s, "DVT02 = %08lx\n", DVT02);
++	s += sprintf(s, "DVT03 = %08lx\n", DVT03);
++	s += sprintf(s, "DBCOL = %08lx\n", DBCOL);
++	s += sprintf(s, "BGCOLOR = %08lx\n", BGCOLOR);
++	s += sprintf(s, "DINTRS = %08lx\n", DINTRS);
++	s += sprintf(s, "DINTRE = %08lx\n", DINTRE);
++	s += sprintf(s, "DINTRCNT = %08lx\n", DINTRCNT);
++	s += sprintf(s, "DSIG = %08lx\n", DSIG);
++	s += sprintf(s, "DMCTRL = %08lx\n", DMCTRL);
++	s += sprintf(s, "CLIPCTRL = %08lx\n", CLIPCTRL);
++	s += sprintf(s, "SPOCTRL = %08lx\n", SPOCTRL);
++	s += sprintf(s, "SVCTRL = %08lx\n", SVCTRL);
++	s += sprintf(s, "DLSTS = %08lx\n", DLSTS);
++	s += sprintf(s, "DLLCTRL = %08lx\n", DLLCTRL);
++	s += sprintf(s, "DVLNUM = %08lx\n", DVLNUM);
++	s += sprintf(s, "DUCTRL = %08lx\n", DUCTRL);
++	s += sprintf(s, "DVECTRL = %08lx\n", DVECTRL);
++	s += sprintf(s, "DHDET = %08lx\n", DHDET);
++	s += sprintf(s, "DVDET = %08lx\n", DVDET);
++	s += sprintf(s, "DODMSK = %08lx\n", DODMSK);
++	s += sprintf(s, "CSC01 = %08lx\n", CSC01);
++	s += sprintf(s, "CSC02 = %08lx\n", CSC02);
++	s += sprintf(s, "CSC03 = %08lx\n", CSC03);
++	s += sprintf(s, "CSC04 = %08lx\n", CSC04);
++	s += sprintf(s, "CSC05 = %08lx\n", CSC05);
++	return (s - buf);
++}
++
++static ssize_t display_store(struct class_device * subsys, const char * buf, size_t n)
++{
++	return n;
++}
++
++static ssize_t clock_show(struct class_device * subsys, char * buf)
++{
++	char * s = buf;
++
++	s += sprintf(s, "SYSCLKSRC = %08lx\n", SYSCLKSRC);
++	s += sprintf(s, "PIXCLKSRC = %08lx\n", PIXCLKSRC);
++	s += sprintf(s, "CLKSLEEP = %08lx\n", CLKSLEEP);
++	s += sprintf(s, "COREPLL = %08lx\n", COREPLL);
++	s += sprintf(s, "DISPPLL = %08lx\n", DISPPLL);
++	s += sprintf(s, "PLLSTAT = %08lx\n", PLLSTAT);
++	s += sprintf(s, "VOVRCLK = %08lx\n", VOVRCLK);
++	s += sprintf(s, "PIXCLK = %08lx\n", PIXCLK);
++	s += sprintf(s, "MEMCLK = %08lx\n", MEMCLK);
++	s += sprintf(s, "M24CLK = %08lx\n", M24CLK);
++	s += sprintf(s, "MBXCLK = %08lx\n", MBXCLK);
++	s += sprintf(s, "SDCLK = %08lx\n", SDCLK);
++	s += sprintf(s, "PIXCLKDIV = %08lx\n", PIXCLKDIV);
++	return (s - buf);
++}
++
++static ssize_t clock_store(struct class_device * subsys, const char * buf, size_t n)
++{
++	return n;
++}
++
++static struct class_device_attribute mbx_class_attrs[] = {
++	__ATTR(sysconf,0644,sysconf_show,sysconf_store),
++	__ATTR(gsctl,0644,gsctl_show,gsctl_store),
++	__ATTR(display,0644,display_show,display_store),
++	__ATTR(clock,0644,clock_show,clock_store),
++};
++
++
++static void mbxfb_sysfs_register(struct fb_info *fbi)
++{
++	int i;
++	for (i = 0; i < ARRAY_SIZE(mbx_class_attrs); i++)
++		class_device_create_file(fbi->class_device,
++					 &mbx_class_attrs[i]);
++}
+diff --git a/drivers/video/mbx/reg_bits.h b/drivers/video/mbx/reg_bits.h
+new file mode 100644
+index 0000000..be152f6
+--- /dev/null
++++ b/drivers/video/mbx/reg_bits.h
+@@ -0,0 +1,489 @@
++#ifndef __REG_BITS_2700G_
++#define __REG_BITS_2700G_
++
++/* /\* System Configuration Registers (0x03FE_0000  0x03FE_0010) *\/ */
++/* #define SYSCFG		__REG_2700G(0x03FE0000) */
++/* #define PFBASE		__REG_2700G(0x03FE0004) */
++/* #define PFCEIL		__REG_2700G(0x03FE0008) */
++/* #define POLLFLAG	__REG_2700G(0x03FE000C) */
++
++#define SYSRST_RST	(1 << 0)
++
++/* /\* Interrupt Control Registers (0x03FE_0014  0x03FE_002F) *\/ */
++/* #define NINTPW		__REG_2700G(0x03FE0014) */
++/* #define MINTENABLE	__REG_2700G(0x03FE0018) */
++/* #define MINTSTAT	__REG_2700G(0x03FE001C) */
++/* #define SINTENABLE	__REG_2700G(0x03FE0020) */
++/* #define SINTSTAT	__REG_2700G(0x03FE0024) */
++/* #define SINTCLR		__REG_2700G(0x03FE0028) */
++
++/* SYSCLKSRC - SYSCLK Source Control Register */
++#define SYSCLKSRC_SEL	Fld(2,0)
++#define SYSCLKSRC_REF	((0x0) << FShft(SYSCLKSRC_SEL))
++#define SYSCLKSRC_PLL_1	((0x1) << FShft(SYSCLKSRC_SEL))
++#define SYSCLKSRC_PLL_2	((0x2) << FShft(SYSCLKSRC_SEL))
++
++/* PIXCLKSRC - PIXCLK Source Control Register */
++#define PIXCLKSRC_SEL	Fld(2,0)
++#define PIXCLKSRC_REF	((0x0) << FShft(PIXCLKSRC_SEL))
++#define PIXCLKSRC_PLL_1	((0x1) << FShft(PIXCLKSRC_SEL))
++#define PIXCLKSRC_PLL_2	((0x2) << FShft(PIXCLKSRC_SEL))
++
++/* Clock Disable Register */
++#define CLKSLEEP_SLP	(1 << 0)
++
++/* Core PLL Control Register */
++#define CORE_PLL_M	Fld(6,7)
++#define Core_Pll_M(x)	((x) << FShft(CORE_PLL_M))
++#define CORE_PLL_N	Fld(3,4)
++#define Core_Pll_N(x)	((x) << FShft(CORE_PLL_N))
++#define CORE_PLL_P	Fld(3,1)
++#define Core_Pll_P(x)	((x) << FShft(CORE_PLL_P))
++#define CORE_PLL_EN	(1 << 0)
++
++/* Display PLL Control Register */
++#define DISP_PLL_M	Fl