Rename /openembedded/ -> /meta/

git-svn-id: https://svn.o-hand.com/repos/poky/trunk@530 311d38ba-8fff-0310-9ca6-ca027cbcb966

52 files changed, 0 insertions, 40344 deletions

diff --git a/openembedded/packages/linux/linux-cmx270-2.6.17/add_2700g_plat-r0.patch b/openembedded/packages/linux/linux-cmx270-2.6.17/add_2700g_plat-r0.patch
deleted file mode 100644
index b4a33e2cf7..0000000000
--- a/openembedded/packages/linux/linux-cmx270-2.6.17/add_2700g_plat-r0.patch
+++ /dev/null
@@ -1,126 +0,0 @@
-Index: linux-2.6.17/arch/arm/mach-pxa/cm-x270.c
-===================================================================
---- linux-2.6.17.orig/arch/arm/mach-pxa/cm-x270.c	2006-07-18 15:40:10.000000000 +0100
-+++ linux-2.6.17/arch/arm/mach-pxa/cm-x270.c	2006-07-20 20:25:22.000000000 +0100
-@@ -11,6 +11,7 @@
- #include <linux/pm.h>
- #include <linux/fb.h>
- #include <linux/rtc-v3020.h>
-+#include <linux/mbxfb.h>
- 
- #include <asm/types.h>
- #include <asm/setup.h>
-@@ -396,10 +397,113 @@
- 	.resource = dm9000_resources,
- };
- 
-+/* 2700G graphics */
-+static u64 fb_dma_mask = ~(u64)0;
-+
-+static struct resource cmx270_2700G_resource[] = {
-+       /* frame buffer memory including ODFB and External SDRAM */
-+       [0] = {
-+               .start = MARATHON_PHYS,
-+               .end   = MARATHON_PHYS + 0x02000000,
-+               .flags = IORESOURCE_MEM,
-+       },
-+       /* Marathon registers */
-+       [1] = {
-+               .start = MARATHON_PHYS + 0x03fe0000,
-+               .end   = MARATHON_PHYS + 0x03ffffff,
-+               .flags = IORESOURCE_MEM,
-+       },
-+};
-+
-+static unsigned long save_lcd_regs[10];
-+
-+/* if 2700G is used, disable PCI throttle */
-+#define LB_TROTTLE_OFF (PXA_CS1_PHYS | (1 << 25))
-+#define LB_TROTTLE_MAX (PXA_CS1_PHYS | (1 << 25) | (1 << 22))
-+static int cmx270_marathon_probe(struct fb_info *fb)
-+{
-+       volatile unsigned long *cpld;
-+       
-+       cpld = (volatile unsigned long*)ioremap(LB_TROTTLE_OFF, 4);
-+       if ( !cpld ) {
-+               return -ENODEV;
-+       }
-+       *cpld = 0;
-+       iounmap((void*)cpld);
-+
-+       /* save PXA-270 pin settings before enabling 2700G */
-+       save_lcd_regs[0] = GPDR1;
-+       save_lcd_regs[1] = GPDR2;
-+       save_lcd_regs[2] = GAFR1_U;
-+       save_lcd_regs[3] = GAFR2_L;
-+       save_lcd_regs[4] = GAFR2_U;
-+
-+       /* Disable PXA-270 on-chip controller driving pins */
-+       GPDR1 &= ~(0xfc000000);
-+       GPDR2 &= ~(0x00c03fff);
-+       GAFR1_U &= ~(0xfff00000);
-+       GAFR2_L &= ~(0x0fffffff);
-+       GAFR2_U &= ~(0x0000f000);
-+       return 0;
-+}
-+
-+static int cmx270_marathon_remove(struct fb_info *fb)
-+{
-+       volatile unsigned long *cpld;
-+       cpld = (volatile unsigned long*)ioremap(LB_TROTTLE_MAX, 4);
-+       
-+       if ( !cpld ) {
-+               return -ENODEV;
-+       }
-+       *cpld = 0;
-+       iounmap((void*)cpld);
-+
-+       GPDR1 =   save_lcd_regs[0];
-+       GPDR2 =   save_lcd_regs[1];
-+       GAFR1_U = save_lcd_regs[2];
-+       GAFR2_L = save_lcd_regs[3];
-+       GAFR2_U = save_lcd_regs[4];
-+       return 0;
-+}
-+
-+static struct mbxfb_platform_data cmx270_2700G_data = {
-+       .xres = {
-+               .min = 240,
-+               .max = 1200,
-+               .defval = 640,
-+       },
-+       .yres = { 
-+               .min = 240,
-+               .max = 1200,
-+               .defval = 480,
-+       },
-+       .bpp = {
-+               .min = 16,
-+               .max = 32,
-+               .defval = 16,
-+       },
-+       .memsize = 8*1024*1024,
-+       .probe = cmx270_marathon_probe,
-+       .remove = cmx270_marathon_remove,
-+};
-+
-+static struct platform_device cmx270_2700G = {
-+       .name           = "mbx-fb",
-+       .dev            = {
-+               .platform_data  = &cmx270_2700G_data,
-+               .dma_mask       = &fb_dma_mask,
-+               .coherent_dma_mask = 0xffffffff,
-+       },
-+       .num_resources  = ARRAY_SIZE(cmx270_2700G_resource),
-+       .resource       = cmx270_2700G_resource,
-+       .id             = -1,
-+};
-+
- static struct platform_device *platform_devices[] __initdata = {\
- 	&cmx270_audio_device,
- 	&v3020_rtc_device,
- 	&dm9000_device,
-+	&cmx270_2700G,
- };
- 
- static int cmx270_ohci_init(struct device *dev)
diff --git a/openembedded/packages/linux/linux-cmx270-2.6.17/cm_x2xx_mbx.patch b/openembedded/packages/linux/linux-cmx270-2.6.17/cm_x2xx_mbx.patch
deleted file mode 100644
index d33f4522f8..0000000000
--- a/openembedded/packages/linux/linux-cmx270-2.6.17/cm_x2xx_mbx.patch
+++ /dev/null
@@ -1,1566 +0,0 @@
- drivers/video/Kconfig        |   10 +
- drivers/video/Makefile       |    1 
- drivers/video/mbx/Makefile   |    3 
- drivers/video/mbx/mbxfb.c    |  646 ++++++++++++++++++++++++++++++++++++++++++
- drivers/video/mbx/mbxsysfs.c |  129 ++++++++
- drivers/video/mbx/reg_bits.h |  489 ++++++++++++++++++++++++++++++++
- drivers/video/mbx/regs.h     |  192 ++++++++++++
- include/linux/mbxfb.h        |   28 ++
- 8 files changed, 1498 insertions(+), 0 deletions(-)
-
-diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
-index 17de4c8..3f472d4 100644
---- a/drivers/video/Kconfig
-+++ b/drivers/video/Kconfig
-@@ -1518,6 +1518,16 @@ config FB_PXA_PARAMETERS
- 
- 	  <file:Documentation/fb/pxafb.txt> describes the available parameters.
- 
-+config FB_MBX
-+	tristate "2700G LCD framebuffer support"
-+	depends on FB && ARCH_PXA
-+	select FB_CFB_FILLRECT
-+	select FB_CFB_COPYAREA
-+	select FB_CFB_IMAGEBLIT
-+	---help---
-+
-+	  If unsure, say N.
-+
- config FB_W100
- 	tristate "W100 frame buffer support"
- 	depends on FB && PXA_SHARPSL
-diff --git a/drivers/video/Makefile b/drivers/video/Makefile
-index c335e9b..eabb5be 100644
---- a/drivers/video/Makefile
-+++ b/drivers/video/Makefile
-@@ -38,6 +38,7 @@ obj-$(CONFIG_FB_SIS)		  += sis/
- obj-$(CONFIG_FB_KYRO)             += kyro/
- obj-$(CONFIG_FB_SAVAGE)		  += savage/
- obj-$(CONFIG_FB_GEODE)		  += geode/
-+obj-$(CONFIG_FB_MBX)		  += mbx/
- obj-$(CONFIG_FB_I810)             += vgastate.o
- obj-$(CONFIG_FB_NEOMAGIC)         += neofb.o vgastate.o
- obj-$(CONFIG_FB_VIRGE)            += virgefb.o
-diff --git a/drivers/video/mbx/Makefile b/drivers/video/mbx/Makefile
-new file mode 100644
-index 0000000..ad042f5
---- /dev/null
-+++ b/drivers/video/mbx/Makefile
-@@ -0,0 +1,3 @@
-+# Makefile for the 2700G controller driver.
-+
-+obj-$(CONFIG_FB_MBX)	+= mbxfb.o
-diff --git a/drivers/video/mbx/mbxfb.c b/drivers/video/mbx/mbxfb.c
-new file mode 100644
-index 0000000..fcf164f
---- /dev/null
-+++ b/drivers/video/mbx/mbxfb.c
-@@ -0,0 +1,646 @@
-+/*
-+ *  linux/drivers/video/mbx/mbxfb.c
-+ *
-+ *  Copyright (C) 2006 Compulab, Ltd.
-+ *  Mike Rapoport <mike@compulab.co.il>
-+ *
-+ *   Based on pxafb.c
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file COPYING in the main directory of this archive for
-+ * more details.
-+ *
-+ *   Intel 2700G (Marathon) Graphics Accelerator Frame Buffer Driver
-+ *
-+ */
-+
-+#include <linux/config.h>
-+#include <linux/module.h>
-+#include <linux/fb.h>
-+#include <linux/delay.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/mbxfb.h>
-+
-+#include <asm/io.h>
-+
-+/* use defines from asm-arm/arch-pxa/bitfields.h for now */
-+/* review (and maybe rework) all bitfields access later */
-+#define UData(Data)	((unsigned long) (Data))
-+#define Fld(Size, Shft)	(((Size) << 16) + (Shft))
-+#define FSize(Field)	((Field) >> 16)
-+#define FShft(Field)	((Field) & 0x0000FFFF)
-+#define FMsk(Field)	(((UData (1) << FSize (Field)) - 1) << FShft (Field))
-+#define FAlnMsk(Field)	((UData (1) << FSize (Field)) - 1)
-+#define F1stBit(Field)	(UData (1) << FShft (Field))
-+
-+static unsigned long virt_base_2700;
-+#include "regs.h"
-+#include "reg_bits.h"
-+
-+#define MIN_XRES	16
-+#define MIN_YRES	16
-+#define MAX_XRES	2048
-+#define MAX_YRES	2048
-+
-+/* FIXME: take care of different chip reivsions with different sizes
-+   of ODFB */
-+#define MEMORY_OFFSET	0x60000
-+
-+struct mbxfb_info {
-+		struct device *dev;
-+		
-+		struct resource *fb_res;
-+		struct resource *fb_req;
-+
-+		struct resource *reg_res;
-+		struct resource *reg_req;
-+
-+		void __iomem *fb_virt_addr;
-+		unsigned long fb_phys_addr;
-+
-+		void __iomem *reg_virt_addr;
-+		unsigned long reg_phys_addr;
-+
-+		int (*platform_probe)(struct fb_info *fb);
-+		int (*platform_remove)(struct fb_info *fb);
-+};
-+
-+static struct fb_var_screeninfo mbxfb_default = {
-+	.xres =		640,
-+	.yres =		480,
-+	.xres_virtual =	640,
-+	.yres_virtual =	480,
-+	.bits_per_pixel = 16,
-+	.red =		{ 11, 5, 0 },
-+      	.green =	{ 5, 6, 0 },
-+      	.blue =		{ 0, 5, 0 },
-+      	.activate =	FB_ACTIVATE_TEST,
-+      	.height =	-1,
-+      	.width =	-1,
-+      	.pixclock =	40000,
-+      	.left_margin =	48,
-+      	.right_margin =	16,
-+      	.upper_margin =	33,
-+      	.lower_margin =	10,
-+      	.hsync_len =	96,
-+      	.vsync_len =	2,
-+      	.vmode =	FB_VMODE_NONINTERLACED,
-+	.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-+};
-+
-+static struct fb_fix_screeninfo mbxfb_fix = {
-+	.id =		"MBX",
-+	.type =		FB_TYPE_PACKED_PIXELS,
-+	.visual =	FB_VISUAL_TRUECOLOR,
-+	.xpanstep =	0,
-+	.ypanstep =	0,
-+	.ywrapstep =	0,
-+	.accel =	FB_ACCEL_NONE,
-+};
-+
-+struct pixclock_div {
-+	u8 m;
-+	u8 n;
-+	u8 p;
-+};
-+
-+static unsigned int mbxfb_get_pixclock(unsigned int pixclock_ps, struct pixclock_div *div)
-+{
-+	u8  m, n, p;
-+	unsigned int err = 0;
-+	unsigned int min_err = ~0x0;
-+	unsigned int clk;
-+	unsigned int best_clk = 0;
-+	unsigned int ref_clk = 13000; /* FIXME: take from platform data */
-+	unsigned int pixclock;
-+
-+	/* convert pixclock to KHz */
-+	pixclock = PICOS2KHZ(pixclock_ps);
-+
-+	for ( m = 1; m < 64; m++ ) {
-+		for ( n = 1; n < 8; n++ ) {
-+			for ( p = 0; p < 8; p++ ) {
-+				clk = (ref_clk * m) / (n * (1 << p));
-+				err = (clk > pixclock) ? (clk - pixclock) : 
-+					(pixclock - clk);
-+				if ( err < min_err ) {
-+					min_err = err;
-+					best_clk = clk;
-+					div->m = m;
-+					div->n = n;
-+					div->p = p;
-+				}
-+			}
-+		}
-+	}
-+	return KHZ2PICOS(best_clk);
-+}
-+
-+static int
-+mbxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
-+		   u_int trans, struct fb_info *info)
-+{
-+	uint val, ret = 1;
-+
-+	if ( regno < 255 ) {
-+		val = (red & 0xff) << 16;
-+		val |= (green & 0xff) << 8;
-+		val |= (blue & 0xff) << 0;
-+		GPLUT = Gplut_Lutadr(regno) | Gplut_Lutdata(val);
-+		udelay(1000);
-+		ret = 0;
-+	}
-+	return ret;
-+}
-+
-+static int mbxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
-+{
-+	struct pixclock_div div;
-+	
-+	var->pixclock = mbxfb_get_pixclock(var->pixclock, &div);
-+
-+	if (var->xres < MIN_XRES)
-+		var->xres = MIN_XRES;
-+	if (var->yres < MIN_YRES)
-+		var->yres = MIN_YRES;
-+	if (var->xres > MAX_XRES)
-+		var->xres = MAX_XRES;
-+	if (var->yres > MAX_YRES)
-+		var->yres = MAX_YRES;
-+	var->xres_virtual =
-+		max(var->xres_virtual, var->xres);
-+	var->yres_virtual =
-+		max(var->yres_virtual, var->yres);
-+
-+	switch (var->bits_per_pixel) {
-+	/* FIXME: implement 8 bits-per-pixel */
-+	case 8:
-+		var->bits_per_pixel = 16;
-+	case 16:
-+		var->green.length = (var->green.length == 5) ? 5 : 6;
-+		var->red.length = 5;
-+		var->blue.length = 5;
-+		var->transp.length = 6 - var->green.length;
-+		var->blue.offset = 0;
-+		var->green.offset = 5;
-+		var->red.offset = 5 + var->green.length;
-+		var->transp.offset =  (5 + var->red.offset) & 15;
-+		break;
-+	case 24:	/* RGB 888   */
-+	case 32:	/* RGBA 8888 */
-+		var->red.offset = 16;
-+		var->red.length = 8;
-+		var->green.offset = 8;
-+		var->green.length = 8;
-+		var->blue.offset = 0;
-+		var->blue.length = 8;
-+		var->transp.length = var->bits_per_pixel - 24;
-+		var->transp.offset = (var->transp.length) ? 24 : 0;
-+		break;
-+	}
-+	var->red.msb_right = 0;
-+	var->green.msb_right = 0;
-+	var->blue.msb_right = 0;
-+	var->transp.msb_right = 0;
-+
-+	return 0;
-+}
-+
-+static int mbxfb_set_par(struct fb_info *info)
-+{
-+	struct fb_var_screeninfo *var = &info->var;
-+	struct pixclock_div div;
-+	ushort hbps, ht, hfps, has;
-+	ushort vbps, vt, vfps, vas;
-+
-+	info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
-+	
-+	/* setup color mode */
-+	GSCTRL &= ~(FMsk(GSCTRL_GPIXFMT));
-+	/* FIXME: add *WORKING* support for 8-bits per color */
-+	if ( info->var.bits_per_pixel == 8 ) {
-+		GSCTRL |= GSCTRL_GPIXFMT_INDEXED;
-+		GSCTRL |= GSCTRL_LUT_EN;
-+		GSCTRL &= ~GSCTRL_GAMMA_EN;
-+		info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
-+		fb_alloc_cmap(&info->cmap, 1<<info->var.bits_per_pixel, 0);
-+	}
-+	else {
-+		fb_dealloc_cmap(&info->cmap);
-+		GSCTRL &= ~GSCTRL_LUT_EN;
-+		info->fix.visual = FB_VISUAL_TRUECOLOR;
-+		switch ( info->var.bits_per_pixel ) {
-+			case 16:
-+				if ( info->var.green.length == 5 )
-+					GSCTRL |= GSCTRL_GPIXFMT_ARGB1555;
-+				else
-+					GSCTRL |= GSCTRL_GPIXFMT_RGB565;
-+				break;
-+			case 24:
-+				GSCTRL |= GSCTRL_GPIXFMT_RGB888;
-+				break;
-+			case 32:
-+				GSCTRL |= GSCTRL_GPIXFMT_ARGB8888;
-+				break;
-+		}
-+	}
-+
-+	/* setup resolution */
-+	GSCTRL &= ~(FMsk(GSCTRL_GSWIDTH) | FMsk(GSCTRL_GSHEIGHT));
-+	GSCTRL |= Gsctrl_Width(info->var.xres - 1) |
-+		Gsctrl_Height(info->var.yres - 1);
-+	
-+	GSADR &= ~(FMsk(GSADR_SRCSTRIDE)); udelay(1000);
-+	GSADR |=  Gsadr_Srcstride(info->var.xres * info->var.bits_per_pixel / (8 * 16) - 1); udelay(1000);
-+
-+	/* setup timings */
-+	var->pixclock = mbxfb_get_pixclock(info->var.pixclock, &div);
-+
-+	DISPPLL = Disp_Pll_M(div.m) | Disp_Pll_N(div.n) | Disp_Pll_P(div.p) | DISP_PLL_EN;
-+	
-+	hbps = var->hsync_len;
-+	has = hbps + var->left_margin;
-+	hfps = has + var->xres;
-+	ht = hfps + var->right_margin;
-+
-+	vbps = var->vsync_len;
-+	vas = vbps + var->upper_margin;
-+	vfps = vas + var->yres;
-+	vt = vfps + var->lower_margin;
-+
-+	DHT01 = Dht01_Hbps(hbps) | Dht01_Ht(ht);
-+ 	DHT02 = Dht02_Hlbs(has) | Dht02_Has(has);
-+	DHT03 = Dht03_Hfps(hfps) | Dht03_Hrbs(hfps);
-+	DHDET = Dhdet_Hdes(has) | Dhdet_Hdef(hfps);
-+	
-+	DVT01 = Dvt01_Vbps(vbps) | Dvt01_Vt(vt);
-+	DVT02 = Dvt02_Vtbs(vas) | Dvt02_Vas(vas);
-+	DVT03 = Dvt03_Vfps(vfps) | Dvt03_Vbbs(vfps);
-+	DVDET = Dvdet_Vdes(vas) | Dvdet_Vdef(vfps);
-+	DVECTRL = Dvectrl_Vevent(vfps) | Dvectrl_Vfetch(vbps);
-+	DSCTRL |= DSCTRL_SYNCGEN_EN;
-+
-+	return 0;
-+}
-+
-+static int mbxfb_blank(int blank, struct fb_info *info)
-+{
-+	switch (blank) {
-+	case FB_BLANK_POWERDOWN:
-+	case FB_BLANK_VSYNC_SUSPEND:
-+	case FB_BLANK_HSYNC_SUSPEND:
-+	case FB_BLANK_NORMAL:
-+		DSCTRL &= ~DSCTRL_SYNCGEN_EN; udelay(1000);
-+		PIXCLK &= ~PIXCLK_EN; udelay(1000);
-+		VOVRCLK &= ~VOVRCLK_EN; udelay(1000);
-+		break;
-+	case FB_BLANK_UNBLANK:
-+		DSCTRL |= DSCTRL_SYNCGEN_EN; udelay(1000);
-+		PIXCLK |= PIXCLK_EN; udelay(1000);
-+		break;
-+	}
-+	return 0;
-+}
-+
-+static struct fb_ops mbxfb_ops = {
-+	.owner		= THIS_MODULE,
-+	.fb_check_var	= mbxfb_check_var,
-+	.fb_set_par	= mbxfb_set_par,
-+	.fb_setcolreg	= mbxfb_setcolreg,
-+	.fb_fillrect	= cfb_fillrect,
-+	.fb_copyarea	= cfb_copyarea,
-+	.fb_imageblit	= cfb_imageblit,
-+	.fb_blank	= mbxfb_blank,
-+};
-+
-+/*
-+   Enable external SDRAM controller. Assume that all clocks are active
-+   by now. 
-+*/
-+static void setup_memc(struct fb_info *fbi)
-+{
-+	unsigned long tmp;
-+
-+	/* FIXME: use platfrom specific parameters */
-+	/* setup SDRAM controller */
-+	LMCFG = LMCFG_LMC_DS | LMCFG_LMC_TS | LMCFG_LMD_TS | LMCFG_LMA_TS;
-+	udelay(1000);
-+	LMPWR = LMPWR_MC_PWR_ACT;
-+	udelay(1000);
-+	/* setup SDRAM timings */
-+	LMTIM = Lmtim_Tras(7) | Lmtim_Trp(3) | Lmtim_Trcd(3) | Lmtim_Trc(9) |
-+		Lmtim_Tdpl(2);
-+	udelay(1000);
-+	/* setup SDRAM refresh rate */
-+	LMREFRESH = 0xc2b;
-+	udelay(1000);
-+	/* setup SDRAM type parameters */
-+	LMTYPE = LMTYPE_CASLAT_3 | LMTYPE_BKSZ_2 | LMTYPE_ROWSZ_11 | 
-+		LMTYPE_COLSZ_8;
-+	udelay(1000);
-+	/* enable memory controller */
-+	LMPWR = LMPWR_MC_PWR_ACT;
-+	udelay(1000);
-+
-+	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
-+	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
-+	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
-+	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
-+	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
-+	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
-+	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
-+	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
-+	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
-+	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
-+	tmp = *(unsigned long*)(virt_base_2700 + MEMORY_OFFSET);
-+}
-+
-+static void enable_clocks(struct fb_info* fbi)
-+{
-+	/* enable clocks */
-+	SYSCLKSRC = SYSCLKSRC_PLL_2; udelay(1000);
-+	PIXCLKSRC = PIXCLKSRC_PLL_1; udelay(1000);
-+	CLKSLEEP = 0x00000000; udelay(1000);
-+	COREPLL = Core_Pll_M(0x17) | Core_Pll_N(0x3) | Core_Pll_P(0x0) | CORE_PLL_EN; udelay(1000);
-+	DISPPLL = Disp_Pll_M(0x1b) | Disp_Pll_N(0x7) | Disp_Pll_P(0x1) | DISP_PLL_EN;
-+
-+	VOVRCLK = 0x00000000; udelay(1000);
-+	PIXCLK = PIXCLK_EN; udelay(1000);
-+	MEMCLK = MEMCLK_EN; udelay(1000);
-+	M24CLK = 0x00000006; udelay(1000);
-+	MBXCLK = 0x00000006; udelay(1000);
-+	SDCLK = SDCLK_EN; udelay(1000);
-+	PIXCLKDIV = 0x00000001; udelay(1000);
-+}
-+
-+static void setup_graphics(struct fb_info* fbi)
-+{
-+	unsigned long gsctrl;
-+
-+	gsctrl = GSCTRL_GAMMA