eglibc/gcc: add patches to fix eglibc 2.15 build

This drops one patch against eglibc for 2.15 and adds two new ones,
also it adds a gcc patch. We use all of these internally and they
are tested quite well.

Signed-off-by: Matthew McClintock <msm@freescale.com>

4 files changed, 4048 insertions, 467 deletions

diff --git a/meta/recipes-devtools/gcc/gcc-4.6.inc b/meta/recipes-devtools/gcc/gcc-4.6.inc
index 4c6fe28f5d..c9529f02c6 100644
--- a/meta/recipes-devtools/gcc/gcc-4.6.inc
+++ b/meta/recipes-devtools/gcc/gcc-4.6.inc
@@ -1,6 +1,6 @@
 require gcc-common.inc
 
-PR = "r28"
+PR = "r29"
 
 # Third digit in PV should be incremented after a minor release
 # happens from this branch on gcc e.g. currently its 4.6.0
@@ -64,7 +64,6 @@ SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH};proto=http \
 	   file://disable_relax_pic_calls_flag.patch \
 	   file://COLLECT_GCC_OPTIONS.patch \
            file://use-defaults.h-and-t-oe-in-B.patch \
-	   file://powerpc-e5500.patch \
            file://fix-for-ice-50099.patch \
 	   file://gcc-with-linker-hash-style.patch \
 	   file://pr46934.patch \
@@ -74,6 +73,8 @@ SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH};proto=http \
 	   file://GPLUSPLUS_INCLUDE_DIR_with_sysroot.patch \
 	   file://fortran-cross-compile-hack.patch \
 	   file://cpp-honour-sysroot.patch \
+	   file://gcc.e6500-FSF46.patch \
+	   file://gcc.no_power_builtins.patch \
 	  "
 
 SRC_URI_append_sh3  = " file://sh3-installfix-fixheaders.patch "
diff --git a/meta/recipes-devtools/gcc/gcc-4.6/gcc.e6500-FSF46.patch b/meta/recipes-devtools/gcc/gcc-4.6/gcc.e6500-FSF46.patch
new file mode 100644
index 0000000000..2de5f778e4
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc-4.6/gcc.e6500-FSF46.patch
@@ -0,0 +1,4015 @@
+Upstream-Status: Pending
+
+People are working to include this fixes upstream
+
+diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/altivec.h gcc-4.6.2/gcc/config/rs6000/altivec.h
+--- gcc-4.6.2-orig/gcc/config/rs6000/altivec.h	2011-02-02 23:42:19.000000000 -0600
++++ gcc-4.6.2/gcc/config/rs6000/altivec.h	2012-03-06 12:33:43.943038996 -0600
+@@ -322,6 +322,30 @@
+ #define vec_vsx_st __builtin_vec_vsx_st
+ #endif
+ 
++#ifdef __ALTIVEC2__
++/* New Altivec instructions */
++#define vec_absd __builtin_vec_absd
++#define vec_lvexbx __builtin_vec_lvexbx
++#define vec_lvexhx __builtin_vec_lvexhx
++#define vec_lvexwx __builtin_vec_lvexwx
++#define vec_stvexbx __builtin_vec_stvexbx
++#define vec_stvexhx __builtin_vec_stvexhx
++#define vec_stvexwx __builtin_vec_stvexwx
++#define vec_lvswx __builtin_vec_lvswx
++#define vec_lvswxl __builtin_vec_lvswxl
++#define vec_stvswx __builtin_vec_stvswx
++#define vec_stvswxl __builtin_vec_stvswxl
++#define vec_lvsm __builtin_vec_lvsm
++#define vec_lvtlx __builtin_vec_lvtlx
++#define vec_lvtlxl __builtin_vec_lvtlxl
++#define vec_lvtrx __builtin_vec_lvtrx
++#define vec_lvtrxl __builtin_vec_lvtrxl
++#define vec_stvflx __builtin_vec_stvflx
++#define vec_stvflxl __builtin_vec_stvflxl
++#define vec_stvfrx __builtin_vec_stvfrx
++#define vec_stvfrxl __builtin_vec_stvfrxl
++#endif
++
+ /* Predicates.
+    For C++, we use templates in order to allow non-parenthesized arguments.
+    For C, instead, we use macros since non-parenthesized arguments were
+diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/altivec.md gcc-4.6.2/gcc/config/rs6000/altivec.md
+--- gcc-4.6.2-orig/gcc/config/rs6000/altivec.md	2011-07-08 15:10:18.000000000 -0500
++++ gcc-4.6.2/gcc/config/rs6000/altivec.md	2012-03-06 12:24:35.058038999 -0600
+@@ -91,9 +91,11 @@
+    (UNSPEC_LVSL         194)
+    (UNSPEC_LVSR         195)
+    (UNSPEC_LVE          196)
++   (UNSPEC_LVEX         197)
+    (UNSPEC_STVX         201)
+    (UNSPEC_STVXL        202)
+    (UNSPEC_STVE         203)
++   (UNSPEC_STVEX        204)
+    (UNSPEC_SET_VSCR     213)
+    (UNSPEC_GET_VRSAVE   214)
+    (UNSPEC_LVX		215)
+@@ -123,6 +125,19 @@
+    (UNSPEC_STVLXL       241)
+    (UNSPEC_STVRX        242)
+    (UNSPEC_STVRXL       243)
++   (UNSPEC_LVTLX        244)
++   (UNSPEC_LVTLXL	245)
++   (UNSPEC_LVTRX	246)
++   (UNSPEC_LVTRXL	247)
++   (UNSPEC_STVFLX	248)
++   (UNSPEC_STVFLXL	249)
++   (UNSPEC_STVFRX	250)
++   (UNSPEC_STVFRXL	251)
++   (UNSPEC_LVSWX        252)
++   (UNSPEC_LVSWXL       253)
++   (UNSPEC_LVSM         254)
++   (UNSPEC_STVSWX       255)
++   (UNSPEC_STVSWXL      256)
+    (UNSPEC_VMULWHUB     308)
+    (UNSPEC_VMULWLUB     309)
+    (UNSPEC_VMULWHSB     310)
+@@ -143,6 +158,9 @@
+    (UNSPEC_VUPKLS_V4SF  325)
+    (UNSPEC_VUPKHU_V4SF  326)
+    (UNSPEC_VUPKLU_V4SF  327)
++   (UNSPEC_VABSDUB      328)
++   (UNSPEC_VABSDUH      329)
++   (UNSPEC_VABSDUW      330)
+ ])
+ 
+ (define_constants
+@@ -323,6 +341,34 @@
+ 
+ ;; Simple binary operations.
+ 
++;; absd
++(define_insn "altivec_vabsduw"
++  [(set (match_operand:V4SI 0 "register_operand" "=v")
++        (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
++                      (match_operand:V4SI 2 "register_operand" "v")]
++		     UNSPEC_VABSDUW))]
++  "TARGET_ALTIVEC2"
++  "vabsduw %0,%1,%2"
++  [(set_attr "type" "vecsimple")])
++
++(define_insn "altivec_vabsduh"
++  [(set (match_operand:V8HI 0 "register_operand" "=v")
++        (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
++                      (match_operand:V8HI 2 "register_operand" "v")]
++		     UNSPEC_VABSDUH))]
++  "TARGET_ALTIVEC2"
++  "vabsduh %0,%1,%2"
++  [(set_attr "type" "vecsimple")])
++
++(define_insn "altivec_vabsdub"
++  [(set (match_operand:V16QI 0 "register_operand" "=v")
++        (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
++                       (match_operand:V16QI 2 "register_operand" "v")]
++		      UNSPEC_VABSDUB))]
++  "TARGET_ALTIVEC2"
++  "vabsdub %0,%1,%2"
++  [(set_attr "type" "vecsimple")])
++
+ ;; add
+ (define_insn "add<mode>3"
+   [(set (match_operand:VI 0 "register_operand" "=v")
+@@ -1741,6 +1787,15 @@
+   "lvewx %0,%y1"
+   [(set_attr "type" "vecload")])
+ 
++(define_insn "altivec_lvex<VI_char>x"
++  [(parallel
++    [(set (match_operand:VI 0 "register_operand" "=v")
++	  (match_operand:VI 1 "memory_operand" "Z"))
++     (unspec [(const_int 0)] UNSPEC_LVEX)])]
++  "TARGET_ALTIVEC2"
++  "lvex<VI_char>x %0,%y1"
++  [(set_attr "type" "vecload")])
++
+ (define_insn "altivec_lvxl"
+   [(parallel
+     [(set (match_operand:V4SI 0 "register_operand" "=v")
+@@ -1791,6 +1846,13 @@
+   "stvewx %1,%y0"
+   [(set_attr "type" "vecstore")])
+ 
++(define_insn "altivec_stvex<VI_char>x"
++  [(set (match_operand:<VI_scalar> 0 "memory_operand" "=Z")
++	(unspec:<VI_scalar> [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVEX))]
++  "TARGET_ALTIVEC2"
++  "stvex<VI_char>x %1,%y0"
++  [(set_attr "type" "vecstore")])
++
+ ;; Generate
+ ;;    vspltis? SCRATCH0,0
+ ;;    vsubu?m SCRATCH2,SCRATCH1,%1
+@@ -2358,7 +2420,7 @@
+   DONE;
+ }")
+ 
+-;; Vector SIMD PEM v2.06c defines LVLX, LVLXL, LVRX, LVRXL,
++;; Vector SIMD PEM v2.06c defines LVLX, LVLXL, LVRX1, LVRXL,
+ ;; STVLX, STVLXL, STVVRX, STVRXL are available only on Cell.
+ (define_insn "altivec_lvlx"
+   [(set (match_operand:V16QI 0 "register_operand" "=v")
+@@ -2394,8 +2456,8 @@
+ 
+ (define_insn "altivec_stvlx"
+   [(parallel
+-    [(set (match_operand:V4SI 0 "memory_operand" "=Z")
+-	  (match_operand:V4SI 1 "register_operand" "v"))
++    [(set (match_operand:V16QI 0 "memory_operand" "=Z")
++	  (match_operand:V16QI 1 "register_operand" "v"))
+      (unspec [(const_int 0)] UNSPEC_STVLX)])]
+   "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
+   "stvlx %1,%y0"
+@@ -2403,8 +2465,8 @@
+ 
+ (define_insn "altivec_stvlxl"
+   [(parallel
+-    [(set (match_operand:V4SI 0 "memory_operand" "=Z")
+-	  (match_operand:V4SI 1 "register_operand" "v"))
++    [(set (match_operand:V16QI 0 "memory_operand" "=Z")
++	  (match_operand:V16QI 1 "register_operand" "v"))
+      (unspec [(const_int 0)] UNSPEC_STVLXL)])]
+   "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
+   "stvlxl %1,%y0"
+@@ -2412,8 +2474,8 @@
+ 
+ (define_insn "altivec_stvrx"
+   [(parallel
+-    [(set (match_operand:V4SI 0 "memory_operand" "=Z")
+-	  (match_operand:V4SI 1 "register_operand" "v"))
++    [(set (match_operand:V16QI 0 "memory_operand" "=Z")
++	  (match_operand:V16QI 1 "register_operand" "v"))
+      (unspec [(const_int 0)] UNSPEC_STVRX)])]
+   "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
+   "stvrx %1,%y0"
+@@ -2421,13 +2483,123 @@
+ 
+ (define_insn "altivec_stvrxl"
+   [(parallel
+-    [(set (match_operand:V4SI 0 "memory_operand" "=Z")
+-	  (match_operand:V4SI 1 "register_operand" "v"))
++    [(set (match_operand:V16QI 0 "memory_operand" "=Z")
++	  (match_operand:V16QI 1 "register_operand" "v"))
+      (unspec [(const_int 0)] UNSPEC_STVRXL)])]
+   "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
+   "stvrxl %1,%y0"
+   [(set_attr "type" "vecstore")])
+ 
++(define_insn "altivec_lvtlx"
++  [(set (match_operand:V16QI 0 "register_operand" "=v")
++        (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] 
++                     UNSPEC_LVTLX))]
++  "TARGET_ALTIVEC2"
++  "lvtlx %0,%y1"
++  [(set_attr "type" "vecload")])
++
++(define_insn "altivec_lvtlxl"
++  [(set (match_operand:V16QI 0 "register_operand" "=v")
++        (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] 
++                     UNSPEC_LVTLXL))]
++  "TARGET_ALTIVEC2"
++  "lvtlxl %0,%y1"
++  [(set_attr "type" "vecload")])
++
++(define_insn "altivec_lvtrx"
++  [(set (match_operand:V16QI 0 "register_operand" "=v")
++        (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] 
++                     UNSPEC_LVTRX))]
++  "TARGET_ALTIVEC2"
++  "lvtrx %0,%y1"
++  [(set_attr "type" "vecload")])
++
++(define_insn "altivec_lvtrxl"
++  [(set (match_operand:V16QI 0 "register_operand" "=v")
++        (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] 
++                     UNSPEC_LVTRXL))]
++  "TARGET_ALTIVEC2"
++  "lvtrxl %0,%y1"
++  [(set_attr "type" "vecload")])
++
++(define_insn "altivec_stvflx"
++  [(parallel
++    [(set (match_operand:V16QI 0 "memory_operand" "=Z")
++         (match_operand:V16QI 1 "register_operand" "v"))
++     (unspec [(const_int 0)] UNSPEC_STVFLX)])]
++  "TARGET_ALTIVEC2"
++  "stvflx %1,%y0"
++  [(set_attr "type" "vecstore")])
++
++(define_insn "altivec_stvflxl"
++  [(parallel
++    [(set (match_operand:V16QI 0 "memory_operand" "=Z")
++         (match_operand:V16QI 1 "register_operand" "v"))
++     (unspec [(const_int 0)] UNSPEC_STVFLXL)])]
++  "TARGET_ALTIVEC2"
++  "stvflxl %1,%y0"
++  [(set_attr "type" "vecstore")])
++
++(define_insn "altivec_stvfrx"
++  [(parallel
++    [(set (match_operand:V16QI 0 "memory_operand" "=Z")
++         (match_operand:V16QI 1 "register_operand" "v"))
++     (unspec [(const_int 0)] UNSPEC_STVFRX)])]
++  "TARGET_ALTIVEC2"
++  "stvfrx %1,%y0"
++  [(set_attr "type" "vecstore")])
++
++(define_insn "altivec_stvfrxl"
++  [(parallel
++    [(set (match_operand:V16QI 0 "memory_operand" "=Z")
++         (match_operand:V16QI 1 "register_operand" "v"))
++     (unspec [(const_int 0)] UNSPEC_STVFRXL)])]
++  "TARGET_ALTIVEC2"
++  "stvfrxl %1,%y0"
++  [(set_attr "type" "vecstore")])
++
++(define_insn "altivec_lvswx"
++  [(set (match_operand:V16QI 0 "register_operand" "=v")
++        (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] 
++		      UNSPEC_LVSWX))]
++  "TARGET_ALTIVEC2"
++  "lvswx %0,%y1"
++  [(set_attr "type" "vecload")])
++
++(define_insn "altivec_lvswxl"
++  [(set (match_operand:V16QI 0 "register_operand" "=v")
++        (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] 
++		      UNSPEC_LVSWXL))]
++  "TARGET_ALTIVEC2"
++  "lvswxl %0,%y1"
++  [(set_attr "type" "vecload")])
++
++(define_insn "altivec_lvsm"
++  [(set (match_operand:V16QI 0 "register_operand" "=v")
++        (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] 
++		      UNSPEC_LVSM))]
++  "TARGET_ALTIVEC2"
++  "lvsm %0,%y1"
++  [(set_attr "type" "vecload")])
++
++(define_insn "altivec_stvswx"
++  [(parallel
++    [(set (match_operand:V16QI 0 "memory_operand" "=Z")
++	  (match_operand:V16QI 1 "register_operand" "v"))
++     (unspec [(const_int 0)] UNSPEC_STVSWX)])]
++  "TARGET_ALTIVEC2"
++  "stvswx %1,%y0"
++  [(set_attr "type" "vecstore")])
++
++(define_insn "altivec_stvswxl"
++  [(parallel
++    [(set (match_operand:V16QI 0 "memory_operand" "=Z")
++	  (match_operand:V16QI 1 "register_operand" "v"))
++     (unspec [(const_int 0)] UNSPEC_STVSWXL)])]
++  "TARGET_ALTIVEC2"
++  "stvswxl %1,%y0"
++  [(set_attr "type" "vecstore")])
++
+ (define_expand "vec_extract_evenv4si"
+  [(set (match_operand:V4SI 0 "register_operand" "")
+         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "")
+diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/e5500.md gcc-4.6.2/gcc/config/rs6000/e5500.md
+--- gcc-4.6.2-orig/gcc/config/rs6000/e5500.md	1969-12-31 18:00:00.000000000 -0600
++++ gcc-4.6.2/gcc/config/rs6000/e5500.md	2012-03-06 12:16:07.590039001 -0600
+@@ -0,0 +1,176 @@
++;; Pipeline description for Freescale PowerPC e5500 core.
++;;   Copyright (C) 2011 Free Software Foundation, Inc.
++;;   Contributed by Edmar Wienskoski (edmar@freescale.com)
++;;
++;; This file is part of GCC.
++;;
++;; GCC is free software; you can redistribute it and/or modify it
++;; under the terms of the GNU General Public License as published
++;; by the Free Software Foundation; either version 3, or (at your
++;; option) any later version.
++;;
++;; GCC is distributed in the hope that it will be useful, but WITHOUT
++;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++;; License for more details.
++;;
++;; You should have received a copy of the GNU General Public License
++;; along with GCC; see the file COPYING3.  If not see
++;; <http://www.gnu.org/licenses/>.
++;;
++;; e5500 64-bit SFX(2), CFX, LSU, FPU, BU
++;; Max issue 3 insns/clock cycle (includes 1 branch)
++
++(define_automaton "e5500_most,e5500_long")
++(define_cpu_unit "e5500_decode_0,e5500_decode_1" "e5500_most")
++
++;; SFX.
++(define_cpu_unit "e5500_sfx_0,e5500_sfx_1" "e5500_most")
++
++;; CFX.
++(define_cpu_unit "e5500_cfx_stage0,e5500_cfx_stage1" "e5500_most")
++
++;; Non-pipelined division.
++(define_cpu_unit "e5500_cfx_div" "e5500_long")
++
++;; LSU.
++(define_cpu_unit "e5500_lsu" "e5500_most")
++
++;; FPU.
++(define_cpu_unit "e5500_fpu" "e5500_long")
++
++;; BU.
++(define_cpu_unit "e5500_bu" "e5500_most")
++
++;; The following units are used to make the automata deterministic.
++(define_cpu_unit "present_e5500_decode_0" "e5500_most")
++(define_cpu_unit "present_e5500_sfx_0" "e5500_most")
++(presence_set "present_e5500_decode_0" "e5500_decode_0")
++(presence_set "present_e5500_sfx_0" "e5500_sfx_0")
++
++;; Some useful abbreviations.
++(define_reservation "e5500_decode"
++    "e5500_decode_0|e5500_decode_1+present_e5500_decode_0")
++(define_reservation "e5500_sfx"
++   "e5500_sfx_0|e5500_sfx_1+present_e5500_sfx_0")
++
++;; SFX.
++(define_insn_reservation "e5500_sfx" 1
++  (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\
++	shift,cntlz,exts")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,e5500_sfx")
++
++(define_insn_reservation "e5500_sfx2" 2
++  (and (eq_attr "type" "cmp,compare,fast_compare,trap")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,e5500_sfx")
++
++(define_insn_reservation "e5500_delayed" 2
++  (and (eq_attr "type" "var_shift_rotate,var_delayed_compare,popcnt")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,e5500_sfx*2")
++
++(define_insn_reservation "e5500_two" 2
++  (and (eq_attr "type" "two")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,e5500_decode+e5500_sfx,e5500_sfx")
++
++(define_insn_reservation "e5500_three" 3
++  (and (eq_attr "type" "three")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,(e5500_decode+e5500_sfx)*2,e5500_sfx")
++
++;; SFX - Mfcr.
++(define_insn_reservation "e5500_mfcr" 4
++  (and (eq_attr "type" "mfcr")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,e5500_sfx_0*4")
++
++;; SFX - Mtcrf.
++(define_insn_reservation "e5500_mtcrf" 1
++  (and (eq_attr "type" "mtcr")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,e5500_sfx_0")
++
++;; SFX - Mtjmpr.
++(define_insn_reservation "e5500_mtjmpr" 1
++  (and (eq_attr "type" "mtjmpr,mfjmpr")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,e5500_sfx")
++
++;; CFX - Multiply.
++(define_insn_reservation "e5500_multiply" 4
++  (and (eq_attr "type" "imul")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,e5500_cfx_stage0,e5500_cfx_stage1")
++
++(define_insn_reservation "e5500_multiply_i" 5
++  (and (eq_attr "type" "imul2,imul3,imul_compare")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,e5500_cfx_stage0,\
++   e5500_cfx_stage0+e5500_cfx_stage1,e5500_cfx_stage1")
++
++;; CFX - Divide.
++(define_insn_reservation "e5500_divide" 16
++  (and (eq_attr "type" "idiv")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
++   e5500_cfx_div*15")
++
++(define_insn_reservation "e5500_divide_d" 26
++  (and (eq_attr "type" "ldiv")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,e5500_cfx_stage0+e5500_cfx_div,\
++   e5500_cfx_div*25")
++
++;; LSU - Loads.
++(define_insn_reservation "e5500_load" 3
++  (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
++			load_l,sync")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,e5500_lsu")
++
++(define_insn_reservation "e5500_fpload" 4
++  (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,e5500_lsu")
++
++;; LSU - Stores.
++(define_insn_reservation "e5500_store" 3
++  (and (eq_attr "type" "store,store_ux,store_u,store_c")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,e5500_lsu")
++
++(define_insn_reservation "e5500_fpstore" 3
++  (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,e5500_lsu")
++
++;; FP.
++(define_insn_reservation "e5500_float" 7
++  (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,e5500_fpu")
++
++(define_insn_reservation "e5500_sdiv" 20
++  (and (eq_attr "type" "sdiv")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,e5500_fpu*20")
++
++(define_insn_reservation "e5500_ddiv" 35
++  (and (eq_attr "type" "ddiv")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,e5500_fpu*35")
++
++;; BU.
++(define_insn_reservation "e5500_branch" 1
++  (and (eq_attr "type" "jmpreg,branch,isync")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,e5500_bu")
++
++;; BU - CR logical.
++(define_insn_reservation "e5500_cr_logical" 1
++  (and (eq_attr "type" "cr_logical,delayed_cr")
++       (eq_attr "cpu" "ppce5500"))
++  "e5500_decode,e5500_bu")
+diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/e6500.md gcc-4.6.2/gcc/config/rs6000/e6500.md
+--- gcc-4.6.2-orig/gcc/config/rs6000/e6500.md	1969-12-31 18:00:00.000000000 -0600
++++ gcc-4.6.2/gcc/config/rs6000/e6500.md	2012-03-06 12:16:25.573039002 -0600
+@@ -0,0 +1,213 @@
++;; Pipeline description for Freescale PowerPC e6500 core.
++;;   Copyright (C) 2011 Free Software Foundation, Inc.
++;;   Contributed by Edmar Wienskoski (edmar@freescale.com)
++;;
++;; This file is part of GCC.
++;;
++;; GCC is free software; you can redistribute it and/or modify it
++;; under the terms of the GNU General Public License as published
++;; by the Free Software Foundation; either version 3, or (at your
++;; option) any later version.
++;;
++;; GCC is distributed in the hope that it will be useful, but WITHOUT
++;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++;; License for more details.
++;;
++;; You should have received a copy of the GNU General Public License
++;; along with GCC; see the file COPYING3.  If not see
++;; <http://www.gnu.org/licenses/>.
++;;
++;; e6500 64-bit SFX(2), CFX, LSU, FPU, BU, VSFX, VCFX, VFPU, VPERM
++;; Max issue 3 insns/clock cycle (includes 1 branch)
++
++(define_automaton "e6500_most,e6500_long,e6500_vec")
++(define_cpu_unit "e6500_decode_0,e6500_decode_1" "e6500_most")
++
++;; SFX.
++(define_cpu_unit "e6500_sfx_0,e6500_sfx_1" "e6500_most")
++
++;; CFX.
++(define_cpu_unit "e6500_cfx_stage0,e6500_cfx_stage1" "e6500_most")
++
++;; Non-pipelined division.
++(define_cpu_unit "e6500_cfx_div" "e6500_long")
++
++;; LSU.
++(define_cpu_unit "e6500_lsu" "e6500_most")
++
++;; FPU.
++(define_cpu_unit "e6500_fpu" "e6500_long")
++
++;; BU.
++(define_cpu_unit "e6500_bu" "e6500_most")
++
++;; Altivec unit
++(define_cpu_unit "e6500_vec,e6500_vecperm" "e6500_vec")
++
++;; The following units are used to make the automata deterministic.
++(define_cpu_unit "present_e6500_decode_0" "e6500_most")
++(define_cpu_unit "present_e6500_sfx_0" "e6500_most")
++(presence_set "present_e6500_decode_0" "e6500_decode_0")
++(presence_set "present_e6500_sfx_0" "e6500_sfx_0")
++
++;; Some useful abbreviations.
++(define_reservation "e6500_decode"
++    "e6500_decode_0|e6500_decode_1+present_e6500_decode_0")
++(define_reservation "e6500_sfx"
++   "e6500_sfx_0|e6500_sfx_1+present_e6500_sfx_0")
++
++;; SFX.
++(define_insn_reservation "e6500_sfx" 1
++  (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\
++	shift,cntlz,exts")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_sfx")
++
++(define_insn_reservation "e6500_sfx2" 2
++  (and (eq_attr "type" "cmp,compare,fast_compare,trap")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_sfx")
++
++(define_insn_reservation "e6500_delayed" 2
++  (and (eq_attr "type" "var_shift_rotate,var_delayed_compare,popcnt")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_sfx*2")
++
++(define_insn_reservation "e6500_two" 2
++  (and (eq_attr "type" "two")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_decode+e6500_sfx,e6500_sfx")
++
++(define_insn_reservation "e6500_three" 3
++  (and (eq_attr "type" "three")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,(e6500_decode+e6500_sfx)*2,e6500_sfx")
++
++;; SFX - Mfcr.
++(define_insn_reservation "e6500_mfcr" 4
++  (and (eq_attr "type" "mfcr")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_sfx_0*4")
++
++;; SFX - Mtcrf.
++(define_insn_reservation "e6500_mtcrf" 1
++  (and (eq_attr "type" "mtcr")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_sfx_0")
++
++;; SFX - Mtjmpr.
++(define_insn_reservation "e6500_mtjmpr" 1
++  (and (eq_attr "type" "mtjmpr,mfjmpr")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_sfx")
++
++;; CFX - Multiply.
++(define_insn_reservation "e6500_multiply" 4
++  (and (eq_attr "type" "imul")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_cfx_stage0,e6500_cfx_stage1")
++
++(define_insn_reservation "e6500_multiply_i" 5
++  (and (eq_attr "type" "imul2,imul3,imul_compare")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_cfx_stage0,\
++   e6500_cfx_stage0+e6500_cfx_stage1,e6500_cfx_stage1")
++
++;; CFX - Divide.
++(define_insn_reservation "e6500_divide" 16
++  (and (eq_attr "type" "idiv")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
++   e6500_cfx_div*15")
++
++(define_insn_reservation "e6500_divide_d" 26
++  (and (eq_attr "type" "ldiv")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
++   e6500_cfx_div*25")
++
++;; LSU - Loads.
++(define_insn_reservation "e6500_load" 3
++  (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
++			load_l,sync")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_lsu")
++
++(define_insn_reservation "e6500_fpload" 4
++  (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_lsu")
++
++(define_insn_reservation "e6500_vecload" 4
++  (and (eq_attr "type" "vecload")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_lsu")
++
++;; LSU - Stores.
++(define_insn_reservation "e6500_store" 3
++  (and (eq_attr "type" "store,store_ux,store_u,store_c")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_lsu")
++
++(define_insn_reservation "e6500_fpstore" 3
++  (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_lsu")
++
++(define_insn_reservation "e6500_vecstore" 4
++  (and (eq_attr "type" "vecstore")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_lsu")
++
++;; FP.
++(define_insn_reservation "e6500_float" 7
++  (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_fpu")
++
++(define_insn_reservation "e6500_sdiv" 20
++  (and (eq_attr "type" "sdiv")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_fpu*20")
++
++(define_insn_reservation "e6500_ddiv" 35
++  (and (eq_attr "type" "ddiv")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_fpu*35")
++
++;; BU.
++(define_insn_reservation "e6500_branch" 1
++  (and (eq_attr "type" "jmpreg,branch,isync")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_bu")
++
++;; BU - CR logical.
++(define_insn_reservation "e6500_cr_logical" 1
++  (and (eq_attr "type" "cr_logical,delayed_cr")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_bu")
++
++;; VSFX.
++(define_insn_reservation "e6500_vecsimple" 1
++  (and (eq_attr "type" "vecsimple,veccmp")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_vec")
++
++;; VCFX.
++(define_insn_reservation "e6500_veccomplex" 4
++  (and (eq_attr "type" "veccomplex")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_vec")
++
++;; VFPU.
++(define_insn_reservation "e6500_vecfloat" 6
++  (and (eq_attr "type" "vecfloat")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_vec")
++
++;; VPERM.
++(define_insn_reservation "e6500_vecperm" 2
++  (and (eq_attr "type" "vecperm")
++       (eq_attr "cpu" "ppce6500"))
++  "e6500_decode,e6500_vecperm")
+diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/rs6000-builtin.def gcc-4.6.2/gcc/config/rs6000/rs6000-builtin.def
+--- gcc-4.6.2-orig/gcc/config/rs6000/rs6000-builtin.def	2011-02-21 15:38:21.000000000 -0600
++++ gcc-4.6.2/gcc/config/rs6000/rs6000-builtin.def	2012-03-06 12:37:40.248039025 -0600
+@@ -224,6 +224,9 @@
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEBX,			RS6000_BTC_MEM)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEHX,			RS6000_BTC_MEM)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEWX,			RS6000_BTC_MEM)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEXBX,			RS6000_BTC_MEM)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEXHX,			RS6000_BTC_MEM)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_LVEXWX,			RS6000_BTC_MEM)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_LVXL,			RS6000_BTC_MEM)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_LVX,			RS6000_BTC_MEM)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_STVX,			RS6000_BTC_MEM)
+@@ -231,14 +234,30 @@
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_LVLXL,			RS6000_BTC_MEM)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_LVRX,			RS6000_BTC_MEM)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_LVRXL,			RS6000_BTC_MEM)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_LVTLX,			RS6000_BTC_MEM)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_LVTLXL,			RS6000_BTC_MEM)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_LVTRX,			RS6000_BTC_MEM)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_LVTRXL,			RS6000_BTC_MEM)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_LVSWX,			RS6000_BTC_MEM)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_LVSWXL,			RS6000_BTC_MEM)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_LVSM,			RS6000_BTC_MEM)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEBX,			RS6000_BTC_MEM)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEHX,			RS6000_BTC_MEM)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEWX,			RS6000_BTC_MEM)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEXBX,			RS6000_BTC_MEM)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEXHX,			RS6000_BTC_MEM)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_STVEXWX,			RS6000_BTC_MEM)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_STVXL,			RS6000_BTC_MEM)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_STVLX,			RS6000_BTC_MEM)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_STVLXL,			RS6000_BTC_MEM)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_STVRX,			RS6000_BTC_MEM)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_STVRXL,			RS6000_BTC_MEM)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_STVFLX,			RS6000_BTC_MEM)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_STVFLXL,			RS6000_BTC_MEM)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_STVFRX,			RS6000_BTC_MEM)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_STVFRXL,			RS6000_BTC_MEM)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_STVSWX,			RS6000_BTC_MEM)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_STVSWXL,			RS6000_BTC_MEM)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPBFP_P,		RS6000_BTC_FP_PURE)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQFP_P,		RS6000_BTC_FP_PURE)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPEQUB_P,		RS6000_BTC_CONST)
+@@ -275,6 +294,9 @@
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_EXT_V4SF,		RS6000_BTC_CONST)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_COPYSIGN_V4SF,		RS6000_BTC_CONST)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VRECIPFP,		RS6000_BTC_FP_PURE)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_ABSDUB,			RS6000_BTC_CONST)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_ABSDUH,			RS6000_BTC_CONST)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_ABSDUW,			RS6000_BTC_CONST)
+ 
+ /* Altivec overloaded builtins.  */
+ /* For now, don't set the classification for overloaded functions.
+@@ -286,6 +308,7 @@
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGT_P,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VCMPGE_P,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ABS,			RS6000_BTC_MISC)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ABSD,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ABSS,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ADD,			RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_ADDC,		RS6000_BTC_MISC)
+@@ -321,10 +344,20 @@
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEBX,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEHX,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEWX,		RS6000_BTC_MISC)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEXBX,		RS6000_BTC_MISC)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEXHX,		RS6000_BTC_MISC)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVEXWX,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVLX,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVLXL,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVRX,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVRXL,		RS6000_BTC_MISC)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVTLX,		RS6000_BTC_MISC)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVTLXL,		RS6000_BTC_MISC)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVTRX,		RS6000_BTC_MISC)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVTRXL,		RS6000_BTC_MISC)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVSWX,		RS6000_BTC_MISC)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVSWXL,		RS6000_BTC_MISC)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVSM,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVSL,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_LVSR,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_MADD,		RS6000_BTC_MISC)
+@@ -389,10 +422,19 @@
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEBX,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEHX,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEWX,		RS6000_BTC_MISC)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEXBX,		RS6000_BTC_MISC)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEXHX,		RS6000_BTC_MISC)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVEXWX,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVLX,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVLXL,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVRX,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVRXL,		RS6000_BTC_MISC)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVFLX,		RS6000_BTC_MISC)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVFLXL,		RS6000_BTC_MISC)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVFRX,		RS6000_BTC_MISC)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVFRXL,		RS6000_BTC_MISC)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVSWX,		RS6000_BTC_MISC)
++RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_STVSWXL,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUB,			RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUBC,		RS6000_BTC_MISC)
+ RS6000_BUILTIN(ALTIVEC_BUILTIN_VEC_SUBS,		RS6000_BTC_MISC)
+diff -ruN gcc-4.6.2-orig/gcc/config/rs6000/rs6000.c gcc-4.6.2/gcc/config/rs6000/rs6000.c
+--- gcc-4.6.2-orig/gcc/config/rs6000/rs6000.c	2011-09-18 17:01:56.000000000 -0500
++++ gcc-4.6.2/gcc/config/rs6000/rs6000.c	2012-03-06 12:44:04.689039002 -0600
+@@ -779,6 +779,44 @@
+   1,			/* prefetch streams /*/
+ };
+ 
++/* Instruction costs on PPCE5500 processors.  */
++static const
++struct processor_costs ppce5500_cost = {
++  COSTS_N_INSNS (5),    /* mulsi */
++  COSTS_N_INSNS (5),    /* mulsi_const */
++  COSTS_N_INSNS (4),    /* mulsi_const9 */
++  COSTS_N_INSNS (5),    /* muldi */
++  COSTS_N_INSNS (14),   /* divsi */
++  COSTS_N_INSNS (14),   /* divdi */
++  COSTS_N_INSNS (7),    /* fp */
++  COSTS_N_INSNS (10),   /* dmul */
++  COSTS_N_INSNS (36),   /* sdiv */
++  COSTS_N_INSNS (66),   /* ddiv */
++  64,			/* cache line size */
++  32,			/* l1 cache */
++  128,			/* l2 cache */
++  1,			/* prefetch streams /*/
++};
++
++/* Instruction costs on PPCE6500 processors.  */
++static const
++struct processor_costs ppce6500_cost = {
++  COSTS_N_INSNS (5),    /* mulsi */
++  COSTS_N_INSNS (5),    /* mulsi_const */
++  COSTS_N_INSNS (4),    /* mulsi_const9 */
++  COSTS_N_INSNS (5),    /* muldi */
++  COSTS_N_INSNS (14),   /* divsi */
++  COSTS_N_INSNS (14),   /* divdi */
++  COSTS_N_INSNS (7),    /* fp */
++  COSTS_N_INSNS (10),   /* dmul */
++  COSTS_N_INSNS (36),   /* sdiv */
++  COSTS_N_INSNS (66),   /* ddiv */
++  64,			/* cache line size */
++  32,			/* l1 cache */
++  128,			/* l2 cache */
++  1,			/* prefetch streams /*/
++};
++
+ /* Instruction costs on AppliedMicro Titan processors.  */
+ static const
+ struct processor_costs titan_cost = {
+@@ -1690,7 +1728,7 @@
+ 		   | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
+ 		   | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP
+ 		   | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE
+-		   | MASK_RECIP_PRECISION)
++		   | MASK_RECIP_PRECISION | MASK_ALTIVEC2)
+ };
+ 
+ /* Masks for instructions set at various powerpc ISAs.  */
+@@ -1785,6 +1823,12 @@
+    | MASK_ISEL},
+   {"e500mc64", PROCESSOR_PPCE500MC64, POWERPC_BASE_MASK | MASK_POWERPC64
+    | MASK_PPC_GFXOPT | MASK_ISEL},
++  {"e5500", PROCESSOR_PPCE5500, POWERPC_BASE_MASK | MASK_POWERPC64
++   | MASK_PPC_GFXOPT | MASK_ISEL | MASK_CMPB | MASK_POPCNTB
++   | MASK_POPCNTD},
++  {"e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
++   | MASK_MFCRF | MASK_ISEL | MASK_CMPB | MASK_POPCNTB | MASK_POPCNTD
++   | MASK_ALTIVEC2},
+   {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
+   {"970", PROCESSOR_POWER4,
+    POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
+@@ -2742,13 +2786,19 @@
+ 		   : PROCESSOR_DEFAULT));
+ 
+   if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
+-      || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64)
++      || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
++      || rs6000_cpu == PROCESSOR_PPCE5500)
+     {
+       if (TARGET_ALTIVEC)
+ 	error ("AltiVec not supported in this target");
+       if (TARGET_SPE)
+ 	error ("SPE not supported in this target");
+     }
++  if (rs6000_cpu == PROCESSOR_PPCE6500)
++    {
++