linux-moblin: Add 2.6.27 moblin kernel

This will be the default moblin kernel.
We also moved the 2.6.27-rc* kernels to meta-moblin.

14 files changed, 0 insertions, 31974 deletions

diff --git a/meta/packages/linux/linux-moblin-2.6.27-rc1/0001_Export_shmem_file_setup_for_DRM-GEM.patch b/meta/packages/linux/linux-moblin-2.6.27-rc1/0001_Export_shmem_file_setup_for_DRM-GEM.patch
deleted file mode 100644
index 9589838afa..0000000000
--- a/meta/packages/linux/linux-moblin-2.6.27-rc1/0001_Export_shmem_file_setup_for_DRM-GEM.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From: Keith Packard <keithp@keithp.com>
-Date: Fri, 20 Jun 2008 07:08:06 +0000 (-0700)
-Subject: Export shmem_file_setup for DRM-GEM
-X-Git-Tag: v2.6.12-rc2
-X-Git-Url: http://gitweb.freedesktop.org/?p=users/anholt/anholt/linux-2.6.git;a=commitdiff;h=350ea3ece12744ae154bbc2ea13da6ba84ca5515
-
-Export shmem_file_setup for DRM-GEM
-
-GEM needs to create shmem files to back buffer objects.  Though currently
-creation of files for objects could have been driven from userland, the
-modesetting work will require allocation of buffer objects before userland
-is running, for boot-time message display.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
-
---- a/mm/shmem.c
-+++ b/mm/shmem.c
-@@ -2582,6 +2582,7 @@ put_memory:
- 	shmem_unacct_size(flags, size);
- 	return ERR_PTR(error);
- }
-+EXPORT_SYMBOL(shmem_file_setup);
- 
- /**
-  * shmem_zero_setup - setup a shared anonymous mapping
-
diff --git a/meta/packages/linux/linux-moblin-2.6.27-rc1/0002_i915.Use_more_consistent_names_for_regs.patch b/meta/packages/linux/linux-moblin-2.6.27-rc1/0002_i915.Use_more_consistent_names_for_regs.patch
deleted file mode 100644
index 9a035b544c..0000000000
--- a/meta/packages/linux/linux-moblin-2.6.27-rc1/0002_i915.Use_more_consistent_names_for_regs.patch
+++ /dev/null
@@ -1,2739 +0,0 @@
-From: Jesse Barnes <jbarnes@virtuousgeek.org>
-Date: Tue, 29 Jul 2008 18:54:06 +0000 (-0700)
-Subject: i915: Use more consistent names for regs, and store them in a separate file.
-X-Git-Tag: v2.6.12-rc2
-X-Git-Url: http://gitweb.freedesktop.org/?p=users/anholt/anholt/linux-2.6.git;a=commitdiff;h=db1cbbd8c4d42e58e9acb3e7af59ad1bb238260d
-
-i915: Use more consistent names for regs, and store them in a separate file.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
-
---- a/drivers/gpu/drm/i915/i915_dma.c
-+++ b/drivers/gpu/drm/i915/i915_dma.c
-@@ -40,11 +40,11 @@ int i915_wait_ring(struct drm_device * d
- {
- 	drm_i915_private_t *dev_priv = dev->dev_private;
- 	drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
--	u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
-+	u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
- 	int i;
- 
- 	for (i = 0; i < 10000; i++) {
--		ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
-+		ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
- 		ring->space = ring->head - (ring->tail + 8);
- 		if (ring->space < 0)
- 			ring->space += ring->Size;
-@@ -67,8 +67,8 @@ void i915_kernel_lost_context(struct drm
- 	drm_i915_private_t *dev_priv = dev->dev_private;
- 	drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
- 
--	ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
--	ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
-+	ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
-+	ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
- 	ring->space = ring->head - (ring->tail + 8);
- 	if (ring->space < 0)
- 		ring->space += ring->Size;
-@@ -98,13 +98,13 @@ static int i915_dma_cleanup(struct drm_d
- 		drm_pci_free(dev, dev_priv->status_page_dmah);
- 		dev_priv->status_page_dmah = NULL;
- 		/* Need to rewrite hardware status page */
--		I915_WRITE(0x02080, 0x1ffff000);
-+		I915_WRITE(HWS_PGA, 0x1ffff000);
- 	}
- 
- 	if (dev_priv->status_gfx_addr) {
- 		dev_priv->status_gfx_addr = 0;
- 		drm_core_ioremapfree(&dev_priv->hws_map, dev);
--		I915_WRITE(0x2080, 0x1ffff000);
-+		I915_WRITE(HWS_PGA, 0x1ffff000);
- 	}
- 
- 	return 0;
-@@ -170,7 +170,7 @@ static int i915_initialize(struct drm_de
- 		dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
- 
- 		memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
--		I915_WRITE(0x02080, dev_priv->dma_status_page);
-+		I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
- 	}
- 	DRM_DEBUG("Enabled hardware status page\n");
- 	return 0;
-@@ -201,9 +201,9 @@ static int i915_dma_resume(struct drm_de
- 	DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
- 
- 	if (dev_priv->status_gfx_addr != 0)
--		I915_WRITE(0x02080, dev_priv->status_gfx_addr);
-+		I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
- 	else
--		I915_WRITE(0x02080, dev_priv->dma_status_page);
-+		I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
- 	DRM_DEBUG("Enabled hardware status page\n");
- 
- 	return 0;
-@@ -402,8 +402,8 @@ static void i915_emit_breadcrumb(struct 
- 		dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
- 
- 	BEGIN_LP_RING(4);
--	OUT_RING(CMD_STORE_DWORD_IDX);
--	OUT_RING(20);
-+	OUT_RING(MI_STORE_DWORD_INDEX);
-+	OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
- 	OUT_RING(dev_priv->counter);
- 	OUT_RING(0);
- 	ADVANCE_LP_RING();
-@@ -505,7 +505,7 @@ static int i915_dispatch_flip(struct drm
- 	i915_kernel_lost_context(dev);
- 
- 	BEGIN_LP_RING(2);
--	OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
-+	OUT_RING(MI_FLUSH | MI_READ_FLUSH);
- 	OUT_RING(0);
- 	ADVANCE_LP_RING();
- 
-@@ -530,8 +530,8 @@ static int i915_dispatch_flip(struct drm
- 	dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
- 
- 	BEGIN_LP_RING(4);
--	OUT_RING(CMD_STORE_DWORD_IDX);
--	OUT_RING(20);
-+	OUT_RING(MI_STORE_DWORD_INDEX);
-+	OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
- 	OUT_RING(dev_priv->counter);
- 	OUT_RING(0);
- 	ADVANCE_LP_RING();
-@@ -728,8 +728,8 @@ static int i915_set_status_page(struct d
- 	dev_priv->hw_status_page = dev_priv->hws_map.handle;
- 
- 	memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
--	I915_WRITE(0x02080, dev_priv->status_gfx_addr);
--	DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
-+	I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
-+	DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
- 			dev_priv->status_gfx_addr);
- 	DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
- 	return 0;
---- a/drivers/gpu/drm/i915/i915_drv.c
-+++ b/drivers/gpu/drm/i915/i915_drv.c
-@@ -279,13 +279,13 @@ static int i915_suspend(struct drm_devic
- 	dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
- 	dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
- 	dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
--	dev_priv->saveDSPABASE = I915_READ(DSPABASE);
-+	dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
- 	if (IS_I965G(dev)) {
- 		dev_priv->saveDSPASURF = I915_READ(DSPASURF);
- 		dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
- 	}
- 	i915_save_palette(dev, PIPE_A);
--	dev_priv->savePIPEASTAT = I915_READ(I915REG_PIPEASTAT);
-+	dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
- 
- 	/* Pipe & plane B info */
- 	dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
-@@ -307,13 +307,13 @@ static int i915_suspend(struct drm_devic
- 	dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
- 	dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
- 	dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
--	dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
-+	dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
- 	if (IS_I965GM(dev) || IS_IGD_GM(dev)) {
- 		dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
- 		dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
- 	}
- 	i915_save_palette(dev, PIPE_B);
--	dev_priv->savePIPEBSTAT = I915_READ(I915REG_PIPEBSTAT);
-+	dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
- 
- 	/* CRT state */
- 	dev_priv->saveADPA = I915_READ(ADPA);
-@@ -328,9 +328,9 @@ static int i915_suspend(struct drm_devic
- 		dev_priv->saveLVDS = I915_READ(LVDS);
- 	if (!IS_I830(dev) && !IS_845G(dev))
- 		dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
--	dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON);
--	dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF);
--	dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);
-+	dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
-+	dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
-+	dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
- 
- 	/* FIXME: save TV & SDVO state */
- 
-@@ -341,19 +341,19 @@ static int i915_suspend(struct drm_devic
- 	dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
- 
- 	/* Interrupt state */
--	dev_priv->saveIIR = I915_READ(I915REG_INT_IDENTITY_R);
--	dev_priv->saveIER = I915_READ(I915REG_INT_ENABLE_R);
--	dev_priv->saveIMR = I915_READ(I915REG_INT_MASK_R);
-+	dev_priv->saveIIR = I915_READ(IIR);
-+	dev_priv->saveIER = I915_READ(IER);
-+	dev_priv->saveIMR = I915_READ(IMR);
- 
- 	/* VGA state */
--	dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
--	dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
--	dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
-+	dev_priv->saveVGA0 = I915_READ(VGA0);
-+	dev_priv->saveVGA1 = I915_READ(VGA1);
-+	dev_priv->saveVGA_PD = I915_READ(VGA_PD);
- 	dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
- 
- 	/* Clock gating state */
- 	dev_priv->saveD_STATE = I915_READ(D_STATE);
--	dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
-+	dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS);
- 
- 	/* Cache mode state */
- 	dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
-@@ -363,7 +363,7 @@ static int i915_suspend(struct drm_devic
- 
- 	/* Scratch space */
- 	for (i = 0; i < 16; i++) {
--		dev_priv->saveSWF0[i] = I915_READ(SWF0 + (i << 2));
-+		dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
- 		dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
- 	}
- 	for (i = 0; i < 3; i++)
-@@ -424,7 +424,7 @@ static int i915_resume(struct drm_device
- 	I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
- 	I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
- 	I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
--	I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
-+	I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
- 	I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
- 	if (IS_I965G(dev)) {
- 		I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
-@@ -436,7 +436,7 @@ static int i915_resume(struct drm_device
- 	i915_restore_palette(dev, PIPE_A);
- 	/* Enable the plane */
- 	I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
--	I915_WRITE(DSPABASE, I915_READ(DSPABASE));
-+	I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
- 
- 	/* Pipe & plane B info */
- 	if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
-@@ -466,7 +466,7 @@ static int i915_resume(struct drm_device
- 	I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
- 	I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
- 	I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
--	I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
-+	I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
- 	I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
- 	if (IS_I965G(dev)) {
- 		I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
-@@ -478,7 +478,7 @@ static int i915_resume(struct drm_device
- 	i915_restore_palette(dev, PIPE_B);
- 	/* Enable the plane */
- 	I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
--	I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
-+	I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
- 
- 	/* CRT state */
- 	I915_WRITE(ADPA, dev_priv->saveADPA);
-@@ -493,9 +493,9 @@ static int i915_resume(struct drm_device
- 
- 	I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
- 	I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
--	I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON);
--	I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF);
--	I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
-+	I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
-+	I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
-+	I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
- 	I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
- 
- 	/* FIXME: restore TV & SDVO state */
-@@ -508,14 +508,14 @@ static int i915_resume(struct drm_device
- 
- 	/* VGA state */
- 	I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
--	I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
--	I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
--	I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
-+	I915_WRITE(VGA0, dev_priv->saveVGA0);
-+	I915_WRITE(VGA1, dev_priv->saveVGA1);
-+	I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
- 	udelay(150);
- 
- 	/* Clock gating state */
- 	I915_WRITE (D_STATE, dev_priv->saveD_STATE);
--	I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
-+	I915_WRITE(CG_2D_DIS, dev_priv->saveCG_2D_DIS);
- 
- 	/* Cache mode state */
- 	I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
-@@ -524,7 +524,7 @@ static int i915_resume(struct drm_device
- 	I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
- 
- 	for (i = 0; i < 16; i++) {
--		I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF0[i]);
-+		I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
- 		I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
- 	}
- 	for (i = 0; i < 3; i++)
---- a/drivers/gpu/drm/i915/i915_drv.h
-+++ b/drivers/gpu/drm/i915/i915_drv.h
-@@ -30,6 +30,8 @@
- #ifndef _I915_DRV_H_
- #define _I915_DRV_H_
- 
-+#include "i915_reg.h"
-+
- /* General customization:
-  */
- 
-@@ -138,7 +140,7 @@ typedef struct drm_i915_private {
- 	u32 saveDSPASTRIDE;
- 	u32 saveDSPASIZE;
- 	u32 saveDSPAPOS;
--	u32 saveDSPABASE;
-+	u32 saveDSPAADDR;
- 	u32 saveDSPASURF;
- 	u32 saveDSPATILEOFF;
- 	u32 savePFIT_PGM_RATIOS;
-@@ -159,24 +161,24 @@ typedef struct drm_i915_private {
- 	u32 saveDSPBSTRIDE;
- 	u32 saveDSPBSIZE;
- 	u32 saveDSPBPOS;
--	u32 saveDSPBBASE;
-+	u32 saveDSPBADDR;
- 	u32 saveDSPBSURF;
- 	u32 saveDSPBTILEOFF;
--	u32 saveVCLK_DIVISOR_VGA0;
--	u32 saveVCLK_DIVISOR_VGA1;
--	u32 saveVCLK_POST_DIV;
-+	u32 saveVGA0;
-+	u32 saveVGA1;
-+	u32 saveVGA_PD;
- 	u32 saveVGACNTRL;
- 	u32 saveADPA;
- 	u32 saveLVDS;
--	u32 saveLVDSPP_ON;
--	u32 saveLVDSPP_OFF;
-+	u32 savePP_ON_DELAYS;
-+	u32 savePP_OFF_DELAYS;
- 	u32 saveDVOA;
- 	u32 saveDVOB;
- 	u32 saveDVOC;
- 	u32 savePP_ON;
- 	u32 savePP_OFF;
- 	u32 savePP_CONTROL;
--	u32 savePP_CYCLE;
-+	u32 savePP_DIVISOR;
- 	u32 savePFIT_CONTROL;
- 	u32 save_palette_a[256];
- 	u32 save_palette_b[256];
-@@ -189,7 +191,7 @@ typedef struct drm_i915_private {
- 	u32 saveIMR;
- 	u32 saveCACHE_MODE_0;
- 	u32 saveD_STATE;
--	u32 saveDSPCLK_GATE_D;
-+	u32 saveCG_2D_DIS;
- 	u32 saveMI_ARB_STATE;
- 	u32 saveSWF0[16];
- 	u32 saveSWF1[16];
-@@ -283,816 +285,26 @@ extern void i915_mem_release(struct drm_
- 	if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);	\
- 	dev_priv->ring.tail = outring;					\
- 	dev_priv->ring.space -= outcount * 4;				\
--	I915_WRITE(LP_RING + RING_TAIL, outring);			\
-+	I915_WRITE(PRB0_TAIL, outring);			\
- } while(0)
- 
--extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
--
--/* Extended config space */
--#define LBB 0xf4
--
--/* VGA stuff */
--
--#define VGA_ST01_MDA 0x3ba
--#define VGA_ST01_CGA 0x3da
--
--#define VGA_MSR_WRITE 0x3c2
--#define VGA_MSR_READ 0x3cc
--#define   VGA_MSR_MEM_EN (1<<1)
--#define   VGA_MSR_CGA_MODE (1<<0)
--
--#define VGA_SR_INDEX 0x3c4
--#define VGA_SR_DATA 0x3c5
--
--#define VGA_AR_INDEX 0x3c0
--#define   VGA_AR_VID_EN (1<<5)
--#define VGA_AR_DATA_WRITE 0x3c0
--#define VGA_AR_DATA_READ 0x3c1
--
--#define VGA_GR_INDEX 0x3ce
--#define VGA_GR_DATA 0x3cf
--/* GR05 */
--#define   VGA_GR_MEM_READ_MODE_SHIFT 3
--#define     VGA_GR_MEM_READ_MODE_PLANE 1
--/* GR06 */
--#define   VGA_GR_MEM_MODE_MASK 0xc
--#define   VGA_GR_MEM_MODE_SHIFT 2
--#define   VGA_GR_MEM_A0000_AFFFF 0
--#define   VGA_GR_MEM_A0000_BFFFF 1
--#define   VGA_GR_MEM_B0000_B7FFF 2
--#define   VGA_GR_MEM_B0000_BFFFF 3
--
--#define VGA_DACMASK 0x3c6
--#define VGA_DACRX 0x3c7
--#define VGA_DACWX 0x3c8
--#define VGA_DACDATA 0x3c9
--
--#define VGA_CR_INDEX_MDA 0x3b4
--#define VGA_CR_DATA_MDA 0x3b5
--#define VGA_CR_INDEX_CGA 0x3d4
--#define VGA_CR_DATA_CGA 0x3d5
--
--#define GFX_OP_USER_INTERRUPT		((0<<29)|(2<<23))
--#define GFX_OP_BREAKPOINT_INTERRUPT	((0<<29)|(1<<23))
--#define CMD_REPORT_HEAD			(7<<23)
--#define CMD_STORE_DWORD_IDX		((0x21<<23) | 0x1)
--#define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)
--
--#define INST_PARSER_CLIENT   0x00000000
--#define INST_OP_FLUSH        0x02000000
--#define INST_FLUSH_MAP_CACHE 0x00000001
--
--#define BB1_START_ADDR_MASK   (~0x7)
--#define BB1_PROTECTED         (1<<0)
--#define BB1_UNPROTECTED       (0<<0)
--#define BB2_END_ADDR_MASK     (~0x7)
--
--/* Framebuffer compression */
--#define FBC_CFB_BASE		0x03200 /* 4k page aligned */
--#define FBC_LL_BASE		0x03204 /* 4k page aligned */
--#define FBC_CONTROL		0x03208
--#define   FBC_CTL_EN		(1<<31)
--#define   FBC_CTL_PERIODIC	(1<<30)
--#define   FBC_CTL_INTERVAL_SHIFT (16)
--#define   FBC_CTL_UNCOMPRESSIBLE (1<<14)
--#define   FBC_CTL_STRIDE_SHIFT	(5)
--#define   FBC_CTL_FENCENO	(1<<0)
--#define FBC_COMMAND		0x0320c
--#define   FBC_CMD_COMPRESS	(1<<0)
--#define FBC_STATUS		0x03210
--#define   FBC_STAT_COMPRESSING	(1<<31)
--#define   FBC_STAT_COMPRESSED	(1<<30)
--#define   FBC_STAT_MODIFIED	(1<<29)
--#define   FBC_STAT_CURRENT_LINE	(1<<0)
--#define FBC_CONTROL2		0x03214
--#define   FBC_CTL_FENCE_DBL	(0<<4)
--#define   FBC_CTL_IDLE_IMM	(0<<2)
--#define   FBC_CTL_IDLE_FULL	(1<<2)
--#define   FBC_CTL_IDLE_LINE	(2<<2)
--#define   FBC_CTL_IDLE_DEBUG	(3<<2)
--#define   FBC_CTL_CPU_FENCE	(1<<1)
--#define   FBC_CTL_PLANEA	(0<<0)
--#define   FBC_CTL_PLANEB	(1<<0)
--#define FBC_FENCE_OFF		0x0321b
--
--#define FBC_LL_SIZE		(1536)
--#define FBC_LL_PAD		(32)
--
--/* Interrupt bits:
-- */
--#define USER_INT_FLAG    (1<<1)
--#define VSYNC_PIPEB_FLAG (1<<5)
--#define VSYNC_PIPEA_FLAG (1<<7)
--#define HWB_OOM_FLAG     (1<<13) /* binner out of memory */
--
--#define I915REG_HWSTAM		0x02098
--#define I915REG_INT_IDENTITY_R	0x020a4
--#define I915REG_INT_MASK_R	0x020a8
--#define I915REG_INT_ENABLE_R	0x020a0
--
--#define I915REG_PIPEASTAT	0x70024
--#define I915REG_PIPEBSTAT	0x71024
--
--#define I915_VBLANK_INTERRUPT_ENABLE	(1UL<<17)
--#define I915_VBLANK_CLEAR		(1UL<<1)
--
--#define SRX_INDEX		0x3c4
--#define SRX_DATA		0x3c5
--#define SR01			1
--#define SR01_SCREEN_OFF		(1<<5)
--
--#define PPCR			0x61204
--#define PPCR_ON			(1<<0)
--
--#define DVOB			0x61140
--#define DVOB_ON			(1<<31)
--#define DVOC			0x61160
--#define DVOC_ON			(1<<31)
--#define LVDS			0x61180
--#define LVDS_ON			(1<<31)
--
--#define ADPA			0x61100
--#define ADPA_DPMS_MASK		(~(3<<10))
--#define ADPA_DPMS_ON		(0<<10)
--#define ADPA_DPMS_SUSPEND	(1<<10)
--#define ADPA_DPMS_STANDBY	(2<<10)
--#define ADPA_DPMS_OFF		(3<<10)
--
--#define NOPID                   0x2094
--#define LP_RING			0x2030
--#define HP_RING			0x2040
--/* The binner has its own ring buffer:
-- */
--#define HWB_RING		0x2400
--
--#define RING_TAIL		0x00
--#define TAIL_ADDR		0x001FFFF8
--#define RING_HEAD		0x04
--#define HEAD_WRAP_COUNT		0xFFE00000
--#define HEAD_WRAP_ONE		0x00200000
--#define HEAD_ADDR		0x001FFFFC
--#define RING_START		0x08
--#define START_ADDR		0x0xFFFFF000
--#define RING_LEN		0x0C
--#define RING_NR_PAGES		0x001FF000
--#define RING_REPORT_MASK	0x00000006
--#define RING_REPORT_64K		0x00000002
--#define RING_REPORT_128K	0x00000004
--#define RING_NO_REPORT		0x00000000
--#define RING_VALID_MASK		0x00000001
--#define RING_VALID		0x00000001
--#define RING_INVALID		0x00000000
--
--/* Instruction parser error reg:
-- */
--#define IPEIR			0x2088
--
--/* Scratch pad debug 0 reg:
-- */
--#define SCPD0			0x209c
--
--/* Error status reg:
-- */
--#define ESR			0x20b8
--
--/* Secondary DMA fetch address debug reg:
-- */
--#define DMA_FADD_S		0x20d4
--
--/* Memory Interface Arbitration State
-- */
--#define MI_ARB_STATE		0x20e4
--
--/* Cache mode 0 reg.
-- *  - Manipulating render cache behaviour is central
-- *    to the concept of zone rendering, tuning this reg can help avoid
-- *    unnecessary render cache reads and even writes (for z/stencil)
-- *    at beginning and end of scene.
-- *
-- * - To change a bit, write to this reg with a mask bit set and the
-- * bit of interest either set or cleared.  EG: (BIT<<16) | BIT to set.
-- */
--#define Cache_Mode_0		0x2120
--#define CACHE_MODE_0		0x2120
--#define CM0_MASK_SHIFT          16
--#define CM0_IZ_OPT_DISABLE      (1<<6)
--#define CM0_ZR_OPT_DISABLE      (1<<5)
--#define CM0_DEPTH_EVICT_DISABLE (1<<4)
--#define CM0_COLOR_EVICT_DISABLE (1<<3)
--#define CM0_DEPTH_WRITE_DISABLE (1<<1)
--#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
--
--
--/* Graphics flush control.  A CPU write flushes the GWB of all writes.
-- * The data is discarded.
-- */
--#define GFX_FLSH_CNTL		0x2170
--
--/* Binner control.  Defines the location of the bin pointer list:
-- */
--#define BINCTL			0x2420
--#define BC_MASK			(1 << 9)
--
--/* Binned scene info.
-- */
--#define BINSCENE		0x2428
--#define BS_OP_LOAD		(1 << 8)
--#define BS_MASK			(1 << 22)
--
--/* Bin command parser debug reg:
-- */
--#define BCPD			0x2480
--
--/* Bin memory control debug reg:
-- */
--#define BMCD			0x2484
--
--/* Bin data cache debug reg:
-- */
--#define BDCD			0x2488
--
--/* Binner pointer cache debug reg:
-- */
--#define BPCD			0x248c
--
--/* Binner scratch pad debug reg:
-- */
--#define BINSKPD			0x24f0
--
--/* HWB scratch pad debug reg:
-- */
--#define HWBSKPD			0x24f4
--
--/* Binner memory pool reg:
-- */
--#define BMP_BUFFER		0x2430
--#define BMP_PAGE_SIZE_4K	(0 << 10)
--#define BMP_BUFFER_SIZE_SHIFT	1
--#define BMP_ENABLE		(1 << 0)
--
--/* Get/put memory from the binner memory pool:
-- */
--#define BMP_GET			0x2438
--#define BMP_PUT			0x2440
--#define BMP_OFFSET_SHIFT	5
--
--/* 3D state packets:
-- */
--#define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
--
--#define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
--#define SC_UPDATE_SCISSOR       (0x1<<1)
--#define SC_ENABLE_MASK          (0x1<<0)
--#define SC_ENABLE               (0x1<<0)
--
--#define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
--
--#define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
--#define SCI_YMIN_MASK      (0xffff<<16)
--#define SCI_XMIN_MASK      (0xffff<<0)
--#define SCI_YMAX_MASK      (0xffff<<16)
--#define SCI_XMAX_MASK      (0xffff<<0)
--
--#define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
--#define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
--#define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
--#define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
--#define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
--#define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
--#define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
--
--#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
--
--#define SRC_COPY_BLT_CMD                ((2<<29)|(0x43<<22)|4)
--#define XY_SRC_COPY_BLT_CMD		((2<<29)|(0x53<<22)|6)
--#define XY_SRC_COPY_BLT_WRITE_ALPHA	(1<<21)
--#define XY_SRC_COPY_BLT_WRITE_RGB	(1<<20)
--#define XY_SRC_COPY_BLT_SRC_TILED	(1<<15)
--#define XY_SRC_COPY_BLT_DST_TILED	(1<<11)
--
--#define MI_BATCH_BUFFER		((0x30<<23)|1)
--#define MI_BATCH_BUFFER_START	(0x31<<23)
--#define MI_BATCH_BUFFER_END	(0xA<<23)
--#define MI_BATCH_NON_SECURE	(1)
--#define MI_BATCH_NON_SECURE_I965 (1<<8)
--
--#define MI_WAIT_FOR_EVENT       ((0x3<<23))
--#define MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
--#define MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
--#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
--
--#define MI_LOAD_SCAN_LINES_INCL  ((0x12<<23))
--
--#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
--#define ASYNC_FLIP                (1<<22)
--#define DISPLAY_PLANE_A           (0<<20)
--#define DISPLAY_PLANE_B           (1<<20)
--
--/* Display regs */
--#define DSPACNTR                0x70180
--#define DSPBCNTR                0x71180
--#define DISPPLANE_SEL_PIPE_MASK                 (1<<24)
--
--/* Define the region of interest for the binner:
-- */
--#define CMD_OP_BIN_CONTROL	 ((0x3<<29)|(0x1d<<24)|(0x84<<16)|4)
--
--#define CMD_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
--
--#define CMD_MI_FLUSH         (0x04 << 23)
--#define MI_NO_WRITE_FLUSH    (1 << 2)
--#define MI_READ_FLUSH        (1 << 0)
--#define MI_EXE_FLUSH         (1 << 1)
--#define MI_END_SCENE         (1 << 4) /* flush binner and incr scene count */
--#define MI_SCENE_COUNT       (1 << 3) /* just increment scene count */
--
--#define BREADCRUMB_BITS 31
--#define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)
--
--#define READ_BREADCRUMB(dev_priv)  (((volatile u32*)(dev_priv->hw_status_page))[5])
--#define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
--
--#define BLC_PWM_CTL		0x61254
--#define BACKLIGHT_MODULATION_FREQ_SHIFT		(17)
--
--#define BLC_PWM_CTL2		0x61250
- /**
-- * This is the most significant 15 bits of the number of backlight cycles in a
-- * complete cycle of the modulated backlight control.
-+ * Reads a dword out of the status page, which is written to from the command
-+ * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
-+ * MI_STORE_DATA_IMM.
-+ *
-+ * The following dwords have a reserved meaning:
-+ * 0: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
-+ * 4: ring 0 head pointer
-+ * 5: ring 1 head pointer (915-class)
-+ * 6: ring 2 head pointer (915-class)
-  *
-- * The actual value is this field multiplied by two.
-+ * The area from dword 0x10 to 0x3ff is available for driver usage.
-  */
--#define BACKLIGHT_MODULATION_FREQ_MASK		(0x7fff << 17)
--#define BLM_LEGACY_MODE				(1 << 16)
--/**
-- * This is the number of cycles out of the backlight modulation cycle for which
-- * the backlight is on.
-- *
-- * This field must be no greater than the number of cycles in the complete
-- * backlight modulation cycle.
-- */
--#define BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
--#define BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
--
--#define I915_GCFGC			0xf0
--#define I915_LOW_FREQUENCY_ENABLE		(1 << 7)
--#define I915_DISPLAY_CLOCK_190_200_MHZ		(0 << 4)
--#define I915_DISPLAY_CLOCK_333_MHZ		(4 << 4)
--#define I915_DISPLAY_CLOCK_MASK			(7 << 4)
--
--#define I855_HPLLCC			0xc0
--#define I855_CLOCK_CONTROL_MASK			(3 << 0)
--#define I855_CLOCK_133_200			(0 << 0)
--#define I855_CLOCK_100_200			(1 << 0)
--#define I855_CLOCK_100_133			(2 << 0)
--#define I855_CLOCK_166_250			(3 << 0)
--
--/* p317, 319
-- */
--#define VCLK2_VCO_M        0x6008 /* treat as 16 bit? (includes msbs) */
--#define VCLK2_VCO_N        0x600a
--#define VCLK2_VCO_DIV_SEL  0x6012
--
--#define VCLK_DIVISOR_VGA0   0x6000
--#define VCLK_DIVISOR_VGA1   0x6004
--#define VCLK_POST_DIV	    0x6010
--/** Selects a post divisor of 4 instead of 2. */
--# define VGA1_PD_P2_DIV_4	(1 << 15)
--/** Overrides the p2 post divisor field */
--# define VGA1_PD_P1_DIV_2	(1 << 13)
--# define VGA1_PD_P1_SHIFT	8
--/** P1 value is 2 greater than this field */
--# define VGA1_PD_P1_MASK	(0x1f << 8)
--/** Selects a post divisor of 4 instead of 2. */
--# define VGA0_PD_P2_DIV_4	(1 << 7)
--/** Overrides the p2 post divisor field */
--# define VGA0_PD_P1_DIV_2	(1 << 5)
--# define VGA0_PD_P1_SHIFT	0
--/** P1 value is 2 greater than this field */
--# define VGA0_PD_P1_MASK	(0x1f << 0)
--
--/* PCI D state control register */
--#define D_STATE		0x6104
--#define DSPCLK_GATE_D	0x6200
--
--/* I830 CRTC registers */
--#define HTOTAL_A	0x60000
--#define HBLANK_A	0x60004
--#define HSYNC_A		0x60008
--#define VTOTAL_A	0x6000c
--#define VBLANK_A	0x60010
--#define VSYNC_A		0x60014
--#define PIPEASRC	0x6001c
--#define BCLRPAT_A	0x60020
--#define VSYNCSHIFT_A	0x60028
--
--#define HTOTAL_B	0x61000
--#define HBLANK_B	0x61004
--#define HSYNC_B		0x61008
--#define VTOTAL_B	0x6100c
--#define VBLANK_B	0x61010
--#define VSYNC_B		0x61014
--#define PIPEBSRC	0x6101c
--#define BCLRPAT_B	0x61020
--#define VSYNCSHIFT_B	0x61028
--
--#define PP_STATUS	0x61200
--# define PP_ON					(1 << 31)
--/**
-- * Indicates that all dependencies of the panel are on:
-- *
-- * - PLL enabled
-- * - pipe enabled
-- * - LVDS/DVOB/DVOC on
-- */
--# define PP_READY				(1 << 30)
--# define PP_SEQUENCE_NONE			(0 << 28)
--# define PP_SEQUENCE_ON				(1 << 28)
--# define PP_SEQUENCE_OFF			(2 << 28)
--# define PP_SEQUENCE_MASK			0x30000000
--#define PP_CONTROL	0x61204
--# define POWER_TARGET_ON			(1 << 0)
--
--#define LVDSPP_ON       0x61208
--#define LVDSPP_OFF      0x6120c
--#define PP_CYCLE        0x61210
--
--#define PFIT_CONTROL	0x61230
--# define PFIT_ENABLE				(1 << 31)
--# define PFIT_PIPE_MASK				(3 << 29)
--# define PFIT_PIPE_SHIFT			29
--# define VERT_INTERP_DISABLE			(0 << 10)
--# define VERT_INTERP_BILINEAR			(1 << 10)
--# define VERT_INTERP_MASK			(3 << 10)
--# define VERT_AUTO_SCALE			(1 << 9)
--# define HORIZ_INTERP_DISABLE			(0 << 6)
--# define HORIZ_INTERP_BILINEAR			(1 << 6)
--# define HORIZ_INTERP_MASK			(3 << 6)
--# define HORIZ_AUTO_SCALE			(1 << 5)
--# define PANEL_8TO6_DITHER_ENABLE		(1 << 3)
--
--#define PFIT_PGM_RATIOS	0x61234
--# define PFIT_VERT_SCALE_MASK			0xfff00000
--# define PFIT_HORIZ_SCALE_MASK			0x0000fff0
--
--#define PFIT_AUTO_RATIOS	0x61238
--
--
--#define DPLL_A		0x06014
--#define DPLL_B		0x06018
--# define DPLL_VCO_ENABLE			(1 << 31)
--# define DPLL_DVO_HIGH_SPEED			(1 << 30)
--# define DPLL_SYNCLOCK_ENABLE			(1 << 29)
--# define DPLL_VGA_MODE_DIS			(1 << 28)
--# define DPLLB_MODE_DAC_SERIAL			(1 << 2