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author | Marcin Juszkiewicz <hrw@openedhand.com> | 2008-04-17 10:04:19 +0000 |
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committer | Marcin Juszkiewicz <hrw@openedhand.com> | 2008-04-17 10:04:19 +0000 |
commit | 66df6d12445faf14fcab925e883375758f7132a2 (patch) | |
tree | 49092dbe08b3a6b9322b9ccf9e0e51a7a6e2c498 /meta/packages/gcc/gcc-4.2.3/arm-crunch-64bit-disable-4.2.0.patch | |
parent | abca3ca42f2097d1cef8c2eb87fce46604618af2 (diff) | |
download | openembedded-core-66df6d12445faf14fcab925e883375758f7132a2.tar.gz openembedded-core-66df6d12445faf14fcab925e883375758f7132a2.tar.bz2 openembedded-core-66df6d12445faf14fcab925e883375758f7132a2.zip |
gcc: upgrade 4.2.2 -> 4.2.3
git-svn-id: https://svn.o-hand.com/repos/poky/trunk@4286 311d38ba-8fff-0310-9ca6-ca027cbcb966
Diffstat (limited to 'meta/packages/gcc/gcc-4.2.3/arm-crunch-64bit-disable-4.2.0.patch')
-rw-r--r-- | meta/packages/gcc/gcc-4.2.3/arm-crunch-64bit-disable-4.2.0.patch | 169 |
1 files changed, 169 insertions, 0 deletions
diff --git a/meta/packages/gcc/gcc-4.2.3/arm-crunch-64bit-disable-4.2.0.patch b/meta/packages/gcc/gcc-4.2.3/arm-crunch-64bit-disable-4.2.0.patch new file mode 100644 index 0000000000..60b17852bd --- /dev/null +++ b/meta/packages/gcc/gcc-4.2.3/arm-crunch-64bit-disable-4.2.0.patch @@ -0,0 +1,169 @@ +--- gcc-4.1.2/gcc/config/arm/cirrus.md-integer 2007-06-15 09:01:37.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/cirrus.md 2007-06-15 09:04:45.000000000 +1000 +@@ -34,7 +34,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (plus:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:DI 2 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfadd64%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] +@@ -74,7 +74,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (minus:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:DI 2 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfsub64%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] +@@ -124,7 +124,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (mult:DI (match_operand:DI 2 "cirrus_fp_register" "v") + (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfmul64%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_dmult") + (set_attr "cirrus" "normal")] +@@ -206,7 +206,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "register_operand" "r")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfrshl64%?\\t%V1, %V0, %s2" + [(set_attr "cirrus" "normal")] + ) +@@ -215,7 +215,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "cirrus_shift_const" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfsh64%?\\t%V0, %V1, #%s2" + [(set_attr "cirrus" "normal")] + ) +@@ -224,7 +224,7 @@ + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (ashiftrt:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "cirrus_shift_const" "")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfsh64%?\\t%V0, %V1, #-%s2" + [(set_attr "cirrus" "normal")] + ) +@@ -232,7 +232,7 @@ + (define_insn "*cirrus_absdi2" + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (abs:DI (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfabs64%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) +@@ -238,11 +238,12 @@ + ) + + ;; This doesn't really clobber ``cc''. Fixme: aldyh. ++;; maybe buggy? + (define_insn "*cirrus_negdi2" + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (neg:DI (match_operand:DI 1 "cirrus_fp_register" "v"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfneg64%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] + ) +@@ -324,14 +324,14 @@ + (define_insn "floatdisf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfcvt64s%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")]) + + (define_insn "floatdidf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "cfcvt64d%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")]) + +@@ -376,7 +376,7 @@ + (define_insn "*cirrus_arm_movdi" + [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v") + (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))] +- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" ++ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0" + "* + { + switch (which_alternative) +--- gcc-4.1.2/gcc/config/arm/arm.md-64 2007-06-15 11:37:42.000000000 +1000 ++++ gcc-4.1.2/gcc/config/arm/arm.md 2007-06-15 11:40:45.000000000 +1000 +@@ -357,7 +357,7 @@ + (clobber (reg:CC CC_REGNUM))])] + "TARGET_EITHER" + " +- if (TARGET_HARD_FLOAT && TARGET_MAVERICK) ++ if (TARGET_HARD_FLOAT && TARGET_MAVERICK && 0) + { + if (!cirrus_fp_register (operands[0], DImode)) + operands[0] = force_reg (DImode, operands[0]); +@@ -393,7 +393,7 @@ + (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0") + (match_operand:DI 2 "s_register_operand" "r, 0"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" ++ "TARGET_ARM" + "#" + "TARGET_ARM && reload_completed" + [(parallel [(set (reg:CC_C CC_REGNUM) +@@ -421,7 +421,7 @@ + (match_operand:SI 2 "s_register_operand" "r,r")) + (match_operand:DI 1 "s_register_operand" "r,0"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" ++ "TARGET_ARM" + "#" + "TARGET_ARM && reload_completed" + [(parallel [(set (reg:CC_C CC_REGNUM) +@@ -450,7 +450,7 @@ + (match_operand:SI 2 "s_register_operand" "r,r")) + (match_operand:DI 1 "s_register_operand" "r,0"))) + (clobber (reg:CC CC_REGNUM))] +- "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" ++ "TARGET_ARM" + "#" + "TARGET_ARM && reload_completed" + [(parallel [(set (reg:CC_C CC_REGNUM) +@@ -838,7 +838,7 @@ + if (TARGET_HARD_FLOAT && TARGET_MAVERICK + && TARGET_ARM + && cirrus_fp_register (operands[0], DImode) +- && cirrus_fp_register (operands[1], DImode)) ++ && cirrus_fp_register (operands[1], DImode) && 0) + { + emit_insn (gen_cirrus_subdi3 (operands[0], operands[1], operands[2])); + DONE; +@@ -2599,7 +2599,7 @@ + values to iwmmxt regs and back. */ + FAIL; + } +- else if (!TARGET_REALLY_IWMMXT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)) ++ else if (!TARGET_REALLY_IWMMXT) + FAIL; + " + ) +@@ -4215,7 +4215,6 @@ + [(set (match_operand:DI 0 "nonimmediate_operand" "=l,l,l,l,>,l, m,*r") + (match_operand:DI 1 "general_operand" "l, I,J,>,l,mi,l,*r"))] + "TARGET_THUMB +- && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) + && ( register_operand (operands[0], DImode) + || register_operand (operands[1], DImode))" + "* |