linux-rp-2.6.23: Add patch to get zylonite mtd working (forward ported 2.6.14 driver) and set display to VGA

git-svn-id: https://svn.o-hand.com/repos/poky/trunk@3786 311d38ba-8fff-0310-9ca6-ca027cbcb966

3 files changed, 4079 insertions, 11 deletions

diff --git a/meta/packages/linux/linux-rp-2.6.23/defconfig-zylonite b/meta/packages/linux/linux-rp-2.6.23/defconfig-zylonite
index 8be4a3bd47..14ea6c355f 100644
--- a/meta/packages/linux/linux-rp-2.6.23/defconfig-zylonite
+++ b/meta/packages/linux/linux-rp-2.6.23/defconfig-zylonite
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.23-rc4
-# Tue Sep 25 15:57:10 2007
+# Linux kernel version: 2.6.23
+# Tue Feb 12 18:04:14 2008
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -65,7 +65,6 @@ CONFIG_FUTEX=y
 CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_VM_EVENT_COUNTERS=y
@@ -262,6 +261,7 @@ CONFIG_BINFMT_ELF=y
 # Power management options
 #
 # CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
 
 #
 # Networking
@@ -272,6 +272,7 @@ CONFIG_NET=y
 # Networking options
 #
 CONFIG_PACKET=m
+# CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
@@ -304,6 +305,7 @@ CONFIG_INET_TCP_DIAG=y
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
 # CONFIG_IPV6 is not set
 # CONFIG_INET6_XFRM_TUNNEL is not set
 # CONFIG_INET6_TUNNEL is not set
@@ -370,7 +372,6 @@ CONFIG_IP_NF_RAW=m
 CONFIG_IP_NF_ARPTABLES=m
 CONFIG_IP_NF_ARPFILTER=m
 CONFIG_IP_NF_ARP_MANGLE=m
-
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
 # CONFIG_TIPC is not set
@@ -551,6 +552,7 @@ CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_SHARPSL is not set
+CONFIG_MTD_NAND_ZYLONITE=y
 # CONFIG_MTD_NAND_NANDSIM is not set
 # CONFIG_MTD_NAND_PLATFORM is not set
 # CONFIG_MTD_ONENAND is not set
@@ -964,11 +966,8 @@ CONFIG_FONT_8x16=y
 CONFIG_LOGO=y
 CONFIG_LOGO_LINUX_MONO=y
 CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_LOGO_OHAND_CLUT224 is not set
-# CONFIG_LOGO_OZ240_CLUT224 is not set
-# CONFIG_LOGO_OZ480_CLUT224 is not set
-# CONFIG_LOGO_OZ640_CLUT224 is not set
+# CONFIG_LOGO_LINUX_CLUT224 is not set
+CONFIG_LOGO_OHAND_CLUT224=y
 
 #
 # Sound
@@ -1025,7 +1024,7 @@ CONFIG_SND_VERBOSE_PROCFS=y
 #
 # CONFIG_SOUND_PRIME is not set
 CONFIG_HID_SUPPORT=y
-CONFIG_HID=m
+CONFIG_HID=y
 # CONFIG_HID_DEBUG is not set
 
 #
@@ -1237,7 +1236,13 @@ CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=m
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
 # CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=m
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
diff --git a/meta/packages/linux/linux-rp-2.6.23/zylonite_mtd-r0.patch b/meta/packages/linux/linux-rp-2.6.23/zylonite_mtd-r0.patch
new file mode 100644
index 0000000000..231b3d76c9
--- /dev/null
+++ b/meta/packages/linux/linux-rp-2.6.23/zylonite_mtd-r0.patch
@@ -0,0 +1,4062 @@
+Gross hacks to make the Zylonite boot from flash in VGA.
+
+Flash driver forward ported to 2.6.14
+
+Index: linux-2.6.23/drivers/mtd/nand/Kconfig
+===================================================================
+--- linux-2.6.23.orig/drivers/mtd/nand/Kconfig	2008-02-12 18:02:36.000000000 +0000
++++ linux-2.6.23/drivers/mtd/nand/Kconfig	2008-02-12 18:03:07.000000000 +0000
+@@ -223,6 +223,10 @@
+ 	tristate "Support for NAND Flash on Sharp SL Series (C7xx + others)"
+ 	depends on ARCH_PXA
+ 
++config MTD_NAND_ZYLONITE
++	tristate "Support for NAND Flash on Zylonite"
++	depends on ARCH_PXA
++
+ config MTD_NAND_BASLER_EXCITE
+ 	tristate  "Support for NAND Flash on Basler eXcite"
+ 	depends on BASLER_EXCITE
+Index: linux-2.6.23/drivers/mtd/nand/Makefile
+===================================================================
+--- linux-2.6.23.orig/drivers/mtd/nand/Makefile	2008-02-12 18:02:36.000000000 +0000
++++ linux-2.6.23/drivers/mtd/nand/Makefile	2008-02-12 18:03:27.000000000 +0000
+@@ -19,6 +19,7 @@
+ obj-$(CONFIG_MTD_NAND_H1900)		+= h1910.o
+ obj-$(CONFIG_MTD_NAND_RTC_FROM4)	+= rtc_from4.o
+ obj-$(CONFIG_MTD_NAND_SHARPSL)		+= sharpsl.o
++obj-$(CONFIG_MTD_NAND_ZYLONITE)		+= mhn_nand.o
+ obj-$(CONFIG_MTD_NAND_TS7250)		+= ts7250.o
+ obj-$(CONFIG_MTD_NAND_NANDSIM)		+= nandsim.o
+ obj-$(CONFIG_MTD_NAND_CS553X)		+= cs553x_nand.o
+Index: linux-2.6.23/drivers/mtd/nand/mhn_nand.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-2.6.23/drivers/mtd/nand/mhn_nand.c	2008-02-12 23:54:00.000000000 +0000
+@@ -0,0 +1,3869 @@
++/*
++ *  drivers/mtd/nand/mhn_nand.c
++ *
++ *  Copyright (C) 2005 Intel Coporation (chao.xie@intel.com)
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ *  Overview:
++ *   This is a device driver for the NAND flash device on zylonite board
++ *   which utilizes the Samsung K9K1216Q0C parts. This is a 64Mibit NAND
++ *   flash device.
++
++ *(C) Copyright 2006 Marvell International Ltd.
++ * All Rights Reserved
++ */
++
++#include <linux/slab.h>
++#include <linux/module.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/nand.h>
++#include <linux/mtd/partitions.h>
++#include <linux/interrupt.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <asm/hardware.h>
++#include <asm/io.h>
++#include <asm/irq.h>
++#include <asm/delay.h>
++#include <asm/dma.h>
++#include <asm/arch/mfp.h>
++//#include <asm/arch/cpu-freq-voltage-mhn.h>
++
++//#define NDCR 0xf0000000
++//#define NDCR        (*((volatile u32 *)0xf0000000))
++//#define NDCR              __REG_2(0x43100000)  /* Data Flash Control register */
++#define NDCR_SPARE_EN             (0x1<<31)
++#define NDCR_ECC_EN               (0x1<<30)
++#define NDCR_DMA_EN               (0x1<<29)
++#define NDCR_ND_RUN               (0x1<<28)
++#define NDCR_DWIDTH_C             (0x1<<27)
++#define NDCR_DWIDTH_M             (0x1<<26)
++#define NDCR_PAGE_SZ              (0x1<<24)
++#define NDCR_NCSX         (0x1<<23)
++#define NDCR_ND_MODE              (0x3<<21)
++#define NDCR_NAND_MODE    0x0
++#define NDCR_CLR_PG_CNT           (0x1<<20)
++#define NDCR_CLR_ECC      (       0x1<<19)
++#define NDCR_RD_ID_CNT_MASK       (0x7<<16)
++#define NDCR_RD_ID_CNT(x)       (((x) << 16) & NDCR_RD_ID_CNT_MASK)
++#define NDCR_RA_START     (0x1<<15)
++#define NDCR_PG_PER_BLK   (0x1<<14)
++#define NDCR_ND_ARB_EN    (0x1<<12)
++
++//#define NDSR        (*((volatile u32 *)0xf0000014))
++//#define NDSR              __REG_2(0x43100014)  /* Data Controller Status Register */
++#define NDSR_RDY  (0x1<<11)
++#define NDSR_CS0_PAGED    (0x1<<10)
++#define NDSR_CS1_PAGED    (0x1<<9)
++#define NDSR_CS0_CMDD     (0x1<<8)
++#define NDSR_CS1_CMDD     (0x1<<7)
++#define NDSR_CS0_BBD      (0x1<<6)
++#define NDSR_CS1_BBD      (0x1<<5)
++#define NDSR_DBERR        (0x1<<4)
++#define NDSR_SBERR        (0x1<<3)
++#define NDSR_WRDREQ       (0x1<<2)
++#define NDSR_RDDREQ       (0x1<<1)
++#define NDSR_WRCMDREQ     (0x1)
++
++#define OSCR              __REG(0x40A00010)  /* OS Timer Counter Register */
++//#define NDCB0             __REG_2(0x43100048)  /* Data Controller Command Buffer0 */
++//#define NDCB1             __REG_2(0x4310004C)  /* Data Controller Command Buffer1 */
++//#define NDCB2             __REG_2(0x43100050)  /* Data Controller Command Buffer2 */
++#define NDCB0_AUTO_RS             (0x1<<25)
++#define NDCB0_CSEL                (0x1<<24)
++#define NDCB0_CMD_TYPE_MASK       (0x7<<21)
++#define   NDCB0_CMD_TYPE(x)       (((x) << 21) & NDCB0_CMD_TYPE_MASK)
++#define NDCB0_NC          (0x1<<20)
++#define NDCB0_DBC         (0x1<<19)
++#define NDCB0_ADDR_CYC_MASK       (0x7<<16)
++#define   NDCB0_ADDR_CYC(x)       (((x) << 16) & NDCB0_ADDR_CYC_MASK)
++#define NDCB0_CMD2_MASK           (0xff<<8)
++#define NDCB0_CMD1_MASK           (0xff)
++#define NDCB0_ADDR_CYC_SHIFT      (16)
++#define DCMD0             __REG(0x4000020c)  /* DMA Command Address Register Channel 0 */
++#define DCMD1             __REG(0x4000021c)  /* DMA Command Address Register Channel 1 */
++#define DCMD2             __REG(0x4000022c)  /* DMA Command Address Register Channel 2 */
++#define DCMD3             __REG(0x4000023c)  /* DMA Command Address Register Channel 3 */
++#define DCMD4             __REG(0x4000024c)  /* DMA Command Address Register Channel 4 */
++#define DCMD5             __REG(0x4000025c)  /* DMA Command Address Register Channel 5 */
++#define DCMD6             __REG(0x4000026c)  /* DMA Command Address Register Channel 6 */
++#define DCMD7             __REG(0x4000027c)  /* DMA Command Address Register Channel 7 */
++#define DCMD8             __REG(0x4000028c)  /* DMA Command Address Register Channel 8 */
++#define DCMD9             __REG(0x4000029c)  /* DMA Command Address Register Channel 9 */
++#define DCMD10            __REG(0x400002ac)  /* DMA Command Address Register Channel 10 */
++#define DCMD11            __REG(0x400002bc)  /* DMA Command Address Register Channel 11 */
++#define DCMD12            __REG(0x400002cc)  /* DMA Command Address Register Channel 12 */
++#define DCMD13            __REG(0x400002dc)  /* DMA Command Address Register Channel 13 */
++#define DCMD14            __REG(0x400002ec)  /* DMA Command Address Register Channel 14 */
++#define DCMD15            __REG(0x400002fc)  /* DMA Command Address Register Channel 15 */
++#define DCMD(x)           __REG2(0x4000020c, (x) << 4)
++#define DCMD_INCSRCADDR   (1 << 31)       /* Source Address Increment Setting. */
++#define DCMD_INCTRGADDR   (1 << 30)       /* Target Address Increment Setting. */
++#define DCMD_FLOWSRC      (1 << 29)       /* Flow Control by the source. */
++#define DCMD_FLOWTRG      (1 << 28)       /* Flow Control by the target. */
++#define DCMD_STARTIRQEN   (1 << 22)       /* Start Interrupt Enable */
++#define DCMD_ENDIRQEN     (1 << 21)       /* End Interrupt Enable */
++#define DCMD_ENDIAN       (1 << 18)       /* Device Endian-ness. */
++#define DCMD_BURST8       (1 << 16)       /* 8 byte burst */
++#define DCMD_BURST16      (2 << 16)       /* 16 byte burst */
++#define DCMD_BURST32      (3 << 16)       /* 32 byte burst */
++#define DCMD_WIDTH1       (1 << 14)       /* 1 byte width */
++#define DCMD_WIDTH2       (2 << 14)       /* 2 byte width (HalfWord) */
++#define DCMD_WIDTH4       (3 << 14)       /* 4 byte width (Word) */
++#define DCMD_LENGTH       0x01fff         /* length mask (max = 8K - 1) */
++#define DCMD_RXPCDR       (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
++#define DCMD_RXMCDR       (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
++#define DCMD_TXPCDR       (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
++#define DRCMR(n)  __REG2(0x40000100, (n)<<2)
++#define DRCMR97           __REG(0x40001184)  /* Request to Channel Map Register for NAND interface data transmit & receive Request */
++#define DRCMR98           __REG(0x40001188)  /* Reserved */
++#define DRCMR99           __REG(0x4000118C)  /* Request to Channel Map Register for NAND interface command transmit Request */
++#define DRCMRRXSADR       DRCMR2
++#define DRCMRTXSADR       DRCMR3
++#define DRCMRRXBTRBR      DRCMR4
++#define DRCMRTXBTTHR      DRCMR5
++#define DRCMRRXFFRBR      DRCMR6
++#define DRCMRTXFFTHR      DRCMR7
++#define DRCMRRXMCDR       DRCMR8
++#define DRCMRRXMODR       DRCMR9
++#define DRCMRTXMODR       DRCMR10
++#define DRCMRRXPCDR       DRCMR11
++#define DRCMRTXPCDR       DRCMR12
++#define DRCMRRXSSDR       DRCMR13
++#define DRCMRTXSSDR       DRCMR14
++#define DRCMRRXICDR       DRCMR17
++#define DRCMRTXICDR       DRCMR18
++#define DRCMRRXSTRBR      DRCMR19
++#define DRCMRTXSTTHR      DRCMR20
++#define DRCMRRXMMC        DRCMR21
++#define DRCMRTXMMC        DRCMR22
++#define DRCMRRXMMC2       DRCMR93
++#define DRCMRTXMMC2       DRCMR94
++#define DRCMRRXMMC3       DRCMR100
++#define DRCMRTXMMC3       DRCMR101
++#define DRCMRUDC(x)       DRCMR((x) + 24)
++#define DRCMR_MAPVLD      (1 << 7)        /* Map Valid (read / write) */
++#define DRCMR_CHLNUM      0x1f            /* mask for Channel Number (read / write) */
++#define DCSR0             __REG(0x40000000)  /* DMA Control / Status Register for Channel 0 */
++#define DCSR1             __REG(0x40000004)  /* DMA Control / Status Register for Channel 1 */
++#define DCSR2             __REG(0x40000008)  /* DMA Control / Status Register for Channel 2 */
++#define DCSR3             __REG(0x4000000c)  /* DMA Control / Status Register for Channel 3 */
++#define DCSR4             __REG(0x40000010)  /* DMA Control / Status Register for Channel 4 */
++#define DCSR5             __REG(0x40000014)  /* DMA Control / Status Register for Channel 5 */
++#define DCSR6             __REG(0x40000018)  /* DMA Control / Status Register for Channel 6 */
++#define DCSR7             __REG(0x4000001c)  /* DMA Control / Status Register for Channel 7 */
++#define DCSR8             __REG(0x40000020)  /* DMA Control / Status Register for Channel 8 */
++#define DCSR9             __REG(0x40000024)  /* DMA Control / Status Register for Channel 9 */
++#define DCSR10            __REG(0x40000028)  /* DMA Control / Status Register for Channel 10 */
++#define DCSR11            __REG(0x4000002c)  /* DMA Control / Status Register for Channel 11 */
++#define DCSR12            __REG(0x40000030)  /* DMA Control / Status Register for Channel 12 */
++#define DCSR13            __REG(0x40000034)  /* DMA Control / Status Register for Channel 13 */
++#define DCSR14            __REG(0x40000038)  /* DMA Control / Status Register for Channel 14 */
++#define DCSR15            __REG(0x4000003c)  /* DMA Control / Status Register for Channel 15 */
++#define DCSR16            __REG(0x40000040)  /* DMA Control / Status Register for Channel 16 */
++#define DCSR17            __REG(0x40000044)  /* DMA Control / Status Register for Channel 17 */
++#define DCSR18            __REG(0x40000048)  /* DMA Control / Status Register for Channel 18 */
++#define DCSR19            __REG(0x4000004c)  /* DMA Control / Status Register for Channel 19 */
++#define DCSR20            __REG(0x40000050)  /* DMA Control / Status Register for Channel 20 */
++#define DCSR21            __REG(0x40000054)  /* DMA Control / Status Register for Channel 21 */
++#define DCSR22            __REG(0x40000058)  /* DMA Control / Status Register for Channel 22 */
++#define DCSR23            __REG(0x4000005c)  /* DMA Control / Status Register for Channel 23 */
++#define DCSR24            __REG(0x40000060)  /* DMA Control / Status Register for Channel 24 */
++#define DCSR25            __REG(0x40000064)  /* DMA Control / Status Register for Channel 25 */
++#define DCSR26            __REG(0x40000068)  /* DMA Control / Status Register for Channel 26 */
++#define DCSR27            __REG(0x4000006c)  /* DMA Control / Status Register for Channel 27 */
++#define DCSR28            __REG(0x40000070)  /* DMA Control / Status Register for Channel 28 */
++#define DCSR29            __REG(0x40000074)  /* DMA Control / Status Register for Channel 29 */
++#define DCSR30            __REG(0x40000078)  /* DMA Control / Status Register for Channel 30 */
++#define DCSR31            __REG(0x4000007c)  /* DMA Control / Status Register for Channel 31 */
++#define DCSR(x)           __REG2(0x40000000, (x) << 2)
++#define DCSR_RUN  (1 << 31)       /* Run Bit (read / write) */
++#define DCSR_NODESC       (1 << 30)       /* No-Descriptor Fetch (read / write) */
++#define DCSR_STOPIRQEN    (1 << 29)       /* Stop Interrupt Enable (read / write) */
++#define DCSR_EORIRQEN     (1 << 28)       /* End of Receive Interrupt Enable (R/W) */
++#define DCSR_EORJMPEN     (1 << 27)       /* Jump to next descriptor on EOR */
++#define DCSR_EORSTOPEN    (1 << 26)       /* STOP on an EOR */
++#define DCSR_SETCMPST     (1 << 25)       /* Set Descriptor Compare Status */
++#define DCSR_CLRCMPST     (1 << 24)       /* Clear Descriptor Compare Status */
++#define DCSR_CMPST        (1 << 10)       /* The Descriptor Compare Status */
++#define DCSR_EORINTR      (1 << 9)        /* The end of Receive */
++#define DCSR_REQPEND      (1 << 8)        /* Request Pending (read-only) */
++#define DCSR_RASINTR      (1 << 4)        /* Request After Channel Stopped */
++#define DCSR_STOPSTATE    (1 << 3)        /* Stop State (read-only) */
++#define DCSR_ENDINTR      (1 << 2)        /* End Interrupt (read / write) */
++#define DCSR_STARTINTR    (1 << 1)        /* Start Interrupt (read / write) */
++#define DCSR_BUSERR       (1 << 0)        /* Bus Error Interrupt (read / write) */
++#define DDADR(x)  __REG2(0x40000200, (x) << 4)
++//#define __REG_2(x)        (*((volatile u32 *)io_p2v_2(x)))
++#define IRQ_NAND      PXA_IRQ(45)
++#define   CKEN_NAND       4       ///< NAND Flash Controller Clock Enable
++
++/* #define CONFIG_MTD_NAND_MONAHANS_DEBUG */
++#ifdef CONFIG_MTD_NAND_MONAHANS_DEBUG
++#define D1(x) do { \
++		printk(KERN_DEBUG "%s: ", __FUNCTION__); \
++		x; \
++	}while(0)
++
++#define	DPRINTK(fmt,args...) printk(KERN_DEBUG fmt, ##args )
++#define PRINT_BUF(buf, num)	print_buf(buf, num)
++#else
++#define D1(x)
++#define DPRINTK(fmt,args...)
++#define PRINT_BUF(buf, num)
++#endif
++
++/* DFC timing 0 register */
++#define DFC_TIMING_tRP		0
++#define DFC_TIMING_tRH		3
++#define DFC_TIMING_tWP		8
++#define DFC_TIMING_tWH		11
++#define DFC_TIMING_tCS		16
++#define DFC_TIMING_tCH		19
++
++/* DFC timing 1 register */
++#define DFC_TIMING_tAR		0
++#define DFC_TIMING_tWHR		4
++#define DFC_TIMING_tR		16
++
++/* max value for each timing setting in DFC */
++#define DFC_TIMING_MAX_tCH	7
++#define DFC_TIMING_MAX_tCS	7
++#define DFC_TIMING_MAX_tWH	7
++#define DFC_TIMING_MAX_tWP	7
++#define DFC_TIMING_MAX_tRH	7
++#define DFC_TIMING_MAX_tRP	7
++#define DFC_TIMING_MAX_tR	65535
++#define DFC_TIMING_MAX_tWHR	15
++#define DFC_TIMING_MAX_tAR	15
++
++/*
++ * The Data Flash Controller Flash timing structure
++ * For NAND flash used on Zylonite board(Samsung K9K1216Q0C),
++ * user should use value at end of each row of following member
++ * bracketed.
++ */
++struct dfc_flash_timing {
++	uint32_t   tCH;	/* Enable signal hold time */
++	uint32_t   tCS;	/* Enable signal setup time */
++	uint32_t   tWH;	/* ND_nWE high duration */
++	uint32_t   tWP;	/* ND_nWE pulse time */
++	uint32_t   tRH;	/* ND_nRE high duration */
++	uint32_t   tRP;	/* ND_nRE pulse width */
++	uint32_t   tR;	/* ND_nWE high to ND_nRE low for read */
++	uint32_t   tWHR;/* ND_nWE high to ND_nRE low delay for status read */
++	uint32_t   tAR;	/* ND_ALE low to ND_nRE low delay */
++};
++
++/* DFC command type */
++enum {
++	DFC_CMD_READ		= 0x00000000,
++	DFC_CMD_PROGRAM		= 0x00200000,
++	DFC_CMD_ERASE		= 0x00400000,
++	DFC_CMD_READ_ID		= 0x00600000,
++	DFC_CMD_STATUS_READ	= 0x00800000,
++	DFC_CMD_RESET		= 0x00a00000
++};
++
++/*
++ * The Data Flash Controller Flash specification structure
++ * For NAND flash used on Zylonite board(Samsung K9K1216Q0C),
++ * user should use value at end of each row of following member
++ * bracketed.
++ */
++struct dfc_flash_info {
++	struct dfc_flash_timing timing; /* NAND Flash timing */
++
++	int	 enable_arbiter;/* Data flash bus arbiter enable (ND_ARB_EN) */
++	uint32_t page_per_block;/* Pages per block (PG_PER_BLK) */
++	uint32_t row_addr_start;/* Row address start position (RA_START) */
++	uint32_t read_id_bytes;	/* returned ID bytes(RD_ID_CNT) */
++	uint32_t dfc_mode;	/* NAND, CARBONDALE, PIXLEY... (ND_MODE) */
++	uint32_t ncsx;		/* Chip select don't care bit (NCSX) */
++	uint32_t page_size;	/* Page size in bytes (PAGE_SZ) */
++	uint32_t oob_size;	/* OOB size */
++	uint32_t flash_width;	/* Width of Flash memory (DWIDTH_M) */
++	uint32_t dfc_width;	/* Width of flash controller(DWIDTH_C) */
++	uint32_t num_blocks;	/* Number of physical blocks in Flash */
++	uint32_t chip_id;
++
++	/* command codes */
++	uint32_t read1;		/* Read */
++	uint32_t read2;		/* unused, DFC don't support yet */
++	uint32_t program;	/* two cycle command */
++	uint32_t read_status;
++	uint32_t read_id;
++	uint32_t erase;		/* two cycle command */
++	uint32_t reset;
++	uint32_t lock;		/* lock whole flash */
++	uint32_t unlock;	/* two cycle command, supporting partial unlock */
++	uint32_t lock_status;	/* read block lock status */
++
++	/* addr2ndcb1 - encode address cycles into register NDCB1 */
++	/* ndbbr2addr - convert register NDBBR to bad block address */
++	int (*addr2ndcb1)(uint16_t cmd, uint32_t addr, uint32_t *p);
++	int (*ndbbr2addr)(uint16_t cmd, uint32_t ndbbr,uint32_t *p);
++};
++
++enum {
++	DFC_FLASH_NULL = 0 ,
++	DFC_FLASH_Samsung_512Mb_X_16 = 1,
++	DFC_FLASH_Micron_1Gb_X_8 = 2,
++	DFC_FLASH_Micron_1Gb_X_16 = 3,
++	DFC_FLASH_STM_1Gb_X_16 = 4,
++	DFC_FLASH_STM_2Gb_X_16 = 5,
++	DFC_FLASH_END,
++};
++
++static int dfc_get_flash_info(int type, struct dfc_flash_info **flash_info);
++
++#define		DFC_NDCR	0
++#define		DFC_NDTR0CS0	1
++#define		DFC_NDTR1CS0	3
++#define		DFC_NDSR	5
++#define		DFC_NDPCR	6
++#define		DFC_NDBDR0	7
++#define		DFC_NDBDR1	8
++#define		DFC_NDDB	16
++#define		DFC_NDCB0	18
++#define		DFC_NDCB1	19
++#define		DFC_NDCB2	20
++
++/* The Data Flash Controller Mode structure */
++struct dfc_mode {
++	int   enable_dma;	/* DMA, or nonDMA mode */
++	int   enable_ecc;	/* ECC on/off */
++	int   enable_spare;	/* Spare enable */
++	int   chip_select;	/* CS0 or CS1 */
++};
++
++/* The Data Flash Controller Context structure */
++struct dfc_context {
++	unsigned char __iomem	*membase;	/* DFC register base */
++	struct dfc_mode 	*dfc_mode;	/* DFC mode */
++	int 			data_dma_ch;	/* Data DMA channel number */
++	int 			cmd_dma_ch;	/* CMD  DMA channel number */
++	struct dfc_flash_info 	*flash_info; /* Flash Spec */
++	struct mtd_info 	*mtd;
++};
++
++#define NDCB0_DMA_ADDR	0x43100048
++#define NDDB_DMA_ADDR	0x43100040
++
++#define NDSR_MASK	0xFFF
++
++/* The following data is a rough evaluation */
++
++/* microsecond, for readID/readStatus/reset */
++#define NAND_OTHER_TIMEOUT 		10
++/* microsecond, for readID/readStatus/reset */
++#define NAND_CMD_TIMEOUT		10
++
++#define BBT_BLOCK_BAD	0x03
++#define BBT_BLOCK_GOOD	0x00
++#define BBT_BLOCK_REV1	0x01
++#define BBT_BLOCK_REV2	0x02
++
++#define BUFLEN		(2048 + 64)
++
++/*
++ * DFC data size enumeration transfered from/to controller,
++ * including padding (zero)to be a multiple of 32.
++ */
++enum {
++	DFC_DATA_SIZE_STATUS = 8,	/* ReadStatus/ReadBlockLockStatus */
++	DFC_DATA_SIZE_ID = 7,	/* ReadID */
++
++	DFC_DATA_SIZE_32 = 32,
++	DFC_DATA_SIZE_512 = 512,	/* R/W disabling spare area */
++	DFC_DATA_SIZE_520 = 520,	/* Spare=1, ECC=1 */
++	DFC_DATA_SIZE_528 = 528,	/* Spare=1, ECC=0 */
++	DFC_DATA_SIZE_544 = 544,	/* R/W enabling spare area.(DMA mode)*/
++
++	DFC_DATA_SIZE_64 = 64,
++	DFC_DATA_SIZE_2048 = 2048, 	/* R/W disabling spare area */
++	DFC_DATA_SIZE_2088 = 2088,	/* R/W enabling spare area with ecc */
++	DFC_DATA_SIZE_2112 = 2112,	/* R/W enabling spare area without ecc*/
++	DFC_DATA_SIZE_2096 = 2096,	/* R/W enabling spare area */
++	DFC_DATA_SIZE_UNUSED = 0xFFFF
++};
++
++/* DFC padding size enumeration transfered from/to controller */
++enum {
++	/*
++	 * ReadStatus/ReadBlockLockStatus/ReadID/
++	 * Read/Program disabling spare area(Both 512 and 2048)
++	 * Read/Program enabling spare area, disabling ECC
++	 */
++	DFC_PADDING_SIZE_0 = 0,
++
++	/* Read/program with SPARE_EN=1, ECC_EN=0, pgSize=512 */
++	DFC_PADDING_SIZE_16 = 16,
++	/* for read/program with SPARE_EN=1, ECC_EN=1, pgSize=512 and 2048 */
++	DFC_PADDING_SIZE_24 = 24,
++	DFC_PADDING_SIZE_UNUSED = 0xFFFF
++};
++
++static unsigned int flash_config = DFC_FLASH_NULL;
++
++void dfc_set_timing(struct dfc_context *context, struct dfc_flash_timing *t);
++void dfc_set_dma(struct dfc_context *context);
++void dfc_set_ecc(struct dfc_context *context);
++void dfc_set_spare(struct dfc_context *context);
++
++int dfc_get_pattern(struct dfc_context *context, uint16_t cmd,
++			int *data_size, int *padding);
++
++static int dfc_wait_event(struct dfc_context *context, uint32_t event,
++		uint32_t *event_out, uint32_t timeout, int enable_int);
++
++int dfc_send_cmd(struct dfc_context *context, uint16_t cmd,
++		uint32_t addr, int num_pages);
++
++void dfc_stop(struct dfc_context *context);
++void dfc_read_fifo_partial(struct dfc_context *context, uint8_t *buffer,
++			int nbytes, int data_size);
++void dfc_write_fifo_partial(struct dfc_context *context, uint8_t *buffer,
++			int nbytes, int data_size);
++
++void dfc_read_fifo(struct dfc_context *context, uint8_t *buffer, int nbytes);
++void dfc_write_fifo(struct dfc_context *context, uint8_t *buffer, int nbytes);
++
++void dfc_read_badblock_addr(struct dfc_context *context, uint32_t *bbaddr);
++
++void dfc_clear_int(struct dfc_context *context, uint32_t int_mask);
++void dfc_enable_int(struct dfc_context *context, uint32_t int_mask);
++void dfc_disable_int(struct dfc_context *context, uint32_t int_mask);
++
++/* high level primitives */
++int dfc_init(struct dfc_context *context, int type);
++int dfc_init_no_gpio(struct dfc_context *context, int type);
++
++int dfc_reset_flash(struct dfc_context *context);
++
++int dfc_setup_cmd_dma(struct dfc_context *context,
++		uint16_t cmd, uint32_t addr, int num_pages,
++		uint32_t *buf, uint32_t buf_phys,
++		uint32_t next_desc_phys, uint32_t dma_int_en,
++		struct pxa_dma_desc *dma_desc);
++
++int dfc_setup_data_dma(struct dfc_context *context,
++		uint16_t cmd, uint32_t buf_phys,
++		uint32_t next_desc_phys, uint32_t dma_int_en,
++		struct pxa_dma_desc *dma_desc);
++
++void dfc_start_cmd_dma(struct dfc_context *context,
++			struct pxa_dma_desc *dma_desc);
++void dfc_start_data_dma(struct dfc_context *context,
++			struct pxa_dma_desc *dma_desc);
++static int monahans_df_dev_ready(struct mtd_info *mtd);
++
++#ifdef CONFIG_DVFM
++static int mhn_nand_dvfm_notifier(unsigned cmd, void *client_data, void *info);
++static struct mhn_fv_notifier dvfm_notifier = {
++	.name 		= "monahans-nand-flash",
++	.priority 	= 0,
++	.notifier_call 	= mhn_nand_dvfm_notifier,
++};
++#endif
++
++static unsigned short search_rel_block(int block, struct mtd_info *mtd);
++
++/*****************************************************************************
++ * The DFC registers read/write routines
++ *****************************************************************************/
++static inline void dfc_write(struct dfc_context *context, int offset,
++		unsigned long value)
++{
++	offset <<= 2;
++	writel(value, context->membase + offset);
++}
++
++static inline unsigned int dfc_read(struct dfc_context *context, int offset)
++{
++	offset <<= 2;
++	return __raw_readl(context->membase + offset);
++}
++
++/****************************************************************************
++ * Flash Information
++ ***************************************************************************/
++
++static int Samsung512MbX16Addr2NDCB1(uint16_t cmd, uint32_t addr, uint32_t *p);
++static int Samsung512MbX16NDBBR2Addr(uint16_t cmd, uint32_t ndbbr, uint32_t *p);
++
++static struct dfc_flash_info samsung512MbX16 =
++{
++	.timing = {
++		.tCH = 10,	/* tCH, Enable signal hold time */
++		.tCS = 0,	/* tCS, Enable signal setup time */
++		.tWH = 20,	/* tWH, ND_nWE high duration */
++		.tWP = 40,	/* tWP, ND_nWE pulse time */
++		.tRH = 30,	/* tRH, ND_nRE high duration */
++		.tRP = 40,	/* tRP, ND_nRE pulse width */
++		/* tR = tR+tRR+tWB+1, ND_nWE high to ND_nRE low for read */
++		.tR = 11123,
++		/* tWHR, ND_nWE high to ND_nRE low delay for status read */
++		.tWHR = 110,
++		.tAR = 10,	/* tAR, ND_ALE low to ND_nRE low delay */
++	},
++	.enable_arbiter = 1,	/* Data flash bus arbiter enable */
++	.page_per_block = 32,	/* Pages per block */
++	.row_addr_start = 0,	/* Second cycle start, Row address start position */
++	.read_id_bytes = 2,	/* 2 bytes, returned ID bytes */
++	.dfc_mode = 0,		/* NAND mode */
++	.ncsx = 0,
++	.page_size = 512,	/* Page size in bytes */
++	.oob_size = 16,		/* OOB size in bytes */
++	.flash_width = 16,	/* Width of Flash memory */
++	.dfc_width = 16,	/* Width of flash controller */
++	.num_blocks = 4096,	/* Number of physical blocks in Flash */
++	.chip_id =  0x46ec,
++
++	/* command codes */
++	.read1 = 0x0000,	/* Read */
++	.read2 = 0x0050,	/* Read1 unused, current DFC don't support */
++	.program = 0x1080,	/* Write, two cycle command */
++	.read_status = 0x0070,	/* Read status */
++	.read_id = 0x0090,	/* Read ID */
++	.erase =  0xD060,	/* Erase, two cycle command */
++	.reset = 0x00FF,	/* Reset */
++	.lock = 0x002A,		/* Lock whole flash */
++	.unlock = 0x2423,	/* Unlock, two cycle command, supporting partial unlock */
++	.lock_status = 0x007A,	/* Read block lock status */
++	.addr2ndcb1 = Samsung512MbX16Addr2NDCB1,
++	.ndbbr2addr = Samsung512MbX16NDBBR2Addr,
++};
++
++static int Samsung512MbX16Addr2NDCB1(uint16_t cmd, uint32_t addr, uint32_t *p)
++{
++	uint32_t ndcb1 = 0;
++
++	if (addr >= 0x4000000) return -EINVAL;
++
++	if (cmd == samsung512MbX16.read1 || cmd == samsung512MbX16.program) {
++		ndcb1 = (addr & 0xFF) | ((addr >> 1) & 0x01FFFF00);
++	} else if (cmd == samsung512MbX16.erase) {
++		ndcb1 = ((addr >> 9) & 0x00FFFFFF);
++	}
++
++	*p = ndcb1;
++	return 0;
++
++}
++
++static int Samsung512MbX16NDBBR2Addr(uint16_t cmd, uint32_t ndbbr, uint32_t *p)
++{
++	*p = ndbbr << 9;
++	return 0;
++}
++
++static int Micron1GbX8Addr2NDCB1(uint16_t cmd, uint32_t addr, uint32_t *p);
++static int Micron1GbX8NDBBR2Addr(uint16_t cmd, uint32_t ndbbr, uint32_t *p);
++
++static struct dfc_flash_info micron1GbX8 =
++{
++	.timing = {
++		.tCH = 10,	/* tCH, Enable signal hold time */
++		.tCS = 25,	/* tCS, Enable signal setup time */
++		.tWH = 15,	/* tWH, ND_nWE high duration */
++		.tWP = 25,	/* tWP, ND_nWE pulse time */
++		.tRH = 15,	/* tRH, ND_nRE high duration */
++		.tRP = 25,	/* tRP, ND_nRE pulse width */
++		/* tR = tR+tRR+tWB+1, ND_nWE high to ND_nRE low for read */
++		.tR = 25000,
++		/* tWHR, ND_nWE high to ND_nRE low delay for status read */
++		.tWHR = 60,
++		.tAR = 10,	/* tAR, ND_ALE low to ND_nRE low delay */
++	},
++	.enable_arbiter = 1,	/* Data flash bus arbiter enable */
++	.page_per_block = 64,	/* Pages per block */
++	.row_addr_start = 1,	/* Second cycle start, Row address start position */
++	.read_id_bytes = 4,	/* Returned ID bytes */
++	.dfc_mode = 0,		/* NAND mode */
++	.ncsx = 0,
++	.page_size = 2048,	/* Page size in bytes */
++	.oob_size = 64,		/* OOB size in bytes */
++	.flash_width = 8,	/* Width of Flash memory */
++	.dfc_width = 8,		/* Width of flash controller */
++	.num_blocks = 1024,	/* Number of physical blocks in Flash */
++	.chip_id =  0xa12c,
++	/* command codes */
++	.read1 = 0x3000,	/* Read */
++	.read2 = 0x0050,	/* Read1 unused, current DFC don't support */
++	.program = 0x1080,	/* Write, two cycle command */
++	.read_status = 0x0070,	/* Read status */
++	.read_id = 0x0090,	/* Read ID */
++	.erase =  0xD060,	/* Erase, two cycle command */
++	.reset = 0x00FF,	/* Reset */
++	.lock = 0x002A,		/* Lock whole flash */
++	.unlock = 0x2423,	/* Unlock, two cycle command, supporting partial unlock */
++	.lock_status = 0x007A,	/* Read block lock status */
++	.addr2ndcb1 = Micron1GbX8Addr2NDCB1,
++	.ndbbr2addr = Micron1GbX8NDBBR2Addr,
++};
++
++static int Micron1GbX8Addr2NDCB1(uint16_t cmd, uint32_t addr, uint32_t *p)
++{
++	uint32_t ndcb1 = 0;
++	uint32_t page;
++
++	if (addr >= 0x8000000)
++		return -EINVAL;
++	page = addr / micron1GbX8.page_size;
++	addr =  (page / micron1GbX8.page_per_block) << 18 |
++		(page % micron1GbX8.page_per_block) << 12;
++
++	if (cmd == micron1GbX8.read1 || cmd == micron1GbX8.program) {
++		ndcb1 = (addr & 0xFFF) | ((addr << 4) & 0xFFFF0000);
++	}
++	else if (cmd == micron1GbX8.erase) {
++		ndcb1 = ((addr >> 18) << 6) & 0xFFFF;
++	}
++
++	*p = ndcb1;
++	return 0;
++}
++
++static int Micron1GbX8NDBBR2Addr(uint16_t cmd, uint32_t ndbbr, uint32_t *p)
++{
++	if (cmd == micron1GbX8.read1 || cmd == micron1GbX8.program) {
++		*p = ((ndbbr & 0xF) << 8) | ((ndbbr >> 8) << 16);
++	}
++	else if (cmd == micron1GbX8.erase) {
++		*p = (ndbbr >> 6) << 18;
++	}
++
++
++	return 0;
++}
++
++
++static int Micron1GbX16Addr2NDCB1(uint16_t cmd, uint32_t addr, uint32_t *p);
++static int Micron1GbX16NDBBR2Addr(uint16_t cmd, uint32_t ndbbr, uint32_t *p);
++
++static struct dfc_flash_info micron1GbX16 =
++{
++	.timing = {
++		.tCH = 10,	/* tCH, Enable signal hold time */
++		.tCS = 25,	/* tCS, Enable signal setup time */
++		.tWH = 15,	/* tWH, ND_nWE high duration */
++		.tWP = 25,	/* tWP, ND_nWE pulse time */
++		.tRH = 15,	/* tRH, ND_nRE high duration */
++		.tRP = 25,	/* tRP, ND_nRE pulse width */
++		/* tR = tR+tRR+tWB+1, ND_nWE high to ND_nRE low for read */
++		.tR = 25000,
++		/* tWHR, ND_nWE high to ND_nRE low delay for status read */
++		.tWHR = 60,
++		.tAR = 10,	/* tAR, ND_ALE low to ND_nRE low delay */
++	},
++	.enable_arbiter = 1,	/* Data flash bus arbiter enable */
++	.page_per_block = 64,	/* Pages per block */
++	.row_addr_start = 1,	/* Second cycle start, Row address start position */
++	.read_id_bytes = 4,	/* Returned ID bytes */
++	.dfc_mode = 0,		/* NAND mode */
++	.ncsx = 0,
++	.page_size = 2048,	/* Page size in bytes */
++	.oob_size = 64,		/* OOB size in bytes */
++	.flash_width = 16,	/* Width of Flash memory */
++	.dfc_width = 16,	/* Width of flash controller */
++	.num_blocks = 1024,	/* Number of physical blocks in Flash */
++	.chip_id =  0xb12c,
++
++	/* command codes */
++	.read1 = 0x3000,	/* Read */
++	.read2 = 0x0050,	/* Read1 unused, current DFC don't support */
++	.program = 0x1080,	/* Write, two cycle command */
++	.read_status = 0x0070,	/* Read status */
++	.read_id = 0x0090,	/* Read ID */
++	.erase =  0xD060,	/* Erase, two cycle command */
++	.reset = 0x00FF,	/* Reset */
++	.lock = 0x002A,		/* Lock whole flash */
++	.unlock = 0x2423,	/* Unlock, two cycle command, supporting partial unlock */
++	.lock_status = 0x007A,	/* Read block lock status */
++	.addr2ndcb1 = Micron1GbX16Addr2NDCB1,
++	.ndbbr2addr = Micron1GbX16NDBBR2Addr,
++};
++
++static int Micron1GbX16Addr2NDCB1(uint16_t cmd, uint32_t addr, uint32_t *p)
++{
++	uint32_t ndcb1 = 0;
++	uint32_t page;
++
++	if (addr >= 0x8000000)
++		return -EINVAL;
++	page = addr / micron1GbX16.page_size;
++	addr =  (page / micron1GbX16.page_per_block) << 17 |
++		(page % micron1GbX16.page_per_block) << 11;
++
++	if (cmd == micron1GbX16.read1 || cmd == micron1GbX16.program) {
++		ndcb1 = (addr & 0x7FF) | ((addr << 5) & 0xFFFF0000);
++	}
++	else if (cmd == micron1GbX16.erase) {
++		ndcb1 = ((addr >> 17) << 6) & 0xFFFF;
++	}
++	*p = ndcb1;
++	return 0;
++}
++
++static int Micron1GbX16NDBBR2Addr(uint16_t cmd, uint32_t ndbbr, uint32_t *p)
++{
++	if (cmd == micron1GbX16.read1 || cmd == micron1GbX16.program) {
++		*p = ((ndbbr & 0x7) << 8) | ((ndbbr >> 8) << 16);
++	}
++	else if (cmd == micron1GbX16.erase) {
++		*p = (ndbbr >> 6) << 17;
++	}
++
++	return 0;
++}
++
++static int STM1GbX16Addr2NDCB1(uint16_t cmd, uint32_t addr, uint32_t *p);
++static int STM1GbX16NDBBR2Addr(uint16_t cmd, uint32_t ndbbr, uint32_t *p);
++
++static struct dfc_flash_info stm1GbX16 =
++{
++	.timing = {
++		.tCH = 10,	/* tCH, Enable signal hold time */
++		.tCS = 10,	/* tCS, Enable signal setup time */
++		.tWH = 20,	/* tWH, ND_nWE high duration */
++		.tWP = 25,	/* tWP, ND_nWE pulse time */
++		.tRH = 20,	/* tRH, ND_nRE high duration */
++		.tRP = 25,	/* tRP, ND_nRE pulse width */
++		/* tR = tR+tRR+tWB+1, ND_nWE high to ND_nRE low for read */
++		.tR = 25000,
++		/* tWHR, ND_nWE high to ND_nRE low delay for status read */
++		.tWHR = 60,
++		.tAR = 10,	/* tAR, ND_ALE low to ND_nRE low delay */
++	},
++	.enable_arbiter = 1,	/* Data flash bus arbiter enable */
++	.page_per_block = 64,	/* Pages per block */
++	.row_addr_start = 1,	/* Second cycle start, Row address start position */
++	.read_id_bytes = 4,	/* Returned ID bytes */
++	.dfc_mode = 0,		/* NAND mode */
++	.ncsx = 0,
++	.page_size = 2048,	/* Page size in bytes */
++	.oob_size = 64,		/* OOB size in bytes */
++	.flash_width = 16,	/* Width of Flash memory */
++	.dfc_width = 16,	/* Width of flash controller */
++	.num_blocks = 1024,	/* Number of physical blocks in Flash */
++	.chip_id =  0xb120,
++
++	/* command codes */
++	.read1 = 0x3000,	/* Read */
++	.read2 = 0x0050,	/* Read1 unused, current DFC don't support */