Drop linux-moblin obsolete kernels

58 files changed, 0 insertions, 47395 deletions

diff --git a/meta-moblin/packages/linux/linux-moblin-2.6.27-rc1/0001_Export_shmem_file_setup_for_DRM-GEM.patch b/meta-moblin/packages/linux/linux-moblin-2.6.27-rc1/0001_Export_shmem_file_setup_for_DRM-GEM.patch
deleted file mode 100644
index 9589838afa..0000000000
--- a/meta-moblin/packages/linux/linux-moblin-2.6.27-rc1/0001_Export_shmem_file_setup_for_DRM-GEM.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From: Keith Packard <keithp@keithp.com>
-Date: Fri, 20 Jun 2008 07:08:06 +0000 (-0700)
-Subject: Export shmem_file_setup for DRM-GEM
-X-Git-Tag: v2.6.12-rc2
-X-Git-Url: http://gitweb.freedesktop.org/?p=users/anholt/anholt/linux-2.6.git;a=commitdiff;h=350ea3ece12744ae154bbc2ea13da6ba84ca5515
-
-Export shmem_file_setup for DRM-GEM
-
-GEM needs to create shmem files to back buffer objects.  Though currently
-creation of files for objects could have been driven from userland, the
-modesetting work will require allocation of buffer objects before userland
-is running, for boot-time message display.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
-
---- a/mm/shmem.c
-+++ b/mm/shmem.c
-@@ -2582,6 +2582,7 @@ put_memory:
- 	shmem_unacct_size(flags, size);
- 	return ERR_PTR(error);
- }
-+EXPORT_SYMBOL(shmem_file_setup);
- 
- /**
-  * shmem_zero_setup - setup a shared anonymous mapping
-
diff --git a/meta-moblin/packages/linux/linux-moblin-2.6.27-rc1/0002_i915.Use_more_consistent_names_for_regs.patch b/meta-moblin/packages/linux/linux-moblin-2.6.27-rc1/0002_i915.Use_more_consistent_names_for_regs.patch
deleted file mode 100644
index 9a035b544c..0000000000
--- a/meta-moblin/packages/linux/linux-moblin-2.6.27-rc1/0002_i915.Use_more_consistent_names_for_regs.patch
+++ /dev/null
@@ -1,2739 +0,0 @@
-From: Jesse Barnes <jbarnes@virtuousgeek.org>
-Date: Tue, 29 Jul 2008 18:54:06 +0000 (-0700)
-Subject: i915: Use more consistent names for regs, and store them in a separate file.
-X-Git-Tag: v2.6.12-rc2
-X-Git-Url: http://gitweb.freedesktop.org/?p=users/anholt/anholt/linux-2.6.git;a=commitdiff;h=db1cbbd8c4d42e58e9acb3e7af59ad1bb238260d
-
-i915: Use more consistent names for regs, and store them in a separate file.
-
-Signed-off-by: Eric Anholt <eric@anholt.net>
----
-
---- a/drivers/gpu/drm/i915/i915_dma.c
-+++ b/drivers/gpu/drm/i915/i915_dma.c
-@@ -40,11 +40,11 @@ int i915_wait_ring(struct drm_device * d
- {
- 	drm_i915_private_t *dev_priv = dev->dev_private;
- 	drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
--	u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
-+	u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
- 	int i;
- 
- 	for (i = 0; i < 10000; i++) {
--		ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
-+		ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
- 		ring->space = ring->head - (ring->tail + 8);
- 		if (ring->space < 0)
- 			ring->space += ring->Size;
-@@ -67,8 +67,8 @@ void i915_kernel_lost_context(struct drm
- 	drm_i915_private_t *dev_priv = dev->dev_private;
- 	drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
- 
--	ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
--	ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
-+	ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
-+	ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
- 	ring->space = ring->head - (ring->tail + 8);
- 	if (ring->space < 0)
- 		ring->space += ring->Size;
-@@ -98,13 +98,13 @@ static int i915_dma_cleanup(struct drm_d
- 		drm_pci_free(dev, dev_priv->status_page_dmah);
- 		dev_priv->status_page_dmah = NULL;
- 		/* Need to rewrite hardware status page */
--		I915_WRITE(0x02080, 0x1ffff000);
-+		I915_WRITE(HWS_PGA, 0x1ffff000);
- 	}
- 
- 	if (dev_priv->status_gfx_addr) {
- 		dev_priv->status_gfx_addr = 0;
- 		drm_core_ioremapfree(&dev_priv->hws_map, dev);
--		I915_WRITE(0x2080, 0x1ffff000);
-+		I915_WRITE(HWS_PGA, 0x1ffff000);
- 	}
- 
- 	return 0;
-@@ -170,7 +170,7 @@ static int i915_initialize(struct drm_de
- 		dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
- 
- 		memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
--		I915_WRITE(0x02080, dev_priv->dma_status_page);
-+		I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
- 	}
- 	DRM_DEBUG("Enabled hardware status page\n");
- 	return 0;
-@@ -201,9 +201,9 @@ static int i915_dma_resume(struct drm_de
- 	DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
- 
- 	if (dev_priv->status_gfx_addr != 0)
--		I915_WRITE(0x02080, dev_priv->status_gfx_addr);
-+		I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
- 	else
--		I915_WRITE(0x02080, dev_priv->dma_status_page);
-+		I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
- 	DRM_DEBUG("Enabled hardware status page\n");
- 
- 	return 0;
-@@ -402,8 +402,8 @@ static void i915_emit_breadcrumb(struct 
- 		dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
- 
- 	BEGIN_LP_RING(4);
--	OUT_RING(CMD_STORE_DWORD_IDX);
--	OUT_RING(20);
-+	OUT_RING(MI_STORE_DWORD_INDEX);
-+	OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
- 	OUT_RING(dev_priv->counter);
- 	OUT_RING(0);
- 	ADVANCE_LP_RING();
-@@ -505,7 +505,7 @@ static int i915_dispatch_flip(struct drm
- 	i915_kernel_lost_context(dev);
- 
- 	BEGIN_LP_RING(2);
--	OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
-+	OUT_RING(MI_FLUSH | MI_READ_FLUSH);
- 	OUT_RING(0);
- 	ADVANCE_LP_RING();
- 
-@@ -530,8 +530,8 @@ static int i915_dispatch_flip(struct drm
- 	dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
- 
- 	BEGIN_LP_RING(4);
--	OUT_RING(CMD_STORE_DWORD_IDX);
--	OUT_RING(20);
-+	OUT_RING(MI_STORE_DWORD_INDEX);
-+	OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
- 	OUT_RING(dev_priv->counter);
- 	OUT_RING(0);
- 	ADVANCE_LP_RING();
-@@ -728,8 +728,8 @@ static int i915_set_status_page(struct d
- 	dev_priv->hw_status_page = dev_priv->hws_map.handle;
- 
- 	memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
--	I915_WRITE(0x02080, dev_priv->status_gfx_addr);
--	DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
-+	I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
-+	DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
- 			dev_priv->status_gfx_addr);
- 	DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
- 	return 0;
---- a/drivers/gpu/drm/i915/i915_drv.c
-+++ b/drivers/gpu/drm/i915/i915_drv.c
-@@ -279,13 +279,13 @@ static int i915_suspend(struct drm_devic
- 	dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
- 	dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
- 	dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
--	dev_priv->saveDSPABASE = I915_READ(DSPABASE);
-+	dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
- 	if (IS_I965G(dev)) {
- 		dev_priv->saveDSPASURF = I915_READ(DSPASURF);
- 		dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
- 	}
- 	i915_save_palette(dev, PIPE_A);
--	dev_priv->savePIPEASTAT = I915_READ(I915REG_PIPEASTAT);
-+	dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
- 
- 	/* Pipe & plane B info */
- 	dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
-@@ -307,13 +307,13 @@ static int i915_suspend(struct drm_devic
- 	dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
- 	dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
- 	dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
--	dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
-+	dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
- 	if (IS_I965GM(dev) || IS_IGD_GM(dev)) {
- 		dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
- 		dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
- 	}
- 	i915_save_palette(dev, PIPE_B);
--	dev_priv->savePIPEBSTAT = I915_READ(I915REG_PIPEBSTAT);
-+	dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
- 
- 	/* CRT state */
- 	dev_priv->saveADPA = I915_READ(ADPA);
-@@ -328,9 +328,9 @@ static int i915_suspend(struct drm_devic
- 		dev_priv->saveLVDS = I915_READ(LVDS);
- 	if (!IS_I830(dev) && !IS_845G(dev))
- 		dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
--	dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON);
--	dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF);
--	dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);
-+	dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
-+	dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
-+	dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
- 
- 	/* FIXME: save TV & SDVO state */
- 
-@@ -341,19 +341,19 @@ static int i915_suspend(struct drm_devic
- 	dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
- 
- 	/* Interrupt state */
--	dev_priv->saveIIR = I915_READ(I915REG_INT_IDENTITY_R);
--	dev_priv->saveIER = I915_READ(I915REG_INT_ENABLE_R);
--	dev_priv->saveIMR = I915_READ(I915REG_INT_MASK_R);
-+	dev_priv->saveIIR = I915_READ(IIR);
-+	dev_priv->saveIER = I915_READ(IER);
-+	dev_priv->saveIMR = I915_READ(IMR);
- 
- 	/* VGA state */
--	dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
--	dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
--	dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
-+	dev_priv->saveVGA0 = I915_READ(VGA0);
-+	dev_priv->saveVGA1 = I915_READ(VGA1);
-+	dev_priv->saveVGA_PD = I915_READ(VGA_PD);
- 	dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
- 
- 	/* Clock gating state */
- 	dev_priv->saveD_STATE = I915_READ(D_STATE);
--	dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
-+	dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS);
- 
- 	/* Cache mode state */
- 	dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
-@@ -363,7 +363,7 @@ static int i915_suspend(struct drm_devic
- 
- 	/* Scratch space */
- 	for (i = 0; i < 16; i++) {
--		dev_priv->saveSWF0[i] = I915_READ(SWF0 + (i << 2));
-+		dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
- 		dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
- 	}
- 	for (i = 0; i < 3; i++)
-@@ -424,7 +424,7 @@ static int i915_resume(struct drm_device
- 	I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
- 	I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
- 	I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
--	I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
-+	I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
- 	I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
- 	if (IS_I965G(dev)) {
- 		I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
-@@ -436,7 +436,7 @@ static int i915_resume(struct drm_device
- 	i915_restore_palette(dev, PIPE_A);
- 	/* Enable the plane */
- 	I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
--	I915_WRITE(DSPABASE, I915_READ(DSPABASE));
-+	I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
- 
- 	/* Pipe & plane B info */
- 	if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
-@@ -466,7 +466,7 @@ static int i915_resume(struct drm_device
- 	I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
- 	I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
- 	I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
--	I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
-+	I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
- 	I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
- 	if (IS_I965G(dev)) {
- 		I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
-@@ -478,7 +478,7 @@ static int i915_resume(struct drm_device
- 	i915_restore_palette(dev, PIPE_B);
- 	/* Enable the plane */
- 	I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
--	I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
-+	I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
- 
- 	/* CRT state */
- 	I915_WRITE(ADPA, dev_priv->saveADPA);
-@@ -493,9 +493,9 @@ static int i915_resume(struct drm_device
- 
- 	I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
- 	I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
--	I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON);
--	I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF);
--	I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
-+	I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
-+	I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
-+	I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
- 	I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
- 
- 	/* FIXME: restore TV & SDVO state */
-@@ -508,14 +508,14 @@ static int i915_resume(struct drm_device
- 
- 	/* VGA state */
- 	I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
--	I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
--	I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
--	I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
-+	I915_WRITE(VGA0, dev_priv->saveVGA0);
-+	I915_WRITE(VGA1, dev_priv->saveVGA1);
-+	I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
- 	udelay(150);
- 
- 	/* Clock gating state */
- 	I915_WRITE (D_STATE, dev_priv->saveD_STATE);
--	I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
-+	I915_WRITE(CG_2D_DIS, dev_priv->saveCG_2D_DIS);
- 
- 	/* Cache mode state */
- 	I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
-@@ -524,7 +524,7 @@ static int i915_resume(struct drm_device
- 	I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
- 
- 	for (i = 0; i < 16; i++) {
--		I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF0[i]);
-+		I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
- 		I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
- 	}
- 	for (i = 0; i < 3; i++)
---- a/drivers/gpu/drm/i915/i915_drv.h
-+++ b/drivers/gpu/drm/i915/i915_drv.h
-@@ -30,6 +30,8 @@
- #ifndef _I915_DRV_H_
- #define _I915_DRV_H_
- 
-+#include "i915_reg.h"
-+
- /* General customization:
-  */
- 
-@@ -138,7 +140,7 @@ typedef struct drm_i915_private {
- 	u32 saveDSPASTRIDE;
- 	u32 saveDSPASIZE;
- 	u32 saveDSPAPOS;
--	u32 saveDSPABASE;
-+	u32 saveDSPAADDR;
- 	u32 saveDSPASURF;
- 	u32 saveDSPATILEOFF;
- 	u32 savePFIT_PGM_RATIOS;
-@@ -159,24 +161,24 @@ typedef struct drm_i915_private {
- 	u32 saveDSPBSTRIDE;
- 	u32 saveDSPBSIZE;
- 	u32 saveDSPBPOS;
--	u32 saveDSPBBASE;
-+	u32 saveDSPBADDR;
- 	u32 saveDSPBSURF;
- 	u32 saveDSPBTILEOFF;
--	u32 saveVCLK_DIVISOR_VGA0;
--	u32 saveVCLK_DIVISOR_VGA1;
--	u32 saveVCLK_POST_DIV;
-+	u32 saveVGA0;
-+	u32 saveVGA1;
-+	u32 saveVGA_PD;
- 	u32 saveVGACNTRL;
- 	u32 saveADPA;
- 	u32 saveLVDS;
--	u32 saveLVDSPP_ON;
--	u32 saveLVDSPP_OFF;
-+	u32 savePP_ON_DELAYS;
-+	u32 savePP_OFF_DELAYS;
- 	u32 saveDVOA;
- 	u32 saveDVOB;
- 	u32 saveDVOC;
- 	u32 savePP_ON;
- 	u32 savePP_OFF;
- 	u32 savePP_CONTROL;
--	u32 savePP_CYCLE;
-+	u32 savePP_DIVISOR;
- 	u32 savePFIT_CONTROL;
- 	u32 save_palette_a[256];
- 	u32 save_palette_b[256];
-@@ -189,7 +191,7 @@ typedef struct drm_i915_private {
- 	u32 saveIMR;
- 	u32 saveCACHE_MODE_0;
- 	u32 saveD_STATE;
--	u32 saveDSPCLK_GATE_D;
-+	u32 saveCG_2D_DIS;
- 	u32 saveMI_ARB_STATE;
- 	u32 saveSWF0[16];
- 	u32 saveSWF1[16];
-@@ -283,816 +285,26 @@ extern void i915_mem_release(struct drm_
- 	if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);	\
- 	dev_priv->ring.tail = outring;					\
- 	dev_priv->ring.space -= outcount * 4;				\
--	I915_WRITE(LP_RING + RING_TAIL, outring);			\
-+	I915_WRITE(PRB0_TAIL, outring);			\
- } while(0)
- 
--extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
--
--/* Extended config space */
--#define LBB 0xf4
--
--/* VGA stuff */
--
--#define VGA_ST01_MDA 0x3ba
--#define VGA_ST01_CGA 0x3da
--
--#define VGA_MSR_WRITE 0x3c2
--#define VGA_MSR_READ 0x3cc
--#define   VGA_MSR_MEM_EN (1<<1)
--#define   VGA_MSR_CGA_MODE (1<<0)
--
--#define VGA_SR_INDEX 0x3c4
--#define VGA_SR_DATA 0x3c5
--
--#define VGA_AR_INDEX 0x3c0
--#define   VGA_AR_VID_EN (1<<5)
--#define VGA_AR_DATA_WRITE 0x3c0
--#define VGA_AR_DATA_READ 0x3c1
--
--#define VGA_GR_INDEX 0x3ce
--#define VGA_GR_DATA 0x3cf
--/* GR05 */
--#define   VGA_GR_MEM_READ_MODE_SHIFT 3
--#define     VGA_GR_MEM_READ_MODE_PLANE 1