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From bf679a27766de623815d820431e1049326f7cac1 Mon Sep 17 00:00:00 2001
From: Ranjith Lohithakshan <ranjithl@ti.com>
Date: Fri, 9 Jul 2010 15:55:41 +0530
Subject: [PATCH 3/9] OMAP3: PM: Introduce Smartreflex support on OMAP3630/DM3730
OMAP3630 has a newer version of Smartreflex IP called Smartreflex2. There are
new register additions and bit definition differences in this version of the IP.
This patch introduces the Class3 driver support for Smartreflex2 on OMAP3630.
Smartreflex2 has the following registers added
IRQ_EOI, IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR
And following register offsets are different from Smartreflex1
SENERROR, ERRCONFIG
Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
---
arch/arm/mach-omap2/smartreflex.c | 190 +++++++++++++++++++----------
arch/arm/mach-omap2/smartreflex.h | 16 +++
arch/arm/plat-omap/include/plat/control.h | 13 ++
3 files changed, 157 insertions(+), 62 deletions(-)
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index fd34af2..fdd9540 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -99,18 +99,26 @@ static int sr_clk_enable(struct omap_sr *sr)
return -1;
}
- /* set fclk- active , iclk- idle */
- sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
- SR_CLKACTIVITY_IOFF_FON);
+ if (cpu_is_omap3630())
+ sr_modify_reg(sr, ERRCONFIG_36XX, SR_IDLEMODE_MASK,
+ SR_SMART_IDLE);
+ else
+ /* set fclk- active , iclk- idle */
+ sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
+ SR_CLKACTIVITY_IOFF_FON);
return 0;
}
static void sr_clk_disable(struct omap_sr *sr)
{
- /* set fclk, iclk- idle */
- sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
- SR_CLKACTIVITY_IOFF_FOFF);
+ if (cpu_is_omap3630())
+ sr_modify_reg(sr, ERRCONFIG_36XX, SR_IDLEMODE_MASK,
+ SR_FORCE_IDLE);
+ else
+ /* set fclk, iclk- idle */
+ sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
+ SR_CLKACTIVITY_IOFF_FOFF);
clk_disable(sr->clk);
sr->is_sr_reset = 1;
@@ -285,39 +293,55 @@ static u32 swcalc_opp6_nvalue(void)
static void sr_set_efuse_nvalues(struct omap_sr *sr)
{
if (sr->srid == SR1) {
- sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
- OMAP343X_SR1_SENNENABLE_MASK) >>
- OMAP343X_SR1_SENNENABLE_SHIFT;
- sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
- OMAP343X_SR1_SENPENABLE_MASK) >>
- OMAP343X_SR1_SENPENABLE_SHIFT;
-
- sr->opp6_nvalue = swcalc_opp6_nvalue();
- sr->opp5_nvalue = omap_ctrl_readl(
- OMAP343X_CONTROL_FUSE_OPP5_VDD1);
- sr->opp4_nvalue = omap_ctrl_readl(
- OMAP343X_CONTROL_FUSE_OPP4_VDD1);
- sr->opp3_nvalue = omap_ctrl_readl(
- OMAP343X_CONTROL_FUSE_OPP3_VDD1);
- sr->opp2_nvalue = omap_ctrl_readl(
- OMAP343X_CONTROL_FUSE_OPP2_VDD1);
- sr->opp1_nvalue = omap_ctrl_readl(
- OMAP343X_CONTROL_FUSE_OPP1_VDD1);
+ if (cpu_is_omap3630()) {
+ sr->senn_mod = sr->senp_mod = 0x1;
+
+ sr->opp4_nvalue = omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP4_VDD1);
+ sr->opp3_nvalue = omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP3_VDD1);
+ sr->opp2_nvalue = omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP2_VDD1);
+ sr->opp1_nvalue = omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP1_VDD1);
+ } else {
+ sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
+ OMAP343X_SR1_SENNENABLE_MASK) >>
+ OMAP343X_SR1_SENNENABLE_SHIFT;
+ sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
+ OMAP343X_SR1_SENPENABLE_MASK) >>
+ OMAP343X_SR1_SENPENABLE_SHIFT;
+
+ sr->opp6_nvalue = swcalc_opp6_nvalue();
+ sr->opp5_nvalue = omap_ctrl_readl(
+ OMAP343X_CONTROL_FUSE_OPP5_VDD1);
+ sr->opp4_nvalue = omap_ctrl_readl(
+ OMAP343X_CONTROL_FUSE_OPP4_VDD1);
+ sr->opp3_nvalue = omap_ctrl_readl(
+ OMAP343X_CONTROL_FUSE_OPP3_VDD1);
+ sr->opp2_nvalue = omap_ctrl_readl(
+ OMAP343X_CONTROL_FUSE_OPP2_VDD1);
+ sr->opp1_nvalue = omap_ctrl_readl(
+ OMAP343X_CONTROL_FUSE_OPP1_VDD1);
+ }
} else if (sr->srid == SR2) {
- sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
- OMAP343X_SR2_SENNENABLE_MASK) >>
- OMAP343X_SR2_SENNENABLE_SHIFT;
-
- sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
- OMAP343X_SR2_SENPENABLE_MASK) >>
- OMAP343X_SR2_SENPENABLE_SHIFT;
-
- sr->opp3_nvalue = omap_ctrl_readl(
- OMAP343X_CONTROL_FUSE_OPP3_VDD2);
- sr->opp2_nvalue = omap_ctrl_readl(
- OMAP343X_CONTROL_FUSE_OPP2_VDD2);
- sr->opp1_nvalue = omap_ctrl_readl(
- OMAP343X_CONTROL_FUSE_OPP1_VDD2);
+ if (cpu_is_omap3630()) {
+ sr->senn_mod = sr->senp_mod = 0x1;
+
+ sr->opp1_nvalue = omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP1_VDD2);
+ sr->opp2_nvalue = omap_ctrl_readl(OMAP36XX_CONTROL_FUSE_OPP2_VDD2);
+ } else {
+ sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
+ OMAP343X_SR2_SENNENABLE_MASK) >>
+ OMAP343X_SR2_SENNENABLE_SHIFT;
+
+ sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
+ OMAP343X_SR2_SENPENABLE_MASK) >>
+ OMAP343X_SR2_SENPENABLE_SHIFT;
+
+ sr->opp3_nvalue = omap_ctrl_readl(
+ OMAP343X_CONTROL_FUSE_OPP3_VDD2);
+ sr->opp2_nvalue = omap_ctrl_readl(
+ OMAP343X_CONTROL_FUSE_OPP2_VDD2);
+ sr->opp1_nvalue = omap_ctrl_readl(
+ OMAP343X_CONTROL_FUSE_OPP1_VDD2);
+ }
}
}
@@ -325,22 +349,42 @@ static void sr_set_efuse_nvalues(struct omap_sr *sr)
static void sr_set_testing_nvalues(struct omap_sr *sr)
{
if (sr->srid == SR1) {
- sr->senp_mod = 0x03; /* SenN-M5 enabled */
- sr->senn_mod = 0x03;
-
- /* calculate nvalues for each opp */
- sr->opp5_nvalue = cal_test_nvalue(0xacd + 0x330, 0x848 + 0x330);
- sr->opp4_nvalue = cal_test_nvalue(0x964 + 0x2a0, 0x727 + 0x2a0);
- sr->opp3_nvalue = cal_test_nvalue(0x85b + 0x200, 0x655 + 0x200);
- sr->opp2_nvalue = cal_test_nvalue(0x506 + 0x1a0, 0x3be + 0x1a0);
- sr->opp1_nvalue = cal_test_nvalue(0x373 + 0x100, 0x28c + 0x100);
+ if (cpu_is_omap3630()) {
+ sr->senp_mod = 0x1;
+ sr->senn_mod = 0x1;
+
+ /* calculate nvalues for each opp */
+ sr->opp1_nvalue = cal_test_nvalue(581, 489);
+ sr->opp2_nvalue = cal_test_nvalue(1072, 910);
+ sr->opp3_nvalue = cal_test_nvalue(1405, 1200);
+ sr->opp4_nvalue = cal_test_nvalue(1842, 1580);
+ sr->opp5_nvalue = cal_test_nvalue(1842, 1580);
+ } else {
+ sr->senp_mod = 0x03; /* SenN-M5 enabled */
+ sr->senn_mod = 0x03;
+
+ /* calculate nvalues for each opp */
+ sr->opp5_nvalue = cal_test_nvalue(0xacd + 0x330, 0x848 + 0x330);
+ sr->opp4_nvalue = cal_test_nvalue(0x964 + 0x2a0, 0x727 + 0x2a0);
+ sr->opp3_nvalue = cal_test_nvalue(0x85b + 0x200, 0x655 + 0x200);
+ sr->opp2_nvalue = cal_test_nvalue(0x506 + 0x1a0, 0x3be + 0x1a0);
+ sr->opp1_nvalue = cal_test_nvalue(0x373 + 0x100, 0x28c + 0x100);
+ }
} else if (sr->srid == SR2) {
- sr->senp_mod = 0x03;
- sr->senn_mod = 0x03;
-
- sr->opp3_nvalue = cal_test_nvalue(0x76f + 0x200, 0x579 + 0x200);
- sr->opp2_nvalue = cal_test_nvalue(0x4f5 + 0x1c0, 0x390 + 0x1c0);
- sr->opp1_nvalue = cal_test_nvalue(0x359, 0x25d);
+ if (cpu_is_omap3630()) {
+ sr->senp_mod = 0x1;
+ sr->senn_mod = 0x1;
+
+ sr->opp1_nvalue = cal_test_nvalue(556, 468);
+ sr->opp2_nvalue = cal_test_nvalue(1099, 933);
+ } else {
+ sr->senp_mod = 0x03;
+ sr->senn_mod = 0x03;
+
+ sr->opp3_nvalue = cal_test_nvalue(0x76f + 0x200, 0x579 + 0x200);
+ sr->opp2_nvalue = cal_test_nvalue(0x4f5 + 0x1c0, 0x390 + 0x1c0);
+ sr->opp1_nvalue = cal_test_nvalue(0x359, 0x25d);
+ }
}
}
@@ -487,6 +531,17 @@ static void sr_configure(struct omap_sr *sr)
{
u32 sr_config;
u32 senp_en , senn_en;
+ u32 senp_en_shift, senn_en_shift, err_config;
+
+ if (cpu_is_omap3630()) {
+ senp_en_shift = SRCONFIG_SENPENABLE_SHIFT_36XX;
+ senn_en_shift = SRCONFIG_SENNENABLE_SHIFT_36XX;
+ err_config = ERRCONFIG_36XX;
+ } else {
+ senp_en_shift = SRCONFIG_SENPENABLE_SHIFT;
+ senn_en_shift = SRCONFIG_SENNENABLE_SHIFT;
+ err_config = ERRCONFIG;
+ }
if (sr->clk_length == 0)
sr_set_clk_length(sr);
@@ -498,15 +553,15 @@ static void sr_configure(struct omap_sr *sr)
(sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
SRCONFIG_MINMAXAVG_EN |
- (senn_en << SRCONFIG_SENNENABLE_SHIFT) |
- (senp_en << SRCONFIG_SENPENABLE_SHIFT) |
+ (senn_en << senn_en_shift) |
+ (senp_en << senp_en_shift) |
SRCONFIG_DELAYCTRL;
sr_write_reg(sr, SRCONFIG, sr_config);
sr_write_reg(sr, AVGWEIGHT, SR1_AVGWEIGHT_SENPAVGWEIGHT |
SR1_AVGWEIGHT_SENNAVGWEIGHT);
- sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
+ sr_modify_reg(sr, err_config, (SR_ERRWEIGHT_MASK |
SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
(SR1_ERRWEIGHT | SR1_ERRMAXLIMIT | SR1_ERRMINLIMIT));
@@ -515,14 +570,14 @@ static void sr_configure(struct omap_sr *sr)
(sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
SRCONFIG_MINMAXAVG_EN |
- (senn_en << SRCONFIG_SENNENABLE_SHIFT) |
- (senp_en << SRCONFIG_SENPENABLE_SHIFT) |
+ (senn_en << senn_en_shift) |
+ (senp_en << senp_en_shift) |
SRCONFIG_DELAYCTRL;
sr_write_reg(sr, SRCONFIG, sr_config);
sr_write_reg(sr, AVGWEIGHT, SR2_AVGWEIGHT_SENPAVGWEIGHT |
SR2_AVGWEIGHT_SENNAVGWEIGHT);
- sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
+ sr_modify_reg(sr, err_config, (SR_ERRWEIGHT_MASK |
SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
(SR2_ERRWEIGHT | SR2_ERRMAXLIMIT | SR2_ERRMINLIMIT));
@@ -604,6 +659,7 @@ static int sr_reset_voltage(int srid)
static int sr_enable(struct omap_sr *sr, u32 target_opp_no)
{
u32 nvalue_reciprocal, v;
+ u32 inten, intst, err_config;
if (!(mpu_opps && l3_opps)) {
pr_notice("VSEL values not found\n");
@@ -662,9 +718,19 @@ static int sr_enable(struct omap_sr *sr, u32 target_opp_no)
sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
/* Enable the interrupt */
- sr_modify_reg(sr, ERRCONFIG,
- (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST),
- (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST));
+ if (cpu_is_omap3630()) {
+ inten = ERRCONFIG_VPBOUNDINTEN_36XX;
+ intst = ERRCONFIG_VPBOUNDINTST_36XX;
+ err_config = ERRCONFIG_36XX;
+ } else {
+ inten = ERRCONFIG_VPBOUNDINTEN;
+ intst = ERRCONFIG_VPBOUNDINTST;
+ err_config = ERRCONFIG;
+ }
+
+ sr_modify_reg(sr, err_config,
+ (inten | intst),
+ (inten | intst));
if (sr->srid == SR1) {
/* set/latch init voltage */
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
index 2a0e823..f20406b 100644
--- a/arch/arm/mach-omap2/smartreflex.h
+++ b/arch/arm/mach-omap2/smartreflex.h
@@ -30,6 +30,9 @@
#define SENERROR 0x20
#define ERRCONFIG 0x24
+#define SENERROR_36XX 0x34
+#define ERRCONFIG_36XX 0x38
+
/* SR Modules */
#define SR1 1
#define SR2 2
@@ -106,6 +109,9 @@
#define SRCONFIG_SENNENABLE_SHIFT 5
#define SRCONFIG_SENPENABLE_SHIFT 3
+#define SRCONFIG_SENNENABLE_SHIFT_36XX 1
+#define SRCONFIG_SENPENABLE_SHIFT_36XX 0
+
#define SRCONFIG_SRENABLE BIT(11)
#define SRCONFIG_SENENABLE BIT(10)
#define SRCONFIG_ERRGEN_EN BIT(9)
@@ -136,9 +142,19 @@
#define SR_CLKACTIVITY_IOFF_FOFF (0x00 << 20)
#define SR_CLKACTIVITY_IOFF_FON (0x02 << 20)
+/* IDLEMODE SETTINGS for OMAP3630 */
+#define SR_IDLEMODE_MASK (0x3 << 24)
+#define SR_FORCE_IDLE 0x0
+#define SR_NO_IDLE 0x1
+#define SR_SMART_IDLE 0x2
+#define SR_SMART_IDLE_WKUP 0x3
+
#define ERRCONFIG_VPBOUNDINTEN BIT(31)
#define ERRCONFIG_VPBOUNDINTST BIT(30)
+#define ERRCONFIG_VPBOUNDINTEN_36XX BIT(23)
+#define ERRCONFIG_VPBOUNDINTST_36XX BIT(22)
+
#define SR1_ERRWEIGHT (0x07 << 16)
#define SR1_ERRMAXLIMIT (0x02 << 8)
#define SR1_ERRMINLIMIT (0xFA << 0)
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
index 20f5c98..68100d6 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -283,6 +283,19 @@
#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
+/* OMAP36XX CONTROL FUSE */
+
+#define OMAP36XX_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)
+#define OMAP36XX_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)
+#define OMAP36XX_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
+#define OMAP36XX_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)
+#define OMAP36XX_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0108)
+
+#define OMAP36XX_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
+#define OMAP36XX_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c)
+
+#define OMAP36XX_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130)
+
/*
* Product ID register
*/
--
1.6.2.4
|
