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The Crunch cfnegs and cfnegd instructions have a hardware bug in all silicon
revisions (D0 to E2) whereby neg(0) returns 0 (not -0). See erratum 12.
For ieee-correctness, and to pass another case in GCC's IEEE testsuite,
we disable the instruction and do it in software unless
-funsafe-math-optimizations (included in -ffast-math) is given.
Martin Guy <martinwguy@yahoo.it>, September 2008
Index: gcc-4.2.4/gcc/config/arm/cirrus.md
===================================================================
--- gcc-4.2.4.orig/gcc/config/arm/cirrus.md 2007-09-01 16:28:30.000000000 +0100
+++ gcc-4.2.4/gcc/config/arm/cirrus.md 2009-08-09 15:45:13.000000000 +0100
@@ -254,10 +254,11 @@
[(set_attr "cirrus" "normal")]
)
+; Cirrus hardware bug: neg 0 -> 0 instead of -0
(define_insn "*cirrus_negsf2"
[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
(neg:SF (match_operand:SF 1 "cirrus_fp_register" "v")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && ! HONOR_SIGNED_ZEROS (SFmode)"
"cfnegs%?\\t%V0, %V1"
[(set_attr "cirrus" "normal")]
)
@@ -265,7 +266,7 @@
(define_insn "*cirrus_negdf2"
[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
(neg:DF (match_operand:DF 1 "cirrus_fp_register" "v")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && ! HONOR_SIGNED_ZEROS (DFmode)"
"cfnegd%?\\t%V0, %V1"
[(set_attr "cirrus" "normal")]
)
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