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int->float instructions cfcvt32s and cfcvt32d do seem to work but if they are
enabled, the vorbis testsuite (file lib/vorbisenc.c) fail and lame to segfault
on nonstandard bit rate wav files such as 11050 bps (file libmp3lame/util.c).
Until someone wants to figure out what the real problem is we just disable these
two insns because then everything seems to work.
Index: gcc-4.2.4/gcc/config/arm/arm.md
===================================================================
--- gcc-4.2.4.orig/gcc/config/arm/arm.md 2009-08-19 05:22:36.000000000 +0100
+++ gcc-4.2.4/gcc/config/arm/arm.md 2009-09-07 23:56:05.000000000 +0100
@@ -3190,10 +3190,14 @@
;; Fixed <--> Floating conversion insns
+; Maverick int->float conversion insns seem to work but tickle an optimization
+; bug in GCC 4.[123].* so we paper over it to get working code :-/
+; It may be the same as http://gcc.gnu.org/bugzilla/show_bug.cgi?id=39501
+
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "s_register_operand" "")
(float:SF (match_operand:SI 1 "s_register_operand" "")))]
- "TARGET_ARM && TARGET_HARD_FLOAT"
+ "TARGET_ARM && TARGET_HARD_FLOAT && !TARGET_MAVERICK"
"
if (TARGET_MAVERICK)
{
@@ -3205,7 +3209,7 @@
(define_expand "floatsidf2"
[(set (match_operand:DF 0 "s_register_operand" "")
(float:DF (match_operand:SI 1 "s_register_operand" "")))]
- "TARGET_ARM && TARGET_HARD_FLOAT"
+ "TARGET_ARM && TARGET_HARD_FLOAT && !TARGET_MAVERICK"
"
if (TARGET_MAVERICK)
{
Index: gcc-4.2.4/gcc/config/arm/cirrus.md
===================================================================
--- gcc-4.2.4.orig/gcc/config/arm/cirrus.md 2009-08-19 04:47:30.000000000 +0100
+++ gcc-4.2.4/gcc/config/arm/cirrus.md 2009-09-07 23:50:17.000000000 +0100
@@ -369,10 +369,13 @@
)
;; Convert Cirrus-SI to Cirrus-SF
+
+; int->float conversions are disabled to avoid a GCC bug. See arm.md
+
(define_insn "cirrus_floatsisf2"
[(set (match_operand:SF 0 "cirrus_fp_register" "=v")
(float:SF (match_operand:SI 1 "s_register_operand" "r")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfmv64lr%?\\t%Z0, %1\;cfcvt32s%?\\t%V0, %Y0"
[(set_attr "type" "f_cvt")
(set_attr "length" "8")
@@ -382,7 +385,7 @@
(define_insn "cirrus_floatsidf2"
[(set (match_operand:DF 0 "cirrus_fp_register" "=v")
(float:DF (match_operand:SI 1 "s_register_operand" "r")))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
"cfmv64lr%?\\t%Z0, %1\;cfcvt32d%?\\t%V0, %Y0"
[(set_attr "type" "f_cvt")
(set_attr "length" "8")
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