diff options
Diffstat (limited to 'recipes/u-boot/u-boot-1.3.2')
25 files changed, 3899 insertions, 0 deletions
diff --git a/recipes/u-boot/u-boot-1.3.2/boc01/001-090205-SPI.patch b/recipes/u-boot/u-boot-1.3.2/boc01/001-090205-SPI.patch new file mode 100644 index 0000000000..6c0ed5c36a --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/boc01/001-090205-SPI.patch @@ -0,0 +1,94 @@ +Index: u-boot-1.3.2/board/freescale/mpc8313erdb/mpc8313erdb.c +=================================================================== +--- u-boot-1.3.2.orig/board/freescale/mpc8313erdb/mpc8313erdb.c ++++ u-boot-1.3.2/board/freescale/mpc8313erdb/mpc8313erdb.c +@@ -28,6 +28,7 @@ + #endif + #include <pci.h> + #include <mpc83xx.h> ++#include <spi.h> + + DECLARE_GLOBAL_DATA_PTR; + +@@ -107,3 +108,33 @@ void ft_board_setup(void *blob, bd_t *bd + #endif + } + #endif ++ ++ ++/* ++ * The following are used to control the SPI chip selects for the SPI command. ++ */ ++#ifdef CONFIG_HARD_SPI ++ ++#define SPI_CS_MASK 0x80000000 ++ ++void spi_eeprom_chipsel(int cs) ++{ ++ volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; ++ ++ if (cs) ++ iopd->dat &= ~SPI_CS_MASK; ++ else ++ iopd->dat |= SPI_CS_MASK; ++} ++ ++/* ++ * The SPI command uses this table of functions for controlling the SPI ++ * chip selects. ++ */ ++spi_chipsel_type spi_chipsel[] = { ++ spi_eeprom_chipsel, ++}; ++int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); ++ ++#endif /* CONFIG_HARD_SPI */ ++ +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h +@@ -369,6 +369,7 @@ + #define CONFIG_CMD_PCI + #define CONFIG_CMD_NAND + #define CONFIG_CMD_JFFS2 ++#define CONFIG_CMD_SPI + + #if defined(CFG_RAMBOOT) + #undef CONFIG_CMD_ENV +@@ -386,6 +387,11 @@ + #define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:384k(uboot),64k(env)" + + ++/* SPI */ ++#define CONFIG_MPC8XXX_SPI ++#define CONFIG_HARD_SPI /* SPI with hardware support */ ++#undef CONFIG_SOFT_SPI /* SPI bit-banged */ ++ + /* + * Miscellaneous configurable options + */ +Index: u-boot-1.3.2/drivers/spi/mpc8xxx_spi.c +=================================================================== +--- u-boot-1.3.2.orig/drivers/spi/mpc8xxx_spi.c ++++ u-boot-1.3.2/drivers/spi/mpc8xxx_spi.c +@@ -34,6 +34,8 @@ + #define SPI_MODE_REV (0x80000000 >> 5) /* Reverse mode - MSB first */ + #define SPI_MODE_MS (0x80000000 >> 6) /* Always master */ + #define SPI_MODE_EN (0x80000000 >> 7) /* Enable interface */ ++#define SPI_MODE_DIV16 (0x80000000 >> 4) /*Divide by 16. */ ++#define SPI_MODE_LEN_8 (0x00700000) /*0111 8-bit characters*/ + + #define SPI_TIMEOUT 1000 + +@@ -45,9 +47,7 @@ void spi_init(void) + * SPI pins on the MPC83xx are not muxed, so all we do is initialize + * some registers + */ +- spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN; +- spi->mode = (spi->mode & 0xfff0ffff) | (1 << 16); /* Use SYSCLK / 8 +- (16.67MHz typ.) */ ++ spi->mode = SPI_MODE_DIV16 |SPI_MODE_LEN_8| SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN; + spi->event = 0xffffffff; /* Clear all SPI events */ + spi->mask = 0x00000000; /* Mask all SPI interrupts */ + spi->com = 0; /* LST bit doesn't do anything, so disregard */ diff --git a/recipes/u-boot/u-boot-1.3.2/boc01/002-081212-GPIO.patch b/recipes/u-boot/u-boot-1.3.2/boc01/002-081212-GPIO.patch new file mode 100644 index 0000000000..0fb3daf98e --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/boc01/002-081212-GPIO.patch @@ -0,0 +1,252 @@ +Index: u-boot-1.3.2/board/freescale/mpc8313erdb/mpc8313erdb.c +=================================================================== +--- u-boot-1.3.2.orig/board/freescale/mpc8313erdb/mpc8313erdb.c ++++ u-boot-1.3.2/board/freescale/mpc8313erdb/mpc8313erdb.c +@@ -29,6 +29,7 @@ + #include <pci.h> + #include <mpc83xx.h> + #include <spi.h> ++#include <gpio.h> + + DECLARE_GLOBAL_DATA_PTR; + +@@ -44,6 +45,48 @@ int board_early_init_f(void) + return 0; + } + ++int misc_init_f(void) ++{ ++ uchar value; ++ uchar i; ++ ++#ifdef PRE_INIT_GPIO ++ value=PRE_INIT_GPIO; ++ ++ for(i=0;i<MAX_GPIO_OUT;i++) ++ { ++ if(value&(1<<i)) ++ { ++ gpio_set(i); ++ } ++ else ++ { ++ gpio_clear(i); ++ } ++ } ++ udelay(1000); ++#endif ++ ++ ++#ifdef INIT_GPIO ++ value=INIT_GPIO; ++ for(i=0;i<MAX_GPIO_OUT;i++) ++ { ++ if(value&(1<<i)) ++ { ++ gpio_set(i); ++ } ++ else ++ { ++ gpio_clear(i); ++ } ++ } ++ puts("GPIO: ready\n"); ++#endif ++ ++ return 0; ++} ++ + int checkboard(void) + { + puts("Board: Freescale MPC8313ERDB\n"); +@@ -109,7 +152,42 @@ void ft_board_setup(void *blob, bd_t *bd + } + #endif + ++#ifdef CONFIG_CMD_GPIO ++void gpio_set(unsigned char ucGpio) ++{ ++ unsigned long ulMask=0; ++ volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; ++ if(ucGpio<32) ++ { ++ ulMask=1<<(31-ucGpio); ++ iopd->dir |= ulMask; ++ iopd->dat |= ulMask; ++ } ++} ++ ++void gpio_clear(unsigned char ucGpio) ++{ ++ unsigned long ulMask=0; ++ volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; ++ if(ucGpio<32) ++ { ++ ulMask=1<<(31-ucGpio); ++ iopd->dir |= ulMask; ++ iopd->dat &= ~ulMask; ++ } ++} + ++char gpio_get(unsigned char ucGpio) ++{ ++ unsigned long ulMask=0; ++ volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; ++ if(ucGpio<32) ++ { ++ ulMask=1<<(31-ucGpio); ++ } ++ return (iopd->dat& ulMask)? 1:0; ++} ++#endif + /* + * The following are used to control the SPI chip selects for the SPI command. + */ +Index: u-boot-1.3.2/common/cmd_gpio.c +=================================================================== +--- /dev/null ++++ u-boot-1.3.2/common/cmd_gpio.c +@@ -0,0 +1,76 @@ ++/* ++ * (C) Copyright 2001 ++ * Alexandre Coffignal, CenoSYS, alexandre.coffignal@cenosys.com ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++ ++#include <common.h> ++#include <config.h> ++#include <command.h> ++#include <gpio.h> ++ ++ ++int do_gpio (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) ++{ ++ unsigned char ucGpio; ++ ++ if (argc < 3) ++ goto usage; ++ ++ ucGpio = simple_strtoul (argv[2], NULL, 10); ++ ++ if (!strncmp(argv[1], "set", 3)) ++ { ++ gpio_set(ucGpio); ++ } ++ else ++ if (!strncmp(argv[1], "clear", 5)) ++ { ++ gpio_clear(ucGpio); ++ } ++ else ++ if (!strncmp(argv[1], "get", 3)) ++ { ++ printf("%s %s %d = %d\n",argv[0],argv[1],ucGpio, gpio_get(ucGpio)); ++ return 0; ++ } ++ else ++ goto usage; ++ ++ printf("%s %s %d\n",argv[0],argv[1],ucGpio); ++ ++ return 0; ++ ++usage : ++ printf ("Usage:\n%s\n", cmdtp->usage); ++ return 1; ++} /* do_gpio() */ ++ ++/***************************************************/ ++ ++U_BOOT_CMD( ++ gpio, 3, 1, do_gpio, ++ "gpio - General Purpose Input/Output\n", ++ " - Set or clear General Purpose Output.\n" ++ "<set/clear/get> - Set or clear General Purpose Output.\n" ++ "<gpio> - number of gpio to be set/clear/get \n" ++); ++ +Index: u-boot-1.3.2/common/Makefile +=================================================================== +--- u-boot-1.3.2.orig/common/Makefile ++++ u-boot-1.3.2/common/Makefile +@@ -50,6 +50,7 @@ endif + COBJS-$(CONFIG_CMD_DISPLAY) += cmd_display.o + COBJS-$(CONFIG_CMD_DOC) += cmd_doc.o + COBJS-$(CONFIG_CMD_DTT) += cmd_dtt.o ++COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o + COBJS-y += cmd_eeprom.o + COBJS-$(CONFIG_CMD_ELF) += cmd_elf.o + COBJS-$(CONFIG_CMD_EXT2) += cmd_ext2.o +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h +@@ -49,6 +49,7 @@ + #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + + #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ ++#define CONFIG_MISC_INIT_F + + #define CFG_IMMR 0xE0000000 + +@@ -370,6 +371,7 @@ + #define CONFIG_CMD_NAND + #define CONFIG_CMD_JFFS2 + #define CONFIG_CMD_SPI ++#define CONFIG_CMD_GPIO + + #if defined(CFG_RAMBOOT) + #undef CONFIG_CMD_ENV +@@ -392,6 +394,11 @@ + #define CONFIG_HARD_SPI /* SPI with hardware support */ + #undef CONFIG_SOFT_SPI /* SPI bit-banged */ + ++/* GPIO */ ++#define PRE_INIT_GPIO 0x28 ++#define INIT_GPIO 0x08 ++#define MAX_GPIO_OUT 7 ++ + /* + * Miscellaneous configurable options + */ +@@ -457,7 +464,7 @@ + + /* System IO Config */ + #define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ +-#define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */ ++#define CFG_SICRL (SICRL_USBDR |SICRL_LBC) /* Enable Internal USB Phy */ + + #define CFG_HID0_INIT 0x000000000 + #define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ +Index: u-boot-1.3.2/include/gpio.h +=================================================================== +--- /dev/null ++++ u-boot-1.3.2/include/gpio.h +@@ -0,0 +1,9 @@ ++#ifndef __GPIO_H__ ++#define __GPIO_H__ ++ ++extern void gpio_set(unsigned char ucGpio); ++extern void gpio_clear(unsigned char ucGpio); ++extern char gpio_get(unsigned char ucGpio); ++ ++#endif /* __GPIO_H__ */ ++ diff --git a/recipes/u-boot/u-boot-1.3.2/boc01/003-081205-DTT_LM73.patch b/recipes/u-boot/u-boot-1.3.2/boc01/003-081205-DTT_LM73.patch new file mode 100644 index 0000000000..9f821f4c71 --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/boc01/003-081205-DTT_LM73.patch @@ -0,0 +1,44 @@ +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h 2008-12-09 16:27:32.000000000 +0100 ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h 2008-12-09 16:28:14.000000000 +0100 +@@ -371,6 +371,7 @@ + #define CONFIG_CMD_NAND + #define CONFIG_CMD_JFFS2 + #define CONFIG_CMD_SPI ++#define CONFIG_CMD_DTT + #define CONFIG_CMD_GPIO + + #if defined(CFG_RAMBOOT) +@@ -399,6 +400,13 @@ + #define INIT_GPIO 0x08 + #define MAX_GPIO_OUT 7 + ++/* Digital Thermometer and Thermostat */ ++#define CONFIG_DTT_LM73 1 ++#define CONFIG_DTT_SENSORS { 0x49 } ++#define CONFIG_DTT_ALARM ++#define CFG_DTT_MAX_TEMP 70 ++#define CFG_DTT_MIN_TEMP -30 ++ + /* + * Miscellaneous configurable options + */ +Index: u-boot-1.3.2/drivers/hwmon/lm73.c +=================================================================== +--- u-boot-1.3.2.orig/drivers/hwmon/lm73.c 2008-03-09 16:20:02.000000000 +0100 ++++ u-boot-1.3.2/drivers/hwmon/lm73.c 2008-12-09 16:27:46.000000000 +0100 +@@ -134,8 +134,13 @@ + /* + * Setup configuraton register + */ ++#ifdef CONFIG_DTT_ALARM ++ /* config = alert active low, enabled, and reset */ ++ val = 0x40; ++#else + /* config = alert active low, disabled, and reset */ + val = 0x64; ++#endif + if (dtt_write(sensor, DTT_CONFIG, val)) + return 1; + /* diff --git a/recipes/u-boot/u-boot-1.3.2/boc01/004-081205-WATCHDOG.patch b/recipes/u-boot/u-boot-1.3.2/boc01/004-081205-WATCHDOG.patch new file mode 100644 index 0000000000..e6e291d9b9 --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/boc01/004-081205-WATCHDOG.patch @@ -0,0 +1,15 @@ +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h 2008-12-09 16:30:51.000000000 +0100 ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h 2008-12-09 16:30:51.000000000 +0100 +@@ -470,6 +470,10 @@ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) + ++ ++#define CONFIG_WATCHDOG ++#define CFG_WATCHDOG_VALUE 0xFFFF ++ + /* System IO Config */ + #define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ + #define CFG_SICRL (SICRL_USBDR |SICRL_LBC) /* Enable Internal USB Phy */ diff --git a/recipes/u-boot/u-boot-1.3.2/boc01/006-081205-EEPROM_INTERSIL.patch b/recipes/u-boot/u-boot-1.3.2/boc01/006-081205-EEPROM_INTERSIL.patch new file mode 100644 index 0000000000..21d7cba1a3 --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/boc01/006-081205-EEPROM_INTERSIL.patch @@ -0,0 +1,16 @@ +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h 2008-12-09 16:30:51.000000000 +0100 ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h 2008-12-09 16:31:01.000000000 +0100 +@@ -269,9 +269,9 @@ + */ + #define CONFIG_CMD_EEPROM + #define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ +-#define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C256*/ ++#define CFG_I2C_EEPROM_ADDR 0x57 /* Intersil 12024 (eeprom)*/ + #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */ +-#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64-Byte Page Write Mode */ ++#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16-Byte Page Write Mode */ + #define CFG_EEPROM_PAGE_WRITE_ENABLE + + /* TSEC */ diff --git a/recipes/u-boot/u-boot-1.3.2/boc01/006-081211-EEPROM_M24C32.patch b/recipes/u-boot/u-boot-1.3.2/boc01/006-081211-EEPROM_M24C32.patch new file mode 100644 index 0000000000..b448d0f62d --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/boc01/006-081211-EEPROM_M24C32.patch @@ -0,0 +1,13 @@ +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h +@@ -271,7 +271,7 @@ + #define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ + #define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C256*/ + #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */ +-#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64-Byte Page Write Mode */ ++#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */ + #define CFG_EEPROM_PAGE_WRITE_ENABLE + + /* TSEC */ diff --git a/recipes/u-boot/u-boot-1.3.2/boc01/007-090217-CAPSENSE.patch b/recipes/u-boot/u-boot-1.3.2/boc01/007-090217-CAPSENSE.patch new file mode 100644 index 0000000000..1b7630536f --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/boc01/007-090217-CAPSENSE.patch @@ -0,0 +1,546 @@ +Index: u-boot-1.3.2/common/cmd_capsense.c +=================================================================== +--- /dev/null ++++ u-boot-1.3.2/common/cmd_capsense.c +@@ -0,0 +1,105 @@ ++/* ++ * (C) Copyright 2008 ++ * Alexandre Coffignal, CénoSYS, alexandre.coffignal@cenosys.com ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ * CapSense Express touch-sensing buttons ++ */ ++ ++#include <common.h> ++#include <config.h> ++#include <command.h> ++ ++#include <capsense.h> ++#include <i2c.h> ++ ++#define ARG_SENSOR_NUMBER 1 ++ ++#define ARG_CMD 1 ++#define ARG_OLD_ADDRESS 2 ++ ++ ++int do_capsense (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) ++{ ++ int i; ++ unsigned char sensors[] = CONFIG_CAPSENSE_SENSORS; ++ int old_bus, old_address; ++ char port[2]; ++ /* switch to correct I2C bus */ ++ old_bus = I2C_GET_BUS(); ++ I2C_SET_BUS(CFG_CAPSENSE_BUS_NUM); ++ ++ /* ++ * Loop through sensors, read ++ * state, and output it. ++ */ ++ if(argc==1) ++ { ++ port[0]=capsense_get_state(CONFIG_CAPSENSE_I2C_ADDRESS,0); ++ port[1]=capsense_get_state(CONFIG_CAPSENSE_I2C_ADDRESS,1); ++ capsense_get_state(CONFIG_CAPSENSE_I2C_ADDRESS,1); ++ printf ("P0 0x%02x 0x%02x\n",port[0],port[1]); ++ for (i = 0; i < 8; i++) ++ { ++ if(sensors[0]&(1<<i)) ++ { ++ printf ("GP0[%d]: %i\n",i,port[0]&(1<<i)?1:0); ++ } ++ if(sensors[1]&(1<<i)) ++ { ++ printf ("GP1[%d]: %i\n",i,port[1]&(1<<i)?1:0); ++ } ++ ++ } ++ } ++ else ++ { ++ if ( strncmp(argv[ARG_CMD], "config", 3) == 0 ) { ++ if ( argc == 3 ) { ++ old_address=simple_strtoul (argv[ARG_OLD_ADDRESS], NULL, 10); ++ if ( capsense_change_i2c_address(old_address, CONFIG_CAPSENSE_I2C_ADDRESS) != 0 ) ++ printf("failed to change i2c address\n"); ++ else ++ printf("i2c address changed to 0x%02X\n", CONFIG_CAPSENSE_I2C_ADDRESS); ++ } ++ ++ capsense_config(CONFIG_CAPSENSE_I2C_ADDRESS); ++ capsense_store_nvm(CONFIG_CAPSENSE_I2C_ADDRESS); ++ } ++ else { ++ printf ("Usage:\n%s\n", cmdtp->help); ++ } ++ } ++ ++ /* switch back to original I2C bus */ ++ I2C_SET_BUS(old_bus); ++ ++ return 0; ++} /* do_capsense() */ ++ ++ ++/***************************************************/ ++ ++U_BOOT_CMD( ++ capsense, 4, 1, do_capsense, ++ "capsense - CapSense Express touch-sensing buttons\n", ++ "capsense\n Read state of the CapSense Express touch-sensing buttons.\n" ++ "capsense config [<old i2c address>]\n Setup default capsense configuration.\n" ++ ); +Index: u-boot-1.3.2/common/Makefile +=================================================================== +--- u-boot-1.3.2.orig/common/Makefile ++++ u-boot-1.3.2/common/Makefile +@@ -50,6 +50,7 @@ endif + COBJS-$(CONFIG_CMD_DISPLAY) += cmd_display.o + COBJS-$(CONFIG_CMD_DOC) += cmd_doc.o + COBJS-$(CONFIG_CMD_DTT) += cmd_dtt.o ++COBJS-$(CONFIG_CMD_CAPSENSE) += cmd_capsense.o + COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o + COBJS-y += cmd_eeprom.o + COBJS-$(CONFIG_CMD_ELF) += cmd_elf.o +Index: u-boot-1.3.2/drivers/i2c/CY8C201xx.c +=================================================================== +--- /dev/null ++++ u-boot-1.3.2/drivers/i2c/CY8C201xx.c +@@ -0,0 +1,289 @@ ++/* ++ * (C) Copyright 2008 ++ * Alexandre Coffignal, CénoSYS, alexandre.coffignal@cenosys.com ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* ++ * CapSense Express touch-sensing buttons ++ */ ++ ++#include <common.h> ++ ++#ifdef CONFIG_CAPSENSE_CY8C201XX ++ ++#include <i2c.h> ++#include <capsense.h> ++ ++int capsense_read(int address, int reg) ++{ ++ int dlen; ++ uchar data[2]; ++ ++ /* ++ * Validate 'reg' param ++ */ ++ if ( (reg < 0) || (reg > 0xA1) ) ++ return -1; ++ ++ /* ++ * Prepare to handle 1 byte result. ++ */ ++ dlen = 1; ++ ++ /* ++ * Now try to read the register. ++ */ ++ if (i2c_read(address, reg, 1, data, dlen) != 0) ++ return -1; ++ ++ return (int)data[0]; ++} ++ ++ ++int capsense_write(int address, int reg, int val) ++{ ++ int dlen; ++ uchar data[2]; ++ ++ /* ++ * Validate 'reg' param ++ */ ++ if((reg < 0) || (reg > 0xA1)) ++ return -1; ++ ++ /* ++ * Handle 1 byte values. ++ */ ++ dlen = 1; ++ data[0] = (char)(val & 0xff); ++ ++ /* ++ * Write value to register. ++ */ ++ if (i2c_write(address, reg, 1, data, dlen) != 0) ++ return 1; ++ ++ return 0; ++} ++ ++ ++int capsense_write_N(int address, int reg, char *data, int dlen) ++{ ++ /* ++ * Validate 'reg' param ++ */ ++ if ( (reg < 0) || (reg > 0xA1) ) ++ return -1; ++ ++ /* ++ * Write value to register. ++ */ ++ if ( i2c_write(address, reg, 1, data, dlen) != 0 ) ++ return 1; ++ ++ return 0; ++} ++ ++ ++int capsense_get_state(int address,char port) ++{ ++ return capsense_read(address,CAPSENSE_REG_READ_STATUS+port); ++} ++ ++ ++int capsense_change_i2c_address(char old_address,char new_address) ++{ ++ unsigned char data[4]; ++ int read_address; ++ printf("capsense change i2c address\n"); ++ //checking if the I2C address is in the limits ( I2C address can have a value from 0 to 127 ) ++ if((old_address>0x7F)||(new_address>0x7F)) ++ { ++ printf("I2C address is not in the limits\n"); ++ return 1; ++ } ++ ++ //reading old capsence address ++ read_address=capsense_read(old_address, CAPSENSE_REG_I2C_ADDR_DM); ++ if(read_address==0xFFFFFFFF) ++ { ++ printf("error reading old capsence address\n"); ++ return 1; //capsense do not respond at new address ++ } ++ ++ if((read_address&0x7F)!=old_address) ++ { ++ printf("reading old capsence address failed\n"); ++ return 1; //Capsense not respond correctly ++ } ++ ++ //writing command for unlocking the I2C device address lock ++ data[0]=0x3C; ++ data[1]=0xA5; ++ data[2]=0x69; ++ if(capsense_write_N(old_address, CAPSENSE_REG_I2C_DEV_LOCK, data , 3)!=0) ++ { ++ printf("writing command for unlocking the I2C device address lock failed\n"); ++ return 1; ++ } ++ ++ //writing the new I2C address to the device I2C address register ++ if(capsense_write(old_address, CAPSENSE_REG_I2C_ADDR_DM,new_address|0x80)!=0) ++ { ++ printf("writing the new I2C address to the device I2C address register failed\n"); ++ return 1; ++ } ++ ++ //writing command for locking the I2C device address lock ++ data[0]=0x96; ++ data[1]=0x5A; ++ data[2]=0xC3; ++ if(capsense_write_N(old_address, CAPSENSE_REG_I2C_DEV_LOCK, data , 3)!=0) ++ { ++ printf("writing command for locking the I2C device failed\n"); ++ return 1; ++ } ++ ++ //reading new capsence address ++ read_address=capsense_read(new_address, CAPSENSE_REG_I2C_ADDR_DM); ++ if(read_address==0xFFFFFFFF) ++ { ++ printf("capsense do not respond at new address\n"); ++ return 1; //capsense do not respond at new address ++ } ++ ++ return 0; ++} ++ ++ ++static char data_GPIO_ENABLE[] = { ++ 0x00, 0x00 // GPIO_ENABLE ++}; ++ ++static char data_CS_ENABLE[] = { ++ 0x1D, 0x10, // CS_ENABLE ++ 0x02, 0x0F, // GPIO_ENABLE ++ 0x00, 0x00, // INVERSION_MASK ++ 0x00, 0x00, // INT_MASK ++ 0x1F, 0x1F, // STATUS_HOLD_MSK ++ 0x00, 0x02, 0x00, 0x00, // DM_PULL_UP0, DM_STRONG0, DM_HIGHZ0, DM_OD_LOW0 ++ 0x00, 0x0F, 0x00, 0x00, // DM_PULL_UP1, DM_STRONG1, DM_HIGHZ1, DM_OD_LOW1 ++}; ++ ++static char data_OUTPUT_PORT[] = { ++ 0x00, 0x00 // OUTPUT_PORT ++}; ++ ++static char data_OP_SEL[] = { ++ 0x00, 0x00, 0x00, 0x00, 0x00, // OP_SEL_00 ++ 0x80, 0x01, 0x00, 0x00, 0x00, // OP_SEL_01 ++ 0x00, 0x00, 0x00, 0x00, 0x00, // OP_SEL_02 ++ 0x00, 0x00, 0x00, 0x00, 0x00, // OP_SEL_03 ++ 0x00, 0x00, 0x00, 0x00, 0x00, // OP_SEL_04 ++ 0x80, 0x10, 0x00, 0x00, 0x00, // OP_SEL_10 ++ 0x80, 0x08, 0x00, 0x00, 0x00, // OP_SEL_11 ++ 0x80, 0x04, 0x00, 0x00, 0x00, // OP_SEL_12 ++ 0x80, 0x00, 0x10, 0x00, 0x00, // OP_SEL_13 ++ 0x00, 0x00, 0x00, 0x00, 0x00, // OP_SEL_14 ++}; ++ ++static char data_CS_NOISE_TH[] = { ++ 0x28, // CS_NOISE_TH ++ 0x64, // CS_BL_UPD_TH ++ 0xA0, // CS_SETL_TIME ++ 0x22, // CS_OTH_SET ++ 0x0A, // CS_HYSTERESIS ++ 0x03, // CS_DEBOUNCE ++ 0x14, // CS_NEG_NOISE_TH ++ 0x14, // CS_LOW_BL_RST ++ 0x00, // CS_FILTERING ++}; ++ ++static char data_CS_SCAN_POS[] = { ++ 0x00, 0x00, 0x00, 0x00, 0x00, // CS_SCAN_POS_0x ++ 0x00, 0x00, 0x00, 0x00, 0x00, // CS_SCAN_POS_1x ++ 0x32, 0x00, 0x32, 0x32, 0x32, // CS_FINGER_TH_0x ++ 0x00, 0x00, 0x00, 0x00, 0x32, // CS_FINGER_TH_1x ++ 0x14, 0x00, 0x0C, 0x0A, 0x14, // CS_IDAC_0x ++ 0x00, 0x00, 0x00, 0x00, 0x0D // CS_IDAC_1x ++}; ++ ++static char data_SLEEP[] = { ++ 0x00, // SLEEP_PIN ++ 0x20, // SLEEP_CTRL ++ 0x00, // SLEEP_SA_CTR ++}; ++ ++int capsense_config(char address) ++{ ++ printf("Setting default capsense configuration at i2c address 0x%02X...\n", address); ++ ++ //entering setup operation mode ++ if ( capsense_write(address, CAPSENSE_COMMAND_REG, CAPSENSE_CMD_SETUP_OPERATION_MODE) != 0 ) { ++ printf("CAPSENSE_COMMAND_REG SETUP_OPERATION_MODE\n"); ++ return 1; ++ } ++ if ( capsense_write_N(address, CAPSENSE_REG_GPIO_ENABLE, data_GPIO_ENABLE, sizeof(data_GPIO_ENABLE)) != 0 ) { ++ printf("CAPSENSE_REG_GPIO_ENABLE\n"); ++ return 1; ++ } ++ if ( capsense_write_N(address, CAPSENSE_REG_CS_ENABLE, data_CS_ENABLE, sizeof(data_CS_ENABLE)) != 0 ) { ++ printf("CAPSENSE_REG_CS_ENABLE\n"); ++ return 1; ++ } ++ if ( capsense_write_N(address, CAPSENSE_REG_OUTPUT_PORT, data_OUTPUT_PORT, sizeof(data_OUTPUT_PORT)) != 0 ) { ++ printf("CAPSENSE_REG_OUTPUT_PORT\n"); ++ return 1; ++ } ++ if ( capsense_write_N(address, CAPSENSE_REG_OP_SEL_0, data_OP_SEL, sizeof(data_OP_SEL)) != 0 ) { ++ printf("CAPSENSE_REG_OP_SEL_0\n"); ++ return 1; ++ } ++ if ( capsense_write_N(address, CAPSENSE_REG_CS_NOISE_TH, data_CS_NOISE_TH, sizeof(data_CS_NOISE_TH)) != 0 ) { ++ printf("CAPSENSE_REG_CS_NOISE_TH\n"); ++ return 1; ++ } ++ if ( capsense_write_N(address, CAPSENSE_REG_CS_SCAN_POS, data_CS_SCAN_POS, sizeof(data_CS_SCAN_POS)) != 0 ) { ++ printf("CAPSENSE_REG_CS_SCAN_POS\n"); ++ return 1; ++ } ++ if ( capsense_write_N(address, CAPSENSE_REG_SLEEP_PIN, data_SLEEP, sizeof(data_SLEEP)) != 0 ) { ++ printf("CAPSENSE_REG_SLEEP_PIN\n"); ++ return 1; ++ } ++ if ( capsense_write(address, CAPSENSE_COMMAND_REG, CAPSENSE_CMD_NORMAL_OPERATION_MODE) != 0 ) { ++ printf("CAPSENSE_COMMAND_REG NORMAL_OPERATION_MODE\n"); ++ return 1; ++ } ++ ++ printf("...done.\n"); ++ ++ return 0; ++} ++ ++void capsense_store_nvm(char address) ++{ ++ //storing the new current configuration to NVM ++ printf("Storing capsense configuration to NVM\n"); ++ capsense_write(address, CAPSENSE_COMMAND_REG, CAPSENSE_CMD_STORE_TO_NVM); ++} ++ ++#endif /* CONFIG_CAPSENSE_CY8C201XX */ +Index: u-boot-1.3.2/drivers/i2c/Makefile +=================================================================== +--- u-boot-1.3.2.orig/drivers/i2c/Makefile ++++ u-boot-1.3.2/drivers/i2c/Makefile +@@ -29,6 +29,7 @@ COBJS-y += fsl_i2c.o + COBJS-y += omap1510_i2c.o + COBJS-y += omap24xx_i2c.o + COBJS-y += tsi108_i2c.o ++COBJS-y += CY8C201xx.o + + COBJS := $(COBJS-y) + SRCS := $(COBJS:.o=.c) +Index: u-boot-1.3.2/include/capsense.h +=================================================================== +--- /dev/null ++++ u-boot-1.3.2/include/capsense.h +@@ -0,0 +1,95 @@ ++/* ++ * (C) Copyright 2008 ++ * Alexandre Coffignal, CénoSYS, alexandre.coffignal@cenosys.com ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USCY8C201xx.c:234:A ++ */ ++ ++/* ++ * CapSense Express touch-sensing buttons. ++ */ ++#ifndef _CAPSENSE_H_ ++#define _CAPSENSE_H_ ++ ++#if defined(CONFIG_CAPSENSE_CY8C201XX) ++ ++#define CONFIG_CAPSENSE /* We have a Capsense */ ++ ++#ifndef CONFIG_CAPSENSE_SENSORS ++/*config for CY3218-CAPEXP1*/ ++#define CONFIG_CAPSENSE_LED {0x05,0x02} // port 0-{0,3} port 1-{2} ++#define CONFIG_CAPSENSE_SENSOR {0x02,0x0C} // port 0-{2} port 1-{3,4} ++#endif ++#endif /* CONFIG_CAPSENSE_SENSORS */ ++ ++extern int capsense_read(int address, int reg); ++extern int capsense_write(int address, int reg, int val); ++extern int capsense_get_state(int address,char port); ++extern int capsense_change_i2c_address(char old_address,char new_address); ++extern int capsense_config(char address); ++extern void capsense_store_nvm(char address); ++#endif ++ ++#if !defined(CFG_CAPSENSE_BUS_NUM) ++#define CFG_CAPSENSE_BUS_NUM 1 ++ ++//----------------------------------------------- ++// Register Map and corresponding constants ++//----------------------------------------------- ++ ++ ++#define CAPSENSE_REG_STATUS_PORT 0x02 ++#define CAPSENSE_REG_OUTPUT_PORT 0x04 ++#define CAPSENSE_REG_CS_ENABLE 0x06 ++#define CAPSENSE_REG_GPIO_ENABLE 0x08 ++#define CAPSENSE_REG_INVERSION_MASK 0x0A ++#define CAPSENSE_REG_INT_MASK 0x0C ++#define CAPSENSE_REG_STATUS_HOLD_MSK 0x0E ++#define CAPSENSE_REG_DRIVE_MODE 0x10 ++#define CAPSENSE_REG_OP_SEL_0 0x1C ++#define CAPSENSE_REG_OP_SEL_1 0x35 ++#define CAPSENSE_REG_CS_NOISE_TH 0x4E ++#define CAPSENSE_REG_CS_SETL_TIME 0x50 ++#define CAPSENSE_REG_CS_OTH_SET 0x51 ++#define CAPSENSE_REG_CS_HYSTERESIS 0x52 ++#define CAPSENSE_REG_CS_DEBOUNCE 0x53 ++#define CAPSENSE_REG_CS_NEG_NOISE_TH 0x54 ++#define CAPSENSE_REG_CS_SCAN_POS 0x57 ++#define CAPSENSE_REG_CS_FINGER_TH 0x61 ++#define CAPSENSE_REG_CS_IDAC 0x6B ++#define CAPSENSE_REG_CS_SLID_CONFIG 0x75 ++#define CAPSENSE_REG_CS_SLID_MUL 0x77 ++#define CAPSENSE_REG_I2C_DEV_LOCK 0x79 ++#define CAPSENSE_REG_DEVICE_ID 0x7A ++#define CAPSENSE_REG_I2C_ADDR_DM 0x7C ++#define CAPSENSE_REG_SLEEP_PIN 0x7E ++#define CAPSENSE_REG_SLEEP_CTRL 0x7F ++#define CAPSENSE_REG_SLEEP_SA_CTR 0x80 ++#define CAPSENSE_REG_CS_READ_BUTTON 0x81 ++#define CAPSENSE_REG_CS_READ_BL 0x82 ++#define CAPSENSE_REG_READ_STATUS 0x88 ++#define CAPSENSE_REG_READ_CEN_POS 0x8A ++ ++#define CAPSENSE_COMMAND_REG 0xA0 ++ ++#define CAPSENSE_CMD_STORE_TO_NVM 0x01 ++#define CAPSENSE_CMD_NORMAL_OPERATION_MODE 0x07 ++#define CAPSENSE_CMD_SETUP_OPERATION_MODE 0x08 ++ ++#endif /* _CAPSENSE_H_ */ +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h +@@ -407,6 +407,13 @@ + #define CFG_DTT_MAX_TEMP 70 + #define CFG_DTT_MIN_TEMP -30 + ++/*Capsense touch sensing buttons (Cpe board)*/ ++#define CONFIG_CMD_CAPSENSE ++#define CONFIG_CAPSENSE_CY8C201XX 1 ++#define CONFIG_CAPSENSE_I2C_ADDRESS 0x25 ++#define CONFIG_CAPSENSE_LEDS {0x02,0x0F} // port 0-{1} port 1-{0,1,2,3} ++#define CONFIG_CAPSENSE_SENSORS {0x1D,0x10} // port 0-{0,2,3,4} port 1-{4} ++ + /* + * Miscellaneous configurable options + */ diff --git a/recipes/u-boot/u-boot-1.3.2/boc01/008-090107-TSEC.patch b/recipes/u-boot/u-boot-1.3.2/boc01/008-090107-TSEC.patch new file mode 100644 index 0000000000..faa8a3a0be --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/boc01/008-090107-TSEC.patch @@ -0,0 +1,157 @@ +Index: u-boot-1.3.2/drivers/net/tsec.c +=================================================================== +--- u-boot-1.3.2.orig/drivers/net/tsec.c 2008-03-09 16:20:02.000000000 +0100 ++++ u-boot-1.3.2/drivers/net/tsec.c 2009-01-07 15:09:40.000000000 +0100 +@@ -179,6 +179,12 @@ + priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; + priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); + ++ /* Init MACCFG2 */ ++ priv->regs->maccfg2 = MACCFG2_INIT_SETTINGS; ++ ++ /* Init ECNTRL */ ++ priv->regs->ecntrl = ECNTRL_INIT_SETTINGS; ++ + #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ + && !defined(BITBANGMII) + miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write); +@@ -204,7 +210,7 @@ + /* Make sure the controller is stopped */ + tsec_halt(dev); + +- /* Init MACCFG2. Defaults to GMII */ ++ /* Init MACCFG2 */ + regs->maccfg2 = MACCFG2_INIT_SETTINGS; + + /* Init ECNTRL */ +@@ -868,7 +874,11 @@ + if(priv->phyinfo) + phy_run_commands(priv, priv->phyinfo->startup); + ++#ifdef CONFIG_TSEC_NON_MANAGEABLE_PHY ++ priv->link = 1; ++#else + adjust_link(dev); ++#endif + + /* Enable Transmit and Receive */ + regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN); +@@ -1318,6 +1328,21 @@ + } + }; + ++/* a non-manageable PHY interface */ ++struct phy_info phy_info_null = { ++ 0, ++ "Non-manageable PHY", ++ 0, ++ (struct phy_cmd[]) { /* config */ ++ {miim_end,} ++ }, ++ (struct phy_cmd[]) { /* startup */ ++ {miim_end,} ++ }, ++ (struct phy_cmd[]) { /* shutdown */ ++ {miim_end,} ++ } ++}; + + uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) + { +@@ -1473,6 +1498,10 @@ + */ + struct phy_info *get_phy_info(struct eth_device *dev) + { ++#ifdef CONFIG_TSEC_NON_MANAGEABLE_PHY ++ debug("%s: Using non-manageable PHY interface\n", dev->name); ++ return &phy_info_null; ++#else + struct tsec_private *priv = (struct tsec_private *)dev->priv; + uint phy_reg, phy_ID; + int i; +@@ -1503,6 +1532,7 @@ + } + + return theInfo; ++#endif // CONFIG_TSEC_NON_MANAGEABLE_PHY + } + + /* Execute the given series of commands on the given device's +Index: u-boot-1.3.2/drivers/net/tsec.h +=================================================================== +--- u-boot-1.3.2.orig/drivers/net/tsec.h 2008-03-09 16:20:02.000000000 +0100 ++++ u-boot-1.3.2/drivers/net/tsec.h 2009-01-07 15:09:40.000000000 +0100 +@@ -56,11 +56,11 @@ + #define MACCFG1_SYNCD_TX_EN 0x00000002 + #define MACCFG1_TX_EN 0x00000001 + +-#define MACCFG2_INIT_SETTINGS 0x00007205 + #define MACCFG2_FULL_DUPLEX 0x00000001 + #define MACCFG2_IF 0x00000300 + #define MACCFG2_GMII 0x00000200 + #define MACCFG2_MII 0x00000100 ++#define MACCFG2_INIT_SETTINGS (0x00007005 | MACCFG2_MII) + + #define ECNTRL_INIT_SETTINGS 0x00001000 + #define ECNTRL_TBI_MODE 0x00000020 +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h 2009-01-07 15:09:39.000000000 +0100 ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h 2009-01-07 15:11:17.000000000 +0100 +@@ -246,8 +246,8 @@ + #define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +-#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +-#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) ++#define CFG_NS16550_COM1 (CFG_IMMR+0x4600) ++#define CFG_NS16550_COM2 (CFG_IMMR+0x4500) + + /* Use the HUSH parser */ + #define CFG_HUSH_PARSER +@@ -302,6 +302,7 @@ + * TSEC configuration + */ + #define CONFIG_TSEC_ENET /* TSEC ethernet support */ ++#define CONFIG_TSEC_NON_MANAGEABLE_PHY /* Non-manageable PHY interface */ + + #ifndef CONFIG_NET_MULTI + #define CONFIG_NET_MULTI 1 +@@ -313,12 +314,12 @@ + #define CONFIG_TSEC1_NAME "TSEC0" + #define CONFIG_TSEC2 1 + #define CONFIG_TSEC2_NAME "TSEC1" +-#define TSEC1_PHY_ADDR 0x1c +-#define TSEC2_PHY_ADDR 4 +-#define TSEC1_FLAGS TSEC_GIGABIT +-#define TSEC2_FLAGS TSEC_GIGABIT ++#define TSEC1_PHY_ADDR 0 //0x1c ++#define TSEC2_PHY_ADDR 0 //4 ++#define TSEC1_FLAGS TSEC_REDUCED //TSEC_GIGABIT ++#define TSEC2_FLAGS TSEC_REDUCED //TSEC_GIGABIT + #define TSEC1_PHYIDX 0 +-#define TSEC2_PHYIDX 0 ++#define TSEC2_PHYIDX 1 //0 + + /* Options are: TSEC[0-1] */ + #define CONFIG_ETHPRIME "TSEC1" +@@ -472,8 +473,8 @@ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ +- HRCWH_TSEC1M_IN_RGMII |\ +- HRCWH_TSEC2M_IN_RGMII |\ ++ HRCWH_TSEC1M_IN_MII |\ ++ HRCWH_TSEC2M_IN_MII |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) + +@@ -482,7 +483,7 @@ + #define CFG_WATCHDOG_VALUE 0xFFFF + + /* System IO Config */ +-#define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ ++#define CFG_SICRH 0 //(SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ + #define CFG_SICRL (SICRL_USBDR |SICRL_LBC) /* Enable Internal USB Phy */ + + #define CFG_HID0_INIT 0x000000000 diff --git a/recipes/u-boot/u-boot-1.3.2/boc01/009-081212-EXIO.patch b/recipes/u-boot/u-boot-1.3.2/boc01/009-081212-EXIO.patch new file mode 100644 index 0000000000..9ea0b0594f --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/boc01/009-081212-EXIO.patch @@ -0,0 +1,139 @@ +Index: u-boot-1.3.2/board/freescale/mpc8313erdb/mpc8313erdb.c +=================================================================== +--- u-boot-1.3.2.orig/board/freescale/mpc8313erdb/mpc8313erdb.c ++++ u-boot-1.3.2/board/freescale/mpc8313erdb/mpc8313erdb.c +@@ -49,6 +49,7 @@ int misc_init_f(void) + { + uchar value; + uchar i; ++ ulong addr; + + #ifdef PRE_INIT_GPIO + value=PRE_INIT_GPIO; +@@ -84,6 +85,18 @@ int misc_init_f(void) + puts("GPIO: ready\n"); + #endif + ++#ifdef PRE_INIT_EXIO ++ addr = ADDR_EXIO; ++ *((u_char *)addr) = PRE_INIT_EXIO; ++ udelay(1000); ++#endif ++ ++#ifdef INIT_EXIO ++ addr = ADDR_EXIO; ++ *((u_char *)addr) = INIT_EXIO; ++ puts("EXIO: ready\n"); ++#endif ++ + return 0; + } + +Index: u-boot-1.3.2/common/cmd_exio.c +=================================================================== +--- /dev/null ++++ u-boot-1.3.2/common/cmd_exio.c +@@ -0,0 +1,67 @@ ++/* ++ * (C) Copyright 2008 ++ * Alexandre Coffignal, CenoSYS, alexandre.coffignal@cenosys.com ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++ ++#include <common.h> ++#include <config.h> ++#include <command.h> ++ ++extern void init_exio(char value); ++ ++int do_exio (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) ++{ ++ unsigned char ucExio; ++ ulong addr; ++ if (argc < 2) ++ goto usage; ++ ++ if (!strncmp(argv[1], "get", 3)) ++ { ++ addr = ADDR_EXIO; ++ ucExio=*((u_char *)addr); ++ printf("%s = 0x%02x\n",argv[0],ucExio); ++ } ++ else ++ { ++ ucExio = simple_strtoul (argv[1], NULL, 10); ++ ++ addr = ADDR_EXIO; ++ *((u_char *)addr) = ucExio; ++ ++ printf("%s 0x%2x\n",argv[0],ucExio); ++ } ++ return 0; ++ ++usage : ++ printf ("Usage:\n%s\n", cmdtp->usage); ++ return 1; ++} /* do_gpio() */ ++ ++/***************************************************/ ++ ++U_BOOT_CMD( ++ exio, 2, 1, do_exio, ++ "exio - Extender io Output\n", ++ " - Set or clear extender io Output.\n" ++ "exio value - \n" ++); +Index: u-boot-1.3.2/common/Makefile +=================================================================== +--- u-boot-1.3.2.orig/common/Makefile ++++ u-boot-1.3.2/common/Makefile +@@ -52,6 +52,7 @@ COBJS-$(CONFIG_CMD_DOC) += cmd_doc.o + COBJS-$(CONFIG_CMD_DTT) += cmd_dtt.o + COBJS-$(CONFIG_CMD_CAPSENSE) += cmd_capsense.o + COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o ++COBJS-$(CONFIG_CMD_EXIO) += cmd_exio.o + COBJS-y += cmd_eeprom.o + COBJS-$(CONFIG_CMD_ELF) += cmd_elf.o + COBJS-$(CONFIG_CMD_EXT2) += cmd_ext2.o +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h +@@ -374,6 +374,7 @@ + #define CONFIG_CMD_SPI + #define CONFIG_CMD_DTT + #define CONFIG_CMD_GPIO ++#define CONFIG_CMD_EXIO + + #if defined(CFG_RAMBOOT) + #undef CONFIG_CMD_ENV +@@ -415,6 +416,11 @@ + #define CONFIG_CAPSENSE_LEDS {0x02,0x0F} // port 0-{1} port 1-{0,1,2,3} + #define CONFIG_CAPSENSE_SENSORS {0x1D,0x10} // port 0-{0,2,3,4} port 1-{4} + ++/* Extender io */ ++#define ADDR_EXIO 0xFA000000 ++#define PRE_INIT_EXIO 0x18 ++#define INIT_EXIO 0x58 ++ + /* + * Miscellaneous configurable options + */ diff --git a/recipes/u-boot/u-boot-1.3.2/boc01/010-081212-LCD.patch b/recipes/u-boot/u-boot-1.3.2/boc01/010-081212-LCD.patch new file mode 100644 index 0000000000..33a0c761f9 --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/boc01/010-081212-LCD.patch @@ -0,0 +1,541 @@ +Index: u-boot-1.3.2/common/Bollore.xbm +=================================================================== +--- /dev/null ++++ u-boot-1.3.2/common/Bollore.xbm +@@ -0,0 +1,174 @@ ++#define Bollore_width 128 ++#define Bollore_height 128 ++static unsigned char Bollore_bits[] = { ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, ++ 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0x00, 0x70, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xf8, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, 0xf8, 0x01, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0xf8, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x80, 0x0f, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, 0x04, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x80, 0xe7, 0x01, 0x00, 0x00, 0x00, 0x86, 0x07, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0xfe, 0x0f, 0x00, 0x80, 0xe7, 0x01, 0x00, 0x00, ++ 0x00, 0x07, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0x3f, 0x00, 0x00, ++ 0xc7, 0x01, 0x00, 0x00, 0x80, 0x03, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x78, 0x38, 0x00, 0x00, 0xc7, 0x01, 0x00, 0x00, 0x80, 0x01, 0x1c, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x78, 0x78, 0x00, 0x00, 0xc7, 0x01, 0x00, 0x00, ++ 0xc0, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x70, 0xc0, 0x01, ++ 0xc7, 0x01, 0x07, 0x00, 0x81, 0x03, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x78, 0x78, 0xf8, 0x07, 0xc7, 0xc1, 0x3f, 0xd8, 0xe3, 0x0f, 0x70, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x78, 0x3c, 0x1c, 0x0e, 0xc7, 0x71, 0x70, 0xfe, ++ 0x33, 0x1c, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 0x0e, 0x1c, ++ 0xc7, 0x71, 0x70, 0x3c, 0x18, 0x38, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xf8, 0x3f, 0x0e, 0x18, 0xc7, 0x39, 0xe0, 0x1c, 0xf8, 0x3f, 0xe0, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x78, 0x70, 0x06, 0x38, 0xc7, 0x39, 0xe0, 0x1c, ++ 0xfc, 0x3f, 0xc0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x78, 0xf0, 0x06, 0x38, ++ 0xc7, 0x39, 0xe0, 0x1c, 0x1c, 0x00, 0xc0, 0x01, 0x00, 0x00, 0x00, 0x00, ++ 0x78, 0xe0, 0x06, 0x38, 0xc7, 0x39, 0xe0, 0x1c, 0x1c, 0x00, 0x80, 0x03, ++ 0x00, 0x00, 0x00, 0x00, 0x78, 0xe0, 0x06, 0x38, 0xc7, 0x39, 0xe0, 0x1c, ++ 0x1c, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x78, 0xf0, 0x0e, 0x18, ++ 0xc7, 0x79, 0xe0, 0x1c, 0x38, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, ++ 0x78, 0x70, 0x0e, 0x1c, 0xc7, 0x71, 0x70, 0x1c, 0x78, 0x30, 0x00, 0x07, ++ 0x00, 0x00, 0x00, 0x00, 0xfc, 0x3e, 0x1c, 0x8e, 0xe7, 0xe1, 0x38, 0x3c, ++ 0xf0, 0x1f, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x1f, 0xf0, 0xc7, ++ 0xff, 0xc3, 0x1f, 0x7e, 0xe0, 0x0f, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, ++ 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0xc0, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, ++ 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0xf8, 0x00, 0x1f, 0xc0, 0x00, 0x3f, 0x00, 0x7e, 0x00, ++ 0x7e, 0x00, 0x7d, 0x3e, 0x00, 0x00, 0x00, 0xfc, 0xc0, 0x7f, 0xc0, 0x80, ++ 0x7f, 0x80, 0xff, 0x00, 0xff, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x30, ++ 0xe0, 0xf1, 0xc0, 0xc0, 0xe1, 0x80, 0xc3, 0x81, 0xc3, 0x81, 0xc7, 0xe3, ++ 0x00, 0x00, 0x00, 0x30, 0xe0, 0xe0, 0xc0, 0xc0, 0xc0, 0xc0, 0x81, 0xc1, ++ 0x81, 0x81, 0xc3, 0xe1, 0x00, 0x00, 0x00, 0x30, 0xe0, 0xff, 0xc0, 0xe0, ++ 0xff, 0xc1, 0x00, 0xc0, 0x81, 0x83, 0xc3, 0xe1, 0x00, 0x00, 0x00, 0x30, ++ 0xe0, 0xff, 0xc0, 0xe0, 0xff, 0xe1, 0x00, 0xc0, 0x01, 0x83, 0xc3, 0xe1, ++ 0x00, 0x00, 0x00, 0x30, 0x60, 0x00, 0xc0, 0xc0, 0x00, 0xc0, 0x00, 0xc0, ++ 0x81, 0x83, 0xc3, 0xe1, 0x00, 0x00, 0x00, 0x30, 0xe0, 0xe0, 0xc0, 0xc0, ++ 0xc0, 0xc0, 0x81, 0x81, 0x81, 0x81, 0xc3, 0xe1, 0x00, 0x00, 0x00, 0x30, ++ 0xc0, 0xff, 0xc0, 0xc0, 0xff, 0x80, 0xff, 0x81, 0xff, 0x81, 0xc3, 0xe1, ++ 0x00, 0x00, 0x00, 0x30, 0x80, 0x7f, 0xc0, 0x80, 0x7f, 0x00, 0xff, 0x00, ++ 0xff, 0x80, 0xc3, 0xe1, 0x00, 0x00, 0x00, 0x20, 0x00, 0x1f, 0x40, 0x00, ++ 0x1e, 0x00, 0x3c, 0x00, 0x3c, 0x00, 0x81, 0xc0, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; +Index: u-boot-1.3.2/common/cmd_lcd.c +=================================================================== +--- /dev/null ++++ u-boot-1.3.2/common/cmd_lcd.c +@@ -0,0 +1,237 @@ ++/* ++ * (C) Copyright 2008 ++ * Alexandre Coffignal, CénoSYS, alexandre.coffignal@cenosys.com ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++#include <common.h> ++#include <config.h> ++#include <command.h> ++#include <NT7506.h> ++//Splash screen in xbm format ++#include "Bollore.xbm" ++ ++ ++#define DELAY 1 ++#define AEL 0x0F ++ ++ ++static void iowrite16(unsigned short value) ++{ ++ ulong addr; ++ unsigned short send; ++ send=value>>8; ++ send+=(value&0xFF)<<8; ++ addr = CFG_LCD_BASE; ++ ++ *((unsigned short *)addr)=send; ++} ++ ++static void NT7506_writeb_ctl(unsigned char value) ++{ ++ unsigned short svalue; ++ svalue=value<<8 | LCD_RSN | LCD_RST | LCD_ERDN | LCD_BCKLIGH; ++ iowrite16(svalue); ++ udelay(DELAY); ++ svalue=value<<8 | LCD_RSN | LCD_RST | LCD_ERD | LCD_BCKLIGH; ++ iowrite16(svalue); ++ udelay(DELAY); ++ ++} ++ ++static void NT7506_writeb_data(unsigned char value) ++{ ++ unsigned short svalue; ++ svalue=value<<8|LCD_RS |LCD_RST | LCD_ERD | LCD_BCKLIGH ; ++ iowrite16(svalue); ++ udelay(DELAY); ++ svalue=value<<8|LCD_RS |LCD_RST | LCD_ERDN | LCD_BCKLIGH; ++ iowrite16(svalue); ++ udelay(DELAY); ++} ++ ++static void NT7506_set_yaddr(unsigned char y) ++{ ++ NT7506_writeb_ctl(NT_PAGE_ADDR+y); ++} ++ ++static void NT7506_set_xaddr(unsigned char x) ++{ ++ NT7506_writeb_ctl(NT_COL_MSB | (x >> 0x04) ); //Send high nibble ++ NT7506_writeb_ctl(NT_COL_LSB | (x & 0x0F) ); //Send low nibble ++} ++ ++static void ImageRota(unsigned char *src, unsigned char *dest, int w ,int h) ++{ ++ int i,j,bit,IndexRead; ++ char mask=0; ++ char bitvalue; ++ for(i=0;i<h/8;i++) ++ { ++ for(j=0;j<(w);j++) ++ { ++ ++ for(bit=0,IndexRead=(i*128)+(j/8);bit<8;bit++,IndexRead+=(w/8)) ++ { ++ mask=(1<<((j%8))); ++ bitvalue=(src[IndexRead]&mask)>>((j%8)); ++ dest[j+i*w]+=(bitvalue<<bit); ++ } ++ } ++ } ++} ++ ++ ++static void NT7506_print_splash(unsigned char *picture, char width, char height) ++{ ++ int i; ++ unsigned char imagerota[2048]; ++ int indeximage=0; ++ ++ int x,y,xfb,yfb; ++ char src[2048]; ++ if(width>128) ++ width=128; ++ if(height>128) ++ height=128; ++ ++ for(i=0;i<2048;i++) ++ imagerota[i]=0; ++ ++ ImageRota(picture,imagerota, width ,128); ++ ++ for(yfb=0;yfb<(height/8);yfb++) ++ { ++ for(xfb=0;xfb<width;xfb++) ++ { ++ src[xfb*16+yfb]=imagerota[indeximage++] ; ++ } ++ } ++ ++ for (y = 0; y < (height/8); y++) ++ { ++ NT7506_set_yaddr(y); ++ NT7506_set_xaddr(0); ++ ++ for (x = 0; x < width; x++) ++ { ++ NT7506_writeb_data(src[(x*(height/8))+y]); ++ NT7506_writeb_data(0x00); ++ } ++ NT7506_writeb_data((unsigned char)0); ++ } ++} ++ ++static void NT7506_init_lcd(char ael) ++{ ++ /* this resets the lcd*/ ++ iowrite16(LCD_RSTN | LCD_ERD | LCD_BCKLIGH); ++ udelay(100); ++ iowrite16(LCD_RST| LCD_ERD | LCD_BCKLIGH); ++ udelay(200); ++ /* Soft reset*/ ++ NT7506_writeb_ctl(NT_RESET); ++ /* Disable ICON display*/ ++ NT7506_writeb_ctl(NT_ICON|OFF); ++ /* Sets the duty ratio 1/128*/ ++ NT7506_writeb_ctl(NT_DUTY); NT7506_writeb_ctl(DUTY_1_128); ++ /* Sets reverse direction between RAM column address and segment driver*/ ++ NT7506_writeb_ctl(NT_ADC_REV); ++ NT7506_writeb_ctl(NT_SHL_NOR); ++ /* Enales the built in Oscillator circuit.*/ ++ NT7506_writeb_ctl(NT_OSC); ++ /* Set Initial row to 0*/ ++ NT7506_writeb_ctl(NT_COM0); NT7506_writeb_ctl(0); ++ /* Sets DC-DC*/ ++ NT7506_writeb_ctl(NT_DCDC|TIME6); ++ /* Selects resistance ratio of the internal resistor*/ ++ NT7506_writeb_ctl(NT_REG_RES|RES_7_2); ++ /* set Reference Voltage mode*/ ++ NT7506_writeb_ctl(NT_ELEC_VOL); NT7506_writeb_ctl(ael); ++ /* Selects LCD bias ratio*/ ++ NT7506_writeb_ctl(NT_BIAS|BIAS_1_11); ++ ++ NT7506_writeb_ctl(NT_DATA_DIR); NT7506_writeb_ctl(0); ++ NT7506_writeb_ctl(NT_FRC_PWM|PWM15); ++ /* Select power circuit functions */ ++ NT7506_writeb_ctl(NT_POWER|VC); ++ udelay(5000); ++ NT7506_writeb_ctl(NT_POWER|VC|VR); ++ udelay(5000); ++ NT7506_writeb_ctl(NT_POWER|VC|VR|VF); ++ udelay(5000); ++ /* Reverses the display status on LCD panel */ ++ NT7506_writeb_ctl(NT_REV_DISP|OFF); ++ /* Forces the whole LCD points to be turned on regardless of the contents of the display data RAM*/ ++ NT7506_writeb_ctl(NT_DISP|ON); ++ /* Set Initial Start Line Address */ ++ NT7506_writeb_ctl(NT_START_LINE); NT7506_writeb_ctl(0x00); ++} ++ ++ ++/**************************************************/ ++int do_lcd(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) ++{ ++ char lcd_ael=AEL; ++ if(argc>1) ++ lcd_ael = simple_strtoul (argv[1], NULL, 10); ++ ++ if(lcd_ael>63) ++ lcd_ael=0x63; ++ ++ NT7506_init_lcd(lcd_ael); ++ NT7506_print_splash(Bollore_bits,Bollore_width,Bollore_height); ++ ++ return 0; ++} ++ ++U_BOOT_CMD( ++ lcd, 2, 1, do_lcd, ++ "lcd - Display splash screen on LCD\n", ++ "lcd\n" ++); ++ ++int do_backlight(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) ++{ ++ if (!strncmp(argv[1], "on", 7)) ++ { ++ iowrite16(LCD_RSN | LCD_RST | LCD_ERD | LCD_BCKLIGH); ++ } ++ else ++ { ++ if (!strncmp(argv[1], "off", 7)) ++ { ++ iowrite16(LCD_RSN | LCD_RST | LCD_ERD | LCD_BCKLIGHN); ++ } ++ else ++ { ++ printf ("Usage:\n%s\n", cmdtp->usage); ++ return 1; ++ } ++ } ++ return 0; ++} ++ ++U_BOOT_CMD( ++ backlight, 2, 1, do_backlight, ++ "backlight - Switch LCD backlight on/off\n", ++ "backlight on|off\n" ++); ++ +Index: u-boot-1.3.2/common/Makefile +=================================================================== +--- u-boot-1.3.2.orig/common/Makefile ++++ u-boot-1.3.2/common/Makefile +@@ -94,6 +94,7 @@ COBJS-$(CONFIG_CMD_STRINGS) += cmd_strin + COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o + COBJS-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o + COBJS-$(CONFIG_CMD_USB) += cmd_usb.o ++COBJS-$(CONFIG_CMD_LCD) +=cmd_lcd.o + COBJS-y += cmd_vfd.o + COBJS-y += command.o + COBJS-y += console.o +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h +@@ -215,13 +215,13 @@ + #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE + #define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ + +-#define CFG_VSC7385_BASE 0xF0000000 ++#define CFG_LCD_BASE 0xF0000000 + +-#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ +-#define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ +-#define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ +-#define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */ +-#define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ ++//#define CONFIG_LCD /* LCD support */ ++#define CFG_BR2_PRELIM 0xf0001001 /* LCD Base address 16bits */ ++#define CFG_OR2_PRELIM 0xFFFF8FF7 /* LCD, 32kB bytes*/ ++#define CFG_LBLAWBAR2_PRELIM CFG_LCD_BASE/* Access window base at lcd base */ ++#define CFG_LBLAWAR2_PRELIM 0x8000000E /* Access window size 32k */ + + /* local bus read write buffer mapping */ + #define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ +@@ -375,6 +375,7 @@ + #define CONFIG_CMD_DTT + #define CONFIG_CMD_GPIO + #define CONFIG_CMD_EXIO ++#define CONFIG_CMD_LCD + + #if defined(CFG_RAMBOOT) + #undef CONFIG_CMD_ENV +Index: u-boot-1.3.2/include/NT7506.h +=================================================================== +--- /dev/null ++++ u-boot-1.3.2/include/NT7506.h +@@ -0,0 +1,71 @@ ++/* ++ * (C) Copyright 2008 ++ * Alexandre Coffignal, CénoSYS, alexandre.coffignal@cenosys.com ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++ ++ ++ ++//NT7506 Instructions ++#define NT_ICON 0xA2 ++#define NT_PAGE_ADDR 0xB0 ++#define NT_COL_MSB 0x10 ++#define NT_COL_LSB 0x00 ++#define NT_DISP 0xAE ++#define NT_START_LINE 0x40 ++#define NT_COM0 0x44 ++#define NT_DUTY 0x48 ++#define DUTY_1_128 0x80 ++#define NT_REV_DISP 0xA6 ++#define NT_POWER 0x28 ++#define VC 0x04 ++#define VR 0x02 ++#define VF 0x01 ++#define NT_DCDC 0x64 ++#define TIME6 0x03 ++#define NT_REG_RES 0x20 ++#define RES_7_2 0x07 ++#define NT_ELEC_VOL 0x81 ++#define NT_BIAS 0x50 ++#define BIAS_1_11 0x06 ++#define NT_ADC_NOR 0xA0 ++#define NT_ADC_REV 0xA1 ++#define NT_SHL_NOR 0xC0 ++#define NT_SHL_REV 0xC8 ++#define NT_OSC 0xAB ++#define NT_RESET 0xE2 ++#define NT_DATA_DIR 0xe8 ++#define NT_FRC_PWM 0x90 ++#define PWM15 0x03 ++ ++#define ON 0x01 ++#define OFF 0x00 ++ ++ ++//NT7506 Hardware ++#define LCD_RST 0x08 ++#define LCD_RSTN 0x00 ++#define LCD_BCKLIGH 0x04 ++#define LCD_BCKLIGHN 0x00 ++#define LCD_RS 0x02 ++#define LCD_RSN 0x00 ++#define LCD_ERD 0x01 ++#define LCD_ERDN 0x00 diff --git a/recipes/u-boot/u-boot-1.3.2/boc01/011-081211-CMD_TEST.patch b/recipes/u-boot/u-boot-1.3.2/boc01/011-081211-CMD_TEST.patch new file mode 100644 index 0000000000..f8a30faccf --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/boc01/011-081211-CMD_TEST.patch @@ -0,0 +1,454 @@ +Index: u-boot-1.3.2/common/Makefile +=================================================================== +--- u-boot-1.3.2.orig/common/Makefile ++++ u-boot-1.3.2/common/Makefile +@@ -95,6 +95,8 @@ COBJS-$(CONFIG_CMD_TERMINAL) += cmd_term + COBJS-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o + COBJS-$(CONFIG_CMD_USB) += cmd_usb.o + COBJS-$(CONFIG_CMD_LCD) +=cmd_lcd.o ++COBJS-$(CONFIG_CMD_FLTEST) += cmd_fltest.o ++COBJS-$(CONFIG_CMD_NANDTEST) += cmd_nandtest.o + COBJS-y += cmd_vfd.o + COBJS-y += command.o + COBJS-y += console.o +Index: u-boot-1.3.2/common/cmd_fltest.c +=================================================================== +--- /dev/null ++++ u-boot-1.3.2/common/cmd_fltest.c +@@ -0,0 +1,198 @@ ++/* ++ * (C) Copyright 2008 ++ * Alexandre Coffignal, CenoSYS, alexandre.coffignal@cenosys.com ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include <common.h> ++#include <command.h> ++ ++#define DEFAULT_RAM_ADDR 0x200000 ++static const ulong bitpattern[] = { ++ 0x11111111, /* single bit */ ++ 0x33333333, /* two adjacent bits */ ++ 0x77777777, /* three adjacent bits */ ++ 0x0F0F0F0F, /* four adjacent bits */ ++ 0x05050505, /* two non-adjacent bits */ ++ 0x15151515, /* three non-adjacent bits */ ++ 0x00550055, /* four non-adjacent bits */ ++ 0xaaaaaaaa, /* alternating 1/0 */ ++ }; ++ ++#define SECTOR_SIZE 0x10000 ++extern int cmd_get_data_size (char *arg, int default_size); ++extern flash_info_t flash_info[]; /* info for FLASH chips */ ++static void fill_ram(ulong pattern) ++{ ++ //fill ram with patern ++ ulong size=SECTOR_SIZE/4; ++ ulong ram, writeval; ++ char *s; ++ if ((s = getenv("loadaddr")) != NULL) ++ { ++ ram = simple_strtoul(s, NULL, 16); ++ } ++ else ++ { ++ ram=DEFAULT_RAM_ADDR; ++ } ++ writeval = pattern; ++ while (size-- > 0) ++ { ++ *((ulong *)ram) = (ulong )writeval; ++ ram += 4; ++ } ++ size=SECTOR_SIZE/4; ++ while (size-- > 0) ++ { ++ *((ulong *)ram) = (ulong )0xFFFFFFFF; ++ ram += 4; ++ } ++} ++ ++static int test_sector(ulong start,ulong patern) ++{ ++ int rc; ++ ulong addr1, addr2, count; ++ char *s; ++ if ((s = getenv("loadaddr")) != NULL) ++ { ++ addr1 = simple_strtoul(s, NULL, 16); ++ } ++ else ++ { ++ addr1=DEFAULT_RAM_ADDR; ++ } ++ rc = flash_write ((char *)addr1, start, SECTOR_SIZE); ++ if (rc != 0) ++ { ++ flash_perror (rc); ++ } ++ addr2 = start; ++ count=(SECTOR_SIZE/4); ++ while (count-- > 0) ++ { ++ ulong word1 = *(ulong *)addr1; ++ ulong word2 = *(ulong *)addr2; ++ if (word1 != word2) ++ { ++ printf("word at 0x%08lx (0x%08lx)!=patern (0x%08lx) count = %ld \n",addr2, word2,word1,count); ++ break; ++ } ++ addr1 += 4; ++ addr2 += 4; ++ } ++ return (0); ++} ++ ++int do_fltest ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++{ ++ ulong start, patern, nb_sector; ++ int i,prot=0; ++ flash_info_t *info = flash_info; ++ int idxtstptrn=0; ++ char forever=0; ++ ++ switch(argc) ++ { ++ case 1 : ++ start = 0; ++ nb_sector = info->sector_count-1; ++ patern=bitpattern[0]; ++ break; ++ case 2 : ++ start = 0; ++ nb_sector = info->sector_count-1; ++ patern=bitpattern[idxtstptrn]; ++ if (!strncmp(argv[1], "forever", 7)) ++ { ++ printf("Test nor flash forever\n"); ++ forever =1; ++ } ++ else ++ { ++ printf ("Usage:\n%s\n", cmdtp->usage); ++ return 1; ++ } ++ break; ++ case 4 : ++ start = simple_strtoul(argv[1], NULL, 16); ++ nb_sector = simple_strtoul(argv[2], NULL, 16); ++ patern = simple_strtoul(argv[3], NULL, 16); ++ break; ++ ++ default : ++ printf ("Usage:\n%s\n", cmdtp->usage); ++ return 1; ++ break; ++ } ++ ++ if((info->sector_count-1)<(start+nb_sector)) ++ { ++ printf ("Usage:\n%s\nnot enought sector on this flash\n", cmdtp->usage); ++ return 1; ++ } ++ ++ for (i = start; i < (start+nb_sector); ++i) ++ { ++ if (info->protect[i]) ++ { ++ prot++; ++ } ++ } ++ if (prot) ++ { ++ printf ("- Warning: %d protected sectors will not be tested!\n", prot); ++ } ++ do ++ { ++ printf("Test start at sector[%d]=%08lX end at sector[%d]=%08lX with patern=%08lX\n",start,info->start[start],start+nb_sector,info->start[start+nb_sector],patern); ++ //Erasing flash ++ flash_erase (info, start, start+nb_sector); ++ for (i = start; i < (start+nb_sector); ++i) ++ { ++ if(!info->protect[i]) ++ { ++ printf("\rtest at sector[%d]=%08lX with patern=%08lX\t",i,info->start[i],patern); ++ //fill ram with patern ++ fill_ram(patern); ++ //test flash sector ++ test_sector(info->start[i],patern); ++ } ++ } ++ printf("\r \n"); ++ //change patern if test forever ++ idxtstptrn++; ++ if(idxtstptrn>7) ++ { ++ idxtstptrn=0; ++ } ++ patern=bitpattern[idxtstptrn]; ++ prot=0; ++ }while(forever); ++ return 0; ++} ++U_BOOT_CMD( ++ fltest, 4, 1, do_fltest, ++ "fltest - flash memory test\n", ++ "fltest start end patern\n - test flash memory from sector start to sector end with partern patern \n" ++ "fltest\n - test entire flash memory\n" ++ "fltest forever\n - loop test entire flash memory\n" ++); +Index: u-boot-1.3.2/common/cmd_nandtest.c +=================================================================== +--- /dev/null ++++ u-boot-1.3.2/common/cmd_nandtest.c +@@ -0,0 +1,219 @@ ++/* ++ * (C) Copyright 2008 ++ * Alexandre Coffignal, CenoSYS, alexandre.coffignal@cenosys.com ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include <common.h> ++#include <command.h> ++#include <nand.h> ++#define DEFAULT_RAM_ADDR 0x200000 ++static const ulong bitpattern[] = { ++ 0x11111111, /* single bit */ ++ 0x33333333, /* two adjacent bits */ ++ 0x77777777, /* three adjacent bits */ ++ 0x0F0F0F0F, /* four adjacent bits */ ++ 0x05050505, /* two non-adjacent bits */ ++ 0x15151515, /* three non-adjacent bits */ ++ 0x00550055, /* four non-adjacent bits */ ++ 0xaaaaaaaa, /* alternating 1/0 */ ++ }; ++ ++static void fill_ram(nand_info_t *nand,ulong pattern) ++{ ++ //fill ram with patern ++ ulong size=nand->erasesize/4; ++ ulong ram, writeval; ++ char *s; ++ if ((s = getenv("loadaddr")) != NULL) ++ { ++ ram = simple_strtoul(s, NULL, 16); ++ } ++ else ++ { ++ ram=DEFAULT_RAM_ADDR; ++ } ++ ++ writeval = pattern; ++ ++ while (size-- > 0) ++ { ++ *((ulong *)ram) = (ulong )writeval; ++ ram += 4; ++ } ++ size=nand->erasesize/4; ++ while (size-- > 0) ++ { ++ *((ulong *)ram) = (ulong )0xFFFFFFFF; ++ ram += 4; ++ } ++} ++ ++static int test_sector(nand_info_t *nand,ulong start,ulong patern) ++{ ++ int rc; ++ ulong addr1, addr2, count; ++ char *s; ++ if ((s = getenv("loadaddr")) != NULL) ++ { ++ addr1 = simple_strtoul(s, NULL, 16); ++ } ++ else ++ { ++ addr1=DEFAULT_RAM_ADDR; ++ } ++ nand_write_options_t opts; ++ memset(&opts, 0, sizeof(opts)); ++ opts.buffer = (u_char*) addr1; ++ opts.length = nand->erasesize-sizeof(long); ++ opts.offset = start; ++ opts.pad = 1; ++ opts.blockalign = 1; ++ opts.quiet = 1; ++ rc = nand_write_opts(nand, &opts); ++ if (rc != 0) ++ { ++ printf(" %d bytes written:ERROR \n", nand->erasesize); ++ } ++ /* read */ ++ nand_read_options_t optsr; ++ memset(&optsr, 0, sizeof(optsr)); ++ optsr.buffer = (u_char*) (addr1+nand->erasesize); ++ optsr.length = nand->erasesize-sizeof(long); ++ optsr.offset = start; ++ optsr.quiet = 1; ++ rc = nand_read_opts(nand, &optsr); ++ if (rc != 0) ++ { ++ printf(" %d bytes read :ERROR \n", nand->erasesize); ++ } ++ addr2 = addr1+nand->erasesize; ++ count=((nand->erasesize-sizeof(long))/4); ++ while (count-- > 0) ++ { ++ ulong word1 = *(ulong *)addr1; ++ ulong word2 = *(ulong *)addr2; ++ if (word1 != word2) ++ { ++ printf("word at 0x%08lx (0x%08lx)!=patern (0x%08lx) count = %ld \n",addr2, word2,word1,count); ++ break; ++ } ++ addr1 += 4; ++ addr2 += 4; ++ } ++ return (0); ++} ++ ++int do_nandtest ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ++{ ++ ulong start, patern, nb_sector,sector; ++ int prot=0; ++ int idxtstptrn=0; ++ char forever=0; ++ int ret; ++ nand_info_t *nand; ++ nand = &nand_info[nand_curr_device]; ++ switch(argc) ++ { ++ case 1 : ++ start = 0; ++ nb_sector = (nand->size/nand->erasesize); ++ patern=bitpattern[0]; ++ break; ++ ++ case 2 : ++ start = 0; ++ nb_sector = (nand->size/nand->erasesize); ++ patern=bitpattern[idxtstptrn]; ++ if (!strncmp(argv[1], "forever", 7)) ++ { ++ printf("Test nor flash forever\n"); ++ forever =1; ++ } ++ else ++ { ++ printf ("Usage:\n%s\n", cmdtp->usage); ++ return 1; ++ } ++ break; ++ case 4 : ++ start = simple_strtoul(argv[1], NULL, 16); ++ nb_sector = simple_strtoul(argv[2], NULL, 16); ++ patern = simple_strtoul(argv[3], NULL, 16); ++ break; ++ ++ default : ++ printf ("Usage:\n%s\n", cmdtp->usage); ++ return 1; ++ break; ++ } ++ ++ ++ if((nb_sector+start) > (nand->size/nand->erasesize)) ++ { ++ printf ("Not enought sector on this nand flash\n"); ++ nb_sector=(nand->size/nand->erasesize)-start; ++ } ++ do ++ { ++ printf("Test start at sector[%d]=%08lX end at sector[%d]=%08lX with patern=%08lX\n",start,start*nand->erasesize ,start+nb_sector,(start+nb_sector)*nand->erasesize ,patern); ++ for (sector = start; sector < nb_sector; sector ++ ) ++ { ++ printk("\rtest sector %d end at %d with patern=%08lX\t",sector,nb_sector-1,patern); ++ //fill ram with patern ++ fill_ram(nand,patern); ++ //test flash sector ++ if(nand_block_isbad(nand, sector*nand->erasesize)) ++ { ++ printf("Bad block\n", nand); ++ } ++ else ++ { ++ //Erasing nand flash ++ nand_erase_options_t opts; ++ memset(&opts, 0, sizeof(opts)); ++ opts.offset = sector*nand->erasesize; ++ opts.length = nand->erasesize; ++ opts.quiet = 1; ++ ret = nand_erase_opts(nand, &opts); ++ //Test nand sector ++ test_sector(nand,sector*nand->erasesize,patern); ++ } ++ } ++ printf("\r \n"); ++ //change patern if test forever ++ idxtstptrn++; ++ if(idxtstptrn>7) ++ { ++ idxtstptrn=0; ++ } ++ patern=bitpattern[idxtstptrn]; ++ prot=0; ++ }while(forever); ++ return 0; ++} ++U_BOOT_CMD( ++ nandtest, 4, 1, do_nandtest, ++ "nandtest- nand flash memory test\n", ++ "nandtest start nb_sector patern\n - test nbsector sector(s) nand flash memory at sector start with partern patern \n" ++ "nandtest\n - test entire nand flash memory\n" ++ "nandtest forever\n - loop test entire nand flash memory\n" ++); ++ +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h +@@ -376,6 +376,9 @@ + #define CONFIG_CMD_GPIO + #define CONFIG_CMD_EXIO + #define CONFIG_CMD_LCD ++#define CONFIG_CMD_FLTEST ++#define CONFIG_CMD_NANDTEST ++ + + #if defined(CFG_RAMBOOT) + #undef CONFIG_CMD_ENV diff --git a/recipes/u-boot/u-boot-1.3.2/boc01/012-081209-BUG_SETENV.patch b/recipes/u-boot/u-boot-1.3.2/boc01/012-081209-BUG_SETENV.patch new file mode 100644 index 0000000000..7c5b2e2123 --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/boc01/012-081209-BUG_SETENV.patch @@ -0,0 +1,26 @@ +Index: u-boot-1.3.2/common/cmd_nvedit.c +=================================================================== +--- u-boot-1.3.2.orig/common/cmd_nvedit.c 2008-12-09 16:40:17.000000000 +0100 ++++ u-boot-1.3.2/common/cmd_nvedit.c 2008-12-09 16:40:49.000000000 +0100 +@@ -353,6 +353,21 @@ + return 0; + } + ++#if defined(CONFIG_HAS_ETH1) ++ if (strcmp(argv[1],"eth1addr") == 0) { ++ char *s = argv[2]; /* always use only one arg */ ++ char *e; ++ for (i=0; i<6; ++i) { ++ bd->bi_enet1addr[i] = s ? simple_strtoul(s, &e, 16) : 0; ++ if (s) s = (*e) ? e+1 : e; ++ } ++#ifdef CONFIG_NET_MULTI ++ eth_set_enetaddr(1, argv[2]); ++#endif ++ return 0; ++ } ++#endif ++ + if (strcmp(argv[1],"ipaddr") == 0) { + char *s = argv[2]; /* always use only one arg */ + char *e; diff --git a/recipes/u-boot/u-boot-1.3.2/boc01/013-090206-FIX_OOB_8BITS_LARGEPAGE_NAND.patch b/recipes/u-boot/u-boot-1.3.2/boc01/013-090206-FIX_OOB_8BITS_LARGEPAGE_NAND.patch new file mode 100644 index 0000000000..803b46d8e9 --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/boc01/013-090206-FIX_OOB_8BITS_LARGEPAGE_NAND.patch @@ -0,0 +1,29 @@ +Index: u-boot-1.3.2/drivers/mtd/nand/nand_bbt.c +=================================================================== +--- u-boot-1.3.2.orig/drivers/mtd/nand/nand_bbt.c 2008-03-09 16:20:02.000000000 +0100 ++++ u-boot-1.3.2/drivers/mtd/nand/nand_bbt.c 2009-02-06 14:50:35.000000000 +0100 +@@ -914,10 +914,11 @@ + .pattern = scan_ff_pattern + }; + ++//Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048. + static struct nand_bbt_descr largepage_memorybased = { + .options = 0, + .offs = 0, +- .len = 2, ++ .len = 1, + .pattern = scan_ff_pattern + }; + +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h 2009-02-06 15:42:07.000000000 +0100 ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h 2009-02-06 15:42:45.000000000 +0100 +@@ -205,6 +205,7 @@ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V ) /* valid */ + #define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ ++ | OR_FCM_PGS \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ diff --git a/recipes/u-boot/u-boot-1.3.2/boc01/014-081211-BOOT_RESCUE.patch b/recipes/u-boot/u-boot-1.3.2/boc01/014-081211-BOOT_RESCUE.patch new file mode 100644 index 0000000000..d2ebdef772 --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/boc01/014-081211-BOOT_RESCUE.patch @@ -0,0 +1,48 @@ +Index: u-boot-1.3.2/common/main.c +=================================================================== +--- u-boot-1.3.2.orig/common/main.c ++++ u-boot-1.3.2/common/main.c +@@ -39,6 +39,7 @@ + #endif + + #include <post.h> ++#include <gpio.h> + + #ifdef CONFIG_SILENT_CONSOLE + DECLARE_GLOBAL_DATA_PTR; +@@ -377,6 +378,15 @@ void main_loop (void) + } + else + #endif /* CONFIG_BOOTCOUNT_LIMIT */ ++#ifdef CONFIG_ENV_BOOTRESCUE ++ if ( gpio_get(GPIO_RED_BUTTON) ) { ++ printf ("Red button pressed: booting in rescue mode.\n"); ++ s = getenv (CONFIG_ENV_BOOTRESCUE); ++ if ( !s ) ++ printf ("Warning: environment variable '" CONFIG_ENV_BOOTRESCUE "' not set. Giving up rescue boot.\n"); ++ } ++ else ++#endif + s = getenv ("bootcmd"); + + debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>"); +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h +@@ -406,6 +406,7 @@ + #define PRE_INIT_GPIO 0x28 + #define INIT_GPIO 0x08 + #define MAX_GPIO_OUT 7 ++#define GPIO_RED_BUTTON 7 + + /* Digital Thermometer and Thermostat */ + #define CONFIG_DTT_LM73 1 +@@ -559,6 +560,7 @@ + * Environment Configuration + */ + #define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_BOOTRESCUE "bootrescue" + + #define CONFIG_ETHADDR 00:E0:0C:00:95:01 + #define CONFIG_HAS_ETH1 diff --git a/recipes/u-boot/u-boot-1.3.2/boc01/015-090205-EMC.patch b/recipes/u-boot/u-boot-1.3.2/boc01/015-090205-EMC.patch new file mode 100644 index 0000000000..afc43c47ed --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/boc01/015-090205-EMC.patch @@ -0,0 +1,31 @@ +Index: u-boot-1.3.2/board/freescale/mpc8313erdb/mpc8313erdb.c +=================================================================== +--- u-boot-1.3.2.orig/board/freescale/mpc8313erdb/mpc8313erdb.c ++++ u-boot-1.3.2/board/freescale/mpc8313erdb/mpc8313erdb.c +@@ -135,8 +135,9 @@ void pci_init_board(void) + struct pci_region *reg[] = { pci_regions }; + int warmboot; + +- /* Enable all 3 PCI_CLK_OUTPUTs. */ +- clk->occr |= 0xe0000000; ++ /* Enable PCI_CLK_OUTPUT 1 only. ++ Disable others for better EMC footprint. */ ++ clk->occr = (clk->occr & 0x1fffffff) | OCCR_PCICOE1; + + /* + * Configure PCI Local Access Windows +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h +@@ -133,8 +133,8 @@ + #define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + /*0x02000000*/ + #define CFG_DDRCDR_VALUE ( DDRCDR_EN \ +- | DDRCDR_PZ_NOMZ \ +- | DDRCDR_NZ_NOMZ \ ++ | DDRCDR_PZ_MAXZ \ ++ | DDRCDR_NZ_MAXZ \ + | DDRCDR_M_ODR ) + + /* diff --git a/recipes/u-boot/u-boot-1.3.2/boc01/016-090209-PM.patch b/recipes/u-boot/u-boot-1.3.2/boc01/016-090209-PM.patch new file mode 100644 index 0000000000..940e4ae40c --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/boc01/016-090209-PM.patch @@ -0,0 +1,56 @@ +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h +@@ -60,7 +60,7 @@ + * to access the PMC registers, unless a JTAG debugger is + * connected, or some resistor modifications are made. + */ +-#define CFG_8313ERDB_BROKEN_PMC 1 ++#undef CFG_8313ERDB_BROKEN_PMC + + #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ + #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ +Index: u-boot-1.3.2/board/freescale/mpc8313erdb/mpc8313erdb.c +=================================================================== +--- u-boot-1.3.2.orig/board/freescale/mpc8313erdb/mpc8313erdb.c ++++ u-boot-1.3.2/board/freescale/mpc8313erdb/mpc8313erdb.c +@@ -30,6 +30,7 @@ + #include <mpc83xx.h> + #include <spi.h> + #include <gpio.h> ++#include <asm/processor.h> + + DECLARE_GLOBAL_DATA_PTR; + +@@ -39,7 +40,29 @@ int board_early_init_f(void) + volatile immap_t *im = (immap_t *)CFG_IMMR; + + if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) +- gd->flags |= GD_FLG_SILENT; ++ { ++ volatile immap_t *immap = (immap_t *) CFG_IMMR; ++ ulong msr; ++ /* Interrupts and MMU off */ ++ __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); ++ ++ msr &= ~( MSR_EE | MSR_IR | MSR_DR); ++ __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); ++ ++ /* enable Reset Control Reg */ ++ immap->reset.rpr = 0x52535445; ++ __asm__ __volatile__ ("sync"); ++ __asm__ __volatile__ ("isync"); ++ ++ /* confirm Reset Control Reg is enabled */ ++ while(!((immap->reset.rcer) & RCER_CRE)); ++ ++ udelay(200); ++ ++ /* perform reset, only one bit */ ++ immap->reset.rcr = RCR_SWHR; ++ } ++ + #endif + + return 0; diff --git a/recipes/u-boot/u-boot-1.3.2/mpc8313e-rdb-autoboot.patch b/recipes/u-boot/u-boot-1.3.2/mpc8313e-rdb-autoboot.patch new file mode 100644 index 0000000000..f844f29b0b --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/mpc8313e-rdb-autoboot.patch @@ -0,0 +1,13 @@ +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h 2008-03-09 16:20:02.000000000 +0100 ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h 2008-09-12 18:08:16.000000000 +0200 +@@ -514,7 +514,7 @@ + #define CONFIG_FDTFILE mpc8313erdb.dtb + + #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ +-#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ ++#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + #define CONFIG_BAUDRATE 115200 + + #define XMK_STR(x) #x diff --git a/recipes/u-boot/u-boot-1.3.2/mpc8313e-rdb-eeprom.patch b/recipes/u-boot/u-boot-1.3.2/mpc8313e-rdb-eeprom.patch new file mode 100644 index 0000000000..51ff0f8ca0 --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/mpc8313e-rdb-eeprom.patch @@ -0,0 +1,21 @@ +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h 2008-11-21 14:55:25.000000000 +0100 ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h 2008-11-21 14:55:36.000000000 +0100 +@@ -263,6 +263,16 @@ + #define CFG_I2C_OFFSET 0x3000 + #define CFG_I2C2_OFFSET 0x3100 + ++/* ++ * EEPROM configuration ++ */ ++#define CONFIG_CMD_EEPROM ++#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ ++#define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C256*/ ++#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */ ++#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64-Byte Page Write Mode */ ++#define CFG_EEPROM_PAGE_WRITE_ENABLE ++ + /* TSEC */ + #define CFG_TSEC1_OFFSET 0x24000 + #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) diff --git a/recipes/u-boot/u-boot-1.3.2/mpc8313e-rdb-lm75.patch b/recipes/u-boot/u-boot-1.3.2/mpc8313e-rdb-lm75.patch new file mode 100644 index 0000000000..e76b95cf9f --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/mpc8313e-rdb-lm75.patch @@ -0,0 +1,23 @@ +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h 2008-11-21 15:00:28.000000000 +0100 ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h 2008-11-21 15:01:10.000000000 +0100 +@@ -364,6 +364,7 @@ + #define CONFIG_CMD_PING + #define CONFIG_CMD_DHCP + #define CONFIG_CMD_I2C ++#define CONFIG_CMD_DTT + #define CONFIG_CMD_MII + #define CONFIG_CMD_DATE + #define CONFIG_CMD_PCI +@@ -390,6 +391,10 @@ + #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + ++/* Digital Thermometer and Thermostat */ ++#define CONFIG_DTT_LM75 1 ++#define CONFIG_DTT_SENSORS { 0x48 } ++ + /* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is diff --git a/recipes/u-boot/u-boot-1.3.2/mpc8313e-rdb-mtdparts.patch b/recipes/u-boot/u-boot-1.3.2/mpc8313e-rdb-mtdparts.patch new file mode 100644 index 0000000000..e453d0145c --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/mpc8313e-rdb-mtdparts.patch @@ -0,0 +1,36 @@ +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h 2008-11-24 16:38:56.000000000 +0100 ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h 2008-11-24 16:38:58.000000000 +0100 +@@ -179,7 +179,7 @@ + #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + + /* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ +-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ ++#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ + #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + + /* +@@ -358,6 +358,7 @@ + #define CONFIG_CMD_DATE + #define CONFIG_CMD_PCI + #define CONFIG_CMD_NAND ++#define CONFIG_CMD_JFFS2 + + #if defined(CFG_RAMBOOT) + #undef CONFIG_CMD_ENV +@@ -366,6 +367,14 @@ + + #define CONFIG_CMDLINE_EDITING 1 + ++/* ++ * JFFS2 partitions (mtdparts command line support) ++ */ ++#define CONFIG_JFFS2_CMDLINE ++#define CONFIG_JFFS2_NAND ++#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand0" ++#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:384k(uboot),64k(env)" ++ + + /* + * Miscellaneous configurable options diff --git a/recipes/u-boot/u-boot-1.3.2/mpc8313e-rdb-nand.patch b/recipes/u-boot/u-boot-1.3.2/mpc8313e-rdb-nand.patch new file mode 100644 index 0000000000..513a3b1242 --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/mpc8313e-rdb-nand.patch @@ -0,0 +1,898 @@ +Index: u-boot-1.3.2/board/freescale/mpc8313erdb/Makefile +=================================================================== +--- u-boot-1.3.2.orig/board/freescale/mpc8313erdb/Makefile 2008-11-24 16:39:09.000000000 +0100 ++++ u-boot-1.3.2/board/freescale/mpc8313erdb/Makefile 2008-11-24 16:39:15.000000000 +0100 +@@ -25,7 +25,7 @@ + + LIB = $(obj)lib$(BOARD).a + +-COBJS := $(BOARD).o sdram.o ++COBJS := $(BOARD).o sdram.o nand.o + + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) + OBJS := $(addprefix $(obj),$(COBJS)) +Index: u-boot-1.3.2/board/freescale/mpc8313erdb/nand.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ u-boot-1.3.2/board/freescale/mpc8313erdb/nand.c 2008-11-24 16:39:15.000000000 +0100 +@@ -0,0 +1,868 @@ ++/* ++ * Copyright (C) Freescale Semiconductor, Inc. 2006. ++ * ++ * Initialized by Nick.Spence@freescale.com ++ * Wilson.Lo@freescale.com ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include <common.h> ++ ++#if defined(CONFIG_CMD_NAND) ++#if defined(CFG_NAND_LEGACY) ++ #error "U-Boot legacy NAND commands not supported." ++#else ++ ++#include <malloc.h> ++#include <asm/errno.h> ++#include <nand.h> ++ ++#undef CFG_FCM_DEBUG ++#define CFG_FCM_DEBUG_LVL 1 ++#ifdef CFG_FCM_DEBUG ++#define FCM_DEBUG(n, args...) \ ++ do { \ ++ if (n <= (CFG_FCM_DEBUG_LVL + 0)) \ ++ printf(args); \ ++ } while(0) ++#else /* CONFIG_FCM_DEBUG */ ++#define FCM_DEBUG(n, args...) do { } while(0) ++#endif ++ ++#define MIN(x, y) ((x < y) ? x : y) ++ ++#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ ++ ++#define FCM_TIMEOUT_USECS 100000 /* Maximum number of uSecs to wait for FCM */ ++ ++/* Private structure holding NAND Flash device specific information */ ++struct fcm_nand { ++ int bank; /* Chip select bank number */ ++ unsigned int base; /* Chip select base address */ ++ int pgs; /* NAND page size */ ++ int oobbuf; /* Pointer to OOB block */ ++ unsigned int page; /* Last page written to / read from */ ++ unsigned int fmr; /* FCM Flash Mode Register value */ ++ unsigned int mdr; /* UPM/FCM Data Register value */ ++ unsigned int use_mdr; /* Non zero if the MDR is to be set */ ++ u_char *addr; /* Address of assigned FCM buffer */ ++ unsigned int read_bytes; /* Number of bytes read during command */ ++ unsigned int index; /* Pointer to next byte to 'read' */ ++ unsigned int req_bytes; /* Number of bytes read if command ok */ ++ unsigned int req_index; /* New read index if command ok */ ++ unsigned int status; /* status read from LTESR after last op*/ ++}; ++ ++ ++/* These map to the positions used by the FCM hardware ECC generator */ ++ ++/* Small Page FLASH with FMR[ECCM] = 0 */ ++static struct nand_oobinfo fcm_oob_sp_eccm0 = { /* TODO */ ++ .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ ++ .eccbytes = 3, ++ .eccpos = {6, 7, 8}, ++ .oobfree = { {0, 5}, {9, 7} } ++}; ++ ++/* Small Page FLASH with FMR[ECCM] = 1 */ ++static struct nand_oobinfo fcm_oob_sp_eccm1 = { /* TODO */ ++ .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ ++ .eccbytes = 3, ++ .eccpos = {8, 9, 10}, ++ .oobfree = { {0, 5}, {6, 2}, {11, 5} } ++}; ++ ++/* Large Page FLASH with FMR[ECCM] = 0 */ ++static struct nand_oobinfo fcm_oob_lp_eccm0 = { ++ .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ ++ .eccbytes = 12, ++ .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56}, ++ .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} } ++}; ++ ++/* Large Page FLASH with FMR[ECCM] = 1 */ ++static struct nand_oobinfo fcm_oob_lp_eccm1 = { ++ .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ ++ .eccbytes = 12, ++ .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, ++ .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} } ++}; ++ ++/* ++ * execute FCM command and wait for it to complete ++ */ ++static int fcm_run_command(struct mtd_info *mtd) ++{ ++ volatile immap_t *im = (immap_t *) CFG_IMMR; ++ volatile lbus83xx_t *lbc= &im->lbus; ++ register struct nand_chip *this = mtd->priv; ++ struct fcm_nand *fcm = this->priv; ++ long long end_tick; ++ ++ /* Setup the FMR[OP] to execute without write protection */ ++ lbc->fmr = fcm->fmr | 3; ++ if (fcm->use_mdr) ++ lbc->mdr = fcm->mdr; ++ ++ FCM_DEBUG(5,"fcm_run_command: fmr= %08X fir= %08X fcr= %08X\n", ++ lbc->fmr, lbc->fir, lbc->fcr); ++ FCM_DEBUG(5,"fcm_run_command: fbar=%08X fpar=%08X fbcr=%08X bank=%d\n", ++ lbc->fbar, lbc->fpar, lbc->fbcr, fcm->bank); ++ ++ /* clear event registers */ ++ lbc->lteatr = 0; ++ lbc->ltesr |= (LTESR_FCT | LTESR_PAR | LTESR_CC); ++ ++ /* execute special operation */ ++ lbc->lsor = fcm->bank; ++ ++ /* wait for FCM complete flag or timeout */ ++ fcm->status = 0; ++ end_tick = usec2ticks(FCM_TIMEOUT_USECS) + get_ticks(); ++ ++ while (end_tick > get_ticks()) { ++ if (lbc->ltesr & LTESR_CC) { ++ fcm->status = lbc->ltesr & ++ (LTESR_FCT | LTESR_PAR | LTESR_CC); ++ break; ++ } ++ } ++ ++ /* store mdr value in case it was needed */ ++ if (fcm->use_mdr) ++ fcm->mdr = lbc->mdr; ++ ++ fcm->use_mdr = 0; ++ ++ FCM_DEBUG(5,"fcm_run_command: stat=%08X mdr= %08X fmr= %08X\n", ++ fcm->status, fcm->mdr, lbc->fmr); ++ ++ /* if the operation completed ok then set the read buffer pointers */ ++ if (fcm->status == LTESR_CC) { ++ fcm->read_bytes = fcm->req_bytes; ++ fcm->index = fcm->req_index; ++ return 0; ++ } ++ ++ return -1; ++} ++ ++/* ++ * Set up the FCM hardware block and page address fields, and the fcm ++ * structure addr field to point to the correct FCM buffer in memory ++ */ ++static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) ++{ ++ volatile immap_t *im = (immap_t *) CFG_IMMR; ++ volatile lbus83xx_t *lbc= &im->lbus; ++ register struct nand_chip *this = mtd->priv; ++ struct fcm_nand *fcm = this->priv; ++ int buf_num; ++ ++ fcm->page = page_addr; ++ ++ lbc->fbar = page_addr >> (this->phys_erase_shift - this->page_shift); ++ if (fcm->pgs) { ++ lbc->fpar = ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) | ++ ( oob ? FPAR_LP_MS : 0) | ++ column; ++ buf_num = (page_addr & 1) << 2; ++ } else { ++ lbc->fpar = ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) | ++ ( oob ? FPAR_SP_MS : 0) | ++ column; ++ buf_num = page_addr & 7; ++ } ++ fcm->addr = (unsigned char*)(fcm->base + (buf_num * 1024)); ++ ++ /* for OOB data point to the second half of the buffer */ ++ if (oob) { ++ fcm->addr += (fcm->pgs ? 2048 : 512); ++ } ++} ++ ++/* not required for FCM */ ++static void fcm_hwcontrol(struct mtd_info *mtdinfo, int cmd) ++{ ++ return; ++} ++ ++ ++/* ++ * FCM does not support 16 bit data busses ++ */ ++static u16 fcm_read_word(struct mtd_info *mtd) ++{ ++ printf("fcm_read_word: UNIMPLEMENTED.\n"); ++ return 0; ++} ++static void fcm_write_word(struct mtd_info *mtd, u16 word) ++{ ++ printf("fcm_write_word: UNIMPLEMENTED.\n"); ++} ++ ++/* ++ * Write buf to the FCM Controller Data Buffer ++ */ ++static void fcm_write_buf(struct mtd_info *mtd, const u_char *buf, int len) ++{ ++ register struct nand_chip *this = mtd->priv; ++ struct fcm_nand *fcm = this->priv; ++ ++ FCM_DEBUG(3,"fcm_write_buf: writing %d bytes starting with 0x%x" ++ " at %d.\n", len, *((unsigned long*) buf), fcm->index); ++ ++ /* If armed catch the address of the OOB buffer so that it can be */ ++ /* updated with the real signature after the program comletes */ ++ if (!fcm->oobbuf) ++ fcm->oobbuf = (int) buf; ++ ++ /* copy the data into the FCM hardware buffer and update the index */ ++ memcpy(&(fcm->addr[fcm->index]), buf, len); ++ fcm->index += len; ++ return; ++} ++ ++ ++/* ++ * FCM does not support individual writes. Instead these are either commands ++ * or data being written, both of which are handled through the cmdfunc ++ * handler. ++ */ ++static void fcm_write_byte(struct mtd_info *mtd, u_char byte) ++{ ++ printf("fcm_write_byte: UNIMPLEMENTED.\n"); ++} ++ ++/* ++ * read a byte from either the FCM hardware buffer if it has any data left ++ * otherwise issue a command to read a single byte. ++ */ ++static u_char fcm_read_byte(struct mtd_info *mtd) ++{ ++ volatile immap_t *im = (immap_t *) CFG_IMMR; ++ volatile lbus83xx_t *lbc= &im->lbus; ++ register struct nand_chip *this = mtd->priv; ++ struct fcm_nand *fcm = this->priv; ++ unsigned char byte; ++ ++ /* If there are still bytes in the FCM then use the next byte */ ++ if(fcm->index < fcm->read_bytes) { ++ byte = fcm->addr[(fcm->index)++]; ++ FCM_DEBUG(4,"fcm_read_byte: byte %u (%02X): %d of %d.\n", ++ byte, byte, fcm->index-1, fcm->read_bytes); ++ } else { ++ /* otherwise issue a command to read 1 byte */ ++ lbc->fir = (FIR_OP_RSW << FIR_OP0_SHIFT); ++ fcm->use_mdr = 1; ++ fcm->read_bytes = 0; ++ fcm->index = 0; ++ fcm->req_bytes = 0; ++ fcm->req_index = 0; ++ byte = fcm_run_command(mtd) ? ERR_BYTE : fcm->mdr & 0xff; ++ FCM_DEBUG(4,"fcm_read_byte: byte %u (%02X) from bus.\n", ++ byte, byte); ++ } ++ ++ return byte; ++} ++ ++ ++/* ++ * Read from the FCM Controller Data Buffer ++ */ ++static void fcm_read_buf(struct mtd_info *mtd, u_char* buf, int len) ++{ ++ volatile immap_t *im = (immap_t *) CFG_IMMR; ++ volatile lbus83xx_t *lbc= &im->lbus; ++ register struct nand_chip *this = mtd->priv; ++ struct fcm_nand *fcm = this->priv; ++ int i; ++ int rest; ++ ++ FCM_DEBUG(3,"fcm_read_buf: reading %d bytes.\n", len); ++ ++ /* If last read failed then return error bytes */ ++ if (fcm->status != LTESR_CC) { ++ /* just keep copying bytes so that the oob works */ ++ memcpy(buf, &(fcm->addr[(fcm->index)]), len); ++ fcm->index += len; ++ } ++ else ++ { ++ /* see how much is still in the FCM buffer */ ++ i = min(len, (fcm->read_bytes - fcm->index)); ++ rest = i - len; ++ len = i; ++ ++ memcpy(buf, &(fcm->addr[(fcm->index)]), len); ++ fcm->index += len; ++ ++ /* If more data is needed then issue another block read */ ++ if (rest) { ++ FCM_DEBUG(3,"fcm_read_buf: getting %d more bytes.\n", ++ rest); ++ buf += len; ++ lbc->fir = (FIR_OP_RBW << FIR_OP0_SHIFT); ++ set_addr(mtd, 0, 0, 0); ++ lbc->fbcr = rest; ++ fcm->req_bytes = lbc->fbcr; ++ fcm->req_index = 0; ++ fcm->use_mdr = 0; ++ if (!fcm_run_command(mtd)) ++ fcm_read_buf(mtd, buf, rest); ++ else ++ memcpy(buf, fcm->addr, rest); ++ } ++ } ++ return; ++} ++ ++ ++/* ++ * Verify buffer against the FCM Controller Data Buffer ++ */ ++static int fcm_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) ++{ ++ volatile immap_t *im = (immap_t *) CFG_IMMR; ++ volatile lbus83xx_t *lbc= &im->lbus; ++ register struct nand_chip *this = mtd->priv; ++ struct fcm_nand *fcm = this->priv; ++ int i; ++ int rest; ++ ++ FCM_DEBUG(3,"fcm_verify_buf: checking %d bytes starting with 0x%02x.\n", ++ len, *((unsigned long*) buf)); ++ /* If last read failed then return error bytes */ ++ if (fcm->status != LTESR_CC) { ++ return EFAULT; ++ } ++ ++ /* see how much is still in the FCM buffer */ ++ i = min(len, (fcm->read_bytes - fcm->index)); ++ rest = i - len; ++ len = i; ++ ++ if (memcmp(buf, &(fcm->addr[(fcm->index)]), len)) { ++ return EFAULT; ++ } ++ ++ fcm->index += len; ++ if (rest) { ++ FCM_DEBUG(3,"fcm_verify_buf: getting %d more bytes.\n", rest); ++ buf += len; ++ lbc->fir = (FIR_OP_RBW << FIR_OP0_SHIFT); ++ set_addr(mtd, 0, 0, 0); ++ lbc->fbcr = rest; ++ fcm->req_bytes = lbc->fbcr; ++ fcm->req_index = 0; ++ fcm->use_mdr = 0; ++ if (fcm_run_command(mtd)) ++ return EFAULT; ++ return fcm_verify_buf(mtd, buf, rest); ++ ++ } ++ return 0; ++} ++ ++/* this function is called after Program and Erase Operations to ++ * check for success or failure */ ++static int fcm_wait(struct mtd_info *mtd, struct nand_chip *this, int state) ++{ ++ volatile immap_t *im = (immap_t *) CFG_IMMR; ++ volatile lbus83xx_t *lbc= &im->lbus; ++ struct fcm_nand *fcm = this->priv; ++ ++ if (fcm->status != LTESR_CC) { ++ return(0x1); /* Status Read error */ ++ } ++ ++ /* Use READ_STATUS command, but wait for the device to be ready */ ++ fcm->use_mdr = 0; ++ fcm->req_index = 0; ++ fcm->read_bytes = 0; ++ fcm->index = 0; ++ fcm->oobbuf = -1; ++ lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | ++ (FIR_OP_RBW << FIR_OP1_SHIFT); ++ lbc->fcr = (NAND_CMD_STATUS << FCR_CMD0_SHIFT); ++ set_addr(mtd, 0, 0, 0); ++ lbc->fbcr = 1; ++ fcm->req_bytes = lbc->fbcr; ++ fcm_run_command(mtd); ++ if (fcm->status != LTESR_CC) { ++ return(0x1); /* Status Read error */ ++ } ++ return this->read_byte(mtd); ++} ++ ++ ++/* cmdfunc send commands to the FCM */ ++static void fcm_cmdfunc(struct mtd_info *mtd, unsigned command, ++ int column, int page_addr) ++{ ++ volatile immap_t *im = (immap_t *) CFG_IMMR; ++ volatile lbus83xx_t *lbc= &im->lbus; ++ register struct nand_chip *this = mtd->priv; ++ struct fcm_nand *fcm = this->priv; ++ ++ fcm->use_mdr = 0; ++ fcm->req_index = 0; ++ ++ /* clear the read buffer */ ++ fcm->read_bytes = 0; ++ if (command != NAND_CMD_PAGEPROG) { ++ fcm->index = 0; ++ fcm->oobbuf = -1; ++ } ++ ++ switch (command) { ++ /* READ0 and READ1 read the entire buffer to use hardware ECC */ ++ case NAND_CMD_READ1: ++ FCM_DEBUG(2,"fcm_cmdfunc: NAND_CMD_READ1, page_addr:" ++ " 0x%x, column: 0x%x.\n", page_addr, column); ++ fcm->req_index = column + 256; ++ goto read0; ++ case NAND_CMD_READ0: ++ FCM_DEBUG(2,"fcm_cmdfunc: NAND_CMD_READ0, page_addr:" ++ " 0x%x, column: 0x%x.\n", page_addr, column); ++ fcm->req_index = column; ++read0: ++ if (fcm->pgs) { ++ lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | ++ (FIR_OP_CA << FIR_OP1_SHIFT) | ++ (FIR_OP_PA << FIR_OP2_SHIFT) | ++ (FIR_OP_CW1 << FIR_OP3_SHIFT) | ++ (FIR_OP_RBW << FIR_OP4_SHIFT); ++ } else { ++ lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | ++ (FIR_OP_CA << FIR_OP1_SHIFT) | ++ (FIR_OP_PA << FIR_OP2_SHIFT) | ++ (FIR_OP_RBW << FIR_OP3_SHIFT); ++ } ++ lbc->fcr = (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | ++ (NAND_CMD_READSTART << FCR_CMD1_SHIFT); ++ lbc->fbcr = 0; /* read entire page to enable ECC */ ++ set_addr(mtd, 0, page_addr, 0); ++ fcm->req_bytes = mtd->oobblock + mtd->oobsize; ++ goto write_cmd2; ++ /* READOOB read only the OOB becasue no ECC is performed */ ++ case NAND_CMD_READOOB: ++ FCM_DEBUG(2,"fcm_cmdfunc: NAND_CMD_READOOB, page_addr:" ++ " 0x%x, column: 0x%x.\n", page_addr, column); ++ if (fcm->pgs) { ++ lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | ++ (FIR_OP_CA << FIR_OP1_SHIFT) | ++ (FIR_OP_PA << FIR_OP2_SHIFT) | ++ (FIR_OP_CW1 << FIR_OP3_SHIFT) | ++ (FIR_OP_RBW << FIR_OP4_SHIFT); ++ lbc->fcr = (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | ++ (NAND_CMD_READSTART << FCR_CMD1_SHIFT); ++ } else { ++ lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | ++ (FIR_OP_CA << FIR_OP1_SHIFT) | ++ (FIR_OP_PA << FIR_OP2_SHIFT) | ++ (FIR_OP_RBW << FIR_OP3_SHIFT); ++ lbc->fcr = (NAND_CMD_READOOB << FCR_CMD0_SHIFT); ++ } ++ lbc->fbcr = mtd->oobsize - column; ++ set_addr(mtd, column, page_addr, 1); ++ goto write_cmd1; ++ /* READID must read all 5 possible bytes while CEB is active */ ++ case NAND_CMD_READID: ++ FCM_DEBUG(2,"fcm_cmdfunc: NAND_CMD_READID.\n"); ++ lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | ++ (FIR_OP_UA << FIR_OP1_SHIFT) | ++ (FIR_OP_RBW << FIR_OP2_SHIFT); ++ lbc->fcr = (NAND_CMD_READID << FCR_CMD0_SHIFT); ++ lbc->fbcr = 5; /* 5 bytes for manuf, device and exts */ ++ fcm->use_mdr = 1; ++ fcm->mdr = 0; ++ goto write_cmd0; ++ /* ERASE1 stores the block and page address */ ++ case NAND_CMD_ERASE1: ++ FCM_DEBUG(2,"fcm_cmdfunc: NAND_CMD_ERASE1, page_addr:" ++ " 0x%x.\n", page_addr); ++ set_addr(mtd, 0, page_addr, 0); ++ goto end; ++ /* ERASE2 uses the block and page address from ERASE1 */ ++ case NAND_CMD_ERASE2: ++ FCM_DEBUG(2,"fcm_cmdfunc: NAND_CMD_ERASE2.\n"); ++ lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | ++ (FIR_OP_PA << FIR_OP1_SHIFT) | ++ (FIR_OP_CM1 << FIR_OP2_SHIFT); ++ lbc->fcr = (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) | ++ (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT); ++ lbc->fbcr = 0; ++ goto write_cmd1; ++ /* SEQIN sets up the addr buffer and all registers except the length */ ++ case NAND_CMD_SEQIN: ++ FCM_DEBUG(2,"fcm_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr:" ++ " 0x%x, column: 0x%x.\n", page_addr, column); ++ if (column == 0) { ++ lbc->fbcr = 0; /* write entire page to enable ECC */ ++ } else { ++ lbc->fbcr = 1; /* mark as partial page so no HW ECC */ ++ } ++ if (fcm->pgs) { ++ /* always use READ0 for large page devices */ ++ lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | ++ (FIR_OP_CA << FIR_OP1_SHIFT) | ++ (FIR_OP_PA << FIR_OP2_SHIFT) | ++ (FIR_OP_WB << FIR_OP3_SHIFT) | ++ (FIR_OP_CW1 << FIR_OP4_SHIFT); ++ lbc->fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) | ++ (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT); ++ set_addr(mtd, column, page_addr, 0); ++ } else { ++ lbc->fir = (FIR_OP_CW0 << FIR_OP0_SHIFT) | ++ (FIR_OP_CM2 << FIR_OP1_SHIFT) | ++ (FIR_OP_CA << FIR_OP2_SHIFT) | ++ (FIR_OP_PA << FIR_OP3_SHIFT) | ++ (FIR_OP_WB << FIR_OP4_SHIFT) | ++ (FIR_OP_CW1 << FIR_OP5_SHIFT); ++ if (column >= mtd->oobblock) { ++ /* OOB area --> READOOB */ ++ column -= mtd->oobblock; ++ lbc->fcr = (NAND_CMD_READOOB << FCR_CMD0_SHIFT) ++ | (NAND_CMD_PAGEPROG<< FCR_CMD1_SHIFT) ++ | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT); ++ set_addr(mtd, column, page_addr, 1); ++ } else if (column < 256) { ++ /* First 256 bytes --> READ0 */ ++ lbc->fcr = (NAND_CMD_READ0 << FCR_CMD0_SHIFT) ++ | (NAND_CMD_PAGEPROG<< FCR_CMD1_SHIFT) ++ | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT); ++ set_addr(mtd, column, page_addr, 0); ++ } else { ++ /* Second 256 bytes --> READ1 */ ++ column -= 256; ++ lbc->fcr = (NAND_CMD_READ1 << FCR_CMD0_SHIFT) ++ | (NAND_CMD_PAGEPROG<< FCR_CMD1_SHIFT) ++ | (NAND_CMD_SEQIN << FCR_CMD2_SHIFT); ++ set_addr(mtd, column, page_addr, 0); ++ } ++ } ++ goto end; ++ /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ ++ case NAND_CMD_PAGEPROG: ++ FCM_DEBUG(2,"fcm_cmdfunc: NAND_CMD_PAGEPROG" ++ " writing %d bytes.\n",fcm->index); ++ /* if the write did not start at 0 or is not a full page */ ++ /* then set the exact length, otherwise use a full page */ ++ /* write so the HW generates the ECC. */ ++ if (lbc->fbcr || ++ (fcm->index != (mtd->oobblock + mtd->oobsize))) ++ lbc->fbcr = fcm->index; ++ fcm->req_bytes = 0; ++ goto write_cmd2; ++ /* CMD_STATUS must read the status byte while CEB is active */ ++ /* Note - it does not wait for the ready line */ ++ case NAND_CMD_STATUS: ++ FCM_DEBUG(2,"fcm_cmdfunc: NAND_CMD_STATUS.\n"); ++ lbc->fir = (FIR_OP_CM0 << FIR_OP0_SHIFT) | ++ (FIR_OP_RBW << FIR_OP1_SHIFT); ++ lbc->fcr = (NAND_CMD_STATUS << FCR_CMD0_SHIFT); ++ lbc->fbcr = 1; ++ goto write_cmd0; ++ /* RESET without waiting for the ready line */ ++ case NAND_CMD_RESET: ++ FCM_DEBUG(2,"fcm_cmdfunc: NAND_CMD_RESET.\n"); ++ lbc->fir = (FIR_OP_CM0 << FIR_OP0_SHIFT); ++ lbc->fcr = (NAND_CMD_RESET << FCR_CMD0_SHIFT); ++ lbc->fbcr = 0; ++ goto write_cmd0; ++ default: ++ printk("fcm_cmdfunc: error, unsupported command.\n"); ++ goto end; ++ } ++ ++ /* Short cuts fall through to save code */ ++ write_cmd0: ++ set_addr(mtd, 0, 0, 0); ++ write_cmd1: ++ fcm->req_bytes = lbc->fbcr; ++ write_cmd2: ++ fcm_run_command(mtd); ++ ++#ifdef CONFIG_MTD_NAND_VERIFY_WRITE ++ /* if we wrote a page then read back the oob to get the ECC */ ++ if ((command == NAND_CMD_PAGEPROG) && ++ (this->eccmode > NAND_ECC_SOFT) && ++ (lbc->fbcr == 0) && ++ (fcm->oobbuf != 0) && ++ (fcm->oobbuf != -1)) { ++ int i; ++ uint *oob_config; ++ unsigned char *oob_buf; ++ ++ i = fcm->page; ++ oob_buf = (unsigned char*) fcm->oobbuf; ++ oob_config = this->autooob->eccpos; ++ ++ /* wait for the write to complete and check it passed */ ++ if (!(this->waitfunc(mtd, this, FL_WRITING) & 0x01)) { ++ /* read back the OOB */ ++ fcm_cmdfunc(mtd, NAND_CMD_READOOB, 0, i); ++ /* if it succeeded then copy the ECC bytes */ ++ if (fcm->status == LTESR_CC) { ++ for (i = 0; i < this->eccbytes; i++) { ++ oob_buf[oob_config[i]] = ++ fcm->addr[oob_config[i]]; ++ } ++ } ++ } ++ } ++#endif ++ ++ end: ++ return; ++} ++ ++/* ++ * fcm_enable_hwecc - start ECC generation ++ */ ++static void fcm_enable_hwecc(struct mtd_info *mtd, int mode) ++{ ++ return; ++} ++ ++/* ++ * fcm_calculate_ecc - Calculate the ECC bytes ++ * This is done by hardware during the write process, so we use this ++ * to arm the oob buf capture on the next write_buf() call. The ECC bytes ++ * only need to be captured if CONFIG_MTD_NAND_VERIFY_WRITE is defined which ++ * reads back the pages and checks they match the data and oob buffers. ++ */ ++static int fcm_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) ++{ ++ register struct nand_chip *this = mtd->priv; ++ struct fcm_nand *fcm = this->priv; ++ ++#ifdef CONFIG_MTD_NAND_VERIFY_WRITE ++ /* arm capture of oob buf ptr on next write_buf */ ++ fcm->oobbuf = 0; ++#endif ++ return 0; ++} ++ ++/* ++ * fcm_correct_data - Detect and correct bit error(s) ++ * The detection and correction is done automatically by the hardware, ++ * if the complete page was read. If the status code is okay then there ++ * was no error, otherwise we return an error code indicating an uncorrectable ++ * error. ++ */ ++static int fcm_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) ++{ ++ register struct nand_chip *this = mtd->priv; ++ struct fcm_nand *fcm = this->priv; ++ ++ /* No errors */ ++ if (fcm->status == LTESR_CC) ++ return 0; ++ ++ return -1; /* uncorrectable error */ ++} ++ ++ ++ ++/* ++ * Dummy scan_bbt to complete setup of the FMR based on NAND size ++ */ ++static int fcm_scan_bbt (struct mtd_info *mtd) ++{ ++ volatile immap_t *im = (immap_t *) CFG_IMMR; ++ volatile lbus83xx_t *lbc= &im->lbus; ++ register struct nand_chip *this = mtd->priv; ++ struct fcm_nand *fcm = this->priv; ++ unsigned int i; ++ unsigned int al; ++ ++ if (!fcm) { ++ printk (KERN_ERR "fcm_scan_bbt():" \ ++ " Failed to allocate chip specific data structure\n"); ++ return -1; ++ } ++ ++ /* calculate FMR Address Length field */ ++ al = 0; ++ for (i = this->pagemask >> 16; i ; i >>= 8) { ++ al++; ++ } ++ ++ /* add to ECCM mode set in fcm_init */ ++ fcm->fmr |= 12 << FMR_CWTO_SHIFT | /* Timeout > 12 mSecs */ ++ al << FMR_AL_SHIFT; ++ ++ FCM_DEBUG(1,"fcm_init: nand->options = %08X\n", this->options); ++ FCM_DEBUG(1,"fcm_init: nand->numchips = %10d\n", this->numchips); ++ FCM_DEBUG(1,"fcm_init: nand->chipsize = %10d\n", this->chipsize); ++ FCM_DEBUG(1,"fcm_init: nand->pagemask = %10X\n", this->pagemask); ++ FCM_DEBUG(1,"fcm_init: nand->eccmode = %10d\n", this->eccmode ); ++ FCM_DEBUG(1,"fcm_init: nand->eccsize = %10d\n", this->eccsize ); ++ FCM_DEBUG(1,"fcm_init: nand->eccbytes = %10d\n", this->eccbytes); ++ FCM_DEBUG(1,"fcm_init: nand->eccsteps = %10d\n", this->eccsteps); ++ FCM_DEBUG(1,"fcm_init: nand->chip_delay = %8d\n", this->chip_delay); ++ FCM_DEBUG(1,"fcm_init: nand->badblockpos = %7d\n", this->badblockpos); ++ FCM_DEBUG(1,"fcm_init: nand->chip_shift = %8d\n", this->chip_shift); ++ FCM_DEBUG(1,"fcm_init: nand->page_shift = %8d\n", this->page_shift); ++ FCM_DEBUG(1,"fcm_init: nand->phys_erase_shift = %2d\n", ++ this->phys_erase_shift); ++ FCM_DEBUG(1,"fcm_init: mtd->flags = %08X\n", mtd->flags); ++ FCM_DEBUG(1,"fcm_init: mtd->size = %10d\n", mtd->size); ++ FCM_DEBUG(1,"fcm_init: mtd->erasesize = %10d\n", mtd->erasesize); ++ FCM_DEBUG(1,"fcm_init: mtd->oobblock = %10d\n", mtd->oobblock); ++ FCM_DEBUG(1,"fcm_init: mtd->oobsize = %10d\n", mtd->oobsize); ++ FCM_DEBUG(1,"fcm_init: mtd->oobavail = %10d\n", mtd->oobavail); ++ FCM_DEBUG(1,"fcm_init: mtd->ecctype = %10d\n", mtd->ecctype); ++ FCM_DEBUG(1,"fcm_init: mtd->eccsize = %10d\n", mtd->eccsize); ++ ++ /* adjust Option Register and ECC to match Flash page size */ ++ if (mtd->oobblock == 512) ++ lbc->bank[fcm->bank].or &= ~(OR_FCM_PGS); ++ else if (mtd->oobblock == 2048) { ++ lbc->bank[fcm->bank].or |= OR_FCM_PGS; ++ /* adjust ecc setup if needed */ ++ if ( (lbc->bank[fcm->bank].br & BR_DECC) == BR_DECC_CHK_GEN) { ++ mtd->eccsize = 2048; ++ mtd->oobavail -= 9; ++ this->eccmode = NAND_ECC_HW12_2048; ++ this->eccsize = 2048; ++ this->eccbytes += 9; ++ this->eccsteps = 1; ++ this->autooob = (fcm->fmr & FMR_ECCM) ? ++ &fcm_oob_lp_eccm1 : &fcm_oob_lp_eccm0; ++ memcpy(&mtd->oobinfo, this->autooob, ++ sizeof(mtd->oobinfo)); ++ } ++ } ++ else { ++ printf("fcm_init: page size %d is not supported\n", ++ mtd->oobblock); ++ return -1; ++ } ++ fcm->pgs = (lbc->bank[fcm->bank].or>>OR_FCM_PGS_SHIFT) & 1; ++ ++ if (al > 2) { ++ printf("fcm_init: %d address bytes is not supported\n", al+2); ++ return -1; ++ } ++ ++ /* restore default scan_bbt function and call it */ ++ this->scan_bbt = nand_default_bbt; ++ return nand_default_bbt(mtd); ++} ++ ++/* ++ * Board-specific NAND initialization. The following members of the ++ * argument are board-specific (per include/linux/mtd/nand_new.h): ++ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device ++ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device ++ * - hwcontrol: hardwarespecific function for accesing control-lines ++ * - dev_ready: hardwarespecific function for accesing device ready/busy line ++ * - enable_hwecc: function to enable (reset) hardware ecc generator. Must ++ * only be provided if a hardware ECC is available ++ * - eccmode: mode of ecc, see defines ++ * - chip_delay: chip dependent delay for transfering data from array to ++ * read regs (tR) ++ * - options: various chip options. They can partly be set to inform ++ * nand_scan about special functionality. See the defines for further ++ * explanation ++ * Members with a "?" were not set in the merged testing-NAND branch, ++ * so they are not set here either. ++ */ ++int board_nand_init(struct nand_chip *nand) ++{ ++ volatile immap_t *im = (immap_t *) CFG_IMMR; ++ volatile lbus83xx_t *lbc= &im->lbus; ++ struct fcm_nand *fcm; ++ unsigned int bank; ++ ++ /* Enable FCM detection of timeouts, ECC errors and completion */ ++ lbc->ltedr &= ~(LTESR_FCT | LTESR_PAR | LTESR_CC); ++ ++ fcm = kmalloc (sizeof(struct fcm_nand), GFP_KERNEL); ++ if (!fcm) { ++ printk (KERN_ERR "board_nand_init():" \ ++ " Cannot allocate read buffer data structure\n"); ++ return; ++ } ++ ++ /* Find which chip select bank is being used for this device */ ++ for (bank=0; bank<8; bank++) { ++ if ( (lbc->bank[bank].br & BR_V) && ++ ( (lbc->bank[bank].br & BR_MSEL) == BR_MS_FCM ) && ++ ( (lbc->bank[bank].br & BR_BA) == ++ (lbc->bank[bank].or & OR_FCM_AM & ++ (unsigned int)(nand->IO_ADDR_R) ) ) ) { ++ fcm->bank = bank; ++// TODO fcm->fmr = FMR_ECCM; /* rest filled in later */ ++ fcm->fmr = 0; /* rest filled in later */ ++ fcm->read_bytes = 0; ++ fcm->index = 0; ++ fcm->pgs = (lbc->bank[bank].or>>OR_FCM_PGS_SHIFT) & 1; ++ fcm->base = lbc->bank[bank].br & BR_BA; ++ fcm->addr = (unsigned char*) (fcm->base); ++ nand->priv = fcm; ++ fcm->oobbuf = -1; ++ break; ++ } ++ } ++ ++ if (!nand->priv) { ++ printk (KERN_ERR "board_nand_init():" \ ++ " Could not find matching Chip Select\n"); ++ return -1; ++ } ++ ++ /* set up nand options */ ++ nand->options = 0; ++ /* set up function call table */ ++ nand->hwcontrol = fcm_hwcontrol; ++ nand->waitfunc = fcm_wait; ++ nand->read_byte = fcm_read_byte; ++ nand->write_byte = fcm_write_byte; ++ nand->read_word = fcm_read_word; ++ nand->write_word = fcm_write_word; ++ nand->read_buf = fcm_read_buf; ++ nand->verify_buf = fcm_verify_buf; ++ nand->write_buf = fcm_write_buf; ++ nand->cmdfunc = fcm_cmdfunc; ++ nand->scan_bbt = fcm_scan_bbt; ++ ++ /* If CS Base Register selects full hardware ECC then use it */ ++ if ( ( (lbc->bank[bank].br & BR_DECC) >> BR_DECC_SHIFT) == 2) { ++ /* put in small page settings and adjust later if needed */ ++ nand->eccmode = NAND_ECC_HW3_512; ++ nand->autooob = (fcm->fmr & FMR_ECCM) ? ++ &fcm_oob_sp_eccm1 : &fcm_oob_sp_eccm0; ++ nand->calculate_ecc = fcm_calculate_ecc; ++ nand->correct_data = fcm_correct_data; ++ nand->enable_hwecc = fcm_enable_hwecc; ++ } else { ++ /* otherwise fall back to default software ECC */ ++ nand->eccmode = NAND_ECC_SOFT; ++ } ++ return 0; ++} ++ ++#endif ++#endif +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h 2008-11-24 16:39:14.000000000 +0100 ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h 2008-11-24 16:39:15.000000000 +0100 +@@ -357,6 +357,7 @@ + #define CONFIG_CMD_MII + #define CONFIG_CMD_DATE + #define CONFIG_CMD_PCI ++#define CONFIG_CMD_NAND + + #if defined(CFG_RAMBOOT) + #undef CONFIG_CMD_ENV diff --git a/recipes/u-boot/u-boot-1.3.2/mpc8313e-rdb-watchdog.patch b/recipes/u-boot/u-boot-1.3.2/mpc8313e-rdb-watchdog.patch new file mode 100644 index 0000000000..db92fea35c --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/mpc8313e-rdb-watchdog.patch @@ -0,0 +1,15 @@ +Index: u-boot-1.3.2/include/configs/MPC8313ERDB.h +=================================================================== +--- u-boot-1.3.2.orig/include/configs/MPC8313ERDB.h 2008-09-12 18:47:22.000000000 +0200 ++++ u-boot-1.3.2/include/configs/MPC8313ERDB.h 2008-09-12 18:48:11.000000000 +0200 +@@ -460,6 +460,10 @@ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) + ++/* Watchdog */ ++#define CONFIG_WATCHDOG ++#define CFG_WATCHDOG_VALUE 0xFFFF ++ + /* System IO Config */ + #define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ + #define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */ diff --git a/recipes/u-boot/u-boot-1.3.2/u-boot-fsl-1.3.0-mpc8313erdb-fix-vitesse-7385-firmware.patch b/recipes/u-boot/u-boot-1.3.2/u-boot-fsl-1.3.0-mpc8313erdb-fix-vitesse-7385-firmware.patch new file mode 100644 index 0000000000..060f8495de --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/u-boot-fsl-1.3.0-mpc8313erdb-fix-vitesse-7385-firmware.patch @@ -0,0 +1,45 @@ +From a91275155f2250040bb21e4a1bb7f44c5092f6a2 Mon Sep 17 00:00:00 2001 +From: Li Yang <leoli@freescale.com> +Date: Wed, 28 May 2008 11:18:55 +0800 +Subject: [PATCH] Fix Vitesse 7385 firmware loading problem + +Signed-off-by: Li Yang <leoli@freescale.com> +--- + include/configs/MPC8313ERDB.h | 13 +++++++------ + 1 files changed, 7 insertions(+), 6 deletions(-) + +diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h +index 6568fe1..4e034ea 100644 +--- a/include/configs/MPC8313ERDB.h ++++ b/include/configs/MPC8313ERDB.h +@@ -184,7 +184,7 @@ + /* + * Local Bus LCRR and LBCR regs + */ +-#define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */ ++#define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_4 /* 0x00010004 */ + #define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \ + | (0xFF << LBCR_BMT_SHIFT) \ + | 0xF ) /* 0x0004ff0f */ +@@ -467,12 +467,13 @@ + #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) + #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) + +-/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +-#define CFG_IBAT6L (0xF0000000 | BATL_PP_10) +-#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) ++/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ ++#define CFG_IBAT6L (0xF8000000 | BATL_PP_10) ++#define CFG_IBAT6U (0xF8000000 | BATU_BL_128M | BATU_VS | BATU_VP) + +-#define CFG_IBAT7L (0) +-#define CFG_IBAT7U (0) ++/* Vitesse 7385 switch @ 0xF0000000 */ ++#define CFG_IBAT7L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) ++#define CFG_IBAT7U (0xF0000000 | BATU_BL_128M | BATU_VS | BATU_VP) + + #define CFG_DBAT0L CFG_IBAT0L + #define CFG_DBAT0U CFG_IBAT0U +-- +1.5.5.1.248.g4b17 + diff --git a/recipes/u-boot/u-boot-1.3.2/u-boot-fsl-1.3.0-mpc8313erdb-performance-tuning-for-TSEC.patch b/recipes/u-boot/u-boot-1.3.2/u-boot-fsl-1.3.0-mpc8313erdb-performance-tuning-for-TSEC.patch new file mode 100644 index 0000000000..2366842fe6 --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/u-boot-fsl-1.3.0-mpc8313erdb-performance-tuning-for-TSEC.patch @@ -0,0 +1,31 @@ +From 5c7efa5e60ec09810c5e2cdbb99872769116eb56 Mon Sep 17 00:00:00 2001 +From: Li Yang <leoli@freescale.com> +Date: Fri, 6 Jun 2008 11:44:32 +0800 +Subject: [PATCH] performance tuning for TSEC ports + +Increase transaction priority and TSEC clock. + +Signed-off-by: Li Yang <leoli@freescale.com> +--- + include/configs/MPC8313ERDB.h | 3 +++ + 1 files changed, 3 insertions(+), 0 deletions(-) + +diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h +index 0f6db5b..710d3e8 100644 +--- a/include/configs/MPC8313ERDB.h ++++ b/include/configs/MPC8313ERDB.h +@@ -65,8 +65,11 @@ + /*#define CFG_8313ERDB_BROKEN_PMC 1 */ + #undef CFG_8313ERDB_BROKEN_PMC + ++/* Performance tuning */ + #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ + #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ ++#define CFG_SPCR_TSECEP 3 /* eTSEC emergency priority (0-3) */ ++#define CFG_SCCR_TSEC1CM 1 /* TSEC1/2 clock mode (0-3) */ + + /* + * DDR Setup +-- +1.5.5.1.248.g4b17 + diff --git a/recipes/u-boot/u-boot-1.3.2/u-boot-fsl-1.3.0-mpc8313erdb-vsc7385-support.patch b/recipes/u-boot/u-boot-1.3.2/u-boot-fsl-1.3.0-mpc8313erdb-vsc7385-support.patch new file mode 100644 index 0000000000..9b23c27f0b --- /dev/null +++ b/recipes/u-boot/u-boot-1.3.2/u-boot-fsl-1.3.0-mpc8313erdb-vsc7385-support.patch @@ -0,0 +1,356 @@ +From fd62a67dc5b454528aa6b1732ccdaf9d845083d4 Mon Sep 17 00:00:00 2001 +From: Li Yang <leoli@freescale.com> +Date: Tue, 3 Jun 2008 19:18:48 +0800 +Subject: [PATCH] add VSC7385 support to MPC8313ERDB + +Signed-off-by: Li Yang <leoli@freescale.com> +--- + drivers/net/tsec.c | 38 +++++++++++- + examples/Makefile | 7 ++- + examples/vsc7385_load/Makefile | 104 ++++++++++++++++++++++++++++++ + examples/vsc7385_load/Readme.txt | 15 ++++ + examples/vsc7385_load/vsc7385_load.c | 117 ++++++++++++++++++++++++++++++++++ + 5 files changed, 279 insertions(+), 2 deletions(-) + create mode 100644 examples/vsc7385_load/Makefile + create mode 100644 examples/vsc7385_load/Readme.txt + create mode 100644 examples/vsc7385_load/vsc7385_load.c + +diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c +index ca6284b..d863ca3 100644 +--- a/drivers/net/tsec.c ++++ b/drivers/net/tsec.c +@@ -9,6 +9,12 @@ + * (C) Copyright 2003, Motorola, Inc. + * author Andy Fleming + * ++ * Copyright (C) 2006-2008 Freescale Semiconductor, Inc. All rights reserved. ++ * Change Log: ++ * Dec,2006: Wilson Lo (Wilson.Lo@freescale.com) ++ * Vitesse VSC7385 L2 Switch support as an unknow phy ++ * for MPC8313ERDB board ++ * + */ + + #include <config.h> +@@ -1350,7 +1356,33 @@ struct phy_info phy_info_dp83865 = { + {miim_end,} + }, + }; ++#ifdef CONFIG_VSC7385_ENET ++uint mii_unknown_hardcoded(uint mii_reg, struct tsec_private *priv) ++{ ++ priv->duplexity = 1; ++ priv->speed = 1000; ++ priv->link = 1; ++ return 0; ++} ++#endif + ++#ifdef CONFIG_VSC7385_ENET ++struct phy_info phy_info_unknown = { ++ 0xffffffff, ++ "unknown phy, assume 1000BaseT Full duplex", ++ 0, ++ (struct phy_cmd[]) { /* config */ ++ {miim_end,} ++ }, ++ (struct phy_cmd[]) { /* startup */ ++ {0x1, miim_read, mii_unknown_hardcoded}, ++ {miim_end,} ++ }, ++ (struct phy_cmd[]) { /* shutdown */ ++ {miim_end,} ++ }, ++}; ++#endif + struct phy_info *phy_info[] = { + &phy_info_cis8204, + &phy_info_cis8201, +@@ -1365,7 +1397,11 @@ struct phy_info *phy_info[] = { + &phy_info_VSC8244, + &phy_info_dp83865, + &phy_info_generic, +- NULL ++#ifdef CONFIG_VSC7385_ENET ++ &phy_info_unknown, ++#endif ++ ++ NULL + }; + + /* Grab the identifier of the device's PHY, and search through +diff --git a/examples/Makefile b/examples/Makefile +index e9b4974..5bb5eab 100644 +--- a/examples/Makefile ++++ b/examples/Makefile +@@ -152,7 +152,12 @@ clibdir := $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`) + + CPPFLAGS += -I.. + +-all: $(obj).depend $(OBJS) $(LIB) $(SREC) $(BIN) $(ELF) ++VSC = vsc7385_load\vsc7385_load.srec ++ ++all: $(obj).depend $(OBJS) $(LIB) $(SREC) $(BIN) $(ELF) $(VSC) ++ ++$(VSC): ++ cd vsc7385_load && $(MAKE) + + ######################################################################### + $(LIB): $(obj).depend $(LIBOBJS) +diff --git a/examples/vsc7385_load/Makefile b/examples/vsc7385_load/Makefile +new file mode 100644 +index 0000000..37dfe3b +--- /dev/null ++++ b/examples/vsc7385_load/Makefile +@@ -0,0 +1,104 @@ ++# ++# Copyright (C) 2006-2008 Freescale Semiconductor, Inc. All rights reserved. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++# Description: Makefile for the Vitesse VSC7385 Gigabit Ethernet Switch ++# firmware loader. ++# ++# Changelog: ++# 20061006 Joe.D'Abbraccio@freescale.com ++# This file is based on the examples/Makefile within the U-Boot ++# source tree. It is modified to build a U-boot application ++# that loads the Vitesse VSC7385 Gigabit Ethernet Switch firmware ++# ++ ++ ++ARCH = ppc ++ ++ifeq ($(ARCH),ppc) ++LOAD_ADDR = 0x40000 ++endif ++ ++PROGNAME = vsc7385_load ++ ++MAINSRC = vsc7385_load ++ ++ifdef TOPDIR ++include $(TOPDIR)/config.mk ++endif ++ ++ ++SREC = $(MAINSRC).srec ++BIN = $(MAINSRC).bin $(MAINSRC) ++ ++ifeq ($(BIG_ENDIAN),y) ++EX_LDFLAGS += -EB ++endif ++ ++ ++SUBSRCS = ++ ++OBJS = $(SREC:.srec=.o) $(SUBSRCS:=.o) ++ ++LIB = ../libstubs.a ++LIBAOBJS= ++ifeq ($(ARCH),ppc) ++LIBAOBJS+= ../$(ARCH)_longjmp.o ../$(ARCH)_setjmp.o ++endif ++LIBCOBJS= ../stubs.o ++LIBOBJS = $(LIBAOBJS) $(LIBCOBJS) ++ ++ifdef TOPDIR ++gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) ++clibdir := $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`) ++endif ++ ++CPPFLAGS += -I. ++ ++all: .depend $(SREC) $(BIN) $(SUBSRCS:=.o) ++ ++######################################################################### ++$(LIB): .depend $(LIBOBJS) ++ $(AR) crv $@ $(LIBOBJS) ++ ++$(LIBOBJS): ++ ++$(PROGNAME): $(PROGNAME).o $(SUBSRCS:=.o) $(LIB) ++ $(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \ ++ -o $(PROGNAME) -e main $< $(SUBSRCS:=.o) $(LIB) \ ++ -Map $(PROGNAME).map -L$(gcclibdir) -lgcc ++ ++$(PROGNAME).srec: $(PROGNAME) ++ $(OBJCOPY) -O srec $< $@ 2>/dev/null ++ ++$(PROGNAME).bin: $(PROGNAME) ++ $(OBJCOPY) -O binary $(PROGNAME) $(PROGNAME).bin 2>/dev/null ++ ++######################################################################### ++ ++.depend: Makefile $(OBJS:.o=.c) #$(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S) ++# $(CC) -M $(CFLAGS) $(OBJS:.o=.c) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S) > $@ ++ $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ ++ ++ifdef TOPDIR ++sinclude .depend ++endif ++ ++######################################################################### ++ ++clean: ++ rm -f $(PROGNAME) *.bin *.srec *.map .depend *.o +diff --git a/examples/vsc7385_load/Readme.txt b/examples/vsc7385_load/Readme.txt +new file mode 100644 +index 0000000..14e7821 +--- /dev/null ++++ b/examples/vsc7385_load/Readme.txt +@@ -0,0 +1,15 @@ ++This directory contains a U-Boot application that loads firmware required by ++the Vitesse VSC7385 Gigabit Switch device on the MPC8349E-mITXE or the ++MPC8313ERDB. The firmware loader application loads a binary image stored ++within the Flash ROM on the hardware platform. The binary image is loaded ++to the VSC7385 device that contains a standalone processor that runs the ++software (within the binary image) independently of the main processor ++subsystem and software within the MPC83xx. Once loaded and started the VSC7385 ++has no interaction with U-Boot or the Linux kernel. ++ ++The firmware loader, U-Boot application, is built using the U-Boot example ++applications as a template. The loader application build process is controlled ++using the example/Makefile by modifying this Makefile to add the loader ++application. An additional makefile is contained within this directory that ++contains the firmware loader application complete build instructions. ++ +diff --git a/examples/vsc7385_load/vsc7385_load.c b/examples/vsc7385_load/vsc7385_load.c +new file mode 100644 +index 0000000..24982e4 +--- /dev/null ++++ b/examples/vsc7385_load/vsc7385_load.c +@@ -0,0 +1,117 @@ ++/* ++ * ++ * Copyright (C) 2006-2008 Freescale Semiconductor, Inc. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ * ++ * Description: Firmware loader for the Vitesse VSC7385 Gigabit Ethernet Switch ++ * ++ * Changelog: ++ * 20070124 Joe.D'Abbraccio@freescale.com ++ * Added support for both MPC8349E-mITX and the MPC8313ERDB ++ * 20061006 Joe.D'Abbraccio@freescale.com ++ * Initial version. ++ * ++ */ ++ ++#include <common.h> ++#include <exports.h> ++#include <config.h> ++ ++#if CONFIG_MPC8349ITX || CONFIG_MPC8313ERDB ++ ++#if CONFIG_MPC8349ITX ++const unsigned char * VSC7385_image = 0xFEFFE000; ++#elif CONFIG_MPC8313ERDB ++const unsigned char * VSC7385_image = 0xFE7FE000; ++#endif ++ ++unsigned long image_size = (8 * 1024); ++ ++ ++int main(int argc, char *argv[]) ++{ ++ unsigned long *RESET = (unsigned long *)(CFG_VSC7385_BASE + 0x1c050); ++ unsigned long *CTRL = (unsigned long *)(CFG_VSC7385_BASE + 0x1c040); ++ unsigned long *ADDR = (unsigned long *)(CFG_VSC7385_BASE + 0x1c044); ++ unsigned long *DATA = (unsigned long *)(CFG_VSC7385_BASE + 0x1c048); ++ unsigned long *CHIPID = (unsigned long *)(CFG_VSC7385_BASE + 0x1c060); ++ unsigned long *MAP = (unsigned long *)(CFG_VSC7385_BASE + 0x1c070); ++ unsigned long size, i, value; ++ unsigned char load_succeeded; ++ ++ size = image_size; ++ *RESET = 3; ++ udelay(200); ++ ++ printf("VSC7385 Version = 0x%08lx\n", *CHIPID); ++ udelay(20); ++ ++ value = ( ++ (1<<7) | ++ (1<<3) | ++ (1<<2) | ++ (1<<1) | ++ (0<<0) ++ ); ++ *CTRL = value; ++ udelay(20); ++ ++ *MAP = 1; ++ udelay(20); ++ ++ *ADDR = 0x0; ++ udelay(20); ++ ++ for (i=0; i<size; i++){ ++ *DATA=VSC7385_image[i]; ++ udelay(20); ++ } ++ load_succeeded = 1; ++ ++ /* Read back to compare */ ++ *ADDR = 0x0; ++ ++ for (i=0; i<size; i++){ ++ udelay(20); ++ value = *DATA; ++ if (value != VSC7385_image[i]) { ++ printf("Error loading VSC7385 IRAM: ADDR: 0x%x, read value 0x%x mismatch image 0x%x\n", ++ i, value, VSC7385_image[i]); ++ load_succeeded = 0; ++ if (getc() == 'q') { ++ break; ++ } ++ } ++ } ++ if (load_succeeded == 1) { ++ printf("Value in IRAM matches binary, total bytes 0x%x loaded\n", size); ++ } ++ ++ value = ( ++ (0<<7) | ++ (1<<3) | ++ (0<<2) | ++ (1<<1) | ++ (1<<0) ++ ); ++ *CTRL = value; ++ ++ return(0); ++} ++ ++#endif +-- +1.5.5.1.248.g4b17 + |