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-rw-r--r--recipes/gcc/gcc-4.3.4/ep93xx/arm-crunch-disable-floatsi.patch64
-rw-r--r--recipes/gcc/gcc-4.3.4/ep93xx/arm-crunch-fix-cirrus-reorg7.patch (renamed from recipes/gcc/gcc-4.3.4/ep93xx/arm-crunch-fix-cirrus-reorg5.patch)74
-rw-r--r--recipes/gcc/gcc-4.3.4/ep93xx/series7
3 files changed, 111 insertions, 34 deletions
diff --git a/recipes/gcc/gcc-4.3.4/ep93xx/arm-crunch-disable-floatsi.patch b/recipes/gcc/gcc-4.3.4/ep93xx/arm-crunch-disable-floatsi.patch
new file mode 100644
index 0000000000..d7512ba042
--- /dev/null
+++ b/recipes/gcc/gcc-4.3.4/ep93xx/arm-crunch-disable-floatsi.patch
@@ -0,0 +1,64 @@
+int->float instructions cfcvt32s and cfcvt32d do seem to work but if they are
+enabled, the vorbis testsuite (file lib/vorbisenc.c) fail and lame to segfault
+on nonstandard bit rate wav files such as 11050 bps (file libmp3lame/util.c).
+
+Until someone wants to figure out what the real problem is we just disable these
+two insns because then everything seems to work.
+
+Index: gcc-4.3.4/gcc/config/arm/arm.md
+===================================================================
+--- gcc-4.3.4.orig/gcc/config/arm/arm.md 2009-09-11 11:39:37.000000000 +0100
++++ gcc-4.3.4/gcc/config/arm/arm.md 2009-09-11 11:42:49.000000000 +0100
+@@ -3543,10 +3543,14 @@
+
+ ;; Fixed <--> Floating conversion insns
+
++; Maverick int->float conversion insns seem to work but tickle an optimization
++; bug in GCC 4.[123].* so we paper over it to get working code :-/
++; It may be the same as http://gcc.gnu.org/bugzilla/show_bug.cgi?id=39501
++
+ (define_expand "floatsisf2"
+ [(set (match_operand:SF 0 "s_register_operand" "")
+ (float:SF (match_operand:SI 1 "s_register_operand" "")))]
+- "TARGET_32BIT && TARGET_HARD_FLOAT"
++ "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_MAVERICK"
+ "
+ if (TARGET_MAVERICK)
+ {
+@@ -3558,7 +3562,7 @@
+ (define_expand "floatsidf2"
+ [(set (match_operand:DF 0 "s_register_operand" "")
+ (float:DF (match_operand:SI 1 "s_register_operand" "")))]
+- "TARGET_32BIT && TARGET_HARD_FLOAT"
++ "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_MAVERICK"
+ "
+ if (TARGET_MAVERICK)
+ {
+Index: gcc-4.3.4/gcc/config/arm/cirrus.md
+===================================================================
+--- gcc-4.3.4.orig/gcc/config/arm/cirrus.md 2009-09-11 11:39:47.000000000 +0100
++++ gcc-4.3.4/gcc/config/arm/cirrus.md 2009-09-11 11:44:04.000000000 +0100
+@@ -359,10 +359,13 @@
+ )
+
+ ;; Convert Cirrus-SI to Cirrus-SF
++
++; int->float conversions are disabled to avoid a GCC bug. See arm.md
++
+ (define_insn "cirrus_floatsisf2"
+ [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
+ (float:SF (match_operand:SI 1 "s_register_operand" "r")))]
+- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfmv64lr%?\\t%Z0, %1\;cfcvt32s%?\\t%V0, %Y0"
+ [(set_attr "type" "f_cvt")
+ (set_attr "length" "8")
+@@ -372,7 +375,7 @@
+ (define_insn "cirrus_floatsidf2"
+ [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
+ (float:DF (match_operand:SI 1 "s_register_operand" "r")))]
+- "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
++ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
+ "cfmv64lr%?\\t%Z0, %1\;cfcvt32d%?\\t%V0, %Y0"
+ [(set_attr "type" "f_cvt")
+ (set_attr "length" "8")
diff --git a/recipes/gcc/gcc-4.3.4/ep93xx/arm-crunch-fix-cirrus-reorg5.patch b/recipes/gcc/gcc-4.3.4/ep93xx/arm-crunch-fix-cirrus-reorg7.patch
index 313b7001bd..1be8499643 100644
--- a/recipes/gcc/gcc-4.3.4/ep93xx/arm-crunch-fix-cirrus-reorg5.patch
+++ b/recipes/gcc/gcc-4.3.4/ep93xx/arm-crunch-fix-cirrus-reorg7.patch
@@ -13,8 +13,10 @@ This patch:
Martin Guy <martinwguy@yahoo.it> 3 March 2009
---- gcc-4.3.2/gcc/config/arm/arm.c.orig 2009-02-18 14:59:22.000000000 +0000
-+++ gcc-4.3.2/gcc/config/arm/arm.c 2009-03-10 09:32:31.000000000 +0000
+Index: gcc-4.3.4/gcc/config/arm/arm.c
+===================================================================
+--- gcc-4.3.4.orig/gcc/config/arm/arm.c 2009-08-09 14:46:51.000000000 +0100
++++ gcc-4.3.4/gcc/config/arm/arm.c 2009-08-09 14:47:11.000000000 +0100
@@ -134,7 +134,7 @@
static int arm_address_cost (rtx);
static bool arm_memory_load_p (rtx);
@@ -24,7 +26,17 @@ This patch:
static void arm_init_builtins (void);
static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
static void arm_init_iwmmxt_builtins (void);
-@@ -6580,122 +6580,122 @@
+@@ -6538,6 +6538,9 @@
+
+ body = PATTERN (insn);
+
++ if (GET_CODE (body) == COND_EXEC)
++ body = COND_EXEC_CODE (body);
++
+ if (GET_CODE (body) != SET)
+ return false;
+
+@@ -6580,122 +6583,118 @@
/* Cirrus reorg for invalid instruction combinations. */
static void
@@ -61,15 +73,15 @@ This patch:
- if (GET_CODE (body) == SET)
- {
- rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
--
++ rtx insn, body;
+
- /* cfldrd, cfldr64, cfstrd, cfstr64 must
- be followed by a non Cirrus insn. */
- if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
- {
- if (arm_cirrus_insn_p (next_nonnote_insn (first)))
- emit_insn_after (gen_nop (), first);
-+ rtx insn, body;
-
+-
- return;
- }
- else if (arm_memory_load_p (first))
@@ -117,14 +129,18 @@ This patch:
- gcc_assert (GET_CODE (rhs) == REG);
- arm_regno = REGNO (rhs);
- }
+-
+- /* Next insn. */
+- first = next_nonnote_insn (first);
+ cfstrd mvd0, [r0]
+ otherwise the FPU stores to random memory locations.
+ */
+ body = PATTERN (insn);
++
++ /* Also applies to conditionally executed ldr */
++ if (GET_CODE (body) == COND_EXEC)
++ body = COND_EXEC_CODE (body);
-- /* Next insn. */
-- first = next_nonnote_insn (first);
--
- if (! arm_cirrus_insn_p (first))
- return;
+ /* If first insn is ldr rN, <mem>... */
@@ -206,16 +222,6 @@ This patch:
- if (arm_cirrus_insn_p (t))
- ++ nops;
+ case PLUS: /* it's [rN, #XXX] or [rN, -#YYY]. */
-+ if (GET_CODE (XEXP (arm_part, 0)) == REG)
-+ arm_regno = REGNO (XEXP (arm_part, 0)); /* usual case */
-+ else if (GET_CODE (XEXP (arm_part, 1)) == REG)
-+ arm_regno = REGNO (XEXP (arm_part, 1)); /* inverted */
-+ else
-+ gcc_unreachable();
-+ break;
-
-- if (arm_cirrus_insn_p (next_nonnote_insn (t)))
-- ++ nops;
+ case PRE_INC:
+ case POST_INC:
+ case PRE_DEC:
@@ -224,28 +230,30 @@ This patch:
+ arm_regno = REGNO (XEXP (arm_part, 0));
+ break;
-- while (nops --)
-- emit_insn_after (gen_nop (), first);
+- if (arm_cirrus_insn_p (next_nonnote_insn (t)))
+- ++ nops;
+ default:
+ /* Do nothing */
+ continue;
+ }
-- return;
-- }
+- while (nops --)
+- emit_insn_after (gen_nop (), first);
+ if (arm_regno == REGNO (ldr_target))
+ emit_insn_after (gen_nop (), insn);
+ }
+ }
+ break;
-+
+
+- return;
+- }
+ default:
+ break;
+ }
}
/* Return TRUE if X references a SYMBOL_REF. */
-@@ -9293,6 +9296,10 @@
+@@ -9293,6 +9292,10 @@
minipool_fix_head = minipool_fix_tail = NULL;
@@ -256,7 +264,7 @@ This patch:
/* The first insn must always be a note, or the code below won't
scan it properly. */
insn = get_insns ();
-@@ -9302,12 +9309,6 @@
+@@ -9302,12 +9305,6 @@
/* Scan all the insns and record the operands that will need fixing. */
for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
{
@@ -269,8 +277,10 @@ This patch:
if (GET_CODE (insn) == BARRIER)
push_minipool_barrier (insn, address);
else if (INSN_P (insn))
---- gcc-4.3.2/gcc/config/arm/arm.opt.orig 2009-03-02 10:17:08.000000000 +0000
-+++ gcc-4.3.2/gcc/config/arm/arm.opt 2009-03-02 10:27:30.000000000 +0000
+Index: gcc-4.3.4/gcc/config/arm/arm.opt
+===================================================================
+--- gcc-4.3.4.orig/gcc/config/arm/arm.opt 2009-08-09 14:46:51.000000000 +0100
++++ gcc-4.3.4/gcc/config/arm/arm.opt 2009-08-09 14:47:11.000000000 +0100
@@ -63,10 +63,6 @@
Target Report Mask(CALLER_INTERWORKING)
Thumb: Assume function pointers may go to non-Thumb aware code
@@ -282,8 +292,10 @@ This patch:
mcpu=
Target RejectNegative Joined
Specify the name of the target CPU
---- gcc-4.3.2/gcc/doc/invoke.texi.old 2008-12-04 11:48:54.000000000 +0000
-+++ gcc-4.3.2/gcc/doc/invoke.texi 2009-03-02 10:26:45.000000000 +0000
+Index: gcc-4.3.4/gcc/doc/invoke.texi
+===================================================================
+--- gcc-4.3.4.orig/gcc/doc/invoke.texi 2009-08-09 14:46:51.000000000 +0100
++++ gcc-4.3.4/gcc/doc/invoke.texi 2009-08-09 14:47:12.000000000 +0100
@@ -429,7 +429,6 @@
-msingle-pic-base -mno-single-pic-base @gol
-mpic-register=@var{reg} @gol
@@ -292,7 +304,7 @@ This patch:
-mieee @gol
-mpoke-function-name @gol
-mthumb -marm @gol
-@@ -8671,18 +8671,6 @@
+@@ -8673,18 +8672,6 @@
Specify the register to be used for PIC addressing. The default is R10
unless stack-checking is enabled, when R9 is used.
diff --git a/recipes/gcc/gcc-4.3.4/ep93xx/series b/recipes/gcc/gcc-4.3.4/ep93xx/series
index e6bfe421f1..626cf54314 100644
--- a/recipes/gcc/gcc-4.3.4/ep93xx/series
+++ b/recipes/gcc/gcc-4.3.4/ep93xx/series
@@ -16,10 +16,11 @@ arm-crunch-drop-thumb2.patch
arm-crunch-arm_dbx_register_number.patch
arm-crunch-pipeline.patch
arm-crunch-ccmav-mode.patch
-arm-crunch-cfcpy-with-cfsh64.patch
-arm-crunch-mieee.patch
+arm-crunch-cfcpy-with-cfsh64.patch
+arm-crunch-mieee.patch
arm-size-bugfix.patch
arm-prologue_use-length.patch
arm-crunch-cftruncd32-attr.patch
-arm-crunch-fix-cirrus-reorg5.patch
+arm-crunch-fix-cirrus-reorg7.patch
arm-crunch-cirrus-di-flag.patch
+arm-crunch-disable-floatsi.patch
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 10:28:32 +0000