diff options
Diffstat (limited to 'packages')
9 files changed, 39002 insertions, 2 deletions
diff --git a/packages/uboot/u-boot-1.1.6/u-boot-1.1.6-83xx-optimizations.patch b/packages/uboot/u-boot-1.1.6/u-boot-1.1.6-83xx-optimizations.patch new file mode 100644 index 0000000000..fe85228771 --- /dev/null +++ b/packages/uboot/u-boot-1.1.6/u-boot-1.1.6-83xx-optimizations.patch @@ -0,0 +1,89 @@ +diff --exclude CVS -uNr u-boot-1.1.6/cpu/mpc83xx/cpu_init.c u-boot-1.1.6.modified/cpu/mpc83xx/cpu_init.c +--- u-boot-1.1.6/cpu/mpc83xx/cpu_init.c 2007-04-10 17:43:16.000000000 -0400 ++++ u-boot-1.1.6.modified/cpu/mpc83xx/cpu_init.c 2007-04-10 17:31:51.000000000 -0400 +@@ -66,10 +66,30 @@ + memset ((void *) gd, 0, sizeof (gd_t)); + + /* system performance tweaking */ ++ /* System Priority Configuration Register (SPCR) */ ++#ifdef CFG_SPCR_PCIHPE ++ /* PCI highest priority enable */ ++ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_PCIHPE) | (CFG_SPCR_PCIHPE << SPCR_PCIHPE_SHIFT); ++#endif + +-#ifdef CFG_ACR_PIPE_DEP +- /* Arbiter pipeline depth */ +- im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (3 << ACR_PIPE_DEP_SHIFT); ++#ifdef CFG_SPCR_PCIPR ++ /* PCI bridge CSB request priority */ ++ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_PCIPR) | (CFG_SPCR_PCIPR << SPCR_PCIPR_SHIFT); ++#endif ++ ++#ifdef CFG_SPCR_OPT ++ /* Optimize transactions between CSB and other devices */ ++ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) | (CFG_SPCR_OPT << SPCR_OPT_SHIFT); ++#endif ++ ++#ifdef CFG_SPCR_TBEN ++ /* e300 time base unit enable */ ++ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TBEN) | (CFG_SPCR_TBEN << SPCR_TBEN_SHIFT); ++#endif ++ ++#ifdef CFG_SPCR_COREPR ++ /* e300 core CSB request priority */ ++ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_COREPR) | (CFG_SPCR_COREPR << SPCR_COREPR_SHIFT); + #endif + + #ifdef CFG_SPCR_TSEC1EP +@@ -82,6 +102,7 @@ + im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (3 << SPCR_TSEC2EP_SHIFT); + #endif + ++ /* System Clock Control Register (SCCR) */ + #ifdef CFG_SCCR_TSEC1CM + /* TSEC1 clock mode */ + im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (1 << SCCR_TSEC1CM_SHIFT); +@@ -91,6 +112,12 @@ + im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (1 << SCCR_TSEC2CM_SHIFT); + #endif + ++ /* Arbiter Control Register (ACR) */ ++#ifdef CFG_ACR_PIPE_DEP ++ /* Arbiter pipeline depth */ ++ im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (3 << ACR_PIPE_DEP_SHIFT); ++#endif ++ + #ifdef CFG_ACR_RPTCNT + /* Arbiter repeat count */ + im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (3 << ACR_RPTCNT_SHIFT)); +diff --exclude CVS -uNr u-boot-1.1.6/include/configs/MPC8323ERDB.h u-boot-1.1.6.modified/include/configs/MPC8323ERDB.h +--- u-boot-1.1.6/include/configs/MPC8323ERDB.h 2007-04-10 17:43:16.000000000 -0400 ++++ u-boot-1.1.6.modified/include/configs/MPC8323ERDB.h 2007-04-10 17:32:03.000000000 -0400 +@@ -63,6 +63,16 @@ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) + ++/* System performance */ ++#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ ++#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ ++#define CFG_SPCR_PCIHPE 0 /* (0-1) PCI highest priority enable */ ++#define CFG_SPCR_PCIPR 0 /* (0-3) PCI bridge CSB request priority */ ++#define CFG_SPCR_OPT 1 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */ ++#define CFG_SPCR_TBEN 1 /* (0-1) e300 time base unit enable */ ++#define CFG_SPCR_COREPR 0 /* (0-3) e300 core CSB request priority */ ++ ++ + /* + * System IO Config + */ +diff --exclude CVS -uNr u-boot-1.1.6/include/mpc83xx.h u-boot-1.1.6.modified/include/mpc83xx.h +--- u-boot-1.1.6/include/mpc83xx.h 2007-04-10 17:43:16.000000000 -0400 ++++ u-boot-1.1.6.modified/include/mpc83xx.h 2007-04-10 17:32:15.000000000 -0400 +@@ -91,6 +91,7 @@ + #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ + #define SPCR_PCIPR_SHIFT (31-7) + #define SPCR_OPT 0x00800000 /* Optimize */ ++#define SPCR_OPT_SHIFT (31-8) + #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ + #define SPCR_TBEN_SHIFT (31-9) + #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ diff --git a/packages/uboot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Add-support-for-the-MPC832XEMDS-board.patch b/packages/uboot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Add-support-for-the-MPC832XEMDS-board.patch new file mode 100644 index 0000000000..5018cd3434 --- /dev/null +++ b/packages/uboot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Add-support-for-the-MPC832XEMDS-board.patch @@ -0,0 +1,1809 @@ +fe298a1bbd7b9526ca1139da8977e1a076c4e176 +diff --git a/Makefile b/Makefile +index d2534ab..d172411 100644 +--- a/Makefile ++++ b/Makefile +@@ -1621,6 +1621,30 @@ MPC8360EMDS_SLAVE_config: unconfig + MPC8349ITX_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349itx + ++MPC832XEMDS_config \ ++MPC832XEMDS_HOST_33_config \ ++MPC832XEMDS_HOST_66_config \ ++MPC832XEMDS_SLAVE_config: unconfig ++ @echo "" >include/config.h ; \ ++ if [ "$(findstring _HOST_,$@)" ] ; then \ ++ echo -n "... PCI HOST " ; \ ++ echo "#define CONFIG_PCI" >>include/config.h ; \ ++ fi ; \ ++ if [ "$(findstring _SLAVE_,$@)" ] ; then \ ++ echo "...PCI SLAVE 66M" ; \ ++ echo "#define CONFIG_PCI" >>include/config.h ; \ ++ echo "#define CONFIG_PCISLAVE" >>include/config.h ; \ ++ fi ; \ ++ if [ "$(findstring _33_,$@)" ] ; then \ ++ echo -n "...33M ..." ; \ ++ echo "#define PCI_33M" >>include/config.h ; \ ++ fi ; \ ++ if [ "$(findstring _66_,$@)" ] ; then \ ++ echo -n "...66M..." ; \ ++ echo "#define PCI_66M" >>include/config.h ; \ ++ fi ; ++ @$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds ++ + ######################################################################### + ## MPC85xx Systems + ######################################################################### +diff --git a/board/mpc832xemds/Makefile b/board/mpc832xemds/Makefile +new file mode 100644 +index 0000000..5ec7a87 +--- /dev/null ++++ b/board/mpc832xemds/Makefile +@@ -0,0 +1,50 @@ ++# ++# (C) Copyright 2006 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).a ++ ++COBJS := $(BOARD).o pci.o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) ++ $(AR) $(ARFLAGS) $@ $(OBJS) ++ ++clean: ++ rm -f $(SOBJS) $(OBJS) ++ ++distclean: clean ++ rm -f $(LIB) core *.bak .depend ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff --git a/board/mpc832xemds/config.mk b/board/mpc832xemds/config.mk +new file mode 100644 +index 0000000..6c3eca7 +--- /dev/null ++++ b/board/mpc832xemds/config.mk +@@ -0,0 +1,28 @@ ++# ++# (C) Copyright 2006 ++# Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++# ++# MPC832XEMDS ++# ++ ++TEXT_BASE = 0xFE000000 +diff --git a/board/mpc832xemds/mpc832xemds.c b/board/mpc832xemds/mpc832xemds.c +new file mode 100644 +index 0000000..772da67 +--- /dev/null ++++ b/board/mpc832xemds/mpc832xemds.c +@@ -0,0 +1,176 @@ ++/* ++ * Copyright (C) 2006 Freescale Semiconductor, Inc. ++ * ++ * Dave Liu <daveliu@freescale.com> ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#include <common.h> ++#include <ioports.h> ++#include <mpc83xx.h> ++#include <i2c.h> ++#include <spd.h> ++#include <miiphy.h> ++#include <command.h> ++#if defined(CONFIG_PCI) ++#include <pci.h> ++#endif ++#if defined(CONFIG_SPD_EEPROM) ++#include <spd_sdram.h> ++#else ++#include <asm/mmu.h> ++#endif ++#if defined(CONFIG_OF_FLAT_TREE) ++#include <ft_build.h> ++#endif ++ ++const qe_iop_conf_t qe_iop_conf_tab[] = { ++ /* ETH3 */ ++ {1, 0, 1, 0, 1}, /* TxD0 */ ++ {1, 1, 1, 0, 1}, /* TxD1 */ ++ {1, 2, 1, 0, 1}, /* TxD2 */ ++ {1, 3, 1, 0, 1}, /* TxD3 */ ++ {1, 9, 1, 0, 1}, /* TxER */ ++ {1, 12, 1, 0, 1}, /* TxEN */ ++ {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ ++ ++ {1, 4, 2, 0, 1}, /* RxD0 */ ++ {1, 5, 2, 0, 1}, /* RxD1 */ ++ {1, 6, 2, 0, 1}, /* RxD2 */ ++ {1, 7, 2, 0, 1}, /* RxD3 */ ++ {1, 8, 2, 0, 1}, /* RxER */ ++ {1, 10, 2, 0, 1}, /* RxDV */ ++ {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ ++ {1, 11, 2, 0, 1}, /* COL */ ++ {1, 13, 2, 0, 1}, /* CRS */ ++ ++ /* ETH4 */ ++ {1, 18, 1, 0, 1}, /* TxD0 */ ++ {1, 19, 1, 0, 1}, /* TxD1 */ ++ {1, 20, 1, 0, 1}, /* TxD2 */ ++ {1, 21, 1, 0, 1}, /* TxD3 */ ++ {1, 27, 1, 0, 1}, /* TxER */ ++ {1, 30, 1, 0, 1}, /* TxEN */ ++ {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */ ++ ++ {1, 22, 2, 0, 1}, /* RxD0 */ ++ {1, 23, 2, 0, 1}, /* RxD1 */ ++ {1, 24, 2, 0, 1}, /* RxD2 */ ++ {1, 25, 2, 0, 1}, /* RxD3 */ ++ {1, 26, 1, 0, 1}, /* RxER */ ++ {1, 28, 2, 0, 1}, /* Rx_DV */ ++ {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */ ++ {1, 29, 2, 0, 1}, /* COL */ ++ {1, 31, 2, 0, 1}, /* CRS */ ++ ++ {3, 4, 3, 0, 2}, /* MDIO */ ++ {3, 5, 1, 0, 2}, /* MDC */ ++ ++ {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ ++}; ++ ++int board_early_init_f(void) ++{ ++ volatile u8 *bcsr = (volatile u8 *)CFG_BCSR; ++ ++ /* Enable flash write */ ++ bcsr[9] &= ~0x08; ++ ++ return 0; ++} ++ ++int fixed_sdram(void); ++ ++long int initdram(int board_type) ++{ ++ volatile immap_t *im = (immap_t *) CFG_IMMR; ++ u32 msize = 0; ++ ++ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) ++ return -1; ++ ++ /* DDR SDRAM - Main SODIMM */ ++ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; ++ ++ msize = fixed_sdram(); ++ ++ puts("\n DDR RAM: "); ++ ++ /* return total bus SDRAM size(bytes) -- DDR */ ++ return (msize * 1024 * 1024); ++} ++ ++/************************************************************************* ++ * fixed sdram init -- doesn't use serial presence detect. ++ ************************************************************************/ ++int fixed_sdram(void) ++{ ++ volatile immap_t *im = (immap_t *) CFG_IMMR; ++ u32 msize = 0; ++ u32 ddr_size; ++ u32 ddr_size_log2; ++ ++ msize = CFG_DDR_SIZE; ++ for (ddr_size = msize << 20, ddr_size_log2 = 0; ++ (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { ++ if (ddr_size & 1) { ++ return -1; ++ } ++ } ++ im->sysconf.ddrlaw[0].ar = ++ LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); ++#if (CFG_DDR_SIZE != 128) ++#warning Currenly any ddr size other than 128 is not supported ++#endif ++ im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; ++ im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; ++ im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; ++ im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; ++ im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; ++ im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; ++ im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; ++ im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; ++ im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; ++ im->ddr.sdram_mode = CFG_DDR_MODE; ++ im->ddr.sdram_mode2 = CFG_DDR_MODE2; ++ im->ddr.sdram_interval = CFG_DDR_INTERVAL; ++ __asm__ __volatile__ ("sync"); ++ udelay(200); ++ ++ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; ++ __asm__ __volatile__ ("sync"); ++ return msize; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: Freescale MPC832XEMDS\n"); ++ return 0; ++} ++ ++#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) ++void ++ft_board_setup(void *blob, bd_t *bd) ++{ ++ u32 *p; ++ int len; ++ ++#ifdef CONFIG_PCI ++ ft_pci_setup(blob, bd); ++#endif ++ ft_cpu_setup(blob, bd); ++ ++ p = ft_get_prop(blob, "/memory/reg", &len); ++ if (p != NULL) { ++ *p++ = cpu_to_be32(bd->bi_memstart); ++ *p = cpu_to_be32(bd->bi_memsize); ++ } ++} ++#endif +diff --git a/board/mpc832xemds/pci.c b/board/mpc832xemds/pci.c +new file mode 100644 +index 0000000..09f3ac3 +--- /dev/null ++++ b/board/mpc832xemds/pci.c +@@ -0,0 +1,313 @@ ++/* ++ * Copyright (C) 2006 Freescale Semiconductor, Inc. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++/* ++ * PCI Configuration space access support for MPC83xx PCI Bridge ++ */ ++#include <asm/mmu.h> ++#include <asm/io.h> ++#include <common.h> ++#include <pci.h> ++#include <i2c.h> ++ ++#include <asm/fsl_i2c.h> ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#if defined(CONFIG_PCI) ++#define PCI_FUNCTION_CONFIG 0x44 ++#define PCI_FUNCTION_CFG_LOCK 0x20 ++ ++/* ++ * Initialize PCI Devices, report devices found ++ */ ++#ifndef CONFIG_PCI_PNP ++static struct pci_config_table pci_mpc83xxemds_config_table[] = { ++ { ++ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, ++ pci_cfgfunc_config_device, ++ {PCI_ENET0_IOADDR, ++ PCI_ENET0_MEMADDR, ++ PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} ++ }, ++ {} ++} ++#endif ++static struct pci_controller hose[] = { ++ { ++#ifndef CONFIG_PCI_PNP ++ config_table:pci_mpc83xxemds_config_table, ++#endif ++ }, ++}; ++ ++/********************************************************************** ++ * pci_init_board() ++ *********************************************************************/ ++void pci_init_board(void) ++#ifdef CONFIG_PCISLAVE ++{ ++ u16 reg16; ++ volatile immap_t *immr; ++ volatile law83xx_t *pci_law; ++ volatile pot83xx_t *pci_pot; ++ volatile pcictrl83xx_t *pci_ctrl; ++ volatile pciconf83xx_t *pci_conf; ++ ++ immr = (immap_t *) CFG_IMMR; ++ pci_law = immr->sysconf.pcilaw; ++ pci_pot = immr->ios.pot; ++ pci_ctrl = immr->pci_ctrl; ++ pci_conf = immr->pci_conf; ++ /* ++ * Configure PCI Inbound Translation Windows ++ */ ++ pci_ctrl[0].pitar0 = 0x0; ++ pci_ctrl[0].pibar0 = 0x0; ++ pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP | ++ PIWAR_WTT_SNOOP | PIWAR_IWS_4K; ++ ++ pci_ctrl[0].pitar1 = 0x0; ++ pci_ctrl[0].pibar1 = 0x0; ++ pci_ctrl[0].piebar1 = 0x0; ++ pci_ctrl[0].piwar1 &= ~PIWAR_EN; ++ ++ pci_ctrl[0].pitar2 = 0x0; ++ pci_ctrl[0].pibar2 = 0x0; ++ pci_ctrl[0].piebar2 = 0x0; ++ pci_ctrl[0].piwar2 &= ~PIWAR_EN; ++ ++ hose[0].first_busno = 0; ++ hose[0].last_busno = 0xff; ++ pci_setup_indirect(&hose[0], ++ (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); ++ reg16 = 0xff; ++ ++ pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), ++ PCI_COMMAND, ®16); ++ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY; ++ pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), ++ PCI_COMMAND, reg16); ++ ++ /* ++ * Clear non-reserved bits in status register. ++ */ ++ pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), ++ PCI_STATUS, 0xffff); ++ pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0), ++ PCI_LATENCY_TIMER, 0x80); ++ ++ /* ++ * Unlock configuration lock in PCI function configuration register. ++ */ ++ pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), ++ PCI_FUNCTION_CONFIG, ®16); ++ reg16 &= ~(PCI_FUNCTION_CFG_LOCK); ++ pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), ++ PCI_FUNCTION_CONFIG, reg16); ++ ++ printf("Enabled PCI 32bit Agent Mode\n"); ++} ++#else ++{ ++ volatile immap_t *immr; ++ volatile clk83xx_t *clk; ++ volatile law83xx_t *pci_law; ++ volatile pot83xx_t *pci_pot; ++ volatile pcictrl83xx_t *pci_ctrl; ++ volatile pciconf83xx_t *pci_conf; ++ ++ u8 val8, orig_i2c_bus; ++ u16 reg16; ++ u32 val32; ++ u32 dev; ++ ++ immr = (immap_t *) CFG_IMMR; ++ clk = (clk83xx_t *) & immr->clk; ++ pci_law = immr->sysconf.pcilaw; ++ pci_pot = immr->ios.pot; ++ pci_ctrl = immr->pci_ctrl; ++ pci_conf = immr->pci_conf; ++ /* ++ * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode ++ */ ++ val32 = clk->occr; ++ udelay(2000); ++#if defined(PCI_66M) ++ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; ++ printf("PCI clock is 66MHz\n"); ++#elif defined(PCI_33M) ++ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 | ++ OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR; ++ printf("PCI clock is 33MHz\n"); ++#else ++ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; ++ printf("PCI clock is 66MHz\n"); ++#endif ++ udelay(2000); ++ ++ /* ++ * Configure PCI Local Access Windows ++ */ ++ pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; ++ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; ++ ++ pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; ++ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; ++ ++ /* ++ * Configure PCI Outbound Translation Windows ++ */ ++ ++ /* PCI mem space - prefetch */ ++ pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; ++ pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; ++ pci_pot[0].pocmr = ++ POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); ++ ++ /* PCI mmio - non-prefetch mem space */ ++ pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; ++ pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; ++ pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); ++ ++ /* PCI IO space */ ++ pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; ++ pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; ++ pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); ++ ++ /* ++ * Configure PCI Inbound Translation Windows ++ */ ++ pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; ++ pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; ++ pci_ctrl[0].piebar1 = 0x0; ++ pci_ctrl[0].piwar1 = ++ PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | ++ PIWAR_IWS_2G; ++ ++ /* ++ * Assign PIB PMC slot to desired PCI bus ++ */ ++ ++ /* Switch temporarily to I2C bus #2 */ ++ orig_i2c_bus = i2c_get_bus_num(); ++ i2c_set_bus_num(1); ++ ++ val8 = 0; ++ i2c_write(0x23, 0x6, 1, &val8, 1); ++ i2c_write(0x23, 0x7, 1, &val8, 1); ++ val8 = 0xff; ++ i2c_write(0x23, 0x2, 1, &val8, 1); ++ i2c_write(0x23, 0x3, 1, &val8, 1); ++ ++ val8 = 0; ++ i2c_write(0x26, 0x6, 1, &val8, 1); ++ val8 = 0x34; ++ i2c_write(0x26, 0x7, 1, &val8, 1); ++ ++ val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */ ++ i2c_write(0x26, 0x2, 1, &val8, 1); ++ val8 = 0xff; ++ i2c_write(0x26, 0x3, 1, &val8, 1); ++ ++ val8 = 0; ++ i2c_write(0x27, 0x6, 1, &val8, 1); ++ i2c_write(0x27, 0x7, 1, &val8, 1); ++ val8 = 0xff; ++ i2c_write(0x27, 0x2, 1, &val8, 1); ++ val8 = 0xef; ++ i2c_write(0x27, 0x3, 1, &val8, 1); ++ asm("eieio"); ++ ++ /* Reset to original I2C bus */ ++ i2c_set_bus_num(orig_i2c_bus); ++ ++ /* ++ * Release PCI RST Output signal ++ */ ++ udelay(2000); ++ pci_ctrl[0].gcr = 1; ++ udelay(2000); ++ ++ hose[0].first_busno = 0; ++ hose[0].last_busno = 0xff; ++ ++ /* PCI memory prefetch space */ ++ pci_set_region(hose[0].regions + 0, ++ CFG_PCI_MEM_BASE, ++ CFG_PCI_MEM_PHYS, ++ CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); ++ ++ /* PCI memory space */ ++ pci_set_region(hose[0].regions + 1, ++ CFG_PCI_MMIO_BASE, ++ CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM); ++ ++ /* PCI IO space */ ++ pci_set_region(hose[0].regions + 2, ++ CFG_PCI_IO_BASE, ++ CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); ++ ++ /* System memory space */ ++ pci_set_region(hose[0].regions + 3, ++ CFG_PCI_SLV_MEM_LOCAL, ++ CFG_PCI_SLV_MEM_BUS, ++ CFG_PCI_SLV_MEM_SIZE, ++ PCI_REGION_MEM | PCI_REGION_MEMORY); ++ ++ hose[0].region_count = 4; ++ ++ pci_setup_indirect(&hose[0], ++ (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); ++ ++ pci_register_hose(hose); ++ ++ /* ++ * Write command register ++ */ ++ reg16 = 0xff; ++ dev = PCI_BDF(0, 0, 0); ++ pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16); ++ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; ++ pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16); ++ ++ /* ++ * Clear non-reserved bits in status register. ++ */ ++ pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff); ++ pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); ++ pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); ++ ++ printf("PCI 32bit bus on PMC2 & PMC3\n"); ++ ++ /* ++ * Hose scan. ++ */ ++ hose->last_busno = pci_hose_scan(hose); ++} ++#endif /* CONFIG_PCISLAVE */ ++ ++#ifdef CONFIG_OF_FLAT_TREE ++void ++ft_pci_setup(void *blob, bd_t *bd) ++{ ++ u32 *p; ++ int len; ++ ++ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); ++ if (p != NULL) { ++ p[0] = hose[0].first_busno; ++ p[1] = hose[0].last_busno; ++ } ++} ++#endif /* CONFIG_OF_FLAT_TREE */ ++#endif /* CONFIG_PCI */ +diff --git a/board/mpc832xemds/u-boot.lds b/board/mpc832xemds/u-boot.lds +new file mode 100644 +index 0000000..937c87a +--- /dev/null ++++ b/board/mpc832xemds/u-boot.lds +@@ -0,0 +1,123 @@ ++/* ++ * (C) Copyright 2006 ++ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++OUTPUT_ARCH(powerpc) ++SECTIONS ++{ ++ /* Read-only sections, merged into text segment: */ ++ . = + SIZEOF_HEADERS; ++ .interp : { *(.interp) } ++ .hash : { *(.hash) } ++ .dynsym : { *(.dynsym) } ++ .dynstr : { *(.dynstr) } ++ .rel.text : { *(.rel.text) } ++ .rela.text : { *(.rela.text) } ++ .rel.data : { *(.rel.data) } ++ .rela.data : { *(.rela.data) } ++ .rel.rodata : { *(.rel.rodata) } ++ .rela.rodata : { *(.rela.rodata) } ++ .rel.got : { *(.rel.got) } ++ .rela.got : { *(.rela.got) } ++ .rel.ctors : { *(.rel.ctors) } ++ .rela.ctors : { *(.rela.ctors) } ++ .rel.dtors : { *(.rel.dtors) } ++ .rela.dtors : { *(.rela.dtors) } ++ .rel.bss : { *(.rel.bss) } ++ .rela.bss : { *(.rela.bss) } ++ .rel.plt : { *(.rel.plt) } ++ .rela.plt : { *(.rela.plt) } ++ .init : { *(.init) } ++ .plt : { *(.plt) } ++ .text : ++ { ++ cpu/mpc83xx/start.o (.text) ++ *(.text) ++ *(.fixup) ++ *(.got1) ++ . = ALIGN(16); ++ *(.rodata) ++ *(.rodata1) ++ *(.rodata.str1.4) ++ *(.eh_frame) ++ } ++ .fini : { *(.fini) } =0 ++ .ctors : { *(.ctors) } ++ .dtors : { *(.dtors) } ++ ++ /* Read-write section, merged into data segment: */ ++ . = (. + 0x0FFF) & 0xFFFFF000; ++ _erotext = .; ++ PROVIDE (erotext = .); ++ .reloc : ++ { ++ *(.got) ++ _GOT2_TABLE_ = .; ++ *(.got2) ++ _FIXUP_TABLE_ = .; ++ *(.fixup) ++ } ++ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; ++ __fixup_entries = (. - _FIXUP_TABLE_) >> 2; ++ ++ .data : ++ { ++ *(.data) ++ *(.data1) ++ *(.sdata) ++ *(.sdata2) ++ *(.dynamic) ++ CONSTRUCTORS ++ } ++ _edata = .; ++ PROVIDE (edata = .); ++ ++ . = .; ++ __u_boot_cmd_start = .; ++ .u_boot_cmd : { *(.u_boot_cmd) } ++ __u_boot_cmd_end = .; ++ ++ ++ . = .; ++ __start___ex_table = .; ++ __ex_table : { *(__ex_table) } ++ __stop___ex_table = .; ++ ++ . = ALIGN(4096); ++ __init_begin = .; ++ .text.init : { *(.text.init) } ++ .data.init : { *(.data.init) } ++ . = ALIGN(4096); ++ __init_end = .; ++ ++ __bss_start = .; ++ .bss : ++ { ++ *(.sbss) *(.scommon) ++ *(.dynbss) ++ *(.bss) ++ *(COMMON) ++ } ++ _end = . ; ++ PROVIDE (end = .); ++} ++ENTRY(_start) +diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c +index 1b51078..bc61219 100644 +--- a/cpu/mpc83xx/cpu.c ++++ b/cpu/mpc83xx/cpu.c +@@ -92,6 +92,22 @@ int checkcpu(void) + case SPR_8360_REV12: + puts("MPC8360, "); + break; ++ case SPR_8323E_REV10: ++ case SPR_8323E_REV11: ++ puts("MPC8323E, "); ++ break; ++ case SPR_8323_REV10: ++ case SPR_8323_REV11: ++ puts("MPC8323, "); ++ break; ++ case SPR_8321E_REV10: ++ case SPR_8321E_REV11: ++ puts("MPC8321E, "); ++ break; ++ case SPR_8321_REV10: ++ case SPR_8321_REV11: ++ puts("MPC8321, "); ++ break; + default: + puts("Rev: Unknown\n"); + return -1; /* Not sure what this is */ +diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c +index 7574fab..eb256e5 100644 +--- a/cpu/mpc83xx/cpu_init.c ++++ b/cpu/mpc83xx/cpu_init.c +@@ -119,6 +119,11 @@ void cpu_init_f (volatile immap_t * im) + #ifdef CFG_SICRL + im->sysconf.sicrl = CFG_SICRL; + #endif ++ /* DDR control driver register */ ++#ifdef CFG_DDRCDR ++ im->sysconf.ddrcdr = CFG_DDRCDR; ++#endif ++ + #ifdef CONFIG_QE + /* Config QE ioports */ + config_qe_ioports(); +diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c +index 40ba6b0..9fd1bf1 100644 +--- a/cpu/mpc83xx/speed.c ++++ b/cpu/mpc83xx/speed.c +@@ -107,15 +107,19 @@ int get_clocks(void) + #endif + u32 core_clk; + u32 i2c1_clk; ++#if !defined(CONFIG_MPC832X) + u32 i2c2_clk; ++#endif + u32 enc_clk; + u32 lbiu_clk; + u32 lclk_clk; + u32 ddr_clk; +-#if defined (CONFIG_MPC8360) ++#if defined(CONFIG_MPC8360) ++ u32 ddr_sec_clk; ++#endif ++#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) + u32 qepmf; + u32 qepdf; +- u32 ddr_sec_clk; + u32 qe_clk; + u32 brg_clk; + #endif +@@ -227,10 +231,12 @@ int get_clocks(void) + return -9; + } + #endif +-#if defined (CONFIG_MPC8360) ++#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) + i2c1_clk = csb_clk; + #endif ++#if !defined(CONFIG_MPC832X) + i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ ++#endif + + switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { + case 0: +@@ -249,12 +255,9 @@ int get_clocks(void) + /* unkown SCCR_ENCCM value */ + return -6; + } +-#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) ++ + lbiu_clk = csb_clk * + (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); +-#else +-#error Unknown MPC83xx chip +-#endif + lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; + switch (lcrr) { + case 2: +@@ -266,17 +269,14 @@ int get_clocks(void) + /* unknown lcrr */ + return -10; + } +-#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360) ++ + ddr_clk = csb_clk * + (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT)); + corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT; +-#if defined (CONFIG_MPC8360) ++#if defined(CONFIG_MPC8360) + ddr_sec_clk = csb_clk * (1 + + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); + #endif +-#else +-#error Unknown MPC83xx chip +-#endif + + corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5); + if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) { +@@ -306,7 +306,7 @@ int get_clocks(void) + return -12; + } + +-#if defined (CONFIG_MPC8360) ++#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) + qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT; + qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT; + qe_clk = (pci_sync_in * qepmf) / (1 + qepdf); +@@ -322,13 +322,17 @@ int get_clocks(void) + #endif + gd->core_clk = core_clk; + gd->i2c1_clk = i2c1_clk; ++#if !defined(CONFIG_MPC832X) + gd->i2c2_clk = i2c2_clk; ++#endif + gd->enc_clk = enc_clk; + gd->lbiu_clk = lbiu_clk; + gd->lclk_clk = lclk_clk; + gd->ddr_clk = ddr_clk; +-#if defined (CONFIG_MPC8360) ++#if defined(CONFIG_MPC8360) + gd->ddr_sec_clk = ddr_sec_clk; ++#endif ++#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) + gd->qe_clk = qe_clk; + gd->brg_clk = brg_clk; + #endif +@@ -352,18 +356,21 @@ int print_clock_conf(void) + printf("Clock configuration:\n"); + printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000); + printf(" Core: %4d MHz\n", gd->core_clk / 1000000); +-#if defined (CONFIG_MPC8360) ++#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) + printf(" QE: %4d MHz\n", gd->qe_clk / 1000000); ++ printf(" BRG: %4d MHz\n", gd->brg_clk / 1000000); + #endif + printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000); + printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000); + printf(" DDR: %4d MHz\n", gd->ddr_clk / 1000000); +-#if defined (CONFIG_MPC8360) ++#if defined(CONFIG_MPC8360) + printf(" DDR Secondary: %4d MHz\n", gd->ddr_sec_clk / 1000000); + #endif + printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000); + printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000); ++#if !defined(CONFIG_MPC832X) + printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000); ++#endif + #if defined(CONFIG_MPC8349) + printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000); + printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000); +diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h +index f7f8ed0..0bcd0a9 100644 +--- a/drivers/qe/qe.h ++++ b/drivers/qe/qe.h +@@ -30,7 +30,7 @@ + #define UCC_MAX_NUM 8 + + #define QE_DATAONLY_BASE (uint)(128) +-#define QE_DATAONLY_SIZE ((uint)(0xc000) - QE_DATAONLY_BASE) ++#define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE) + + /* QE threads SNUM + */ +diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c +index c44a5be..aea455b 100644 +--- a/drivers/q |