diff options
Diffstat (limited to 'packages')
47 files changed, 1815 insertions, 2496 deletions
diff --git a/packages/cmake/cmake-native_2.4.8.bb b/packages/cmake/cmake-native_2.4.8.bb index 1a56fa40e0..02bc3aed48 100644 --- a/packages/cmake/cmake-native_2.4.8.bb +++ b/packages/cmake/cmake-native_2.4.8.bb @@ -1,4 +1,3 @@ -CMAKE_MAJOR_VERSION="2.4" require cmake.inc inherit native diff --git a/packages/cmake/cmake.inc b/packages/cmake/cmake.inc index 5190b6233f..d046c84858 100644 --- a/packages/cmake/cmake.inc +++ b/packages/cmake/cmake.inc @@ -3,9 +3,10 @@ DESCRIPTION = "A cross-platform, open-source make system" HOMEPAGE = "http://www.cmake.org/" -LICENSE = "Berkely-style license" +LICENSE = "Berkeley-style license" SECTION = "console/utils" +CMAKE_MAJOR_VERSION = "${@bb.data.getVar('PV',d,1).split('.')[0]}.${@bb.data.getVar('PV',d,1).split('.')[1]}" SRC_URI = "http://www.cmake.org/files/v${CMAKE_MAJOR_VERSION}/cmake-${PV}.tar.gz" inherit autotools diff --git a/packages/cmake/cmake_2.4.8.bb b/packages/cmake/cmake_2.4.8.bb index 619aea9701..68f03c17a9 100644 --- a/packages/cmake/cmake_2.4.8.bb +++ b/packages/cmake/cmake_2.4.8.bb @@ -1,2 +1 @@ -CMAKE_MAJOR_VERSION="2.4" require cmake.inc diff --git a/packages/dfu-util/dfu-util-native_svn.bb b/packages/dfu-util/dfu-util-native_svn.bb index 457094df9e..6304fad55b 100644 --- a/packages/dfu-util/dfu-util-native_svn.bb +++ b/packages/dfu-util/dfu-util-native_svn.bb @@ -6,12 +6,12 @@ DEPENDS = "libusb-native usbpath-native" do_stage() { install -d ${STAGING_BINDIR_NATIVE} - install -m 0755 src/dfu-util ${STAGING_BINDIR_NATIVE}/ + install -m 0755 src/dfu-util ${STAGING_BINDIR_NATIVE}/dfu-util-${PV} } do_deploy() { - install -d ${DEPLOY_DIR_IMAGE} - install -m 0755 src/dfu-util_static ${DEPLOY_DIR_IMAGE}/dfu-util + install -d ${DEPLOY_DIR_TOOLS} + install -m 0755 src/dfu-util_static ${DEPLOY_DIR_TOOLS}/dfu-util-${PV} } addtask deploy before do_package after do_install diff --git a/packages/dfu-util/dfu-util_svn.bb b/packages/dfu-util/dfu-util_svn.bb index 1f34a5bc24..2e1afd55b1 100644 --- a/packages/dfu-util/dfu-util_svn.bb +++ b/packages/dfu-util/dfu-util_svn.bb @@ -1,9 +1,9 @@ DESCRIPTION = "USB Device Firmware Upgrade utility" SECTION = "devel" -AUTHOR = "Harald Welte" +AUTHOR = "Harald Welte <laforge@openmoko.org>" LICENSE = "GPL" PV = "0.1+svnr${SRCREV}" -PR = "r0" +PR = "r1" DEPENDS = "libusb usbpath" diff --git a/packages/ezx/ezx-boot-usb-native.inc b/packages/ezx/ezx-boot-usb-native.inc new file mode 100644 index 0000000000..e2ebb52df4 --- /dev/null +++ b/packages/ezx/ezx-boot-usb-native.inc @@ -0,0 +1,32 @@ +DESCRIPTION = "Boots a Motorola EZX device with a user supplied kernel zImage" +DEPENDS = "libusb-native" +SECTION = "devel" +AUTHOR = "Harald Welte <laforge@openezx.org>" +LICENSE = "GPL" + +SRC_URI = "\ + svn://svn.openezx.org/trunk/src/host;module=boot_usb;proto=http \ + file://asm-arm \ +" +S = "${WORKDIR}/boot_usb" + +inherit native + +do_compile() { + ${CC} -I${WORKDIR} ${CFLAGS} ${LDFLAGS} -lusb -o ezx-boot-usb boot_usb.c +} + +do_deploy() { + install -d ${DEPLOY_DIR_TOOLS} + install -m 0755 ezx-boot-usb ${DEPLOY_DIR_TOOLS}/ezx-boot-usb-${PV} +} + +do_stage() { + : +} + +do_install() { + : +} + +addtask deploy before do_build after do_compile diff --git a/packages/ezx/ezx-boot-usb-native_0.1.0.bb b/packages/ezx/ezx-boot-usb-native_0.1.0.bb index 5919f28a11..b70aca3709 100644 --- a/packages/ezx/ezx-boot-usb-native_0.1.0.bb +++ b/packages/ezx/ezx-boot-usb-native_0.1.0.bb @@ -1,30 +1,7 @@ -DESCRIPTION = "Boots an EZX device with a user supplied kernel zImage" -DEPENDS = "libusb-native" -SECTION = "devel" -AUTHOR = "Harald Welte" -LICENSE = "GPL" +require ezx-boot-usb-native.inc PR = "r0" SRC_URI = "http://www.openezx.org/download/boot_usb-${PV}.tar.bz2" S = "${WORKDIR}/boot_usb-${PV}" inherit native - -do_compile() { - ${CC} ${CFLAGS} ${LDFLAGS} -lusb -o ezx-boot-usb boot_usb.c -} - -do_deploy() { - install -d ${DEPLOY_DIR_IMAGE} - install -m 0755 ezx-boot-usb ${DEPLOY_DIR_IMAGE}/ezx-boot-usb -} - -do_stage() { - : -} - -do_install() { - : -} - -addtask deploy before do_build after do_compile diff --git a/packages/ezx/ezx-boot-usb-native_0.2.0.bb b/packages/ezx/ezx-boot-usb-native_0.2.0.bb index 6091e36d11..7c2883b5b7 100644 --- a/packages/ezx/ezx-boot-usb-native_0.2.0.bb +++ b/packages/ezx/ezx-boot-usb-native_0.2.0.bb @@ -1,31 +1,5 @@ -DESCRIPTION = "Boots a Motorola EZX device with a user supplied kernel zImage" -DEPENDS = "libusb-native" -SECTION = "devel" -AUTHOR = "Team OpenEZX <openezx-devel@lists.openezx.org>" -LICENSE = "GPL" -PR = "r0" +require ezx-boot-usb-native.inc SRC_URI = "http://www.openezx.org/download/boot_usb-${PV}.tar.bz2 \ file://asm-arm" S = "${WORKDIR}/boot_usb-${PV}" - -inherit native - -do_compile() { - ${CC} ${CFLAGS} -I${WORKDIR} ${LDFLAGS} -lusb -o ezx-boot-usb boot_usb.c -} - -do_deploy() { - install -d ${DEPLOY_DIR_IMAGE} - install -m 0755 ezx-boot-usb ${DEPLOY_DIR_IMAGE}/ezx-boot-usb -} - -do_stage() { - : -} - -do_install() { - : -} - -addtask deploy before do_build after do_compile diff --git a/packages/ezx/ezx-boot-usb-native_svn.bb b/packages/ezx/ezx-boot-usb-native_svn.bb index 64e8a486e0..6ab4263dba 100644 --- a/packages/ezx/ezx-boot-usb-native_svn.bb +++ b/packages/ezx/ezx-boot-usb-native_svn.bb @@ -1,35 +1,5 @@ -DESCRIPTION = "Boots an EZX device with a user supplied kernel zImage" -DEPENDS = "libusb-native" -SECTION = "devel" -AUTHOR = "Harald Welte" -LICENSE = "GPL" -PR = "r1" +require ezx-boot-usb-native.inc DEFAULT_PREFERENCE = "-1" -REV = "1922" -PV = "0.1.0+r${REV}" - -SRC_URI = "svn://svn.openezx.org/trunk/src/host;module=boot_usb;proto=http;rev=${REV}" -S = "${WORKDIR}/boot_usb" - -inherit native - -do_compile() { - ${CC} ${CFLAGS} ${LDFLAGS} -lusb -o ezx-boot-usb boot_usb.c -} - -do_deploy() { - install -d ${DEPLOY_DIR_IMAGE} - install -m 0755 ezx-boot-usb ${DEPLOY_DIR_IMAGE}/ezx-boot-usb -} - -do_stage() { - : -} - -do_install() { - : -} - -addtask deploy before do_build after do_compile +PV = "0.2.0+r${SRCREV}" diff --git a/packages/freesmartphone/frameworkd/frameworkd.conf b/packages/freesmartphone/frameworkd/frameworkd.conf index e69de29bb2..8b13789179 100644 --- a/packages/freesmartphone/frameworkd/frameworkd.conf +++ b/packages/freesmartphone/frameworkd/frameworkd.conf @@ -0,0 +1 @@ + diff --git a/packages/freesmartphone/frameworkd/om-gta02/frameworkd.conf b/packages/freesmartphone/frameworkd/om-gta02/frameworkd.conf index 0076639f98..b38425129f 100644 --- a/packages/freesmartphone/frameworkd/om-gta02/frameworkd.conf +++ b/packages/freesmartphone/frameworkd/om-gta02/frameworkd.conf @@ -1,8 +1,15 @@ [idlenotifier] -# don't read from accellerometers for now +# don't read from accellerometers for GTA02 ignoreinput=2,3 [input] -# don't read from accellerometers for now +# don't read from accellerometers for GTA02 ignoreinput=2,3 +[ophoned] +# GTA02 has TI Calypso +modemtype = ti_calypso + +[opreferencesd] +rootdir = +../etc/freesmartphone/opreferences:/etc/freesmartphone/opreferences:/usr/etc/freesmartphone/opreferences diff --git a/packages/freesmartphone/frameworkd_git.bb b/packages/freesmartphone/frameworkd_git.bb index 53ea10f0fb..4d3e498f9e 100644 --- a/packages/freesmartphone/frameworkd_git.bb +++ b/packages/freesmartphone/frameworkd_git.bb @@ -5,7 +5,7 @@ SECTION = "console/network" DEPENDS = "python-cython-native python-pyrex-native" LICENSE = "GPL" PV = "0.8.0+gitr${SRCREV}" -PR = "r0" +PR = "r1" inherit distutils update-rc.d diff --git a/packages/linux/linux-ml403-slab-2.6.x_git.bb b/packages/linux/linux-ml403-slab-2.6.x_git.bb deleted file mode 100644 index ad823c2aa6..0000000000 --- a/packages/linux/linux-ml403-slab-2.6.x_git.bb +++ /dev/null @@ -1,80 +0,0 @@ -#Kernel for the xilinx-ml403 board using SecretLabs git tree -# Copyright (C) 2007, Stelios Koroneos - Digital OPSiS, All Rights Reserved -# Released under the MIT license (see packages/COPYING) -SECTION = "kernel" -DESCRIPTION = "Linux kernel for Xilinx ML403 Virtex 4 fpga board" -LICENSE = "GPL" -PR = "r2" -PV = "2.6+git${SRCDATE}" - -COMPATIBLE_MACHINE = "xilinx-ml403" - -SRC_URI = "file://xilinx-ml403_defconfig " - -inherit kernel xilinx-bsp - -S = "${WORKDIR}/linux-2.6" - - -FILES_kernel-image = "/boot/zImage.elf" - -export OS = "Linux" -ARCH = "ppc" -KERNEL_IMAGETYPE = "zImage" -KERNEL_OUTPUT = "arch/ppc/boot/images/zImage.elf" - -#make sure git-native gets build before as -python __anonymous () { - - import bb - - - depends = bb.data.getVarFlag('do_fetch', 'depends', d) or "" - depends = depends + " git-native:do_populate_staging" - bb.data.setVarFlag('do_fetch', 'depends', depends, d) - -} - - -do_fetch () { - - cd ${WORKDIR} - ${STAGING_BINDIR_NATIVE}/git clone git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git - cd linux-2.6 - ${STAGING_BINDIR_NATIVE}/git clone git://git.secretlab.ca/git/linux-2.6-virtex.git master -} - - - -do_configure() { - - install -m 644 ${WORKDIR}/xilinx-ml403_defconfig ${S}/.config - make ARCH=${ARCH} oldconfig -} - -do_stage_append () { -#need ppc platforms includes + friends in order for external kernel modules to compile as headers a$ - - install -d ${STAGING_KERNEL_DIR}/arch/ - cp -pPR arch/ppc ${STAGING_KERNEL_DIR}/arch/ - cp -pPR arch/powerpc ${STAGING_KERNEL_DIR}/arch/ - - install -d ${STAGING_KERNEL_DIR}/include/asm - cp -pPR include/asm-powerpc ${STAGING_KERNEL_DIR}/include/ - cp -pPR include/asm-ppc ${STAGING_KERNEL_DIR}/include/ -} - - - -do_deploy() { - install -d ${DEPLOY_DIR_IMAGE} - install -m 0644 arch/${ARCH}/boot/images/${KERNEL_IMAGETYPE}.elf \ - ${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${PV}-${MACHINE}-${DATETIME} -} - -#seems like 2.6.21 kernel images have moved (or is this only for the Denx kernel ?) -#so we need to copy the kernel image where kernel.bbclass expects it to be -do_install_prepend() { - install -m 0644 arch/${ARCH}/boot/images/${KERNEL_IMAGETYPE}.elf \ - arch/${ARCH}/boot/${KERNEL_IMAGETYPE} -} diff --git a/packages/linux/linux-omap2-git/beagleboard/0001-ARM-OMAP-SmartReflex-driver.patch b/packages/linux/linux-omap2-git/beagleboard/0001-ARM-OMAP-SmartReflex-driver.patch deleted file mode 100644 index 550a4f58be..0000000000 --- a/packages/linux/linux-omap2-git/beagleboard/0001-ARM-OMAP-SmartReflex-driver.patch +++ /dev/null @@ -1,1002 +0,0 @@ -From: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> -To: linux-omap@vger.kernel.org -Cc: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> -Subject: [PATCH 1/3] ARM: OMAP: SmartReflex driver, reference source and header files -Date: Mon, 2 Jun 2008 14:30:12 +0300 - -The following patch set integrates TI's SmartReflex driver. SmartReflex is a -module that adjusts OMAP3 VDD1 and VDD2 operating voltages around the nominal -values of current operating point depending on silicon characteristics and -operating conditions. - -The driver creates two sysfs entries into /sys/power/ named "sr_vdd1_autocomp" -and "sr_vdd2_autocomp" which can be used to activate SmartReflex modules 1 and -2. - -Use the following commands to enable SmartReflex: - -echo -n 1 > /sys/power/sr_vdd1_autocomp -echo -n 1 > /sys/power/sr_vdd2_autocomp - -To disable: - -echo -n 0 > /sys/power/sr_vdd1_autocomp -echo -n 0 > /sys/power/sr_vdd2_autocomp - -This particular patch adds the TI reference source and header files for -SmartReflex. Only modifications include minor styling to pass checkpatch.pl -test. - -Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> ---- - arch/arm/mach-omap2/smartreflex.c | 815 +++++++++++++++++++++++++++++++++++++ - arch/arm/mach-omap2/smartreflex.h | 136 ++++++ - 2 files changed, 951 insertions(+), 0 deletions(-) - create mode 100644 arch/arm/mach-omap2/smartreflex.c - create mode 100644 arch/arm/mach-omap2/smartreflex.h - -diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c -new file mode 100644 -index 0000000..dae7460 ---- /dev/null -+++ b/arch/arm/mach-omap2/smartreflex.c -@@ -0,0 +1,815 @@ -+/* -+ * linux/arch/arm/mach-omap3/smartreflex.c -+ * -+ * OMAP34XX SmartReflex Voltage Control -+ * -+ * Copyright (C) 2007 Texas Instruments, Inc. -+ * Lesly A M <x0080970@ti.com> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+ -+#include <linux/kernel.h> -+#include <linux/init.h> -+#include <linux/interrupt.h> -+#include <linux/module.h> -+#include <linux/delay.h> -+#include <linux/err.h> -+#include <linux/clk.h> -+#include <linux/sysfs.h> -+ -+#include <asm/arch/prcm.h> -+#include <asm/arch/power_companion.h> -+#include <linux/io.h> -+ -+#include "prcm-regs.h" -+#include "smartreflex.h" -+ -+ -+/* #define DEBUG_SR 1 */ -+#ifdef DEBUG_SR -+# define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__ ,\ -+ ## args) -+#else -+# define DPRINTK(fmt, args...) -+#endif -+ -+struct omap_sr{ -+ int srid; -+ int is_sr_reset; -+ int is_autocomp_active; -+ struct clk *fck; -+ u32 req_opp_no; -+ u32 opp1_nvalue, opp2_nvalue, opp3_nvalue, opp4_nvalue, opp5_nvalue; -+ u32 senp_mod, senn_mod; -+ u32 srbase_addr; -+ u32 vpbase_addr; -+}; -+ -+static struct omap_sr sr1 = { -+ .srid = SR1, -+ .is_sr_reset = 1, -+ .is_autocomp_active = 0, -+ .srbase_addr = OMAP34XX_SR1_BASE, -+}; -+ -+static struct omap_sr sr2 = { -+ .srid = SR2, -+ .is_sr_reset = 1, -+ .is_autocomp_active = 0, -+ .srbase_addr = OMAP34XX_SR2_BASE, -+}; -+ -+static inline void sr_write_reg(struct omap_sr *sr, int offset, u32 value) -+{ -+ omap_writel(value, sr->srbase_addr + offset); -+} -+ -+static inline void sr_modify_reg(struct omap_sr *sr, int offset, u32 mask, -+ u32 value) -+{ -+ u32 reg_val; -+ -+ reg_val = omap_readl(sr->srbase_addr + offset); -+ reg_val &= ~mask; -+ reg_val |= value; -+ -+ omap_writel(reg_val, sr->srbase_addr + offset); -+} -+ -+static inline u32 sr_read_reg(struct omap_sr *sr, int offset) -+{ -+ return omap_readl(sr->srbase_addr + offset); -+} -+ -+ -+#ifndef USE_EFUSE_VALUES -+static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen) -+{ -+ u32 gn, rn, mul; -+ -+ for (gn = 0; gn < GAIN_MAXLIMIT; gn++) { -+ mul = 1 << (gn + 8); -+ rn = mul / sensor; -+ if (rn < R_MAXLIMIT) { -+ *sengain = gn; -+ *rnsen = rn; -+ } -+ } -+} -+#endif -+ -+static int sr_clk_enable(struct omap_sr *sr) -+{ -+ if (clk_enable(sr->fck) != 0) { -+ printk(KERN_ERR "Could not enable sr%d_fck\n", sr->srid); -+ goto clk_enable_err; -+ } -+ -+ /* set fclk- active , iclk- idle */ -+ sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK, -+ SR_CLKACTIVITY_IOFF_FON); -+ -+ return 0; -+ -+clk_enable_err: -+ return -1; -+} -+ -+static int sr_clk_disable(struct omap_sr *sr) -+{ -+ /* set fclk, iclk- idle */ -+ sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK, -+ SR_CLKACTIVITY_IOFF_FOFF); -+ -+ clk_disable(sr->fck); -+ sr->is_sr_reset = 1; -+ -+ return 0; -+} -+ -+static void sr_set_nvalues(struct omap_sr *sr) -+{ -+#ifdef USE_EFUSE_VALUES -+ u32 n1, n2; -+#else -+ u32 senpval, sennval; -+ u32 senpgain, senngain; -+ u32 rnsenp, rnsenn; -+#endif -+ -+ if (sr->srid == SR1) { -+#ifdef USE_EFUSE_VALUES -+ /* Read values for VDD1 from EFUSE */ -+#else -+ /* since E-Fuse Values are not available, calculating the -+ * reciprocal of the SenN and SenP values for SR1 -+ */ -+ sr->senp_mod = 0x03; /* SenN-M5 enabled */ -+ sr->senn_mod = 0x03; -+ -+ /* for OPP5 */ -+ senpval = 0x848 + 0x330; -+ sennval = 0xacd + 0x330; -+ -+ cal_reciprocal(senpval, &senpgain, &rnsenp); -+ cal_reciprocal(sennval, &senngain, &rnsenn); -+ -+ sr->opp5_nvalue = -+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | -+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | -+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | -+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); -+ -+ /* for OPP4 */ -+ senpval = 0x727 + 0x2a0; -+ sennval = 0x964 + 0x2a0; -+ -+ cal_reciprocal(senpval, &senpgain, &rnsenp); -+ cal_reciprocal(sennval, &senngain, &rnsenn); -+ -+ sr->opp4_nvalue = -+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | -+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | -+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | -+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); -+ -+ /* for OPP3 */ -+ senpval = 0x655 + 0x200; -+ sennval = 0x85b + 0x200; -+ -+ cal_reciprocal(senpval, &senpgain, &rnsenp); -+ cal_reciprocal(sennval, &senngain, &rnsenn); -+ -+ sr->opp3_nvalue = -+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | -+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | -+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | -+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); -+ -+ /* for OPP2 */ -+ senpval = 0x3be + 0x1a0; -+ sennval = 0x506 + 0x1a0; -+ -+ cal_reciprocal(senpval, &senpgain, &rnsenp); -+ cal_reciprocal(sennval, &senngain, &rnsenn); -+ -+ sr->opp2_nvalue = -+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | -+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | -+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | -+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); -+ -+ /* for OPP1 */ -+ senpval = 0x28c + 0x100; -+ sennval = 0x373 + 0x100; -+ -+ cal_reciprocal(senpval, &senpgain, &rnsenp); -+ cal_reciprocal(sennval, &senngain, &rnsenn); -+ -+ sr->opp1_nvalue = -+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | -+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | -+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | -+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); -+ -+ sr_clk_enable(sr); -+ sr_write_reg(sr, NVALUERECIPROCAL, sr->opp3_nvalue); -+ sr_clk_disable(sr); -+ -+#endif -+ } else if (sr->srid == SR2) { -+#ifdef USE_EFUSE_VALUES -+ /* Read values for VDD2 from EFUSE */ -+#else -+ /* since E-Fuse Values are not available, calculating the -+ * reciprocal of the SenN and SenP values for SR2 -+ */ -+ sr->senp_mod = 0x03; -+ sr->senn_mod = 0x03; -+ -+ /* for OPP3 */ -+ senpval = 0x579 + 0x200; -+ sennval = 0x76f + 0x200; -+ -+ cal_reciprocal(senpval, &senpgain, &rnsenp); -+ cal_reciprocal(sennval, &senngain, &rnsenn); -+ -+ sr->opp3_nvalue = -+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | -+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | -+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | -+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); -+ -+ /* for OPP2 */ -+ senpval = 0x390 + 0x1c0; -+ sennval = 0x4f5 + 0x1c0; -+ -+ cal_reciprocal(senpval, &senpgain, &rnsenp); -+ cal_reciprocal(sennval, &senngain, &rnsenn); -+ -+ sr->opp2_nvalue = -+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | -+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | -+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | -+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); -+ -+ /* for OPP1 */ -+ senpval = 0x25d; -+ sennval = 0x359; -+ -+ cal_reciprocal(senpval, &senpgain, &rnsenp); -+ cal_reciprocal(sennval, &senngain, &rnsenn); -+ -+ sr->opp1_nvalue = -+ ((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) | -+ (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | -+ (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | -+ (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); -+ -+#endif -+ } -+ -+} -+ -+static void sr_configure_vp(int srid) -+{ -+ u32 vpconfig; -+ -+ if (srid == SR1) { -+ vpconfig = PRM_VP1_CONFIG_ERROROFFSET | PRM_VP1_CONFIG_ERRORGAIN -+ | PRM_VP1_CONFIG_INITVOLTAGE | PRM_VP1_CONFIG_TIMEOUTEN; -+ -+ PRM_VP1_CONFIG = vpconfig; -+ PRM_VP1_VSTEPMIN = PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN | -+ PRM_VP1_VSTEPMIN_VSTEPMIN; -+ -+ PRM_VP1_VSTEPMAX = PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX | -+ PRM_VP1_VSTEPMAX_VSTEPMAX; -+ -+ PRM_VP1_VLIMITTO = PRM_VP1_VLIMITTO_VDDMAX | -+ PRM_VP1_VLIMITTO_VDDMIN | PRM_VP1_VLIMITTO_TIMEOUT; -+ -+ PRM_VP1_CONFIG |= PRM_VP1_CONFIG_INITVDD; -+ PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_INITVDD; -+ -+ } else if (srid == SR2) { -+ vpconfig = PRM_VP2_CONFIG_ERROROFFSET | PRM_VP2_CONFIG_ERRORGAIN -+ | PRM_VP2_CONFIG_INITVOLTAGE | PRM_VP2_CONFIG_TIMEOUTEN; -+ -+ PRM_VP2_CONFIG = vpconfig; -+ PRM_VP2_VSTEPMIN = PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN | -+ PRM_VP2_VSTEPMIN_VSTEPMIN; -+ -+ PRM_VP2_VSTEPMAX = PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX | -+ PRM_VP2_VSTEPMAX_VSTEPMAX; -+ -+ PRM_VP2_VLIMITTO = PRM_VP2_VLIMITTO_VDDMAX | -+ PRM_VP2_VLIMITTO_VDDMIN | PRM_VP2_VLIMITTO_TIMEOUT; -+ -+ PRM_VP2_CONFIG |= PRM_VP2_CONFIG_INITVDD; -+ PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_INITVDD; -+ -+ } -+} -+ -+static void sr_configure_vc(void) -+{ -+ PRM_VC_SMPS_SA = -+ (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA1_SHIFT) | -+ (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA0_SHIFT); -+ -+ PRM_VC_SMPS_VOL_RA = (R_VDD2_SR_CONTROL << PRM_VC_SMPS_VOLRA1_SHIFT) | -+ (R_VDD1_SR_CONTROL << PRM_VC_SMPS_VOLRA0_SHIFT); -+ -+ PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL0_ON << PRM_VC_CMD_ON_SHIFT) | -+ (PRM_VC_CMD_VAL0_ONLP << PRM_VC_CMD_ONLP_SHIFT) | -+ (PRM_VC_CMD_VAL0_RET << PRM_VC_CMD_RET_SHIFT) | -+ (PRM_VC_CMD_VAL0_OFF << PRM_VC_CMD_OFF_SHIFT); -+ -+ PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL1_ON << PRM_VC_CMD_ON_SHIFT) | -+ (PRM_VC_CMD_VAL1_ONLP << PRM_VC_CMD_ONLP_SHIFT) | -+ (PRM_VC_CMD_VAL1_RET << PRM_VC_CMD_RET_SHIFT) | -+ (PRM_VC_CMD_VAL1_OFF << PRM_VC_CMD_OFF_SHIFT); -+ -+ PRM_VC_CH_CONF = PRM_VC_CH_CONF_CMD1 | PRM_VC_CH_CONF_RAV1; -+ -+ PRM_VC_I2C_CFG = PRM_VC_I2C_CFG_MCODE | PRM_VC_I2C_CFG_HSEN -+ | PRM_VC_I2C_CFG_SREN; -+ -+ /* Setup voltctrl and other setup times */ -+#ifdef CONFIG_SYSOFFMODE -+ PRM_VOLTCTRL = PRM_VOLTCTRL_AUTO_OFF | PRM_VOLTCTRL_AUTO_RET; -+ PRM_CLKSETUP = PRM_CLKSETUP_DURATION; -+ PRM_VOLTSETUP1 = (PRM_VOLTSETUP_TIME2 << PRM_VOLTSETUP_TIME2_OFFSET) | -+ (PRM_VOLTSETUP_TIME1 << PRM_VOLTSETUP_TIME1_OFFSET); -+ PRM_VOLTOFFSET = PRM_VOLTOFFSET_DURATION; -+ PRM_VOLTSETUP2 = PRM_VOLTSETUP2_DURATION; -+#else -+ PRM_VOLTCTRL |= PRM_VOLTCTRL_AUTO_RET; -+#endif -+ -+} -+ -+ -+static void sr_configure(struct omap_sr *sr) -+{ -+ u32 sys_clk, sr_clk_length = 0; -+ u32 sr_config; -+ u32 senp_en , senn_en; -+ -+ senp_en = sr->senp_mod; -+ senn_en = sr->senn_mod; -+ -+ sys_clk = prcm_get_system_clock_speed(); -+ -+ switch (sys_clk) { -+ case 12000: -+ sr_clk_length = SRCLKLENGTH_12MHZ_SYSCLK; -+ break; -+ case 13000: -+ sr_clk_length = SRCLKLENGTH_13MHZ_SYSCLK; -+ break; -+ case 19200: -+ sr_clk_length = SRCLKLENGTH_19MHZ_SYSCLK; -+ break; -+ case 26000: -+ sr_clk_length = SRCLKLENGTH_26MHZ_SYSCLK; -+ break; -+ case 38400: -+ sr_clk_length = SRCLKLENGTH_38MHZ_SYSCLK; -+ break; -+ default : -+ printk(KERN_ERR "Invalid sysclk value\n"); -+ break; -+ } -+ -+ DPRINTK(KERN_DEBUG "SR : sys clk %lu\n", sys_clk); -+ if (sr->srid == SR1) { -+ sr_config = SR1_SRCONFIG_ACCUMDATA | -+ (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | -+ SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN | -+ SRCONFIG_MINMAXAVG_EN | -+ (senn_en << SRCONFIG_SENNENABLE_SHIFT) | -+ (senp_en << SRCONFIG_SENPENABLE_SHIFT) | -+ SRCONFIG_DELAYCTRL; -+ -+ sr_write_reg(sr, SRCONFIG, sr_config); -+ -+ sr_write_reg(sr, AVGWEIGHT, SR1_AVGWEIGHT_SENPAVGWEIGHT | -+ SR1_AVGWEIGHT_SENNAVGWEIGHT); -+ -+ sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK | -+ SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK), -+ (SR1_ERRWEIGHT | SR1_ERRMAXLIMIT | SR1_ERRMINLIMIT)); -+ -+ } else if (sr->srid == SR2) { -+ sr_config = SR2_SRCONFIG_ACCUMDATA | -+ (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | -+ SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN | -+ SRCONFIG_MINMAXAVG_EN | -+ (senn_en << SRCONFIG_SENNENABLE_SHIFT) | -+ (senp_en << SRCONFIG_SENPENABLE_SHIFT) | -+ SRCONFIG_DELAYCTRL; -+ -+ sr_write_reg(sr, SRCONFIG, sr_config); -+ -+ sr_write_reg(sr, AVGWEIGHT, SR2_AVGWEIGHT_SENPAVGWEIGHT | -+ SR2_AVGWEIGHT_SENNAVGWEIGHT); -+ -+ sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK | -+ SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK), -+ (SR2_ERRWEIGHT | SR2_ERRMAXLIMIT | SR2_ERRMINLIMIT)); -+ -+ } -+ sr->is_sr_reset = 0; -+} -+ -+static void sr_enable(struct omap_sr *sr, u32 target_opp_no) -+{ -+ u32 nvalue_reciprocal, current_nvalue; -+ -+ sr->req_opp_no = target_opp_no; -+ -+ if (sr->srid == SR1) { -+ switch (target_opp_no) { -+ case 5: -+ nvalue_reciprocal = sr->opp5_nvalue; -+ break; -+ case 4: -+ nvalue_reciprocal = sr->opp4_nvalue; -+ break; -+ case 3: -+ nvalue_reciprocal = sr->opp3_nvalue; -+ break; -+ case 2: -+ nvalue_reciprocal = sr->opp2_nvalue; -+ break; -+ case 1: -+ nvalue_reciprocal = sr->opp1_nvalue; -+ break; -+ default: -+ nvalue_reciprocal = sr->opp3_nvalue; -+ break; -+ } -+ } else { -+ switch (target_opp_no) { -+ case 3: -+ nvalue_reciprocal = sr->opp3_nvalue; -+ break; -+ case 2: -+ nvalue_reciprocal = sr->opp2_nvalue; -+ break; -+ case 1: -+ nvalue_reciprocal = sr->opp1_nvalue; -+ break; -+ default: -+ nvalue_reciprocal = sr->opp3_nvalue; -+ break; -+ } -+ } -+ -+ current_nvalue = sr_read_reg(sr, NVALUERECIPROCAL); -+ -+ if (current_nvalue == nvalue_reciprocal) { -+ DPRINTK("System is already at the desired voltage level\n"); -+ return; -+ } -+ -+ sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal); -+ -+ /* Enable the interrupt */ -+ sr_modify_reg(sr, ERRCONFIG, -+ (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST), -+ (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST)); -+ -+ if (sr->srid == SR1) { -+ /* Enable VP1 */ -+ PRM_VP1_CONFIG |= PRM_VP1_CONFIG_VPENABLE; -+ } else if (sr->srid == SR2) { -+ /* Enable VP2 */ -+ PRM_VP2_CONFIG |= PRM_VP2_CONFIG_VPENABLE; -+ } -+ -+ /* SRCONFIG - enable SR */ -+ sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE); -+ -+} -+ -+static void sr_disable(struct omap_sr *sr) -+{ -+ sr->is_sr_reset = 1; -+ -+ /* SRCONFIG - disable SR */ -+ sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, ~SRCONFIG_SRENABLE); -+ -+ if (sr->srid == SR1) { -+ /* Enable VP1 */ -+ PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE; -+ } else if (sr->srid == SR2) { -+ /* Enable VP2 */ -+ PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE; -+ } -+} -+ -+ -+void sr_start_vddautocomap(int srid, u32 target_opp_no) -+{ -+ struct omap_sr *sr = NULL; -+ -+ if (srid == SR1) -+ sr = &sr1; -+ else if (srid == SR2) -+ sr = &sr2; -+ -+ if (sr->is_sr_reset == 1) { -+ sr_clk_enable(sr); -+ sr_configure(sr); -+ } -+ -+ if (sr->is_autocomp_active == 1) -+ DPRINTK(KERN_WARNING "SR%d: VDD autocomp is already active\n", -+ srid); -+ -+ sr->is_autocomp_active = 1; -+ sr_enable(sr, target_opp_no); -+} -+EXPORT_SYMBOL(sr_start_vddautocomap); -+ -+int sr_stop_vddautocomap(int srid) -+{ -+ struct omap_sr *sr = NULL; -+ -+ if (srid == SR1) -+ sr = &sr1; -+ else if (srid == SR2) -+ sr = &sr2; -+ -+ if (sr->is_autocomp_active == 1) { -+ sr_disable(sr); -+ sr_clk_disable(sr); -+ sr->is_autocomp_active = 0; -+ return SR_TRUE; -+ } else { -+ DPRINTK(KERN_WARNING "SR%d: VDD autocomp is not active\n", -+ srid); -+ return SR_FALSE; -+ } -+ -+} -+EXPORT_SYMBOL(sr_stop_vddautocomap); -+ -+void enable_smartreflex(int srid) -+{ -+ u32 target_opp_no = 0; -+ struct omap_sr *sr = NULL; -+ -+ if (srid == SR1) -+ sr = &sr1; -+ else if (srid == SR2) -+ sr = &sr2; -+ -+ if (sr->is_autocomp_active == 1) { -+ if (sr->is_sr_reset == 1) { -+ if (srid == SR1) { -+ /* Enable SR clks */ -+ CM_FCLKEN_WKUP |= SR1_CLK_ENABLE; -+ target_opp_no = get_opp_no(current_vdd1_opp); -+ -+ } else if (srid == SR2) { -+ /* Enable SR clks */ -+ CM_FCLKEN_WKUP |= SR2_CLK_ENABLE; -+ target_opp_no = get_opp_no(current_vdd2_opp); -+ } -+ -+ sr_configure(sr); -+ -+ sr_enable(sr, target_opp_no); -+ } -+ } -+} -+ -+void disable_smartreflex(int srid) -+{ -+ struct omap_sr *sr = NULL; -+ -+ if (srid == SR1) -+ sr = &sr1; -+ else if (srid == SR2) -+ sr = &sr2; -+ -+ if (sr->is_autocomp_active == 1) { -+ if (srid == SR1) { -+ /* Enable SR clk */ -+ CM_FCLKEN_WKUP |= SR1_CLK_ENABLE; -+ -+ } else if (srid == SR2) { -+ /* Enable SR clk */ -+ CM_FCLKEN_WKUP |= SR2_CLK_ENABLE; -+ } -+ -+ if (sr->is_sr_reset == 0) { -+ -+ sr->is_sr_reset = 1; -+ /* SRCONFIG - disable SR */ -+ sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, -+ ~SRCONFIG_SRENABLE); -+ -+ if (sr->srid == SR1) { -+ /* Disable SR clk */ -+ CM_FCLKEN_WKUP &= ~SR1_CLK_ENABLE; -+ /* Enable VP1 */ -+ PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE; -+ -+ } else if (sr->srid == SR2) { -+ /* Disable SR clk */ -+ CM_FCLKEN_WKUP &= ~SR2_CLK_ENABLE; -+ /* Enable VP2 */ -+ PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE; -+ } -+ } -+ } -+} -+ -+ -+/* Voltage Scaling using SR VCBYPASS */ -+int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel) -+{ -+ int ret; -+ int sr_status = 0; -+ u32 vdd, target_opp_no; -+ u32 vc_bypass_value; -+ u32 reg_addr = 0; -+ u32 loop_cnt = 0, retries_cnt = 0; -+ -+ vdd = get_vdd(target_opp); -+ target_opp_no = get_opp_no(target_opp); -+ -+ if (vdd == PRCM_VDD1) { -+ sr_status = sr_stop_vddautocomap(SR1); -+ -+ PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL_0 & ~PRM_VC_CMD_ON_MASK) | -+ (vsel << PRM_VC_CMD_ON_SHIFT); -+ reg_addr = R_VDD1_SR_CONTROL; -+ -+ } else if (vdd == PRCM_VDD2) { -+ sr_status = sr_stop_vddautocomap(SR2); -+ -+ PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL_1 & ~PRM_VC_CMD_ON_MASK) | -+ (vsel << PRM_VC_CMD_ON_SHIFT); -+ reg_addr = R_VDD2_SR_CONTROL; -+ } -+ -+ vc_bypass_value = (vsel << PRM_VC_BYPASS_DATA_SHIFT) | -+ (reg_addr << PRM_VC_BYPASS_REGADDR_SHIFT) | -+ (R_SRI2C_SLAVE_ADDR << PRM_VC_BYPASS_SLAVEADDR_SHIFT); -+ -+ PRM_VC_BYPASS_VAL = vc_bypass_value; -+ -+ PRM_VC_BYPASS_VAL |= PRM_VC_BYPASS_VALID; -+ -+ DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, PRM_VC_BYPASS_VAL); -+ DPRINTK("PRM_IRQST_MPU %X\n", PRM_IRQSTATUS_MPU); -+ -+ while ((PRM_VC_BYPASS_VAL & PRM_VC_BYPASS_VALID) != 0x0) { -+ ret = loop_wait(&loop_cnt, &retries_cnt, 10); -+ if (ret != PRCM_PASS) { -+ printk(KERN_INFO "Loop count exceeded in check SR I2C" -+ "write\n"); -+ return ret; -+ } -+ } -+ -+ omap_udelay(T2_SMPS_UPDATE_DELAY); -+ -+ if (sr_status) { -+ if (vdd == PRCM_VDD1) -+ sr_start_vddautocomap(SR1, target_opp_no); -+ else if (vdd == PRCM_VDD2) -+ sr_start_vddautocomap(SR2, target_opp_no); -+ } -+ -+ return SR_PASS; -+} -+ -+/* Sysfs interface to select SR VDD1 auto compensation */ -+static ssize_t omap_sr_vdd1_autocomp_show(struct kset *subsys, char *buf) -+{ -+ return sprintf(buf, "%d\n", sr1.is_autocomp_active); -+} -+ -+static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys, -+ const char *buf, size_t n) -+{ -+ u32 current_vdd1opp_no; -+ unsigned short value; -+ -+ if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) { -+ printk(KERN_ERR "sr_vdd1_autocomp: Invalid value\n"); -+ return -EINVAL; -+ } -+ -+ current_vdd1opp_no = get_opp_no(current_vdd1_opp); -+ -+ if (value == 0) -+ sr_stop_vddautocomap(SR1); -+ else -+ sr_start_vddautocomap(SR1, current_vdd1opp_no); -+ -+ return n; -+} -+ -+static struct subsys_attribute sr_vdd1_autocomp = { -+ .attr = { -+ .name = __stringify(sr_vdd1_autocomp), -+ .mode = 0644, -+ }, -+ .show = omap_sr_vdd1_autocomp_show, -+ .store = omap_sr_vdd1_autocomp_store, -+}; -+ -+/* Sysfs interface to select SR VDD2 auto compensation */ -+static ssize_t omap_sr_vdd2_autocomp_show(struct kset *subsys, char *buf) -+{ -+ return sprintf(buf, "%d\n", sr2.is_autocomp_active); -+} -+ -+static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys, -+ const char *buf, size_t n) -+{ -+ u32 current_vdd2opp_no; -+ unsigned short value; -+ -+ if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) { -+ printk(KERN_ERR "sr_vdd2_autocomp: Invalid value\n"); -+ return -EINVAL; -+ } -+ -+ current_vdd2opp_no = get_opp_no(current_vdd2_opp); -+ -+ if (value == 0) -+ sr_stop_vddautocomap(SR2); -+ else -+ sr_start_vddautocomap(SR2, current_vdd2opp_no); -+ -+ return n; -+} -+ -+static struct subsys_attribute sr_vdd2_autocomp = { -+ .attr = { -+ .name = __stringify(sr_vdd2_autocomp), -+ .mode = 0644, -+ }, -+ .show = omap_sr_vdd2_autocomp_show, -+ .store = omap_sr_vdd2_autocomp_store, -+}; -+ -+ -+ -+static int __init omap3_sr_init(void) -+{ -+ int ret = 0; -+ u8 RdReg; -+ -+#ifdef CONFIG_ARCH_OMAP34XX -+ sr1.fck = clk_get(NULL, "sr1_fck"); -+ if (IS_ERR(sr1.fck)) -+ printk(KERN_ERR "Could not get sr1_fck\n"); -+ -+ sr2.fck = clk_get(NULL, "sr2_fck"); -+ if (IS_ERR(sr2.fck)) -+ printk(KERN_ERR "Could not get sr2_fck\n"); -+#endif /* #ifdef CONFIG_ARCH_OMAP34XX */ -+ -+ /* Call the VPConfig, VCConfig, set N Values. */ -+ sr_set_nvalues(&sr1); -+ sr_configure_vp(SR1); -+ -+ sr_set_nvalues(&sr2); -+ sr_configure_vp(SR2); -+ -+ sr_configure_vc(); -+ -+ /* Enable SR on T2 */ -+ ret = t2_in(PM_RECEIVER, &RdReg, R_DCDC_GLOBAL_CFG); -+ RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX; -+ ret |= t2_out(PM_RECEIVER, RdReg, R_DCDC_GLOBAL_CFG); -+ -+ -+ printk(KERN_INFO "SmartReflex driver initialized\n"); -+ -+ ret = subsys_create_file(&power_subsys, &sr_vdd1_autocomp); -+ if (ret) -+ printk(KERN_ERR "subsys_create_file failed: %d\n", ret); -+ -+ ret = subsys_create_file(&power_subsys, &sr_vdd2_autocomp); -+ if (ret) -+ printk(KERN_ERR "subsys_create_file failed: %d\n", ret); -+ -+ return 0; -+} -+ -+arch_initcall(omap3_sr_init); -diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h -new file mode 100644 -index 0000000..62907ef ---- /dev/null -+++ b/arch/arm/mach-omap2/smartreflex.h -@@ -0,0 +1,136 @@ -+/* -+ * linux/arch/arm/mach-omap3/smartreflex.h -+ * -+ * Copyright (C) 2007 Texas Instruments, Inc. -+ * Lesly A M <x0080970@ti.com> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+ -+/* SR Modules */ -+#define SR1 1 -+#define SR2 2 -+ -+#define SR_FAIL 1 -+#define SR_PASS 0 -+ -+#define SR_TRUE 1 -+#define SR_FALSE 0 -+ -+#define GAIN_MAXLIMIT 16 -+#define R_MAXLIMIT 256 -+ -+#define SR1_CLK_ENABLE (0x1 << 6) -+#define SR2_CLK_ENABLE (0x1 << 7) -+ -+/* PRM_VP1_CONFIG */ -+#define PRM_VP1_CONFIG_ERROROFFSET (0x00 << 24) -+#define PRM_VP1_CONFIG_ERRORGAIN (0x20 << 16) -+ -+#define PRM_VP1_CONFIG_INITVOLTAGE (0x30 << 8) /* 1.2 volt */ -+#define PRM_VP1_CONFIG_TIMEOUTEN (0x1 << 3) -+#define PRM_VP1_CONFIG_INITVDD (0x1 << 2) -+#define PRM_VP1_CONFIG_FORCEUPDATE (0x1 << 1) -+#define PRM_VP1_CONFIG_VPENABLE (0x1 << 0) -+ -+/* PRM_VP1_VSTEPMIN */ -+#define PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN (0x01F4 << 8) -+#define PRM_VP1_VSTEPMIN_VSTEPMIN (0x01 << 0) -+ -+/* PRM_VP1_VSTEPMAX */ -+#define PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX (0x01F4 << 8) -+#define PRM_VP1_VSTEPMAX_VSTEPMAX (0x04 << 0) -+ -+/* PRM_VP1_VLIMITTO */ -+#define PRM_VP1_VLIMITTO_VDDMAX (0x3C << 24) -+#define PRM_VP1_VLIMITTO_VDDMIN (0x0 << 16) -+#define PRM_VP1_VLIMITTO_TIMEOUT (0xFFFF << 0) -+ -+/* PRM_VP2_CONFIG */ -+#define PRM_VP2_CONFIG_ERROROFFSET (0x00 << 24) -+#define PRM_VP2_CONFIG_ERRORGAIN (0x20 << 16) -+ -+#define PRM_VP2_CONFIG_INITVOLTAGE (0x30 << 8) /* 1.2 volt */ -+#define PRM_VP2_CONFIG_TIMEOUTEN (0x1 << 3) -+#define PRM_VP2_CONFIG_INITVDD (0x1 << 2) -+#define PRM_VP2_CONFIG_FORCEUPDATE (0x1 << 1) -+#define PRM_VP2_CONFIG_VPENABLE (0x1 << 0) -+ -+/* PRM_VP2_VSTEPMIN */ -+#define PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN (0x01F4 << 8) -+#define PRM_VP2_VSTEPMIN_VSTEPMIN (0x01 << 0) -+ -+/* PRM_VP2_VSTEPMAX */ -+#define PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX (0x01F4 << 8) -+#define PRM_VP2_VSTEPMAX_VSTEPMAX (0x04 << 0) -+ -+/* PRM_VP2_VLIMITTO */ -+#define PRM_VP2_VLIMITTO_VDDMAX (0x2C << 24) -+#define PRM_VP2_VLIMITTO_VDDMIN (0x0 << 16) -+#define PRM_VP2_VLIMITTO_TIMEOUT (0xFFFF << 0) -+ -+/* SRCONFIG */ -+#define SR1_SRCONFIG_ACCUMDATA (0x1F4 << 22) -+#define SR2_SRCONFIG_ACCUMDATA (0x1F4 << 22) -+ -+#define SRCLKLENGTH_12MHZ_SYSCLK 0x3C -+#define SRCLKLENGTH_13MHZ_SYSCLK 0x41 -+#define SRCLKLENGTH_19MHZ_SYSCLK 0x60 -+#define SRCLKLENGTH_26MHZ_SYSCLK 0x82 -+#define SRCLKLENGTH_38MHZ_SYSCLK 0xC0 -+ -+#define SRCONFIG_SRCLKLENGTH_SHIFT 12 -+#define SRCONFIG_SENNENABLE_SHIFT 5 -+#define SRCONFIG_SENPENABLE_SHIFT 3 -+ -+#define SRCONFIG_SRENABLE (0x01 << 11) -+#define SRCONFIG_SENENABLE (0x01 << 10) -+#define SRCONFIG_ERRGEN_EN (0x01 << 9) -+#define SRCONFIG_MINMAXAVG_EN (0x01 << 8) -+ -+#define SRCONFIG_DELAYCTRL (0x01 << 2) -+#define SRCONFIG_CLKCTRL (0x00 << 0) -+ -+/* AVGWEIGHT */ -+#define SR1_AVGWEIGHT_SENPAVGWEIGHT (0x03 << 2) -+#define SR1_AVGWEIGHT_SENNAVGWEIGHT (0x03 << 0) -+ -+#define SR2_AVGWEIGHT_SENPAVGWEIGHT (0x01 << 2) -+#define SR2_AVGWEIGHT_SENNAVGWEIGHT (0x01 << 0) -+ -+/* NVALUERECIPROCAL */ -+#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20 -+#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16 -+#define NVALUERECIPROCAL_RNSENP_SHIFT 8 -+#define NVALUERECIPROCAL_RNSENN_SHIFT 0 -+ -+/* ERRCONFIG */ -+#define SR_CLKACTIVITY_MASK (0x03 << 20) -+#define SR_ERRWEIGHT_MASK (0x07 << 16) -+#define SR_ERRMAXLIMIT_MASK (0xFF << 8) -+#define SR_ERRMINLIMIT_MASK (0xFF << 0) -+ -+#define SR_CLKACTIVITY_IOFF_FOFF (0x00 << 20) -+#define SR_CLKACTIVITY_IOFF_FON (0x02 << 20) -+ -+#define ERRCONFIG_VPBOUNDINTEN (0x1 << 31) -+#define ERRCONFIG_VPBOUNDINTST (0x1 << 30) -+ -+#define SR1_ERRWEIGHT (0x07 << 16) -+#define SR1_ERRMAXLIMIT (0x02 << 8) -+#define SR1_ERRMINLIMIT (0xFA << 0) -+ -+#define SR2_ERRWEIGHT (0x07 << 16) -+#define SR2_ERRMAXLIMIT (0x02 << 8) -+#define SR2_ERRMINLIMIT (0xF9 << 0) -+ -+extern u32 current_vdd1_opp; -+extern u32 current_vdd2_opp; -+extern struct kset power_subsys; -+ -+extern inline int loop_wait(u32 *lcnt, u32 *rcnt, u32 delay); -+extern void omap_udelay(u32 udelay); -+ --- -1.5.4.3 diff --git a/packages/linux/linux-omap2-git/beagleboard/0002-ARM-OMAP-SmartReflex-driver.patch b/packages/linux/linux-omap2-git/beagleboard/0002-ARM-OMAP-SmartReflex-driver.patch deleted file mode 100644 index 8e609395a0..0000000000 --- a/packages/linux/linux-omap2-git/beagleboard/0002-ARM-OMAP-SmartReflex-driver.patch +++ /dev/null @@ -1,278 +0,0 @@ -From: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> -To: linux-omap@vger.kernel.org -Cc: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> -Subject: [PATCH 2/3] ARM: OMAP: SmartReflex driver: added required register and bit definitions. -Date: Fri, 6 Jun 2008 12:49:48 +0300 - -Added new register and bit definitions to enable Smartreflex driver integration. -Also PRM_VC_SMPS_SA bit definitions' naming was changed to match the naming of -other similar bit definitions. - -Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> ---- - arch/arm/mach-omap2/prm-regbits-34xx.h | 27 ++++++-- - arch/arm/mach-omap2/smartreflex.h | 124 ++++++++++++++++++++++++++++++- - include/asm-arm/arch-omap/control.h | 19 +++++ - include/asm-arm/arch-omap/omap34xx.h | 2 + - 4 files changed, 163 insertions(+), 9 deletions(-) - -diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h -index c6a7940..f82b5a7 100644 ---- a/arch/arm/mach-omap2/prm-regbits-34xx.h -+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h -@@ -435,10 +435,10 @@ - /* PM_PWSTST_EMU specific bits */ - - /* PRM_VC_SMPS_SA */ --#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16 --#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16) --#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0 --#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0) -+#define OMAP3430_SMPS_SA1_SHIFT 16 -+#define OMAP3430_SMPS_SA1_MASK (0x7f << 16) -+#define OMAP3430_SMPS_SA0_SHIFT 0 -+#define OMAP3430_SMPS_SA0_MASK (0x7f << 0) - - /* PRM_VC_SMPS_VOL_RA */ - #define OMAP3430_VOLRA1_SHIFT 16 -@@ -452,7 +452,7 @@ - #define OMAP3430_CMDRA0_SHIFT 0 - #define OMAP3430_CMDRA0_MASK (0xff << 0) - --/* PRM_VC_CMD_VAL_0 specific bits */ -+/* PRM_VC_CMD_VAL */ - #define OMAP3430_VC_CMD_ON_SHIFT 24 - #define OMAP3430_VC_CMD_ON_MASK (0xFF << 24) - #define OMAP3430_VC_CMD_ONLP_SHIFT 16 -@@ -462,7 +462,17 @@ - #define OMAP3430_VC_CMD_OFF_SHIFT 0 - #define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0) - -+/* PRM_VC_CMD_VAL_0 specific bits */ -+#define OMAP3430_VC_CMD_VAL0_ON (0x3 << 4) -+#define OMAP3430_VC_CMD_VAL0_ONLP (0x3 << 3) -+#define OMAP3430_VC_CMD_VAL0_RET (0x3 << 3) -+#define OMAP3430_VC_CMD_VAL0_OFF (0x3 << 3) -+ - /* PRM_VC_CMD_VAL_1 specific bits */ -+#define OMAP3430_VC_CMD_VAL1_ON (0xB << 2) -+#define OMAP3430_VC_CMD_VAL1_ONLP (0x3 << 3) -+#define OMAP3430_VC_CMD_VAL1_RET (0x3 << 3) -+#define OMAP3430_VC_CMD_VAL1_OFF (0x3 << 3) - - /* PRM_VC_CH_CONF */ - #define OMAP3430_CMD1 (1 << 20) -@@ -521,6 +531,13 @@ - #define OMAP3430_AUTO_RET (1 << 1) - #define OMAP3430_AUTO_SLEEP (1 << 0) - -+/* Constants to define setup durations */ -+#define OMAP3430_CLKSETUP_DURATION 0xff -+#define OMAP3430_VOLTSETUP_TIME2 0xfff -+#define OMAP3430_VOLTSETUP_TIME1 0xfff -+#define OMAP3430_VOLTOFFSET_DURATION 0xff -+#define OMAP3430_VOLTSETUP2_DURATION 0xff -+ - /* PRM_SRAM_PCHARGE */ - #define OMAP3430_PCHARGE_TIME_SHIFT 0 - #define OMAP3430_PCHARGE_TIME_MASK (0xff << 0) -diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h -index 62907ef..2091a15 100644 ---- a/arch/arm/mach-omap2/smartreflex.h -+++ b/arch/arm/mach-omap2/smartreflex.h -@@ -1,5 +1,10 @@ -+#ifndef __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H -+#define __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H - /* -- * linux/arch/arm/mach-omap3/smartreflex.h -+ * linux/arch/arm/mach-omap2/smartreflex.h -+ * -+ * Copyright (C) 2008 Nokia Corporation -+ * Kalle Jokiniemi - * - * Copyright (C) 2007 Texas Instruments, Inc. - * Lesly A M <x0080970@ti.com> -@@ -9,6 +14,21 @@ - * published by the Free Software Foundation. - */ - -+#define PHY_TO_OFF_PM_MASTER(p) (p - 0x36) -+#define PHY_TO_OFF_PM_RECIEVER(p) (p - 0x5b) -+#define PHY_TO_OFF_PM_INT(p) (p - 0x2e) -+ -+/* SMART REFLEX REG ADDRESS OFFSET */ -+#define SRCONFIG 0x00 -+#define SRSTATUS 0x04 -+#define SENVAL 0x08 -+#define SENMIN 0x0C -+#define SENMAX 0x10 -+#define SENAVG 0x14 -+#define AVGWEIGHT 0x18 -+#define NVALUERECIPROCAL 0x1C -+#define SENERROR 0x20 -+#define ERRCONFIG 0x24 - - /* SR Modules */ - #define SR1 1 -@@ -127,10 +147,106 @@ - #define SR2_ERRMAXLIMIT (0x02 << 8) - #define SR2_ERRMINLIMIT (0xF9 << 0) - -+/* T2 SMART REFLEX */ -+#define R_SRI2C_SLAVE_ADDR 0x12 -+#define R_VDD1_SR_CONTROL 0x00 -+#define R_VDD2_SR_CONTROL 0x01 -+#define T2_SMPS_UPDATE_DELAY 360 /* In uSec */ -+ -+/* Vmode control */ -+#define R_DCDC_GLOBAL_CFG PHY_TO_OFF_PM_RECIEVER(0x61) -+ -+#define R_VDD1_VSEL PHY_TO_OFF_PM_RECIEVER(0xb9) -+#define R_VDD1_VMODE_CFG PHY_TO_OFF_PM_RECIEVER(0xba) -+#define R_VDD1_VFLOOR PHY_TO_OFF_PM_RECIEVER(0xbb) -+#define R_VDD1_VROOF PHY_TO_OFF_PM_RECIEVER(0xbc) -+#define R_VDD1_STEP PHY_TO_OFF_PM_RECIEVER(0xbd) -+ -+#define R_VDD2_VSEL PHY_TO_OFF_PM_RECIEVER(0xc7) -+#define R_VDD2_VMODE_CFG PHY_TO_OFF_PM_RECIEVER(0xc8) -+#define R_VDD2_VFLOOR PHY_TO_OFF_PM_RECIEVER(0xc9) -+#define R_VDD2_VROOF PHY_TO_OFF_PM_RECIEVER(0xca) -+#define R_VDD2_STEP PHY_TO_OFF_PM_RECIEVER(0xcb) -+ -+/* R_DCDC_GLOBAL_CFG register, SMARTREFLEX_ENABLE valuws */ -+#define DCDC_GLOBAL_CFG_ENABLE_SRFLX 0x08 -+ -+/* VDDs*/ -+#define PRCM_VDD1 1 -+#define PRCM_VDD2 2 -+#define PRCM_MAX_SYSC_REGS 30 -+ -+/* XXX: These should be removed/moved from here once we have a working DVFS -+ implementation in place */ -+#define AT_3430 1 /*3430 ES 1.0 */ -+#define AT_3430_ES2 2 /*3430 ES 2.0 */ -+ -+#define ID_OPP 0xE2 /*OPP*/ -+ -+/* DEVICE ID/DPLL ID/CLOCK ID: bits 28-31 for OMAP type */ -+#define OMAP_TYPE_SHIFT 28 -+#define OMAP_TYPE_MASK 0xF -+/* OPP ID: bits: 0-4 for OPP number */ -+#define OPP_NO_POS 0 -+#define OPP_NO_MASK 0x1F -+/* OPP ID: bits: 5-6 for VDD */ -+#define VDD_NO_POS 5 -+#define VDD_NO_MASK 0x3 -+/* Other IDs: bits 20-27 for ID type */ -+/* These IDs have bits 25,26,27 as 1 */ -+#define OTHER_ID_TYPE_SHIFT 20 -+#define OTHER_ID_TYPE_MASK 0xFF -+ -+#define OTHER_ID_TYPE(X) ((X & OTHER_ID_TYPE_MASK) << OTHER_ID_TYPE_SHIFT) -+#define ID_OPP_NO(X) ((X & OPP_NO_MASK) << OPP_NO_POS) -+#define ID_VDD(X) ((X & VDD_NO_MASK) << VDD_NO_POS) -+#define OMAP(X) ((X >> OMAP_TYPE_SHIFT) & OMAP_TYPE_MASK) -+#define get_opp_no(X) ((X >> OPP_NO_POS) & OPP_NO_MASK) -+#define get_vdd(X) ((X >> VDD_NO_POS) & VDD_NO_MASK) -+ -+/* VDD1 OPPs */ -+#define PRCM_VDD1_OPP1 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ -+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x1)) -+#define PRCM_VDD1_OPP2 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ -+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x2)) -+#define PRCM_VDD1_OPP3 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ -+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x3)) -+#define PRCM_VDD1_OPP4 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ -+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x4)) -+#define PRCM_VDD1_OPP5 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ -+ ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x5)) -+#define PRCM_NO_VDD1_OPPS 5 -+ -+ -+/* VDD2 OPPs */ -+#define PRCM_VDD2_OPP1 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ -+ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x1)) -+#define PRCM_VDD2_OPP2 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ -+ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x2)) -+#define PRCM_VDD2_OPP3 (OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \ -+ ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x3)) -+#define PRCM_NO_VDD2_OPPS 3 -+/* XXX: end remove/move */ -+ -+ -+/* XXX: find more appropriate place for these once DVFS is in place */ - extern u32 current_vdd1_opp; - extern u32 current_vdd2_opp; --extern struct kset power_subsys; - --extern inline int loop_wait(u32 *lcnt, u32 *rcnt, u32 delay); --extern void omap_udelay(u32 udelay); -+/* -+ * Smartreflex module enable/disable interface. -+ * NOTE: if smartreflex is not enabled from sysfs, these functions will not -+ * do anything. -+ */ -+#if defined(CONFIG_ARCH_OMAP34XX) && defined(CONFIG_TWL4030_CORE) -+void enable_smartreflex(int srid); -+void disable_smartreflex(int srid); -+#else -+static inline void enable_smartreflex(int srid) {} -+static inline void disable_smartreflex(int srid) {} -+#endif -+ -+ -+#endif -+ - -diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h -index 12bc22a..6e64fe7 100644 ---- a/include/asm-arm/arch-omap/control.h -+++ b/include/asm-arm/arch-omap/control.h -@@ -138,6 +138,15 @@ - #define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) - #define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) - #define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) -+#define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110) -+#define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114) -+#define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118) -+#define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c) -+#define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120) -+#define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124) -+#define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128) -+#define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c) -+#define OMAP343X_CONTROL_FUSE_SR (OMAP2_CONTROL_GENERAL + 0x0130) - #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) - #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) - #define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4) -@@ -172,6 +181,16 @@ - #define OMAP2_SYSBOOT_1_MASK (1 << 1) - #define OMAP2_SYSBOOT_0_MASK (1 << 0) - -+/* CONTROL_FUSE_SR bits */ -+#define OMAP343X_SR2_SENNENABLE_MASK (0x3 << 10) -+#define OMAP343X_SR2_SENNENABLE_SHIFT 10 -+#define OMAP343X_SR2_SENPENABLE_MASK (0x3 << 8) -+#define OMAP343X_SR2_SENPENABLE_SHIFT 8 -+#define OMAP343X_SR1_SENNENABLE_MASK (0x3 << 2) -+#define OMAP343X_SR1_SENNENABLE_SHIFT 2 -+#define OMAP343X_SR1_SENPENABLE_MASK (0x3 << 0) -+#define OMAP343X_SR1_SENPENABLE_SHIFT 0 -+ - #ifndef __ASSEMBLY__ - #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) - extern void __iomem *omap_ctrl_base_get(void); -diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h -index 6a0459a..3667fd6 100644 ---- a/include/asm-arm/arch-omap/omap34xx.h -+++ b/include/asm-arm/arch-omap/omap34xx.h -@@ -54,6 +54,8 @@ - #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) - #define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000) - #define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000) -+#define OMAP34XX_SR1_BASE 0x480C9000 -+#define OMAP34XX_SR2_BASE 0x480CB000 - - - #if defined(CONFIG_ARCH_OMAP3430) --- -1.5.4.3 diff --git a/packages/linux/linux-omap2-git/beagleboard/0003-ARM-OMAP-SmartReflex-driver.patch b/packages/linux/linux-omap2-git/beagleboard/0003-ARM-OMAP-SmartReflex-driver.patch deleted file mode 100644 index 40d5790367..0000000000 --- a/packages/linux/linux-omap2-git/beagleboard/0003-ARM-OMAP-SmartReflex-driver.patch +++ /dev/null @@ -1,1001 +0,0 @@ -From: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> -To: linux-omap@vger.kernel.org -Cc: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> -Subject: [PATCH 3/3] ARM: OMAP: SmartReflex driver: integration to linux-omap -Date: Fri, 6 Jun 2008 12:49:49 +0300 -Message-Id: <1212745789-13926-3-git-send-email-ext-kalle.jokiniemi@nokia.com> - -- Changed register accesses to use prm_{read,write}_mod_reg and - prm_{set,clear,rmw}_mod_reg_bits() functions instread of - "REG_X = REG_Y" type accesses. - -- Changed direct register clock enables/disables to clockframework calls. - -- replaced cpu-related #ifdefs with if (cpu_is_xxxx()) calls. - -- Added E-fuse support: Use silicon characteristics parameters from E-fuse - -- added smartreflex_disable/enable calls to pm34xx.c suspend function. - -- Added "SmartReflex support" entry into Kconfig under "System type->TI OMAP - Implementations". It depends on ARCH_OMAP34XX and TWL4030_CORE. - -- Added "SmartReflex testing support" Kconfig option for using hard coded - software parameters instead of E-fuse parameters. - -Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> ---- - arch/arm/mach-omap2/Makefile | 3 + - arch/arm/mach-omap2/pm34xx.c | 9 + - arch/arm/mach-omap2/smartreflex.c | 531 +++++++++++++++++++++++-------------- - arch/arm/mach-omap2/smartreflex.h | 9 +- - arch/arm/plat-omap/Kconfig | 31 +++ - 5 files changed, 385 insertions(+), 198 deletions(-) - -diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile -index 50c6657..f645b6e 100644 ---- a/arch/arm/mach-omap2/Makefile -+++ b/arch/arm/mach-omap2/Makefile -@@ -25,6 +25,9 @@ obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o - obj-$(CONFIG_PM_DEBUG) += pm-debug.o - endif - -+# SmartReflex driver -+obj-$(CONFIG_OMAP_SMARTREFLEX) += smartreflex.o -+ - # Clock framework - obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o - obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o -diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c -index 7e775cc..3da4f47 100644 ---- a/arch/arm/mach-omap2/pm34xx.c -+++ b/arch/arm/mach-omap2/pm34xx.c -@@ -36,6 +36,7 @@ - - #include "prm.h" - #include "pm.h" -+#include "smartreflex.h" - - struct power_state { - struct powerdomain *pwrdm; -@@ -256,6 +257,10 @@ static int omap3_pm_suspend(void) - struct power_state *pwrst; - int state, ret = 0; - -+ /* XXX Disable smartreflex before entering suspend */ -+ disable_smartreflex(SR1); -+ disable_smartreflex(SR2); -+ - /* Read current next_pwrsts */ - list_for_each_entry(pwrst, &pwrst_list, node) - pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); -@@ -287,6 +292,10 @@ restore: - printk(KERN_INFO "Successfully put all powerdomains " - "to target state\n"); - -+ /* XXX Enable smartreflex after suspend */ -+ enable_smartreflex(SR1); -+ enable_smartreflex(SR2); -+ - return ret; - } - -diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c -index dae7460..0b10a5d 100644 ---- a/arch/arm/mach-omap2/smartreflex.c -+++ b/arch/arm/mach-omap2/smartreflex.c -@@ -3,6 +3,9 @@ - * - * OMAP34XX SmartReflex Voltage Control - * -+ * Copyright (C) 2008 Nokia Corporation -+ * Kalle Jokiniemi -+ * - * Copyright (C) 2007 Texas Instruments, Inc. - * Lesly A M <x0080970@ti.com> - * -@@ -20,13 +23,16 @@ - #include <linux/err.h> - #include <linux/clk.h> - #include <linux/sysfs.h> -- --#include <asm/arch/prcm.h> --#include <asm/arch/power_companion.h> -+#include <linux/kobject.h> -+#include <linux/i2c/twl4030.h> - #include <linux/io.h> - --#include "prcm-regs.h" -+#include <asm/arch/omap34xx.h> -+#include <asm/arch/control.h> -+ -+#include "prm.h" - #include "smartreflex.h" -+#include "prm-regbits-34xx.h" - - - /* #define DEBUG_SR 1 */ -@@ -37,11 +43,16 @@ - # define DPRINTK(fmt, args...) - #endif - -+/* XXX: These should be relocated where-ever the OPP implementation will be */ -+u32 current_vdd1_opp; -+u32 current_vdd2_opp; -+ - struct omap_sr{ - int srid; - int is_sr_reset; - int is_autocomp_active; - struct clk *fck; -+ u32 clk_length; - u32 req_opp_no; - u32 opp1_nvalue, opp2_nvalue, opp3_nvalue, opp4_nvalue, opp5_nvalue; - u32 senp_mod, senn_mod; -@@ -53,6 +64,7 @@ static struct omap_sr sr1 = { - .srid = SR1, - .is_sr_reset = 1, - .is_autocomp_active = 0, -+ .clk_length = 0, - .srbase_addr = OMAP34XX_SR1_BASE, - }; - -@@ -60,6 +72,7 @@ static struct omap_sr sr2 = { - .srid = SR2, - .is_sr_reset = 1, - .is_autocomp_active = 0, -+ .clk_length = 0, - .srbase_addr = OMAP34XX_SR2_BASE, - }; - -@@ -85,8 +98,6 @@ static inline u32 sr_read_reg(struct omap_sr *sr, int offset) - return omap_readl(sr->srbase_addr + offset); - } - -- --#ifndef USE_EFUSE_VALUES - static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen) - { - u32 gn, rn, mul; -@@ -100,7 +111,21 @@ static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen) - } - } - } --#endif -+ -+static void sr_clk_get(struct omap_sr *sr) -+{ -+ if (sr->srid == SR1) { -+ sr->fck = clk_get(NULL, "sr1_fck"); -+ if (IS_ERR(sr->fck)) -+ printk(KERN_ERR "Could not get sr1_fck\n"); -+ -+ } else if (sr->srid == SR2) { -+ sr->fck = clk_get(NULL, "sr2_fck"); -+ if (IS_ERR(sr->fck)) -+ printk(KERN_ERR "Could not get sr2_fck\n"); -+ -+ } -+} - - static int sr_clk_enable(struct omap_sr *sr) - { -@@ -131,22 +156,86 @@ static int sr_clk_disable(struct omap_sr *sr) - return 0; - } - --static void sr_set_nvalues(struct omap_sr *sr) -+static void sr_set_clk_length(struct omap_sr *sr) -+{ -+ struct clk *osc_sys_ck; -+ u32 sys_clk = 0; -+ -+ osc_sys_ck = clk_get(NULL, "osc_sys_ck"); -+ sys_clk = clk_get_rate(osc_sys_ck); -+ clk_put(osc_sys_ck); -+ -+ switch (sys_clk) { -+ case 12000000: -+ sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK; -+ break; -+ case 13000000: -+ sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK; -+ break; -+ case 19200000: -+ sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK; -+ break; -+ case 26000000: -+ sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK; -+ break; -+ case 38400000: -+ sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK; -+ break; -+ default : -+ printk(KERN_ERR "Invalid sysclk value: %d\n", sys_clk); -+ break; -+ } -+} -+ -+static void sr_set_efuse_nvalues(struct omap_sr *sr) -+{ -+ if (sr->srid == SR1) { -+ sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) & -+ OMAP343X_SR1_SENNENABLE_MASK) >> -+ OMAP343X_SR1_SENNENABLE_SHIFT; -+ -+ sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) & -+ OMAP343X_SR1_SENPENABLE_MASK) >> -+ OMAP343X_SR1_SENPENABLE_SHIFT; -+ -+ sr->opp5_nvalue = omap_ctrl_readl( -+ OMAP343X_CONTROL_FUSE_OPP5_VDD1); -+ sr->opp4_nvalue = omap_ctrl_readl( -+ OMAP343X_CONTROL_FUSE_OPP4_VDD1); -+ sr->opp3_nvalue = omap_ctrl_readl( -+ OMAP343X_CONTROL_FUSE_OPP3_VDD1); -+ sr->opp2_nvalue = omap_ctrl_readl( -+ OMAP343X_CONTROL_FUSE_OPP2_VDD1); -+ sr->opp1_nvalue = omap_ctrl_readl( -+ OMAP343X_CONTROL_FUSE_OPP1_VDD1); -+ } else if (sr->srid == SR2) { -+ sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) & -+ OMAP343X_SR2_SENNENABLE_MASK) >> -+ OMAP343X_SR2_SENNENABLE_SHIFT; -+ -+ sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) & -+ OMAP343X_SR2_SENPENABLE_MASK) >> -+ OMAP343X_SR2_SENPENABLE_SHIFT; -+ -+ sr->opp3_nvalue = omap_ctrl_readl( -+ OMAP343X_CONTROL_FUSE_OPP3_VDD2); -+ sr->opp2_nvalue = omap_ctrl_readl( -+ OMAP343X_CONTROL_FUSE_OPP2_VDD2); -+ sr->opp1_nvalue = omap_ctrl_readl( -+ OMAP343X_CONTROL_FUSE_OPP1_VDD2); -+ } -+} -+ -+/* Hard coded nvalues for testing purposes, may cause device to hang! */ -+static void sr_set_testing_nvalues(struct omap_sr *sr) - { --#ifdef USE_EFUSE_VALUES -- u32 n1, n2; --#else - u32 senpval, sennval; - u32 senpgain, senngain; - u32 rnsenp, rnsenn; --#endif - - if (sr->srid == SR1) { --#ifdef USE_EFUSE_VALUES -- /* Read values for VDD1 from EFUSE */ --#else -- /* since E-Fuse Values are not available, calculating the -- * reciprocal of the SenN and SenP values for SR1 -+ /* Calculating the reciprocal of the SenN and SenP values -+ * for SR1 - */ - sr->senp_mod = 0x03; /* SenN-M5 enabled */ - sr->senn_mod = 0x03; -@@ -216,15 +305,16 @@ static void sr_set_nvalues(struct omap_sr *sr) - (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | - (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); - -+ /* XXX The clocks are enabled in the startup and NVALUE is -+ * set also there. Disabling this for now, but this could -+ * be related to dynamic sleep during boot */ -+#if 0 - sr_clk_enable(sr); - sr_write_reg(sr, NVALUERECIPROCAL, sr->opp3_nvalue); - sr_clk_disable(sr); -- - #endif -+ - } else if (sr->srid == SR2) { --#ifdef USE_EFUSE_VALUES -- /* Read values for VDD2 from EFUSE */ --#else - /* since E-Fuse Values are not available, calculating the - * reciprocal of the SenN and SenP values for SR2 - */ -@@ -269,134 +359,163 @@ static void sr_set_nvalues(struct omap_sr *sr) - (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) | - (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) | - (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT)); -- --#endif - } - - } - -+static void sr_set_nvalues(struct omap_sr *sr) -+{ -+ if (SR_TESTING_NVALUES) -+ sr_set_testing_nvalues(sr); -+ else -+ sr_set_efuse_nvalues(sr); -+} -+ - static void sr_configure_vp(int srid) - { - u32 vpconfig; - - if (srid == SR1) { - vpconfig = PRM_VP1_CONFIG_ERROROFFSET | PRM_VP1_CONFIG_ERRORGAIN -- | PRM_VP1_CONFIG_INITVOLTAGE | PRM_VP1_CONFIG_TIMEOUTEN; -- -- PRM_VP1_CONFIG = vpconfig; -- PRM_VP1_VSTEPMIN = PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN | -- PRM_VP1_VSTEPMIN_VSTEPMIN; -- -- PRM_VP1_VSTEPMAX = PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX | -- PRM_VP1_VSTEPMAX_VSTEPMAX; -- -- PRM_VP1_VLIMITTO = PRM_VP1_VLIMITTO_VDDMAX | -- PRM_VP1_VLIMITTO_VDDMIN | PRM_VP1_VLIMITTO_TIMEOUT; -- -- PRM_VP1_CONFIG |= PRM_VP1_CONFIG_INITVDD; -- PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_INITVDD; -+ | PRM_VP1_CONFIG_INITVOLTAGE -+ | PRM_VP1_CONFIG_TIMEOUTEN; -+ -+ prm_write_mod_reg(vpconfig, OMAP3430_GR_MOD, -+ OMAP3_PRM_VP1_CONFIG_OFFSET); -+ prm_write_mod_reg(PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN | -+ PRM_VP1_VSTEPMIN_VSTEPMIN, -+ OMAP3430_GR_MOD, -+ OMAP3_PRM_VP1_VSTEPMIN_OFFSET); -+ -+ prm_write_mod_reg(PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX | -+ PRM_VP1_VSTEPMAX_VSTEPMAX, -+ OMAP3430_GR_MOD, -+ OMAP3_PRM_VP1_VSTEPMAX_OFFSET); -+ -+ prm_write_mod_reg(PRM_VP1_VLIMITTO_VDDMAX | -+ PRM_VP1_VLIMITTO_VDDMIN | -+ PRM_VP1_VLIMITTO_TIMEOUT, -+ OMAP3430_GR_MOD, -+ OMAP3_PRM_VP1_VLIMITTO_OFFSET); -+ -+ /* Trigger initVDD value copy to voltage processor */ -+ prm_set_mod_reg_bits(PRM_VP1_CONFIG_INITVDD, OMAP3430_GR_MOD, -+ OMAP3_PRM_VP1_CONFIG_OFFSET); -+ /* Clear initVDD copy trigger bit */ -+ prm_clear_mod_reg_bits(PRM_VP1_CONFIG_INITVDD, OMAP3430_GR_MOD, -+ OMAP3_PRM_VP1_CONFIG_OFFSET); - - } else if (srid == SR2) { - vpconfig = PRM_VP2_CONFIG_ERROROFFSET | PRM_VP2_CONFIG_ERRORGAIN -- | PRM_VP2_CONFIG_INITVOLTAGE | PRM_VP2_CONFIG_TIMEOUTEN; -- -- PRM_VP2_CONFIG = vpconfig; -- PRM_VP2_VSTEPMIN = PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN | -- PRM_VP2_VSTEPMIN_VSTEPMIN; -- -- PRM_VP2_VSTEPMAX = PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX | -- PRM_VP2_VSTEPMAX_VSTEPMAX; -- -- PRM_VP2_VLIMITTO = PRM_VP2_VLIMITTO_VDDMAX | -- PRM_VP2_VLIMITTO_VDDMIN | PRM_VP2_VLIMITTO_TIMEOUT; -- -- PRM_VP2_CONFIG |= PRM_VP2_CONFIG_INITVDD; -- PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_INITVDD; -+ | PRM_VP2_CONFIG_INITVOLTAGE -+ | PRM_VP2_CONFIG_TIMEOUTEN; -+ -+ prm_write_mod_reg(vpconfig, OMAP3430_GR_MOD, -+ OMAP3_PRM_VP2_CONFIG_OFFSET); -+ prm_write_mod_reg(PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN | -+ PRM_VP2_VSTEPMIN_VSTEPMIN, -+ OMAP3430_GR_MOD, -+ OMAP3_PRM_VP2_VSTEPMIN_OFFSET); -+ -+ prm_write_mod_reg(PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX | -+ PRM_VP2_VSTEPMAX_VSTEPMAX, -+ OMAP3430_GR_MOD, -+ OMAP3_PRM_VP2_VSTEPMAX_OFFSET); -+ -+ prm_write_mod_reg(PRM_VP2_VLIMITTO_VDDMAX | -+ PRM_VP2_VLIMITTO_VDDMIN | -+ PRM_VP2_VLIMITTO_TIMEOUT, -+ OMAP3430_GR_MOD, -+ OMAP3_PRM_VP2_VLIMITTO_OFFSET); -+ -+ /* Trigger initVDD value copy to voltage processor */ -+ prm_set_mod_reg_bits(PRM_VP2_CONFIG_INITVDD, OMAP3430_GR_MOD, -+ OMAP3_PRM_VP2_CONFIG_OFFSET); -+ /* Reset initVDD copy trigger bit */ -+ prm_clear_mod_reg_bits(PRM_VP2_CONFIG_INITVDD, OMAP3430_GR_MOD, -+ OMAP3_PRM_VP2_CONFIG_OFFSET); - - } - } - - static void sr_configure_vc(void) - { -- PRM_VC_SMPS_SA = -- (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA1_SHIFT) | -- (R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA0_SHIFT); -- -- PRM_VC_SMPS_VOL_RA = (R_VDD2_SR_CONTROL << PRM_VC_SMPS_VOLRA1_SHIFT) | -- (R_VDD1_SR_CONTROL << PRM_VC_SMPS_VOLRA0_SHIFT); -- -- PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL0_ON << PRM_VC_CMD_ON_SHIFT) | -- (PRM_VC_CMD_VAL0_ONLP << PRM_VC_CMD_ONLP_SHIFT) | -- (PRM_VC_CMD_VAL0_RET << PRM_VC_CMD_RET_SHIFT) | -- (PRM_VC_CMD_VAL0_OFF << PRM_VC_CMD_OFF_SHIFT); -- -- PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL1_ON << PRM_VC_CMD_ON_SHIFT) | -- (PRM_VC_CMD_VAL1_ONLP << PRM_VC_CMD_ONLP_SHIFT) | -- (PRM_VC_CMD_VAL1_RET << PRM_VC_CMD_RET_SHIFT) | -- (PRM_VC_CMD_VAL1_OFF << PRM_VC_CMD_OFF_SHIFT); -- -- PRM_VC_CH_CONF = PRM_VC_CH_CONF_CMD1 | PRM_VC_CH_CONF_RAV1; -- -- PRM_VC_I2C_CFG = PRM_VC_I2C_CFG_MCODE | PRM_VC_I2C_CFG_HSEN -- | PRM_VC_I2C_CFG_SREN; -+ prm_write_mod_reg((R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA1_SHIFT) | -+ (R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA0_SHIFT), -+ OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_SA_OFFSET); -+ -+ prm_write_mod_reg((R_VDD2_SR_CONTROL << OMAP3430_VOLRA1_SHIFT) | -+ (R_VDD1_SR_CONTROL << OMAP3430_VOLRA0_SHIFT), -+ OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET); -+ -+ prm_write_mod_reg((OMAP3430_VC_CMD_VAL0_ON << -+ OMAP3430_VC_CMD_ON_SHIFT) | -+ (OMAP3430_VC_CMD_VAL0_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) | -+ (OMAP3430_VC_CMD_VAL0_RET << OMAP3430_VC_CMD_RET_SHIFT) | -+ (OMAP3430_VC_CMD_VAL0_OFF << OMAP3430_VC_CMD_OFF_SHIFT), -+ OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_0_OFFSET); -+ -+ prm_write_mod_reg((OMAP3430_VC_CMD_VAL1_ON << -+ OMAP3430_VC_CMD_ON_SHIFT) | -+ (OMAP3430_VC_CMD_VAL1_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) | -+ (OMAP3430_VC_CMD_VAL1_RET << OMAP3430_VC_CMD_RET_SHIFT) | -+ (OMAP3430_VC_CMD_VAL1_OFF << OMAP3430_VC_CMD_OFF_SHIFT), -+ OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_1_OFFSET); -+ -+ prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1, -+ OMAP3430_GR_MOD, -+ OMAP3_PRM_VC_CH_CONF_OFFSET); -+ -+ prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN | OMAP3430_SREN, -+ OMAP3430_GR_MOD, -+ OMAP3_PRM_VC_I2C_CFG_OFFSET); - - /* Setup voltctrl and other setup times */ -+ /* XXX CONFIG_SYSOFFMODE has not been implemented yet */ - #ifdef CONFIG_SYSOFFMODE -- PRM_VOLTCTRL = PRM_VOLTCTRL_AUTO_OFF | PRM_VOLTCTRL_AUTO_RET; -- PRM_CLKSETUP = PRM_CLKSETUP_DURATION; -- PRM_VOLTSETUP1 = (PRM_VOLTSETUP_TIME2 << PRM_VOLTSETUP_TIME2_OFFSET) | -- (PRM_VOLTSETUP_TIME1 << PRM_VOLTSETUP_TIME1_OFFSET); -- PRM_VOLTOFFSET = PRM_VOLTOFFSET_DURATION; -- PRM_VOLTSETUP2 = PRM_VOLTSETUP2_DURATION; -+ prm_write_mod_reg(OMAP3430_AUTO_OFF | OMAP3430_AUTO_RET, -+ OMAP3430_GR_MOD, -+ OMAP3_PRM_VOLTCTRL_OFFSET); -+ -+ prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD, -+ OMAP3_PRM_CLKSETUP_OFFSET); -+ prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2 << -+ OMAP3430_VOLTSETUP_TIME2_OFFSET) | -+ (OMAP3430_VOLTSETUP_TIME1 << -+ OMAP3430_VOLTSETUP_TIME1_OFFSET), -+ OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET); -+ -+ prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD, -+ OMAP3_PRM_VOLTOFFSET_OFFSET); -+ prm_write_mod_reg(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_GR_MOD, -+ OMAP3_PRM_VOLTSETUP2_OFFSET); - #else -- PRM_VOLTCTRL |= PRM_VOLTCTRL_AUTO_RET; -+ prm_set_mod_reg_bits(OMAP3430_AUTO_RET, OMAP3430_GR_MOD, -+ OMAP3_PRM_VOLTCTRL_OFFSET); - #endif - - } - -- - static void sr_configure(struct omap_sr *sr) - { -- u32 sys_clk, sr_clk_length = 0; - u32 sr_config; - u32 senp_en , senn_en; - -+ if (sr->clk_length == 0) -+ sr_set_clk_length(sr); -+ - senp_en = sr->senp_mod; - senn_en = sr->senn_mod; -- -- sys_clk = prcm_get_system_clock_speed(); -- -- switch (sys_clk) { -- case 12000: -- sr_clk_length = SRCLKLENGTH_12MHZ_SYSCLK; -- break; -- case 13000: -- sr_clk_length = SRCLKLENGTH_13MHZ_SYSCLK; -- break; -- case 19200: -- sr_clk_length = SRCLKLENGTH_19MHZ_SYSCLK; -- break; -- case 26000: -- sr_clk_length = SRCLKLENGTH_26MHZ_SYSCLK; -- break; -- case 38400: -- sr_clk_length = SRCLKLENGTH_38MHZ_SYSCLK; -- break; -- default : -- printk(KERN_ERR "Invalid sysclk value\n"); -- break; -- } -- -- DPRINTK(KERN_DEBUG "SR : sys clk %lu\n", sys_clk); - if (sr->srid == SR1) { - sr_config = SR1_SRCONFIG_ACCUMDATA | -- (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | -+ (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | - SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN | - SRCONFIG_MINMAXAVG_EN | - (senn_en << SRCONFIG_SENNENABLE_SHIFT) | - (senp_en << SRCONFIG_SENPENABLE_SHIFT) | - SRCONFIG_DELAYCTRL; -- -+ DPRINTK(KERN_DEBUG "setting SRCONFIG1 to 0x%08lx\n", -+ (unsigned long int) sr_config); - sr_write_reg(sr, SRCONFIG, sr_config); - - sr_write_reg(sr, AVGWEIGHT, SR1_AVGWEIGHT_SENPAVGWEIGHT | -@@ -408,18 +527,18 @@ static void sr_configure(struct omap_sr *sr) - - } else if (sr->srid == SR2) { - sr_config = SR2_SRCONFIG_ACCUMDATA | -- (sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | -+ (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) | - SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN | - SRCONFIG_MINMAXAVG_EN | - (senn_en << SRCONFIG_SENNENABLE_SHIFT) | - (senp_en << SRCONFIG_SENPENABLE_SHIFT) | - SRCONFIG_DELAYCTRL; - -+ DPRINTK(KERN_DEBUG "setting SRCONFIG2 to 0x%08lx\n", -+ (unsigned long int) sr_config); - sr_write_reg(sr, SRCONFIG, sr_config); -- - sr_write_reg(sr, AVGWEIGHT, SR2_AVGWEIGHT_SENPAVGWEIGHT | - SR2_AVGWEIGHT_SENNAVGWEIGHT); -- - sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK | - SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK), - (SR2_ERRWEIGHT | SR2_ERRMAXLIMIT | SR2_ERRMINLIMIT)); -@@ -428,9 +547,9 @@ static void sr_configure(struct omap_sr *sr) - sr->is_sr_reset = 0; - } - --static void sr_enable(struct omap_sr *sr, u32 target_opp_no) -+static int sr_enable(struct omap_sr *sr, u32 target_opp_no) - { -- u32 nvalue_reciprocal, current_nvalue; -+ u32 nvalue_reciprocal; - - sr->req_opp_no = target_opp_no; - -@@ -472,11 +591,10 @@ static void sr_enable(struct omap_sr *sr, u32 target_opp_no) - } - } - -- current_nvalue = sr_read_reg(sr, NVALUERECIPROCAL); -- -- if (current_nvalue == nvalue_reciprocal) { -- DPRINTK("System is already at the desired voltage level\n"); -- return; -+ if (nvalue_reciprocal == 0) { -+ printk(KERN_NOTICE "OPP%d doesn't support SmartReflex\n", -+ target_opp_no); -+ return SR_FALSE; - } - - sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal); -@@ -485,18 +603,19 @@ static void sr_enable(struct omap_sr *sr, u32 target_opp_no) - sr_modify_reg(sr, ERRCONFIG, - (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST), - (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST)); -- - if (sr->srid == SR1) { - /* Enable VP1 */ -- PRM_VP1_CONFIG |= PRM_VP1_CONFIG_VPENABLE; -+ prm_set_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE, OMAP3430_GR_MOD, -+ OMAP3_PRM_VP1_CONFIG_OFFSET); - } else if (sr->srid == SR2) { - /* Enable VP2 */ -- PRM_VP2_CONFIG |= PRM_VP2_CONFIG_VPENABLE; -+ prm_set_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE, OMAP3430_GR_MOD, -+ OMAP3_PRM_VP2_CONFIG_OFFSET); - } - - /* SRCONFIG - enable SR */ - sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE); -- -+ return SR_TRUE; - } - - static void sr_disable(struct omap_sr *sr) -@@ -507,11 +626,13 @@ static void sr_disable(struct omap_sr *sr) - sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, ~SRCONFIG_SRENABLE); - - if (sr->srid == SR1) { -- /* Enable VP1 */ -- PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE; -+ /* Disable VP1 */ -+ prm_clear_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE, OMAP3430_GR_MOD, -+ OMAP3_PRM_VP1_CONFIG_OFFSET); - } else if (sr->srid == SR2) { -- /* Enable VP2 */ -- PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE; -+ /* Disable VP2 */ -+ prm_clear_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE, OMAP3430_GR_MOD, -+ OMAP3_PRM_VP2_CONFIG_OFFSET); - } - } - -@@ -535,7 +656,12 @@ void sr_start_vddautocomap(int srid, u32 target_opp_no) - srid); - - sr->is_autocomp_active = 1; -- sr_enable(sr, target_opp_no); -+ if (!sr_enable(sr, target_opp_no)) { -+ printk(KERN_WARNING "SR%d: VDD autocomp not activated\n", srid); -+ sr->is_autocomp_active = 0; -+ if (sr->is_sr_reset == 1) -+ sr_clk_disable(sr); -+ } - } - EXPORT_SYMBOL(sr_start_vddautocomap); - -@@ -574,20 +700,18 @@ void enable_smartreflex(int srid) - - if (sr->is_autocomp_active == 1) { - if (sr->is_sr_reset == 1) { -- if (srid == SR1) { -- /* Enable SR clks */ -- CM_FCLKEN_WKUP |= SR1_CLK_ENABLE; -- target_opp_no = get_opp_no(current_vdd1_opp); -+ /* Enable SR clks */ -+ sr_clk_enable(sr); - -- } else if (srid == SR2) { -- /* Enable SR clks */ -- CM_FCLKEN_WKUP |= SR2_CLK_ENABLE; -+ if (srid == SR1) -+ target_opp_no = get_opp_no(current_vdd1_opp); -+ else if (srid == SR2) - target_opp_no = get_opp_no(current_vdd2_opp); -- } - - sr_configure(sr); - -- sr_enable(sr, target_opp_no); -+ if (!sr_enable(sr, target_opp_no)) -+ sr_clk_disable(sr); - } - } - } -@@ -602,15 +726,6 @@ void disable_smartreflex(int srid) - sr = &sr2; - - if (sr->is_autocomp_active == 1) { -- if (srid == SR1) { -- /* Enable SR clk */ -- CM_FCLKEN_WKUP |= SR1_CLK_ENABLE; -- -- } else if (srid == SR2) { -- /* Enable SR clk */ -- CM_FCLKEN_WKUP |= SR2_CLK_ENABLE; -- } -- - if (sr->is_sr_reset == 0) { - - sr->is_sr_reset = 1; -@@ -618,17 +733,18 @@ void disable_smartreflex(int srid) - sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, - ~SRCONFIG_SRENABLE); - -+ /* Disable SR clk */ -+ sr_clk_disable(sr); - if (sr->srid == SR1) { -- /* Disable SR clk */ -- CM_FCLKEN_WKUP &= ~SR1_CLK_ENABLE; -- /* Enable VP1 */ -- PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE; -- -+ /* Disable VP1 */ -+ prm_clear_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE, -+ OMAP3430_GR_MOD, -+ OMAP3_PRM_VP1_CONFIG_OFFSET); - } else if (sr->srid == SR2) { -- /* Disable SR clk */ -- CM_FCLKEN_WKUP &= ~SR2_CLK_ENABLE; -- /* Enable VP2 */ -- PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE; -+ /* Disable VP2 */ -+ prm_clear_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE, -+ OMAP3430_GR_MOD, -+ OMAP3_PRM_VP2_CONFIG_OFFSET); - } - } - } -@@ -638,7 +754,6 @@ void disable_smartreflex(int srid) - /* Voltage Scaling using SR VCBYPASS */ - int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel) - { -- int ret; - int sr_status = 0; - u32 vdd, target_opp_no; - u32 vc_bypass_value; -@@ -651,39 +766,53 @@ int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel) - if (vdd == PRCM_VDD1) { - sr_status = sr_stop_vddautocomap(SR1); - -- PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL_0 & ~PRM_VC_CMD_ON_MASK) | -- (vsel << PRM_VC_CMD_ON_SHIFT); -+ prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK, -+ (vsel << OMAP3430_VC_CMD_ON_SHIFT), -+ OMAP3430_GR_MOD, -+ OMAP3_PRM_VC_CMD_VAL_0_OFFSET); - reg_addr = R_VDD1_SR_CONTROL; - - } else if (vdd == PRCM_VDD2) { - sr_status = sr_stop_vddautocomap(SR2); - -- PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL_1 & ~PRM_VC_CMD_ON_MASK) | -- (vsel << PRM_VC_CMD_ON_SHIFT); -+ prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK, -+ (vsel << OMAP3430_VC_CMD_ON_SHIFT), -+ OMAP3430_GR_MOD, -+ OMAP3_PRM_VC_CMD_VAL_1_OFFSET); - reg_addr = R_VDD2_SR_CONTROL; - } - -- vc_bypass_value = (vsel << PRM_VC_BYPASS_DATA_SHIFT) | -- (reg_addr << PRM_VC_BYPASS_REGADDR_SHIFT) | -- (R_SRI2C_SLAVE_ADDR << PRM_VC_BYPASS_SLAVEADDR_SHIFT); -+ vc_bypass_value = (vsel << OMAP3430_DATA_SHIFT) | -+ (reg_addr << OMAP3430_REGADDR_SHIFT) | -+ (R_SRI2C_SLAVE_ADDR << OMAP3430_SLAVEADDR_SHIFT); - -- PRM_VC_BYPASS_VAL = vc_bypass_value; -+ prm_write_mod_reg(vc_bypass_value, OMAP3430_GR_MOD, -+ OMAP3_PRM_VC_BYPASS_VAL_OFFSET); - -- PRM_VC_BYPASS_VAL |= PRM_VC_BYPASS_VALID; -+ vc_bypass_value = prm_set_mod_reg_bits(OMAP3430_VALID, OMAP3430_GR_MOD, -+ OMAP3_PRM_VC_BYPASS_VAL_OFFSET); - -- DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, PRM_VC_BYPASS_VAL); -- DPRINTK("PRM_IRQST_MPU %X\n", PRM_IRQSTATUS_MPU); -+ DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, vc_bypass_value); -+ DPRINTK("PRM_IRQST_MPU %X\n", prm_read_mod_reg(OCP_MOD, -+ OMAP3_PRM_IRQSTATUS_MPU_OFFSET)); - -- while ((PRM_VC_BYPASS_VAL & PRM_VC_BYPASS_VALID) != 0x0) { -- ret = loop_wait(&loop_cnt, &retries_cnt, 10); -- if (ret != PRCM_PASS) { -+ while ((vc_bypass_value & OMAP3430_VALID) != 0x0) { -+ loop_cnt++; -+ if (retries_cnt > 10) { - printk(KERN_INFO "Loop count exceeded in check SR I2C" - "write\n"); -- return ret; -+ return SR_FAIL; -+ } -+ if (loop_cnt > 50) { -+ retries_cnt++; -+ loop_cnt = 0; -+ udelay(10); - } -+ vc_bypass_value = prm_read_mod_reg(OMAP3430_GR_MOD, -+ OMAP3_PRM_VC_BYPASS_VAL_OFFSET); - } - -- omap_udelay(T2_SMPS_UPDATE_DELAY); -+ udelay(T2_SMPS_UPDATE_DELAY); - - if (sr_status) { - if (vdd == PRCM_VDD1) -@@ -696,13 +825,15 @@ int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel) - } - - /* Sysfs interface to select SR VDD1 auto compensation */ --static ssize_t omap_sr_vdd1_autocomp_show(struct kset *subsys, char *buf) -+static ssize_t omap_sr_vdd1_autocomp_show(struct kobject *kobj, -+ struct kobj_attribute *attr, char *buf) - { - return sprintf(buf, "%d\n", sr1.is_autocomp_active); - } - --static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys, -- const char *buf, size_t n) -+static ssize_t omap_sr_vdd1_autocomp_store(struct kobject *kobj, -+ struct kobj_attribute *attr, -+ const char *buf, size_t n) - { - u32 current_vdd1opp_no; - unsigned short value; -@@ -722,7 +853,7 @@ static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys, - return n; - } - --static struct subsys_attribute sr_vdd1_autocomp = { -+static struct kobj_attribute sr_vdd1_autocomp = { - .attr = { - .name = __stringify(sr_vdd1_autocomp), - .mode = 0644, -@@ -732,13 +863,15 @@ static struct subsys_attribute sr_vdd1_autocomp = { - }; - - /* Sysfs interface to select SR VDD2 auto compensation */ --static ssize_t omap_sr_vdd2_autocomp_show(struct kset *subsys, char *buf) -+static ssize_t omap_sr_vdd2_autocomp_show(struct kobject *kobj, -+ struct kobj_attribute *attr, char *buf) - { - return sprintf(buf, "%d\n", sr2.is_autocomp_active); - } - --static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys, -- const char *buf, size_t n) -+static ssize_t omap_sr_vdd2_autocomp_store(struct kobject *kobj, -+ struct kobj_attribute *attr, -+ const char *buf, size_t n) - { - u32 current_vdd2opp_no; - unsigned short value; -@@ -758,7 +891,7 @@ static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys, - return n; - } - --static struct subsys_attribute sr_vdd2_autocomp = { -+static struct kobj_attribute sr_vdd2_autocomp = { - .attr = { - .name = __stringify(sr_vdd2_autocomp), - .mode = 0644, -@@ -774,15 +907,19 @@ static int __init omap3_sr_init(void) - int ret = 0; - u8 RdReg; - --#ifdef CONFIG_ARCH_OMAP34XX -- sr1.fck = clk_get(NULL, "sr1_fck"); -- if (IS_ERR(sr1.fck)) -- printk(KERN_ERR "Could not get sr1_fck\n"); -- -- sr2.fck = clk_get(NULL, "sr2_fck"); -- if (IS_ERR(sr2.fck)) -- printk(KERN_ERR "Could not get sr2_fck\n"); --#endif /* #ifdef CONFIG_ARCH_OMAP34XX */ -+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) { -+ current_vdd1_opp = PRCM_VDD1_OPP3; -+ current_vdd2_opp = PRCM_VDD2_OPP3; -+ } else { -+ current_vdd1_opp = PRCM_VDD1_OPP1; -+ current_vdd2_opp = PRCM_VDD1_OPP1; -+ } -+ if (cpu_is_omap34xx()) { -+ sr_clk_get(&sr1); -+ sr_clk_get(&sr2); -+ } -+ sr_set_clk_length(&sr1); -+ sr_set_clk_length(&sr2); - - /* Call the VPConfig, VCConfig, set N Values. */ - sr_set_nvalues(&sr1); -@@ -794,22 +931,24 @@ static int __init omap3_sr_init(void) - sr_configure_vc(); - - /* Enable SR on T2 */ -- ret = t2_in(PM_RECEIVER, &RdReg, R_DCDC_GLOBAL_CFG); -- RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX; -- ret |= t2_out(PM_RECEIVER, RdReg, R_DCDC_GLOBAL_CFG); -+ ret = twl4030_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &RdReg, -+ R_DCDC_GLOBAL_CFG); - -+ RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX; -+ ret |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, RdReg, -+ R_DCDC_GLOBAL_CFG); - - printk(KERN_INFO "SmartReflex driver initialized\n"); - -- ret = subsys_create_file(&power_subsys, &sr_vdd1_autocomp); -+ ret = sysfs_create_file(power_kobj, &sr_vdd1_autocomp.attr); - if (ret) -- printk(KERN_ERR "subsys_create_file failed: %d\n", ret); -+ printk(KERN_ERR "sysfs_create_file failed: %d\n", ret); - -- ret = subsys_create_file(&power_subsys, &sr_vdd2_autocomp); -+ ret = sysfs_create_file(power_kobj, &sr_vdd2_autocomp.attr); - if (ret) -- printk(KERN_ERR "subsys_create_file failed: %d\n", ret); -+ printk(KERN_ERR "sysfs_create_file failed: %d\n", ret); - - return 0; - } - --arch_initcall(omap3_sr_init); -+late_initcall(omap3_sr_init); -diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h -index 2091a15..194429e 100644 ---- a/arch/arm/mach-omap2/smartreflex.h -+++ b/arch/arm/mach-omap2/smartreflex.h -@@ -233,12 +233,18 @@ - extern u32 current_vdd1_opp; - extern u32 current_vdd2_opp; - -+#ifdef CONFIG_OMAP_SMARTREFLEX_TESTING -+#define SR_TESTING_NVALUES 1 -+#else -+#define SR_TESTING_NVALUES 0 -+#endif -+ - /* - * Smartreflex module enable/disable interface. - * NOTE: if smartreflex is not enabled from sysfs, these functions will not - * do anything. - */ --#if defined(CONFIG_ARCH_OMAP34XX) && defined(CONFIG_TWL4030_CORE) -+#ifdef CONFIG_OMAP_SMARTREFLEX - void enable_smartreflex(int srid); - void disable_smartreflex(int srid); - #else -@@ -246,7 +252,6 @@ static inline void enable_smartreflex(int srid) {} - static inline void disable_smartreflex(int srid) {} - #endif - -- - #endif - - -diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig -index b085b07..960c13f 100644 ---- a/arch/arm/plat-omap/Kconfig -+++ b/arch/arm/plat-omap/Kconfig -@@ -56,6 +56,37 @@ config OMAP_DEBUG_CLOCKDOMAIN - for every clockdomain register write. However, the - extra detail costs some memory. - -+config OMAP_SMARTREFLEX -+ bool "SmartReflex support" -+ depends on ARCH_OMAP34XX && TWL4030_CORE -+ help -+ Say Y if you want to enable SmartReflex. -+ -+ SmartReflex can perform continuous dynamic voltage -+ scaling around the nominal operating point voltage -+ according to silicon characteristics and operating -+ conditions. Enabling SmartReflex reduces power -+ consumption. -+ -+ Please note, that by default SmartReflex is only -+ initialized. To enable the automatic voltage -+ compensation for VDD1 and VDD2, user must write 1 to -+ /sys/power/sr_vddX_autocomp, where X is 1 or 2. -+ -+config OMAP_SMARTREFLEX_TESTING -+ bool "Smartreflex testing support" -+ depends on OMAP_SMARTREFLEX -+ default n -+ help -+ Say Y if you want to enable SmartReflex testing with SW hardcoded -+ NVALUES intead of E-fuse NVALUES set in factory silicon testing. -+ -+ In some devices the E-fuse values have not been set, even though -+ SmartReflex modules are included. Using these hardcoded values set -+ in software, one can test the SmartReflex features without E-fuse. -+ -+ WARNING: Enabling this option may cause your device to hang! -+ - config OMAP_RESET_CLOCKS - bool "Reset unused clocks during boot" - depends on ARCH_OMAP --- -1.5.4.3 diff --git a/packages/linux/linux-omap2-git/beagleboard/16bpp.patch b/packages/linux/linux-omap2-git/beagleboard/16bpp.patch new file mode 100644 index 0000000000..f1e2181c82 --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/16bpp.patch @@ -0,0 +1,13 @@ +diff --git a/drivers/video/omap/lcd_omap3beagle.c b/drivers/video/omap/lcd_omap3beagle.c +index 69d4e06..c1c4f4c 100644 +--- a/drivers/video/omap/lcd_omap3beagle.c ++++ b/drivers/video/omap/lcd_omap3beagle.c +@@ -66,7 +66,7 @@ struct lcd_panel omap3beagle_panel = { + .name = "omap3beagle", + .config = OMAP_LCDC_PANEL_TFT, + +- .bpp = 24, ++ .bpp = 16, + .data_lines = 24, + .x_res = LCD_XRES, + .y_res = LCD_YRES, diff --git a/packages/linux/linux-omap2-git/beagleboard/defconfig b/packages/linux/linux-omap2-git/beagleboard/defconfig index e11c379d8a..d4c1e9300a 100644 --- a/packages/linux/linux-omap2-git/beagleboard/defconfig +++ b/packages/linux/linux-omap2-git/beagleboard/defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.26-rc7-omap1 -# Mon Jun 23 10:04:35 2008 +# Tue Jun 24 20:16:52 2008 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -1023,13 +1023,178 @@ CONFIG_SSB_POSSIBLE=y # # Multimedia core support # -# CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set -# CONFIG_VIDEO_MEDIA is not set +CONFIG_VIDEO_DEV=m +CONFIG_VIDEO_V4L2_COMMON=m +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +CONFIG_DVB_CORE=m +CONFIG_VIDEO_MEDIA=m # # Multimedia drivers # +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_TUNER=m +# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_VIDEO_V4L2=m +CONFIG_VIDEO_V4L1=m +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +# CONFIG_TUNER_3036 is not set +# CONFIG_VIDEO_AU0828 is not set +CONFIG_V4L_USB_DRIVERS=y +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_VIDEO_USBVISION is not set +# CONFIG_USB_VICAM is not set +# CONFIG_USB_IBMCAM is not set +# CONFIG_USB_KONICAWC is not set +# CONFIG_USB_QUICKCAM_MESSENGER is not set +# CONFIG_USB_ET61X251 is not set +# CONFIG_VIDEO_OVCAMCHIP is not set +# CONFIG_USB_W9968CF is not set +# CONFIG_USB_OV511 is not set +# CONFIG_USB_SE401 is not set +# CONFIG_USB_SN9C102 is not set +# CONFIG_USB_STV680 is not set +# CONFIG_USB_ZC0301 is not set +# CONFIG_USB_PWC is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_SOC_CAMERA is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_RADIO_TEA5761 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_USB_SI470X is not set +CONFIG_DVB_CAPTURE_DRIVERS=y +# CONFIG_TTPCI_EEPROM is not set + +# +# Supported USB Adapters +# +CONFIG_DVB_USB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_DIBUSB_MB=m +# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m +CONFIG_DVB_CINERGYT2=m +# CONFIG_DVB_CINERGYT2_TUNING is not set + +# +# Supported FlexCopII (B2C2) Adapters +# +# CONFIG_DVB_B2C2_FLEXCOP is not set + +# +# Supported DVB Frontends +# + +# +# Customise DVB Frontends +# +# CONFIG_DVB_FE_CUSTOMISE is not set + +# +# DVB-S (satellite) frontends +# +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_MT312=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_TUNER_ITD1000=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_TUA6100=m + +# +# DVB-T (terrestrial) frontends +# +CONFIG_DVB_SP8870=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +CONFIG_DVB_L64781=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_MT352=m +CONFIG_DVB_ZL10353=m +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_TDA10048=m + +# +# DVB-C (cable) frontends +# +CONFIG_DVB_VES1820=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_STV0297=m + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +CONFIG_DVB_NXT200X=m +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_OR51132 is not set +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_AU8522=m +CONFIG_DVB_S5H1411=m + +# +# Digital terrestrial only tuners/PLL +# +CONFIG_DVB_PLL=m +CONFIG_DVB_TUNER_DIB0070=m + +# +# SEC control devices for DVB-S +# +CONFIG_DVB_LNBP21=m +# CONFIG_DVB_ISL6405 is not set +CONFIG_DVB_ISL6421=m # CONFIG_DAB is not set # @@ -1038,7 +1203,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y +# CONFIG_FIRMWARE_EDID is not set # CONFIG_FB_DDC is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y @@ -1086,7 +1251,10 @@ CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y # CONFIG_FONTS is not set CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y -# CONFIG_LOGO is not set +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y # # Sound @@ -1099,15 +1267,15 @@ CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y -CONFIG_SND_HWDEP=m -CONFIG_SND_RAWMIDI=m +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y CONFIG_SND_SEQUENCER=m # CONFIG_SND_SEQ_DUMMY is not set CONFIG_SND_OSSEMUL=y CONFIG_SND_MIXER_OSS=y CONFIG_SND_PCM_OSS=y CONFIG_SND_PCM_OSS_PLUGINS=y -# CONFIG_SND_SEQUENCER_OSS is not set +CONFIG_SND_SEQUENCER_OSS=y # CONFIG_SND_DYNAMIC_MINORS is not set CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_VERBOSE_PROCFS=y @@ -1139,9 +1307,9 @@ CONFIG_SND_VERBOSE_PROCFS=y # # USB devices # -CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_AUDIO=y CONFIG_SND_USB_CAIAQ=m -# CONFIG_SND_USB_CAIAQ_INPUT is not set +CONFIG_SND_USB_CAIAQ_INPUT=y # # System on Chip audio support @@ -1156,6 +1324,9 @@ CONFIG_SND_SOC=y # SoC Audio for the Texas Instruments OMAP # CONFIG_SND_OMAP_SOC=y +CONFIG_SND_OMAP_SOC_MCBSP=y +CONFIG_SND_OMAP_SOC_OMAP3BEAGLE=y +CONFIG_SND_SOC_TWL4030=y # # Open Sound System @@ -1227,7 +1398,7 @@ CONFIG_USB_MUSB_LOGLEVEL=0 # CONFIG_USB_ACM=m CONFIG_USB_PRINTER=m -# CONFIG_USB_WDM is not set +CONFIG_USB_WDM=m # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' diff --git a/packages/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch b/packages/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch new file mode 100644 index 0000000000..25e5aad9c9 --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch @@ -0,0 +1,114 @@ +From linux-omap-owner@vger.kernel.org Tue Jun 24 09:24:30 2008 +Received: from localhost + ([127.0.0.1] helo=dominion ident=koen) + by dominion.dominion.void with esmtp (Exim 4.63) + (envelope-from <linux-omap-owner@vger.kernel.org>) + id 1KB2tB-0005XT-FQ + for koen@localhost; Tue, 24 Jun 2008 09:24:30 +0200 +Received: from xs.service.utwente.nl [130.89.5.250] + by dominion with POP3 (fetchmail-6.3.6) + for <koen@localhost> (single-drop); Tue, 24 Jun 2008 09:24:29 +0200 (CEST) +Received: from mail.service.utwente.nl ([130.89.5.254]) by exchange.service.utwente.nl with Microsoft SMTPSVC(6.0.3790.3959); + Tue, 24 Jun 2008 09:13:04 +0200 +Received: from mx.utwente.nl ([130.89.2.13]) by mail.service.utwente.nl with Microsoft SMTPSVC(6.0.3790.3959); + Tue, 24 Jun 2008 09:13:03 +0200 +Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) + by mx.utwente.nl (8.12.10/SuSE Linux 0.7) with ESMTP id m5O7CcD7008917 + for <k.kooi@student.utwente.nl>; Tue, 24 Jun 2008 09:12:38 +0200 +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1751623AbYFXHMh (ORCPT <rfc822;k.kooi@student.utwente.nl>); + Tue, 24 Jun 2008 03:12:37 -0400 +Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751670AbYFXHMh + (ORCPT <rfc822;linux-omap-outgoing>); + Tue, 24 Jun 2008 03:12:37 -0400 +Received: from utopia.booyaka.com ([72.9.107.138]:47392 "EHLO + utopia.booyaka.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1751623AbYFXHMg (ORCPT + <rfc822;linux-omap@vger.kernel.org>); Tue, 24 Jun 2008 03:12:36 -0400 +Received: (qmail 1797 invoked by uid 526); 24 Jun 2008 07:12:35 -0000 +Date: Tue, 24 Jun 2008 01:12:35 -0600 (MDT) +From: Paul Walmsley <paul@pwsan.com> +To: linux-omap@vger.kernel.org +Subject: [PATCH] OMAP3 clock: DPLL{1,2}_FCLK clksel can divide by 4 +Message-ID: <alpine.DEB.1.00.0806240111320.9741@utopia.booyaka.com> +User-Agent: Alpine 1.00 (DEB 882 2007-12-20) +MIME-Version: 1.0 +Content-Type: TEXT/PLAIN; charset=US-ASCII +Sender: linux-omap-owner@vger.kernel.org +Precedence: bulk +List-ID: <linux-omap.vger.kernel.org> +X-Mailing-List: linux-omap@vger.kernel.org +X-UTwente-MailScanner-Information: Scanned by MailScanner. Contact servicedesk@icts.utwente.nl for more information. +X-UTwente-MailScanner: Found to be clean +X-UTwente-MailScanner-From: linux-omap-owner@vger.kernel.org +X-Spam-Status: No +X-OriginalArrivalTime: 24 Jun 2008 07:13:04.0264 (UTC) FILETIME=[BE950880:01C8D5C9] + + +OMAP34xx ES2 TRM Delta G to H states that the divider for DPLL1_FCLK and +DPLL2_FCLK can divide by 4 in addition to dividing by 1 and 2. Encode this +into the OMAP3 clock framework. + +Signed-off-by: Paul Walmsley <paul@pwsan.com> +--- + + arch/arm/mach-omap2/clock34xx.h | 20 ++++++++++++++++---- + 1 files changed, 16 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h +index b4dceea..9605744 100644 +--- a/arch/arm/mach-omap2/clock34xx.h ++++ b/arch/arm/mach-omap2/clock34xx.h +@@ -1029,8 +1029,15 @@ static struct clk corex2_fck = { + + /* DPLL power domain clock controls */ + +-static const struct clksel div2_core_clksel[] = { +- { .parent = &core_ck, .rates = div2_rates }, ++static const struct clksel_rate div4_rates[] = { ++ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, ++ { .div = 2, .val = 2, .flags = RATE_IN_343X }, ++ { .div = 4, .val = 4, .flags = RATE_IN_343X }, ++ { .div = 0 } ++}; ++ ++static const struct clksel div4_core_clksel[] = { ++ { .parent = &core_ck, .rates = div4_rates }, + { .parent = NULL } + }; + +@@ -1044,7 +1051,7 @@ static struct clk dpll1_fck = { + .init = &omap2_init_clksel_parent, + .clksel_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), + .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, +- .clksel = div2_core_clksel, ++ .clksel = div4_core_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, +@@ -1119,7 +1126,7 @@ static struct clk dpll2_fck = { + .init = &omap2_init_clksel_parent, + .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), + .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, +- .clksel = div2_core_clksel, ++ .clksel = div4_core_clksel, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | + PARENT_CONTROLS_CLOCK, + .recalc = &omap2_clksel_recalc, +@@ -1155,6 +1162,11 @@ static struct clk iva2_ck = { + + /* Common interface clocks */ + ++static const struct clksel div2_core_clksel[] = { ++ { .parent = &core_ck, .rates = div2_rates }, ++ { .parent = NULL } ++}; ++ + static struct clk l3_ick = { + .name = "l3_ick", + .parent = &core_ck, +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/packages/linux/linux-omap2-git/beagleboard/omap3-jitter.patch b/packages/linux/linux-omap2-git/beagleboard/omap3-jitter.patch new file mode 100644 index 0000000000..2e0dfd9f13 --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/omap3-jitter.patch @@ -0,0 +1,95 @@ +From linux-omap-owner@vger.kernel.org Tue Jun 24 09:24:30 2008 +Received: from localhost + ([127.0.0.1] helo=dominion ident=koen) + by dominion.dominion.void with esmtp (Exim 4.63) + (envelope-from <linux-omap-owner@vger.kernel.org>) + id 1KB2tC-0005XT-Mj + for koen@localhost; Tue, 24 Jun 2008 09:24:30 +0200 +Received: from xs.service.utwente.nl [130.89.5.250] + by dominion with POP3 (fetchmail-6.3.6) + for <koen@localhost> (single-drop); Tue, 24 Jun 2008 09:24:30 +0200 (CEST) +Received: from mail.service.utwente.nl ([130.89.5.253]) by exchange.service.utwente.nl with Microsoft SMTPSVC(6.0.3790.3959); + Tue, 24 Jun 2008 09:20:48 +0200 +Received: from smtp.utwente.nl ([130.89.2.8]) by mail.service.utwente.nl with Microsoft SMTPSVC(6.0.3790.3959); + Tue, 24 Jun 2008 09:20:47 +0200 +Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) + by smtp.utwente.nl (8.12.10/SuSE Linux 0.7) with ESMTP id m5O7BPWU031214 + for <k.kooi@student.utwente.nl>; Tue, 24 Jun 2008 09:11:25 +0200 +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1751128AbYFXHLY (ORCPT <rfc822;k.kooi@student.utwente.nl>); + Tue, 24 Jun 2008 03:11:24 -0400 +Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751405AbYFXHLX + (ORCPT <rfc822;linux-omap-outgoing>); + Tue, 24 Jun 2008 03:11:23 -0400 +Received: from utopia.booyaka.com ([72.9.107.138]:44580 "EHLO + utopia.booyaka.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1751128AbYFXHLX (ORCPT + <rfc822;linux-omap@vger.kernel.org>); Tue, 24 Jun 2008 03:11:23 -0400 +Received: (qmail 1744 invoked by uid 526); 24 Jun 2008 07:11:21 -0000 +Date: Tue, 24 Jun 2008 01:11:21 -0600 (MDT) +From: Paul Walmsley <paul@pwsan.com> +To: linux-omap@vger.kernel.org +Subject: [PATCH] OMAP3 clock: fix DPLL jitter correction and rate + programming +Message-ID: <alpine.DEB.1.00.0806240109440.9741@utopia.booyaka.com> +User-Agent: Alpine 1.00 (DEB 882 2007-12-20) +MIME-Version: 1.0 +Content-Type: TEXT/PLAIN; charset=US-ASCII +Sender: linux-omap-owner@vger.kernel.org +Precedence: bulk +List-ID: <linux-omap.vger.kernel.org> +X-Mailing-List: linux-omap@vger.kernel.org +X-UTwente-MailScanner-Information: Scanned by MailScanner. Contact servicedesk@icts.utwente.nl for more information. +X-UTwente-MailScanner: Found to be clean +X-UTwente-MailScanner-From: linux-omap-owner@vger.kernel.org +X-Spam-Status: No +X-OriginalArrivalTime: 24 Jun 2008 07:20:48.0265 (UTC) FILETIME=[D325F790:01C8D5CA] + + +Fix DPLL jitter correction programming. Previously, +omap3_noncore_dpll_program() stored the FREQSEL jitter correction +parameter to the wrong register. This caused jitter correction to be set +incorrectly and also caused the DPLL divider to be programmed incorrectly. + +Also, fix DPLL divider programming. An off-by-one error existed in +omap3_noncore_dpll_program(), causing DPLLs to be programmed with a higher +divider than intended. + +Signed-off-by: Paul Walmsley <paul@pwsan.com> +--- + + arch/arm/mach-omap2/clock34xx.c | 13 ++++++++----- + 1 files changed, 8 insertions(+), 5 deletions(-) + +diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c +index 408b51a..8fdf8f3 100644 +--- a/arch/arm/mach-omap2/clock34xx.c ++++ b/arch/arm/mach-omap2/clock34xx.c +@@ -346,14 +346,17 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) + /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ + _omap3_noncore_dpll_bypass(clk); + ++ /* Set jitter correction */ ++ v = __raw_readl(dd->control_reg); ++ v &= ~dd->freqsel_mask; ++ v |= freqsel << __ffs(dd->freqsel_mask); ++ __raw_writel(v, dd->control_reg); ++ ++ /* Set DPLL multiplier, divider */ + v = __raw_readl(dd->mult_div1_reg); + v &= ~(dd->mult_mask | dd->div1_mask); +- +- /* Set mult (M), div1 (N), freqsel */ + v |= m << __ffs(dd->mult_mask); +- v |= n << __ffs(dd->div1_mask); +- v |= freqsel << __ffs(dd->freqsel_mask); +- ++ v |= (n - 1) << __ffs(dd->div1_mask); + __raw_writel(v, dd->mult_div1_reg); + + /* We let the clock framework set the other output dividers later */ +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/packages/linux/linux-omap2-git/beagleboard/soc.patch b/packages/linux/linux-omap2-git/beagleboard/soc.patch new file mode 100644 index 0000000000..bb97403f29 --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/soc.patch @@ -0,0 +1,1173 @@ +diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig +index 3903ab7..468536d 100644 +--- a/sound/soc/codecs/Kconfig ++++ b/sound/soc/codecs/Kconfig +@@ -44,3 +44,7 @@ config SND_SOC_CS4270_VD33_ERRATA + config SND_SOC_TLV320AIC3X + tristate + depends on SND_SOC && I2C ++ ++config SND_SOC_TWL4030 ++ tristate ++ depends on SND_SOC && I2C +diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile +index 4e1314c..d2c0b12 100644 +--- a/sound/soc/codecs/Makefile ++++ b/sound/soc/codecs/Makefile +@@ -6,6 +6,7 @@ snd-soc-wm9712-objs := wm9712.o + snd-soc-wm9713-objs := wm9713.o + snd-soc-cs4270-objs := cs4270.o + snd-soc-tlv320aic3x-objs := tlv320aic3x.o ++snd-soc-twl4030-objs := twl4030.o + + obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o + obj-$(CONFIG_SND_SOC_WM8731) += snd-soc-wm8731.o +@@ -15,3 +16,4 @@ obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o + obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o + obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o + obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o ++obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o +diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c +new file mode 100644 +index 0000000..c9eee19 +--- /dev/null ++++ b/sound/soc/codecs/twl4030.c +@@ -0,0 +1,595 @@ ++/* ++ * ALSA SoC TWL4030 codec driver ++ * ++ * Author: Steve Sakoman, <steve@sakoman.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include <linux/module.h> ++#include <linux/moduleparam.h> ++#include <linux/init.h> ++#include <linux/delay.h> ++#include <linux/pm.h> ++#include <linux/i2c.h> ++#include <linux/platform_device.h> ++#include <linux/i2c/twl4030.h> ++#include <sound/core.h> ++#include <sound/pcm.h> ++#include <sound/pcm_params.h> ++#include <sound/soc.h> ++#include <sound/soc-dapm.h> ++#include <sound/initval.h> ++ ++#include "twl4030.h" ++ ++/* ++ * twl4030 register cache & default register settings ++ */ ++static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = { ++ 0x00, // this register not used ++ 0x93, // REG_CODEC_MODE (0x1) ++ 0xc3, // REG_OPTION (0x2) ++ 0x00, // REG_UNKNOWN (0x3) ++ 0x00, // REG_MICBIAS_CTL (0x4) ++ 0x34, // REG_ANAMICL (0x5) ++ 0x14, // REG_ANAMICR (0x6) ++ 0x0a, // REG_AVADC_CTL (0x7) ++ 0x00, // REG_ADCMICSEL (0x8) ++ 0x00, // REG_DIGMIXING (0x9) ++ 0x0c, // REG_ATXL1PGA (0xA) ++ 0x0c, // REG_ATXR1PGA (0xB) ++ 0x00, // REG_AVTXL2PGA (0xC) ++ 0x00, // REG_AVTXR2PGA (0xD) ++ 0x01, // REG_AUDIO_IF (0xE) ++ 0x00, // REG_VOICE_IF (0xF) ++ 0x00, // REG_ARXR1PGA (0x10) ++ 0x00, // REG_ARXL1PGA (0x11) ++ 0x6c, // REG_ARXR2PGA (0x12) ++ 0x6c, // REG_ARXL2PGA (0x13) ++ 0x00, // REG_VRXPGA (0x14) ++ 0x00, // REG_VSTPGA (0x15) ++ 0x00, // REG_VRX2ARXPGA (0x16) ++ 0x0c, // REG_AVDAC_CTL (0x17) ++ 0x00, // REG_ARX2VTXPGA (0x18) ++ 0x00, // REG_ARXL1_APGA_CTL (0x19) ++ 0x00, // REG_ARXR1_APGA_CTL (0x1A) ++ 0x4b, // REG_ARXL2_APGA_CTL (0x1B) ++ 0x4b, // REG_ARXR2_APGA_CTL (0x1C) ++ 0x00, // REG_ATX2ARXPGA (0x1D) ++ 0x00, // REG_BT_IF (0x1E) ++ 0x00, // REG_BTPGA (0x1F) ++ 0x00, // REG_BTSTPGA (0x20) ++ 0x00, // REG_EAR_CTL (0x21) ++ 0x24, // REG_HS_SEL (0x22) ++ 0x0a, // REG_HS_GAIN_SET (0x23) ++ 0x00, // REG_HS_POPN_SET (0x24) ++ 0x00, // REG_PREDL_CTL (0x25) ++ 0x00, // REG_PREDR_CTL (0x26) ++ 0x00, // REG_PRECKL_CTL (0x27) ++ 0x00, // REG_PRECKR_CTL (0x28) ++ 0x00, // REG_HFL_CTL (0x29) ++ 0x00, // REG_HFR_CTL (0x2A) ++ 0x00, // REG_ALC_CTL (0x2B) ++ 0x00, // REG_ALC_SET1 (0x2C) ++ 0x00, // REG_ALC_SET2 (0x2D) ++ 0x00, // REG_BOOST_CTL (0x2E) ++ 0x01, // REG_SOFTVOL_CTL (0x2F) ++ 0x00, // REG_DTMF_FREQSEL (0x30) ++ 0x00, // REG_DTMF_TONEXT1H (0x31) ++ 0x00, // REG_DTMF_TONEXT1L (0x32) ++ 0x00, // REG_DTMF_TONEXT2H (0x33) ++ 0x00, // REG_DTMF_TONEXT2L (0x34) ++ 0x00, // REG_DTMF_TONOFF (0x35) ++ 0x00, // REG_DTMF_WANONOFF (0x36) ++ 0x00, // REG_I2S_RX_SCRAMBLE_H (0x37) ++ 0x00, // REG_I2S_RX_SCRAMBLE_M (0x38) ++ 0x00, // REG_I2S_RX_SCRAMBLE_L (0x39) ++ 0x16, // REG_APLL_CTL (0x3A) ++ 0x00, // REG_DTMF_CTL (0x3B) ++ 0x00, // REG_DTMF_PGA_CTL2 (0x3C) ++ 0x00, // REG_DTMF_PGA_CTL1 (0x3D) ++ 0x00, // REG_MISC_SET_1 (0x3E) ++ 0x00, // REG_PCMBTMUX (0x3F) ++ 0x00, // REG_RX_PATH_SEL (0x43) ++ 0x00, // REG_VDL_APGA_CTL (0x44) ++ 0x00, // REG_VIBRA_CTL (0x45) ++ 0x00, // REG_VIBRA_SET (0x46) ++ 0x00, // REG_VIBRA_PWM_SET (0x47) ++ 0x00, // REG_ANAMIC_GAIN (0x48) ++ 0x00, // REG_MISC_SET_2 (0x49) ++}; ++ ++static void twl4030_dump_registers(void) ++{ ++ int i = 0; ++ u8 data; ++ ++ printk(KERN_INFO "TWL 4030 Register dump for Audio Module\n"); ++ ++ for (i = REG_CODEC_MODE; i <= REG_MISC_SET_2; i++) { ++ twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &data, i); ++ printk(KERN_INFO "Register[0x%02x]=0x%02x\n", i, data); ++ } ++} ++ ++struct twl4030_priv { ++ unsigned int dummy; ++}; ++ ++/* ++ * read twl4030 register cache ++ */ ++static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec, ++ unsigned int reg) ++{ ++ u8 *cache = codec->reg_cache; ++ ++ return cache[reg]; ++} ++ ++/* ++ * write twl4030 register cache ++ */ ++static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec, ++ u8 reg, u8 value) ++{ ++ u8 *cache = codec->reg_cache; ++ ++ if (reg >= TWL4030_CACHEREGNUM) ++ return; ++ cache[reg] = value; ++} ++ ++/* ++ * write to the twl4030 register space ++ */ ++static int twl4030_write(struct snd_soc_codec *codec, ++ unsigned int reg, unsigned int value) ++{ ++ twl4030_write_reg_cache(codec, reg, value); ++ return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg); ++} ++ ++static void twl4030_init_chip(void) ++{ ++ unsigned char byte; ++ int i; ++ ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[REG_CODEC_MODE] & 0xfd, REG_CODEC_MODE); ++ ++ udelay(10); /* 10 ms delay for power settling */ ++ ++ for (i = REG_OPTION; i <= REG_MISC_SET_2; i++) { ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, twl4030_reg[i], i); ++ } ++ ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[REG_CODEC_MODE], REG_CODEC_MODE); ++ ++ udelay(10); /* 10 ms delay for power settling */ ++ ++ /* initiate offset cancellation */ ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[REG_ANAMICL] | 0x80, REG_ANAMICL); ++ ++ /* wait for offset cancellation to complete */ ++ twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, REG_ANAMICL); ++ while ((byte & 0x80) == 0x80) ++ twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, REG_ANAMICL); ++ ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[REG_MISC_SET_1] | 0x02, REG_MISC_SET_1); ++ ++ twl4030_dump_registers(); ++} ++ ++static const struct snd_kcontrol_new twl4030_snd_controls[] = { ++ SOC_DOUBLE_R("Master Playback Volume", ++ REG_ARXL2PGA, REG_ARXR2PGA, ++ 0, 127, 0), ++ SOC_DOUBLE_R("Capture Volume", ++ REG_ATXL1PGA, REG_ATXR1PGA, ++ 0, 127, 0), ++}; ++ ++/* add non dapm controls */ ++static int twl4030_add_controls(struct snd_soc_codec *codec) ++{ ++ int err, i; ++ ++ for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) { ++ err = snd_ctl_add(codec->card, ++ snd_soc_cnew(&twl4030_snd_controls[i], ++ codec, NULL)); ++ if (err < 0) ++ return err; ++ } ++ ++ return 0; ++} ++ ++#define TWL4030_PWR 0 ++ ++static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { ++ SND_SOC_DAPM_INPUT("INL"), ++ SND_SOC_DAPM_INPUT("INR"), ++ ++ SND_SOC_DAPM_OUTPUT("OUTL"), ++ SND_SOC_DAPM_OUTPUT("OUTR"), ++ ++ SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0), ++ SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0), ++ ++ SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0), ++ SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0), ++}; ++ ++static const char *intercon[][3] = { ++ /* outputs */ ++ {"OUTL", NULL, "DACL"}, ++ {"OUTR", NULL, "DACR"}, ++ ++ /* inputs */ ++ {"ADCL", NULL, "INL"}, ++ {"ADCR", NULL, "INR"}, ++ ++ /* terminator */ ++ {NULL, NULL, NULL}, ++}; ++ ++static int twl4030_add_widgets(struct snd_soc_codec *codec) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(twl4030_dapm_widgets); i++) ++ snd_soc_dapm_new_control(codec, &twl4030_dapm_widgets[i]); ++ ++ /* set up audio path interconnects */ ++ for (i = 0; intercon[i][0] != NULL; i++) ++ snd_soc_dapm_connect_input(codec, intercon[i][0], ++ intercon[i][1], intercon[i][2]); ++ ++ snd_soc_dapm_new_widgets(codec); ++ return 0; ++} ++ ++static int twl4030_dapm_event(struct snd_soc_codec *codec, int event) ++{ ++ ++ printk(KERN_INFO "TWL4030 Audio Codec dapm event\n"); ++ switch (event) { ++ case SNDRV_CTL_POWER_D0: /* full On */ ++ break; ++ case SNDRV_CTL_POWER_D1: /* partial On */ ++ case SNDRV_CTL_POWER_D2: /* partial On */ ++ break; ++ case SNDRV_CTL_POWER_D3hot: /* off, with power */ ++ break; ++ case SNDRV_CTL_POWER_D3cold: /* off, without power */ ++ break; ++ } ++ codec->dapm_state = event; ++ ++ return 0; ++} ++ ++static void twl4030_power_up (struct snd_soc_codec *codec, u8 mode) ++{ ++ twl4030_write(codec, REG_CODEC_MODE, mode & ~CODECPDZ); ++ twl4030_write(codec, REG_CODEC_MODE, mode | CODECPDZ); ++ udelay(10); ++ ++ u8 popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET) | (0x40); ++ twl4030_write(codec, REG_HS_POPN_SET, popn); ++ ++ u8 hsgain = twl4030_read_reg_cache(codec, REG_HS_GAIN_SET) | (0x0a); ++ twl4030_write(codec, REG_HS_GAIN_SET, hsgain); ++ ++ popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET) | (0x02); ++ twl4030_write(codec, REG_HS_POPN_SET, popn); ++} ++ ++static void twl4030_power_down (struct snd_soc_codec *codec) ++{ ++ u8 popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET) & ~(0x02); ++ twl4030_write(codec, REG_HS_POPN_SET, popn); ++ ++ u8 hsgain = twl4030_read_reg_cache(codec, REG_HS_GAIN_SET) & ~(0x0f); ++ twl4030_write(codec, REG_HS_GAIN_SET, hsgain); ++ ++ popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET) & ~(0x40); ++ twl4030_write(codec, REG_HS_POPN_SET, popn); ++ ++ u8 mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE) & ~CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ udelay(10); ++} ++ ++ ++static int twl4030_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_device *socdev = rtd->socdev; ++ struct snd_soc_codec *codec = socdev->codec; ++ struct twl4030_priv *twl4030 = codec->private_data; ++ ++ twl4030_power_down(codec); ++ ++ u8 mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE) & ~CODECPDZ; ++ ++ mode &= ~APLL_RATE; ++ switch (params_rate(params)) { ++ case 44100: ++ printk(KERN_INFO "TWL4030 hw params: set rate to 44.1khz\n"); ++ mode |= APLL_RATE_44100; ++ break; ++ case 48000: ++ printk(KERN_INFO "TWL4030 hw params: set rate to 48khz\n"); ++ mode |= APLL_RATE_48000; ++ break; ++ default: ++ printk(KERN_INFO "TWL4030 hw params: unknown rate %d\n", params_rate(params)); ++ return -EINVAL; ++ } ++ ++ /* bit size */ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ printk(KERN_INFO "TWL4030 hw params: set format to S16_LE\n"); ++ break; ++ case SNDRV_PCM_FORMAT_S24_LE: ++ printk(KERN_INFO "TWL4030 hw params: set format to S24_LE\n"); ++ break; ++ default: ++ printk(KERN_INFO "TWL4030 hw params: unknown format %d\n", params_format(params)); ++ return -EINVAL; ++ } ++ ++ /* change rate and turn codec back on */ ++ twl4030_power_up(codec, mode); ++ ++ return 0; ++} ++ ++static int twl4030_mute(struct snd_soc_codec_dai *dai, int mute) ++{ ++ struct snd_soc_codec *codec = dai->codec; ++ ++ u8 ldac_reg = twl4030_read_reg_cache(codec, REG_ARXL2PGA); ++ u8 rdac_reg = twl4030_read_reg_cache(codec, REG_ARXR2PGA); ++ ++ if (mute) { ++ printk(KERN_INFO "TWL4030 Audio Codec mute\n"); ++ twl4030_write(codec, REG_ARXL2PGA, 0x00); ++ twl4030_write(codec, REG_ARXR2PGA, 0x00); ++ twl4030_write_reg_cache(codec, REG_ARXL2PGA, ldac_reg); ++ twl4030_write_reg_cache(codec, REG_ARXR2PGA, rdac_reg); ++ } ++ else { ++ printk(KERN_INFO "TWL4030 Audio Codec unmute: %02x/%02x\n", ldac_reg, rdac_reg); ++ twl4030_write(codec, REG_ARXL2PGA, ldac_reg); ++ twl4030_write(codec, REG_ARXR2PGA, rdac_reg); ++ } ++ ++ return 0; ++} ++ ++static int twl4030_set_dai_fmt(struct snd_soc_codec_dai *codec_dai, ++ unsigned int fmt) ++{ ++ struct snd_soc_codec *codec = codec_dai->codec; ++ struct twl4030_priv *twl4030 = codec->private_data; ++ ++ /* get current format */ ++ u8 format = twl4030_read_reg_cache(codec, REG_AUDIO_IF); ++ ++ /* set master/slave audio interface */ ++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { ++ case SND_SOC_DAIFMT_CBM_CFM: ++ printk(KERN_INFO "TWL4030 set dai fmt: master\n"); ++ format &= ~(AIF_SLAVE_EN); ++ format |= CLK256FS_EN; ++ break; ++ case SND_SOC_DAIFMT_CBS_CFS: ++ printk(KERN_INFO "TWL4030 set dai fmt: slave\n"); ++ format &= ~(CLK256FS_EN); ++ format |= AIF_SLAVE_EN; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ /* interface format */ ++ format &= ~AIF_FORMAT; ++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_I2S: ++ printk(KERN_INFO "TWL4030 set dai fmt: i2s\n"); ++ format |= AIF_FORMAT_CODEC; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ /* turn off codec before changing format */ ++ twl4030_power_down(codec); ++ ++ /* change format */ ++ twl4030_write(codec, REG_AUDIO_IF, format); ++ ++ u8 mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); ++ twl4030_power_up(codec, mode); ++ ++ return 0; ++} ++ ++#define TWL4030_RATES SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 ++#define TWL4030_FORMATS SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE ++ ++struct snd_soc_codec_dai twl4030_dai = { ++ .name = "twl4030", ++ .playback = { ++ .stream_name = "Playback", ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = TWL4030_RATES, ++ .formats = TWL4030_FORMATS,}, ++ .capture = { ++ .stream_name = "Capture", ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = TWL4030_RATES, ++ .formats = TWL4030_FORMATS,}, ++ .ops = { ++ .hw_params = twl4030_hw_params, ++ }, ++ .dai_ops = { ++ .digital_mute = twl4030_mute, ++ .set_fmt = twl4030_set_dai_fmt, ++ } ++}; ++ ++EXPORT_SYMBOL_GPL(twl4030_dai); ++ ++static int twl4030_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec = socdev->codec; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec suspend\n"); ++ twl4030_dapm_event(codec, SNDRV_CTL_POWER_D3cold); ++ ++ return 0; ++} ++ ++static int twl4030_resume(struct platform_device *pdev) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec = socdev->codec; ++ int i; ++ u16 *cache = codec->reg_cache; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec resume\n"); ++ /* Sync reg_cache with the hardware */ ++ for (i = REG_CODEC_MODE; i <= REG_MISC_SET_2; i++) { ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, cache[i], i); ++ } ++ twl4030_dapm_event(codec, SNDRV_CTL_POWER_D3hot); ++ twl4030_dapm_event(codec, codec->suspend_dapm_state); ++ return 0; ++} ++ ++/* ++ * initialize the driver ++ * register the mixer and dsp interfaces with the kernel ++ */ ++ ++static int twl4030_init(struct snd_soc_device *socdev) ++{ ++ struct snd_soc_codec *codec = socdev->codec; ++ int ret = 0; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec init \n"); ++ ++ twl4030_init_chip(); ++ ++ codec->name = "twl4030"; ++ codec->owner = THIS_MODULE; ++ codec->read = twl4030_read_reg_cache; ++ codec->write = twl4030_write; ++ codec->dapm_event = twl4030_dapm_event; ++ codec->dai = &twl4030_dai; ++ codec->num_dai = 1; ++ codec->reg_cache_size = sizeof(twl4030_reg); ++ codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg), GFP_KERNEL); ++ if (codec->reg_cache == NULL) ++ return -ENOMEM; ++ ++ /* register pcms */ ++ ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); ++ if (ret < 0) { ++ printk(KERN_ERR "twl4030: failed to create pcms\n"); ++ goto pcm_err; ++ } ++ ++ twl4030_add_controls(codec); ++ twl4030_add_widgets(codec); ++ ++ ret = snd_soc_register_card(socdev); ++ if (ret < 0) { ++ printk(KERN_ERR "twl4030: failed to register card\n"); ++ goto card_err; ++ } ++ ++ return ret; ++ ++card_err: ++ printk(KERN_INFO "TWL4030 Audio Codec init card error\n"); ++ snd_soc_free_pcms(socdev); ++ snd_soc_dapm_free(socdev); ++pcm_err: ++ printk(KERN_INFO "TWL4030 Audio Codec init pcm error\n"); ++ kfree(codec->reg_cache); ++ return ret; ++} ++ ++static struct snd_soc_device *twl4030_socdev; ++ ++static int twl4030_probe(struct platform_device *pdev) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec; ++ struct twl4030_priv *twl4030; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec probe\n"); ++ ++ codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); ++ if (codec == NULL) ++ return -ENOMEM; ++ ++ twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL); ++ if (twl4030 == NULL) { ++ kfree(codec); ++ return -ENOMEM; ++ } ++ ++ codec->private_data = twl4030; ++ socdev->codec = codec; ++ mutex_init(&codec->mutex); ++ INIT_LIST_HEAD(&codec->dapm_widgets); ++ INIT_LIST_HEAD(&codec->dapm_paths); ++ ++ twl4030_socdev = socdev; ++ twl4030_init(socdev); ++ ++ printk(KERN_INFO "TWL4030 Audio Codec probe exit\n"); ++ return 0; ++} ++ ++static int twl4030_remove(struct platform_device *pdev) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec = socdev->codec; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec remove\n"); ++ kfree(codec->private_data); ++ kfree(codec); ++ ++ return 0; ++} ++ ++struct snd_soc_codec_device soc_codec_dev_twl4030 = { ++ .probe = twl4030_probe, ++ .remove = twl4030_remove, ++ .suspend = twl4030_suspend, ++ .resume = twl4030_resume, ++}; ++EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030); ++ ++MODULE_DESCRIPTION("ASoC TWL4030 codec driver"); ++MODULE_AUTHOR("Steve Sakoman"); ++MODULE_LICENSE("GPL"); +diff --git a/sound/soc/codecs/twl4030.h b/sound/soc/codecs/twl4030.h +new file mode 100644 +index 0000000..af8eb43 +--- /dev/null ++++ b/sound/soc/codecs/twl4030.h +@@ -0,0 +1,125 @@ ++/* ++ * ALSA SoC TWL4030 codec driver ++ * ++ * Author: Steve Sakoman, <steve@sakoman.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __TWL4030_AUDIO_H__ ++#define __TWL4030_AUDIO_H__ ++ ++#define REG_CODEC_MODE 0x1 ++#define REG_OPTION 0x2 ++#define REG_UNKNOWN 0x3 ++#define REG_MICBIAS_CTL 0x4 ++#define REG_ANAMICL 0x5 ++#define REG_ANAMICR 0x6 ++#define REG_AVADC_CTL 0x7 ++#define REG_ADCMICSEL 0x8 ++#define REG_DIGMIXING 0x9 ++#define REG_ATXL1PGA 0xA ++#define REG_ATXR1PGA 0xB ++#define REG_AVTXL2PGA 0xC ++#define REG_AVTXR2PGA 0xD ++#define REG_AUDIO_IF 0xE ++#define REG_VOICE_IF 0xF ++#define REG_ARXR1PGA 0x10 ++#define REG_ARXL1PGA 0x11 ++#define REG_ARXR2PGA 0x12 ++#define REG_ARXL2PGA 0x13 ++#define REG_VRXPGA 0x14 ++#define REG_VSTPGA 0x15 ++#define REG_VRX2ARXPGA 0x16 ++#define REG_AVDAC_CTL 0x17 ++#define REG_ARX2VTXPGA 0x18 ++#define REG_ARXL1_APGA_CTL 0x19 ++#define REG_ARXR1_APGA_CTL 0x1A ++#define REG_ARXL2_APGA_CTL 0x1B ++#define REG_ARXR2_APGA_CTL 0x1C ++#define REG_ATX2ARXPGA 0x1D ++#define REG_BT_IF 0x1E ++#define REG_BTPGA 0x1F ++#define REG_BTSTPGA 0x20 ++#define REG_EAR_CTL 0x21 ++#define REG_HS_SEL 0x22 ++#define REG_HS_GAIN_SET 0x23 ++#define REG_HS_POPN_SET 0x24 ++#define REG_PREDL_CTL 0x25 ++#define REG_PREDR_CTL 0x26 ++#define REG_PRECKL_CTL 0x27 ++#define REG_PRECKR_CTL 0x28 ++#define REG_HFL_CTL 0x29 ++#define REG_HFR_CTL 0x2A ++#define REG_ALC_CTL 0x2B ++#define REG_ALC_SET1 0x2C ++#define REG_ALC_SET2 0x2D ++#define REG_BOOST_CTL 0x2E ++#define REG_SOFTVOL_CTL 0x2F ++#define REG_DTMF_FREQSEL 0x30 ++#define REG_DTMF_TONEXT1H 0x31 ++#define REG_DTMF_TONEXT1L 0x32 ++#define REG_DTMF_TONEXT2H 0x33 ++#define REG_DTMF_TONEXT2L 0x34 ++#define REG_DTMF_TONOFF 0x35 ++#define REG_DTMF_WANONOFF 0x36 ++#define REG_I2S_RX_SCRAMBLE_H 0x37 ++#define REG_I2S_RX_SCRAMBLE_M 0x38 ++#define REG_I2S_RX_SCRAMBLE_L 0x39 ++#define REG_APLL_CTL 0x3A ++#define REG_DTMF_CTL 0x3B ++#define REG_DTMF_PGA_CTL2 0x3C ++#define REG_DTMF_PGA_CTL1 0x3D ++#define REG_MISC_SET_1 0x3E ++#define REG_PCMBTMUX 0x3F ++#define REG_RX_PATH_SEL 0x43 ++#define REG_VDL_APGA_CTL 0x44 ++#define REG_VIBRA_CTL 0x45 ++#define REG_VIBRA_SET 0x46 ++#define REG_VIBRA_PWM_SET 0x47 ++#define REG_ANAMIC_GAIN 0x48 ++#define REG_MISC_SET_2 0x49 ++ ++#define TWL4030_CACHEREGNUM REG_MISC_SET_2 + 1 ++ ++/* Bitfield Definitions */ ++ ++/* CODEC_MODE Fields */ ++ ++#define APLL_RATE 0xF0 ++#define APLL_RATE_8000 0x00 ++#define APLL_RATE_11025 0x10 ++#define APLL_RATE_12000 0x20 ++#define APLL_RATE_16000 0x40 ++#define APLL_RATE_22050 0x50 ++#define APLL_RATE_24000 0x60 ++#define APLL_RATE_32000 0x80 ++#define APLL_RATE_44100 0x90 ++#define APLL_RATE_48000 0xa0 ++#define SEL_16K 0x04 ++#define CODECPDZ 0x02 ++#define OPT_MODE 0x01 ++ ++/* AUDIO_IF Fields */ ++ ++#define AIF_SLAVE_EN 0x80 ++#define DATA_WIDTH 0x60 ++#define DATA_WIDTH_16S_16W 0x00 ++#define DATA_WIDTH_32S_16W 0x40 ++#define DATA_WIDTH_32S_24W 0x60 ++#define AIF_FORMAT 0x18 ++#define AIF_FORMAT_CODEC 0x00 ++#define AIF_FORMAT_LEFT 0x08 ++#define AIF_FORMAT_RIGHT 0x10 ++#define AIF_FORMAT_TDM 0x18 ++#define AIF_TRI_EN 0x04 ++#define CLK256FS_EN 0x02 ++#define AIF_EN 0x01 ++ ++ ++extern struct snd_soc_codec_dai twl4030_dai; ++extern struct snd_soc_codec_device soc_codec_dev_twl4030; ++ ++#endif /* End of __TWL4030_AUDIO_H__ */ +diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig +index 0230d83..8703cea 100644 +--- a/sound/soc/omap/Kconfig ++++ b/sound/soc/omap/Kconfig +@@ -16,4 +16,20 @@ config SND_OMAP_SOC_N810 + help + Say Y if you want to add support for SoC audio on Nokia N810. + ++config SND_OMAP_SOC_OMAP3EVM ++ tristate "SoC Audio support for OMAP3 EVM" ++ depends on SND_OMAP_SOC && MACH_OMAP3EVM ++ select SND_OMAP_SOC_MCBSP ++ select SND_SOC_TWL4030 ++ help ++ Say Y if you want to add support for SoC audio on the OMAP3 EVM. ++ ++config SND_OMAP_SOC_OMAP3BEAGLE ++ tristate "SoC Audio support for OMAP3 Beagle" ++ depends on SND_OMAP_SOC && MACH_OMAP3_BEAGLE ++ select SND_OMAP_SOC_MCBSP ++ select SND_SOC_TWL4030 ++ help ++ Say Y if you want to add support for SoC audio on the OMAP3 Beagle. ++ + endmenu +diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile +index d8d8d58..638a240 100644 +--- a/sound/soc/omap/Makefile ++++ b/sound/soc/omap/Makefile +@@ -7,5 +7,10 @@ obj-$(CONFIG_SND_OMAP_SOC_MCBSP) += snd-soc-omap-mcbsp.o + + # OMAP Machine Support + snd-soc-n810-objs := n810.o ++snd-soc-omap3evm-objs := omap3evm.o ++snd-soc-omap3beagle-objs := omap3beagle.o + + obj-$(CONFIG_SND_OMAP_SOC_N810) += snd-soc-n810.o ++obj-$(CONFIG_SND_OMAP_SOC_OMAP3EVM) += snd-soc-omap3evm.o ++obj-$(CONFIG_SND_OMAP_SOC_OMAP3BEAGLE) += snd-soc-omap3beagle.o ++ +diff --git a/sound/soc/omap/omap3beagle.c b/sound/soc/omap/omap3beagle.c +new file mode 100644 +index 0000000..fb79938 +--- /dev/null ++++ b/sound/soc/omap/omap3beagle.c +@@ -0,0 +1,180 @@ ++/* ++ * omap3beagle.c -- SoC audio for OMAP3 Beagle ++ * ++ * Author: Steve Sakoman <steve@sakoman.com> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA ++ * 02110-1301 USA ++ * ++ */ ++ ++#include <linux/clk.h> ++#include <linux/platform_device.h> ++#include <sound/core.h> ++#include <sound/pcm.h> ++#include <sound/soc.h> ++#include <sound/soc-dapm.h> ++ ++#include <asm/mach-types.h> ++#include <asm/arch/hardware.h> ++#include <asm/arch/gpio.h> ++#include <asm/arch/mcbsp.h> ++ ++#include "omap-mcbsp.h" ++#include "omap-pcm.h" ++#include "../codecs/twl4030.h" ++ ++static int omap3beagle_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai; ++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; ++ int ret; ++ ++ /* Set codec DAI configuration */ ++ ret = codec_dai->dai_ops.set_fmt(codec_dai, ++ SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM); ++ if (ret < 0) { ++ printk(KERN_INFO "can't set codec DAI configuration\n"); ++ return ret; ++ } ++ ++ /* Set cpu DAI configuration */ ++ ret = cpu_dai->dai_ops.set_fmt(cpu_dai, ++ SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM); ++ if (ret < 0) { ++ printk(KERN_INFO "can't set cpu DAI configuration\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static struct snd_soc_ops omap3beagle_ops = { ++ .hw_params = omap3beagle_hw_params, ++}; ++ ++static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { ++ SND_SOC_DAPM_HP("Headphone Jack", NULL), ++ SND_SOC_DAPM_LINE("Line In", NULL), ++}; ++ ++static const char *audio_map[][3] = { ++ {"Headphone Jack", NULL, "HPLOUT"}, ++ {"Headphone Jack", NULL, "HPROUT"}, ++ ++ {"Line In", NULL, "Line In"}, ++ {"Line In", NULL, "Line In"}, ++}; ++ ++static int omap3beagle_twl4030_init(struct snd_soc_codec *codec) ++{ ++ int i; ++ ++ printk(KERN_INFO "OMAP3 Beagle TWL4030 SoC init\n"); ++ ++ /* Add omap3beagle specific widgets */ ++ for (i = 0; i < ARRAY_SIZE(twl4030_dapm_widgets); i++) ++ snd_soc_dapm_new_control(codec, &twl4030_dapm_widgets[i]); ++ ++ /* Set up omap3beagle specific audio path audio_map */ ++ for (i = 0; i < ARRAY_SIZE(audio_map); i++) ++ snd_soc_dapm_connect_input(codec, audio_map[i][0], ++ audio_map[i][1], audio_map[i][2]); ++ ++ /* always connected */ ++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1); ++ snd_soc_dapm_set_endpoint(codec, "Line In", 1); ++ ++ snd_soc_dapm_sync_endpoints(codec); ++ ++ return 0; ++} ++ ++/* Digital audio interface glue - connects codec <--> CPU */ ++static struct snd_soc_dai_link omap3beagle_dai = { ++ .name = "TWL4030", ++ .stream_name = "TWL4030", ++ .cpu_dai = &omap_mcbsp_dai[0], ++ .codec_dai = &twl4030_dai, ++ .init = omap3beagle_twl4030_init, ++ .ops = &omap3beagle_ops, ++}; ++ ++/* Audio machine driver */ ++static struct snd_soc_machine snd_soc_machine_omap3beagle = { ++ .name = "omap3beagle", ++ .dai_link = &omap3beagle_dai, ++ .num_links = 1, ++}; ++ ++/* Audio subsystem */ ++static struct snd_soc_device omap3beagle_snd_devdata = { ++ .machine = &snd_soc_machine_omap3beagle, ++ .platform = &omap_soc_platform, ++ .codec_dev = &soc_codec_dev_twl4030, ++}; ++ ++static struct platform_device *omap3beagle_snd_device; ++ ++static int __init omap3beagle_soc_init(void) ++{ ++ int ret; ++ ++ printk(KERN_INFO "OMAP3 Beagle SoC init\n"); ++ if (!machine_is_omap3_beagle()) { ++ printk(KERN_INFO "Not OMAP3 Beagle!\n"); ++ return -ENODEV; ++ } ++ ++ omap3beagle_snd_device = platform_device_alloc("soc-audio", -1); ++ if (!omap3beagle_snd_device) { ++ printk(KERN_INFO "Platform device allocation failed\n"); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(omap3beagle_snd_device, &omap3beagle_snd_devdata); ++ omap3beagle_snd_devdata.dev = &omap3beagle_snd_device->dev; ++ *(unsigned int *)omap3beagle_dai.cpu_dai->private_data = 1; /* McBSP2 */ ++ ++ ret = platform_device_add(omap3beagle_snd_device); ++ if (ret) ++ goto err1; ++ ++ return 0; ++ ++err1: ++ printk(KERN_INFO "Unable to add platform device\n"); ++ platform_device_put(omap3beagle_snd_device); ++ ++ return ret; ++} ++ ++static void __exit omap3beagle_soc_exit(void) ++{ ++ printk(KERN_INFO "OMAP3 Beagle SoC exit\n"); ++ platform_device_unregister(omap3beagle_snd_device); ++} ++ ++module_init(omap3beagle_soc_init); ++module_exit(omap3beagle_soc_exit); ++ ++MODULE_AUTHOR("Steve Sakoman <steve@sakoman.com>"); ++MODULE_DESCRIPTION("ALSA SoC OMAP3 Beagle"); ++MODULE_LICENSE("GPL"); +diff --git a/sound/soc/omap/omap3evm.c b/sound/soc/omap/omap3evm.c +new file mode 100644 +index 0000000..32d4f5d +--- /dev/null ++++ b/sound/soc/omap/omap3evm.c +@@ -0,0 +1,180 @@ ++/* ++ * omap3evm.c -- SoC audio for OMAP3 EVM ++ * ++ * Author: Steve Sakoman <steve@sakoman.com> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA ++ * 02110-1301 USA ++ * ++ */ ++ ++#include <linux/clk.h> ++#include <linux/platform_device.h> ++#include <sound/core.h> ++#include <sound/pcm.h> ++#include <sound/soc.h> ++#include <sound/soc-dapm.h> ++ ++#include <asm/mach-types.h> ++#include <asm/arch/hardware.h> ++#include <asm/arch/gpio.h> ++#include <asm/arch/mcbsp.h> ++ ++#include "omap-mcbsp.h" ++#include "omap-pcm.h" ++#include "../codecs/twl4030.h" ++ ++static int omap3evm_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai; ++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; ++ int ret; ++ ++ /* Set codec DAI configuration */ ++ ret = codec_dai->dai_ops.set_fmt(codec_dai, ++ SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM); ++ if (ret < 0) { ++ printk(KERN_INFO "can't set codec DAI configuration\n"); ++ return ret; ++ } ++ ++ /* Set cpu DAI configuration */ ++ ret = cpu_dai->dai_ops.set_fmt(cpu_dai, ++ SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM); ++ if (ret < 0) { ++ printk(KERN_INFO "can't set cpu DAI configuration\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static struct snd_soc_ops omap3evm_ops = { ++ .hw_params = omap3evm_hw_params, ++}; ++ ++static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { ++ SND_SOC_DAPM_HP("Headphone Jack", NULL), ++ SND_SOC_DAPM_LINE("Line In", NULL), ++}; ++ ++static const char *audio_map[][3] = { ++ {"Headphone Jack", NULL, "HPLOUT"}, ++ {"Headphone Jack", NULL, "HPROUT"}, ++ ++ {"Line In", NULL, "Line In"}, ++ {"Line In", NULL, "Line In"}, ++}; ++ ++static int omap3evm_twl4030_init(struct snd_soc_codec *codec) ++{ ++ int i; ++ ++ printk(KERN_INFO "OMAP3 EVM TWL4030 SoC init\n"); ++ ++ /* Add omap3evm specific widgets */ ++ for (i = 0; i < ARRAY_SIZE(twl4030_dapm_widgets); i++) ++ snd_soc_dapm_new_control(codec, &twl4030_dapm_widgets[i]); ++ ++ /* Set up omap3evm specific audio path audio_map */ ++ for (i = 0; i < ARRAY_SIZE(audio_map); i++) ++ snd_soc_dapm_connect_input(codec, audio_map[i][0], ++ audio_map[i][1], audio_map[i][2]); ++ ++ /* always connected */ ++ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1); ++ snd_soc_dapm_set_endpoint(codec, "Line In", 1); ++ ++ snd_soc_dapm_sync_endpoints(codec); ++ ++ return 0; ++} ++ ++/* Digital audio interface glue - connects codec <--> CPU */ ++static struct snd_soc_dai_link omap3evm_dai = { ++ .name = "TWL4030", ++ .stream_name = "TWL4030", ++ .cpu_dai = &omap_mcbsp_dai[0], ++ .codec_dai = &twl4030_dai, ++ .init = omap3evm_twl4030_init, ++ .ops = &omap3evm_ops, ++}; ++ ++/* Audio machine driver */ ++static struct snd_soc_machine snd_soc_machine_omap3evm = { ++ .name = "omap3evm", ++ .dai_link = &omap3evm_dai, ++ .num_links = 1, ++}; ++ ++/* Audio subsystem */ ++static struct snd_soc_device omap3evm_snd_devdata = { ++ .machine = &snd_soc_machine_omap3evm, ++ .platform = &omap_soc_platform, ++ .codec_dev = &soc_codec_dev_twl4030, ++}; ++ ++static struct platform_device *omap3evm_snd_device; ++ ++static int __init omap3evm_soc_init(void) ++{ ++ int ret; ++ ++ printk(KERN_INFO "OMAP3 EVM SoC init\n"); ++ if (!machine_is_omap3evm()) { ++ printk(KERN_INFO "Not OMAP3 EVM!\n"); ++ return -ENODEV; ++ } ++ ++ omap3evm_snd_device = platform_device_alloc("soc-audio", -1); ++ if (!omap3evm_snd_device) { ++ printk(KERN_INFO "Platform device allocation failed\n"); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(omap3evm_snd_device, &omap3evm_snd_devdata); ++ omap3evm_snd_devdata.dev = &omap3evm_snd_device->dev; ++ *(unsigned int *)omap3evm_dai.cpu_dai->private_data = 1; /* McBSP2 */ ++ ++ ret = platform_device_add(omap3evm_snd_device); ++ if (ret) ++ goto err1; ++ ++ return 0; ++ ++err1: ++ printk(KERN_INFO "Unable to add platform device\n"); ++ platform_device_put(omap3evm_snd_device); ++ ++ return ret; ++} ++ ++static void __exit omap3evm_soc_exit(void) ++{ ++ printk(KERN_INFO "OMAP3 EVM SoC exit\n"); ++ platform_device_unregister(omap3evm_snd_device); ++} ++ ++module_init(omap3evm_soc_init); ++module_exit(omap3evm_soc_exit); ++ ++MODULE_AUTHOR("Steve Sakoman <steve@sakoman.com>"); ++MODULE_DESCRIPTION("ALSA SoC OMAP3 EVM"); ++MODULE_LICENSE("GPL"); diff --git a/packages/linux/linux-omap2_git.bb b/packages/linux/linux-omap2_git.bb index 0e68729552..3147ef46a7 100644 --- a/packages/linux/linux-omap2_git.bb +++ b/packages/linux/linux-omap2_git.bb @@ -2,10 +2,10 @@ require linux-omap.inc FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/linux-omap2-git/${MACHINE}" -SRCREV = "6a32eb134fbf2ea1d384e0bfa8e9ba6eec952817" +SRCREV = "af933cd32a5e14f119a4acb4fe20055f6f8ab1aa" -PV = "2.6.25+2.6.26-rc7+${PR}+git${SRCREV}" -PR = "r27" +PV = "2.6.25+2.6.26-rc8+${PR}+git${SRCREV}" +PR = "r30" SRC_URI = "git://source.mvista.com/git/linux-omap-2.6.git;protocol=git \ @@ -14,13 +14,14 @@ SRC_URI = "git://source.mvista.com/git/linux-omap-2.6.git;protocol=git \ SRC_URI_append_beagleboard = " file://no-harry-potter.diff;patch=1 \ file://0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch;patch=1 \ file://flash.patch;patch=1 \ - file://0001-ARM-OMAP-SmartReflex-driver.patch;patch=1 \ - file://0002-ARM-OMAP-SmartReflex-driver.patch;patch=1 \ - file://0003-ARM-OMAP-SmartReflex-driver.patch;patch=1 \ file://0001-omap3-cpuidle.patch;patch=1 \ file://0002-omap3-cpuidle.patch;patch=1 \ file://timer-suppression.patch;patch=1 \ file://fix-dispc-clocks.patch;patch=1 \ + file://soc.patch;patch=1 \ + file://16bpp.patch;patch=1 \ + file://omap3-dppl-divider.patch;patch=1 \ + file://omap3-jitter.patch;patch=1 \ " SRC_URI_append_omap3evm = " file://no-harry-potter.diff;patch=1 \ diff --git a/packages/linux/linux-openezx-devel_svn.bb b/packages/linux/linux-openezx-devel_svn.bb new file mode 100644 index 0000000000..34daac007c --- /dev/null +++ b/packages/linux/linux-openezx-devel_svn.bb @@ -0,0 +1,63 @@ +DESCRIPTION = "OpenEZX 2.6 Linux Development Kernel for the Motorola EZX GSM phones" +AUTHOR = "The OpenEZX Team <openezx-devel@lists.openezx.org>" +HOMEPAGE = "http://www.openezx.org" + +DEFAULT_PREFERENCE = "-1" + +require linux.inc + +RPSRC = "http://www.rpsys.net/openzaurus/patches/archive" + +KERNEL_RELEASE = "2.6.24" +KERNEL_PATCHES = "kernel-2.6.24.x-patches" +PV = "${KERNEL_RELEASE}+svnr${SRCREV}" +PR = "r0" + +SRC_URI = "\ + ${KERNELORG_MIRROR}/pub/linux/kernel/v2.6/linux-${KERNEL_RELEASE}.tar.bz2 \ + svn://svn.openezx.org/branches;module=${KERNEL_PATCHES};proto=http \ +# file://logo_linux_clut224.ppm \ +" +S = "${WORKDIR}/linux-${KERNEL_RELEASE}" + + +############################################################## +# kernel image resides on a seperate flash partition (for now) +# But we can flash it from userspace (flash_unlock /dev/mtdX && flash_eraseall /dev/mtdX && flashcp /boot/zImage /dev/mtdX) +# so lets make a package of it. What about a postinst that flashes the new kernel? + +COMPATIBLE_HOST = "arm.*-linux" +COMPATIBLE_MACHINE = '(a780|e680|a1200|rorkre2|rokre6)' + +# For now the code for serial console is disabled in compress.c +#CMDLINE_CON = "console=ttyS2,115200n8 console=tty1 " +CMDLINE_CON = "console=tty1 " + +CMDLINE_ROOT = "root=/dev/mmcblk0p2 rootfstype=ext2 rootwait=1" +CMDLINE_NFSROOT = "root=/dev/nfs rootfstype=nfs nfsroot=192.168.0.200:/export/ezx-image rootdelay=1 " +# Uncomment to enable dyntick +#CMDLINE_OTHER = "dyntick=enable" +CMDLINE_DEBUG = '${@base_conditional("DISTRO_TYPE", "release", "quiet", "debug",d)}' +CMDLINE_IP = "ip=192.168.0.202:192.168.0.200:192.168.0.200:255.255.255.0" +CMDLINE_MEM = "mem=32M@0xA0000000 mem=16M@0xAC000000" +CMDLINE = "${CMDLINE_CON} ${CMDLINE_ROOT} ${CMDLINE_IP} ${CMDLINE_ROTATE} ${CMDLINE_OTHER} ${CMDLINE_DEBUG} ${CMDLINE_MEM}" +# Uncomment to use root-over-nfs-over-usb +#CMDLINE_NFSROOT_USB = "${CMDLINE_CON} ${CMDLINE_NFSROOT} ${CMDLINE_IP} ${CMDLINE_ROTATE} ${CMDLINE_OTHER} ${CMDLINE_DEBUG} ${CMDLINE_MEM}" + +# 1024x1024 once was the maximum kernel size for boot-over-usb -- is it still? +#KERNEL_IMAGE_MAXSIZE = "1294336" + +############################################################### +# module configs specific to this kernel +# +#module_autoload_pxaficp_ir = "pxaficp_ir" +#module_autoload_snd-pcm-oss = "snd-pcm-oss" + +do_prepatch() { + mv ${WORKDIR}/${KERNEL_PATCHES}/defconfig-${MACHINE} ${WORKDIR}/defconfig + mv ${WORKDIR}/${KERNEL_PATCHES} ${S}/patches && cd ${S} && quilt push -av + mv patches patches.openezx + mv .pc .pc.old +} + +addtask prepatch after do_unpack before do_patch diff --git a/packages/linux/linux-ml403-slab-2.6.x/.mtn2git_empty b/packages/linux/linux-xilinx-slab/.mtn2git_empty index e69de29bb2..e69de29bb2 100644 --- a/packages/linux/linux-ml403-slab-2.6.x/.mtn2git_empty +++ b/packages/linux/linux-xilinx-slab/.mtn2git_empty diff --git a/packages/linux/linux-ml403-slab-2.6.x/xilinx-ml403_defconfig b/packages/linux/linux-xilinx-slab/xilinx-ml403_defconfig index 3babe21954..3babe21954 100644 --- a/packages/linux/linux-ml403-slab-2.6.x/xilinx-ml403_defconfig +++ b/packages/linux/linux-xilinx-slab/xilinx-ml403_defconfig diff --git a/packages/linux/linux-xilinx-slab_git.bb b/packages/linux/linux-xilinx-slab_git.bb new file mode 100644 index 0000000000..df71fee865 --- /dev/null +++ b/packages/linux/linux-xilinx-slab_git.bb @@ -0,0 +1,48 @@ +#Kernel for the xilinx-ml403 board using SecretLabs git tree +# Copyright (C) 2007, Stelios Koroneos - Digital OPSiS, All Rights Reserved +# Released under the MIT license (see packages/COPYING) +SECTION = "kernel" +DESCRIPTION = "Linux kernel for Xilinx ML403 Virtex 4 fpga board" +LICENSE = "GPL" + +SRCREV = "d7ed933b578d9c4dec0e23a5a6f78c464b31c47c" + +PR = "r3" +PV = "2.6.25+2.6.26+${PR}+git${SRCREV}" + +COMPATIBLE_MACHINE = "xilinx-ml403" + +#inherit kernel xilinx-bsp +inherit kernel + +S = "${WORKDIR}/git" + + +FILES_kernel-image = "/boot/zImage.elf" + +export OS = "Linux" +ARCH = "ppc" +KERNEL_IMAGETYPE = "zImage" +KERNEL_OUTPUT = "arch/ppc/boot/images/zImage.elf" + +SRC_URI = "\ + git://git.secretlab.ca/git/linux-2.6-virtex.git;protocol=git \ + " + +do_configure() { + + make ARCH=${ARCH} ml403_defconfig +} + +do_deploy() { + install -d ${DEPLOY_DIR_IMAGE} + install -m 0644 arch/${ARCH}/boot/images/${KERNEL_IMAGETYPE}.elf \ + ${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE}-${PV}-${MACHINE}-${DATETIME} +} + +#seems like 2.6.21 kernel images have moved (or is this only for the Denx kernel ?) +#so we need to copy the kernel image where kernel.bbclass expects it to be +#do_install_prepend() { +# install -m 0644 arch/${ARCH}/boot/images/${KERNEL_IMAGETYPE}.elf \ +# arch/${ARCH}/boot/${KERNEL_IMAGETYPE} +#} diff --git a/packages/mozilla/firefox_3.0.bb b/packages/mozilla/firefox_3.0.bb index 5e693a1692..1198344888 100644 --- a/packages/mozilla/firefox_3.0.bb +++ b/packages/mozilla/firefox_3.0.bb @@ -10,6 +10,8 @@ SRC_URI = "http://ftp.mozilla.org/pub/mozilla.org/firefox/releases/3.0/source/fi file://Bug405992.atomic.nspr.diff;patch=1 \ file://random_to_urandom.diff;patch=1 \ file://jemalloc-tls.patch;patch=1 \ + http://ftp.mozilla.org/pub/mozilla.org/js/js-1.7.0.tar.gz \ + http://ftp.debian.org/debian/pool/main/i/iceweasel/iceweasel_3.0~rc2-2.diff.gz;patch=1 \ " S = "${WORKDIR}/mozilla" @@ -19,6 +21,10 @@ S = "${WORKDIR}/mozilla" inherit mozilla require firefox.inc +do_unpack2() { + cp -pPr ${WORKDIR}/js/src* ${S}/js/ +} + do_compile_prepend() { cp ${WORKDIR}/jsautocfg.h ${S}/js/src/ sed -i "s|CPU_ARCH =|CPU_ARCH = ${TARGET_ARCH}|" security/coreconf/Linux.mk @@ -36,3 +42,5 @@ do_stage() { # removes 2 lines that call absent headers sed -e '178,179d' ${STAGING_INCDIR}/firefox-${PV}/nsIServiceManager.h } + +addtask unpack2 after do_unpack before do_patch diff --git a/packages/obexftp/obexftp_0.20.bb b/packages/obexftp/obexftp_0.20.bb index 386e83d6dc..2a0b310a49 100644 --- a/packages/obexftp/obexftp_0.20.bb +++ b/packages/obexftp/obexftp_0.20.bb @@ -2,17 +2,17 @@ DESCRIPTION = "OBEX Ftp Client based on openobex." SECTION = "console/network" HOMEPAGE = "http://openobex.triq.net" LICENSE = "GPL" -DEPENDS = "openobex libgsm virtual/libiconv" -PR = "r3" +DEPENDS = "openobex libgsm" +PR = "r4" SRC_URI = "${SOURCEFORGE_MIRROR}/openobex/obexftp-${PV}.tar.gz \ file://iconv.patch;patch=1 \ file://i-hate-libtool.patch;patch=1 \ file://m4.patch;patch=1" -inherit autotools +inherit autotools gettext -EXTRA_OECONF = "--enable-bluetooth --disable-swig --disable-perl --disable-python --disable-tcl --disable-builddocs" +EXTRA_OECONF += "--enable-bluetooth --disable-swig --disable-perl --disable-python --disable-tcl --disable-builddocs --disable-rpath" PARALLEL_MAKE = "" diff --git a/packages/obexftp/obexftp_0.22.bb b/packages/obexftp/obexftp_0.22.bb new file mode 100644 index 0000000000..89e10a72af --- /dev/null +++ b/packages/obexftp/obexftp_0.22.bb @@ -0,0 +1,30 @@ +DESCRIPTION = "OBEX Ftp Client based on openobex." +SECTION = "console/network" +HOMEPAGE = "http://dev.zuckschwerdt.org/openobex/wiki/ObexFtp" +LICENSE = "GPL" +DEPENDS = "openobex bluez-libs libusb virtual/libiconv" +PR = "r0" + +SRC_URI = "${SOURCEFORGE_MIRROR}/openobex/obexftp-${PV}.tar.bz2 \ + " + +inherit autotools pkgconfig + +EXTRA_OECONF += "--enable-bluetooth \ + --disable-swig \ + --disable-perl \ + --disable-python \ + --disable-tcl \ + --disable-ruby \ + --disable-builddocs \ + --disable-rpath \ + " + +PARALLEL_MAKE = "" + +LEAD_SONAME = "libobexftp.so" + +do_stage() { + autotools_stage_all +} + diff --git a/packages/olsrd/olsrd.inc b/packages/olsr/olsrd.inc index 990d8a1678..e668f11847 100644 --- a/packages/olsrd/olsrd.inc +++ b/packages/olsr/olsrd.inc @@ -5,7 +5,8 @@ SECTION = "console/network" PRIORITY = "optional" LICENSE = "BSD" -SRC_URI="http://www.olsr.org/releases/0.4/olsrd-${PV}.tar.bz2 \ +MAJ_VER = "${@bb.data.getVar('PV',d,1).split('.')[0]}.${@bb.data.getVar('PV',d,1).split('.')[1]}" +SRC_URI="http://www.olsr.org/releases/${MAJ_VER}/olsrd-${PV}.tar.bz2 \ file://init \ file://olsrd.conf" diff --git a/packages/olsrd/.mtn2git_empty b/packages/olsr/olsrd/.mtn2git_empty index e69de29bb2..e69de29bb2 100644 --- a/packages/olsrd/.mtn2git_empty +++ b/packages/olsr/olsrd/.mtn2git_empty diff --git a/packages/olsrd/files/0.4.9-httpinfo-makefile.diff b/packages/olsr/olsrd/0.4.9-httpinfo-makefile.diff index d4058f5b30..d4058f5b30 100644 --- a/packages/olsrd/files/0.4.9-httpinfo-makefile.diff +++ b/packages/olsr/olsrd/0.4.9-httpinfo-makefile.diff diff --git a/packages/olsrd/files/init b/packages/olsr/olsrd/init index 46b2aaabd2..46b2aaabd2 100644 --- a/packages/olsrd/files/init +++ b/packages/olsr/olsrd/init diff --git a/packages/olsrd/files/lib.diff b/packages/olsr/olsrd/lib.diff index f3935cc53d..f3935cc53d 100644 --- a/packages/olsrd/files/lib.diff +++ b/packages/olsr/olsrd/lib.diff diff --git a/packages/olsrd/files/olsrd.conf b/packages/olsr/olsrd/olsrd.conf index dbd0472803..dbd0472803 100644 --- a/packages/olsrd/files/olsrd.conf +++ b/packages/olsr/olsrd/olsrd.conf diff --git a/packages/olsrd/files/unbreak-makefile.patch b/packages/olsr/olsrd/unbreak-makefile.patch index cdf31df414..cdf31df414 100644 --- a/packages/olsrd/files/unbreak-makefile.patch +++ b/packages/olsr/olsrd/unbreak-makefile.patch diff --git a/packages/olsrd/olsrd_0.4.10.bb b/packages/olsr/olsrd_0.4.10.bb index 9722ca7d8d..9722ca7d8d 100644 --- a/packages/olsrd/olsrd_0.4.10.bb +++ b/packages/olsr/olsrd_0.4.10.bb diff --git a/packages/olsrd/olsrd_0.4.8.bb b/packages/olsr/olsrd_0.4.8.bb index 98a6344fb7..c2b9c825b6 100644 --- a/packages/olsrd/olsrd_0.4.8.bb +++ b/packages/olsr/olsrd_0.4.8.bb @@ -5,7 +5,8 @@ SECTION = "console/network" PRIORITY = "optional" LICENSE = "BSD" -SRC_URI="http://www.olsr.org/releases/0.4/olsrd-${PV}.tar.bz2 \ +MAJ_VER = "${@bb.data.getVar('PV',d,1).split('.')[0]}.${@bb.data.getVar('PV',d,1).split('.')[1]}" +SRC_URI="http://www.olsr.org/releases/${MAJ_VER}/olsrd-${PV}.tar.bz2 \ file://init \ file://olsrd.conf" diff --git a/packages/olsrd/olsrd_0.4.9.bb b/packages/olsr/olsrd_0.4.9.bb index 1f186f4bbb..1f186f4bbb 100644 --- a/packages/olsrd/olsrd_0.4.9.bb +++ b/packages/olsr/olsrd_0.4.9.bb diff --git a/packages/olsrd/olsrd_0.5.3.bb b/packages/olsr/olsrd_0.5.3.bb index 5bc448a126..34f20f64f8 100644 --- a/packages/olsrd/olsrd_0.5.3.bb +++ b/packages/olsr/olsrd_0.5.3.bb @@ -1,7 +1,8 @@ require olsrd.inc + PR = "r0" -SRC_URI="http://www.olsr.org/releases/0.5/olsrd-${PV}.tar.bz2 \ +SRC_URI="http://www.olsr.org/releases/${MAJ_VER}/olsrd-${PV}.tar.bz2 \ file://init \ file://olsrd.conf \ file://unbreak-makefile.patch;patch=1" diff --git a/packages/olsrd/olsrd_cvs.bb b/packages/olsr/olsrd_cvs.bb index a6d2ff7657..a6d2ff7657 100644 --- a/packages/olsrd/olsrd_cvs.bb +++ b/packages/olsr/olsrd_cvs.bb diff --git a/packages/olsrd/files/.mtn2git_empty b/packages/olsrd/files/.mtn2git_empty deleted file mode 100644 index e69de29bb2..0000000000 --- a/packages/olsrd/files/.mtn2git_empty +++ /dev/null diff --git a/packages/openocd/openocd-native_svn.bb b/packages/openocd/openocd-native_svn.bb index 4ab1d37fe2..3ca688b5c3 100644 --- a/packages/openocd/openocd-native_svn.bb +++ b/packages/openocd/openocd-native_svn.bb @@ -10,8 +10,8 @@ do_stage() { } do_deploy() { - install -d ${DEPLOY_DIR_IMAGE} - install -m 0755 src/openocd ${DEPLOY_DIR_IMAGE}/openocd + install -d ${DEPLOY_DIR_TOOLS} + install -m 0755 src/openocd ${DEPLOY_DIR_TOOLS}/openocd-${PV} } addtask deploy before do_package after do_install diff --git a/packages/openocd/openocd_svn.bb b/packages/openocd/openocd_svn.bb index d5c5ba05cd..6823eabb98 100644 --- a/packages/openocd/openocd_svn.bb +++ b/packages/openocd/openocd_svn.bb @@ -1,8 +1,8 @@ DESCRIPTION = "Free and Open On-Chip Debugging, In-System Programming and Boundary-Scan Testing" HOMEPAGE = "http://openocd.berlios.de/" LICENSE = "GPL" -PV = "0.0+r${SRCREV}" -PR = "r2" +PV = "0.0+svnr${SRCREV}" +PR = "r3" inherit autotools @@ -11,4 +11,4 @@ SRC_URI = "svn://svn.berlios.de/openocd;module=trunk \ S = "${WORKDIR}/trunk" DEPENDS = "libftdi" -EXTRA_OECONF = " --enable-ft2232_libftdi --disable-ftdi2232 --disable-ftd2xx" +EXTRA_OECONF = " --enable-ft2232_libftdi --disable-ftdi2232 --disable-ftd2xx" diff --git a/packages/s3c24xx-utils/s3c2410-boot-usb-native_svn.bb b/packages/s3c24xx-utils/s3c2410-boot-usb-native_svn.bb index 671606c201..675d07c910 100644 --- a/packages/s3c24xx-utils/s3c2410-boot-usb-native_svn.bb +++ b/packages/s3c24xx-utils/s3c2410-boot-usb-native_svn.bb @@ -1,10 +1,10 @@ DESCRIPTION = "Boots a S3C2410 device with a user supplied kernel zImage" DEPENDS = "libusb-native" SECTION = "devel" -AUTHOR = "Harald Welte" +AUTHOR = "Harald Welte <laforge@openmoko.org>" LICENSE = "GPL" -PV = "0.1.0+svn${SRCREV}" -PR = "r0" +PV = "0.1.0+svnr${SRCREV}" +PR = "r1" SRC_URI = "svn://svn.openmoko.org/trunk/src/host/;module=s3c2410_boot_usb;proto=https" S = "${WORKDIR}/s3c2410_boot_usb" @@ -16,8 +16,8 @@ do_compile() { } do_deploy() { - install -d ${DEPLOY_DIR_IMAGE} - install -m 0755 s3c2410-boot-usb ${DEPLOY_DIR_IMAGE} + install -d ${DEPLOY_DIR_TOOLS} + install -m 0755 s3c2410-boot-usb ${DEPLOY_DIR_TOOLS}/s3c2410-boot-usb-${PV} } do_stage() { diff --git a/packages/s3c24xx-utils/s3c24xx-gpio_svn.bb b/packages/s3c24xx-utils/s3c24xx-gpio_svn.bb index 516fbb0c3a..0a57d2c0e6 100644 --- a/packages/s3c24xx-utils/s3c24xx-gpio_svn.bb +++ b/packages/s3c24xx-utils/s3c24xx-gpio_svn.bb @@ -1,8 +1,9 @@ DESCRIPTION = "A user-space tool to show and modify the state of GPIOs on the S3c24xx platform" SECTION = "console/utils" +AUTHOR = "Werner Almesberger <werner@openmoko.org>" LICENSE = "GPL" -PV = "1.0+svn${SRCREV}" -PR = "r1" +PV = "1.0+svnr${SRCREV}" +PR = "r2" SRC_URI = "svn://svn.openmoko.org/trunk/src/target;module=gpio;proto=http" S = "${WORKDIR}/gpio" diff --git a/packages/s3c24xx-utils/sjf2410-linux-native_svn.bb b/packages/s3c24xx-utils/sjf2410-linux-native_svn.bb index bead6039f8..fcfbba923d 100644 --- a/packages/s3c24xx-utils/sjf2410-linux-native_svn.bb +++ b/packages/s3c24xx-utils/sjf2410-linux-native_svn.bb @@ -1,8 +1,8 @@ DESCRIPTION = "JTAG utility to interface w/ a S3C2410 device" SECTION = "devel" -AUTHOR = "Harald Welte" +AUTHOR = "Harald Welte <laforge@openmoko.org>" LICENSE = "GPL" -PV = "0.1+svn${SRCREV}" +PV = "0.1+svnr${SRCREV}" PR = "r0" SRC_URI = "svn://svn.openmoko.org/trunk/src/host/;module=sjf2410-linux;proto=https" @@ -17,8 +17,8 @@ do_compile() { } do_deploy() { - install -d ${DEPLOY_DIR_IMAGE} - install -m 0755 sjf2410 ${DEPLOY_DIR_IMAGE}/sjf2410 + install -d ${DEPLOY_DIR_TOOLS} + install -m 0755 sjf2410 ${DEPLOY_DIR_TOOLS}/sjf2410-${PV} } do_stage() { |