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Diffstat (limited to 'packages/uboot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Add-support-for-the-MPC832XEMDS-board.patch')
-rw-r--r--packages/uboot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Add-support-for-the-MPC832XEMDS-board.patch1809
1 files changed, 0 insertions, 1809 deletions
diff --git a/packages/uboot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Add-support-for-the-MPC832XEMDS-board.patch b/packages/uboot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Add-support-for-the-MPC832XEMDS-board.patch
deleted file mode 100644
index 5018cd3434..0000000000
--- a/packages/uboot/u-boot-1.1.6/u-boot-1.1.6-fsl-1-Add-support-for-the-MPC832XEMDS-board.patch
+++ /dev/null
@@ -1,1809 +0,0 @@
-fe298a1bbd7b9526ca1139da8977e1a076c4e176
-diff --git a/Makefile b/Makefile
-index d2534ab..d172411 100644
---- a/Makefile
-+++ b/Makefile
-@@ -1621,6 +1621,30 @@ MPC8360EMDS_SLAVE_config: unconfig
- MPC8349ITX_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349itx
-
-+MPC832XEMDS_config \
-+MPC832XEMDS_HOST_33_config \
-+MPC832XEMDS_HOST_66_config \
-+MPC832XEMDS_SLAVE_config: unconfig
-+ @echo "" >include/config.h ; \
-+ if [ "$(findstring _HOST_,$@)" ] ; then \
-+ echo -n "... PCI HOST " ; \
-+ echo "#define CONFIG_PCI" >>include/config.h ; \
-+ fi ; \
-+ if [ "$(findstring _SLAVE_,$@)" ] ; then \
-+ echo "...PCI SLAVE 66M" ; \
-+ echo "#define CONFIG_PCI" >>include/config.h ; \
-+ echo "#define CONFIG_PCISLAVE" >>include/config.h ; \
-+ fi ; \
-+ if [ "$(findstring _33_,$@)" ] ; then \
-+ echo -n "...33M ..." ; \
-+ echo "#define PCI_33M" >>include/config.h ; \
-+ fi ; \
-+ if [ "$(findstring _66_,$@)" ] ; then \
-+ echo -n "...66M..." ; \
-+ echo "#define PCI_66M" >>include/config.h ; \
-+ fi ;
-+ @$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds
-+
- #########################################################################
- ## MPC85xx Systems
- #########################################################################
-diff --git a/board/mpc832xemds/Makefile b/board/mpc832xemds/Makefile
-new file mode 100644
-index 0000000..5ec7a87
---- /dev/null
-+++ b/board/mpc832xemds/Makefile
-@@ -0,0 +1,50 @@
-+#
-+# (C) Copyright 2006
-+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-+#
-+# See file CREDITS for list of people who contributed to this
-+# project.
-+#
-+# This program is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU General Public License as
-+# published by the Free Software Foundation; either version 2 of
-+# the License, or (at your option) any later version.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with this program; if not, write to the Free Software
-+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+# MA 02111-1307 USA
-+#
-+
-+include $(TOPDIR)/config.mk
-+
-+LIB = $(obj)lib$(BOARD).a
-+
-+COBJS := $(BOARD).o pci.o
-+
-+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-+OBJS := $(addprefix $(obj),$(COBJS))
-+SOBJS := $(addprefix $(obj),$(SOBJS))
-+
-+$(LIB): $(obj).depend $(OBJS)
-+ $(AR) $(ARFLAGS) $@ $(OBJS)
-+
-+clean:
-+ rm -f $(SOBJS) $(OBJS)
-+
-+distclean: clean
-+ rm -f $(LIB) core *.bak .depend
-+
-+#########################################################################
-+
-+# defines $(obj).depend target
-+include $(SRCTREE)/rules.mk
-+
-+sinclude $(obj).depend
-+
-+#########################################################################
-diff --git a/board/mpc832xemds/config.mk b/board/mpc832xemds/config.mk
-new file mode 100644
-index 0000000..6c3eca7
---- /dev/null
-+++ b/board/mpc832xemds/config.mk
-@@ -0,0 +1,28 @@
-+#
-+# (C) Copyright 2006
-+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-+#
-+# See file CREDITS for list of people who contributed to this
-+# project.
-+#
-+# This program is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU General Public License as
-+# published by the Free Software Foundation; either version 2 of
-+# the License, or (at your option) any later version.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with this program; if not, write to the Free Software
-+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+# MA 02111-1307 USA
-+#
-+
-+#
-+# MPC832XEMDS
-+#
-+
-+TEXT_BASE = 0xFE000000
-diff --git a/board/mpc832xemds/mpc832xemds.c b/board/mpc832xemds/mpc832xemds.c
-new file mode 100644
-index 0000000..772da67
---- /dev/null
-+++ b/board/mpc832xemds/mpc832xemds.c
-@@ -0,0 +1,176 @@
-+/*
-+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
-+ *
-+ * Dave Liu <daveliu@freescale.com>
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ */
-+
-+#include <common.h>
-+#include <ioports.h>
-+#include <mpc83xx.h>
-+#include <i2c.h>
-+#include <spd.h>
-+#include <miiphy.h>
-+#include <command.h>
-+#if defined(CONFIG_PCI)
-+#include <pci.h>
-+#endif
-+#if defined(CONFIG_SPD_EEPROM)
-+#include <spd_sdram.h>
-+#else
-+#include <asm/mmu.h>
-+#endif
-+#if defined(CONFIG_OF_FLAT_TREE)
-+#include <ft_build.h>
-+#endif
-+
-+const qe_iop_conf_t qe_iop_conf_tab[] = {
-+ /* ETH3 */
-+ {1, 0, 1, 0, 1}, /* TxD0 */
-+ {1, 1, 1, 0, 1}, /* TxD1 */
-+ {1, 2, 1, 0, 1}, /* TxD2 */
-+ {1, 3, 1, 0, 1}, /* TxD3 */
-+ {1, 9, 1, 0, 1}, /* TxER */
-+ {1, 12, 1, 0, 1}, /* TxEN */
-+ {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
-+
-+ {1, 4, 2, 0, 1}, /* RxD0 */
-+ {1, 5, 2, 0, 1}, /* RxD1 */
-+ {1, 6, 2, 0, 1}, /* RxD2 */
-+ {1, 7, 2, 0, 1}, /* RxD3 */
-+ {1, 8, 2, 0, 1}, /* RxER */
-+ {1, 10, 2, 0, 1}, /* RxDV */
-+ {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
-+ {1, 11, 2, 0, 1}, /* COL */
-+ {1, 13, 2, 0, 1}, /* CRS */
-+
-+ /* ETH4 */
-+ {1, 18, 1, 0, 1}, /* TxD0 */
-+ {1, 19, 1, 0, 1}, /* TxD1 */
-+ {1, 20, 1, 0, 1}, /* TxD2 */
-+ {1, 21, 1, 0, 1}, /* TxD3 */
-+ {1, 27, 1, 0, 1}, /* TxER */
-+ {1, 30, 1, 0, 1}, /* TxEN */
-+ {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */
-+
-+ {1, 22, 2, 0, 1}, /* RxD0 */
-+ {1, 23, 2, 0, 1}, /* RxD1 */
-+ {1, 24, 2, 0, 1}, /* RxD2 */
-+ {1, 25, 2, 0, 1}, /* RxD3 */
-+ {1, 26, 1, 0, 1}, /* RxER */
-+ {1, 28, 2, 0, 1}, /* Rx_DV */
-+ {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
-+ {1, 29, 2, 0, 1}, /* COL */
-+ {1, 31, 2, 0, 1}, /* CRS */
-+
-+ {3, 4, 3, 0, 2}, /* MDIO */
-+ {3, 5, 1, 0, 2}, /* MDC */
-+
-+ {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
-+};
-+
-+int board_early_init_f(void)
-+{
-+ volatile u8 *bcsr = (volatile u8 *)CFG_BCSR;
-+
-+ /* Enable flash write */
-+ bcsr[9] &= ~0x08;
-+
-+ return 0;
-+}
-+
-+int fixed_sdram(void);
-+
-+long int initdram(int board_type)
-+{
-+ volatile immap_t *im = (immap_t *) CFG_IMMR;
-+ u32 msize = 0;
-+
-+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-+ return -1;
-+
-+ /* DDR SDRAM - Main SODIMM */
-+ im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
-+
-+ msize = fixed_sdram();
-+
-+ puts("\n DDR RAM: ");
-+
-+ /* return total bus SDRAM size(bytes) -- DDR */
-+ return (msize * 1024 * 1024);
-+}
-+
-+/*************************************************************************
-+ * fixed sdram init -- doesn't use serial presence detect.
-+ ************************************************************************/
-+int fixed_sdram(void)
-+{
-+ volatile immap_t *im = (immap_t *) CFG_IMMR;
-+ u32 msize = 0;
-+ u32 ddr_size;
-+ u32 ddr_size_log2;
-+
-+ msize = CFG_DDR_SIZE;
-+ for (ddr_size = msize << 20, ddr_size_log2 = 0;
-+ (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
-+ if (ddr_size & 1) {
-+ return -1;
-+ }
-+ }
-+ im->sysconf.ddrlaw[0].ar =
-+ LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-+#if (CFG_DDR_SIZE != 128)
-+#warning Currenly any ddr size other than 128 is not supported
-+#endif
-+ im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
-+ im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
-+ im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
-+ im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
-+ im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
-+ im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
-+ im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
-+ im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
-+ im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
-+ im->ddr.sdram_mode = CFG_DDR_MODE;
-+ im->ddr.sdram_mode2 = CFG_DDR_MODE2;
-+ im->ddr.sdram_interval = CFG_DDR_INTERVAL;
-+ __asm__ __volatile__ ("sync");
-+ udelay(200);
-+
-+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-+ __asm__ __volatile__ ("sync");
-+ return msize;
-+}
-+
-+int checkboard(void)
-+{
-+ puts("Board: Freescale MPC832XEMDS\n");
-+ return 0;
-+}
-+
-+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-+void
-+ft_board_setup(void *blob, bd_t *bd)
-+{
-+ u32 *p;
-+ int len;
-+
-+#ifdef CONFIG_PCI
-+ ft_pci_setup(blob, bd);
-+#endif
-+ ft_cpu_setup(blob, bd);
-+
-+ p = ft_get_prop(blob, "/memory/reg", &len);
-+ if (p != NULL) {
-+ *p++ = cpu_to_be32(bd->bi_memstart);
-+ *p = cpu_to_be32(bd->bi_memsize);
-+ }
-+}
-+#endif
-diff --git a/board/mpc832xemds/pci.c b/board/mpc832xemds/pci.c
-new file mode 100644
-index 0000000..09f3ac3
---- /dev/null
-+++ b/board/mpc832xemds/pci.c
-@@ -0,0 +1,313 @@
-+/*
-+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ */
-+
-+/*
-+ * PCI Configuration space access support for MPC83xx PCI Bridge
-+ */
-+#include <asm/mmu.h>
-+#include <asm/io.h>
-+#include <common.h>
-+#include <pci.h>
-+#include <i2c.h>
-+
-+#include <asm/fsl_i2c.h>
-+
-+DECLARE_GLOBAL_DATA_PTR;
-+
-+#if defined(CONFIG_PCI)
-+#define PCI_FUNCTION_CONFIG 0x44
-+#define PCI_FUNCTION_CFG_LOCK 0x20
-+
-+/*
-+ * Initialize PCI Devices, report devices found
-+ */
-+#ifndef CONFIG_PCI_PNP
-+static struct pci_config_table pci_mpc83xxemds_config_table[] = {
-+ {
-+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-+ pci_cfgfunc_config_device,
-+ {PCI_ENET0_IOADDR,
-+ PCI_ENET0_MEMADDR,
-+ PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
-+ },
-+ {}
-+}
-+#endif
-+static struct pci_controller hose[] = {
-+ {
-+#ifndef CONFIG_PCI_PNP
-+ config_table:pci_mpc83xxemds_config_table,
-+#endif
-+ },
-+};
-+
-+/**********************************************************************
-+ * pci_init_board()
-+ *********************************************************************/
-+void pci_init_board(void)
-+#ifdef CONFIG_PCISLAVE
-+{
-+ u16 reg16;
-+ volatile immap_t *immr;
-+ volatile law83xx_t *pci_law;
-+ volatile pot83xx_t *pci_pot;
-+ volatile pcictrl83xx_t *pci_ctrl;
-+ volatile pciconf83xx_t *pci_conf;
-+
-+ immr = (immap_t *) CFG_IMMR;
-+ pci_law = immr->sysconf.pcilaw;
-+ pci_pot = immr->ios.pot;
-+ pci_ctrl = immr->pci_ctrl;
-+ pci_conf = immr->pci_conf;
-+ /*
-+ * Configure PCI Inbound Translation Windows
-+ */
-+ pci_ctrl[0].pitar0 = 0x0;
-+ pci_ctrl[0].pibar0 = 0x0;
-+ pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
-+ PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
-+
-+ pci_ctrl[0].pitar1 = 0x0;
-+ pci_ctrl[0].pibar1 = 0x0;
-+ pci_ctrl[0].piebar1 = 0x0;
-+ pci_ctrl[0].piwar1 &= ~PIWAR_EN;
-+
-+ pci_ctrl[0].pitar2 = 0x0;
-+ pci_ctrl[0].pibar2 = 0x0;
-+ pci_ctrl[0].piebar2 = 0x0;
-+ pci_ctrl[0].piwar2 &= ~PIWAR_EN;
-+
-+ hose[0].first_busno = 0;
-+ hose[0].last_busno = 0xff;
-+ pci_setup_indirect(&hose[0],
-+ (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
-+ reg16 = 0xff;
-+
-+ pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
-+ PCI_COMMAND, &reg16);
-+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY;
-+ pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
-+ PCI_COMMAND, reg16);
-+
-+ /*
-+ * Clear non-reserved bits in status register.
-+ */
-+ pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
-+ PCI_STATUS, 0xffff);
-+ pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0),
-+ PCI_LATENCY_TIMER, 0x80);
-+
-+ /*
-+ * Unlock configuration lock in PCI function configuration register.
-+ */
-+ pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
-+ PCI_FUNCTION_CONFIG, &reg16);
-+ reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
-+ pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
-+ PCI_FUNCTION_CONFIG, reg16);
-+
-+ printf("Enabled PCI 32bit Agent Mode\n");
-+}
-+#else
-+{
-+ volatile immap_t *immr;
-+ volatile clk83xx_t *clk;
-+ volatile law83xx_t *pci_law;
-+ volatile pot83xx_t *pci_pot;
-+ volatile pcictrl83xx_t *pci_ctrl;
-+ volatile pciconf83xx_t *pci_conf;
-+
-+ u8 val8, orig_i2c_bus;
-+ u16 reg16;
-+ u32 val32;
-+ u32 dev;
-+
-+ immr = (immap_t *) CFG_IMMR;
-+ clk = (clk83xx_t *) & immr->clk;
-+ pci_law = immr->sysconf.pcilaw;
-+ pci_pot = immr->ios.pot;
-+ pci_ctrl = immr->pci_ctrl;
-+ pci_conf = immr->pci_conf;
-+ /*
-+ * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
-+ */
-+ val32 = clk->occr;
-+ udelay(2000);
-+#if defined(PCI_66M)
-+ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
-+ printf("PCI clock is 66MHz\n");
-+#elif defined(PCI_33M)
-+ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
-+ OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
-+ printf("PCI clock is 33MHz\n");
-+#else
-+ clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
-+ printf("PCI clock is 66MHz\n");
-+#endif
-+ udelay(2000);
-+
-+ /*
-+ * Configure PCI Local Access Windows
-+ */
-+ pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
-+ pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
-+
-+ pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
-+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
-+
-+ /*
-+ * Configure PCI Outbound Translation Windows
-+ */
-+
-+ /* PCI mem space - prefetch */
-+ pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
-+ pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
-+ pci_pot[0].pocmr =
-+ POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK);
-+
-+ /* PCI mmio - non-prefetch mem space */
-+ pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
-+ pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
-+ pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
-+
-+ /* PCI IO space */
-+ pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
-+ pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
-+ pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
-+
-+ /*
-+ * Configure PCI Inbound Translation Windows
-+ */
-+ pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
-+ pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
-+ pci_ctrl[0].piebar1 = 0x0;
-+ pci_ctrl[0].piwar1 =
-+ PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
-+ PIWAR_IWS_2G;
-+
-+ /*
-+ * Assign PIB PMC slot to desired PCI bus
-+ */
-+
-+ /* Switch temporarily to I2C bus #2 */
-+ orig_i2c_bus = i2c_get_bus_num();
-+ i2c_set_bus_num(1);
-+
-+ val8 = 0;
-+ i2c_write(0x23, 0x6, 1, &val8, 1);
-+ i2c_write(0x23, 0x7, 1, &val8, 1);
-+ val8 = 0xff;
-+ i2c_write(0x23, 0x2, 1, &val8, 1);
-+ i2c_write(0x23, 0x3, 1, &val8, 1);
-+
-+ val8 = 0;
-+ i2c_write(0x26, 0x6, 1, &val8, 1);
-+ val8 = 0x34;
-+ i2c_write(0x26, 0x7, 1, &val8, 1);
-+
-+ val8 = 0xf9; /* PMC2, PMC3 slot to PCI bus */
-+ i2c_write(0x26, 0x2, 1, &val8, 1);
-+ val8 = 0xff;
-+ i2c_write(0x26, 0x3, 1, &val8, 1);
-+
-+ val8 = 0;
-+ i2c_write(0x27, 0x6, 1, &val8, 1);
-+ i2c_write(0x27, 0x7, 1, &val8, 1);
-+ val8 = 0xff;
-+ i2c_write(0x27, 0x2, 1, &val8, 1);
-+ val8 = 0xef;
-+ i2c_write(0x27, 0x3, 1, &val8, 1);
-+ asm("eieio");
-+
-+ /* Reset to original I2C bus */
-+ i2c_set_bus_num(orig_i2c_bus);
-+
-+ /*
-+ * Release PCI RST Output signal
-+ */
-+ udelay(2000);
-+ pci_ctrl[0].gcr = 1;
-+ udelay(2000);
-+
-+ hose[0].first_busno = 0;
-+ hose[0].last_busno = 0xff;
-+
-+ /* PCI memory prefetch space */
-+ pci_set_region(hose[0].regions + 0,
-+ CFG_PCI_MEM_BASE,
-+ CFG_PCI_MEM_PHYS,
-+ CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
-+
-+ /* PCI memory space */
-+ pci_set_region(hose[0].regions + 1,
-+ CFG_PCI_MMIO_BASE,
-+ CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM);
-+
-+ /* PCI IO space */
-+ pci_set_region(hose[0].regions + 2,
-+ CFG_PCI_IO_BASE,
-+ CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO);
-+
-+ /* System memory space */
-+ pci_set_region(hose[0].regions + 3,
-+ CFG_PCI_SLV_MEM_LOCAL,
-+ CFG_PCI_SLV_MEM_BUS,
-+ CFG_PCI_SLV_MEM_SIZE,
-+ PCI_REGION_MEM | PCI_REGION_MEMORY);
-+
-+ hose[0].region_count = 4;
-+
-+ pci_setup_indirect(&hose[0],
-+ (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
-+
-+ pci_register_hose(hose);
-+
-+ /*
-+ * Write command register
-+ */
-+ reg16 = 0xff;
-+ dev = PCI_BDF(0, 0, 0);
-+ pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, &reg16);
-+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-+ pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16);
-+
-+ /*
-+ * Clear non-reserved bits in status register.
-+ */
-+ pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff);
-+ pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
-+ pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
-+
-+ printf("PCI 32bit bus on PMC2 & PMC3\n");
-+
-+ /*
-+ * Hose scan.
-+ */
-+ hose->last_busno = pci_hose_scan(hose);
-+}
-+#endif /* CONFIG_PCISLAVE */
-+
-+#ifdef CONFIG_OF_FLAT_TREE
-+void
-+ft_pci_setup(void *blob, bd_t *bd)
-+{
-+ u32 *p;
-+ int len;
-+
-+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
-+ if (p != NULL) {
-+ p[0] = hose[0].first_busno;
-+ p[1] = hose[0].last_busno;
-+ }
-+}
-+#endif /* CONFIG_OF_FLAT_TREE */
-+#endif /* CONFIG_PCI */
-diff --git a/board/mpc832xemds/u-boot.lds b/board/mpc832xemds/u-boot.lds
-new file mode 100644
-index 0000000..937c87a
---- /dev/null
-+++ b/board/mpc832xemds/u-boot.lds
-@@ -0,0 +1,123 @@
-+/*
-+ * (C) Copyright 2006
-+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+OUTPUT_ARCH(powerpc)
-+SECTIONS
-+{
-+ /* Read-only sections, merged into text segment: */
-+ . = + SIZEOF_HEADERS;
-+ .interp : { *(.interp) }
-+ .hash : { *(.hash) }
-+ .dynsym : { *(.dynsym) }
-+ .dynstr : { *(.dynstr) }
-+ .rel.text : { *(.rel.text) }
-+ .rela.text : { *(.rela.text) }
-+ .rel.data : { *(.rel.data) }
-+ .rela.data : { *(.rela.data) }
-+ .rel.rodata : { *(.rel.rodata) }
-+ .rela.rodata : { *(.rela.rodata) }
-+ .rel.got : { *(.rel.got) }
-+ .rela.got : { *(.rela.got) }
-+ .rel.ctors : { *(.rel.ctors) }
-+ .rela.ctors : { *(.rela.ctors) }
-+ .rel.dtors : { *(.rel.dtors) }
-+ .rela.dtors : { *(.rela.dtors) }
-+ .rel.bss : { *(.rel.bss) }
-+ .rela.bss : { *(.rela.bss) }
-+ .rel.plt : { *(.rel.plt) }
-+ .rela.plt : { *(.rela.plt) }
-+ .init : { *(.init) }
-+ .plt : { *(.plt) }
-+ .text :
-+ {
-+ cpu/mpc83xx/start.o (.text)
-+ *(.text)
-+ *(.fixup)
-+ *(.got1)
-+ . = ALIGN(16);
-+ *(.rodata)
-+ *(.rodata1)
-+ *(.rodata.str1.4)
-+ *(.eh_frame)
-+ }
-+ .fini : { *(.fini) } =0
-+ .ctors : { *(.ctors) }
-+ .dtors : { *(.dtors) }
-+
-+ /* Read-write section, merged into data segment: */
-+ . = (. + 0x0FFF) & 0xFFFFF000;
-+ _erotext = .;
-+ PROVIDE (erotext = .);
-+ .reloc :
-+ {
-+ *(.got)
-+ _GOT2_TABLE_ = .;
-+ *(.got2)
-+ _FIXUP_TABLE_ = .;
-+ *(.fixup)
-+ }
-+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
-+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-+
-+ .data :
-+ {
-+ *(.data)
-+ *(.data1)
-+ *(.sdata)
-+ *(.sdata2)
-+ *(.dynamic)
-+ CONSTRUCTORS
-+ }
-+ _edata = .;
-+ PROVIDE (edata = .);
-+
-+ . = .;
-+ __u_boot_cmd_start = .;
-+ .u_boot_cmd : { *(.u_boot_cmd) }
-+ __u_boot_cmd_end = .;
-+
-+
-+ . = .;
-+ __start___ex_table = .;
-+ __ex_table : { *(__ex_table) }
-+ __stop___ex_table = .;
-+
-+ . = ALIGN(4096);
-+ __init_begin = .;
-+ .text.init : { *(.text.init) }
-+ .data.init : { *(.data.init) }
-+ . = ALIGN(4096);
-+ __init_end = .;
-+
-+ __bss_start = .;
-+ .bss :
-+ {
-+ *(.sbss) *(.scommon)
-+ *(.dynbss)
-+ *(.bss)
-+ *(COMMON)
-+ }
-+ _end = . ;
-+ PROVIDE (end = .);
-+}
-+ENTRY(_start)
-diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
-index 1b51078..bc61219 100644
---- a/cpu/mpc83xx/cpu.c
-+++ b/cpu/mpc83xx/cpu.c
-@@ -92,6 +92,22 @@ int checkcpu(void)
- case SPR_8360_REV12:
- puts("MPC8360, ");
- break;
-+ case SPR_8323E_REV10:
-+ case SPR_8323E_REV11:
-+ puts("MPC8323E, ");
-+ break;
-+ case SPR_8323_REV10:
-+ case SPR_8323_REV11:
-+ puts("MPC8323, ");
-+ break;
-+ case SPR_8321E_REV10:
-+ case SPR_8321E_REV11:
-+ puts("MPC8321E, ");
-+ break;
-+ case SPR_8321_REV10:
-+ case SPR_8321_REV11:
-+ puts("MPC8321, ");
-+ break;
- default:
- puts("Rev: Unknown\n");
- return -1; /* Not sure what this is */
-diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
-index 7574fab..eb256e5 100644
---- a/cpu/mpc83xx/cpu_init.c
-+++ b/cpu/mpc83xx/cpu_init.c
-@@ -119,6 +119,11 @@ void cpu_init_f (volatile immap_t * im)
- #ifdef CFG_SICRL
- im->sysconf.sicrl = CFG_SICRL;
- #endif
-+ /* DDR control driver register */
-+#ifdef CFG_DDRCDR
-+ im->sysconf.ddrcdr = CFG_DDRCDR;
-+#endif
-+
- #ifdef CONFIG_QE
- /* Config QE ioports */
- config_qe_ioports();
-diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
-index 40ba6b0..9fd1bf1 100644
---- a/cpu/mpc83xx/speed.c
-+++ b/cpu/mpc83xx/speed.c
-@@ -107,15 +107,19 @@ int get_clocks(void)
- #endif
- u32 core_clk;
- u32 i2c1_clk;
-+#if !defined(CONFIG_MPC832X)
- u32 i2c2_clk;
-+#endif
- u32 enc_clk;
- u32 lbiu_clk;
- u32 lclk_clk;
- u32 ddr_clk;
--#if defined (CONFIG_MPC8360)
-+#if defined(CONFIG_MPC8360)
-+ u32 ddr_sec_clk;
-+#endif
-+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
- u32 qepmf;
- u32 qepdf;
-- u32 ddr_sec_clk;
- u32 qe_clk;
- u32 brg_clk;
- #endif
-@@ -227,10 +231,12 @@ int get_clocks(void)
- return -9;
- }
- #endif
--#if defined (CONFIG_MPC8360)
-+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
- i2c1_clk = csb_clk;
- #endif
-+#if !defined(CONFIG_MPC832X)
- i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
-+#endif
-
- switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
- case 0:
-@@ -249,12 +255,9 @@ int get_clocks(void)
- /* unkown SCCR_ENCCM value */
- return -6;
- }
--#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
-+
- lbiu_clk = csb_clk *
- (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
--#else
--#error Unknown MPC83xx chip
--#endif
- lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
- switch (lcrr) {
- case 2:
-@@ -266,17 +269,14 @@ int get_clocks(void)
- /* unknown lcrr */
- return -10;
- }
--#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
-+
- ddr_clk = csb_clk *
- (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
- corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
--#if defined (CONFIG_MPC8360)
-+#if defined(CONFIG_MPC8360)
- ddr_sec_clk = csb_clk * (1 +
- ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
- #endif
--#else
--#error Unknown MPC83xx chip
--#endif
-
- corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
- if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
-@@ -306,7 +306,7 @@ int get_clocks(void)
- return -12;
- }
-
--#if defined (CONFIG_MPC8360)
-+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
- qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT;
- qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT;
- qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
-@@ -322,13 +322,17 @@ int get_clocks(void)
- #endif
- gd->core_clk = core_clk;
- gd->i2c1_clk = i2c1_clk;
-+#if !defined(CONFIG_MPC832X)
- gd->i2c2_clk = i2c2_clk;
-+#endif
- gd->enc_clk = enc_clk;
- gd->lbiu_clk = lbiu_clk;
- gd->lclk_clk = lclk_clk;
- gd->ddr_clk = ddr_clk;
--#if defined (CONFIG_MPC8360)
-+#if defined(CONFIG_MPC8360)
- gd->ddr_sec_clk = ddr_sec_clk;
-+#endif
-+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
- gd->qe_clk = qe_clk;
- gd->brg_clk = brg_clk;
- #endif
-@@ -352,18 +356,21 @@ int print_clock_conf(void)
- printf("Clock configuration:\n");
- printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
- printf(" Core: %4d MHz\n", gd->core_clk / 1000000);
--#if defined (CONFIG_MPC8360)
-+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
- printf(" QE: %4d MHz\n", gd->qe_clk / 1000000);
-+ printf(" BRG: %4d MHz\n", gd->brg_clk / 1000000);
- #endif
- printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000);
- printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000);
- printf(" DDR: %4d MHz\n", gd->ddr_clk / 1000000);
--#if defined (CONFIG_MPC8360)
-+#if defined(CONFIG_MPC8360)
- printf(" DDR Secondary: %4d MHz\n", gd->ddr_sec_clk / 1000000);
- #endif
- printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000);
- printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000);
-+#if !defined(CONFIG_MPC832X)
- printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000);
-+#endif
- #if defined(CONFIG_MPC8349)
- printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000);
- printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000);
-diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
-index f7f8ed0..0bcd0a9 100644
---- a/drivers/qe/qe.h
-+++ b/drivers/qe/qe.h
-@@ -30,7 +30,7 @@
- #define UCC_MAX_NUM 8
-
- #define QE_DATAONLY_BASE (uint)(128)
--#define QE_DATAONLY_SIZE ((uint)(0xc000) - QE_DATAONLY_BASE)
-+#define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE)
-
- /* QE threads SNUM
- */
-diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
-index c44a5be..aea455b 100644
---- a/drivers/qe/uec.c
-+++ b/drivers/qe/uec.c
-@@ -432,7 +432,12 @@ static int init_phy(struct eth_device *dev)
- }
- memset(mii_info, 0, sizeof(*mii_info));
-
-- mii_info->speed = SPEED_1000;
-+ if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
-+ mii_info->speed = SPEED_1000;
-+ } else {
-+ mii_info->speed = SPEED_100;
-+ }
-+
- mii_info->duplex = DUPLEX_FULL;
- mii_info->pause = 0;
- mii_info->link = 1;
-@@ -508,7 +513,8 @@ static void adjust_link(struct eth_device *dev)
- }
-
- if (mii_info->speed != uec->oldspeed) {
-- switch (mii_info->speed) {
-+ if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
-+ switch (mii_info->speed) {
- case 1000:
- break;
- case 100:
-@@ -531,6 +537,7 @@ static void adjust_link(struct eth_device *dev)
- printf("%s: Ack,Speed(%d)is illegal\n",
- dev->name, mii_info->speed);
- break;
-+ }
- }
-
- printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
-diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h
-index 79dcae4..ff9512f 100644
---- a/include/asm-ppc/e300.h
-+++ b/include/asm-ppc/e300.h
-@@ -15,6 +15,11 @@
- #define PVR_8360_REV10 (PVR_83xx | 0x0020)
- #define PVR_8360_REV11 (PVR_83xx | 0x0020)
-
-+#if defined(CONFIG_MPC832X)
-+#undef PVR_83xx
-+#define PVR_83xx 0x80840000
-+#endif
-+
- /*
- * Hardware Implementation-Dependent Register 0 (HID0)
- */
-diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
-index 67b035c..77a079f 100644
---- a/include/asm-ppc/immap_83xx.h
-+++ b/include/asm-ppc/immap_83xx.h
-@@ -60,7 +60,10 @@ typedef struct sysconf83xx {
- u32 spcr; /* System Priority Configuration Register */
- u32 sicrl; /* System I/O Configuration Register Low */
- u32 sicrh; /* System I/O Configuration Register High */
-- u8 res6[0xE4];
-+ u8 res6[0x0C];
-+ u32 ddrcdr; /* DDR Control Driver Register */
-+ u32 ddrdsr; /* DDR Debug Status Register */
-+ u8 res7[0xD0];
- } sysconf83xx_t;
-
- /*
-@@ -274,25 +277,35 @@ typedef struct ddr83xx {
- ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
- u8 res0[0x60];
- u32 cs_config[4]; /* Chip Select x Configuration */
-- u8 res1[0x78];
-+ u8 res1[0x70];
-+ u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
-+ u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
- u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
- u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
- u32 sdram_cfg; /* SDRAM Control Configuration */
-- u8 res2[4];
-+ u32 sdram_cfg2; /* SDRAM Control Configuration 2 */
- u32 sdram_mode; /* SDRAM Mode Configuration */
-- u8 res3[8];
-+ u32 sdram_mode2; /* SDRAM Mode Configuration 2 */
-+ u32 sdram_md_cntl; /* SDRAM Mode Control */
- u32 sdram_interval; /* SDRAM Interval Configuration */
-- u8 res9[8];
-- u32 sdram_clk_cntl;
-- u8 res4[0xCCC];
-+ u32 ddr_data_init; /* SDRAM Data Initialization */
-+ u8 res2[4];
-+ u32 sdram_clk_cntl; /* SDRAM Clock Control */
-+ u8 res3[0x14];
-+ u32 ddr_init_addr; /* DDR training initialization address */
-+ u32 ddr_init_ext_addr; /* DDR training initialization extended address */
-+ u8 res4[0xAA8];
-+ u32 ddr_ip_rev1; /* DDR IP block revision 1 */
-+ u32 ddr_ip_rev2; /* DDR IP block revision 2 */
-+ u8 res5[0x200];
- u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */
- u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */
- u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */
-- u8 res5[0x14];
-+ u8 res6[0x14];
- u32 capture_data_hi; /* Memory Data Path Read Capture High */
- u32 capture_data_lo; /* Memory Data Path Read Capture Low */
- u32 capture_ecc; /* Memory Data Path Read Capture ECC */
-- u8 res6[0x14];
-+ u8 res7[0x14];
- u32 err_detect; /* Memory Error Detect */
- u32 err_disable; /* Memory Error Disable */
- u32 err_int_en; /* Memory Error Interrupt Enable */
-@@ -300,9 +313,9 @@ typedef struct ddr83xx {
- u32 capture_address; /* Memory Error Address Capture */
- u32 capture_ext_address;/* Memory Error Extended Address Capture */
- u32 err_sbe; /* Memory Single-Bit ECC Error Management */
-- u8 res7[0xA4];
-+ u8 res8[0xA4];
- u32 debug_reg;
-- u8 res8[0xFC];
-+ u8 res9[0xFC];
- } ddr83xx_t;
-
- /*
-@@ -607,6 +620,43 @@ typedef struct immap {
- u8 res10[0xC0000];
- u8 qe[0x100000]; /* QE block */
- } immap_t;
-+
-+#elif defined(CONFIG_MPC832X)
-+typedef struct immap {
-+ sysconf83xx_t sysconf; /* System configuration */
-+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
-+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
-+ rtclk83xx_t pit; /* Periodic Interval Timer */
-+ gtm83xx_t gtm[2]; /* Global Timers Module */
-+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
-+ arbiter83xx_t arbiter; /* System Arbiter Registers */
-+ reset83xx_t reset; /* Reset Module */
-+ clk83xx_t clk; /* System Clock Module */
-+ pmc83xx_t pmc; /* Power Management Control Module */
-+ qepi83xx_t qepi; /* QE Ports Interrupts Registers */
-+ u8 res0[0x300];
-+ u8 dll_ddr[0x100];
-+ u8 dll_lbc[0x100];
-+ u8 res1[0x200];
-+ qepio83xx_t qepio; /* QE Parallel I/O ports */
-+ u8 res2[0x800];
-+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
-+ fsl_i2c_t i2c[2]; /* I2C Controllers */
-+ u8 res3[0x1300];
-+ duart83xx_t duart[2]; /* DUART */
-+ u8 res4[0x900];
-+ lbus83xx_t lbus; /* Local Bus Controller Registers */
-+ u8 res5[0x2000];
-+ dma83xx_t dma; /* DMA */
-+ pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
-+ u8 res6[128];
-+ ios83xx_t ios; /* Sequencer (IOS) */
-+ pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
-+ u8 res7[0x27A00];
-+ security83xx_t security;
-+ u8 res8[0xC0000];
-+ u8 qe[0x100000]; /* QE block */
-+} immap_t;
- #endif
-
- #endif /* __IMMAP_83xx__ */
-diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h
-index f385032..950b949 100644
---- a/include/asm-ppc/immap_qe.h
-+++ b/include/asm-ppc/immap_qe.h
-@@ -547,4 +547,10 @@ typedef struct qe_immap {
-
- extern qe_map_t *qe_immr;
-
-+#if defined(CONFIG_MPC8360)
-+#define QE_MURAM_SIZE 0xc000UL
-+#elif defined(CONFIG_MPC832X)
-+#define QE_MURAM_SIZE 0x4000UL
-+#endif
-+
- #endif /* __IMMAP_QE_H__ */
-diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
-new file mode 100644
-index 0000000..b8bf00f
---- /dev/null
-+++ b/include/configs/MPC832XEMDS.h
-@@ -0,0 +1,629 @@
-+/*
-+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#ifndef __CONFIG_H
-+#define __CONFIG_H
-+
-+#undef DEBUG
-+
-+/*
-+ * High Level Configuration Options
-+ */
-+#define CONFIG_E300 1 /* E300 family */
-+#define CONFIG_QE 1 /* Has QE */
-+#define CONFIG_MPC83XX 1 /* MPC83xx family */
-+#define CONFIG_MPC832X 1 /* MPC832x CPU specific */
-+#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
-+
-+/*
-+ * System Clock Setup
-+ */
-+#ifdef CONFIG_PCISLAVE
-+#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
-+#else
-+#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
-+#endif
-+
-+#ifndef CONFIG_SYS_CLK_FREQ
-+#define CONFIG_SYS_CLK_FREQ 66000000
-+#endif
-+
-+/*
-+ * Hardware Reset Configuration Word
-+ */
-+#define CFG_HRCW_LOW (\
-+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
-+ HRCWL_DDR_TO_SCB_CLK_2X1 |\
-+ HRCWL_VCO_1X2 |\
-+ HRCWL_CSB_TO_CLKIN_2X1 |\
-+ HRCWL_CORE_TO_CSB_2X1 |\
-+ HRCWL_CE_PLL_VCO_DIV_2 |\
-+ HRCWL_CE_PLL_DIV_1X1 |\
-+ HRCWL_CE_TO_PLL_1X3)
-+
-+#ifdef CONFIG_PCISLAVE
-+#define CFG_HRCW_HIGH (\
-+ HRCWH_PCI_AGENT |\
-+ HRCWH_PCI1_ARBITER_DISABLE |\
-+ HRCWH_CORE_ENABLE |\
-+ HRCWH_FROM_0XFFF00100 |\
-+ HRCWH_BOOTSEQ_DISABLE |\
-+ HRCWH_SW_WATCHDOG_DISABLE |\
-+ HRCWH_ROM_LOC_LOCAL_16BIT |\
-+ HRCWH_BIG_ENDIAN |\
-+ HRCWH_LALE_NORMAL)
-+#else
-+#define CFG_HRCW_HIGH (\
-+ HRCWH_PCI_HOST |\
-+ HRCWH_PCI1_ARBITER_ENABLE |\
-+ HRCWH_CORE_ENABLE |\
-+ HRCWH_FROM_0X00000100 |\
-+ HRCWH_BOOTSEQ_DISABLE |\
-+ HRCWH_SW_WATCHDOG_DISABLE |\
-+ HRCWH_ROM_LOC_LOCAL_16BIT |\
-+ HRCWH_BIG_ENDIAN |\
-+ HRCWH_LALE_NORMAL)
-+#endif
-+
-+/*
-+ * System IO Config
-+ */
-+#define CFG_SICRL 0x00000000
-+
-+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
-+
-+/*
-+ * IMMR new address
-+ */
-+#define CFG_IMMR 0xE0000000
-+
-+/*
-+ * DDR Setup
-+ */
-+#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
-+#define CFG_SDRAM_BASE CFG_DDR_BASE
-+#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
-+#define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
-+
-+#undef CONFIG_SPD_EEPROM
-+#if defined(CONFIG_SPD_EEPROM)
-+/* Determine DDR configuration from I2C interface
-+ */
-+#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
-+#else
-+/* Manually set up DDR parameters
-+ */
-+#define CFG_DDR_SIZE 128 /* MB */
-+#define CFG_DDR_CS0_CONFIG 0x80840102
-+#define CFG_DDR_TIMING_0 0x00220802
-+#define CFG_DDR_TIMING_1 0x3935d322
-+#define CFG_DDR_TIMING_2 0x0f9048ca
-+#define CFG_DDR_TIMING_3 0x00000000
-+#define CFG_DDR_CLK_CNTL 0x02000000
-+#define CFG_DDR_MODE 0x44400232
-+#define CFG_DDR_MODE2 0x8000c000
-+#define CFG_DDR_INTERVAL 0x03200064
-+#define CFG_DDR_CS0_BNDS 0x00000007
-+#define CFG_DDR_SDRAM_CFG 0x43080000
-+#define CFG_DDR_SDRAM_CFG2 0x00401000
-+#endif
-+
-+/*
-+ * Memory test
-+ */
-+#undef CFG_DRAM_TEST /* memory test, takes time */
-+#define CFG_MEMTEST_START 0x00000000 /* memtest region */
-+#define CFG_MEMTEST_END 0x00100000
-+
-+/*
-+ * The reserved memory
-+ */
-+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-+
-+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-+#define CFG_RAMBOOT
-+#else
-+#undef CFG_RAMBOOT
-+#endif
-+
-+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
-+
-+/*
-+ * Initial RAM Base Address Setup
-+ */
-+#define CFG_INIT_RAM_LOCK 1
-+#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
-+#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
-+#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
-+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-+
-+/*
-+ * Local Bus Configuration & Clock Setup
-+ */
-+#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2)
-+#define CFG_LBC_LBCR 0x00000000
-+
-+/*
-+ * FLASH on the Local Bus
-+ */
-+#define CFG_FLASH_CFI /* use the Common Flash Interface */
-+#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
-+#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
-+#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */
-+
-+#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
-+#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
-+
-+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
-+ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
-+ BR_V) /* valid */
-+#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
-+
-+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
-+#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
-+
-+#undef CFG_FLASH_CHECKSUM
-+
-+/*
-+ * BCSR on the Local Bus
-+ */
-+#define CFG_BCSR 0xF8000000
-+#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
-+#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
-+
-+#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
-+#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
-+
-+/*
-+ * SDRAM on the Local Bus
-+ */
-+#undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */
-+
-+#ifdef CFG_LB_SDRAM
-+#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
-+#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-+
-+#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE
-+#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
-+
-+/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
-+/*
-+ * Base Register 2 and Option Register 2 configure SDRAM.
-+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
-+ *
-+ * For BR2, need:
-+ * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
-+ * port size = 32-bits = BR2[19:20] = 11
-+ * no parity checking = BR2[21:22] = 00
-+ * SDRAM for MSEL = BR2[24:26] = 011
-+ * Valid = BR[31] = 1
-+ *
-+ * 0 4 8 12 16 20 24 28
-+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
-+ *
-+ * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
-+ * the top 17 bits of BR2.
-+ */
-+
-+#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */
-+
-+/*
-+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
-+ *
-+ * For OR2, need:
-+ * 64MB mask for AM, OR2[0:7] = 1111 1100
-+ * XAM, OR2[17:18] = 11
-+ * 9 columns OR2[19-21] = 010
-+ * 13 rows OR2[23-25] = 100
-+ * EAD set for extra time OR[31] = 1
-+ *
-+ * 0 4 8 12 16 20 24 28
-+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
-+ */
-+
-+#define CFG_OR2_PRELIM 0xfc006901
-+
-+#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
-+#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
-+
-+/*
-+ * LSDMR masks
-+ */
-+#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
-+#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
-+#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
-+#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
-+#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
-+#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
-+#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
-+#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
-+
-+#define CFG_LBC_LSDMR_COMMON 0x0063b723
-+
-+/*
-+ * SDRAM Controller configuration sequence.
-+ */
-+#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
-+ | CFG_LBC_LSDMR_OP_PCHALL)
-+#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
-+ | CFG_LBC_LSDMR_OP_ARFRSH)
-+#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
-+ | CFG_LBC_LSDMR_OP_ARFRSH)
-+#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
-+ | CFG_LBC_LSDMR_OP_MRW)
-+#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
-+ | CFG_LBC_LSDMR_OP_NORMAL)
-+
-+#endif
-+
-+/*
-+ * Windows to access PIB via local bus
-+ */
-+#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
-+#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
-+
-+/*
-+ * CS2 on Local Bus, to PIB
-+ */
-+#define CFG_BR2_PRELIM 0xf8008801 /* CS2 base address at 0xf8008000 */
-+#define CFG_OR2_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
-+
-+/*
-+ * CS3 on Local Bus, to PIB
-+ */
-+#define CFG_BR3_PRELIM 0xf8010801 /* CS3 base address at 0xf8010000 */
-+#define CFG_OR3_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
-+
-+/*
-+ * Serial Port
-+ */
-+#define CONFIG_CONS_INDEX 1
-+#undef CONFIG_SERIAL_SOFTWARE_FIFO
-+#define CFG_NS16550
-+#define CFG_NS16550_SERIAL
-+#define CFG_NS16550_REG_SIZE 1
-+#define CFG_NS16550_CLK get_bus_freq(0)
-+
-+#define CFG_BAUDRATE_TABLE \
-+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-+
-+#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
-+#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
-+
-+/* Use the HUSH parser */
-+#define CFG_HUSH_PARSER
-+#ifdef CFG_HUSH_PARSER
-+#define CFG_PROMPT_HUSH_PS2 "> "
-+#endif
-+
-+/* pass open firmware flat tree */
-+#define CONFIG_OF_FLAT_TREE 1
-+#define CONFIG_OF_BOARD_SETUP 1
-+
-+/* maximum size of the flat tree (8K) */
-+#define OF_FLAT_TREE_MAX_SIZE 8192
-+
-+#define OF_CPU "PowerPC,8323@0"
-+#define OF_SOC "soc8323@e0000000"
-+#define OF_TBCLK (bd->bi_busfreq / 4)
-+#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500"
-+
-+/* I2C */
-+#define CONFIG_HARD_I2C /* I2C with hardware support */
-+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-+#define CONFIG_FSL_I2C
-+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-+#define CFG_I2C_SLAVE 0x7F
-+#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */
-+#define CFG_I2C_OFFSET 0x3000
-+
-+/*
-+ * Config on-board RTC
-+ */
-+#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
-+#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
-+
-+/*
-+ * General PCI
-+ * Addresses are mapped 1-1.
-+ */
-+#define CFG_PCI_MEM_BASE 0x80000000
-+#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
-+#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
-+#define CFG_PCI_MMIO_BASE 0x90000000
-+#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
-+#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
-+#define CFG_PCI_IO_BASE 0xE0300000
-+#define CFG_PCI_IO_PHYS 0xE0300000
-+#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
-+
-+#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE
-+#define CFG_PCI_SLV_MEM_BUS 0x00000000
-+#define CFG_PCI_SLV_MEM_SIZE 0x80000000
-+
-+
-+#ifdef CONFIG_PCI
-+
-+#define CONFIG_NET_MULTI
-+#define CONFIG_PCI_PNP /* do pci plug-and-play */
-+
-+#undef CONFIG_EEPRO100
-+#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-+#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
-+
-+#endif /* CONFIG_PCI */
-+
-+
-+#ifndef CONFIG_NET_MULTI
-+#define CONFIG_NET_MULTI 1
-+#endif
-+
-+/*
-+ * QE UEC ethernet configuration
-+ */
-+#define CONFIG_UEC_ETH
-+#define CONFIG_ETHPRIME "Freescale GETH"
-+
-+#define CONFIG_UEC_ETH1 /* ETH3 */
-+
-+#ifdef CONFIG_UEC_ETH1
-+#define CFG_UEC1_UCC_NUM 2 /* UCC3 */
-+#define CFG_UEC1_RX_CLK QE_CLK9
-+#define CFG_UEC1_TX_CLK QE_CLK10
-+#define CFG_UEC1_ETH_TYPE FAST_ETH
-+#define CFG_UEC1_PHY_ADDR 3
-+#define CFG_UEC1_INTERFACE_MODE ENET_100_MII
-+#endif
-+
-+#define CONFIG_UEC_ETH2 /* ETH4 */
-+
-+#ifdef CONFIG_UEC_ETH2
-+#define CFG_UEC2_UCC_NUM 3 /* UCC4 */
-+#define CFG_UEC2_RX_CLK QE_CLK7
-+#define CFG_UEC2_TX_CLK QE_CLK8
-+#define CFG_UEC2_ETH_TYPE FAST_ETH
-+#define CFG_UEC2_PHY_ADDR 4
-+#define CFG_UEC2_INTERFACE_MODE ENET_100_MII
-+#endif
-+
-+/*
-+ * Environment
-+ */
-+#ifndef CFG_RAMBOOT
-+ #define CFG_ENV_IS_IN_FLASH 1
-+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
-+ #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
-+ #define CFG_ENV_SIZE 0x2000
-+#else
-+ #define CFG_NO_FLASH 1 /* Flash is not usable now */
-+ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
-+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
-+ #define CFG_ENV_SIZE 0x2000
-+#endif
-+
-+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-+
-+#if defined(CFG_RAMBOOT)
-+#if defined(CONFIG_PCI)
-+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
-+ | CFG_CMD_PING \
-+ | CFG_CMD_ASKENV \
-+ | CFG_CMD_PCI \
-+ | CFG_CMD_I2C) \
-+ & \
-+ ~(CFG_CMD_ENV \
-+ | CFG_CMD_LOADS))
-+#else
-+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
-+ | CFG_CMD_PING \
-+ | CFG_CMD_ASKENV \
-+ | CFG_CMD_I2C) \
-+ & \
-+ ~(CFG_CMD_ENV \
-+ | CFG_CMD_LOADS))
-+#endif
-+#else
-+#if defined(CONFIG_PCI)
-+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
-+ | CFG_CMD_PCI \
-+ | CFG_CMD_PING \
-+ | CFG_CMD_ASKENV \
-+ | CFG_CMD_I2C)
-+#else
-+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
-+ | CFG_CMD_PING \
-+ | CFG_CMD_ASKENV \
-+ | CFG_CMD_I2C )
-+#endif
-+#endif
-+
-+#include <cmd_confdefs.h>
-+
-+#undef CONFIG_WATCHDOG /* watchdog disabled */
-+
-+/*
-+ * Miscellaneous configurable options
-+ */
-+#define CFG_LONGHELP /* undef to save memory */
-+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
-+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-+
-+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-+ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-+#else
-+ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
-+#endif
-+
-+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-+#define CFG_MAXARGS 16 /* max number of command args */
-+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-+#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
-+
-+/*
-+ * For booting Linux, the board info and command line data
-+ * have to be in the first 8 MB of memory, since this is
-+ * the maximum mapped by the Linux kernel during initialization.
-+ */
-+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-+
-+/*
-+ * Core HID Setup
-+ */
-+#define CFG_HID0_INIT 0x000000000
-+#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
-+#define CFG_HID2 HID2_HBE
-+
-+/*
-+ * Cache Config
-+ */
-+#define CFG_DCACHE_SIZE 16384
-+#define CFG_CACHELINE_SIZE 32
-+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
-+#endif
-+
-+/*
-+ * MMU Setup
-+ */
-+
-+/* DDR: cache cacheable */
-+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-+#define CFG_DBAT0L CFG_IBAT0L
-+#define CFG_DBAT0U CFG_IBAT0U
-+
-+/* IMMRBAR & PCI IO: cache-inhibit and guarded */
-+#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \
-+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-+#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
-+#define CFG_DBAT1L CFG_IBAT1L
-+#define CFG_DBAT1U CFG_IBAT1U
-+
-+/* BCSR: cache-inhibit and guarded */
-+#define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \
-+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-+#define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
-+#define CFG_DBAT2L CFG_IBAT2L
-+#define CFG_DBAT2U CFG_IBAT2U
-+
-+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
-+#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-+#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-+#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \
-+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-+#define CFG_DBAT3U CFG_IBAT3U
-+
-+#define CFG_IBAT4L (0)
-+#define CFG_IBAT4U (0)
-+#define CFG_DBAT4L CFG_IBAT4L
-+#define CFG_DBAT4U CFG_IBAT4U
-+
-+/* Stack in dcache: cacheable, no memory coherence */
-+#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10)
-+#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-+#define CFG_DBAT5L CFG_IBAT5L
-+#define CFG_DBAT5U CFG_IBAT5U
-+
-+#ifdef CONFIG_PCI
-+/* PCI MEM space: cacheable */
-+#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-+#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-+#define CFG_DBAT6L CFG_IBAT6L
-+#define CFG_DBAT6U CFG_IBAT6U
-+/* PCI MMIO space: cache-inhibit and guarded */
-+#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
-+ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-+#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-+#define CFG_DBAT7L CFG_IBAT7L
-+#define CFG_DBAT7U CFG_IBAT7U
-+#else
-+#define CFG_IBAT6L (0)
-+#define CFG_IBAT6U (0)
-+#define CFG_IBAT7L (0)
-+#define CFG_IBAT7U (0)
-+#define CFG_DBAT6L CFG_IBAT6L
-+#define CFG_DBAT6U CFG_IBAT6U
-+#define CFG_DBAT7L CFG_IBAT7L
-+#define CFG_DBAT7U CFG_IBAT7U
-+#endif
-+
-+/*
-+ * Internal Definitions
-+ *
-+ * Boot Flags
-+ */
-+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-+#define BOOTFLAG_WARM 0x02 /* Software reboot */
-+
-+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
-+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-+#endif
-+
-+/*
-+ * Environment Configuration
-+ */
-+
-+#define CONFIG_ENV_OVERWRITE
-+
-+#if defined(CONFIG_UEC_ETH)
-+#define CONFIG_ETHADDR 00:04:9f:ef:03:01
-+#define CONFIG_HAS_ETH1
-+#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02
-+#endif
-+
-+#define CONFIG_BAUDRATE 115200
-+
-+#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
-+
-+#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
-+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
-+
-+#define CONFIG_EXTRA_ENV_SETTINGS \
-+ "netdev=eth0\0" \
-+ "consoledev=ttyS0\0" \
-+ "ramdiskaddr=1000000\0" \
-+ "ramdiskfile=ramfs.83xx\0" \
-+ "fdtaddr=400000\0" \
-+ "fdtfile=mpc832xemds.dtb\0" \
-+ ""
-+
-+#define CONFIG_NFSBOOTCOMMAND \
-+ "setenv bootargs root=/dev/nfs rw " \
-+ "nfsroot=$serverip:$rootpath " \
-+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-+ "console=$consoledev,$baudrate $othbootargs;" \
-+ "tftp $loadaddr $bootfile;" \
-+ "tftp $fdtaddr $fdtfile;" \
-+ "bootm $loadaddr - $fdtaddr"
-+
-+#define CONFIG_RAMBOOTCOMMAND \
-+ "setenv bootargs root=/dev/ram rw " \
-+ "console=$consoledev,$baudrate $othbootargs;" \
-+ "tftp $ramdiskaddr $ramdiskfile;" \
-+ "tftp $loadaddr $bootfile;" \
-+ "tftp $fdtaddr $fdtfile;" \
-+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
-+
-+
-+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-+
-+#endif /* __CONFIG_H */
-diff --git a/include/mpc83xx.h b/include/mpc83xx.h
-index 504b6a9..52e4369 100644
---- a/include/mpc83xx.h
-+++ b/include/mpc83xx.h
-@@ -75,6 +75,15 @@
- #define SPR_8360E_REV12 0x80480012
- #define SPR_8360_REV12 0x80490012
-
-+#define SPR_8323E_REV10 0x80620010
-+#define SPR_8323_REV10 0x80630010
-+#define SPR_8321E_REV10 0x80660010
-+#define SPR_8321_REV10 0x80670010
-+#define SPR_8323E_REV11 0x80620011
-+#define SPR_8323_REV11 0x80630011
-+#define SPR_8321E_REV11 0x80660011
-+#define SPR_8321_REV11 0x80670011
-+
- /* SPCR - System Priority Configuration Register
- */
- #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */
-@@ -167,6 +176,14 @@
- #define SICRH_UC1EOBI 0x00000004
- #define SICRH_UC2E1OBI 0x00000002
- #define SICRH_UC2E2OBI 0x00000001
-+
-+#elif defined(CONFIG_MPC832X)
-+/* SICRL bits - MPC832X specific */
-+#define SICRL_LDP_LCS_A 0x80000000
-+#define SICRL_IRQ_CKS 0x20000000
-+#define SICRL_PCI_MSRC 0x10000000
-+#define SICRL_URT_CTPR 0x06000000
-+#define SICRL_IRQ_CTPR 0x00C00000
- #endif
-
- /* SWCRR - System Watchdog Control Register
-@@ -270,7 +287,7 @@
- #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
- #define HRCWL_CORE_TO_CSB_3X1 0x00060000
-
--#if defined(CONFIG_MPC8360)
-+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
- #define HRCWL_CEVCOD 0x000000C0
- #define HRCWL_CEVCOD_SHIFT 6
- #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000
-@@ -718,7 +735,7 @@
- #define BR_MS_UPMA 0x00000080 /* UPMA */
- #define BR_MS_UPMB 0x000000A0 /* UPMB */
- #define BR_MS_UPMC 0x000000C0 /* UPMC */
--#if defined(CONFIG_MPC8360)
-+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
- #define BR_ATOM 0x0000000C
- #define BR_ATOM_SHIFT 2
- #endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 02:48:40 +0000