diff options
Diffstat (limited to 'packages/linux/linux-omap2-git')
28 files changed, 77047 insertions, 1648 deletions
diff --git a/packages/linux/linux-omap2-git/beagleboard/0001-omap3-cpuidle.patch b/packages/linux/linux-omap2-git/beagleboard/0001-omap3-cpuidle.patch index 28b1ef2214..cdc9447b4c 100644 --- a/packages/linux/linux-omap2-git/beagleboard/0001-omap3-cpuidle.patch +++ b/packages/linux/linux-omap2-git/beagleboard/0001-omap3-cpuidle.patch @@ -1,450 +1,450 @@ -From: "Rajendra Nayak" <rnayak@ti.com>
-To: <linux-omap@vger.kernel.org>
-Subject: [PATCH 01/02] OMAP3 CPUidle driver
-Date: Tue, 10 Jun 2008 12:39:00 +0530
-
-This patch adds the OMAP3 cpuidle driver. Irq enable/disable is done in the core cpuidle driver
-before it queries the governor for the next state.
-
-Signed-off-by: Rajendra Nayak <rnayak@ti.com>
-
----
- arch/arm/mach-omap2/Makefile | 2
- arch/arm/mach-omap2/cpuidle34xx.c | 293 ++++++++++++++++++++++++++++++++++++++
- arch/arm/mach-omap2/cpuidle34xx.h | 51 ++++++
- arch/arm/mach-omap2/pm34xx.c | 5
- drivers/cpuidle/cpuidle.c | 10 +
- 5 files changed, 359 insertions(+), 2 deletions(-)
-
-Index: linux-omap-2.6/arch/arm/mach-omap2/Makefile
-===================================================================
---- linux-omap-2.6.orig/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:33.855303920 +0530
-+++ linux-omap-2.6/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:39.569121361 +0530
-@@ -20,7 +20,7 @@ obj-y += pm.o
- obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
- obj-$(CONFIG_ARCH_OMAP2420) += sleep242x.o
- obj-$(CONFIG_ARCH_OMAP2430) += sleep243x.o
--obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
-+obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o
- obj-$(CONFIG_PM_DEBUG) += pm-debug.o
- endif
-
-Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c 2008-06-10 11:41:27.644820323 +0530
-@@ -0,0 +1,293 @@
-+/*
-+ * linux/arch/arm/mach-omap2/cpuidle34xx.c
-+ *
-+ * OMAP3 CPU IDLE Routines
-+ *
-+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
-+ * Rajendra Nayak <rnayak@ti.com>
-+ *
-+ * Copyright (C) 2007 Texas Instruments, Inc.
-+ * Karthik Dasu <karthik-dp@ti.com>
-+ *
-+ * Copyright (C) 2006 Nokia Corporation
-+ * Tony Lindgren <tony@atomide.com>
-+ *
-+ * Copyright (C) 2005 Texas Instruments, Inc.
-+ * Richard Woodruff <r-woodruff2@ti.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/cpuidle.h>
-+#include <asm/arch/pm.h>
-+#include <asm/arch/prcm.h>
-+#include <asm/arch/powerdomain.h>
-+#include <asm/arch/clockdomain.h>
-+#include <asm/arch/irqs.h>
-+#include "cpuidle34xx.h"
-+
-+#ifdef CONFIG_CPU_IDLE
-+
-+struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
-+struct omap3_processor_cx current_cx_state;
-+
-+static int omap3_idle_bm_check(void)
-+{
-+ /* Check for omap3_fclks_active() here once available */
-+ return 0;
-+}
-+
-+/* omap3_enter_idle - Programs OMAP3 to enter the specified state.
-+ * returns the total time during which the system was idle.
-+ */
-+static int omap3_enter_idle(struct cpuidle_device *dev,
-+ struct cpuidle_state *state)
-+{
-+ struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
-+ struct timespec ts_preidle, ts_postidle, ts_idle;
-+ struct powerdomain *mpu_pd, *core_pd, *per_pd, *neon_pd;
-+ int neon_pwrst;
-+
-+ current_cx_state = *cx;
-+
-+ if (cx->type == OMAP3_STATE_C0) {
-+ /* Do nothing for C0, not even a wfi */
-+ return 0;
-+ }
-+
-+ /* Used to keep track of the total time in idle */
-+ getnstimeofday(&ts_preidle);
-+
-+ mpu_pd = pwrdm_lookup("mpu_pwrdm");
-+ core_pd = pwrdm_lookup("core_pwrdm");
-+ per_pd = pwrdm_lookup("per_pwrdm");
-+ neon_pd = pwrdm_lookup("neon_pwrdm");
-+
-+ /* Reset previous power state registers */
-+ pwrdm_clear_all_prev_pwrst(mpu_pd);
-+ pwrdm_clear_all_prev_pwrst(neon_pd);
-+ pwrdm_clear_all_prev_pwrst(core_pd);
-+ pwrdm_clear_all_prev_pwrst(per_pd);
-+
-+ if (omap_irq_pending())
-+ return 0;
-+
-+ neon_pwrst = pwrdm_read_pwrst(neon_pd);
-+
-+ /* Program MPU/NEON to target state */
-+ if (cx->mpu_state < PWRDM_POWER_ON) {
-+ if (neon_pwrst == PWRDM_POWER_ON) {
-+ if (cx->mpu_state == PWRDM_POWER_RET)
-+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET);
-+ else if (cx->mpu_state == PWRDM_POWER_OFF)
-+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_OFF);
-+ }
-+ pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
-+ }
-+
-+ /* Program CORE to target state */
-+ if (cx->core_state < PWRDM_POWER_ON)
-+ pwrdm_set_next_pwrst(core_pd, cx->core_state);
-+
-+ /* Execute ARM wfi */
-+ omap_sram_idle();
-+
-+ /* Program MPU/NEON to ON */
-+ if (cx->mpu_state < PWRDM_POWER_ON) {
-+ if (neon_pwrst == PWRDM_POWER_ON)
-+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_ON);
-+ pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON);
-+ }
-+
-+ if (cx->core_state < PWRDM_POWER_ON)
-+ pwrdm_set_next_pwrst(core_pd, PWRDM_POWER_ON);
-+
-+ getnstimeofday(&ts_postidle);
-+ ts_idle = timespec_sub(ts_postidle, ts_preidle);
-+ return timespec_to_ns(&ts_idle);
-+}
-+
-+/*
-+ * omap3_enter_idle_bm - enter function for states with CPUIDLE_FLAG_CHECK_BM
-+ *
-+ * This function checks for all the pre-requisites needed for OMAP3 to enter
-+ * CORE RET/OFF state. It then calls omap3_enter_idle to program the desired
-+ * C state.
-+ */
-+static int omap3_enter_idle_bm(struct cpuidle_device *dev,
-+ struct cpuidle_state *state)
-+{
-+ struct cpuidle_state *new_state = NULL;
-+ int i, j;
-+
-+ if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
-+
-+ /* Find current state in list */
-+ for (i = 0; i < OMAP3_MAX_STATES; i++)
-+ if (state == &dev->states[i])
-+ break;
-+ BUG_ON(i == OMAP3_MAX_STATES);
-+
-+ /* Back up to non 'CHECK_BM' state */
-+ for (j = i - 1; j > 0; j--) {
-+ struct cpuidle_state *s = &dev->states[j];
-+
-+ if (!(s->flags & CPUIDLE_FLAG_CHECK_BM)) {
-+ new_state = s;
-+ break;
-+ }
-+ }
-+
-+ pr_debug("%s: Bus activity: Entering %s (instead of %s)\n",
-+ __FUNCTION__, new_state->name, state->name);
-+ }
-+
-+ return omap3_enter_idle(dev, new_state ? : state);
-+}
-+
-+DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
-+
-+/* omap3_init_power_states - Initialises the OMAP3 specific C states.
-+ * Below is the desciption of each C state.
-+ *
-+ C0 . System executing code
-+ C1 . MPU WFI + Core active
-+ C2 . MPU CSWR + Core active
-+ C3 . MPU OFF + Core active
-+ C4 . MPU CSWR + Core CSWR
-+ C5 . MPU OFF + Core CSWR
-+ C6 . MPU OFF + Core OFF
-+ */
-+void omap_init_power_states(void)
-+{
-+ /* C0 . System executing code */
-+ omap3_power_states[0].valid = 1;
-+ omap3_power_states[0].type = OMAP3_STATE_C0;
-+ omap3_power_states[0].sleep_latency = 0;
-+ omap3_power_states[0].wakeup_latency = 0;
-+ omap3_power_states[0].threshold = 0;
-+ omap3_power_states[0].mpu_state = PWRDM_POWER_ON;
-+ omap3_power_states[0].core_state = PWRDM_POWER_ON;
-+ omap3_power_states[0].flags = CPUIDLE_FLAG_TIME_VALID |
-+ CPUIDLE_FLAG_SHALLOW;
-+
-+ /* C1 . MPU WFI + Core active */
-+ omap3_power_states[1].valid = 1;
-+ omap3_power_states[1].type = OMAP3_STATE_C1;
-+ omap3_power_states[1].sleep_latency = 10;
-+ omap3_power_states[1].wakeup_latency = 10;
-+ omap3_power_states[1].threshold = 30;
-+ omap3_power_states[1].mpu_state = PWRDM_POWER_ON;
-+ omap3_power_states[1].core_state = PWRDM_POWER_ON;
-+ omap3_power_states[1].flags = CPUIDLE_FLAG_TIME_VALID |
-+ CPUIDLE_FLAG_SHALLOW;
-+
-+ /* C2 . MPU CSWR + Core active */
-+ omap3_power_states[2].valid = 1;
-+ omap3_power_states[2].type = OMAP3_STATE_C2;
-+ omap3_power_states[2].sleep_latency = 50;
-+ omap3_power_states[2].wakeup_latency = 50;
-+ omap3_power_states[2].threshold = 300;
-+ omap3_power_states[2].mpu_state = PWRDM_POWER_RET;
-+ omap3_power_states[2].core_state = PWRDM_POWER_ON;
-+ omap3_power_states[2].flags = CPUIDLE_FLAG_TIME_VALID |
-+ CPUIDLE_FLAG_BALANCED;
-+
-+ /* C3 . MPU OFF + Core active */
-+ omap3_power_states[3].valid = 0;
-+ omap3_power_states[3].type = OMAP3_STATE_C3;
-+ omap3_power_states[3].sleep_latency = 1500;
-+ omap3_power_states[3].wakeup_latency = 1800;
-+ omap3_power_states[3].threshold = 4000;
-+ omap3_power_states[3].mpu_state = PWRDM_POWER_OFF;
-+ omap3_power_states[3].core_state = PWRDM_POWER_RET;
-+ omap3_power_states[3].flags = CPUIDLE_FLAG_TIME_VALID |
-+ CPUIDLE_FLAG_BALANCED;
-+
-+ /* C4 . MPU CSWR + Core CSWR*/
-+ omap3_power_states[4].valid = 1;
-+ omap3_power_states[4].type = OMAP3_STATE_C4;
-+ omap3_power_states[4].sleep_latency = 2500;
-+ omap3_power_states[4].wakeup_latency = 7500;
-+ omap3_power_states[4].threshold = 12000;
-+ omap3_power_states[4].mpu_state = PWRDM_POWER_RET;
-+ omap3_power_states[4].core_state = PWRDM_POWER_RET;
-+ omap3_power_states[4].flags = CPUIDLE_FLAG_TIME_VALID |
-+ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
-+
-+ /* C5 . MPU OFF + Core CSWR */
-+ omap3_power_states[5].valid = 0;
-+ omap3_power_states[5].type = OMAP3_STATE_C5;
-+ omap3_power_states[5].sleep_latency = 3000;
-+ omap3_power_states[5].wakeup_latency = 8500;
-+ omap3_power_states[5].threshold = 15000;
-+ omap3_power_states[5].mpu_state = PWRDM_POWER_OFF;
-+ omap3_power_states[5].core_state = PWRDM_POWER_RET;
-+ omap3_power_states[5].flags = CPUIDLE_FLAG_TIME_VALID |
-+ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
-+
-+ /* C6 . MPU OFF + Core OFF */
-+ omap3_power_states[6].valid = 0;
-+ omap3_power_states[6].type = OMAP3_STATE_C6;
-+ omap3_power_states[6].sleep_latency = 10000;
-+ omap3_power_states[6].wakeup_latency = 30000;
-+ omap3_power_states[6].threshold = 300000;
-+ omap3_power_states[6].mpu_state = PWRDM_POWER_OFF;
-+ omap3_power_states[6].core_state = PWRDM_POWER_OFF;
-+ omap3_power_states[6].flags = CPUIDLE_FLAG_TIME_VALID |
-+ CPUIDLE_FLAG_DEEP | CPUIDLE_FLAG_CHECK_BM;
-+}
-+
-+struct cpuidle_driver omap3_idle_driver = {
-+ .name = "omap3_idle",
-+ .owner = THIS_MODULE,
-+};
-+/*
-+ * omap3_idle_init - Init routine for OMAP3 idle.
-+ * Registers the OMAP3 specific cpuidle driver with the cpuidle f/w
-+ * with the valid set of states.
-+ */
-+int omap3_idle_init(void)
-+{
-+ int i, count = 0;
-+ struct omap3_processor_cx *cx;
-+ struct cpuidle_state *state;
-+ struct cpuidle_device *dev;
-+
-+ omap_init_power_states();
-+ cpuidle_register_driver(&omap3_idle_driver);
-+
-+ dev = &per_cpu(omap3_idle_dev, smp_processor_id());
-+
-+ for (i = 0; i < OMAP3_MAX_STATES; i++) {
-+ cx = &omap3_power_states[i];
-+ state = &dev->states[count];
-+
-+ if (!cx->valid)
-+ continue;
-+ cpuidle_set_statedata(state, cx);
-+ state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
-+ state->target_residency = cx->threshold;
-+ state->flags = cx->flags;
-+ state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
-+ omap3_enter_idle_bm : omap3_enter_idle;
-+ sprintf(state->name, "C%d", count+1);
-+ count++;
-+ }
-+
-+ if (!count)
-+ return -EINVAL;
-+ dev->state_count = count;
-+
-+ if (cpuidle_register_device(dev)) {
-+ printk(KERN_ERR "%s: CPUidle register device failed\n",
-+ __FUNCTION__);
-+ return -EIO;
-+ }
-+
-+ return 0;
-+}
-+__initcall(omap3_idle_init);
-+#endif /* CONFIG_CPU_IDLE */
-Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h 2008-06-09 20:15:39.569121361 +0530
-@@ -0,0 +1,51 @@
-+/*
-+ * linux/arch/arm/mach-omap2/cpuidle34xx.h
-+ *
-+ * OMAP3 cpuidle structure definitions
-+ *
-+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
-+ * Written by Rajendra Nayak <rnayak@ti.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
-+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
-+ *
-+ * History:
-+ *
-+ */
-+
-+#ifndef ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX
-+#define ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX
-+
-+#define OMAP3_MAX_STATES 7
-+#define OMAP3_STATE_C0 0 /* C0 - System executing code */
-+#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */
-+#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */
-+#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */
-+#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */
-+#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */
-+#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */
-+
-+extern void omap_sram_idle(void);
-+extern int omap3_irq_pending(void);
-+
-+struct omap3_processor_cx {
-+ u8 valid;
-+ u8 type;
-+ u32 sleep_latency;
-+ u32 wakeup_latency;
-+ u32 mpu_state;
-+ u32 core_state;
-+ u32 threshold;
-+ u32 flags;
-+};
-+
-+void omap_init_power_states(void);
-+int omap3_idle_init(void);
-+
-+#endif /* ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX */
-+
-Index: linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c
-===================================================================
---- linux-omap-2.6.orig/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:15:33.855303920 +0530
-+++ linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:16:20.976798343 +0530
-@@ -141,7 +141,7 @@ static irqreturn_t prcm_interrupt_handle
- return IRQ_HANDLED;
- }
-
--static void omap_sram_idle(void)
-+void omap_sram_idle(void)
- {
- /* Variable to tell what needs to be saved and restored
- * in omap_sram_idle*/
-@@ -156,6 +156,7 @@ static void omap_sram_idle(void)
-
- mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
- switch (mpu_next_state) {
-+ case PWRDM_POWER_ON:
- case PWRDM_POWER_RET:
- /* No need to save context */
- save_state = 0;
-@@ -386,7 +387,9 @@ int __init omap3_pm_init(void)
-
- prcm_setup_regs();
-
-+#ifndef CONFIG_CPU_IDLE
- pm_idle = omap3_pm_idle;
-+#endif
-
- err1:
- return ret;
-Index: linux-omap-2.6/drivers/cpuidle/cpuidle.c
-===================================================================
---- linux-omap-2.6.orig/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:33.856303888 +0530
-+++ linux-omap-2.6/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:39.570121329 +0530
-@@ -58,6 +58,11 @@ static void cpuidle_idle_call(void)
- return;
- }
-
-+#ifdef CONFIG_ARCH_OMAP3
-+ local_irq_disable();
-+ local_fiq_disable();
-+#endif
-+
- /* ask the governor for the next state */
- next_state = cpuidle_curr_governor->select(dev);
- if (need_resched())
-@@ -70,6 +75,11 @@ static void cpuidle_idle_call(void)
- target_state->time += (unsigned long long)dev->last_residency;
- target_state->usage++;
-
-+#ifdef CONFIG_ARCH_OMAP3
-+ local_irq_enable();
-+ local_fiq_enable();
-+#endif
-+
- /* give the governor an opportunity to reflect on the outcome */
- if (cpuidle_curr_governor->reflect)
- cpuidle_curr_governor->reflect(dev);
-
---
-To unsubscribe from this list: send the line "unsubscribe linux-omap" in
-the body of a message to majordomo@vger.kernel.org
-More majordomo info at http://vger.kernel.org/majordomo-info.html
-
+From: "Rajendra Nayak" <rnayak@ti.com> +To: <linux-omap@vger.kernel.org> +Subject: [PATCH 01/02] OMAP3 CPUidle driver +Date: Tue, 10 Jun 2008 12:39:00 +0530 + +This patch adds the OMAP3 cpuidle driver. Irq enable/disable is done in the core cpuidle driver +before it queries the governor for the next state. + +Signed-off-by: Rajendra Nayak <rnayak@ti.com> + +--- + arch/arm/mach-omap2/Makefile | 2 + arch/arm/mach-omap2/cpuidle34xx.c | 293 ++++++++++++++++++++++++++++++++++++++ + arch/arm/mach-omap2/cpuidle34xx.h | 51 ++++++ + arch/arm/mach-omap2/pm34xx.c | 5 + drivers/cpuidle/cpuidle.c | 10 + + 5 files changed, 359 insertions(+), 2 deletions(-) + +Index: linux-omap-2.6/arch/arm/mach-omap2/Makefile +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:33.855303920 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:39.569121361 +0530 +@@ -20,7 +20,7 @@ obj-y += pm.o + obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o + obj-$(CONFIG_ARCH_OMAP2420) += sleep242x.o + obj-$(CONFIG_ARCH_OMAP2430) += sleep243x.o +-obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o ++obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o + obj-$(CONFIG_PM_DEBUG) += pm-debug.o + endif + +Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c 2008-06-10 11:41:27.644820323 +0530 +@@ -0,0 +1,293 @@ ++/* ++ * linux/arch/arm/mach-omap2/cpuidle34xx.c ++ * ++ * OMAP3 CPU IDLE Routines ++ * ++ * Copyright (C) 2007-2008 Texas Instruments, Inc. ++ * Rajendra Nayak <rnayak@ti.com> ++ * ++ * Copyright (C) 2007 Texas Instruments, Inc. ++ * Karthik Dasu <karthik-dp@ti.com> ++ * ++ * Copyright (C) 2006 Nokia Corporation ++ * Tony Lindgren <tony@atomide.com> ++ * ++ * Copyright (C) 2005 Texas Instruments, Inc. ++ * Richard Woodruff <r-woodruff2@ti.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include <linux/cpuidle.h> ++#include <asm/arch/pm.h> ++#include <asm/arch/prcm.h> ++#include <asm/arch/powerdomain.h> ++#include <asm/arch/clockdomain.h> ++#include <asm/arch/irqs.h> ++#include "cpuidle34xx.h" ++ ++#ifdef CONFIG_CPU_IDLE ++ ++struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; ++struct omap3_processor_cx current_cx_state; ++ ++static int omap3_idle_bm_check(void) ++{ ++ /* Check for omap3_fclks_active() here once available */ ++ return 0; ++} ++ ++/* omap3_enter_idle - Programs OMAP3 to enter the specified state. ++ * returns the total time during which the system was idle. ++ */ ++static int omap3_enter_idle(struct cpuidle_device *dev, ++ struct cpuidle_state *state) ++{ ++ struct omap3_processor_cx *cx = cpuidle_get_statedata(state); ++ struct timespec ts_preidle, ts_postidle, ts_idle; ++ struct powerdomain *mpu_pd, *core_pd, *per_pd, *neon_pd; ++ int neon_pwrst; ++ ++ current_cx_state = *cx; ++ ++ if (cx->type == OMAP3_STATE_C0) { ++ /* Do nothing for C0, not even a wfi */ ++ return 0; ++ } ++ ++ /* Used to keep track of the total time in idle */ ++ getnstimeofday(&ts_preidle); ++ ++ mpu_pd = pwrdm_lookup("mpu_pwrdm"); ++ core_pd = pwrdm_lookup("core_pwrdm"); ++ per_pd = pwrdm_lookup("per_pwrdm"); ++ neon_pd = pwrdm_lookup("neon_pwrdm"); ++ ++ /* Reset previous power state registers */ ++ pwrdm_clear_all_prev_pwrst(mpu_pd); ++ pwrdm_clear_all_prev_pwrst(neon_pd); ++ pwrdm_clear_all_prev_pwrst(core_pd); ++ pwrdm_clear_all_prev_pwrst(per_pd); ++ ++ if (omap_irq_pending()) ++ return 0; ++ ++ neon_pwrst = pwrdm_read_pwrst(neon_pd); ++ ++ /* Program MPU/NEON to target state */ ++ if (cx->mpu_state < PWRDM_POWER_ON) { ++ if (neon_pwrst == PWRDM_POWER_ON) { ++ if (cx->mpu_state == PWRDM_POWER_RET) ++ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET); ++ else if (cx->mpu_state == PWRDM_POWER_OFF) ++ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_OFF); ++ } ++ pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state); ++ } ++ ++ /* Program CORE to target state */ ++ if (cx->core_state < PWRDM_POWER_ON) ++ pwrdm_set_next_pwrst(core_pd, cx->core_state); ++ ++ /* Execute ARM wfi */ ++ omap_sram_idle(); ++ ++ /* Program MPU/NEON to ON */ ++ if (cx->mpu_state < PWRDM_POWER_ON) { ++ if (neon_pwrst == PWRDM_POWER_ON) ++ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_ON); ++ pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON); ++ } ++ ++ if (cx->core_state < PWRDM_POWER_ON) ++ pwrdm_set_next_pwrst(core_pd, PWRDM_POWER_ON); ++ ++ getnstimeofday(&ts_postidle); ++ ts_idle = timespec_sub(ts_postidle, ts_preidle); ++ return timespec_to_ns(&ts_idle); ++} ++ ++/* ++ * omap3_enter_idle_bm - enter function for states with CPUIDLE_FLAG_CHECK_BM ++ * ++ * This function checks for all the pre-requisites needed for OMAP3 to enter ++ * CORE RET/OFF state. It then calls omap3_enter_idle to program the desired ++ * C state. ++ */ ++static int omap3_enter_idle_bm(struct cpuidle_device *dev, ++ struct cpuidle_state *state) ++{ ++ struct cpuidle_state *new_state = NULL; ++ int i, j; ++ ++ if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { ++ ++ /* Find current state in list */ ++ for (i = 0; i < OMAP3_MAX_STATES; i++) ++ if (state == &dev->states[i]) ++ break; ++ BUG_ON(i == OMAP3_MAX_STATES); ++ ++ /* Back up to non 'CHECK_BM' state */ ++ for (j = i - 1; j > 0; j--) { ++ struct cpuidle_state *s = &dev->states[j]; ++ ++ if (!(s->flags & CPUIDLE_FLAG_CHECK_BM)) { ++ new_state = s; ++ break; ++ } ++ } ++ ++ pr_debug("%s: Bus activity: Entering %s (instead of %s)\n", ++ __FUNCTION__, new_state->name, state->name); ++ } ++ ++ return omap3_enter_idle(dev, new_state ? : state); ++} ++ ++DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); ++ ++/* omap3_init_power_states - Initialises the OMAP3 specific C states. ++ * Below is the desciption of each C state. ++ * ++ C0 . System executing code ++ C1 . MPU WFI + Core active ++ C2 . MPU CSWR + Core active ++ C3 . MPU OFF + Core active ++ C4 . MPU CSWR + Core CSWR ++ C5 . MPU OFF + Core CSWR ++ C6 . MPU OFF + Core OFF ++ */ ++void omap_init_power_states(void) ++{ ++ /* C0 . System executing code */ ++ omap3_power_states[0].valid = 1; ++ omap3_power_states[0].type = OMAP3_STATE_C0; ++ omap3_power_states[0].sleep_latency = 0; ++ omap3_power_states[0].wakeup_latency = 0; ++ omap3_power_states[0].threshold = 0; ++ omap3_power_states[0].mpu_state = PWRDM_POWER_ON; ++ omap3_power_states[0].core_state = PWRDM_POWER_ON; ++ omap3_power_states[0].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_SHALLOW; ++ ++ /* C1 . MPU WFI + Core active */ ++ omap3_power_states[1].valid = 1; ++ omap3_power_states[1].type = OMAP3_STATE_C1; ++ omap3_power_states[1].sleep_latency = 10; ++ omap3_power_states[1].wakeup_latency = 10; ++ omap3_power_states[1].threshold = 30; ++ omap3_power_states[1].mpu_state = PWRDM_POWER_ON; ++ omap3_power_states[1].core_state = PWRDM_POWER_ON; ++ omap3_power_states[1].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_SHALLOW; ++ ++ /* C2 . MPU CSWR + Core active */ ++ omap3_power_states[2].valid = 1; ++ omap3_power_states[2].type = OMAP3_STATE_C2; ++ omap3_power_states[2].sleep_latency = 50; ++ omap3_power_states[2].wakeup_latency = 50; ++ omap3_power_states[2].threshold = 300; ++ omap3_power_states[2].mpu_state = PWRDM_POWER_RET; ++ omap3_power_states[2].core_state = PWRDM_POWER_ON; ++ omap3_power_states[2].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_BALANCED; ++ ++ /* C3 . MPU OFF + Core active */ ++ omap3_power_states[3].valid = 0; ++ omap3_power_states[3].type = OMAP3_STATE_C3; ++ omap3_power_states[3].sleep_latency = 1500; ++ omap3_power_states[3].wakeup_latency = 1800; ++ omap3_power_states[3].threshold = 4000; ++ omap3_power_states[3].mpu_state = PWRDM_POWER_OFF; ++ omap3_power_states[3].core_state = PWRDM_POWER_RET; ++ omap3_power_states[3].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_BALANCED; ++ ++ /* C4 . MPU CSWR + Core CSWR*/ ++ omap3_power_states[4].valid = 1; ++ omap3_power_states[4].type = OMAP3_STATE_C4; ++ omap3_power_states[4].sleep_latency = 2500; ++ omap3_power_states[4].wakeup_latency = 7500; ++ omap3_power_states[4].threshold = 12000; ++ omap3_power_states[4].mpu_state = PWRDM_POWER_RET; ++ omap3_power_states[4].core_state = PWRDM_POWER_RET; ++ omap3_power_states[4].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM; ++ ++ /* C5 . MPU OFF + Core CSWR */ ++ omap3_power_states[5].valid = 0; ++ omap3_power_states[5].type = OMAP3_STATE_C5; ++ omap3_power_states[5].sleep_latency = 3000; ++ omap3_power_states[5].wakeup_latency = 8500; ++ omap3_power_states[5].threshold = 15000; ++ omap3_power_states[5].mpu_state = PWRDM_POWER_OFF; ++ omap3_power_states[5].core_state = PWRDM_POWER_RET; ++ omap3_power_states[5].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM; ++ ++ /* C6 . MPU OFF + Core OFF */ ++ omap3_power_states[6].valid = 0; ++ omap3_power_states[6].type = OMAP3_STATE_C6; ++ omap3_power_states[6].sleep_latency = 10000; ++ omap3_power_states[6].wakeup_latency = 30000; ++ omap3_power_states[6].threshold = 300000; ++ omap3_power_states[6].mpu_state = PWRDM_POWER_OFF; ++ omap3_power_states[6].core_state = PWRDM_POWER_OFF; ++ omap3_power_states[6].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_DEEP | CPUIDLE_FLAG_CHECK_BM; ++} ++ ++struct cpuidle_driver omap3_idle_driver = { ++ .name = "omap3_idle", ++ .owner = THIS_MODULE, ++}; ++/* ++ * omap3_idle_init - Init routine for OMAP3 idle. ++ * Registers the OMAP3 specific cpuidle driver with the cpuidle f/w ++ * with the valid set of states. ++ */ ++int omap3_idle_init(void) ++{ ++ int i, count = 0; ++ struct omap3_processor_cx *cx; ++ struct cpuidle_state *state; ++ struct cpuidle_device *dev; ++ ++ omap_init_power_states(); ++ cpuidle_register_driver(&omap3_idle_driver); ++ ++ dev = &per_cpu(omap3_idle_dev, smp_processor_id()); ++ ++ for (i = 0; i < OMAP3_MAX_STATES; i++) { ++ cx = &omap3_power_states[i]; ++ state = &dev->states[count]; ++ ++ if (!cx->valid) ++ continue; ++ cpuidle_set_statedata(state, cx); ++ state->exit_latency = cx->sleep_latency + cx->wakeup_latency; ++ state->target_residency = cx->threshold; ++ state->flags = cx->flags; ++ state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ? ++ omap3_enter_idle_bm : omap3_enter_idle; ++ sprintf(state->name, "C%d", count+1); ++ count++; ++ } ++ ++ if (!count) ++ return -EINVAL; ++ dev->state_count = count; ++ ++ if (cpuidle_register_device(dev)) { ++ printk(KERN_ERR "%s: CPUidle register device failed\n", ++ __FUNCTION__); ++ return -EIO; ++ } ++ ++ return 0; ++} ++__initcall(omap3_idle_init); ++#endif /* CONFIG_CPU_IDLE */ +Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h 2008-06-09 20:15:39.569121361 +0530 +@@ -0,0 +1,51 @@ ++/* ++ * linux/arch/arm/mach-omap2/cpuidle34xx.h ++ * ++ * OMAP3 cpuidle structure definitions ++ * ++ * Copyright (C) 2007-2008 Texas Instruments, Inc. ++ * Written by Rajendra Nayak <rnayak@ti.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED ++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. ++ * ++ * History: ++ * ++ */ ++ ++#ifndef ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX ++#define ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX ++ ++#define OMAP3_MAX_STATES 7 ++#define OMAP3_STATE_C0 0 /* C0 - System executing code */ ++#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */ ++#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */ ++#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */ ++#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */ ++#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */ ++#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */ ++ ++extern void omap_sram_idle(void); ++extern int omap3_irq_pending(void); ++ ++struct omap3_processor_cx { ++ u8 valid; ++ u8 type; ++ u32 sleep_latency; ++ u32 wakeup_latency; ++ u32 mpu_state; ++ u32 core_state; ++ u32 threshold; ++ u32 flags; ++}; ++ ++void omap_init_power_states(void); ++int omap3_idle_init(void); ++ ++#endif /* ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX */ ++ +Index: linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:15:33.855303920 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:16:20.976798343 +0530 +@@ -141,7 +141,7 @@ static irqreturn_t prcm_interrupt_handle + return IRQ_HANDLED; + } + +-static void omap_sram_idle(void) ++void omap_sram_idle(void) + { + /* Variable to tell what needs to be saved and restored + * in omap_sram_idle*/ +@@ -156,6 +156,7 @@ static void omap_sram_idle(void) + + mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); + switch (mpu_next_state) { ++ case PWRDM_POWER_ON: + case PWRDM_POWER_RET: + /* No need to save context */ + save_state = 0; +@@ -386,7 +387,9 @@ int __init omap3_pm_init(void) + + prcm_setup_regs(); + ++#ifndef CONFIG_CPU_IDLE + pm_idle = omap3_pm_idle; ++#endif + + err1: + return ret; +Index: linux-omap-2.6/drivers/cpuidle/cpuidle.c +=================================================================== +--- linux-omap-2.6.orig/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:33.856303888 +0530 ++++ linux-omap-2.6/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:39.570121329 +0530 +@@ -58,6 +58,11 @@ static void cpuidle_idle_call(void) + return; + } + ++#ifdef CONFIG_ARCH_OMAP3 ++ local_irq_disable(); ++ local_fiq_disable(); ++#endif ++ + /* ask the governor for the next state */ + next_state = cpuidle_curr_governor->select(dev); + if (need_resched()) +@@ -70,6 +75,11 @@ static void cpuidle_idle_call(void) + target_state->time += (unsigned long long)dev->last_residency; + target_state->usage++; + ++#ifdef CONFIG_ARCH_OMAP3 ++ local_irq_enable(); ++ local_fiq_enable(); ++#endif ++ + /* give the governor an opportunity to reflect on the outcome */ + if (cpuidle_curr_governor->reflect) + cpuidle_curr_governor->reflect(dev); + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/packages/linux/linux-omap2-git/beagleboard/0002-omap3-cpuidle.patch b/packages/linux/linux-omap2-git/beagleboard/0002-omap3-cpuidle.patch index c17c690fe1..d35fd47567 100644 --- a/packages/linux/linux-omap2-git/beagleboard/0002-omap3-cpuidle.patch +++ b/packages/linux/linux-omap2-git/beagleboard/0002-omap3-cpuidle.patch @@ -1,88 +1,88 @@ -From: "Rajendra Nayak" <rnayak@ti.com>
-To: <linux-omap@vger.kernel.org>
-Subject: [PATCH 02/02] Kconfig changes
-Date: Tue, 10 Jun 2008 12:39:02 +0530
-
-Updates the CPUidle Kconfig
-
-Signed-off-by: Rajendra Nayak <rnayak@ti.com>
-
----
- arch/arm/Kconfig | 10 ++++++++++
- drivers/cpuidle/Kconfig | 28 ++++++++++++++++++++++------
- 2 files changed, 32 insertions(+), 6 deletions(-)
-
-Index: linux-omap-2.6/arch/arm/Kconfig
-===================================================================
---- linux-omap-2.6.orig/arch/arm/Kconfig 2008-06-10 11:43:10.790502713 +0530
-+++ linux-omap-2.6/arch/arm/Kconfig 2008-06-10 11:43:38.701604549 +0530
-@@ -954,6 +954,16 @@ config ATAGS_PROC
-
- endmenu
-
-+if (ARCH_OMAP)
-+
-+menu "CPUIdle"
-+
-+source "drivers/cpuidle/Kconfig"
-+
-+endmenu
-+
-+endif
-+
- if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)
-
- menu "CPU Frequency scaling"
-Index: linux-omap-2.6/drivers/cpuidle/Kconfig
-===================================================================
---- linux-omap-2.6.orig/drivers/cpuidle/Kconfig 2008-06-10 11:43:10.790502713 +0530
-+++ linux-omap-2.6/drivers/cpuidle/Kconfig 2008-06-10 12:06:36.139332151 +0530
-@@ -1,20 +1,36 @@
-+menu "CPU idle PM support"
-
- config CPU_IDLE
- bool "CPU idle PM support"
-- default ACPI
-+ default n
- help
- CPU idle is a generic framework for supporting software-controlled
- idle processor power management. It includes modular cross-platform
- governors that can be swapped during runtime.
-
-- If you're using an ACPI-enabled platform, you should say Y here.
-+ If you're using a mobile platform that supports CPU idle PM (e.g.
-+ an ACPI-capable notebook), you should say Y here.
-+
-+if CPU_IDLE
-+
-+comment "Governors"
-
- config CPU_IDLE_GOV_LADDER
-- bool
-+ bool "ladder"
- depends on CPU_IDLE
-- default y
-+ default n
-
- config CPU_IDLE_GOV_MENU
-- bool
-+ bool "menu"
- depends on CPU_IDLE && NO_HZ
-- default y
-+ default n
-+ help
-+ This cpuidle governor evaluates all available states and chooses the
-+ deepest state that meets all of the following constraints: BM activity,
-+ expected time until next timer interrupt, and last break event time
-+ delta. It is designed to minimize power consumption. Currently
-+ dynticks is required.
-+
-+endif # CPU_IDLE
-+
-+endmenu
-
---
-To unsubscribe from this list: send the line "unsubscribe linux-omap" in
-the body of a message to majordomo@vger.kernel.org
-More majordomo info at http://vger.kernel.org/majordomo-info.html
-
+From: "Rajendra Nayak" <rnayak@ti.com> +To: <linux-omap@vger.kernel.org> +Subject: [PATCH 02/02] Kconfig changes +Date: Tue, 10 Jun 2008 12:39:02 +0530 + +Updates the CPUidle Kconfig + +Signed-off-by: Rajendra Nayak <rnayak@ti.com> + +--- + arch/arm/Kconfig | 10 ++++++++++ + drivers/cpuidle/Kconfig | 28 ++++++++++++++++++++++------ + 2 files changed, 32 insertions(+), 6 deletions(-) + +Index: linux-omap-2.6/arch/arm/Kconfig +=================================================================== +--- linux-omap-2.6.orig/arch/arm/Kconfig 2008-06-10 11:43:10.790502713 +0530 ++++ linux-omap-2.6/arch/arm/Kconfig 2008-06-10 11:43:38.701604549 +0530 +@@ -954,6 +954,16 @@ config ATAGS_PROC + + endmenu + ++if (ARCH_OMAP) ++ ++menu "CPUIdle" ++ ++source "drivers/cpuidle/Kconfig" ++ ++endmenu ++ ++endif ++ + if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA) + + menu "CPU Frequency scaling" +Index: linux-omap-2.6/drivers/cpuidle/Kconfig +=================================================================== +--- linux-omap-2.6.orig/drivers/cpuidle/Kconfig 2008-06-10 11:43:10.790502713 +0530 ++++ linux-omap-2.6/drivers/cpuidle/Kconfig 2008-06-10 12:06:36.139332151 +0530 +@@ -1,20 +1,36 @@ ++menu "CPU idle PM support" + + config CPU_IDLE + bool "CPU idle PM support" +- default ACPI ++ default n + help + CPU idle is a generic framework for supporting software-controlled + idle processor power management. It includes modular cross-platform + governors that can be swapped during runtime. + +- If you're using an ACPI-enabled platform, you should say Y here. ++ If you're using a mobile platform that supports CPU idle PM (e.g. ++ an ACPI-capable notebook), you should say Y here. ++ ++if CPU_IDLE ++ ++comment "Governors" + + config CPU_IDLE_GOV_LADDER +- bool ++ bool "ladder" + depends on CPU_IDLE +- default y ++ default n + + config CPU_IDLE_GOV_MENU +- bool ++ bool "menu" + depends on CPU_IDLE && NO_HZ +- default y ++ default n ++ help ++ This cpuidle governor evaluates all available states and chooses the ++ deepest state that meets all of the following constraints: BM activity, ++ expected time until next timer interrupt, and last break event time ++ delta. It is designed to minimize power consumption. Currently ++ dynticks is required. ++ ++endif # CPU_IDLE ++ ++endmenu + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/packages/linux/linux-omap2-git/beagleboard/01-fix-timing-print.diff b/packages/linux/linux-omap2-git/beagleboard/01-fix-timing-print.diff new file mode 100644 index 0000000000..89fbe3a836 --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/01-fix-timing-print.diff @@ -0,0 +1,23 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Sat, 5 Jul 2008 20:31:56 +0000 (+0100) +Subject: omapfb: fix video timings message +X-Git-Tag: beagle-5~3 +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=2929b75035ebe8702ba2ff2c81b654c487701f64 + +omapfb: fix video timings message +--- + +diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c +index 418ed9f..1166a01 100644 +--- a/drivers/video/omap/omapfb_main.c ++++ b/drivers/video/omap/omapfb_main.c +@@ -1789,7 +1789,8 @@ static int omapfb_do_probe(struct platform_device *pdev, + vram, fbdev->mem_desc.region_cnt); + pr_info("omapfb: Pixclock %lu kHz hfreq %lu.%lu kHz " + "vfreq %lu.%lu Hz\n", +- phz / 1000, hhz / 10000, hhz % 10, vhz / 10, vhz % 10); ++ phz / 1000, hhz / 10000, hhz % 10000, ++ vhz / 10, vhz % 10); + + return 0; + diff --git a/packages/linux/linux-omap2-git/beagleboard/02-set-clkseld11.diff b/packages/linux/linux-omap2-git/beagleboard/02-set-clkseld11.diff new file mode 100644 index 0000000000..c437f145d3 --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/02-set-clkseld11.diff @@ -0,0 +1,22 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Sat, 5 Jul 2008 20:32:38 +0000 (+0100) +Subject: omap: set CLKSEL_DSS1 to 2 +X-Git-Tag: beagle-5~2 +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=d23f9c3c5c6243b626f7ec4c255469de2536e488 + +omap: set CLKSEL_DSS1 to 2 +--- + +diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c +index 8fdf8f3..04dedec 100644 +--- a/arch/arm/mach-omap2/clock34xx.c ++++ b/arch/arm/mach-omap2/clock34xx.c +@@ -596,6 +596,8 @@ int __init omap2_clk_init(void) + /* u32 clkrate; */ + u32 cpu_clkflg; + ++ __raw_writel(0x1002, io_p2v(0x48004e40)); ++ + /* REVISIT: Ultimately this will be used for multiboot */ + #if 0 + if (cpu_is_omap242x()) { diff --git a/packages/linux/linux-omap2-git/beagleboard/03-enable-overlay-opt.diff b/packages/linux/linux-omap2-git/beagleboard/03-enable-overlay-opt.diff new file mode 100644 index 0000000000..9fa749f5fc --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/03-enable-overlay-opt.diff @@ -0,0 +1,27 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Sun, 6 Jul 2008 13:15:36 +0000 (+0100) +Subject: omapfb: enable overlay optimisation when possible +X-Git-Tag: beagle-5~1 +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=a63ac3abdf6781f863112321260fe7a5da757802 + +omapfb: enable overlay optimisation when possible +--- + +diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c +index 6aff476..3b36227 100644 +--- a/drivers/video/omap/dispc.c ++++ b/drivers/video/omap/dispc.c +@@ -582,11 +582,13 @@ static int omap_dispc_enable_plane(int plane, int enable) + const u32 at_reg[] = { DISPC_GFX_ATTRIBUTES, + DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES, + DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES }; ++ unsigned overlay_opt = plane & !!enable & !dispc.color_key.key_type; + if ((unsigned int)plane > dispc.mem_desc.region_cnt) + return -EINVAL; + + enable_lcd_clocks(1); + MOD_REG_FLD(at_reg[plane], 1, enable ? 1 : 0); ++ MOD_REG_FLD(DISPC_CONTROL, 1<<12 | 1<<5, overlay_opt<<12 | 1<<5); + enable_lcd_clocks(0); + + return 0; diff --git a/packages/linux/linux-omap2-git/beagleboard/04-use-pcd.diff b/packages/linux/linux-omap2-git/beagleboard/04-use-pcd.diff new file mode 100644 index 0000000000..bdf8ab5f0b --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/04-use-pcd.diff @@ -0,0 +1,28 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Sun, 6 Jul 2008 13:22:54 +0000 (+0100) +Subject: omapfb: use PCD if set in panel config +X-Git-Tag: beagle-5 +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=c8060d36ae156771f00a7a27cabf1b4435c378bd + +omapfb: use PCD if set in panel config +--- + +diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c +index 3b36227..4e1a8e3 100644 +--- a/drivers/video/omap/dispc.c ++++ b/drivers/video/omap/dispc.c +@@ -798,7 +798,13 @@ static void set_lcd_timings(void) + l |= panel->acb & 0xff; + dispc_write_reg(DISPC_POL_FREQ, l); + +- calc_ck_div(is_tft, panel->pixel_clock * 1000, &lck_div, &pck_div); ++ if (panel->pcd) { ++ pck_div = panel->pcd; ++ lck_div = 1; ++ } else { ++ calc_ck_div(is_tft, panel->pixel_clock * 1000, ++ &lck_div, &pck_div); ++ } + + l = dispc_read_reg(DISPC_DIVISOR); + l &= ~(FLD_MASK(16, 8) | FLD_MASK(0, 8)); diff --git a/packages/linux/linux-omap2-git/beagleboard/05-fix-display-panning.diff b/packages/linux/linux-omap2-git/beagleboard/05-fix-display-panning.diff new file mode 100644 index 0000000000..d3c9fffcda --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/05-fix-display-panning.diff @@ -0,0 +1,45 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Mon, 7 Jul 2008 00:13:00 +0000 (+0100) +Subject: omapfb: fix display panning +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=9fec252c96b0e69bcef0afd9cb9dd72b7179c239 + +omapfb: fix display panning +--- + +diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c +index 4e1a8e3..c17371c 100644 +--- a/drivers/video/omap/dispc.c ++++ b/drivers/video/omap/dispc.c +@@ -435,6 +435,8 @@ static inline int _setup_plane(int plane, int channel_out, + + dispc_write_reg(ri_reg[plane], (screen_width - width) * bpp / 8 + 1); + ++ MOD_REG_FLD(DISPC_CONTROL, 1<<5, 1<<5); ++ + return height * screen_width * bpp / 8; + } + +diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c +index 1166a01..3e4959e 100644 +--- a/drivers/video/omap/omapfb_main.c ++++ b/drivers/video/omap/omapfb_main.c +@@ -206,8 +206,8 @@ static int ctrl_change_mode(struct fb_info *fbi) + struct omapfb_device *fbdev = plane->fbdev; + struct fb_var_screeninfo *var = &fbi->var; + +- offset = var->yoffset * fbi->fix.line_length + +- var->xoffset * var->bits_per_pixel / 8; ++ offset = (var->yoffset * var->xres_virtual + var->xoffset) * ++ var->bits_per_pixel / 8; + + if (fbdev->ctrl->sync) + fbdev->ctrl->sync(); +@@ -423,6 +423,8 @@ static void set_fb_fix(struct fb_info *fbi) + } + fix->accel = FB_ACCEL_OMAP1610; + fix->line_length = var->xres_virtual * bpp / 8; ++ fix->xpanstep = 1; ++ fix->ypanstep = 1; + } + + static int set_color_mode(struct omapfb_plane_struct *plane, diff --git a/packages/linux/linux-omap2-git/beagleboard/06-ensure-fclk.diff b/packages/linux/linux-omap2-git/beagleboard/06-ensure-fclk.diff new file mode 100644 index 0000000000..79871a7208 --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/06-ensure-fclk.diff @@ -0,0 +1,31 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Mon, 7 Jul 2008 23:59:08 +0000 (+0100) +Subject: omapfb: ensure fck/lcd < 173MHz +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=0523ece1bad659c48c66aea364d83f7490e7e5ae + +omapfb: ensure fck/lcd < 173MHz +--- + +diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c +index c17371c..85d6cad 100644 +--- a/drivers/video/omap/dispc.c ++++ b/drivers/video/omap/dispc.c +@@ -738,14 +738,16 @@ static void setup_color_conv_coef(void) + MOD_REG_FLD(at2_reg, (1 << 11), ct->full_range); + } + ++#define MAX_FCK_LCD 173000000 ++ + static void calc_ck_div(int is_tft, int pck, int *lck_div, int *pck_div) + { + unsigned long fck, lck; + +- *lck_div = 1; + pck = max(1, pck); + fck = clk_get_rate(dispc.dss1_fck); +- lck = fck; ++ *lck_div = (fck + MAX_FCK_LCD - 1) / MAX_FCK_LCD; ++ lck = fck / *lck_div; + *pck_div = (lck + pck - 1) / pck; + if (is_tft) + *pck_div = max(2, *pck_div); diff --git a/packages/linux/linux-omap2-git/beagleboard/07-set-burst-size.diff b/packages/linux/linux-omap2-git/beagleboard/07-set-burst-size.diff new file mode 100644 index 0000000000..99bd80eae0 --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/07-set-burst-size.diff @@ -0,0 +1,21 @@ +From: Mans Rullgard <mans@mansr.com> +Date: Tue, 8 Jul 2008 18:26:43 +0000 (+0100) +Subject: omapfb: set graphics burst size to 16x32 +X-Git-Url: http://git.mansr.com/?p=linux-omap;a=commitdiff_plain;h=4f9e415dfcd5613a8de973f6c9878cab959c5869 + +omapfb: set graphics burst size to 16x32 +--- + +diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c +index 85d6cad..fd06ca2 100644 +--- a/drivers/video/omap/dispc.c ++++ b/drivers/video/omap/dispc.c +@@ -409,7 +409,7 @@ static inline int _setup_plane(int plane, int channel_out, + l |= cconv_en << 9; + + l &= ~(0x03 << burst_shift); +- l |= DISPC_BURST_8x32 << burst_shift; ++ l |= DISPC_BURST_16x32 << burst_shift; + + l &= ~(1 << chout_shift); + l |= chout_val << chout_shift; diff --git a/packages/linux/linux-omap2-git/beagleboard/16bpp.patch b/packages/linux/linux-omap2-git/beagleboard/16bpp.patch index f1e2181c82..d2bff4b018 100644 --- a/packages/linux/linux-omap2-git/beagleboard/16bpp.patch +++ b/packages/linux/linux-omap2-git/beagleboard/16bpp.patch @@ -1,13 +1,137 @@ +diff --git a/drivers/video/omap/Kconfig b/drivers/video/omap/Kconfig +index bdeb8fb..bf256f3 100644 +--- a/drivers/video/omap/Kconfig ++++ b/drivers/video/omap/Kconfig +@@ -7,6 +7,27 @@ config FB_OMAP + help + Frame buffer driver for OMAP based boards. + ++choice ++ depends on FB_OMAP && MACH_OMAP3_BEAGLE ++ prompt "Screen resolution" ++ default FB_OMAP_079M3R ++ help ++ Selected desired screen resolution ++ ++config FB_OMAP_031M3R ++ boolean "640 x 480 @ 60 Hz Reduced blanking" ++ ++config FB_OMAP_048M3R ++ boolean "800 x 600 @ 60 Hz Reduced blanking" ++ ++config FB_OMAP_079M3R ++ boolean "1024 x 768 @ 60 Hz Reduced blanking" ++ ++config FB_OMAP_092M9R ++ boolean "1280 x 720 @ 60 Hz Reduced blanking" ++ ++endchoice ++ + config FB_OMAP_LCDC_EXTERNAL + bool "External LCD controller support" + depends on FB_OMAP diff --git a/drivers/video/omap/lcd_omap3beagle.c b/drivers/video/omap/lcd_omap3beagle.c -index 69d4e06..c1c4f4c 100644 +index 69d4e06..5e098c2 100644 --- a/drivers/video/omap/lcd_omap3beagle.c +++ b/drivers/video/omap/lcd_omap3beagle.c -@@ -66,7 +66,7 @@ struct lcd_panel omap3beagle_panel = { +@@ -31,10 +31,6 @@ + + #define LCD_PANEL_ENABLE_GPIO 170 + +-#define LCD_XRES 1024 +-#define LCD_YRES 768 +-#define LCD_PIXCLOCK 64000 /* in kHz */ +- + static int omap3beagle_panel_init(struct lcd_panel *panel, + struct omapfb_device *fbdev) + { +@@ -65,19 +61,76 @@ static unsigned long omap3beagle_panel_get_caps(struct lcd_panel *panel) + struct lcd_panel omap3beagle_panel = { .name = "omap3beagle", .config = OMAP_LCDC_PANEL_TFT, - +- - .bpp = 24, + .bpp = 16, .data_lines = 24, - .x_res = LCD_XRES, - .y_res = LCD_YRES, +- .x_res = LCD_XRES, +- .y_res = LCD_YRES, +- .hsw = 3, /* hsync_len (4) - 1 */ +- .hfp = 3, /* right_margin (4) - 1 */ +- .hbp = 39, /* left_margin (40) - 1 */ +- .vsw = 1, /* vsync_len (2) - 1 */ +- .vfp = 2, /* lower_margin */ +- .vbp = 7, /* upper_margin (8) - 1 */ +- +- .pixel_clock = LCD_PIXCLOCK, ++ ++#if defined CONFIG_FB_OMAP_031M3R ++ ++ /* 640 x 480 @ 60 Hz Reduced blanking VESA CVT 0.31M3-R */ ++ .x_res = 640, ++ .y_res = 480, ++ .hfp = 48, ++ .hsw = 32, ++ .hbp = 80, ++ .vfp = 3, ++ .vsw = 4, ++ .vbp = 7, ++ .pixel_clock = 23500, ++ ++#elif defined CONFIG_FB_OMAP_048M3R ++ ++ /* 800 x 600 @ 60 Hz Reduced blanking VESA CVT 0.48M3-R */ ++ .x_res = 800, ++ .y_res = 600, ++ .hfp = 48, ++ .hsw = 32, ++ .hbp = 80, ++ .vfp = 3, ++ .vsw = 4, ++ .vbp = 11, ++ .pixel_clock = 35500, ++ ++#elif defined CONFIG_FB_OMAP_079M3R ++ ++ /* 1024 x 768 @ 60 Hz Reduced blanking VESA CVT 0.79M3-R */ ++ .x_res = 1024, ++ .y_res = 768, ++ .hfp = 48, ++ .hsw = 32, ++ .hbp = 80, ++ .vfp = 3, ++ .vsw = 4, ++ .vbp = 15, ++ .pixel_clock = 56000, ++ ++#elif defined CONFIG_FB_OMAP_092M9R ++ ++ /* 1280 x 720 @ 60 Hz Reduced blanking VESA CVT 0.92M9-R */ ++ .x_res = 1280, ++ .y_res = 720, ++ .hfp = 48, ++ .hsw = 32, ++ .hbp = 80, ++ .vfp = 3, ++ .vsw = 5, ++ .vbp = 13, ++ .pixel_clock = 64000, ++ ++#else ++ ++ /* use 640 x 480 if no config option */ ++ /* 640 x 480 @ 60 Hz Reduced blanking VESA CVT 0.31M3-R */ ++ .x_res = 640, ++ .y_res = 480, ++ .hfp = 48, ++ .hsw = 32, ++ .hbp = 80, ++ .vfp = 3, ++ .vsw = 4, ++ .vbp = 7, ++ .pixel_clock = 23500, ++ ++#endif + + .init = omap3beagle_panel_init, + .cleanup = omap3beagle_panel_cleanup, + diff --git a/packages/linux/linux-omap2-git/beagleboard/cache-display-fix.patch b/packages/linux/linux-omap2-git/beagleboard/cache-display-fix.patch new file mode 100644 index 0000000000..c96b95f2f4 --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/cache-display-fix.patch @@ -0,0 +1,238 @@ +On Tue, 2008-07-01 at 06:23 +0100, Dirk Behme wrote: +> Catalin Marinas wrote: +> > But, anyway, if you want a patch, Harry is updating it to a recent +> > kernel. +> +> Any news on this? I think there are some people wanting a patch ;) + +See below for a preliminary patch updated to 2.6.26-rc8. Note that I +don't plan to submit it in its current form but clean it up a bit first. + + +Show the cache type of ARMv7 CPUs + +From: Catalin Marinas <catalin.marinas@arm.com> + +Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> +--- + + arch/arm/kernel/setup.c | 137 +++++++++++++++++++++++++++++++++++++++++++++- + include/asm-arm/system.h | 18 ++++++ + 2 files changed, 153 insertions(+), 2 deletions(-) + + +diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c +index 5ae0eb2..0cd238d 100644 +--- a/arch/arm/kernel/setup.c ++++ b/arch/arm/kernel/setup.c +@@ -256,6 +256,24 @@ static const char *proc_arch[] = { + "?(17)", + }; + ++static const char *v7_cache_policy[4] = { ++ "reserved", ++ "AVIVT", ++ "VIPT", ++ "PIPT", ++}; ++ ++static const char *v7_cache_type[8] = { ++ "none", ++ "instruction only", ++ "data only", ++ "separate instruction and data", ++ "unified", ++ "unknown type", ++ "unknown type", ++ "unknown type", ++}; ++ + #define CACHE_TYPE(x) (((x) >> 25) & 15) + #define CACHE_S(x) ((x) & (1 << 24)) + #define CACHE_DSIZE(x) (((x) >> 12) & 4095) /* only if S=1 */ +@@ -266,6 +284,22 @@ static const char *proc_arch[] = { + #define CACHE_M(y) ((y) & (1 << 2)) + #define CACHE_LINE(y) ((y) & 3) + ++#define CACHE_TYPE_V7(x) (((x) >> 14) & 3) ++#define CACHE_UNIFIED(x) ((((x) >> 27) & 7)+1) ++#define CACHE_COHERENT(x) ((((x) >> 24) & 7)+1) ++ ++#define CACHE_ID_LEVEL_MASK 7 ++#define CACHE_ID_LEVEL_BITS 3 ++ ++#define CACHE_LINE_V7(v) ((1 << (((v) & 7)+4))) ++#define CACHE_ASSOC_V7(v) ((((v) >> 3) & ((1<<10)-1))+1) ++#define CACHE_SETS_V7(v) ((((v) >> 13) & ((1<<15)-1))+1) ++#define CACHE_SIZE_V7(v) (CACHE_LINE_V7(v)*CACHE_ASSOC_V7(v)*CACHE_SETS_V7(v)) ++#define CACHE_WA_V7(v) (((v) & (1<<28)) != 0) ++#define CACHE_RA_V7(v) (((v) & (1<<29)) != 0) ++#define CACHE_WB_V7(v) (((v) & (1<<30)) != 0) ++#define CACHE_WT_V7(v) (((v) & (1<<31)) != 0) ++ + static inline void dump_cache(const char *prefix, int cpu, unsigned int cache) + { + unsigned int mult = 2 + (CACHE_M(cache) ? 1 : 0); +@@ -279,11 +313,57 @@ static inline void dump_cache(const char *prefix, int cpu, unsigned int cache) + CACHE_LINE(cache))); + } + ++static void dump_v7_cache(const char *type, int cpu, unsigned int level) ++{ ++ unsigned int cachesize; ++ ++ write_extended_cpuid(2,0,0,0,level); /* Set the cache size selection register */ ++ write_extended_cpuid(0,7,5,4,0); /* Prefetch flush to wait for above */ ++ cachesize = read_extended_cpuid(1,0,0,0); ++ ++ printk("CPU%u: %s cache: %d bytes, associativity %d, %d byte lines, %d sets,\n supports%s%s%s%s\n", ++ cpu, type, ++ CACHE_SIZE_V7(cachesize),CACHE_ASSOC_V7(cachesize), ++ CACHE_LINE_V7(cachesize),CACHE_SETS_V7(cachesize), ++ CACHE_WA_V7(cachesize) ? " WA" : "", ++ CACHE_RA_V7(cachesize) ? " RA" : "", ++ CACHE_WB_V7(cachesize) ? " WB" : "", ++ CACHE_WT_V7(cachesize) ? " WT" : ""); ++} ++ + static void __init dump_cpu_info(int cpu) + { + unsigned int info = read_cpuid(CPUID_CACHETYPE); + +- if (info != processor_id) { ++ if (info != processor_id && (info & (1 << 31))) { ++ /* ARMv7 style of cache info register */ ++ unsigned int id = read_extended_cpuid(1,0,0,1); ++ unsigned int level = 0; ++ printk("CPU%u: L1 I %s cache. Caches unified at level %u, coherent at level %u\n", ++ cpu, ++ v7_cache_policy[CACHE_TYPE_V7(info)], ++ CACHE_UNIFIED(id), ++ CACHE_COHERENT(id)); ++ ++ while (id & CACHE_ID_LEVEL_MASK) { ++ printk("CPU%u: Level %u cache is %s\n", ++ cpu, (level >> 1)+1, v7_cache_type[id & CACHE_ID_LEVEL_MASK]); ++ ++ if (id & 1) { ++ /* Dump I at this level */ ++ dump_v7_cache("I", cpu, level | 1); ++ } ++ ++ if (id & (4 | 2)) { ++ /* Dump D or unified at this level */ ++ dump_v7_cache((id & 4) ? "unified" : "D", cpu, level); ++ } ++ ++ /* Next level out */ ++ level += 2; ++ id >>= CACHE_ID_LEVEL_BITS; ++ } ++ } else if (info != processor_id) { + printk("CPU%u: D %s %s cache\n", cpu, cache_is_vivt() ? "VIVT" : "VIPT", + cache_types[CACHE_TYPE(info)]); + if (CACHE_S(info)) { +@@ -916,6 +996,30 @@ c_show_cache(struct seq_file *m, const char *type, unsigned int cache) + CACHE_LINE(cache))); + } + ++static void c_show_v7_cache(struct seq_file *m, const char *type, unsigned int levelselect) ++{ ++ unsigned int cachesize; ++ unsigned int level = (levelselect >> 1) + 1; ++ ++ write_extended_cpuid(2,0,0,0,levelselect); /* Set the cache size selection register */ ++ write_extended_cpuid(0,7,5,4,0); /* Prefetch flush to wait for above */ ++ cachesize = read_extended_cpuid(1,0,0,0); ++ ++ seq_printf(m, "L%u %s size\t\t: %d bytes\n" ++ "L%u %s assoc\t\t: %d\n" ++ "L%u %s line length\t: %d\n" ++ "L%u %s sets\t\t: %d\n" ++ "L%u %s supports\t\t:%s%s%s%s\n", ++ level, type, CACHE_SIZE_V7(cachesize), ++ level, type, CACHE_ASSOC_V7(cachesize), ++ level, type, CACHE_LINE_V7(cachesize), ++ level, type, CACHE_SETS_V7(cachesize), ++ level, type, CACHE_WA_V7(cachesize) ? " WA" : "", ++ CACHE_RA_V7(cachesize) ? " RA" : "", ++ CACHE_WB_V7(cachesize) ? " WB" : "", ++ CACHE_WT_V7(cachesize) ? " WT" : ""); ++} ++ + static int c_show(struct seq_file *m, void *v) + { + int i; +@@ -971,7 +1075,36 @@ static int c_show(struct seq_file *m, void *v) + + { + unsigned int cache_info = read_cpuid(CPUID_CACHETYPE); +- if (cache_info != processor_id) { ++ if (cache_info != processor_id && (cache_info & (1<<31))) { ++ /* V7 style of cache info register */ ++ unsigned int id = read_extended_cpuid(1,0,0,1); ++ unsigned int levelselect = 0; ++ seq_printf(m, "L1 I cache\t:%s\n" ++ "Cache unification level\t: %u\n" ++ "Cache coherency level\t: %u\n", ++ v7_cache_policy[CACHE_TYPE_V7(cache_info)], ++ CACHE_UNIFIED(id), ++ CACHE_COHERENT(id)); ++ ++ while (id & CACHE_ID_LEVEL_MASK) { ++ seq_printf(m, "Level %u cache\t\t: %s\n", ++ (levelselect >> 1)+1, v7_cache_type[id & CACHE_ID_LEVEL_MASK]); ++ ++ if (id & 1) { ++ /* Dump I at this level */ ++ c_show_v7_cache(m, "I", levelselect | 1); ++ } ++ ++ if (id & (4 | 2)) { ++ /* Dump D or unified at this level */ ++ c_show_v7_cache(m, (id & 4) ? "cache" : "D", levelselect); ++ } ++ ++ /* Next level out */ ++ levelselect += 2; ++ id >>= CACHE_ID_LEVEL_BITS; ++ } ++ } else if (cache_info != processor_id) { + seq_printf(m, "Cache type\t: %s\n" + "Cache clean\t: %s\n" + "Cache lockdown\t: %s\n" +diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h +index 514af79..704738e 100644 +--- a/include/asm-arm/system.h ++++ b/include/asm-arm/system.h +@@ -74,6 +74,24 @@ + : "cc"); \ + __val; \ + }) ++#define read_extended_cpuid(op1,op2,op3,op4) \ ++ ({ \ ++ unsigned int __val; \ ++ asm("mrc p15," __stringify(op1) ",%0,c" __stringify(op2)",c" __stringify(op3)"," __stringify(op4) \ ++ : "=r" (__val) \ ++ : \ ++ : "cc"); \ ++ __val; \ ++ }) ++ ++#define write_extended_cpuid(op1,op2,op3,op4,v) \ ++ ({ \ ++ unsigned int __val = v; \ ++ asm("mcr p15," __stringify(op1) ",%0,c" __stringify(op2)",c" __stringify(op3)"," __stringify(op4) \ ++ : \ ++ : "r" (__val) \ ++ : "cc"); \ ++ }) + #else + extern unsigned int processor_id; + #define read_cpuid(reg) (processor_id) + + +-- +Catalin + + diff --git a/packages/linux/linux-omap2-git/beagleboard/defconfig b/packages/linux/linux-omap2-git/beagleboard/defconfig index d4c1e9300a..6381271cf9 100644 --- a/packages/linux/linux-omap2-git/beagleboard/defconfig +++ b/packages/linux/linux-omap2-git/beagleboard/defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.26-rc7-omap1 -# Tue Jun 24 20:16:52 2008 +# Linux kernel version: 2.6.26-rc9-omap1 +# Tue Jul 8 15:36:02 2008 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -23,6 +23,7 @@ CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ARCH_SUPPORTS_AOUT=y CONFIG_ZONE_DMA=y +CONFIG_OPROFILE_ARMV7=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -31,7 +32,6 @@ CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y @@ -84,8 +84,9 @@ CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set -# CONFIG_PROFILING is not set +CONFIG_PROFILING=y # CONFIG_MARKERS is not set +CONFIG_OPROFILE=y CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set CONFIG_HAVE_KPROBES=y @@ -254,7 +255,7 @@ CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_PREEMPT=y +# CONFIG_PREEMPT is not set CONFIG_HZ=128 CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set @@ -346,7 +347,7 @@ CONFIG_PM=y CONFIG_PM_SLEEP=y CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y -CONFIG_APM_EMULATION=y +# CONFIG_APM_EMULATION is not set CONFIG_ARCH_SUSPEND_POSSIBLE=y # @@ -772,7 +773,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set -# CONFIG_INPUT_APMPOWER is not set # # Input Device Drivers @@ -932,7 +932,6 @@ CONFIG_HAVE_GPIO_LIB=y CONFIG_POWER_SUPPLY=m # CONFIG_POWER_SUPPLY_DEBUG is not set # CONFIG_PDA_POWER is not set -# CONFIG_APM_POWER is not set # CONFIG_BATTERY_DS2760 is not set # CONFIG_BATTERY_BQ27x00 is not set CONFIG_HWMON=y @@ -1038,6 +1037,7 @@ CONFIG_MEDIA_TUNER=m # CONFIG_MEDIA_TUNER_CUSTOMIZE is not set CONFIG_MEDIA_TUNER_SIMPLE=m CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA18271=m CONFIG_MEDIA_TUNER_TDA9887=m CONFIG_MEDIA_TUNER_TEA5761=m CONFIG_MEDIA_TUNER_TEA5767=m @@ -1049,9 +1049,17 @@ CONFIG_MEDIA_TUNER_XC2028=m CONFIG_MEDIA_TUNER_XC5000=m CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L1=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_VIDEO_TUNER=m CONFIG_VIDEO_CAPTURE_DRIVERS=y # CONFIG_VIDEO_ADV_DEBUG is not set CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_WM8775=m +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_CX25840=m +CONFIG_VIDEO_CX2341X=m # CONFIG_VIDEO_VIVI is not set # CONFIG_VIDEO_CPIA is not set # CONFIG_VIDEO_CPIA2 is not set @@ -1060,23 +1068,29 @@ CONFIG_VIDEO_HELPER_CHIPS_AUTO=y # CONFIG_TUNER_3036 is not set # CONFIG_VIDEO_AU0828 is not set CONFIG_V4L_USB_DRIVERS=y -# CONFIG_VIDEO_PVRUSB2 is not set +CONFIG_USB_VIDEO_CLASS=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set # CONFIG_VIDEO_EM28XX is not set -# CONFIG_VIDEO_USBVISION is not set -# CONFIG_USB_VICAM is not set -# CONFIG_USB_IBMCAM is not set -# CONFIG_USB_KONICAWC is not set -# CONFIG_USB_QUICKCAM_MESSENGER is not set +CONFIG_VIDEO_USBVISION=m +CONFIG_VIDEO_USBVIDEO=m +CONFIG_USB_VICAM=m +CONFIG_USB_IBMCAM=m +CONFIG_USB_KONICAWC=m +CONFIG_USB_QUICKCAM_MESSENGER=m # CONFIG_USB_ET61X251 is not set -# CONFIG_VIDEO_OVCAMCHIP is not set -# CONFIG_USB_W9968CF is not set -# CONFIG_USB_OV511 is not set -# CONFIG_USB_SE401 is not set -# CONFIG_USB_SN9C102 is not set -# CONFIG_USB_STV680 is not set +CONFIG_VIDEO_OVCAMCHIP=m +CONFIG_USB_W9968CF=m +CONFIG_USB_OV511=m +CONFIG_USB_SE401=m +CONFIG_USB_SN9C102=m +CONFIG_USB_STV680=m # CONFIG_USB_ZC0301 is not set -# CONFIG_USB_PWC is not set -# CONFIG_USB_ZR364XX is not set +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_ZR364XX=m # CONFIG_USB_STKWEBCAM is not set # CONFIG_SOC_CAMERA is not set CONFIG_RADIO_ADAPTERS=y @@ -1226,9 +1240,13 @@ CONFIG_FB_CFB_IMAGEBLIT=y # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set CONFIG_FB_OMAP=y +# CONFIG_FB_OMAP_031M3R is not set +# CONFIG_FB_OMAP_048M3R is not set +CONFIG_FB_OMAP_079M3R=y +# CONFIG_FB_OMAP_092M9R is not set # CONFIG_FB_OMAP_LCDC_EXTERNAL is not set # CONFIG_FB_OMAP_BOOTLOADER_INIT is not set -CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=4 +CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=8 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -1827,7 +1845,6 @@ CONFIG_TIMER_STATS=y # CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set -CONFIG_DEBUG_PREEMPT=y # CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_RT_MUTEX_TESTER is not set # CONFIG_DEBUG_SPINLOCK is not set diff --git a/packages/linux/linux-omap2-git/beagleboard/fix-dispc-clocks.patch b/packages/linux/linux-omap2-git/beagleboard/fix-dispc-clocks.patch deleted file mode 100644 index aade27fd8a..0000000000 --- a/packages/linux/linux-omap2-git/beagleboard/fix-dispc-clocks.patch +++ /dev/null @@ -1,147 +0,0 @@ -From linux-omap-owner@vger.kernel.org Sun Jun 22 10:11:39 2008
-Received: from localhost
- ([127.0.0.1] helo=dominion ident=koen)
- by dominion.dominion.void with esmtp (Exim 4.63)
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-Date: Sat, 21 Jun 2008 11:05:10 -0600 (MDT)
-From: Paul Walmsley <paul@pwsan.com>
-To: "Gadiyar, Anand" <gadiyar@ti.com>,
- "linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>
-cc: Dirk Behme <dirk.behme@googlemail.com>,
- "jouni.hogander@nokia.com" <jouni.hogander@nokia.com>
-Subject: [PATCH] OMAP3 clock: fix omap2_clk_wait_ready for OMAP3430ES2 DSS
-In-Reply-To: <5A47E75E594F054BAF48C5E4FC4B92AB022BB66209@dbde02.ent.ti.com>
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-
-
-On OMAP3430ES2, DSS has both an initiator standby CM_IDLEST bit, and a
-target idle CM_IDLEST bit. This is a departure from previous silicon,
-which only had an initiator standby bit.
-
-This means we need to test the target idle bit after enabling
-dss1_alwon_fclk. Previous clock code has done the wrong thing since ES2
-came out: it's either tested the wrong bit, causing intermittent
-
- Clock dss1_alwon_fck didn't enable in 100000 tries
-
-messages; or not tested anything at all, causing intermittent crashes
-during DISPC initialization with:
-
- Unhandled fault: external abort on non-linefetch (0x1028)
-
-This patch modifies omap2_clk_wait_ready() to wait for the DSS to become
-accessible after dss1_alwon_fclk is enabled.
-
-Thanks to Anand Gadiyar <gadiyar@ti.com> for identifying one of the
-problem patches.
-
-Signed-off-by: Paul Walmsley <paul@pwsan.com>
----
-
- arch/arm/mach-omap2/clock.c | 30 ++++++++++++++++++++++++------
- arch/arm/mach-omap2/cm-regbits-34xx.h | 4 +++-
- 2 files changed, 27 insertions(+), 7 deletions(-)
-
-diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
-index ed15868..1820f75 100644
---- a/arch/arm/mach-omap2/clock.c
-+++ b/arch/arm/mach-omap2/clock.c
-@@ -244,18 +244,36 @@ static void omap2_clk_wait_ready(struct clk *clk)
- }
-
- /* REVISIT: What are the appropriate exclusions for 34XX? */
-- /* OMAP3: ignore DSS-mod clocks */
-- if (cpu_is_omap34xx() &&
-- ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
-- (((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(CORE_MOD, 0)) &&
-- clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
-- return;
-+ if (cpu_is_omap34xx()) {
-+
-+ /* 3430ES1 DSS and SSI have no target idlest bits */
-+ if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0) &&
-+ ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
-+ ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&
-+ clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
-+ return;
-+
-+ /* Even for 3430ES2 DSS, only wait for dss1_alwon_fclk */
-+ if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0) &&
-+ (reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) &&
-+ clk->enable_bit != OMAP3430_EN_DSS1_SHIFT)
-+ return;
-+
-+ }
-
- /* Check if both functional and interface clocks
- * are running. */
- bit = 1 << clk->enable_bit;
- if (!(__raw_readl((__force void __iomem *)other_reg) & bit))
- return;
-+
-+ /* OMAP3430ES2 DSS is an unusual case */
-+ if (cpu_is_omap34xx() &&
-+ (reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) &&
-+ clk->enable_bit == OMAP3430_EN_DSS1_SHIFT) {
-+ bit = OMAP3430ES2_ST_DSS_IDLE;
-+ }
-+
- st_reg = ((other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
-
- omap2_wait_clock_ready((__force void __iomem *)st_reg, bit, clk->name);
-diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
-index 6ec66f4..946c552 100644
---- a/arch/arm/mach-omap2/cm-regbits-34xx.h
-+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
-@@ -500,7 +500,9 @@
- #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
-
- /* CM_IDLEST_DSS */
--#define OMAP3430_ST_DSS (1 << 0)
-+#define OMAP3430ES2_ST_DSS_IDLE (1 << 1)
-+#define OMAP3430ES2_ST_DSS_STDBY (1 << 0)
-+#define OMAP3430ES1_ST_DSS (1 << 0)
-
- /* CM_AUTOIDLE_DSS */
- #define OMAP3430_AUTO_DSS (1 << 0)
---
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-the body of a message to majordomo@vger.kernel.org
-More majordomo info at http://vger.kernel.org/majordomo-info.html
-
diff --git a/packages/linux/linux-omap2-git/beagleboard/i2c-omap-race-fix.diff b/packages/linux/linux-omap2-git/beagleboard/i2c-omap-race-fix.diff new file mode 100644 index 0000000000..6eb33f76b7 --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/i2c-omap-race-fix.diff @@ -0,0 +1,118 @@ +From linux-omap-owner@vger.kernel.org Tue Jul 15 21:23:13 2008 +Received: from localhost + ([127.0.0.1] helo=dominion ident=koen) + by dominion.dominion.void with esmtp (Exim 4.69) + (envelope-from <linux-omap-owner@vger.kernel.org>) + id 1KIq7E-0004FX-VS + for koen@localhost; Tue, 15 Jul 2008 21:23:13 +0200 +Received: from xs.service.utwente.nl [130.89.5.250] + by dominion with POP3 (fetchmail-6.3.6) + for <koen@localhost> (single-drop); Tue, 15 Jul 2008 21:23:12 +0200 (CEST) +Received: from mail.service.utwente.nl ([130.89.5.254]) by exchange.service.utwente.nl with Microsoft SMTPSVC(6.0.3790.3959); + Tue, 15 Jul 2008 21:01:02 +0200 +Received: from mx.utwente.nl ([130.89.2.12]) by mail.service.utwente.nl with Microsoft SMTPSVC(6.0.3790.3959); + Tue, 15 Jul 2008 21:01:01 +0200 +Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) + by mx.utwente.nl (8.12.10/SuSE Linux 0.7) with ESMTP id m6FJ0qDf031889 + for <k.kooi@student.utwente.nl>; Tue, 15 Jul 2008 21:00:52 +0200 +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1756776AbYGOTAV (ORCPT <rfc822;k.kooi@student.utwente.nl>); + Tue, 15 Jul 2008 15:00:21 -0400 +Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1755065AbYGOTAV + (ORCPT <rfc822;linux-omap-outgoing>); + Tue, 15 Jul 2008 15:00:21 -0400 +Received: from utopia.booyaka.com ([72.9.107.138]:35569 "EHLO + utopia.booyaka.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1756776AbYGOTAU (ORCPT + <rfc822;linux-omap@vger.kernel.org>); Tue, 15 Jul 2008 15:00:20 -0400 +Received: (qmail 2982 invoked by uid 526); 15 Jul 2008 19:00:18 -0000 +Date: Tue, 15 Jul 2008 13:00:18 -0600 (MDT) +From: Paul Walmsley <paul@pwsan.com> +To: linux-omap@vger.kernel.org +Subject: [PATCH] i2c-omap: close suspected race between omap_i2c_idle() and + omap_i2c_isr() +Message-ID: <alpine.DEB.1.00.0807151259180.467@utopia.booyaka.com> +User-Agent: Alpine 1.00 (DEB 882 2007-12-20) +MIME-Version: 1.0 +Content-Type: TEXT/PLAIN; charset=US-ASCII +Sender: linux-omap-owner@vger.kernel.org +Precedence: bulk +List-ID: <linux-omap.vger.kernel.org> +X-Mailing-List: linux-omap@vger.kernel.org +X-UTwente-MailScanner-Information: Scanned by MailScanner. Contact servicedesk@icts.utwente.nl for more information. +X-UTwente-MailScanner: Found to be clean +X-UTwente-MailScanner-From: linux-omap-owner@vger.kernel.org +X-Spam-Status: No +X-OriginalArrivalTime: 15 Jul 2008 19:01:01.0610 (UTC) FILETIME=[1FBA68A0:01C8E6AD] + + +omap_i2c_idle() sets an internal flag, "dev->idle", instructing its +ISR to decline interrupts. It sets this flag before it actually masks +the interrupts on the I2C controller. This is problematic, since an +I2C interrupt could arrive after dev->idle is set, but before the +interrupt source is masked. When this happens, Linux disables the I2C +controller's IRQ, causing all future transactions on the bus to fail. + +Symptoms, happening on about 7% of boots: + + irq 56: nobody cared (try booting with the "irqpoll" option) + <warning traceback here> + Disabling IRQ #56 + i2c_omap i2c_omap.1: controller timed out + +In omap_i2c_idle(), this patch sets dev->idle only after the interrupt +mask write to the I2C controller has left the ARM write buffer. +That's probably the major offender. For additional prophylaxis, in +omap_i2c_unidle(), the patch clears the dev->idle flag before +interrupts are enabled, rather than afterwards. + +The patch has survived twenty-two reboots on the 3430SDP here without +wedging I2C1. Not absolutely dispositive, but promising! + + +Signed-off-by: Paul Walmsley <paul@pwsan.com> +--- + + drivers/i2c/busses/i2c-omap.c | 10 ++++++++-- + 1 files changed, 8 insertions(+), 2 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c +index 55779f5..ed7e9ad 100644 +--- a/drivers/i2c/busses/i2c-omap.c ++++ b/drivers/i2c/busses/i2c-omap.c +@@ -209,22 +209,28 @@ static void omap_i2c_unidle(struct omap_i2c_dev *dev) + if (dev->iclk != NULL) + clk_enable(dev->iclk); + clk_enable(dev->fclk); ++ dev->idle = 0; + if (dev->iestate) + omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); +- dev->idle = 0; + } + + static void omap_i2c_idle(struct omap_i2c_dev *dev) + { + u16 iv; + +- dev->idle = 1; + dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); + omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0); + if (dev->rev1) + iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); + else + omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate); ++ /* ++ * The wmb() is to ensure that the I2C interrupt mask write ++ * reaches the I2C controller before the dev->idle store ++ * occurs. ++ */ ++ wmb(); ++ dev->idle = 1; + clk_disable(dev->fclk); + if (dev->iclk != NULL) + clk_disable(dev->iclk); +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/packages/linux/linux-omap2-git/beagleboard/logo_linux_clut224.ppm b/packages/linux/linux-omap2-git/beagleboard/logo_linux_clut224.ppm new file mode 100644 index 0000000000..d29fc1c544 --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/logo_linux_clut224.ppm @@ -0,0 +1,73147 @@ +P3 +# CREATOR: GIMP PNM Filter Version 1.1 +387 63 +255 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 +97 +3 +246 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+0 diff --git a/packages/linux/linux-omap2-git/beagleboard/no-empty-flash-warnings.patch b/packages/linux/linux-omap2-git/beagleboard/no-empty-flash-warnings.patch new file mode 100644 index 0000000000..ab344b0449 --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/no-empty-flash-warnings.patch @@ -0,0 +1,15 @@ +diff --git a/fs/jffs2/scan.c b/fs/jffs2/scan.c +index 1d437de..33b3feb 100644 +--- a/fs/jffs2/scan.c ++++ b/fs/jffs2/scan.c +@@ -647,8 +647,8 @@ scan_more: + inbuf_ofs = ofs - buf_ofs; + while (inbuf_ofs < scan_end) { + if (unlikely(*(uint32_t *)(&buf[inbuf_ofs]) != 0xffffffff)) { +- printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n", +- empty_start, ofs); ++// printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n", ++// empty_start, ofs); + if ((err = jffs2_scan_dirty_space(c, jeb, ofs-empty_start))) + return err; + goto scan_more; diff --git a/packages/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch b/packages/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch deleted file mode 100644 index 25e5aad9c9..0000000000 --- a/packages/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch +++ /dev/null @@ -1,114 +0,0 @@ -From linux-omap-owner@vger.kernel.org Tue Jun 24 09:24:30 2008 -Received: from localhost - ([127.0.0.1] helo=dominion ident=koen) - by dominion.dominion.void with esmtp (Exim 4.63) - (envelope-from <linux-omap-owner@vger.kernel.org>) - id 1KB2tB-0005XT-FQ - for koen@localhost; Tue, 24 Jun 2008 09:24:30 +0200 -Received: from xs.service.utwente.nl [130.89.5.250] - by dominion with POP3 (fetchmail-6.3.6) - for <koen@localhost> (single-drop); Tue, 24 Jun 2008 09:24:29 +0200 (CEST) -Received: from mail.service.utwente.nl ([130.89.5.254]) by exchange.service.utwente.nl with Microsoft SMTPSVC(6.0.3790.3959); - Tue, 24 Jun 2008 09:13:04 +0200 -Received: from mx.utwente.nl ([130.89.2.13]) by mail.service.utwente.nl with Microsoft SMTPSVC(6.0.3790.3959); - Tue, 24 Jun 2008 09:13:03 +0200 -Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) - by mx.utwente.nl (8.12.10/SuSE Linux 0.7) with ESMTP id m5O7CcD7008917 - for <k.kooi@student.utwente.nl>; Tue, 24 Jun 2008 09:12:38 +0200 -Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand - id S1751623AbYFXHMh (ORCPT <rfc822;k.kooi@student.utwente.nl>); - Tue, 24 Jun 2008 03:12:37 -0400 -Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751670AbYFXHMh - (ORCPT <rfc822;linux-omap-outgoing>); - Tue, 24 Jun 2008 03:12:37 -0400 -Received: from utopia.booyaka.com ([72.9.107.138]:47392 "EHLO - utopia.booyaka.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org - with ESMTP id S1751623AbYFXHMg (ORCPT - <rfc822;linux-omap@vger.kernel.org>); Tue, 24 Jun 2008 03:12:36 -0400 -Received: (qmail 1797 invoked by uid 526); 24 Jun 2008 07:12:35 -0000 -Date: Tue, 24 Jun 2008 01:12:35 -0600 (MDT) -From: Paul Walmsley <paul@pwsan.com> -To: linux-omap@vger.kernel.org -Subject: [PATCH] OMAP3 clock: DPLL{1,2}_FCLK clksel can divide by 4 -Message-ID: <alpine.DEB.1.00.0806240111320.9741@utopia.booyaka.com> -User-Agent: Alpine 1.00 (DEB 882 2007-12-20) -MIME-Version: 1.0 -Content-Type: TEXT/PLAIN; charset=US-ASCII -Sender: linux-omap-owner@vger.kernel.org -Precedence: bulk -List-ID: <linux-omap.vger.kernel.org> -X-Mailing-List: linux-omap@vger.kernel.org -X-UTwente-MailScanner-Information: Scanned by MailScanner. Contact servicedesk@icts.utwente.nl for more information. -X-UTwente-MailScanner: Found to be clean -X-UTwente-MailScanner-From: linux-omap-owner@vger.kernel.org -X-Spam-Status: No -X-OriginalArrivalTime: 24 Jun 2008 07:13:04.0264 (UTC) FILETIME=[BE950880:01C8D5C9] - - -OMAP34xx ES2 TRM Delta G to H states that the divider for DPLL1_FCLK and -DPLL2_FCLK can divide by 4 in addition to dividing by 1 and 2. Encode this -into the OMAP3 clock framework. - -Signed-off-by: Paul Walmsley <paul@pwsan.com> ---- - - arch/arm/mach-omap2/clock34xx.h | 20 ++++++++++++++++---- - 1 files changed, 16 insertions(+), 4 deletions(-) - -diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h -index b4dceea..9605744 100644 ---- a/arch/arm/mach-omap2/clock34xx.h -+++ b/arch/arm/mach-omap2/clock34xx.h -@@ -1029,8 +1029,15 @@ static struct clk corex2_fck = { - - /* DPLL power domain clock controls */ - --static const struct clksel div2_core_clksel[] = { -- { .parent = &core_ck, .rates = div2_rates }, -+static const struct clksel_rate div4_rates[] = { -+ { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, -+ { .div = 2, .val = 2, .flags = RATE_IN_343X }, -+ { .div = 4, .val = 4, .flags = RATE_IN_343X }, -+ { .div = 0 } -+}; -+ -+static const struct clksel div4_core_clksel[] = { -+ { .parent = &core_ck, .rates = div4_rates }, - { .parent = NULL } - }; - -@@ -1044,7 +1051,7 @@ static struct clk dpll1_fck = { - .init = &omap2_init_clksel_parent, - .clksel_reg = _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), - .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, -- .clksel = div2_core_clksel, -+ .clksel = div4_core_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, - .recalc = &omap2_clksel_recalc, -@@ -1119,7 +1126,7 @@ static struct clk dpll2_fck = { - .init = &omap2_init_clksel_parent, - .clksel_reg = _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), - .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, -- .clksel = div2_core_clksel, -+ .clksel = div4_core_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, - .recalc = &omap2_clksel_recalc, -@@ -1155,6 +1162,11 @@ static struct clk iva2_ck = { - - /* Common interface clocks */ - -+static const struct clksel div2_core_clksel[] = { -+ { .parent = &core_ck, .rates = div2_rates }, -+ { .parent = NULL } -+}; -+ - static struct clk l3_ick = { - .name = "l3_ick", - .parent = &core_ck, --- -To unsubscribe from this list: send the line "unsubscribe linux-omap" in -the body of a message to majordomo@vger.kernel.org -More majordomo info at http://vger.kernel.org/majordomo-info.html - diff --git a/packages/linux/linux-omap2-git/beagleboard/omap3-jitter.patch b/packages/linux/linux-omap2-git/beagleboard/omap3-jitter.patch deleted file mode 100644 index 2e0dfd9f13..0000000000 --- a/packages/linux/linux-omap2-git/beagleboard/omap3-jitter.patch +++ /dev/null @@ -1,95 +0,0 @@ -From linux-omap-owner@vger.kernel.org Tue Jun 24 09:24:30 2008 -Received: from localhost - ([127.0.0.1] helo=dominion ident=koen) - by dominion.dominion.void with esmtp (Exim 4.63) - (envelope-from <linux-omap-owner@vger.kernel.org>) - id 1KB2tC-0005XT-Mj - for koen@localhost; Tue, 24 Jun 2008 09:24:30 +0200 -Received: from xs.service.utwente.nl [130.89.5.250] - by dominion with POP3 (fetchmail-6.3.6) - for <koen@localhost> (single-drop); Tue, 24 Jun 2008 09:24:30 +0200 (CEST) -Received: from mail.service.utwente.nl ([130.89.5.253]) by exchange.service.utwente.nl with Microsoft SMTPSVC(6.0.3790.3959); - Tue, 24 Jun 2008 09:20:48 +0200 -Received: from smtp.utwente.nl ([130.89.2.8]) by mail.service.utwente.nl with Microsoft SMTPSVC(6.0.3790.3959); - Tue, 24 Jun 2008 09:20:47 +0200 -Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) - by smtp.utwente.nl (8.12.10/SuSE Linux 0.7) with ESMTP id m5O7BPWU031214 - for <k.kooi@student.utwente.nl>; Tue, 24 Jun 2008 09:11:25 +0200 -Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand - id S1751128AbYFXHLY (ORCPT <rfc822;k.kooi@student.utwente.nl>); - Tue, 24 Jun 2008 03:11:24 -0400 -Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751405AbYFXHLX - (ORCPT <rfc822;linux-omap-outgoing>); - Tue, 24 Jun 2008 03:11:23 -0400 -Received: from utopia.booyaka.com ([72.9.107.138]:44580 "EHLO - utopia.booyaka.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org - with ESMTP id S1751128AbYFXHLX (ORCPT - <rfc822;linux-omap@vger.kernel.org>); Tue, 24 Jun 2008 03:11:23 -0400 -Received: (qmail 1744 invoked by uid 526); 24 Jun 2008 07:11:21 -0000 -Date: Tue, 24 Jun 2008 01:11:21 -0600 (MDT) -From: Paul Walmsley <paul@pwsan.com> -To: linux-omap@vger.kernel.org -Subject: [PATCH] OMAP3 clock: fix DPLL jitter correction and rate - programming -Message-ID: <alpine.DEB.1.00.0806240109440.9741@utopia.booyaka.com> -User-Agent: Alpine 1.00 (DEB 882 2007-12-20) -MIME-Version: 1.0 -Content-Type: TEXT/PLAIN; charset=US-ASCII -Sender: linux-omap-owner@vger.kernel.org -Precedence: bulk -List-ID: <linux-omap.vger.kernel.org> -X-Mailing-List: linux-omap@vger.kernel.org -X-UTwente-MailScanner-Information: Scanned by MailScanner. Contact servicedesk@icts.utwente.nl for more information. -X-UTwente-MailScanner: Found to be clean -X-UTwente-MailScanner-From: linux-omap-owner@vger.kernel.org -X-Spam-Status: No -X-OriginalArrivalTime: 24 Jun 2008 07:20:48.0265 (UTC) FILETIME=[D325F790:01C8D5CA] - - -Fix DPLL jitter correction programming. Previously, -omap3_noncore_dpll_program() stored the FREQSEL jitter correction -parameter to the wrong register. This caused jitter correction to be set -incorrectly and also caused the DPLL divider to be programmed incorrectly. - -Also, fix DPLL divider programming. An off-by-one error existed in -omap3_noncore_dpll_program(), causing DPLLs to be programmed with a higher -divider than intended. - -Signed-off-by: Paul Walmsley <paul@pwsan.com> ---- - - arch/arm/mach-omap2/clock34xx.c | 13 ++++++++----- - 1 files changed, 8 insertions(+), 5 deletions(-) - -diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c -index 408b51a..8fdf8f3 100644 ---- a/arch/arm/mach-omap2/clock34xx.c -+++ b/arch/arm/mach-omap2/clock34xx.c -@@ -346,14 +346,17 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) - /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ - _omap3_noncore_dpll_bypass(clk); - -+ /* Set jitter correction */ -+ v = __raw_readl(dd->control_reg); -+ v &= ~dd->freqsel_mask; -+ v |= freqsel << __ffs(dd->freqsel_mask); -+ __raw_writel(v, dd->control_reg); -+ -+ /* Set DPLL multiplier, divider */ - v = __raw_readl(dd->mult_div1_reg); - v &= ~(dd->mult_mask | dd->div1_mask); -- -- /* Set mult (M), div1 (N), freqsel */ - v |= m << __ffs(dd->mult_mask); -- v |= n << __ffs(dd->div1_mask); -- v |= freqsel << __ffs(dd->freqsel_mask); -- -+ v |= (n - 1) << __ffs(dd->div1_mask); - __raw_writel(v, dd->mult_div1_reg); - - /* We let the clock framework set the other output dividers later */ --- -To unsubscribe from this list: send the line "unsubscribe linux-omap" in -the body of a message to majordomo@vger.kernel.org -More majordomo info at http://vger.kernel.org/majordomo-info.html - diff --git a/packages/linux/linux-omap2-git/beagleboard/oprofile-0.9.3.armv7.diff b/packages/linux/linux-omap2-git/beagleboard/oprofile-0.9.3.armv7.diff new file mode 100644 index 0000000000..dbc11fbe7d --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/oprofile-0.9.3.armv7.diff @@ -0,0 +1,611 @@ +Hi, + +This patch adds Oprofile support on ARMv7, using the PMNC unit. +Tested on OMAP3430 SDP. + +Feedback and comments are welcome. + +The patch to user space components is attached for reference. It i applies +against version 0.9.3 of oprofile source +(http://prdownloads.sourceforge.net/oprofile/oprofile-0.9.3.tar.gz). + +Regards, +Jean. + +--- + +From: Jean Pihet <jpihet@mvista.com> +Date: Tue, 6 May 2008 17:21:44 +0200 +Subject: [PATCH] ARM: Add ARMv7 oprofile support + +Add ARMv7 Oprofile support to kernel + +Signed-off-by: Jean Pihet <jpihet@mvista.com> +--- + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index c60a27d..60b50a0 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -161,6 +161,11 @@ config OPROFILE_MPCORE + config OPROFILE_ARM11_CORE + bool + ++config OPROFILE_ARMV7 ++ def_bool y ++ depends on CPU_V7 && !SMP ++ bool ++ + endif + + config VECTORS_BASE +diff --git a/arch/arm/oprofile/Makefile b/arch/arm/oprofile/Makefile +index e61d0cc..88e31f5 100644 +--- a/arch/arm/oprofile/Makefile ++++ b/arch/arm/oprofile/Makefile +@@ -11,3 +11,4 @@ oprofile-$(CONFIG_CPU_XSCALE) += op_model_xscale.o + oprofile-$(CONFIG_OPROFILE_ARM11_CORE) += op_model_arm11_core.o + oprofile-$(CONFIG_OPROFILE_ARMV6) += op_model_v6.o + oprofile-$(CONFIG_OPROFILE_MPCORE) += op_model_mpcore.o ++oprofile-$(CONFIG_OPROFILE_ARMV7) += op_model_v7.o +diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c +index 0a5cf3a..3fcd752 100644 +--- a/arch/arm/oprofile/common.c ++++ b/arch/arm/oprofile/common.c +@@ -145,6 +145,10 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) + spec = &op_mpcore_spec; + #endif + ++#ifdef CONFIG_OPROFILE_ARMV7 ++ spec = &op_armv7_spec; ++#endif ++ + if (spec) { + ret = spec->init(); + if (ret < 0) +diff --git a/arch/arm/oprofile/op_arm_model.h +b/arch/arm/oprofile/op_arm_model.h +index 4899c62..8c4e4f6 100644 +--- a/arch/arm/oprofile/op_arm_model.h ++++ b/arch/arm/oprofile/op_arm_model.h +@@ -26,6 +26,7 @@ extern struct op_arm_model_spec op_xscale_spec; + + extern struct op_arm_model_spec op_armv6_spec; + extern struct op_arm_model_spec op_mpcore_spec; ++extern struct op_arm_model_spec op_armv7_spec; + + extern void arm_backtrace(struct pt_regs * const regs, unsigned int depth); + +diff --git a/arch/arm/oprofile/op_model_v7.c b/arch/arm/oprofile/op_model_v7.c +new file mode 100644 +index 0000000..a159bc1 +--- /dev/null ++++ b/arch/arm/oprofile/op_model_v7.c +@@ -0,0 +1,407 @@ ++/** ++ * @file op_model_v7.c ++ * ARM V7 (Cortex A8) Event Monitor Driver ++ * ++ * @remark Copyright 2008 Jean Pihet <jpihet@mvista.com> ++ * @remark Copyright 2004 ARM SMP Development Team ++ */ ++#include <linux/types.h> ++#include <linux/errno.h> ++#include <linux/oprofile.h> ++#include <linux/interrupt.h> ++#include <linux/irq.h> ++#include <linux/smp.h> ++ ++#include "op_counter.h" ++#include "op_arm_model.h" ++#include "op_model_v7.h" ++ ++/* #define DEBUG */ ++ ++ ++/* ++ * ARM V7 PMNC support ++ */ ++ ++static u32 cnt_en[CNTMAX]; ++ ++static inline void armv7_pmnc_write(u32 val) ++{ ++ val &= PMNC_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (val)); ++} ++ ++static inline u32 armv7_pmnc_read(void) ++{ ++ u32 val; ++ ++ asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); ++ return val; ++} ++ ++static inline u32 armv7_pmnc_enable_counter(unsigned int cnt) ++{ ++ u32 val; ++ ++ if (cnt >= CNTMAX) { ++ printk(KERN_ERR "oprofile: CPU%u enabling wrong PMNC counter" ++ " %d\n", smp_processor_id(), cnt); ++ return -1; ++ } ++ ++ if (cnt == CCNT) ++ val = CNTENS_C; ++ else ++ val = (1 << (cnt - CNT0)); ++ ++ val &= CNTENS_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val)); ++ ++ return cnt; ++} ++ ++static inline u32 armv7_pmnc_disable_counter(unsigned int cnt) ++{ ++ u32 val; ++ ++ if (cnt >= CNTMAX) { ++ printk(KERN_ERR "oprofile: CPU%u disabling wrong PMNC counter" ++ " %d\n", smp_processor_id(), cnt); ++ return -1; ++ } ++ ++ if (cnt == CCNT) ++ val = CNTENC_C; ++ else ++ val = (1 << (cnt - CNT0)); ++ ++ val &= CNTENC_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val)); ++ ++ return cnt; ++} ++ ++static inline u32 armv7_pmnc_enable_intens(unsigned int cnt) ++{ ++ u32 val; ++ ++ if (cnt >= CNTMAX) { ++ printk(KERN_ERR "oprofile: CPU%u enabling wrong PMNC counter" ++ " interrupt enable %d\n", smp_processor_id(), cnt); ++ return -1; ++ } ++ ++ if (cnt == CCNT) ++ val = INTENS_C; ++ else ++ val = (1 << (cnt - CNT0)); ++ ++ val &= INTENS_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val)); ++ ++ return cnt; ++} ++ ++static inline u32 armv7_pmnc_getreset_flags(void) ++{ ++ u32 val; ++ ++ /* Read */ ++ asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); ++ ++ /* Write to clear flags */ ++ val &= FLAG_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val)); ++ ++ return val; ++} ++ ++static inline int armv7_pmnc_select_counter(unsigned int cnt) ++{ ++ u32 val; ++ ++ if ((cnt == CCNT) || (cnt >= CNTMAX)) { ++ printk(KERN_ERR "oprofile: CPU%u selecting wrong PMNC counteri" ++ " %d\n", smp_processor_id(), cnt); ++ return -1; ++ } ++ ++ val = (cnt - CNT0) & SELECT_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val)); ++ ++ return cnt; ++} ++ ++static inline void armv7_pmnc_write_evtsel(unsigned int cnt, u32 val) ++{ ++ if (armv7_pmnc_select_counter(cnt) == cnt) { ++ val &= EVTSEL_MASK; ++ asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); ++ } ++} ++ ++static void armv7_pmnc_reset_counter(unsigned int cnt) ++{ ++ u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt); ++ u32 val = -(u32)counter_config[cpu_cnt].count; ++ ++ switch (cnt) { ++ case CCNT: ++ armv7_pmnc_disable_counter(cnt); ++ ++ asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (val)); ++ ++ if (cnt_en[cnt] != 0) ++ armv7_pmnc_enable_counter(cnt); ++ ++ break; ++ ++ case CNT0: ++ case CNT1: ++ case CNT2: ++ case CNT3: ++ armv7_pmnc_disable_counter(cnt); ++ ++ if (armv7_pmnc_select_counter(cnt) == cnt) ++ asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (val)); ++ ++ if (cnt_en[cnt] != 0) ++ armv7_pmnc_enable_counter(cnt); ++ ++ break; ++ ++ default: ++ printk(KERN_ERR "oprofile: CPU%u resetting wrong PMNC counter" ++ " %d\n", smp_processor_id(), cnt); ++ break; ++ } ++} ++ ++int armv7_setup_pmnc(void) ++{ ++ unsigned int cnt; ++ ++ if (armv7_pmnc_read() & PMNC_E) { ++ printk(KERN_ERR "oprofile: CPU%u PMNC still enabled when setup" ++ " new event counter.\n", smp_processor_id()); ++ return -EBUSY; ++ } ++ ++ /* ++ * Initialize & Reset PMNC: C bit, D bit and P bit. ++ * Note: Using a slower count for CCNT (D bit: divide by 64) results ++ * in a more stable system ++ */ ++ armv7_pmnc_write(PMNC_P | PMNC_C | PMNC_D); ++ ++ ++ for (cnt = CCNT; cnt < CNTMAX; cnt++) { ++ unsigned long event; ++ u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt); ++ ++ /* ++ * Disable counter ++ */ ++ armv7_pmnc_disable_counter(cnt); ++ cnt_en[cnt] = 0; ++ ++ if (!counter_config[cpu_cnt].enabled) ++ continue; ++ ++ event = counter_config[cpu_cnt].event & 255; ++ ++ /* ++ * Set event (if destined for PMNx counters) ++ * We don't need to set the event if it's a cycle count ++ */ ++ if (cnt != CCNT) ++ armv7_pmnc_write_evtsel(cnt, event); ++ ++ /* ++ * Enable interrupt for this counter ++ */ ++ armv7_pmnc_enable_intens(cnt); ++ ++ /* ++ * Reset counter ++ */ ++ armv7_pmnc_reset_counter(cnt); ++ ++ /* ++ * Enable counter ++ */ ++ armv7_pmnc_enable_counter(cnt); ++ cnt_en[cnt] = 1; ++ } ++ ++ return 0; ++} ++ ++static inline void armv7_start_pmnc(void) ++{ ++ armv7_pmnc_write(armv7_pmnc_read() | PMNC_E); ++} ++ ++static inline void armv7_stop_pmnc(void) ++{ ++ armv7_pmnc_write(armv7_pmnc_read() & ~PMNC_E); ++} ++ ++/* ++ * CPU counters' IRQ handler (one IRQ per CPU) ++ */ ++static irqreturn_t armv7_pmnc_interrupt(int irq, void *arg) ++{ ++ struct pt_regs *regs = get_irq_regs(); ++ unsigned int cnt; ++ u32 flags; ++ ++ ++ /* ++ * Stop IRQ generation ++ */ ++ armv7_stop_pmnc(); ++ ++ /* ++ * Get and reset overflow status flags ++ */ ++ flags = armv7_pmnc_getreset_flags(); ++ ++ /* ++ * Cycle counter ++ */ ++ if (flags & FLAG_C) { ++ u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), CCNT); ++ armv7_pmnc_reset_counter(CCNT); ++ oprofile_add_sample(regs, cpu_cnt); ++ } ++ ++ /* ++ * PMNC counters 0:3 ++ */ ++ for (cnt = CNT0; cnt < CNTMAX; cnt++) { ++ if (flags & (1 << (cnt - CNT0))) { ++ u32 cpu_cnt = CPU_COUNTER(smp_processor_id(), cnt); ++ armv7_pmnc_reset_counter(cnt); ++ oprofile_add_sample(regs, cpu_cnt); ++ } ++ } ++ ++ /* ++ * Allow IRQ generation ++ */ ++ armv7_start_pmnc(); ++ ++ return IRQ_HANDLED; ++} ++ ++int armv7_request_interrupts(int *irqs, int nr) ++{ ++ unsigned int i; ++ int ret = 0; ++ ++ for (i = 0; i < nr; i++) { ++ ret = request_irq(irqs[i], armv7_pmnc_interrupt, ++ IRQF_DISABLED, "CP15 PMNC", NULL); ++ if (ret != 0) { ++ printk(KERN_ERR "oprofile: unable to request IRQ%u" ++ " for ARMv7\n", ++ irqs[i]); ++ break; ++ } ++ } ++ ++ if (i != nr) ++ while (i-- != 0) ++ free_irq(irqs[i], NULL); ++ ++ return ret; ++} ++ ++void armv7_release_interrupts(int *irqs, int nr) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < nr; i++) ++ free_irq(irqs[i], NULL); ++} ++ ++#ifdef DEBUG ++static void armv7_pmnc_dump_regs(void) ++{ ++ u32 val; ++ unsigned int cnt; ++ ++ printk(KERN_INFO "PMNC registers dump:\n"); ++ ++ asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); ++ printk(KERN_INFO "PMNC =0x%08x\n", val); ++ ++ asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val)); ++ printk(KERN_INFO "CNTENS=0x%08x\n", val); ++ ++ asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val)); ++ printk(KERN_INFO "INTENS=0x%08x\n", val); ++ ++ asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); ++ printk(KERN_INFO "FLAGS =0x%08x\n", val); ++ ++ asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val)); ++ printk(KERN_INFO "SELECT=0x%08x\n", val); ++ ++ asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); ++ printk(KERN_INFO "CCNT =0x%08x\n", val); ++ ++ for (cnt = CNT0; cnt < CNTMAX; cnt++) { ++ armv7_pmnc_select_counter(cnt); ++ asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); ++ printk(KERN_INFO "CNT[%d] count =0x%08x\n", cnt-CNT0, val); ++ asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); ++ printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n", cnt-CNT0, val); ++ } ++} ++#endif ++ ++ ++static int irqs[] = { ++#ifdef CONFIG_ARCH_OMAP3 ++ INT_34XX_BENCH_MPU_EMUL, ++#endif ++}; ++ ++static void armv7_pmnc_stop(void) ++{ ++#ifdef DEBUG ++ armv7_pmnc_dump_regs(); ++#endif ++ armv7_stop_pmnc(); ++ armv7_release_interrupts(irqs, ARRAY_SIZE(irqs)); ++} ++ ++static int armv7_pmnc_start(void) ++{ ++ int ret; ++ ++#ifdef DEBUG ++ armv7_pmnc_dump_regs(); ++#endif ++ ret = armv7_request_interrupts(irqs, ARRAY_SIZE(irqs)); ++ if (ret >= 0) ++ armv7_start_pmnc(); ++ ++ return ret; ++} ++ ++static int armv7_detect_pmnc(void) ++{ ++ return 0; ++} ++ ++struct op_arm_model_spec op_armv7_spec = { ++ .init = armv7_detect_pmnc, ++ .num_counters = 5, ++ .setup_ctrs = armv7_setup_pmnc, ++ .start = armv7_pmnc_start, ++ .stop = armv7_pmnc_stop, ++ .name = "arm/armv7", ++}; +diff --git a/arch/arm/oprofile/op_model_v7.h b/arch/arm/oprofile/op_model_v7.h +new file mode 100644 +index 0000000..08f40ea +--- /dev/null ++++ b/arch/arm/oprofile/op_model_v7.h +@@ -0,0 +1,101 @@ ++/** ++ * @file op_model_v7.h ++ * ARM v7 (Cortex A8) Event Monitor Driver ++ * ++ * @remark Copyright 2008 Jean Pihet <jpihet@mvista.com> ++ * @remark Copyright 2004 ARM SMP Development Team ++ * @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com> ++ * @remark Copyright 2000-2004 MontaVista Software Inc ++ * @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com> ++ * @remark Copyright 2004 Intel Corporation ++ * @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk> ++ * @remark Copyright 2004 Oprofile Authors ++ * ++ * @remark Read the file COPYING ++ * ++ * @author Zwane Mwaikambo ++ */ ++#ifndef OP_MODEL_V7_H ++#define OP_MODEL_V7_H ++ ++/* ++ * Per-CPU PMNC: config reg ++ */ ++#define PMNC_E (1 << 0) /* Enable all counters */ ++#define PMNC_P (1 << 1) /* Reset all counters */ ++#define PMNC_C (1 << 2) /* Cycle counter reset */ ++#define PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */ ++#define PMNC_X (1 << 4) /* Export to ETM */ ++#define PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ ++#define PMNC_MASK 0x3f /* Mask for writable bits */ ++ ++/* ++ * Available counters ++ */ ++#define CCNT 0 ++#define CNT0 1 ++#define CNT1 2 ++#define CNT2 3 ++#define CNT3 4 ++#define CNTMAX 5 ++ ++#define CPU_COUNTER(cpu, counter) ((cpu) * CNTMAX + (counter)) ++ ++/* ++ * CNTENS: counters enable reg ++ */ ++#define CNTENS_P0 (1 << 0) ++#define CNTENS_P1 (1 << 1) ++#define CNTENS_P2 (1 << 2) ++#define CNTENS_P3 (1 << 3) ++#define CNTENS_C (1 << 31) ++#define CNTENS_MASK 0x8000000f /* Mask for writable bits */ ++ ++/* ++ * CNTENC: counters disable reg ++ */ ++#define CNTENC_P0 (1 << 0) ++#define CNTENC_P1 (1 << 1) ++#define CNTENC_P2 (1 << 2) ++#define CNTENC_P3 (1 << 3) ++#define CNTENC_C (1 << 31) ++#define CNTENC_MASK 0x8000000f /* Mask for writable bits */ ++ ++/* ++ * INTENS: counters overflow interrupt enable reg ++ */ ++#define INTENS_P0 (1 << 0) ++#define INTENS_P1 (1 << 1) ++#define INTENS_P2 (1 << 2) ++#define INTENS_P3 (1 << 3) ++#define INTENS_C (1 << 31) ++#define INTENS_MASK 0x8000000f /* Mask for writable bits */ ++ ++/* ++ * EVTSEL: Event selection reg ++ */ ++#define EVTSEL_MASK 0x7f /* Mask for writable bits */ ++ ++/* ++ * SELECT: Counter selection reg ++ */ ++#define SELECT_MASK 0x1f /* Mask for writable bits */ ++ ++/* ++ * FLAG: counters overflow flag status reg ++ */ ++#define FLAG_P0 (1 << 0) ++#define FLAG_P1 (1 << 1) ++#define FLAG_P2 (1 << 2) ++#define FLAG_P3 (1 << 3) ++#define FLAG_C (1 << 31) ++#define FLAG_MASK 0x8000000f /* Mask for writable bits */ ++ ++ ++int armv7_setup_pmu(void); ++int armv7_start_pmu(void); ++int armv7_stop_pmu(void); ++int armv7_request_interrupts(int *, int); ++void armv7_release_interrupts(int *, int); ++ ++#endif +diff --git a/include/asm-arm/arch-omap/irqs.h +b/include/asm-arm/arch-omap/irqs.h +index c80e160..89ca90e 100644 +--- a/include/asm-arm/arch-omap/irqs.h ++++ b/include/asm-arm/arch-omap/irqs.h +@@ -297,6 +297,7 @@ + #define INT_243X_HS_USB_DMA 93 + #define INT_243X_CARKIT_IRQ 94 + ++#define INT_34XX_BENCH_MPU_EMUL 3 + #define INT_34XX_ST_MCBSP2_IRQ 4 + #define INT_34XX_ST_MCBSP3_IRQ 5 + #define INT_34XX_SYS_NIRQ 7 diff --git a/packages/linux/linux-omap2-git/beagleboard/serialfix.diff b/packages/linux/linux-omap2-git/beagleboard/serialfix.diff new file mode 100644 index 0000000000..74c2ebaa69 --- /dev/null +++ b/packages/linux/linux-omap2-git/beagleboard/serialfix.diff @@ -0,0 +1,18 @@ +--- /tmp/pm34xx.c 2008-07-14 18:09:08.000000000 +0200 ++++ git/arch/arm/mach-omap2/pm34xx.c 2008-07-14 18:09:42.453198000 +0200 +@@ -398,13 +398,13 @@ + INT_34XX_PRCM_MPU_IRQ); + goto err1; + } +- ++/* + ret = pwrdm_for_each(pwrdms_setup); + if (ret) { + printk(KERN_ERR "Failed to setup powerdomains\n"); + goto err2; + } +- ++*/ + mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); + if (mpu_pwrdm == NULL) { + printk(KERN_ERR "Failed to get mpu_pwrdm\n"); diff --git a/packages/linux/linux-omap2-git/beagleboard/soc.patch b/packages/linux/linux-omap2-git/beagleboard/soc.patch index bb97403f29..f4cce21ca7 100644 --- a/packages/linux/linux-omap2-git/beagleboard/soc.patch +++ b/packages/linux/linux-omap2-git/beagleboard/soc.patch @@ -29,10 +29,10 @@ index 4e1314c..d2c0b12 100644 +obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c new file mode 100644 -index 0000000..c9eee19 +index 0000000..eb8370c --- /dev/null +++ b/sound/soc/codecs/twl4030.c -@@ -0,0 +1,595 @@ +@@ -0,0 +1,625 @@ +/* + * ALSA SoC TWL4030 codec driver + * @@ -196,7 +196,7 @@ index 0000000..c9eee19 + twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, + twl4030_reg[REG_CODEC_MODE] & 0xfd, REG_CODEC_MODE); + -+ udelay(10); /* 10 ms delay for power settling */ ++ udelay(10); /* delay for power settling */ + + for (i = REG_OPTION; i <= REG_MISC_SET_2; i++) { + twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, twl4030_reg[i], i); @@ -205,7 +205,7 @@ index 0000000..c9eee19 + twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, + twl4030_reg[REG_CODEC_MODE], REG_CODEC_MODE); + -+ udelay(10); /* 10 ms delay for power settling */ ++ udelay(10); /* delay for power settling */ + + /* initiate offset cancellation */ + twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, @@ -219,7 +219,6 @@ index 0000000..c9eee19 + twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, + twl4030_reg[REG_MISC_SET_1] | 0x02, REG_MISC_SET_1); + -+ twl4030_dump_registers(); +} + +static const struct snd_kcontrol_new twl4030_snd_controls[] = { @@ -247,8 +246,6 @@ index 0000000..c9eee19 + return 0; +} + -+#define TWL4030_PWR 0 -+ +static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { + SND_SOC_DAPM_INPUT("INL"), + SND_SOC_DAPM_INPUT("INR"), @@ -314,32 +311,40 @@ index 0000000..c9eee19 + +static void twl4030_power_up (struct snd_soc_codec *codec, u8 mode) +{ ++ u8 popn, hsgain; ++ + twl4030_write(codec, REG_CODEC_MODE, mode & ~CODECPDZ); + twl4030_write(codec, REG_CODEC_MODE, mode | CODECPDZ); + udelay(10); + -+ u8 popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET) | (0x40); ++ popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET); ++ popn &= RAMP_DELAY; ++ popn |= VMID_EN | RAMP_DELAY_161MS; + twl4030_write(codec, REG_HS_POPN_SET, popn); + -+ u8 hsgain = twl4030_read_reg_cache(codec, REG_HS_GAIN_SET) | (0x0a); ++ hsgain = HSR_GAIN_0DB| HSL_GAIN_0DB; + twl4030_write(codec, REG_HS_GAIN_SET, hsgain); + -+ popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET) | (0x02); ++ popn |= RAMP_EN; + twl4030_write(codec, REG_HS_POPN_SET, popn); +} + +static void twl4030_power_down (struct snd_soc_codec *codec) +{ -+ u8 popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET) & ~(0x02); ++ u8 popn, hsgain, mode; ++ ++ popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET); ++ popn &= ~RAMP_EN; + twl4030_write(codec, REG_HS_POPN_SET, popn); + -+ u8 hsgain = twl4030_read_reg_cache(codec, REG_HS_GAIN_SET) & ~(0x0f); ++ hsgain = HSR_GAIN_PWR_DOWN | HSL_GAIN_PWR_DOWN; + twl4030_write(codec, REG_HS_GAIN_SET, hsgain); + -+ popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET) & ~(0x40); ++ popn &= ~VMID_EN; + twl4030_write(codec, REG_HS_POPN_SET, popn); + -+ u8 mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE) & ~CODECPDZ; ++ mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); ++ mode &= ~CODECPDZ; + twl4030_write(codec, REG_CODEC_MODE, mode); + udelay(10); +} @@ -352,19 +357,18 @@ index 0000000..c9eee19 + struct snd_soc_device *socdev = rtd->socdev; + struct snd_soc_codec *codec = socdev->codec; + struct twl4030_priv *twl4030 = codec->private_data; ++ u8 mode, old_mode, format, old_format; + -+ twl4030_power_down(codec); -+ -+ u8 mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE) & ~CODECPDZ; + ++ /* bit rate */ ++ old_mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE) & ~CODECPDZ; ++ mode = old_mode; + mode &= ~APLL_RATE; + switch (params_rate(params)) { + case 44100: -+ printk(KERN_INFO "TWL4030 hw params: set rate to 44.1khz\n"); + mode |= APLL_RATE_44100; + break; + case 48000: -+ printk(KERN_INFO "TWL4030 hw params: set rate to 48khz\n"); + mode |= APLL_RATE_48000; + break; + default: @@ -372,22 +376,43 @@ index 0000000..c9eee19 + return -EINVAL; + } + -+ /* bit size */ ++ if (mode != old_mode) { ++ /* change rate and turn codec back on */ ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ mode |= CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ } ++ ++ /* sample size */ ++ old_format = twl4030_read_reg_cache(codec, REG_AUDIO_IF); ++ format = old_format; ++ format &= ~DATA_WIDTH; + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: -+ printk(KERN_INFO "TWL4030 hw params: set format to S16_LE\n"); ++ format |= DATA_WIDTH_16S_16W; + break; + case SNDRV_PCM_FORMAT_S24_LE: -+ printk(KERN_INFO "TWL4030 hw params: set format to S24_LE\n"); ++ format |= DATA_WIDTH_32S_24W; + break; + default: + printk(KERN_INFO "TWL4030 hw params: unknown format %d\n", params_format(params)); + return -EINVAL; + } + -+ /* change rate and turn codec back on */ -+ twl4030_power_up(codec, mode); ++ if (format != old_format) { ++ ++ /* turn off codec before changing format */ ++ mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); ++ mode &= ~CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); + ++ /* change format */ ++ twl4030_write(codec, REG_AUDIO_IF, format); ++ ++ /* turn on codec */ ++ mode |= CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ } + return 0; +} + @@ -399,14 +424,14 @@ index 0000000..c9eee19 + u8 rdac_reg = twl4030_read_reg_cache(codec, REG_ARXR2PGA); + + if (mute) { -+ printk(KERN_INFO "TWL4030 Audio Codec mute\n"); ++ /* printk(KERN_INFO "TWL4030 Audio Codec mute\n"); */ + twl4030_write(codec, REG_ARXL2PGA, 0x00); + twl4030_write(codec, REG_ARXR2PGA, 0x00); + twl4030_write_reg_cache(codec, REG_ARXL2PGA, ldac_reg); + twl4030_write_reg_cache(codec, REG_ARXR2PGA, rdac_reg); + } + else { -+ printk(KERN_INFO "TWL4030 Audio Codec unmute: %02x/%02x\n", ldac_reg, rdac_reg); ++ /* printk(KERN_INFO "TWL4030 Audio Codec unmute: %02x/%02x\n", ldac_reg, rdac_reg); */ + twl4030_write(codec, REG_ARXL2PGA, ldac_reg); + twl4030_write(codec, REG_ARXR2PGA, rdac_reg); + } @@ -419,19 +444,21 @@ index 0000000..c9eee19 +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct twl4030_priv *twl4030 = codec->private_data; ++ u8 mode, old_format, format; + -+ /* get current format */ -+ u8 format = twl4030_read_reg_cache(codec, REG_AUDIO_IF); ++ /* get format */ ++ old_format = twl4030_read_reg_cache(codec, REG_AUDIO_IF); ++ format = old_format; + + /* set master/slave audio interface */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: -+ printk(KERN_INFO "TWL4030 set dai fmt: master\n"); ++ /* printk(KERN_INFO "TWL4030 set dai fmt: master\n"); */ + format &= ~(AIF_SLAVE_EN); + format |= CLK256FS_EN; + break; + case SND_SOC_DAIFMT_CBS_CFS: -+ printk(KERN_INFO "TWL4030 set dai fmt: slave\n"); ++ /* printk(KERN_INFO "TWL4030 set dai fmt: slave\n"); */ + format &= ~(CLK256FS_EN); + format |= AIF_SLAVE_EN; + break; @@ -443,21 +470,26 @@ index 0000000..c9eee19 + format &= ~AIF_FORMAT; + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: -+ printk(KERN_INFO "TWL4030 set dai fmt: i2s\n"); ++ /* printk(KERN_INFO "TWL4030 set dai fmt: i2s\n"); */ + format |= AIF_FORMAT_CODEC; + break; + default: + return -EINVAL; + } + -+ /* turn off codec before changing format */ -+ twl4030_power_down(codec); ++ if (format != old_format) { + -+ /* change format */ -+ twl4030_write(codec, REG_AUDIO_IF, format); ++ /* turn off codec before changing format */ ++ mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); ++ mode &= ~CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); + -+ u8 mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); -+ twl4030_power_up(codec, mode); ++ /* change format */ ++ twl4030_write(codec, REG_AUDIO_IF, format); ++ ++ mode |= CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ } + + return 0; +} @@ -530,8 +562,6 @@ index 0000000..c9eee19 + + printk(KERN_INFO "TWL4030 Audio Codec init \n"); + -+ twl4030_init_chip(); -+ + codec->name = "twl4030"; + codec->owner = THIS_MODULE; + codec->read = twl4030_read_reg_cache; @@ -560,6 +590,9 @@ index 0000000..c9eee19 + goto card_err; + } + ++ twl4030_init_chip(); ++ twl4030_power_up(codec, APLL_RATE_44100 | OPT_MODE); ++ + return ret; + +card_err: @@ -580,8 +613,6 @@ index 0000000..c9eee19 + struct snd_soc_codec *codec; + struct twl4030_priv *twl4030; + -+ printk(KERN_INFO "TWL4030 Audio Codec probe\n"); -+ + codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); + if (codec == NULL) + return -ENOMEM; @@ -601,7 +632,6 @@ index 0000000..c9eee19 + twl4030_socdev = socdev; + twl4030_init(socdev); + -+ printk(KERN_INFO "TWL4030 Audio Codec probe exit\n"); + return 0; +} + @@ -630,10 +660,10 @@ index 0000000..c9eee19 +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/twl4030.h b/sound/soc/codecs/twl4030.h new file mode 100644 -index 0000000..af8eb43 +index 0000000..e126f96 --- /dev/null +++ b/sound/soc/codecs/twl4030.h -@@ -0,0 +1,125 @@ +@@ -0,0 +1,152 @@ +/* + * ALSA SoC TWL4030 codec driver + * @@ -722,7 +752,7 @@ index 0000000..af8eb43 + +/* Bitfield Definitions */ + -+/* CODEC_MODE Fields */ ++/* CODEC_MODE (0x01) Fields */ + +#define APLL_RATE 0xF0 +#define APLL_RATE_8000 0x00 @@ -738,7 +768,7 @@ index 0000000..af8eb43 +#define CODECPDZ 0x02 +#define OPT_MODE 0x01 + -+/* AUDIO_IF Fields */ ++/* AUDIO_IF (0x0E) Fields */ + +#define AIF_SLAVE_EN 0x80 +#define DATA_WIDTH 0x60 @@ -754,6 +784,33 @@ index 0000000..af8eb43 +#define CLK256FS_EN 0x02 +#define AIF_EN 0x01 + ++/* HS_GAIN_SET (0x23) Fields */ ++ ++#define HSR_GAIN 0x0c ++#define HSR_GAIN_PWR_DOWN 0x00 ++#define HSR_GAIN_PLUS_6DB 0x04 ++#define HSR_GAIN_0DB 0x08 ++#define HSR_GAIN_MINUS_6DB 0x0c ++#define HSL_GAIN 0x0c ++#define HSL_GAIN_PWR_DOWN 0x00 ++#define HSL_GAIN_PLUS_6DB 0x01 ++#define HSL_GAIN_0DB 0x02 ++#define HSL_GAIN_MINUS_6DB 0x03 ++ ++/* HS_POPN_SET (0x24) Fields */ ++ ++#define VMID_EN 0x40 ++#define EXTMUTE 0x20 ++#define RAMP_DELAY 0x1C ++#define RAMP_DELAY_20MS 0x00 ++#define RAMP_DELAY_40MS 0x04 ++#define RAMP_DELAY_81MS 0x08 ++#define RAMP_DELAY_161MS 0x0c ++#define RAMP_DELAY_323MS 0x10 ++#define RAMP_DELAY_645MS 0x14 ++#define RAMP_DELAY_1291MS 0x18 ++#define RAMP_DELAY_2581MS 0x1c ++#define RAMP_EN 0x02 + +extern struct snd_soc_codec_dai twl4030_dai; +extern struct snd_soc_codec_device soc_codec_dev_twl4030; @@ -801,10 +858,10 @@ index d8d8d58..638a240 100644 + diff --git a/sound/soc/omap/omap3beagle.c b/sound/soc/omap/omap3beagle.c new file mode 100644 -index 0000000..fb79938 +index 0000000..878f894 --- /dev/null +++ b/sound/soc/omap/omap3beagle.c -@@ -0,0 +1,180 @@ +@@ -0,0 +1,142 @@ +/* + * omap3beagle.c -- SoC audio for OMAP3 Beagle + * @@ -877,50 +934,12 @@ index 0000000..fb79938 + .hw_params = omap3beagle_hw_params, +}; + -+static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { -+ SND_SOC_DAPM_HP("Headphone Jack", NULL), -+ SND_SOC_DAPM_LINE("Line In", NULL), -+}; -+ -+static const char *audio_map[][3] = { -+ {"Headphone Jack", NULL, "HPLOUT"}, -+ {"Headphone Jack", NULL, "HPROUT"}, -+ -+ {"Line In", NULL, "Line In"}, -+ {"Line In", NULL, "Line In"}, -+}; -+ -+static int omap3beagle_twl4030_init(struct snd_soc_codec *codec) -+{ -+ int i; -+ -+ printk(KERN_INFO "OMAP3 Beagle TWL4030 SoC init\n"); -+ -+ /* Add omap3beagle specific widgets */ -+ for (i = 0; i < ARRAY_SIZE(twl4030_dapm_widgets); i++) -+ snd_soc_dapm_new_control(codec, &twl4030_dapm_widgets[i]); -+ -+ /* Set up omap3beagle specific audio path audio_map */ -+ for (i = 0; i < ARRAY_SIZE(audio_map); i++) -+ snd_soc_dapm_connect_input(codec, audio_map[i][0], -+ audio_map[i][1], audio_map[i][2]); -+ -+ /* always connected */ -+ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1); -+ snd_soc_dapm_set_endpoint(codec, "Line In", 1); -+ -+ snd_soc_dapm_sync_endpoints(codec); -+ -+ return 0; -+} -+ +/* Digital audio interface glue - connects codec <--> CPU */ +static struct snd_soc_dai_link omap3beagle_dai = { + .name = "TWL4030", + .stream_name = "TWL4030", + .cpu_dai = &omap_mcbsp_dai[0], + .codec_dai = &twl4030_dai, -+ .init = omap3beagle_twl4030_init, + .ops = &omap3beagle_ops, +}; + @@ -987,10 +1006,10 @@ index 0000000..fb79938 +MODULE_LICENSE("GPL"); diff --git a/sound/soc/omap/omap3evm.c b/sound/soc/omap/omap3evm.c new file mode 100644 -index 0000000..32d4f5d +index 0000000..a64c788 --- /dev/null +++ b/sound/soc/omap/omap3evm.c -@@ -0,0 +1,180 @@ +@@ -0,0 +1,142 @@ +/* + * omap3evm.c -- SoC audio for OMAP3 EVM + * @@ -1063,50 +1082,12 @@ index 0000000..32d4f5d + .hw_params = omap3evm_hw_params, +}; + -+static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { -+ SND_SOC_DAPM_HP("Headphone Jack", NULL), -+ SND_SOC_DAPM_LINE("Line In", NULL), -+}; -+ -+static const char *audio_map[][3] = { -+ {"Headphone Jack", NULL, "HPLOUT"}, -+ {"Headphone Jack", NULL, "HPROUT"}, -+ -+ {"Line In", NULL, "Line In"}, -+ {"Line In", NULL, "Line In"}, -+}; -+ -+static int omap3evm_twl4030_init(struct snd_soc_codec *codec) -+{ -+ int i; -+ -+ printk(KERN_INFO "OMAP3 EVM TWL4030 SoC init\n"); -+ -+ /* Add omap3evm specific widgets */ -+ for (i = 0; i < ARRAY_SIZE(twl4030_dapm_widgets); i++) -+ snd_soc_dapm_new_control(codec, &twl4030_dapm_widgets[i]); -+ -+ /* Set up omap3evm specific audio path audio_map */ -+ for (i = 0; i < ARRAY_SIZE(audio_map); i++) -+ snd_soc_dapm_connect_input(codec, audio_map[i][0], -+ audio_map[i][1], audio_map[i][2]); -+ -+ /* always connected */ -+ snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1); -+ snd_soc_dapm_set_endpoint(codec, "Line In", 1); -+ -+ snd_soc_dapm_sync_endpoints(codec); -+ -+ return 0; -+} -+ +/* Digital audio interface glue - connects codec <--> CPU */ +static struct snd_soc_dai_link omap3evm_dai = { + .name = "TWL4030", + .stream_name = "TWL4030", + .cpu_dai = &omap_mcbsp_dai[0], + .codec_dai = &twl4030_dai, -+ .init = omap3evm_twl4030_init, + .ops = &omap3evm_ops, +}; + diff --git a/packages/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch b/packages/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch index 28b1ef2214..cdc9447b4c 100644 --- a/packages/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch +++ b/packages/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch @@ -1,450 +1,450 @@ -From: "Rajendra Nayak" <rnayak@ti.com>
-To: <linux-omap@vger.kernel.org>
-Subject: [PATCH 01/02] OMAP3 CPUidle driver
-Date: Tue, 10 Jun 2008 12:39:00 +0530
-
-This patch adds the OMAP3 cpuidle driver. Irq enable/disable is done in the core cpuidle driver
-before it queries the governor for the next state.
-
-Signed-off-by: Rajendra Nayak <rnayak@ti.com>
-
----
- arch/arm/mach-omap2/Makefile | 2
- arch/arm/mach-omap2/cpuidle34xx.c | 293 ++++++++++++++++++++++++++++++++++++++
- arch/arm/mach-omap2/cpuidle34xx.h | 51 ++++++
- arch/arm/mach-omap2/pm34xx.c | 5
- drivers/cpuidle/cpuidle.c | 10 +
- 5 files changed, 359 insertions(+), 2 deletions(-)
-
-Index: linux-omap-2.6/arch/arm/mach-omap2/Makefile
-===================================================================
---- linux-omap-2.6.orig/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:33.855303920 +0530
-+++ linux-omap-2.6/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:39.569121361 +0530
-@@ -20,7 +20,7 @@ obj-y += pm.o
- obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
- obj-$(CONFIG_ARCH_OMAP2420) += sleep242x.o
- obj-$(CONFIG_ARCH_OMAP2430) += sleep243x.o
--obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
-+obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o
- obj-$(CONFIG_PM_DEBUG) += pm-debug.o
- endif
-
-Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c 2008-06-10 11:41:27.644820323 +0530
-@@ -0,0 +1,293 @@
-+/*
-+ * linux/arch/arm/mach-omap2/cpuidle34xx.c
-+ *
-+ * OMAP3 CPU IDLE Routines
-+ *
-+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
-+ * Rajendra Nayak <rnayak@ti.com>
-+ *
-+ * Copyright (C) 2007 Texas Instruments, Inc.
-+ * Karthik Dasu <karthik-dp@ti.com>
-+ *
-+ * Copyright (C) 2006 Nokia Corporation
-+ * Tony Lindgren <tony@atomide.com>
-+ *
-+ * Copyright (C) 2005 Texas Instruments, Inc.
-+ * Richard Woodruff <r-woodruff2@ti.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/cpuidle.h>
-+#include <asm/arch/pm.h>
-+#include <asm/arch/prcm.h>
-+#include <asm/arch/powerdomain.h>
-+#include <asm/arch/clockdomain.h>
-+#include <asm/arch/irqs.h>
-+#include "cpuidle34xx.h"
-+
-+#ifdef CONFIG_CPU_IDLE
-+
-+struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
-+struct omap3_processor_cx current_cx_state;
-+
-+static int omap3_idle_bm_check(void)
-+{
-+ /* Check for omap3_fclks_active() here once available */
-+ return 0;
-+}
-+
-+/* omap3_enter_idle - Programs OMAP3 to enter the specified state.
-+ * returns the total time during which the system was idle.
-+ */
-+static int omap3_enter_idle(struct cpuidle_device *dev,
-+ struct cpuidle_state *state)
-+{
-+ struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
-+ struct timespec ts_preidle, ts_postidle, ts_idle;
-+ struct powerdomain *mpu_pd, *core_pd, *per_pd, *neon_pd;
-+ int neon_pwrst;
-+
-+ current_cx_state = *cx;
-+
-+ if (cx->type == OMAP3_STATE_C0) {
-+ /* Do nothing for C0, not even a wfi */
-+ return 0;
-+ }
-+
-+ /* Used to keep track of the total time in idle */
-+ getnstimeofday(&ts_preidle);
-+
-+ mpu_pd = pwrdm_lookup("mpu_pwrdm");
-+ core_pd = pwrdm_lookup("core_pwrdm");
-+ per_pd = pwrdm_lookup("per_pwrdm");
-+ neon_pd = pwrdm_lookup("neon_pwrdm");
-+
-+ /* Reset previous power state registers */
-+ pwrdm_clear_all_prev_pwrst(mpu_pd);
-+ pwrdm_clear_all_prev_pwrst(neon_pd);
-+ pwrdm_clear_all_prev_pwrst(core_pd);
-+ pwrdm_clear_all_prev_pwrst(per_pd);
-+
-+ if (omap_irq_pending())
-+ return 0;
-+
-+ neon_pwrst = pwrdm_read_pwrst(neon_pd);
-+
-+ /* Program MPU/NEON to target state */
-+ if (cx->mpu_state < PWRDM_POWER_ON) {
-+ if (neon_pwrst == PWRDM_POWER_ON) {
-+ if (cx->mpu_state == PWRDM_POWER_RET)
-+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET);
-+ else if (cx->mpu_state == PWRDM_POWER_OFF)
-+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_OFF);
-+ }
-+ pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
-+ }
-+
-+ /* Program CORE to target state */
-+ if (cx->core_state < PWRDM_POWER_ON)
-+ pwrdm_set_next_pwrst(core_pd, cx->core_state);
-+
-+ /* Execute ARM wfi */
-+ omap_sram_idle();
-+
-+ /* Program MPU/NEON to ON */
-+ if (cx->mpu_state < PWRDM_POWER_ON) {
-+ if (neon_pwrst == PWRDM_POWER_ON)
-+ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_ON);
-+ pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON);
-+ }
-+
-+ if (cx->core_state < PWRDM_POWER_ON)
-+ pwrdm_set_next_pwrst(core_pd, PWRDM_POWER_ON);
-+
-+ getnstimeofday(&ts_postidle);
-+ ts_idle = timespec_sub(ts_postidle, ts_preidle);
-+ return timespec_to_ns(&ts_idle);
-+}
-+
-+/*
-+ * omap3_enter_idle_bm - enter function for states with CPUIDLE_FLAG_CHECK_BM
-+ *
-+ * This function checks for all the pre-requisites needed for OMAP3 to enter
-+ * CORE RET/OFF state. It then calls omap3_enter_idle to program the desired
-+ * C state.
-+ */
-+static int omap3_enter_idle_bm(struct cpuidle_device *dev,
-+ struct cpuidle_state *state)
-+{
-+ struct cpuidle_state *new_state = NULL;
-+ int i, j;
-+
-+ if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
-+
-+ /* Find current state in list */
-+ for (i = 0; i < OMAP3_MAX_STATES; i++)
-+ if (state == &dev->states[i])
-+ break;
-+ BUG_ON(i == OMAP3_MAX_STATES);
-+
-+ /* Back up to non 'CHECK_BM' state */
-+ for (j = i - 1; j > 0; j--) {
-+ struct cpuidle_state *s = &dev->states[j];
-+
-+ if (!(s->flags & CPUIDLE_FLAG_CHECK_BM)) {
-+ new_state = s;
-+ break;
-+ }
-+ }
-+
-+ pr_debug("%s: Bus activity: Entering %s (instead of %s)\n",
-+ __FUNCTION__, new_state->name, state->name);
-+ }
-+
-+ return omap3_enter_idle(dev, new_state ? : state);
-+}
-+
-+DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
-+
-+/* omap3_init_power_states - Initialises the OMAP3 specific C states.
-+ * Below is the desciption of each C state.
-+ *
-+ C0 . System executing code
-+ C1 . MPU WFI + Core active
-+ C2 . MPU CSWR + Core active
-+ C3 . MPU OFF + Core active
-+ C4 . MPU CSWR + Core CSWR
-+ C5 . MPU OFF + Core CSWR
-+ C6 . MPU OFF + Core OFF
-+ */
-+void omap_init_power_states(void)
-+{
-+ /* C0 . System executing code */
-+ omap3_power_states[0].valid = 1;
-+ omap3_power_states[0].type = OMAP3_STATE_C0;
-+ omap3_power_states[0].sleep_latency = 0;
-+ omap3_power_states[0].wakeup_latency = 0;
-+ omap3_power_states[0].threshold = 0;
-+ omap3_power_states[0].mpu_state = PWRDM_POWER_ON;
-+ omap3_power_states[0].core_state = PWRDM_POWER_ON;
-+ omap3_power_states[0].flags = CPUIDLE_FLAG_TIME_VALID |
-+ CPUIDLE_FLAG_SHALLOW;
-+
-+ /* C1 . MPU WFI + Core active */
-+ omap3_power_states[1].valid = 1;
-+ omap3_power_states[1].type = OMAP3_STATE_C1;
-+ omap3_power_states[1].sleep_latency = 10;
-+ omap3_power_states[1].wakeup_latency = 10;
-+ omap3_power_states[1].threshold = 30;
-+ omap3_power_states[1].mpu_state = PWRDM_POWER_ON;
-+ omap3_power_states[1].core_state = PWRDM_POWER_ON;
-+ omap3_power_states[1].flags = CPUIDLE_FLAG_TIME_VALID |
-+ CPUIDLE_FLAG_SHALLOW;
-+
-+ /* C2 . MPU CSWR + Core active */
-+ omap3_power_states[2].valid = 1;
-+ omap3_power_states[2].type = OMAP3_STATE_C2;
-+ omap3_power_states[2].sleep_latency = 50;
-+ omap3_power_states[2].wakeup_latency = 50;
-+ omap3_power_states[2].threshold = 300;
-+ omap3_power_states[2].mpu_state = PWRDM_POWER_RET;
-+ omap3_power_states[2].core_state = PWRDM_POWER_ON;
-+ omap3_power_states[2].flags = CPUIDLE_FLAG_TIME_VALID |
-+ CPUIDLE_FLAG_BALANCED;
-+
-+ /* C3 . MPU OFF + Core active */
-+ omap3_power_states[3].valid = 0;
-+ omap3_power_states[3].type = OMAP3_STATE_C3;
-+ omap3_power_states[3].sleep_latency = 1500;
-+ omap3_power_states[3].wakeup_latency = 1800;
-+ omap3_power_states[3].threshold = 4000;
-+ omap3_power_states[3].mpu_state = PWRDM_POWER_OFF;
-+ omap3_power_states[3].core_state = PWRDM_POWER_RET;
-+ omap3_power_states[3].flags = CPUIDLE_FLAG_TIME_VALID |
-+ CPUIDLE_FLAG_BALANCED;
-+
-+ /* C4 . MPU CSWR + Core CSWR*/
-+ omap3_power_states[4].valid = 1;
-+ omap3_power_states[4].type = OMAP3_STATE_C4;
-+ omap3_power_states[4].sleep_latency = 2500;
-+ omap3_power_states[4].wakeup_latency = 7500;
-+ omap3_power_states[4].threshold = 12000;
-+ omap3_power_states[4].mpu_state = PWRDM_POWER_RET;
-+ omap3_power_states[4].core_state = PWRDM_POWER_RET;
-+ omap3_power_states[4].flags = CPUIDLE_FLAG_TIME_VALID |
-+ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
-+
-+ /* C5 . MPU OFF + Core CSWR */
-+ omap3_power_states[5].valid = 0;
-+ omap3_power_states[5].type = OMAP3_STATE_C5;
-+ omap3_power_states[5].sleep_latency = 3000;
-+ omap3_power_states[5].wakeup_latency = 8500;
-+ omap3_power_states[5].threshold = 15000;
-+ omap3_power_states[5].mpu_state = PWRDM_POWER_OFF;
-+ omap3_power_states[5].core_state = PWRDM_POWER_RET;
-+ omap3_power_states[5].flags = CPUIDLE_FLAG_TIME_VALID |
-+ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;
-+
-+ /* C6 . MPU OFF + Core OFF */
-+ omap3_power_states[6].valid = 0;
-+ omap3_power_states[6].type = OMAP3_STATE_C6;
-+ omap3_power_states[6].sleep_latency = 10000;
-+ omap3_power_states[6].wakeup_latency = 30000;
-+ omap3_power_states[6].threshold = 300000;
-+ omap3_power_states[6].mpu_state = PWRDM_POWER_OFF;
-+ omap3_power_states[6].core_state = PWRDM_POWER_OFF;
-+ omap3_power_states[6].flags = CPUIDLE_FLAG_TIME_VALID |
-+ CPUIDLE_FLAG_DEEP | CPUIDLE_FLAG_CHECK_BM;
-+}
-+
-+struct cpuidle_driver omap3_idle_driver = {
-+ .name = "omap3_idle",
-+ .owner = THIS_MODULE,
-+};
-+/*
-+ * omap3_idle_init - Init routine for OMAP3 idle.
-+ * Registers the OMAP3 specific cpuidle driver with the cpuidle f/w
-+ * with the valid set of states.
-+ */
-+int omap3_idle_init(void)
-+{
-+ int i, count = 0;
-+ struct omap3_processor_cx *cx;
-+ struct cpuidle_state *state;
-+ struct cpuidle_device *dev;
-+
-+ omap_init_power_states();
-+ cpuidle_register_driver(&omap3_idle_driver);
-+
-+ dev = &per_cpu(omap3_idle_dev, smp_processor_id());
-+
-+ for (i = 0; i < OMAP3_MAX_STATES; i++) {
-+ cx = &omap3_power_states[i];
-+ state = &dev->states[count];
-+
-+ if (!cx->valid)
-+ continue;
-+ cpuidle_set_statedata(state, cx);
-+ state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
-+ state->target_residency = cx->threshold;
-+ state->flags = cx->flags;
-+ state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
-+ omap3_enter_idle_bm : omap3_enter_idle;
-+ sprintf(state->name, "C%d", count+1);
-+ count++;
-+ }
-+
-+ if (!count)
-+ return -EINVAL;
-+ dev->state_count = count;
-+
-+ if (cpuidle_register_device(dev)) {
-+ printk(KERN_ERR "%s: CPUidle register device failed\n",
-+ __FUNCTION__);
-+ return -EIO;
-+ }
-+
-+ return 0;
-+}
-+__initcall(omap3_idle_init);
-+#endif /* CONFIG_CPU_IDLE */
-Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h 2008-06-09 20:15:39.569121361 +0530
-@@ -0,0 +1,51 @@
-+/*
-+ * linux/arch/arm/mach-omap2/cpuidle34xx.h
-+ *
-+ * OMAP3 cpuidle structure definitions
-+ *
-+ * Copyright (C) 2007-2008 Texas Instruments, Inc.
-+ * Written by Rajendra Nayak <rnayak@ti.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
-+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
-+ *
-+ * History:
-+ *
-+ */
-+
-+#ifndef ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX
-+#define ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX
-+
-+#define OMAP3_MAX_STATES 7
-+#define OMAP3_STATE_C0 0 /* C0 - System executing code */
-+#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */
-+#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */
-+#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */
-+#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */
-+#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */
-+#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */
-+
-+extern void omap_sram_idle(void);
-+extern int omap3_irq_pending(void);
-+
-+struct omap3_processor_cx {
-+ u8 valid;
-+ u8 type;
-+ u32 sleep_latency;
-+ u32 wakeup_latency;
-+ u32 mpu_state;
-+ u32 core_state;
-+ u32 threshold;
-+ u32 flags;
-+};
-+
-+void omap_init_power_states(void);
-+int omap3_idle_init(void);
-+
-+#endif /* ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX */
-+
-Index: linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c
-===================================================================
---- linux-omap-2.6.orig/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:15:33.855303920 +0530
-+++ linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:16:20.976798343 +0530
-@@ -141,7 +141,7 @@ static irqreturn_t prcm_interrupt_handle
- return IRQ_HANDLED;
- }
-
--static void omap_sram_idle(void)
-+void omap_sram_idle(void)
- {
- /* Variable to tell what needs to be saved and restored
- * in omap_sram_idle*/
-@@ -156,6 +156,7 @@ static void omap_sram_idle(void)
-
- mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
- switch (mpu_next_state) {
-+ case PWRDM_POWER_ON:
- case PWRDM_POWER_RET:
- /* No need to save context */
- save_state = 0;
-@@ -386,7 +387,9 @@ int __init omap3_pm_init(void)
-
- prcm_setup_regs();
-
-+#ifndef CONFIG_CPU_IDLE
- pm_idle = omap3_pm_idle;
-+#endif
-
- err1:
- return ret;
-Index: linux-omap-2.6/drivers/cpuidle/cpuidle.c
-===================================================================
---- linux-omap-2.6.orig/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:33.856303888 +0530
-+++ linux-omap-2.6/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:39.570121329 +0530
-@@ -58,6 +58,11 @@ static void cpuidle_idle_call(void)
- return;
- }
-
-+#ifdef CONFIG_ARCH_OMAP3
-+ local_irq_disable();
-+ local_fiq_disable();
-+#endif
-+
- /* ask the governor for the next state */
- next_state = cpuidle_curr_governor->select(dev);
- if (need_resched())
-@@ -70,6 +75,11 @@ static void cpuidle_idle_call(void)
- target_state->time += (unsigned long long)dev->last_residency;
- target_state->usage++;
-
-+#ifdef CONFIG_ARCH_OMAP3
-+ local_irq_enable();
-+ local_fiq_enable();
-+#endif
-+
- /* give the governor an opportunity to reflect on the outcome */
- if (cpuidle_curr_governor->reflect)
- cpuidle_curr_governor->reflect(dev);
-
---
-To unsubscribe from this list: send the line "unsubscribe linux-omap" in
-the body of a message to majordomo@vger.kernel.org
-More majordomo info at http://vger.kernel.org/majordomo-info.html
-
+From: "Rajendra Nayak" <rnayak@ti.com> +To: <linux-omap@vger.kernel.org> +Subject: [PATCH 01/02] OMAP3 CPUidle driver +Date: Tue, 10 Jun 2008 12:39:00 +0530 + +This patch adds the OMAP3 cpuidle driver. Irq enable/disable is done in the core cpuidle driver +before it queries the governor for the next state. + +Signed-off-by: Rajendra Nayak <rnayak@ti.com> + +--- + arch/arm/mach-omap2/Makefile | 2 + arch/arm/mach-omap2/cpuidle34xx.c | 293 ++++++++++++++++++++++++++++++++++++++ + arch/arm/mach-omap2/cpuidle34xx.h | 51 ++++++ + arch/arm/mach-omap2/pm34xx.c | 5 + drivers/cpuidle/cpuidle.c | 10 + + 5 files changed, 359 insertions(+), 2 deletions(-) + +Index: linux-omap-2.6/arch/arm/mach-omap2/Makefile +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:33.855303920 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/Makefile 2008-06-09 20:15:39.569121361 +0530 +@@ -20,7 +20,7 @@ obj-y += pm.o + obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o + obj-$(CONFIG_ARCH_OMAP2420) += sleep242x.o + obj-$(CONFIG_ARCH_OMAP2430) += sleep243x.o +-obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o ++obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o + obj-$(CONFIG_PM_DEBUG) += pm-debug.o + endif + +Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c 2008-06-10 11:41:27.644820323 +0530 +@@ -0,0 +1,293 @@ ++/* ++ * linux/arch/arm/mach-omap2/cpuidle34xx.c ++ * ++ * OMAP3 CPU IDLE Routines ++ * ++ * Copyright (C) 2007-2008 Texas Instruments, Inc. ++ * Rajendra Nayak <rnayak@ti.com> ++ * ++ * Copyright (C) 2007 Texas Instruments, Inc. ++ * Karthik Dasu <karthik-dp@ti.com> ++ * ++ * Copyright (C) 2006 Nokia Corporation ++ * Tony Lindgren <tony@atomide.com> ++ * ++ * Copyright (C) 2005 Texas Instruments, Inc. ++ * Richard Woodruff <r-woodruff2@ti.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include <linux/cpuidle.h> ++#include <asm/arch/pm.h> ++#include <asm/arch/prcm.h> ++#include <asm/arch/powerdomain.h> ++#include <asm/arch/clockdomain.h> ++#include <asm/arch/irqs.h> ++#include "cpuidle34xx.h" ++ ++#ifdef CONFIG_CPU_IDLE ++ ++struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; ++struct omap3_processor_cx current_cx_state; ++ ++static int omap3_idle_bm_check(void) ++{ ++ /* Check for omap3_fclks_active() here once available */ ++ return 0; ++} ++ ++/* omap3_enter_idle - Programs OMAP3 to enter the specified state. ++ * returns the total time during which the system was idle. ++ */ ++static int omap3_enter_idle(struct cpuidle_device *dev, ++ struct cpuidle_state *state) ++{ ++ struct omap3_processor_cx *cx = cpuidle_get_statedata(state); ++ struct timespec ts_preidle, ts_postidle, ts_idle; ++ struct powerdomain *mpu_pd, *core_pd, *per_pd, *neon_pd; ++ int neon_pwrst; ++ ++ current_cx_state = *cx; ++ ++ if (cx->type == OMAP3_STATE_C0) { ++ /* Do nothing for C0, not even a wfi */ ++ return 0; ++ } ++ ++ /* Used to keep track of the total time in idle */ ++ getnstimeofday(&ts_preidle); ++ ++ mpu_pd = pwrdm_lookup("mpu_pwrdm"); ++ core_pd = pwrdm_lookup("core_pwrdm"); ++ per_pd = pwrdm_lookup("per_pwrdm"); ++ neon_pd = pwrdm_lookup("neon_pwrdm"); ++ ++ /* Reset previous power state registers */ ++ pwrdm_clear_all_prev_pwrst(mpu_pd); ++ pwrdm_clear_all_prev_pwrst(neon_pd); ++ pwrdm_clear_all_prev_pwrst(core_pd); ++ pwrdm_clear_all_prev_pwrst(per_pd); ++ ++ if (omap_irq_pending()) ++ return 0; ++ ++ neon_pwrst = pwrdm_read_pwrst(neon_pd); ++ ++ /* Program MPU/NEON to target state */ ++ if (cx->mpu_state < PWRDM_POWER_ON) { ++ if (neon_pwrst == PWRDM_POWER_ON) { ++ if (cx->mpu_state == PWRDM_POWER_RET) ++ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET); ++ else if (cx->mpu_state == PWRDM_POWER_OFF) ++ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_OFF); ++ } ++ pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state); ++ } ++ ++ /* Program CORE to target state */ ++ if (cx->core_state < PWRDM_POWER_ON) ++ pwrdm_set_next_pwrst(core_pd, cx->core_state); ++ ++ /* Execute ARM wfi */ ++ omap_sram_idle(); ++ ++ /* Program MPU/NEON to ON */ ++ if (cx->mpu_state < PWRDM_POWER_ON) { ++ if (neon_pwrst == PWRDM_POWER_ON) ++ pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_ON); ++ pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON); ++ } ++ ++ if (cx->core_state < PWRDM_POWER_ON) ++ pwrdm_set_next_pwrst(core_pd, PWRDM_POWER_ON); ++ ++ getnstimeofday(&ts_postidle); ++ ts_idle = timespec_sub(ts_postidle, ts_preidle); ++ return timespec_to_ns(&ts_idle); ++} ++ ++/* ++ * omap3_enter_idle_bm - enter function for states with CPUIDLE_FLAG_CHECK_BM ++ * ++ * This function checks for all the pre-requisites needed for OMAP3 to enter ++ * CORE RET/OFF state. It then calls omap3_enter_idle to program the desired ++ * C state. ++ */ ++static int omap3_enter_idle_bm(struct cpuidle_device *dev, ++ struct cpuidle_state *state) ++{ ++ struct cpuidle_state *new_state = NULL; ++ int i, j; ++ ++ if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { ++ ++ /* Find current state in list */ ++ for (i = 0; i < OMAP3_MAX_STATES; i++) ++ if (state == &dev->states[i]) ++ break; ++ BUG_ON(i == OMAP3_MAX_STATES); ++ ++ /* Back up to non 'CHECK_BM' state */ ++ for (j = i - 1; j > 0; j--) { ++ struct cpuidle_state *s = &dev->states[j]; ++ ++ if (!(s->flags & CPUIDLE_FLAG_CHECK_BM)) { ++ new_state = s; ++ break; ++ } ++ } ++ ++ pr_debug("%s: Bus activity: Entering %s (instead of %s)\n", ++ __FUNCTION__, new_state->name, state->name); ++ } ++ ++ return omap3_enter_idle(dev, new_state ? : state); ++} ++ ++DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); ++ ++/* omap3_init_power_states - Initialises the OMAP3 specific C states. ++ * Below is the desciption of each C state. ++ * ++ C0 . System executing code ++ C1 . MPU WFI + Core active ++ C2 . MPU CSWR + Core active ++ C3 . MPU OFF + Core active ++ C4 . MPU CSWR + Core CSWR ++ C5 . MPU OFF + Core CSWR ++ C6 . MPU OFF + Core OFF ++ */ ++void omap_init_power_states(void) ++{ ++ /* C0 . System executing code */ ++ omap3_power_states[0].valid = 1; ++ omap3_power_states[0].type = OMAP3_STATE_C0; ++ omap3_power_states[0].sleep_latency = 0; ++ omap3_power_states[0].wakeup_latency = 0; ++ omap3_power_states[0].threshold = 0; ++ omap3_power_states[0].mpu_state = PWRDM_POWER_ON; ++ omap3_power_states[0].core_state = PWRDM_POWER_ON; ++ omap3_power_states[0].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_SHALLOW; ++ ++ /* C1 . MPU WFI + Core active */ ++ omap3_power_states[1].valid = 1; ++ omap3_power_states[1].type = OMAP3_STATE_C1; ++ omap3_power_states[1].sleep_latency = 10; ++ omap3_power_states[1].wakeup_latency = 10; ++ omap3_power_states[1].threshold = 30; ++ omap3_power_states[1].mpu_state = PWRDM_POWER_ON; ++ omap3_power_states[1].core_state = PWRDM_POWER_ON; ++ omap3_power_states[1].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_SHALLOW; ++ ++ /* C2 . MPU CSWR + Core active */ ++ omap3_power_states[2].valid = 1; ++ omap3_power_states[2].type = OMAP3_STATE_C2; ++ omap3_power_states[2].sleep_latency = 50; ++ omap3_power_states[2].wakeup_latency = 50; ++ omap3_power_states[2].threshold = 300; ++ omap3_power_states[2].mpu_state = PWRDM_POWER_RET; ++ omap3_power_states[2].core_state = PWRDM_POWER_ON; ++ omap3_power_states[2].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_BALANCED; ++ ++ /* C3 . MPU OFF + Core active */ ++ omap3_power_states[3].valid = 0; ++ omap3_power_states[3].type = OMAP3_STATE_C3; ++ omap3_power_states[3].sleep_latency = 1500; ++ omap3_power_states[3].wakeup_latency = 1800; ++ omap3_power_states[3].threshold = 4000; ++ omap3_power_states[3].mpu_state = PWRDM_POWER_OFF; ++ omap3_power_states[3].core_state = PWRDM_POWER_RET; ++ omap3_power_states[3].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_BALANCED; ++ ++ /* C4 . MPU CSWR + Core CSWR*/ ++ omap3_power_states[4].valid = 1; ++ omap3_power_states[4].type = OMAP3_STATE_C4; ++ omap3_power_states[4].sleep_latency = 2500; ++ omap3_power_states[4].wakeup_latency = 7500; ++ omap3_power_states[4].threshold = 12000; ++ omap3_power_states[4].mpu_state = PWRDM_POWER_RET; ++ omap3_power_states[4].core_state = PWRDM_POWER_RET; ++ omap3_power_states[4].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM; ++ ++ /* C5 . MPU OFF + Core CSWR */ ++ omap3_power_states[5].valid = 0; ++ omap3_power_states[5].type = OMAP3_STATE_C5; ++ omap3_power_states[5].sleep_latency = 3000; ++ omap3_power_states[5].wakeup_latency = 8500; ++ omap3_power_states[5].threshold = 15000; ++ omap3_power_states[5].mpu_state = PWRDM_POWER_OFF; ++ omap3_power_states[5].core_state = PWRDM_POWER_RET; ++ omap3_power_states[5].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM; ++ ++ /* C6 . MPU OFF + Core OFF */ ++ omap3_power_states[6].valid = 0; ++ omap3_power_states[6].type = OMAP3_STATE_C6; ++ omap3_power_states[6].sleep_latency = 10000; ++ omap3_power_states[6].wakeup_latency = 30000; ++ omap3_power_states[6].threshold = 300000; ++ omap3_power_states[6].mpu_state = PWRDM_POWER_OFF; ++ omap3_power_states[6].core_state = PWRDM_POWER_OFF; ++ omap3_power_states[6].flags = CPUIDLE_FLAG_TIME_VALID | ++ CPUIDLE_FLAG_DEEP | CPUIDLE_FLAG_CHECK_BM; ++} ++ ++struct cpuidle_driver omap3_idle_driver = { ++ .name = "omap3_idle", ++ .owner = THIS_MODULE, ++}; ++/* ++ * omap3_idle_init - Init routine for OMAP3 idle. ++ * Registers the OMAP3 specific cpuidle driver with the cpuidle f/w ++ * with the valid set of states. ++ */ ++int omap3_idle_init(void) ++{ ++ int i, count = 0; ++ struct omap3_processor_cx *cx; ++ struct cpuidle_state *state; ++ struct cpuidle_device *dev; ++ ++ omap_init_power_states(); ++ cpuidle_register_driver(&omap3_idle_driver); ++ ++ dev = &per_cpu(omap3_idle_dev, smp_processor_id()); ++ ++ for (i = 0; i < OMAP3_MAX_STATES; i++) { ++ cx = &omap3_power_states[i]; ++ state = &dev->states[count]; ++ ++ if (!cx->valid) ++ continue; ++ cpuidle_set_statedata(state, cx); ++ state->exit_latency = cx->sleep_latency + cx->wakeup_latency; ++ state->target_residency = cx->threshold; ++ state->flags = cx->flags; ++ state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ? ++ omap3_enter_idle_bm : omap3_enter_idle; ++ sprintf(state->name, "C%d", count+1); ++ count++; ++ } ++ ++ if (!count) ++ return -EINVAL; ++ dev->state_count = count; ++ ++ if (cpuidle_register_device(dev)) { ++ printk(KERN_ERR "%s: CPUidle register device failed\n", ++ __FUNCTION__); ++ return -EIO; ++ } ++ ++ return 0; ++} ++__initcall(omap3_idle_init); ++#endif /* CONFIG_CPU_IDLE */ +Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h 2008-06-09 20:15:39.569121361 +0530 +@@ -0,0 +1,51 @@ ++/* ++ * linux/arch/arm/mach-omap2/cpuidle34xx.h ++ * ++ * OMAP3 cpuidle structure definitions ++ * ++ * Copyright (C) 2007-2008 Texas Instruments, Inc. ++ * Written by Rajendra Nayak <rnayak@ti.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED ++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. ++ * ++ * History: ++ * ++ */ ++ ++#ifndef ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX ++#define ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX ++ ++#define OMAP3_MAX_STATES 7 ++#define OMAP3_STATE_C0 0 /* C0 - System executing code */ ++#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */ ++#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */ ++#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */ ++#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */ ++#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */ ++#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */ ++ ++extern void omap_sram_idle(void); ++extern int omap3_irq_pending(void); ++ ++struct omap3_processor_cx { ++ u8 valid; ++ u8 type; ++ u32 sleep_latency; ++ u32 wakeup_latency; ++ u32 mpu_state; ++ u32 core_state; ++ u32 threshold; ++ u32 flags; ++}; ++ ++void omap_init_power_states(void); ++int omap3_idle_init(void); ++ ++#endif /* ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX */ ++ +Index: linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c +=================================================================== +--- linux-omap-2.6.orig/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:15:33.855303920 +0530 ++++ linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c 2008-06-09 20:16:20.976798343 +0530 +@@ -141,7 +141,7 @@ static irqreturn_t prcm_interrupt_handle + return IRQ_HANDLED; + } + +-static void omap_sram_idle(void) ++void omap_sram_idle(void) + { + /* Variable to tell what needs to be saved and restored + * in omap_sram_idle*/ +@@ -156,6 +156,7 @@ static void omap_sram_idle(void) + + mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); + switch (mpu_next_state) { ++ case PWRDM_POWER_ON: + case PWRDM_POWER_RET: + /* No need to save context */ + save_state = 0; +@@ -386,7 +387,9 @@ int __init omap3_pm_init(void) + + prcm_setup_regs(); + ++#ifndef CONFIG_CPU_IDLE + pm_idle = omap3_pm_idle; ++#endif + + err1: + return ret; +Index: linux-omap-2.6/drivers/cpuidle/cpuidle.c +=================================================================== +--- linux-omap-2.6.orig/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:33.856303888 +0530 ++++ linux-omap-2.6/drivers/cpuidle/cpuidle.c 2008-06-09 20:15:39.570121329 +0530 +@@ -58,6 +58,11 @@ static void cpuidle_idle_call(void) + return; + } + ++#ifdef CONFIG_ARCH_OMAP3 ++ local_irq_disable(); ++ local_fiq_disable(); ++#endif ++ + /* ask the governor for the next state */ + next_state = cpuidle_curr_governor->select(dev); + if (need_resched()) +@@ -70,6 +75,11 @@ static void cpuidle_idle_call(void) + target_state->time += (unsigned long long)dev->last_residency; + target_state->usage++; + ++#ifdef CONFIG_ARCH_OMAP3 ++ local_irq_enable(); ++ local_fiq_enable(); ++#endif ++ + /* give the governor an opportunity to reflect on the outcome */ + if (cpuidle_curr_governor->reflect) + cpuidle_curr_governor->reflect(dev); + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/packages/linux/linux-omap2-git/omap3evm/0002-omap3-cpuidle.patch b/packages/linux/linux-omap2-git/omap3evm/0002-omap3-cpuidle.patch index c17c690fe1..d35fd47567 100644 --- a/packages/linux/linux-omap2-git/omap3evm/0002-omap3-cpuidle.patch +++ b/packages/linux/linux-omap2-git/omap3evm/0002-omap3-cpuidle.patch @@ -1,88 +1,88 @@ -From: "Rajendra Nayak" <rnayak@ti.com>
-To: <linux-omap@vger.kernel.org>
-Subject: [PATCH 02/02] Kconfig changes
-Date: Tue, 10 Jun 2008 12:39:02 +0530
-
-Updates the CPUidle Kconfig
-
-Signed-off-by: Rajendra Nayak <rnayak@ti.com>
-
----
- arch/arm/Kconfig | 10 ++++++++++
- drivers/cpuidle/Kconfig | 28 ++++++++++++++++++++++------
- 2 files changed, 32 insertions(+), 6 deletions(-)
-
-Index: linux-omap-2.6/arch/arm/Kconfig
-===================================================================
---- linux-omap-2.6.orig/arch/arm/Kconfig 2008-06-10 11:43:10.790502713 +0530
-+++ linux-omap-2.6/arch/arm/Kconfig 2008-06-10 11:43:38.701604549 +0530
-@@ -954,6 +954,16 @@ config ATAGS_PROC
-
- endmenu
-
-+if (ARCH_OMAP)
-+
-+menu "CPUIdle"
-+
-+source "drivers/cpuidle/Kconfig"
-+
-+endmenu
-+
-+endif
-+
- if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)
-
- menu "CPU Frequency scaling"
-Index: linux-omap-2.6/drivers/cpuidle/Kconfig
-===================================================================
---- linux-omap-2.6.orig/drivers/cpuidle/Kconfig 2008-06-10 11:43:10.790502713 +0530
-+++ linux-omap-2.6/drivers/cpuidle/Kconfig 2008-06-10 12:06:36.139332151 +0530
-@@ -1,20 +1,36 @@
-+menu "CPU idle PM support"
-
- config CPU_IDLE
- bool "CPU idle PM support"
-- default ACPI
-+ default n
- help
- CPU idle is a generic framework for supporting software-controlled
- idle processor power management. It includes modular cross-platform
- governors that can be swapped during runtime.
-
-- If you're using an ACPI-enabled platform, you should say Y here.
-+ If you're using a mobile platform that supports CPU idle PM (e.g.
-+ an ACPI-capable notebook), you should say Y here.
-+
-+if CPU_IDLE
-+
-+comment "Governors"
-
- config CPU_IDLE_GOV_LADDER
-- bool
-+ bool "ladder"
- depends on CPU_IDLE
-- default y
-+ default n
-
- config CPU_IDLE_GOV_MENU
-- bool
-+ bool "menu"
- depends on CPU_IDLE && NO_HZ
-- default y
-+ default n
-+ help
-+ This cpuidle governor evaluates all available states and chooses the
-+ deepest state that meets all of the following constraints: BM activity,
-+ expected time until next timer interrupt, and last break event time
-+ delta. It is designed to minimize power consumption. Currently
-+ dynticks is required.
-+
-+endif # CPU_IDLE
-+
-+endmenu
-
---
-To unsubscribe from this list: send the line "unsubscribe linux-omap" in
-the body of a message to majordomo@vger.kernel.org
-More majordomo info at http://vger.kernel.org/majordomo-info.html
-
+From: "Rajendra Nayak" <rnayak@ti.com> +To: <linux-omap@vger.kernel.org> +Subject: [PATCH 02/02] Kconfig changes +Date: Tue, 10 Jun 2008 12:39:02 +0530 + +Updates the CPUidle Kconfig + +Signed-off-by: Rajendra Nayak <rnayak@ti.com> + +--- + arch/arm/Kconfig | 10 ++++++++++ + drivers/cpuidle/Kconfig | 28 ++++++++++++++++++++++------ + 2 files changed, 32 insertions(+), 6 deletions(-) + +Index: linux-omap-2.6/arch/arm/Kconfig +=================================================================== +--- linux-omap-2.6.orig/arch/arm/Kconfig 2008-06-10 11:43:10.790502713 +0530 ++++ linux-omap-2.6/arch/arm/Kconfig 2008-06-10 11:43:38.701604549 +0530 +@@ -954,6 +954,16 @@ config ATAGS_PROC + + endmenu + ++if (ARCH_OMAP) ++ ++menu "CPUIdle" ++ ++source "drivers/cpuidle/Kconfig" ++ ++endmenu ++ ++endif ++ + if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA) + + menu "CPU Frequency scaling" +Index: linux-omap-2.6/drivers/cpuidle/Kconfig +=================================================================== +--- linux-omap-2.6.orig/drivers/cpuidle/Kconfig 2008-06-10 11:43:10.790502713 +0530 ++++ linux-omap-2.6/drivers/cpuidle/Kconfig 2008-06-10 12:06:36.139332151 +0530 +@@ -1,20 +1,36 @@ ++menu "CPU idle PM support" + + config CPU_IDLE + bool "CPU idle PM support" +- default ACPI ++ default n + help + CPU idle is a generic framework for supporting software-controlled + idle processor power management. It includes modular cross-platform + governors that can be swapped during runtime. + +- If you're using an ACPI-enabled platform, you should say Y here. ++ If you're using a mobile platform that supports CPU idle PM (e.g. ++ an ACPI-capable notebook), you should say Y here. ++ ++if CPU_IDLE ++ ++comment "Governors" + + config CPU_IDLE_GOV_LADDER +- bool ++ bool "ladder" + depends on CPU_IDLE +- default y ++ default n + + config CPU_IDLE_GOV_MENU +- bool ++ bool "menu" + depends on CPU_IDLE && NO_HZ +- default y ++ default n ++ help ++ This cpuidle governor evaluates all available states and chooses the ++ deepest state that meets all of the following constraints: BM activity, ++ expected time until next timer interrupt, and last break event time ++ delta. It is designed to minimize power consumption. Currently ++ dynticks is required. ++ ++endif # CPU_IDLE ++ ++endmenu + +-- +To unsubscribe from this list: send the line "unsubscribe linux-omap" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/packages/linux/linux-omap2-git/omap3evm/defconfig b/packages/linux/linux-omap2-git/omap3evm/defconfig index f74cef90ee..e61fad48d9 100644 --- a/packages/linux/linux-omap2-git/omap3evm/defconfig +++ b/packages/linux/linux-omap2-git/omap3evm/defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.26-rc3-omap1 -# Wed May 21 07:38:41 2008 +# Linux kernel version: 2.6.26-rc5-omap1 +# Sun Jun 15 21:58:01 2008 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -42,7 +42,8 @@ CONFIG_BSD_PROCESS_ACCT=y # CONFIG_BSD_PROCESS_ACCT_V3 is not set # CONFIG_TASKSTATS is not set # CONFIG_AUDIT is not set -# CONFIG_IKCONFIG is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CGROUPS is not set CONFIG_GROUP_SCHED=y @@ -170,9 +171,9 @@ CONFIG_ARCH_OMAP3=y # # OMAP Feature Selections # -CONFIG_OMAP_DEBUG_SRAM_PATCH=y # CONFIG_OMAP_DEBUG_POWERDOMAIN is not set # CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set +# CONFIG_OMAP_SMARTREFLEX is not set # CONFIG_OMAP_RESET_CLOCKS is not set CONFIG_OMAP_BOOT_TAG=y CONFIG_OMAP_BOOT_REASON=y @@ -186,9 +187,9 @@ CONFIG_OMAP_MCBSP=y CONFIG_OMAP_32K_TIMER=y CONFIG_OMAP_32K_TIMER_HZ=128 CONFIG_OMAP_DM_TIMER=y -# CONFIG_OMAP_LL_DEBUG_UART1 is not set +CONFIG_OMAP_LL_DEBUG_UART1=y # CONFIG_OMAP_LL_DEBUG_UART2 is not set -CONFIG_OMAP_LL_DEBUG_UART3=y +# CONFIG_OMAP_LL_DEBUG_UART3 is not set CONFIG_ARCH_OMAP34XX=y CONFIG_ARCH_OMAP3430=y @@ -232,10 +233,6 @@ CONFIG_ARM_THUMB=y # CONFIG_ARM_THUMBEE is not set # CONFIG_CPU_ICACHE_DISABLE is not set # CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_LOCKDOWN_TO_64K_L2 is not set -# CONFIG_CPU_LOCKDOWN_TO_128K_L2 is not set -CONFIG_CPU_LOCKDOWN_TO_256K_L2=y -# CONFIG_CPU_L2CACHE_DISABLE is not set # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_HAS_TLS_REG=y # CONFIG_OUTER_CACHE is not set @@ -257,7 +254,7 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_PREEMPT is not set CONFIG_HZ=128 CONFIG_AEABI=y -CONFIG_OABI_COMPAT=y +# CONFIG_OABI_COMPAT is not set # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y @@ -286,6 +283,15 @@ CONFIG_CMDLINE=" quiet " # CONFIG_KEXEC is not set # +# CPUIdle +# + +# +# CPU idle PM support +# +# CONFIG_CPU_IDLE is not set + +# # CPU Frequency scaling # # CONFIG_CPU_FREQ is not set @@ -297,9 +303,6 @@ CONFIG_CMDLINE=" quiet " # # At least one emulation must be selected # -CONFIG_FPE_NWFPE=y -# CONFIG_FPE_NWFPE_XP is not set -# CONFIG_FPE_FASTFPE is not set CONFIG_VFP=y CONFIG_VFPv3=y # CONFIG_NEON is not set @@ -593,9 +596,42 @@ CONFIG_HAVE_IDE=y # SCSI device support # # CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set # CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set # CONFIG_ATA is not set # CONFIG_MD is not set CONFIG_NETDEVICES=y @@ -697,7 +733,10 @@ CONFIG_INPUT=y # # Userland interfaces # -# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVBUG=y @@ -714,7 +753,18 @@ CONFIG_INPUT_KEYBOARD=y # CONFIG_KEYBOARD_STOWAWAY is not set # CONFIG_KEYBOARD_LM8323 is not set # CONFIG_KEYBOARD_GPIO is not set -# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y @@ -737,7 +787,10 @@ CONFIG_TOUCHSCREEN_ADS7846=y # # Hardware I/O ports # -# CONFIG_SERIO is not set +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set # CONFIG_GAMEPORT is not set # @@ -950,9 +1003,17 @@ CONFIG_DUMMY_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y # CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y +CONFIG_FONTS=y +# CONFIG_FONT_8x8 is not set CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set # CONFIG_LOGO is not set # @@ -966,9 +1027,11 @@ CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y # CONFIG_SND_SEQUENCER is not set CONFIG_SND_OSSEMUL=y -# CONFIG_SND_MIXER_OSS is not set +CONFIG_SND_MIXER_OSS=y CONFIG_SND_PCM_OSS=y CONFIG_SND_PCM_OSS_PLUGINS=y # CONFIG_SND_DYNAMIC_MINORS is not set @@ -1003,7 +1066,7 @@ CONFIG_SND_PCM_XRUN_DEBUG=y # # USB devices # -# CONFIG_SND_USB_AUDIO is not set +CONFIG_SND_USB_AUDIO=y # CONFIG_SND_USB_CAIAQ is not set # @@ -1027,8 +1090,6 @@ CONFIG_SND_SOC_TWL4030=y # Open Sound System # CONFIG_SOUND_PRIME=y -# CONFIG_SOUND_MSNDCLAS is not set -# CONFIG_SOUND_MSNDPIN is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set @@ -1077,7 +1138,7 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_SL811_HCD=y CONFIG_USB_R8A66597_HCD=y -CONFIG_USB_MUSB_HDRC=m +CONFIG_USB_MUSB_HDRC=y CONFIG_USB_MUSB_SOC=y # @@ -1086,7 +1147,6 @@ CONFIG_USB_MUSB_SOC=y CONFIG_USB_MUSB_HOST=y # CONFIG_USB_MUSB_PERIPHERAL is not set # CONFIG_USB_MUSB_OTG is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set CONFIG_USB_MUSB_HDRC_HCD=y # CONFIG_MUSB_PIO_ONLY is not set CONFIG_USB_INVENTRA_DMA=y @@ -1098,6 +1158,7 @@ CONFIG_USB_MUSB_LOGLEVEL=0 # # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1106,12 +1167,27 @@ CONFIG_USB_MUSB_LOGLEVEL=0 # # may also be needed; see USB_STORAGE Help for more information # -# CONFIG_USB_LIBUSUAL is not set +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +CONFIG_USB_LIBUSUAL=y # # USB Imaging devices # # CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set CONFIG_USB_MON=y # @@ -1142,34 +1218,8 @@ CONFIG_USB_MON=y # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set -CONFIG_USB_GADGET=m -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_PXA2XX is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LH7A40X is not set -CONFIG_USB_GADGET_OMAP=y -CONFIG_USB_OMAP=m -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -# CONFIG_USB_GADGET_DUALSPEED is not set -# CONFIG_USB_ZERO is not set -CONFIG_USB_ETH=m -CONFIG_USB_ETH_RNDIS=y -CONFIG_USB_GADGETFS=m -CONFIG_USB_FILE_STORAGE=m -# CONFIG_USB_FILE_STORAGE_TEST is not set -CONFIG_USB_G_SERIAL=m -# CONFIG_USB_MIDI_GADGET is not set -CONFIG_USB_G_PRINTER=m +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_GADGET is not set CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set CONFIG_MMC_UNSAFE_RESUME=y @@ -1180,6 +1230,7 @@ CONFIG_MMC_UNSAFE_RESUME=y CONFIG_MMC_BLOCK=y CONFIG_MMC_BLOCK_BOUNCE=y CONFIG_SDIO_UART=m +# CONFIG_MMC_TEST is not set # # MMC/SD Host Controller Drivers @@ -1259,7 +1310,7 @@ CONFIG_EXT3_FS=y CONFIG_JBD=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set +CONFIG_FS_POSIX_ACL=y CONFIG_XFS_FS=m CONFIG_XFS_QUOTA=y # CONFIG_XFS_POSIX_ACL is not set @@ -1327,12 +1378,14 @@ CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y # CONFIG_JFFS2_FS_WBUF_VERIFY is not set CONFIG_JFFS2_SUMMARY=y -# CONFIG_JFFS2_FS_XATTR is not set +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y CONFIG_JFFS2_COMPRESSION_OPTIONS=y CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_LZO=y CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set +CONFIG_JFFS2_RUBIN=y # CONFIG_JFFS2_CMODE_NONE is not set CONFIG_JFFS2_CMODE_PRIORITY=y # CONFIG_JFFS2_CMODE_SIZE is not set @@ -1461,7 +1514,7 @@ CONFIG_FRAME_POINTER=y # CONFIG_DEBUG_USER is not set # CONFIG_DEBUG_ERRORS is not set # CONFIG_DEBUG_STACK_USAGE is not set -CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_LL is not set # CONFIG_DEBUG_ICEDCC is not set # @@ -1561,6 +1614,8 @@ CONFIG_CRC32=y CONFIG_LIBCRC32C=y CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y diff --git a/packages/linux/linux-omap2-git/omap3evm/no-empty-flash-warnings.patch b/packages/linux/linux-omap2-git/omap3evm/no-empty-flash-warnings.patch new file mode 100644 index 0000000000..ab344b0449 --- /dev/null +++ b/packages/linux/linux-omap2-git/omap3evm/no-empty-flash-warnings.patch @@ -0,0 +1,15 @@ +diff --git a/fs/jffs2/scan.c b/fs/jffs2/scan.c +index 1d437de..33b3feb 100644 +--- a/fs/jffs2/scan.c ++++ b/fs/jffs2/scan.c +@@ -647,8 +647,8 @@ scan_more: + inbuf_ofs = ofs - buf_ofs; + while (inbuf_ofs < scan_end) { + if (unlikely(*(uint32_t *)(&buf[inbuf_ofs]) != 0xffffffff)) { +- printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n", +- empty_start, ofs); ++// printk(KERN_WARNING "Empty flash at 0x%08x ends at 0x%08x\n", ++// empty_start, ofs); + if ((err = jffs2_scan_dirty_space(c, jeb, ofs-empty_start))) + return err; + goto scan_more; diff --git a/packages/linux/linux-omap2-git/omap3evm/soc.patch b/packages/linux/linux-omap2-git/omap3evm/soc.patch new file mode 100644 index 0000000000..f4cce21ca7 --- /dev/null +++ b/packages/linux/linux-omap2-git/omap3evm/soc.patch @@ -0,0 +1,1154 @@ +diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig +index 3903ab7..468536d 100644 +--- a/sound/soc/codecs/Kconfig ++++ b/sound/soc/codecs/Kconfig +@@ -44,3 +44,7 @@ config SND_SOC_CS4270_VD33_ERRATA + config SND_SOC_TLV320AIC3X + tristate + depends on SND_SOC && I2C ++ ++config SND_SOC_TWL4030 ++ tristate ++ depends on SND_SOC && I2C +diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile +index 4e1314c..d2c0b12 100644 +--- a/sound/soc/codecs/Makefile ++++ b/sound/soc/codecs/Makefile +@@ -6,6 +6,7 @@ snd-soc-wm9712-objs := wm9712.o + snd-soc-wm9713-objs := wm9713.o + snd-soc-cs4270-objs := cs4270.o + snd-soc-tlv320aic3x-objs := tlv320aic3x.o ++snd-soc-twl4030-objs := twl4030.o + + obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o + obj-$(CONFIG_SND_SOC_WM8731) += snd-soc-wm8731.o +@@ -15,3 +16,4 @@ obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o + obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o + obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o + obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o ++obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o +diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c +new file mode 100644 +index 0000000..eb8370c +--- /dev/null ++++ b/sound/soc/codecs/twl4030.c +@@ -0,0 +1,625 @@ ++/* ++ * ALSA SoC TWL4030 codec driver ++ * ++ * Author: Steve Sakoman, <steve@sakoman.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include <linux/module.h> ++#include <linux/moduleparam.h> ++#include <linux/init.h> ++#include <linux/delay.h> ++#include <linux/pm.h> ++#include <linux/i2c.h> ++#include <linux/platform_device.h> ++#include <linux/i2c/twl4030.h> ++#include <sound/core.h> ++#include <sound/pcm.h> ++#include <sound/pcm_params.h> ++#include <sound/soc.h> ++#include <sound/soc-dapm.h> ++#include <sound/initval.h> ++ ++#include "twl4030.h" ++ ++/* ++ * twl4030 register cache & default register settings ++ */ ++static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = { ++ 0x00, // this register not used ++ 0x93, // REG_CODEC_MODE (0x1) ++ 0xc3, // REG_OPTION (0x2) ++ 0x00, // REG_UNKNOWN (0x3) ++ 0x00, // REG_MICBIAS_CTL (0x4) ++ 0x34, // REG_ANAMICL (0x5) ++ 0x14, // REG_ANAMICR (0x6) ++ 0x0a, // REG_AVADC_CTL (0x7) ++ 0x00, // REG_ADCMICSEL (0x8) ++ 0x00, // REG_DIGMIXING (0x9) ++ 0x0c, // REG_ATXL1PGA (0xA) ++ 0x0c, // REG_ATXR1PGA (0xB) ++ 0x00, // REG_AVTXL2PGA (0xC) ++ 0x00, // REG_AVTXR2PGA (0xD) ++ 0x01, // REG_AUDIO_IF (0xE) ++ 0x00, // REG_VOICE_IF (0xF) ++ 0x00, // REG_ARXR1PGA (0x10) ++ 0x00, // REG_ARXL1PGA (0x11) ++ 0x6c, // REG_ARXR2PGA (0x12) ++ 0x6c, // REG_ARXL2PGA (0x13) ++ 0x00, // REG_VRXPGA (0x14) ++ 0x00, // REG_VSTPGA (0x15) ++ 0x00, // REG_VRX2ARXPGA (0x16) ++ 0x0c, // REG_AVDAC_CTL (0x17) ++ 0x00, // REG_ARX2VTXPGA (0x18) ++ 0x00, // REG_ARXL1_APGA_CTL (0x19) ++ 0x00, // REG_ARXR1_APGA_CTL (0x1A) ++ 0x4b, // REG_ARXL2_APGA_CTL (0x1B) ++ 0x4b, // REG_ARXR2_APGA_CTL (0x1C) ++ 0x00, // REG_ATX2ARXPGA (0x1D) ++ 0x00, // REG_BT_IF (0x1E) ++ 0x00, // REG_BTPGA (0x1F) ++ 0x00, // REG_BTSTPGA (0x20) ++ 0x00, // REG_EAR_CTL (0x21) ++ 0x24, // REG_HS_SEL (0x22) ++ 0x0a, // REG_HS_GAIN_SET (0x23) ++ 0x00, // REG_HS_POPN_SET (0x24) ++ 0x00, // REG_PREDL_CTL (0x25) ++ 0x00, // REG_PREDR_CTL (0x26) ++ 0x00, // REG_PRECKL_CTL (0x27) ++ 0x00, // REG_PRECKR_CTL (0x28) ++ 0x00, // REG_HFL_CTL (0x29) ++ 0x00, // REG_HFR_CTL (0x2A) ++ 0x00, // REG_ALC_CTL (0x2B) ++ 0x00, // REG_ALC_SET1 (0x2C) ++ 0x00, // REG_ALC_SET2 (0x2D) ++ 0x00, // REG_BOOST_CTL (0x2E) ++ 0x01, // REG_SOFTVOL_CTL (0x2F) ++ 0x00, // REG_DTMF_FREQSEL (0x30) ++ 0x00, // REG_DTMF_TONEXT1H (0x31) ++ 0x00, // REG_DTMF_TONEXT1L (0x32) ++ 0x00, // REG_DTMF_TONEXT2H (0x33) ++ 0x00, // REG_DTMF_TONEXT2L (0x34) ++ 0x00, // REG_DTMF_TONOFF (0x35) ++ 0x00, // REG_DTMF_WANONOFF (0x36) ++ 0x00, // REG_I2S_RX_SCRAMBLE_H (0x37) ++ 0x00, // REG_I2S_RX_SCRAMBLE_M (0x38) ++ 0x00, // REG_I2S_RX_SCRAMBLE_L (0x39) ++ 0x16, // REG_APLL_CTL (0x3A) ++ 0x00, // REG_DTMF_CTL (0x3B) ++ 0x00, // REG_DTMF_PGA_CTL2 (0x3C) ++ 0x00, // REG_DTMF_PGA_CTL1 (0x3D) ++ 0x00, // REG_MISC_SET_1 (0x3E) ++ 0x00, // REG_PCMBTMUX (0x3F) ++ 0x00, // REG_RX_PATH_SEL (0x43) ++ 0x00, // REG_VDL_APGA_CTL (0x44) ++ 0x00, // REG_VIBRA_CTL (0x45) ++ 0x00, // REG_VIBRA_SET (0x46) ++ 0x00, // REG_VIBRA_PWM_SET (0x47) ++ 0x00, // REG_ANAMIC_GAIN (0x48) ++ 0x00, // REG_MISC_SET_2 (0x49) ++}; ++ ++static void twl4030_dump_registers(void) ++{ ++ int i = 0; ++ u8 data; ++ ++ printk(KERN_INFO "TWL 4030 Register dump for Audio Module\n"); ++ ++ for (i = REG_CODEC_MODE; i <= REG_MISC_SET_2; i++) { ++ twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &data, i); ++ printk(KERN_INFO "Register[0x%02x]=0x%02x\n", i, data); ++ } ++} ++ ++struct twl4030_priv { ++ unsigned int dummy; ++}; ++ ++/* ++ * read twl4030 register cache ++ */ ++static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec, ++ unsigned int reg) ++{ ++ u8 *cache = codec->reg_cache; ++ ++ return cache[reg]; ++} ++ ++/* ++ * write twl4030 register cache ++ */ ++static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec, ++ u8 reg, u8 value) ++{ ++ u8 *cache = codec->reg_cache; ++ ++ if (reg >= TWL4030_CACHEREGNUM) ++ return; ++ cache[reg] = value; ++} ++ ++/* ++ * write to the twl4030 register space ++ */ ++static int twl4030_write(struct snd_soc_codec *codec, ++ unsigned int reg, unsigned int value) ++{ ++ twl4030_write_reg_cache(codec, reg, value); ++ return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg); ++} ++ ++static void twl4030_init_chip(void) ++{ ++ unsigned char byte; ++ int i; ++ ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[REG_CODEC_MODE] & 0xfd, REG_CODEC_MODE); ++ ++ udelay(10); /* delay for power settling */ ++ ++ for (i = REG_OPTION; i <= REG_MISC_SET_2; i++) { ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, twl4030_reg[i], i); ++ } ++ ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[REG_CODEC_MODE], REG_CODEC_MODE); ++ ++ udelay(10); /* delay for power settling */ ++ ++ /* initiate offset cancellation */ ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[REG_ANAMICL] | 0x80, REG_ANAMICL); ++ ++ /* wait for offset cancellation to complete */ ++ twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, REG_ANAMICL); ++ while ((byte & 0x80) == 0x80) ++ twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, REG_ANAMICL); ++ ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, ++ twl4030_reg[REG_MISC_SET_1] | 0x02, REG_MISC_SET_1); ++ ++} ++ ++static const struct snd_kcontrol_new twl4030_snd_controls[] = { ++ SOC_DOUBLE_R("Master Playback Volume", ++ REG_ARXL2PGA, REG_ARXR2PGA, ++ 0, 127, 0), ++ SOC_DOUBLE_R("Capture Volume", ++ REG_ATXL1PGA, REG_ATXR1PGA, ++ 0, 127, 0), ++}; ++ ++/* add non dapm controls */ ++static int twl4030_add_controls(struct snd_soc_codec *codec) ++{ ++ int err, i; ++ ++ for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) { ++ err = snd_ctl_add(codec->card, ++ snd_soc_cnew(&twl4030_snd_controls[i], ++ codec, NULL)); ++ if (err < 0) ++ return err; ++ } ++ ++ return 0; ++} ++ ++static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { ++ SND_SOC_DAPM_INPUT("INL"), ++ SND_SOC_DAPM_INPUT("INR"), ++ ++ SND_SOC_DAPM_OUTPUT("OUTL"), ++ SND_SOC_DAPM_OUTPUT("OUTR"), ++ ++ SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0), ++ SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0), ++ ++ SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0), ++ SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0), ++}; ++ ++static const char *intercon[][3] = { ++ /* outputs */ ++ {"OUTL", NULL, "DACL"}, ++ {"OUTR", NULL, "DACR"}, ++ ++ /* inputs */ ++ {"ADCL", NULL, "INL"}, ++ {"ADCR", NULL, "INR"}, ++ ++ /* terminator */ ++ {NULL, NULL, NULL}, ++}; ++ ++static int twl4030_add_widgets(struct snd_soc_codec *codec) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(twl4030_dapm_widgets); i++) ++ snd_soc_dapm_new_control(codec, &twl4030_dapm_widgets[i]); ++ ++ /* set up audio path interconnects */ ++ for (i = 0; intercon[i][0] != NULL; i++) ++ snd_soc_dapm_connect_input(codec, intercon[i][0], ++ intercon[i][1], intercon[i][2]); ++ ++ snd_soc_dapm_new_widgets(codec); ++ return 0; ++} ++ ++static int twl4030_dapm_event(struct snd_soc_codec *codec, int event) ++{ ++ ++ printk(KERN_INFO "TWL4030 Audio Codec dapm event\n"); ++ switch (event) { ++ case SNDRV_CTL_POWER_D0: /* full On */ ++ break; ++ case SNDRV_CTL_POWER_D1: /* partial On */ ++ case SNDRV_CTL_POWER_D2: /* partial On */ ++ break; ++ case SNDRV_CTL_POWER_D3hot: /* off, with power */ ++ break; ++ case SNDRV_CTL_POWER_D3cold: /* off, without power */ ++ break; ++ } ++ codec->dapm_state = event; ++ ++ return 0; ++} ++ ++static void twl4030_power_up (struct snd_soc_codec *codec, u8 mode) ++{ ++ u8 popn, hsgain; ++ ++ twl4030_write(codec, REG_CODEC_MODE, mode & ~CODECPDZ); ++ twl4030_write(codec, REG_CODEC_MODE, mode | CODECPDZ); ++ udelay(10); ++ ++ popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET); ++ popn &= RAMP_DELAY; ++ popn |= VMID_EN | RAMP_DELAY_161MS; ++ twl4030_write(codec, REG_HS_POPN_SET, popn); ++ ++ hsgain = HSR_GAIN_0DB| HSL_GAIN_0DB; ++ twl4030_write(codec, REG_HS_GAIN_SET, hsgain); ++ ++ popn |= RAMP_EN; ++ twl4030_write(codec, REG_HS_POPN_SET, popn); ++} ++ ++static void twl4030_power_down (struct snd_soc_codec *codec) ++{ ++ u8 popn, hsgain, mode; ++ ++ popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET); ++ popn &= ~RAMP_EN; ++ twl4030_write(codec, REG_HS_POPN_SET, popn); ++ ++ hsgain = HSR_GAIN_PWR_DOWN | HSL_GAIN_PWR_DOWN; ++ twl4030_write(codec, REG_HS_GAIN_SET, hsgain); ++ ++ popn &= ~VMID_EN; ++ twl4030_write(codec, REG_HS_POPN_SET, popn); ++ ++ mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); ++ mode &= ~CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ udelay(10); ++} ++ ++ ++static int twl4030_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_device *socdev = rtd->socdev; ++ struct snd_soc_codec *codec = socdev->codec; ++ struct twl4030_priv *twl4030 = codec->private_data; ++ u8 mode, old_mode, format, old_format; ++ ++ ++ /* bit rate */ ++ old_mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE) & ~CODECPDZ; ++ mode = old_mode; ++ mode &= ~APLL_RATE; ++ switch (params_rate(params)) { ++ case 44100: ++ mode |= APLL_RATE_44100; ++ break; ++ case 48000: ++ mode |= APLL_RATE_48000; ++ break; ++ default: ++ printk(KERN_INFO "TWL4030 hw params: unknown rate %d\n", params_rate(params)); ++ return -EINVAL; ++ } ++ ++ if (mode != old_mode) { ++ /* change rate and turn codec back on */ ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ mode |= CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ } ++ ++ /* sample size */ ++ old_format = twl4030_read_reg_cache(codec, REG_AUDIO_IF); ++ format = old_format; ++ format &= ~DATA_WIDTH; ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ format |= DATA_WIDTH_16S_16W; ++ break; ++ case SNDRV_PCM_FORMAT_S24_LE: ++ format |= DATA_WIDTH_32S_24W; ++ break; ++ default: ++ printk(KERN_INFO "TWL4030 hw params: unknown format %d\n", params_format(params)); ++ return -EINVAL; ++ } ++ ++ if (format != old_format) { ++ ++ /* turn off codec before changing format */ ++ mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); ++ mode &= ~CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ ++ /* change format */ ++ twl4030_write(codec, REG_AUDIO_IF, format); ++ ++ /* turn on codec */ ++ mode |= CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ } ++ return 0; ++} ++ ++static int twl4030_mute(struct snd_soc_codec_dai *dai, int mute) ++{ ++ struct snd_soc_codec *codec = dai->codec; ++ ++ u8 ldac_reg = twl4030_read_reg_cache(codec, REG_ARXL2PGA); ++ u8 rdac_reg = twl4030_read_reg_cache(codec, REG_ARXR2PGA); ++ ++ if (mute) { ++ /* printk(KERN_INFO "TWL4030 Audio Codec mute\n"); */ ++ twl4030_write(codec, REG_ARXL2PGA, 0x00); ++ twl4030_write(codec, REG_ARXR2PGA, 0x00); ++ twl4030_write_reg_cache(codec, REG_ARXL2PGA, ldac_reg); ++ twl4030_write_reg_cache(codec, REG_ARXR2PGA, rdac_reg); ++ } ++ else { ++ /* printk(KERN_INFO "TWL4030 Audio Codec unmute: %02x/%02x\n", ldac_reg, rdac_reg); */ ++ twl4030_write(codec, REG_ARXL2PGA, ldac_reg); ++ twl4030_write(codec, REG_ARXR2PGA, rdac_reg); ++ } ++ ++ return 0; ++} ++ ++static int twl4030_set_dai_fmt(struct snd_soc_codec_dai *codec_dai, ++ unsigned int fmt) ++{ ++ struct snd_soc_codec *codec = codec_dai->codec; ++ struct twl4030_priv *twl4030 = codec->private_data; ++ u8 mode, old_format, format; ++ ++ /* get format */ ++ old_format = twl4030_read_reg_cache(codec, REG_AUDIO_IF); ++ format = old_format; ++ ++ /* set master/slave audio interface */ ++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { ++ case SND_SOC_DAIFMT_CBM_CFM: ++ /* printk(KERN_INFO "TWL4030 set dai fmt: master\n"); */ ++ format &= ~(AIF_SLAVE_EN); ++ format |= CLK256FS_EN; ++ break; ++ case SND_SOC_DAIFMT_CBS_CFS: ++ /* printk(KERN_INFO "TWL4030 set dai fmt: slave\n"); */ ++ format &= ~(CLK256FS_EN); ++ format |= AIF_SLAVE_EN; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ /* interface format */ ++ format &= ~AIF_FORMAT; ++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_I2S: ++ /* printk(KERN_INFO "TWL4030 set dai fmt: i2s\n"); */ ++ format |= AIF_FORMAT_CODEC; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ if (format != old_format) { ++ ++ /* turn off codec before changing format */ ++ mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE); ++ mode &= ~CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ ++ /* change format */ ++ twl4030_write(codec, REG_AUDIO_IF, format); ++ ++ mode |= CODECPDZ; ++ twl4030_write(codec, REG_CODEC_MODE, mode); ++ } ++ ++ return 0; ++} ++ ++#define TWL4030_RATES SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 ++#define TWL4030_FORMATS SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE ++ ++struct snd_soc_codec_dai twl4030_dai = { ++ .name = "twl4030", ++ .playback = { ++ .stream_name = "Playback", ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = TWL4030_RATES, ++ .formats = TWL4030_FORMATS,}, ++ .capture = { ++ .stream_name = "Capture", ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = TWL4030_RATES, ++ .formats = TWL4030_FORMATS,}, ++ .ops = { ++ .hw_params = twl4030_hw_params, ++ }, ++ .dai_ops = { ++ .digital_mute = twl4030_mute, ++ .set_fmt = twl4030_set_dai_fmt, ++ } ++}; ++ ++EXPORT_SYMBOL_GPL(twl4030_dai); ++ ++static int twl4030_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec = socdev->codec; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec suspend\n"); ++ twl4030_dapm_event(codec, SNDRV_CTL_POWER_D3cold); ++ ++ return 0; ++} ++ ++static int twl4030_resume(struct platform_device *pdev) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec = socdev->codec; ++ int i; ++ u16 *cache = codec->reg_cache; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec resume\n"); ++ /* Sync reg_cache with the hardware */ ++ for (i = REG_CODEC_MODE; i <= REG_MISC_SET_2; i++) { ++ twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, cache[i], i); ++ } ++ twl4030_dapm_event(codec, SNDRV_CTL_POWER_D3hot); ++ twl4030_dapm_event(codec, codec->suspend_dapm_state); ++ return 0; ++} ++ ++/* ++ * initialize the driver ++ * register the mixer and dsp interfaces with the kernel ++ */ ++ ++static int twl4030_init(struct snd_soc_device *socdev) ++{ ++ struct snd_soc_codec *codec = socdev->codec; ++ int ret = 0; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec init \n"); ++ ++ codec->name = "twl4030"; ++ codec->owner = THIS_MODULE; ++ codec->read = twl4030_read_reg_cache; ++ codec->write = twl4030_write; ++ codec->dapm_event = twl4030_dapm_event; ++ codec->dai = &twl4030_dai; ++ codec->num_dai = 1; ++ codec->reg_cache_size = sizeof(twl4030_reg); ++ codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg), GFP_KERNEL); ++ if (codec->reg_cache == NULL) ++ return -ENOMEM; ++ ++ /* register pcms */ ++ ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); ++ if (ret < 0) { ++ printk(KERN_ERR "twl4030: failed to create pcms\n"); ++ goto pcm_err; ++ } ++ ++ twl4030_add_controls(codec); ++ twl4030_add_widgets(codec); ++ ++ ret = snd_soc_register_card(socdev); ++ if (ret < 0) { ++ printk(KERN_ERR "twl4030: failed to register card\n"); ++ goto card_err; ++ } ++ ++ twl4030_init_chip(); ++ twl4030_power_up(codec, APLL_RATE_44100 | OPT_MODE); ++ ++ return ret; ++ ++card_err: ++ printk(KERN_INFO "TWL4030 Audio Codec init card error\n"); ++ snd_soc_free_pcms(socdev); ++ snd_soc_dapm_free(socdev); ++pcm_err: ++ printk(KERN_INFO "TWL4030 Audio Codec init pcm error\n"); ++ kfree(codec->reg_cache); ++ return ret; ++} ++ ++static struct snd_soc_device *twl4030_socdev; ++ ++static int twl4030_probe(struct platform_device *pdev) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec; ++ struct twl4030_priv *twl4030; ++ ++ codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); ++ if (codec == NULL) ++ return -ENOMEM; ++ ++ twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL); ++ if (twl4030 == NULL) { ++ kfree(codec); ++ return -ENOMEM; ++ } ++ ++ codec->private_data = twl4030; ++ socdev->codec = codec; ++ mutex_init(&codec->mutex); ++ INIT_LIST_HEAD(&codec->dapm_widgets); ++ INIT_LIST_HEAD(&codec->dapm_paths); ++ ++ twl4030_socdev = socdev; ++ twl4030_init(socdev); ++ ++ return 0; ++} ++ ++static int twl4030_remove(struct platform_device *pdev) ++{ ++ struct snd_soc_device *socdev = platform_get_drvdata(pdev); ++ struct snd_soc_codec *codec = socdev->codec; ++ ++ printk(KERN_INFO "TWL4030 Audio Codec remove\n"); ++ kfree(codec->private_data); ++ kfree(codec); ++ ++ return 0; ++} ++ ++struct snd_soc_codec_device soc_codec_dev_twl4030 = { ++ .probe = twl4030_probe, ++ .remove = twl4030_remove, ++ .suspend = twl4030_suspend, ++ .resume = twl4030_resume, ++}; ++EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030); ++ ++MODULE_DESCRIPTION("ASoC TWL4030 codec driver"); ++MODULE_AUTHOR("Steve Sakoman"); ++MODULE_LICENSE("GPL"); +diff --git a/sound/soc/codecs/twl4030.h b/sound/soc/codecs/twl4030.h +new file mode 100644 +index 0000000..e126f96 +--- /dev/null ++++ b/sound/soc/codecs/twl4030.h +@@ -0,0 +1,152 @@ ++/* ++ * ALSA SoC TWL4030 codec driver ++ * ++ * Author: Steve Sakoman, <steve@sakoman.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __TWL4030_AUDIO_H__ ++#define __TWL4030_AUDIO_H__ ++ ++#define REG_CODEC_MODE 0x1 ++#define REG_OPTION 0x2 ++#define REG_UNKNOWN 0x3 ++#define REG_MICBIAS_CTL 0x4 ++#define REG_ANAMICL 0x5 ++#define REG_ANAMICR 0x6 ++#define REG_AVADC_CTL 0x7 ++#define REG_ADCMICSEL 0x8 ++#define REG_DIGMIXING 0x9 ++#define REG_ATXL1PGA 0xA ++#define REG_ATXR1PGA 0xB ++#define REG_AVTXL2PGA 0xC ++#define REG_AVTXR2PGA 0xD ++#define REG_AUDIO_IF 0xE ++#define REG_VOICE_IF 0xF ++#define REG_ARXR1PGA 0x10 ++#define REG_ARXL1PGA 0x11 ++#define REG_ARXR2PGA 0x12 ++#define REG_ARXL2PGA 0x13 ++#define REG_VRXPGA 0x14 ++#define REG_VSTPGA 0x15 ++#define REG_VRX2ARXPGA 0x16 ++#define REG_AVDAC_CTL 0x17 ++#define REG_ARX2VTXPGA 0x18 ++#define REG_ARXL1_APGA_CTL 0x19 ++#define REG_ARXR1_APGA_CTL 0x1A ++#define REG_ARXL2_APGA_CTL 0x1B ++#define REG_ARXR2_APGA_CTL 0x1C ++#define REG_ATX2ARXPGA 0x1D ++#define REG_BT_IF 0x1E ++#define REG_BTPGA 0x1F ++#define REG_BTSTPGA 0x20 ++#define REG_EAR_CTL 0x21 ++#define REG_HS_SEL 0x22 ++#define REG_HS_GAIN_SET 0x23 ++#define REG_HS_POPN_SET 0x24 ++#define REG_PREDL_CTL 0x25 ++#define REG_PREDR_CTL 0x26 ++#define REG_PRECKL_CTL 0x27 ++#define REG_PRECKR_CTL 0x28 ++#define REG_HFL_CTL 0x29 ++#define REG_HFR_CTL 0x2A ++#define REG_ALC_CTL 0x2B ++#define REG_ALC_SET1 0x2C ++#define REG_ALC_SET2 0x2D ++#define REG_BOOST_CTL 0x2E ++#define REG_SOFTVOL_CTL 0x2F ++#define REG_DTMF_FREQSEL 0x30 ++#define REG_DTMF_TONEXT1H 0x31 ++#define REG_DTMF_TONEXT1L 0x32 ++#define REG_DTMF_TONEXT2H 0x33 ++#define REG_DTMF_TONEXT2L 0x34 ++#define REG_DTMF_TONOFF 0x35 ++#define REG_DTMF_WANONOFF 0x36 ++#define REG_I2S_RX_SCRAMBLE_H 0x37 ++#define REG_I2S_RX_SCRAMBLE_M 0x38 ++#define REG_I2S_RX_SCRAMBLE_L 0x39 ++#define REG_APLL_CTL 0x3A ++#define REG_DTMF_CTL 0x3B ++#define REG_DTMF_PGA_CTL2 0x3C ++#define REG_DTMF_PGA_CTL1 0x3D ++#define REG_MISC_SET_1 0x3E ++#define REG_PCMBTMUX 0x3F ++#define REG_RX_PATH_SEL 0x43 ++#define REG_VDL_APGA_CTL 0x44 ++#define REG_VIBRA_CTL 0x45 ++#define REG_VIBRA_SET 0x46 ++#define REG_VIBRA_PWM_SET 0x47 ++#define REG_ANAMIC_GAIN 0x48 ++#define REG_MISC_SET_2 0x49 ++ ++#define TWL4030_CACHEREGNUM REG_MISC_SET_2 + 1 ++ ++/* Bitfield Definitions */ ++ ++/* CODEC_MODE (0x01) Fields */ ++ ++#define APLL_RATE 0xF0 ++#define APLL_RATE_8000 0x00 ++#define APLL_RATE_11025 0x10 ++#define APLL_RATE_12000 0x20 ++#define APLL_RATE_16000 0x40 ++#define APLL_RATE_22050 0x50 ++#define APLL_RATE_24000 0x60 ++#define APLL_RATE_32000 0x80 ++#define APLL_RATE_44100 0x90 ++#define APLL_RATE_48000 0xa0 ++#define SEL_16K 0x04 ++#define CODECPDZ 0x02 ++#define OPT_MODE 0x01 ++ ++/* AUDIO_IF (0x0E) Fields */ ++ ++#define AIF_SLAVE_EN 0x80 ++#define DATA_WIDTH 0x60 ++#define DATA_WIDTH_16S_16W 0x00 ++#define DATA_WIDTH_32S_16W 0x40 ++#define DATA_WIDTH_32S_24W 0x60 ++#define AIF_FORMAT 0x18 ++#define AIF_FORMAT_CODEC 0x00 ++#define AIF_FORMAT_LEFT 0x08 ++#define AIF_FORMAT_RIGHT 0x10 ++#define AIF_FORMAT_TDM 0x18 ++#define AIF_TRI_EN 0x04 ++#define CLK256FS_EN 0x02 ++#define AIF_EN 0x01 ++ ++/* HS_GAIN_SET (0x23) Fields */ ++ ++#define HSR_GAIN 0x0c ++#define HSR_GAIN_PWR_DOWN 0x00 ++#define HSR_GAIN_PLUS_6DB 0x04 ++#define HSR_GAIN_0DB 0x08 ++#define HSR_GAIN_MINUS_6DB 0x0c ++#define HSL_GAIN 0x0c ++#define HSL_GAIN_PWR_DOWN 0x00 ++#define HSL_GAIN_PLUS_6DB 0x01 ++#define HSL_GAIN_0DB 0x02 ++#define HSL_GAIN_MINUS_6DB 0x03 ++ ++/* HS_POPN_SET (0x24) Fields */ ++ ++#define VMID_EN 0x40 ++#define EXTMUTE 0x20 ++#define RAMP_DELAY 0x1C ++#define RAMP_DELAY_20MS 0x00 ++#define RAMP_DELAY_40MS 0x04 ++#define RAMP_DELAY_81MS 0x08 ++#define RAMP_DELAY_161MS 0x0c ++#define RAMP_DELAY_323MS 0x10 ++#define RAMP_DELAY_645MS 0x14 ++#define RAMP_DELAY_1291MS 0x18 ++#define RAMP_DELAY_2581MS 0x1c ++#define RAMP_EN 0x02 ++ ++extern struct snd_soc_codec_dai twl4030_dai; ++extern struct snd_soc_codec_device soc_codec_dev_twl4030; ++ ++#endif /* End of __TWL4030_AUDIO_H__ */ +diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig +index 0230d83..8703cea 100644 +--- a/sound/soc/omap/Kconfig ++++ b/sound/soc/omap/Kconfig +@@ -16,4 +16,20 @@ config SND_OMAP_SOC_N810 + help + Say Y if you want to add support for SoC audio on Nokia N810. + ++config SND_OMAP_SOC_OMAP3EVM ++ tristate "SoC Audio support for OMAP3 EVM" ++ depends on SND_OMAP_SOC && MACH_OMAP3EVM ++ select SND_OMAP_SOC_MCBSP ++ select SND_SOC_TWL4030 ++ help ++ Say Y if you want to add support for SoC audio on the OMAP3 EVM. ++ ++config SND_OMAP_SOC_OMAP3BEAGLE ++ tristate "SoC Audio support for OMAP3 Beagle" ++ depends on SND_OMAP_SOC && MACH_OMAP3_BEAGLE ++ select SND_OMAP_SOC_MCBSP ++ select SND_SOC_TWL4030 ++ help ++ Say Y if you want to add support for SoC audio on the OMAP3 Beagle. ++ + endmenu +diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile +index d8d8d58..638a240 100644 +--- a/sound/soc/omap/Makefile ++++ b/sound/soc/omap/Makefile +@@ -7,5 +7,10 @@ obj-$(CONFIG_SND_OMAP_SOC_MCBSP) += snd-soc-omap-mcbsp.o + + # OMAP Machine Support + snd-soc-n810-objs := n810.o ++snd-soc-omap3evm-objs := omap3evm.o ++snd-soc-omap3beagle-objs := omap3beagle.o + + obj-$(CONFIG_SND_OMAP_SOC_N810) += snd-soc-n810.o ++obj-$(CONFIG_SND_OMAP_SOC_OMAP3EVM) += snd-soc-omap3evm.o ++obj-$(CONFIG_SND_OMAP_SOC_OMAP3BEAGLE) += snd-soc-omap3beagle.o ++ +diff --git a/sound/soc/omap/omap3beagle.c b/sound/soc/omap/omap3beagle.c +new file mode 100644 +index 0000000..878f894 +--- /dev/null ++++ b/sound/soc/omap/omap3beagle.c +@@ -0,0 +1,142 @@ ++/* ++ * omap3beagle.c -- SoC audio for OMAP3 Beagle ++ * ++ * Author: Steve Sakoman <steve@sakoman.com> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA ++ * 02110-1301 USA ++ * ++ */ ++ ++#include <linux/clk.h> ++#include <linux/platform_device.h> ++#include <sound/core.h> ++#include <sound/pcm.h> ++#include <sound/soc.h> ++#include <sound/soc-dapm.h> ++ ++#include <asm/mach-types.h> ++#include <asm/arch/hardware.h> ++#include <asm/arch/gpio.h> ++#include <asm/arch/mcbsp.h> ++ ++#include "omap-mcbsp.h" ++#include "omap-pcm.h" ++#include "../codecs/twl4030.h" ++ ++static int omap3beagle_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai; ++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; ++ int ret; ++ ++ /* Set codec DAI configuration */ ++ ret = codec_dai->dai_ops.set_fmt(codec_dai, ++ SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM); ++ if (ret < 0) { ++ printk(KERN_INFO "can't set codec DAI configuration\n"); ++ return ret; ++ } ++ ++ /* Set cpu DAI configuration */ ++ ret = cpu_dai->dai_ops.set_fmt(cpu_dai, ++ SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM); ++ if (ret < 0) { ++ printk(KERN_INFO "can't set cpu DAI configuration\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static struct snd_soc_ops omap3beagle_ops = { ++ .hw_params = omap3beagle_hw_params, ++}; ++ ++/* Digital audio interface glue - connects codec <--> CPU */ ++static struct snd_soc_dai_link omap3beagle_dai = { ++ .name = "TWL4030", ++ .stream_name = "TWL4030", ++ .cpu_dai = &omap_mcbsp_dai[0], ++ .codec_dai = &twl4030_dai, ++ .ops = &omap3beagle_ops, ++}; ++ ++/* Audio machine driver */ ++static struct snd_soc_machine snd_soc_machine_omap3beagle = { ++ .name = "omap3beagle", ++ .dai_link = &omap3beagle_dai, ++ .num_links = 1, ++}; ++ ++/* Audio subsystem */ ++static struct snd_soc_device omap3beagle_snd_devdata = { ++ .machine = &snd_soc_machine_omap3beagle, ++ .platform = &omap_soc_platform, ++ .codec_dev = &soc_codec_dev_twl4030, ++}; ++ ++static struct platform_device *omap3beagle_snd_device; ++ ++static int __init omap3beagle_soc_init(void) ++{ ++ int ret; ++ ++ printk(KERN_INFO "OMAP3 Beagle SoC init\n"); ++ if (!machine_is_omap3_beagle()) { ++ printk(KERN_INFO "Not OMAP3 Beagle!\n"); ++ return -ENODEV; ++ } ++ ++ omap3beagle_snd_device = platform_device_alloc("soc-audio", -1); ++ if (!omap3beagle_snd_device) { ++ printk(KERN_INFO "Platform device allocation failed\n"); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(omap3beagle_snd_device, &omap3beagle_snd_devdata); ++ omap3beagle_snd_devdata.dev = &omap3beagle_snd_device->dev; ++ *(unsigned int *)omap3beagle_dai.cpu_dai->private_data = 1; /* McBSP2 */ ++ ++ ret = platform_device_add(omap3beagle_snd_device); ++ if (ret) ++ goto err1; ++ ++ return 0; ++ ++err1: ++ printk(KERN_INFO "Unable to add platform device\n"); ++ platform_device_put(omap3beagle_snd_device); ++ ++ return ret; ++} ++ ++static void __exit omap3beagle_soc_exit(void) ++{ ++ printk(KERN_INFO "OMAP3 Beagle SoC exit\n"); ++ platform_device_unregister(omap3beagle_snd_device); ++} ++ ++module_init(omap3beagle_soc_init); ++module_exit(omap3beagle_soc_exit); ++ ++MODULE_AUTHOR("Steve Sakoman <steve@sakoman.com>"); ++MODULE_DESCRIPTION("ALSA SoC OMAP3 Beagle"); ++MODULE_LICENSE("GPL"); +diff --git a/sound/soc/omap/omap3evm.c b/sound/soc/omap/omap3evm.c +new file mode 100644 +index 0000000..a64c788 +--- /dev/null ++++ b/sound/soc/omap/omap3evm.c +@@ -0,0 +1,142 @@ ++/* ++ * omap3evm.c -- SoC audio for OMAP3 EVM ++ * ++ * Author: Steve Sakoman <steve@sakoman.com> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA ++ * 02110-1301 USA ++ * ++ */ ++ ++#include <linux/clk.h> ++#include <linux/platform_device.h> ++#include <sound/core.h> ++#include <sound/pcm.h> ++#include <sound/soc.h> ++#include <sound/soc-dapm.h> ++ ++#include <asm/mach-types.h> ++#include <asm/arch/hardware.h> ++#include <asm/arch/gpio.h> ++#include <asm/arch/mcbsp.h> ++ ++#include "omap-mcbsp.h" ++#include "omap-pcm.h" ++#include "../codecs/twl4030.h" ++ ++static int omap3evm_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai; ++ struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai; ++ int ret; ++ ++ /* Set codec DAI configuration */ ++ ret = codec_dai->dai_ops.set_fmt(codec_dai, ++ SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM); ++ if (ret < 0) { ++ printk(KERN_INFO "can't set codec DAI configuration\n"); ++ return ret; ++ } ++ ++ /* Set cpu DAI configuration */ ++ ret = cpu_dai->dai_ops.set_fmt(cpu_dai, ++ SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM); ++ if (ret < 0) { ++ printk(KERN_INFO "can't set cpu DAI configuration\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static struct snd_soc_ops omap3evm_ops = { ++ .hw_params = omap3evm_hw_params, ++}; ++ ++/* Digital audio interface glue - connects codec <--> CPU */ ++static struct snd_soc_dai_link omap3evm_dai = { ++ .name = "TWL4030", ++ .stream_name = "TWL4030", ++ .cpu_dai = &omap_mcbsp_dai[0], ++ .codec_dai = &twl4030_dai, ++ .ops = &omap3evm_ops, ++}; ++ ++/* Audio machine driver */ ++static struct snd_soc_machine snd_soc_machine_omap3evm = { ++ .name = "omap3evm", ++ .dai_link = &omap3evm_dai, ++ .num_links = 1, ++}; ++ ++/* Audio subsystem */ ++static struct snd_soc_device omap3evm_snd_devdata = { ++ .machine = &snd_soc_machine_omap3evm, ++ .platform = &omap_soc_platform, ++ .codec_dev = &soc_codec_dev_twl4030, ++}; ++ ++static struct platform_device *omap3evm_snd_device; ++ ++static int __init omap3evm_soc_init(void) ++{ ++ int ret; ++ ++ printk(KERN_INFO "OMAP3 EVM SoC init\n"); ++ if (!machine_is_omap3evm()) { ++ printk(KERN_INFO "Not OMAP3 EVM!\n"); ++ return -ENODEV; ++ } ++ ++ omap3evm_snd_device = platform_device_alloc("soc-audio", -1); ++ if (!omap3evm_snd_device) { ++ printk(KERN_INFO "Platform device allocation failed\n"); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(omap3evm_snd_device, &omap3evm_snd_devdata); ++ omap3evm_snd_devdata.dev = &omap3evm_snd_device->dev; ++ *(unsigned int *)omap3evm_dai.cpu_dai->private_data = 1; /* McBSP2 */ ++ ++ ret = platform_device_add(omap3evm_snd_device); ++ if (ret) ++ goto err1; ++ ++ return 0; ++ ++err1: ++ printk(KERN_INFO "Unable to add platform device\n"); ++ platform_device_put(omap3evm_snd_device); ++ ++ return ret; ++} ++ ++static void __exit omap3evm_soc_exit(void) ++{ ++ printk(KERN_INFO "OMAP3 EVM SoC exit\n"); ++ platform_device_unregister(omap3evm_snd_device); ++} ++ ++module_init(omap3evm_soc_init); ++module_exit(omap3evm_soc_exit); ++ ++MODULE_AUTHOR("Steve Sakoman <steve@sakoman.com>"); ++MODULE_DESCRIPTION("ALSA SoC OMAP3 EVM"); ++MODULE_LICENSE("GPL"); diff --git a/packages/linux/linux-omap2-git/omap3evm/timer-suppression.patch b/packages/linux/linux-omap2-git/omap3evm/timer-suppression.patch new file mode 100644 index 0000000000..04362c96e3 --- /dev/null +++ b/packages/linux/linux-omap2-git/omap3evm/timer-suppression.patch @@ -0,0 +1,43 @@ +diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c +index b854a89..26f5569 100644 +--- a/kernel/time/tick-sched.c ++++ b/kernel/time/tick-sched.c +@@ -253,6 +253,16 @@ void tick_nohz_stop_sched_tick(void) + + /* Schedule the tick, if we are at least one jiffie off */ + if ((long)delta_jiffies >= 1) { ++ /* ++ * calculate the expiry time for the next timer wheel ++ * timer ++ */ ++ expires = ktime_add_ns(last_update, tick_period.tv64 * ++ delta_jiffies); ++ ++ /* Skip reprogram of event if its not changed */ ++ if(ts->tick_stopped && ktime_equal(expires, dev->next_event)) ++ goto out2; + + if (delta_jiffies > 1) + cpu_set(cpu, nohz_cpu_mask); +@@ -304,12 +314,7 @@ void tick_nohz_stop_sched_tick(void) + goto out; + } + +- /* +- * calculate the expiry time for the next timer wheel +- * timer +- */ +- expires = ktime_add_ns(last_update, tick_period.tv64 * +- delta_jiffies); ++ /* Mark expiries */ + ts->idle_expires = expires; + + if (ts->nohz_mode == NOHZ_MODE_HIGHRES) { +@@ -328,6 +333,7 @@ void tick_nohz_stop_sched_tick(void) + tick_do_update_jiffies64(ktime_get()); + cpu_clear(cpu, nohz_cpu_mask); + } ++out2: + raise_softirq_irqoff(TIMER_SOFTIRQ); + out: + ts->next_jiffies = next_jiffies; diff --git a/packages/linux/linux-omap2-git/omap3evm/touchscreen.patch b/packages/linux/linux-omap2-git/omap3evm/touchscreen.patch new file mode 100644 index 0000000000..2325c401e4 --- /dev/null +++ b/packages/linux/linux-omap2-git/omap3evm/touchscreen.patch @@ -0,0 +1,22 @@ +diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c +index d8109ae..f8ce669 100644 +--- a/arch/arm/mach-omap2/board-omap3evm.c ++++ b/arch/arm/mach-omap2/board-omap3evm.c +@@ -128,8 +128,16 @@ static int ads7846_get_pendown_state(void) + } + + struct ads7846_platform_data ads7846_config = { ++ .x_max = 0x0fff, ++ .y_max = 0x0fff, ++ .x_plate_ohms = 180, ++ .pressure_max = 255, ++ .debounce_max = 10, ++ .debounce_tol = 3, ++ .debounce_rep = 1, + .get_pendown_state = ads7846_get_pendown_state, + .keep_vref_on = 1, ++ .settle_delay_usecs = 150, + }; + + static struct omap2_mcspi_device_config ads7846_mcspi_config = { + |