25 files changed, 7572 insertions, 1745 deletions

diff --git a/packages/linux/linux-omap2-git/beagleboard/00001-mcbsp-transform.patch b/packages/linux/linux-omap2-git/beagleboard/00001-mcbsp-transform.patch
deleted file mode 100644
index 452370bf3e..0000000000
--- a/packages/linux/linux-omap2-git/beagleboard/00001-mcbsp-transform.patch
+++ /dev/null
@@ -1,1160 +0,0 @@
-From: Eduardo Valentin <eduardo.valentin@indt.org.br>

-

-This patch transform mcbsp code into a very initial

-implementation of a platform driver.

-

-It also gets ride of ifdefs on mcbsp.c code.

-To do it, a platform data structure was defined.

-

-Platform devices are located in arch/arm/plat-omap/devices.c

-

-Signed-off-by: Eduardo Valentin <eduardo.valentin@indt.org.br>

----

- arch/arm/plat-omap/devices.c      |   45 +++

- arch/arm/plat-omap/mcbsp.c        |  660 ++++++++++++++-----------------------

- include/asm-arm/arch-omap/mcbsp.h |   73 ++++-

- 3 files changed, 367 insertions(+), 411 deletions(-)

-

-diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c

-index 099182b..b3e0147 100644

---- a/arch/arm/plat-omap/devices.c

-+++ b/arch/arm/plat-omap/devices.c

-@@ -27,6 +27,7 @@

- #include <asm/arch/gpio.h>

- #include <asm/arch/menelaus.h>

- #include <asm/arch/dsp_common.h>

-+#include <asm/arch/mcbsp.h>

- 

- #if	defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)

- 

-@@ -150,6 +151,49 @@ static inline void omap_init_kp(void) {}

- #endif

- 

- /*-------------------------------------------------------------------------*/

-+#if defined(CONFIG_OMAP_MCBSP) || defined(CONFIG_OMAP_MCBSP_MODULE)

-+

-+static struct platform_device omap_mcbsp_devices[OMAP_MAX_MCBSP_COUNT];

-+static int mcbsps_configured;

-+

-+void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,

-+					int size)

-+{

-+	int i;

-+

-+	if (size > OMAP_MAX_MCBSP_COUNT) {

-+		printk(KERN_WARNING "Registered too many McBSPs platform_data."

-+			" Using maximum (%d) available.\n",

-+			OMAP_MAX_MCBSP_COUNT);

-+		size = OMAP_MAX_MCBSP_COUNT;

-+	}

-+

-+	for (i = 0; i < size; i++) {

-+		struct platform_device *new_mcbsp = &omap_mcbsp_devices[i];

-+		new_mcbsp->name = "omap-mcbsp";

-+		new_mcbsp->id = i + 1;

-+		new_mcbsp->dev.platform_data = &config[i];

-+	}

-+	mcbsps_configured = size;

-+}

-+

-+static void __init omap_init_mcbsp(void)

-+{

-+	int i;

-+

-+	for (i = 0; i < mcbsps_configured; i++)

-+		platform_device_register(&omap_mcbsp_devices[i]);

-+}

-+#else

-+void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,

-+					int size)

-+{  }

-+

-+static inline void __init omap_init_mcbsp(void)

-+{  }

-+#endif

-+

-+/*-------------------------------------------------------------------------*/

- 

- #if	defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) \

- 	|| defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)

-@@ -511,6 +555,7 @@ static int __init omap_init_devices(void)

- 	 */

- 	omap_init_dsp();

- 	omap_init_kp();

-+	omap_init_mcbsp();

- 	omap_init_mmc();

- 	omap_init_uwire();

- 	omap_init_wdt();

-diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c

-index 053de31..5536223 100644

---- a/arch/arm/plat-omap/mcbsp.c

-+++ b/arch/arm/plat-omap/mcbsp.c

-@@ -15,6 +15,7 @@

- #include <linux/module.h>

- #include <linux/init.h>

- #include <linux/device.h>

-+#include <linux/platform_device.h>

- #include <linux/wait.h>

- #include <linux/completion.h>

- #include <linux/interrupt.h>

-@@ -25,83 +26,53 @@

- #include <linux/irq.h>

- 

- #include <asm/arch/dma.h>

--#include <asm/arch/mux.h>

--#include <asm/arch/irqs.h>

--#include <asm/arch/dsp_common.h>

- #include <asm/arch/mcbsp.h>

- 

--#ifdef CONFIG_MCBSP_DEBUG

--#define DBG(x...)	printk(x)

--#else

--#define DBG(x...)			do { } while (0)

--#endif

--

--struct omap_mcbsp {

--	u32                          io_base;

--	u8                           id;

--	u8                           free;

--	omap_mcbsp_word_length       rx_word_length;

--	omap_mcbsp_word_length       tx_word_length;

--

--	omap_mcbsp_io_type_t         io_type; /* IRQ or poll */

--	/* IRQ based TX/RX */

--	int                          rx_irq;

--	int                          tx_irq;

--

--	/* DMA stuff */

--	u8                           dma_rx_sync;

--	short                        dma_rx_lch;

--	u8                           dma_tx_sync;

--	short                        dma_tx_lch;

--

--	/* Completion queues */

--	struct completion            tx_irq_completion;

--	struct completion            rx_irq_completion;

--	struct completion            tx_dma_completion;

--	struct completion            rx_dma_completion;

--

--	/* Protect the field .free, while checking if the mcbsp is in use */

--	spinlock_t                   lock;

--};

--

- static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];

--#ifdef CONFIG_ARCH_OMAP1

--static struct clk *mcbsp_dsp_ck;

--static struct clk *mcbsp_api_ck;

--static struct clk *mcbsp_dspxor_ck;

--#endif

--#ifdef CONFIG_ARCH_OMAP2

--static struct clk *mcbsp1_ick;

--static struct clk *mcbsp1_fck;

--static struct clk *mcbsp2_ick;

--static struct clk *mcbsp2_fck;

--#endif

-+

-+#define omap_mcbsp_check_valid_id(id)	(mcbsp[id].pdata && \

-+					mcbsp[id].pdata->ops && \

-+					mcbsp[id].pdata->ops->check && \

-+					(mcbsp[id].pdata->ops->check(id) == 0))

- 

- static void omap_mcbsp_dump_reg(u8 id)

- {

--	DBG("**** MCBSP%d regs ****\n", mcbsp[id].id);

--	DBG("DRR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));

--	DBG("DRR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));

--	DBG("DXR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));

--	DBG("DXR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));

--	DBG("SPCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));

--	DBG("SPCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));

--	DBG("RCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));

--	DBG("RCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));

--	DBG("XCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));

--	DBG("XCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));

--	DBG("SRGR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));

--	DBG("SRGR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));

--	DBG("PCR0:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));

--	DBG("***********************\n");

-+	dev_dbg(mcbsp[id].dev, "**** McBSP%d regs ****\n", mcbsp[id].id);

-+	dev_dbg(mcbsp[id].dev, "DRR2:  0x%04x\n",

-+			OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));

-+	dev_dbg(mcbsp[id].dev, "DRR1:  0x%04x\n",

-+			OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));

-+	dev_dbg(mcbsp[id].dev, "DXR2:  0x%04x\n",

-+			OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));

-+	dev_dbg(mcbsp[id].dev, "DXR1:  0x%04x\n",

-+			OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));

-+	dev_dbg(mcbsp[id].dev, "SPCR2: 0x%04x\n",

-+			OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));

-+	dev_dbg(mcbsp[id].dev, "SPCR1: 0x%04x\n",

-+			OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));

-+	dev_dbg(mcbsp[id].dev, "RCR2:  0x%04x\n",

-+			OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));

-+	dev_dbg(mcbsp[id].dev, "RCR1:  0x%04x\n",

-+			OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));

-+	dev_dbg(mcbsp[id].dev, "XCR2:  0x%04x\n",

-+			OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));

-+	dev_dbg(mcbsp[id].dev, "XCR1:  0x%04x\n",

-+			OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));

-+	dev_dbg(mcbsp[id].dev, "SRGR2: 0x%04x\n",

-+			OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));

-+	dev_dbg(mcbsp[id].dev, "SRGR1: 0x%04x\n",

-+			OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));

-+	dev_dbg(mcbsp[id].dev, "PCR0:  0x%04x\n",

-+			OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));

-+	dev_dbg(mcbsp[id].dev, "***********************\n");

- }

- 

- static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)

- {

- 	struct omap_mcbsp *mcbsp_tx = dev_id;

- 

--	DBG("TX IRQ callback : 0x%x\n",

--	    OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));

-+	dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n",

-+		OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));

- 

- 	complete(&mcbsp_tx->tx_irq_completion);

- 

-@@ -112,8 +83,8 @@ static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)

- {

- 	struct omap_mcbsp *mcbsp_rx = dev_id;

- 

--	DBG("RX IRQ callback : 0x%x\n",

--	    OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));

-+	dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n",

-+		OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));

- 

- 	complete(&mcbsp_rx->rx_irq_completion);

- 

-@@ -124,8 +95,8 @@ static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)

- {

- 	struct omap_mcbsp *mcbsp_dma_tx = data;

- 

--	DBG("TX DMA callback : 0x%x\n",

--	    OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));

-+	dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",

-+		OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));

- 

- 	/* We can free the channels */

- 	omap_free_dma(mcbsp_dma_tx->dma_tx_lch);

-@@ -138,8 +109,8 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)

- {

- 	struct omap_mcbsp *mcbsp_dma_rx = data;

- 

--	DBG("RX DMA callback : 0x%x\n",

--	    OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));

-+	dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",

-+		OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));

- 

- 	/* We can free the channels */

- 	omap_free_dma(mcbsp_dma_rx->dma_rx_lch);

-@@ -156,9 +127,16 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)

-  */

- void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)

- {

--	u32 io_base = mcbsp[id].io_base;

-+	u32 io_base;

-+

-+	if (!omap_mcbsp_check_valid_id(id)) {

-+		printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);

-+		return;

-+	}

- 

--	DBG("OMAP-McBSP: McBSP%d  io_base: 0x%8x\n", id + 1, io_base);

-+	io_base = mcbsp[id].io_base;

-+	dev_dbg(mcbsp[id].dev, "Configuring McBSP%d  io_base: 0x%8x\n",

-+			mcbsp[id].id, io_base);

- 

- 	/* We write the given config */

- 	OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);

-@@ -175,97 +153,22 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)

- }

- EXPORT_SYMBOL(omap_mcbsp_config);

- 

--static int omap_mcbsp_check(unsigned int id)

--{

--	if (cpu_is_omap730()) {

--		if (id > OMAP_MAX_MCBSP_COUNT - 1) {

--		       printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",

--				id + 1);

--		       return -1;

--		}

--		return 0;

--	}

--

--	if (cpu_is_omap15xx() || cpu_is_omap16xx() || cpu_is_omap24xx()) {

--		if (id > OMAP_MAX_MCBSP_COUNT) {

--			printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",

--				id + 1);

--			return -1;

--		}

--		return 0;

--	}

--

--	return -1;

--}

--

--#ifdef CONFIG_ARCH_OMAP1

--static void omap_mcbsp_dsp_request(void)

--{

--	if (cpu_is_omap15xx() || cpu_is_omap16xx()) {

--		int ret;

--

--		ret = omap_dsp_request_mem();

--		if (ret < 0) {

--			printk(KERN_ERR "Could not get dsp memory: %i\n", ret);

--			return;

--		}

--

--		clk_enable(mcbsp_dsp_ck);

--		clk_enable(mcbsp_api_ck);

--

--		/* enable 12MHz clock to mcbsp 1 & 3 */

--		clk_enable(mcbsp_dspxor_ck);

--

--		/*

--		 * DSP external peripheral reset

--		 * FIXME: This should be moved to dsp code

--		 */

--		__raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1,

--			     DSP_RSTCT2);

--	}

--}

--

--static void omap_mcbsp_dsp_free(void)

--{

--	if (cpu_is_omap15xx() || cpu_is_omap16xx()) {

--		omap_dsp_release_mem();

--		clk_disable(mcbsp_dspxor_ck);

--		clk_disable(mcbsp_dsp_ck);

--		clk_disable(mcbsp_api_ck);

--	}

--}

--#endif

--

--#ifdef CONFIG_ARCH_OMAP2

--static void omap2_mcbsp2_mux_setup(void)

--{

--	if (cpu_is_omap2420()) {

--		omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);

--		omap_cfg_reg(R14_24XX_MCBSP2_FSX);

--		omap_cfg_reg(W15_24XX_MCBSP2_DR);

--		omap_cfg_reg(V15_24XX_MCBSP2_DX);

--		omap_cfg_reg(V14_24XX_GPIO117);

--	}

--	/*

--	 * Need to add MUX settings for OMAP 2430 SDP

--	 */

--}

--#endif

--

- /*

-  * We can choose between IRQ based or polled IO.

-  * This needs to be called before omap_mcbsp_request().

-  */

- int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)

- {

--	if (omap_mcbsp_check(id) < 0)

--		return -EINVAL;

-+	if (!omap_mcbsp_check_valid_id(id)) {

-+		printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);

-+		return -ENODEV;

-+	}

- 

- 	spin_lock(&mcbsp[id].lock);

- 

- 	if (!mcbsp[id].free) {

--		printk(KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n",

--			id + 1);

-+		dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n",

-+			mcbsp[id].id);

- 		spin_unlock(&mcbsp[id].lock);

- 		return -EINVAL;

- 	}

-@@ -282,34 +185,20 @@ int omap_mcbsp_request(unsigned int id)

- {

- 	int err;

- 

--	if (omap_mcbsp_check(id) < 0)

--		return -EINVAL;

--

--#ifdef CONFIG_ARCH_OMAP1

--	/*

--	 * On 1510, 1610 and 1710, McBSP1 and McBSP3

--	 * are DSP public peripherals.

--	 */

--	if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)

--		omap_mcbsp_dsp_request();

--#endif

--

--#ifdef CONFIG_ARCH_OMAP2

--	if (cpu_is_omap24xx()) {

--		if (id == OMAP_MCBSP1) {

--			clk_enable(mcbsp1_ick);

--			clk_enable(mcbsp1_fck);

--		} else {

--			clk_enable(mcbsp2_ick);

--			clk_enable(mcbsp2_fck);

--		}

-+	if (!omap_mcbsp_check_valid_id(id)) {

-+		printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);

-+		return -ENODEV;

- 	}

--#endif

-+

-+	if (mcbsp[id].pdata->ops->request)

-+		mcbsp[id].pdata->ops->request(id);

-+

-+	mcbsp_clk_enable(&mcbsp[id]);

- 

- 	spin_lock(&mcbsp[id].lock);

- 	if (!mcbsp[id].free) {

--		printk(KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n",

--			id + 1);

-+		dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n",

-+			mcbsp[id].id);

- 		spin_unlock(&mcbsp[id].lock);

- 		return -1;

- 	}

-@@ -322,9 +211,9 @@ int omap_mcbsp_request(unsigned int id)

- 		err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler,

- 					0, "McBSP", (void *) (&mcbsp[id]));

- 		if (err != 0) {

--			printk(KERN_ERR "OMAP-McBSP: Unable to "

--					"request TX IRQ %d for McBSP%d\n",

--					mcbsp[id].tx_irq, mcbsp[id].id);

-+			dev_err(mcbsp[id].dev, "Unable to request TX IRQ %d "

-+					"for McBSP%d\n", mcbsp[id].tx_irq,

-+					mcbsp[id].id);

- 			return err;

- 		}

- 

-@@ -333,9 +222,9 @@ int omap_mcbsp_request(unsigned int id)

- 		err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler,

- 					0, "McBSP", (void *) (&mcbsp[id]));

- 		if (err != 0) {

--			printk(KERN_ERR "OMAP-McBSP: Unable to "

--					"request RX IRQ %d for McBSP%d\n",

--					mcbsp[id].rx_irq, mcbsp[id].id);

-+			dev_err(mcbsp[id].dev, "Unable to request RX IRQ %d "

-+					"for McBSP%d\n", mcbsp[id].rx_irq,

-+					mcbsp[id].id);

- 			free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));

- 			return err;

- 		}

-@@ -349,32 +238,20 @@ EXPORT_SYMBOL(omap_mcbsp_request);

- 

- void omap_mcbsp_free(unsigned int id)

- {

--	if (omap_mcbsp_check(id) < 0)

-+	if (!omap_mcbsp_check_valid_id(id)) {

-+		printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);

- 		return;

--

--#ifdef CONFIG_ARCH_OMAP1

--	if (cpu_class_is_omap1()) {

--		if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)

--			omap_mcbsp_dsp_free();

- 	}

--#endif

--

--#ifdef CONFIG_ARCH_OMAP2

--	if (cpu_is_omap24xx()) {

--		if (id == OMAP_MCBSP1) {

--			clk_disable(mcbsp1_ick);

--			clk_disable(mcbsp1_fck);

--		} else {

--			clk_disable(mcbsp2_ick);

--			clk_disable(mcbsp2_fck);

--		}

--	}

--#endif

-+

-+	if (mcbsp[id].pdata->ops->free)

-+		mcbsp[id].pdata->ops->free(id);

-+

-+	mcbsp_clk_disable(&mcbsp[id]);

- 

- 	spin_lock(&mcbsp[id].lock);

- 	if (mcbsp[id].free) {

--		printk(KERN_ERR "OMAP-McBSP: McBSP%d was not reserved\n",

--			id + 1);

-+		dev_err(mcbsp[id].dev, "McBSP%d was not reserved\n",

-+			mcbsp[id].id);

- 		spin_unlock(&mcbsp[id].lock);

- 		return;

- 	}

-@@ -400,8 +277,10 @@ void omap_mcbsp_start(unsigned int id)

- 	u32 io_base;

- 	u16 w;

- 

--	if (omap_mcbsp_check(id) < 0)

-+	if (!omap_mcbsp_check_valid_id(id)) {

-+		printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);

- 		return;

-+	}

- 

- 	io_base = mcbsp[id].io_base;

- 

-@@ -435,8 +314,10 @@ void omap_mcbsp_stop(unsigned int id)

- 	u32 io_base;

- 	u16 w;

- 

--	if (omap_mcbsp_check(id) < 0)

-+	if (!omap_mcbsp_check_valid_id(id)) {

-+		printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);

- 		return;

-+	}

- 

- 	io_base = mcbsp[id].io_base;

- 

-@@ -457,7 +338,14 @@ EXPORT_SYMBOL(omap_mcbsp_stop);

- /* polled mcbsp i/o operations */

- int omap_mcbsp_pollwrite(unsigned int id, u16 buf)

- {

--	u32 base = mcbsp[id].io_base;

-+	u32 base;

-+

-+	if (!omap_mcbsp_check_valid_id(id)) {

-+		printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);

-+		return -ENODEV;

-+	}

-+

-+	base = mcbsp[id].io_base;

- 	writew(buf, base + OMAP_MCBSP_REG_DXR1);

- 	/* if frame sync error - clear the error */

- 	if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {

-@@ -479,8 +367,8 @@ int omap_mcbsp_pollwrite(unsigned int id, u16 buf)

- 				       (XRST),

- 				       base + OMAP_MCBSP_REG_SPCR2);

- 				udelay(10);

--				printk(KERN_ERR

--				       " Could not write to McBSP Register\n");

-+				dev_err(mcbsp[id].dev, "Could not write to"

-+					" McBSP%d Register\n", mcbsp[id].id);

- 				return -2;

- 			}

- 		}

-@@ -492,7 +380,14 @@ EXPORT_SYMBOL(omap_mcbsp_pollwrite);

- 

- int omap_mcbsp_pollread(unsigned int id, u16 *buf)

- {

--	u32 base = mcbsp[id].io_base;

-+	u32 base;

-+

-+	if (!omap_mcbsp_check_valid_id(id)) {

-+		printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);

-+		return -ENODEV;

-+	}

-+

-+	base = mcbsp[id].io_base;

- 	/* if frame sync error - clear the error */

- 	if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {

- 		/* clear error */

-@@ -513,8 +408,8 @@ int omap_mcbsp_pollread(unsigned int id, u16 *buf)

- 				       (RRST),

- 				       base + OMAP_MCBSP_REG_SPCR1);

- 				udelay(10);

--				printk(KERN_ERR

--				       " Could not read from McBSP Register\n");

-+				dev_err(mcbsp[id].dev, "Could not read from"

-+					" McBSP%d Register\n", mcbsp[id].id);

- 				return -2;

- 			}

- 		}

-@@ -531,12 +426,15 @@ EXPORT_SYMBOL(omap_mcbsp_pollread);

- void omap_mcbsp_xmit_word(unsigned int id, u32 word)

- {

- 	u32 io_base;

--	omap_mcbsp_word_length word_length = mcbsp[id].tx_word_length;

-+	omap_mcbsp_word_length word_length;

- 

--	if (omap_mcbsp_check(id) < 0)

-+	if (!omap_mcbsp_check_valid_id(id)) {

-+		printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);

- 		return;

-+	}

- 

- 	io_base = mcbsp[id].io_base;

-+	word_length = mcbsp[id].tx_word_length;

- 

- 	wait_for_completion(&(mcbsp[id].tx_irq_completion));

- 

-@@ -550,11 +448,14 @@ u32 omap_mcbsp_recv_word(unsigned int id)

- {

- 	u32 io_base;

- 	u16 word_lsb, word_msb = 0;

--	omap_mcbsp_word_length word_length = mcbsp[id].rx_word_length;

-+	omap_mcbsp_word_length word_length;

- 

--	if (omap_mcbsp_check(id) < 0)

--		return -EINVAL;

-+	if (!omap_mcbsp_check_valid_id(id)) {

-+		printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);

-+		return -ENODEV;

-+	}

- 

-+	word_length = mcbsp[id].rx_word_length;

- 	io_base = mcbsp[id].io_base;

- 

- 	wait_for_completion(&(mcbsp[id].rx_irq_completion));

-@@ -569,11 +470,20 @@ EXPORT_SYMBOL(omap_mcbsp_recv_word);

- 

- int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)

- {

--	u32 io_base = mcbsp[id].io_base;

--	omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;

--	omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;

-+	u32 io_base;

-+	omap_mcbsp_word_length tx_word_length;

-+	omap_mcbsp_word_length rx_word_length;

- 	u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;

- 

-+	if (!omap_mcbsp_check_valid_id(id)) {

-+		printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);

-+		return -ENODEV;

-+	}

-+

-+	io_base = mcbsp[id].io_base;

-+	tx_word_length = mcbsp[id].tx_word_length;

-+	rx_word_length = mcbsp[id].rx_word_length;

-+

- 	if (tx_word_length != rx_word_length)

- 		return -EINVAL;

- 

-@@ -587,7 +497,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)

- 			udelay(10);

- 			OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);

- 			udelay(10);

--			printk(KERN_ERR "McBSP transmitter not ready\n");

-+			dev_err(mcbsp[id].dev, "McBSP%d transmitter not "

-+				"ready\n", mcbsp[id].id);

- 			return -EAGAIN;

- 		}

- 	}

-@@ -607,7 +518,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)

- 			udelay(10);

- 			OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);

- 			udelay(10);

--			printk(KERN_ERR "McBSP receiver not ready\n");

-+			dev_err(mcbsp[id].dev, "McBSP%d receiver not "

-+				"ready\n", mcbsp[id].id);

- 			return -EAGAIN;

- 		}

- 	}

-@@ -623,11 +535,20 @@ EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);

- 

- int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)

- {

--	u32 io_base = mcbsp[id].io_base, clock_word = 0;

--	omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;

--	omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;

-+	u32 io_base, clock_word = 0;

-+	omap_mcbsp_word_length tx_word_length;

-+	omap_mcbsp_word_length rx_word_length;

- 	u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;

- 

-+	if (!omap_mcbsp_check_valid_id(id)) {

-+		printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);

-+		return -ENODEV;

-+	}

-+

-+	io_base = mcbsp[id].io_base;

-+	tx_word_length = mcbsp[id].tx_word_length;

-+	rx_word_length = mcbsp[id].rx_word_length;

-+

- 	if (tx_word_length != rx_word_length)

- 		return -EINVAL;

- 

-@@ -641,7 +562,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)

- 			udelay(10);

- 			OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);

- 			udelay(10);

--			printk(KERN_ERR "McBSP transmitter not ready\n");

-+			dev_err(mcbsp[id].dev, "McBSP%d transmitter not "

-+				"ready\n", mcbsp[id].id);

- 			return -EAGAIN;

- 		}

- 	}

-@@ -661,7 +583,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)

- 			udelay(10);

- 			OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);

- 			udelay(10);

--			printk(KERN_ERR "McBSP receiver not ready\n");

-+			dev_err(mcbsp[id].dev, "McBSP%d receiver not "

-+				"ready\n", mcbsp[id].id);

- 			return -EAGAIN;

- 		}

- 	}

-@@ -692,20 +615,24 @@ int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,

- 	int dest_port = 0;

- 	int sync_dev = 0;

- 

--	if (omap_mcbsp_check(id) < 0)

--		return -EINVAL;

-+	if (!omap_mcbsp_check_valid_id(id)) {

-+		printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);

-+		return -ENODEV;

-+	}

- 

- 	if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX",

- 				omap_mcbsp_tx_dma_callback,

- 				&mcbsp[id],

- 				&dma_tx_ch)) {

--		printk(KERN_ERR "OMAP-McBSP: Unable to request DMA channel for"

--				" McBSP%d TX. Trying IRQ based TX\n", id + 1);

-+		dev_err(mcbsp[id].dev, " Unable to request DMA channel for "

-+				"McBSP%d TX. Trying IRQ based TX\n",

-+				mcbsp[id].id);

- 		return -EAGAIN;

- 	}

- 	mcbsp[id].dma_tx_lch = dma_tx_ch;

- 

--	DBG("TX DMA on channel %d\n", dma_tx_ch);

-+	dev_err(mcbsp[id].dev, "McBSP%d TX DMA on channel %d\n", mcbsp[id].id,

-+		dma_tx_ch);

- 

- 	init_completion(&(mcbsp[id].tx_dma_completion));

- 

-@@ -713,7 +640,7 @@ int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,

- 		src_port = OMAP_DMA_PORT_TIPB;

- 		dest_port = OMAP_DMA_PORT_EMIFF;

- 	}

--	if (cpu_is_omap24xx())

-+	if (cpu_class_is_omap2())

- 		sync_dev = mcbsp[id].dma_tx_sync;

- 

- 	omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,

-@@ -749,20 +676,24 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,

- 	int dest_port = 0;

- 	int sync_dev = 0;

- 

--	if (omap_mcbsp_check(id) < 0)

--		return -EINVAL;

-+	if (!omap_mcbsp_check_valid_id(id)) {

-+		printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);

-+		return -ENODEV;

-+	}

- 

- 	if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX",

- 				omap_mcbsp_rx_dma_callback,

- 				&mcbsp[id],

- 				&dma_rx_ch)) {

--		printk(KERN_ERR "Unable to request DMA channel for McBSP%d RX."

--				" Trying IRQ based RX\n", id + 1);

-+		dev_err(mcbsp[id].dev, "Unable to request DMA channel for "

-+				"McBSP%d RX. Trying IRQ based RX\n",

-+				mcbsp[id].id);

- 		return -EAGAIN;

- 	}

- 	mcbsp[id].dma_rx_lch = dma_rx_ch;

- 

--	DBG("RX DMA on channel %d\n", dma_rx_ch);

-+	dev_err(mcbsp[id].dev, "McBSP%d RX DMA on channel %d\n", mcbsp[id].id,

-+		dma_rx_ch);

- 

- 	init_completion(&(mcbsp[id].rx_dma_completion));

- 

-@@ -770,7 +701,7 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,

- 		src_port = OMAP_DMA_PORT_TIPB;

- 		dest_port = OMAP_DMA_PORT_EMIFF;

- 	}

--	if (cpu_is_omap24xx())

-+	if (cpu_class_is_omap2())

- 		sync_dev = mcbsp[id].dma_rx_sync;

- 

- 	omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,

-@@ -809,8 +740,10 @@ void omap_mcbsp_set_spi_mode(unsigned int id,

- {

- 	struct omap_mcbsp_reg_cfg mcbsp_cfg;

- 

--	if (omap_mcbsp_check(id) < 0)

-+	if (!omap_mcbsp_check_valid_id(id)) {

-+		printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);

- 		return;

-+	}

- 

- 	memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));

- 

-@@ -871,182 +804,91 @@ EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);

-  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.

-  * 730 has only 2 McBSP, and both of them are MPU peripherals.

-  */

--struct omap_mcbsp_info {

--	u32 virt_base;

--	u8 dma_rx_sync, dma_tx_sync;

--	u16 rx_irq, tx_irq;

--};

-+static int __init omap_mcbsp_probe(struct platform_device *pdev)

-+{

-+	struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;

-+	int id = pdev->id - 1;

-+	int ret = 0;

-+	int i;

- 

--#ifdef CONFIG_ARCH_OMAP730

--static const struct omap_mcbsp_info mcbsp_730[] = {

--	[0] = { .virt_base = io_p2v(OMAP730_MCBSP1_BASE),

--		.dma_rx_sync = OMAP_DMA_MCBSP1_RX,

--		.dma_tx_sync = OMAP_DMA_MCBSP1_TX,

--		.rx_irq = INT_730_McBSP1RX,

--		.tx_irq = INT_730_McBSP1TX },

--	[1] = { .virt_base = io_p2v(OMAP730_MCBSP2_BASE),

--		.dma_rx_sync = OMAP_DMA_MCBSP3_RX,

--		.dma_tx_sync = OMAP_DMA_MCBSP3_TX,

--		.rx_irq = INT_730_McBSP2RX,

--		.tx_irq = INT_730_McBSP2TX },

--};

--#endif

--

--#ifdef CONFIG_ARCH_OMAP15XX

--static const struct omap_mcbsp_info mcbsp_1510[] = {

--	[0] = { .virt_base = OMAP1510_MCBSP1_BASE,

--		.dma_rx_sync = OMAP_DMA_MCBSP1_RX,

--		.dma_tx_sync = OMAP_DMA_MCBSP1_TX,

--		.rx_irq = INT_McBSP1RX,

--		.tx_irq = INT_McBSP1TX },

--	[1] = { .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),

--		.dma_rx_sync = OMAP_DMA_MCBSP2_RX,

--		.dma_tx_sync = OMAP_DMA_MCBSP2_TX,

--		.rx_irq = INT_1510_SPI_RX,

--		.tx_irq = INT_1510_SPI_TX },

--	[2] = { .virt_base = OMAP1510_MCBSP3_BASE,

--		.dma_rx_sync = OMAP_DMA_MCBSP3_RX,

--		.dma_tx_sync = OMAP_DMA_MCBSP3_TX,

--		.rx_irq = INT_McBSP3RX,

--		.tx_irq = INT_McBSP3TX },

--};

--#endif

--

--#if defined(CONFIG_ARCH_OMAP16XX)

--static const struct omap_mcbsp_info mcbsp_1610[] = {

--	[0] = { .virt_base = OMAP1610_MCBSP1_BASE,

--		.dma_rx_sync = OMAP_DMA_MCBSP1_RX,

--		.dma_tx_sync = OMAP_DMA_MCBSP1_TX,

--		.rx_irq = INT_McBSP1RX,

--		.tx_irq = INT_McBSP1TX },

--	[1] = { .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),

--		.dma_rx_sync = OMAP_DMA_MCBSP2_RX,

--		.dma_tx_sync = OMAP_DMA_MCBSP2_TX,

--		.rx_irq = INT_1610_McBSP2_RX,

--		.tx_irq = INT_1610_McBSP2_TX },

--	[2] = { .virt_base = OMAP1610_MCBSP3_BASE,

--		.dma_rx_sync = OMAP_DMA_MCBSP3_RX,

--		.dma_tx_sync = OMAP_DMA_MCBSP3_TX,

--		.rx_irq = INT_McBSP3RX,

--		.tx_irq = INT_McBSP3TX },

--};

--#endif

--

--#if defined(CONFIG_ARCH_OMAP24XX)

--static const struct omap_mcbsp_info mcbsp_24xx[] = {

--	[0] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),

--		.dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,

--		.dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,

--		.rx_irq = INT_24XX_MCBSP1_IRQ_RX,

--		.tx_irq = INT_24XX_MCBSP1_IRQ_TX,

--		},

--	[1] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),

--		.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,

--		.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,

--		.rx_irq = INT_24XX_MCBSP2_IRQ_RX,

--		.tx_irq = INT_24XX_MCBSP2_IRQ_TX,

--		},

--};

--#endif

-+	if (!pdata) {

-+		dev_err(&pdev->dev, "McBSP device initialized without"

-+				"platform data\n");

-+		ret = -EINVAL;

-+		goto exit;

-+	}

- 

--static int __init omap_mcbsp_init(void)

-+	dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);

-+

-+	if (id >= OMAP_MAX_MCBSP_COUNT) {

-+		dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);

-+		ret = -EINVAL;

-+		goto exit;

-+	}

-+

-+	spin_lock_init(&mcbsp[id].lock);

-+	mcbsp[id].id = id + 1;

-+	mcbsp[id].free = 1;

-+	mcbsp[id].dma_tx_lch = -1;

-+	mcbsp[id].dma_rx_lch = -1;

-+

-+	mcbsp[id].io_base = pdata->virt_base;

-+	/* Default I/O is IRQ based */

-+	mcbsp[id].io_type = OMAP_MCBSP_IRQ_IO;

-+	mcbsp[id].tx_irq = pdata->tx_irq;

-+	mcbsp[id].rx_irq = pdata->rx_irq;

-+	mcbsp[id].dma_rx_sync = pdata->dma_rx_sync;

-+	mcbsp[id].dma_tx_sync = pdata->dma_tx_sync;

-+

-+	mcbsp[id].nr_clocks = ARRAY_SIZE(pdata->clocks);

-+	for (i = 0; i < ARRAY_SIZE(pdata->clocks); i++)

-+		mcbsp[id].clocks[i] = clk_get(&pdev->dev, pdata->clocks[i]);

-+

-+	mcbsp[id].pdata = pdata;

-+	mcbsp[id].dev = &pdev->dev;

-+	platform_set_drvdata(pdev, &mcbsp[id]);

-+

-+exit:

-+	return ret;

-+}

-+

-+static int omap_mcbsp_remove(struct platform_device *pdev)

- {

--	int mcbsp_count = 0, i;

--	static const struct omap_mcbsp_info *mcbsp_info;

-+	struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);

- 

--	printk(KERN_INFO "Initializing OMAP McBSP system\n");

-+	platform_set_drvdata(pdev, NULL);

-+	if (mcbsp) {

-+		int i;

- 

--#ifdef CONFIG_ARCH_OMAP1

--	mcbsp_dsp_ck = clk_get(0, "dsp_ck");

--	if (IS_ERR(mcbsp_dsp_ck)) {

--		printk(KERN_ERR "mcbsp: could not acquire dsp_ck handle.\n");

--		return PTR_ERR(mcbsp_dsp_ck);

--	}

--	mcbsp_api_ck = clk_get(0, "api_ck");

--	if (IS_ERR(mcbsp_api_ck)) {

--		printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n");

--		return PTR_ERR(mcbsp_api_ck);

--	}

--	mcbsp_dspxor_ck = clk_get(0, "dspxor_ck");

--	if (IS_ERR(mcbsp_dspxor_ck)) {

--		printk(KERN_ERR "mcbsp: could not acquire dspxor_ck handle.\n");

--		return PTR_ERR(mcbsp_dspxor_ck);

--	}

--#endif

--#ifdef CONFIG_ARCH_OMAP2

--	mcbsp1_ick = clk_get(0, "mcbsp1_ick");

--	if (IS_ERR(mcbsp1_ick)) {

--		printk(KERN_ERR "mcbsp: could not acquire "

--				"mcbsp1_ick handle.\n");

--		return PTR_ERR(mcbsp1_ick);

--	}

--	mcbsp1_fck = clk_get(0, "mcbsp1_fck");

--	if (IS_ERR(mcbsp1_fck)) {

--		printk(KERN_ERR "mcbsp: could not acquire "

--				"mcbsp1_fck handle.\n");

--		return PTR_ERR(mcbsp1_fck);

--	}

--	mcbsp2_ick = clk_get(0, "mcbsp2_ick");

--	if (IS_ERR(mcbsp2_ick)) {

--		printk(KERN_ERR "mcbsp: could not acquire "

--				"mcbsp2_ick handle.\n");

--		return PTR_ERR(mcbsp2_ick);

--	}

--	mcbsp2_fck = clk_get(0, "mcbsp2_fck");

--	if (IS_ERR(mcbsp2_fck)) {

--		printk(KERN_ERR "mcbsp: could not acquire "

--				"mcbsp2_fck handle.\n");

--		return PTR_ERR(mcbsp2_fck);

--	}

--#endif

-+		if (mcbsp->pdata && mcbsp->pdata->ops &&

-+				mcbsp->pdata->ops->free)

-+			mcbsp->pdata->ops->free(mcbsp->id);

- 

--#ifdef CONFIG_ARCH_OMAP730

--	if (cpu_is_omap730()) {

--		mcbsp_info = mcbsp_730;

--		mcbsp_count = ARRAY_SIZE(mcbsp_730);

--	}

--#endif

--#ifdef CONFIG_ARCH_OMAP15XX

--	if (cpu_is_omap15xx()) {

--		mcbsp_info = mcbsp_1510;

--		mcbsp_count = ARRAY_SIZE(mcbsp_1510);

--	}

--#endif

--#if defined(CONFIG_ARCH_OMAP16XX)

--	if (cpu_is_omap16xx()) {

--		mcbsp_info = mcbsp_1610;

--		mcbsp_count = ARRAY_SIZE(mcbsp_1610);

--	}

--#endif

--#if defined(CONFIG_ARCH_OMAP24XX)

--	if (cpu_is_omap24xx()) {

--		mcbsp_info = mcbsp_24xx;

--		mcbsp_count = ARRAY_SIZE(mcbsp_24xx);

--		omap2_mcbsp2_mux_setup();

--	}

--#endif

--	for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {

--		if (i >= mcbsp_count) {

--			mcbsp[i].io_base = 0;

--			mcbsp[i].free = 0;

--			continue;

--		}

--		mcbsp[i].id = i + 1;

--		mcbsp[i].free = 1;

--		mcbsp[i].dma_tx_lch = -1;

--		mcbsp[i].dma_rx_lch = -1;

--

--		mcbsp[i].io_base = mcbsp_info[i].virt_base;

--		/* Default I/O is IRQ based */

--		mcbsp[i].io_type = OMAP_MCBSP_IRQ_IO;

--		mcbsp[i].tx_irq = mcbsp_info[i].tx_irq;

--		mcbsp[i].rx_irq = mcbsp_info[i].rx_irq;

--		mcbsp[i].dma_rx_sync = mcbsp_info[i].dma_rx_sync;

--		mcbsp[i].dma_tx_sync = mcbsp_info[i].dma_tx_sync;

--		spin_lock_init(&mcbsp[i].lock);

-+		mcbsp_clk_disable(mcbsp);

-+		mcbsp_clk_put(mcbsp);

-+

-+		for (i = 0; i < mcbsp->nr_clocks; i++)

-+			mcbsp->clocks[i] = NULL;

-+

-+		mcbsp->free = 0;

-+		mcbsp->dev = NULL;

- 	}

- 

- 	return 0;

- }

- 

--arch_initcall(omap_mcbsp_init);

-+static struct platform_driver omap_mcbsp_driver = {

-+	.probe		= omap_mcbsp_probe,

-+	.remove		= omap_mcbsp_remove,

-+	.driver		= {

-+		.name	= "omap-mcbsp",

-+	},

-+};

-+

-+int __init omap_mcbsp_init(void)

-+{

-+	/* Register the McBSP driver */

-+	return platform_driver_register(&omap_mcbsp_driver);

-+}

-+

-+

-diff --git a/include/asm-arm/arch-omap/mcbsp.h b/include/asm-arm/arch-omap/mcbsp.h

-index b53c3b2..aa47421 100644

---- a/include/asm-arm/arch-omap/mcbsp.h

-+++ b/include/asm-arm/arch-omap/mcbsp.h

-@@ -24,7 +24,11 @@

- #ifndef __ASM_ARCH_OMAP_MCBSP_H

- #define __ASM_ARCH_OMAP_MCBSP_H

- 

-+#include <linux/completion.h>

-+#include <linux/spinlock.h>

-+

- #include <asm/hardware.h>

-+#include <asm/arch/clock.h>

- 

- #define OMAP730_MCBSP1_BASE	0xfffb1000

- #define OMAP730_MCBSP2_BASE	0xfffb1800

-@@ -40,6 +44,9 @@

- #define OMAP24XX_MCBSP1_BASE	0x48074000

- #define OMAP24XX_MCBSP2_BASE	0x48076000

- 

-+#define OMAP34XX_MCBSP1_BASE	0x48074000

-+#define OMAP34XX_MCBSP2_BASE	0x49022000

-+

- #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)

- 

- #define OMAP_MCBSP_REG_DRR2	0x00

-@@ -74,7 +81,8 @@

- #define OMAP_MCBSP_REG_XCERG	0x3A

- #define OMAP_MCBSP_REG_XCERH	0x3C

- 

--#define OMAP_MAX_MCBSP_COUNT 3

-+#define OMAP_MAX_MCBSP_COUNT	3

-+#define MAX_MCBSP_CLOCKS	3

- 

- #define AUDIO_MCBSP_DATAWRITE	(OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)

- #define AUDIO_MCBSP_DATAREAD	(OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)

-@@ -117,7 +125,8 @@

- #define OMAP_MCBSP_REG_XCERG	0x74

- #define OMAP_MCBSP_REG_XCERH	0x78

- 

--#define OMAP_MAX_MCBSP_COUNT 2

-+#define OMAP_MAX_MCBSP_COUNT	2

-+#define MAX_MCBSP_CLOCKS	2

- 

- #define AUDIO_MCBSP_DATAWRITE	(OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)

- #define AUDIO_MCBSP_DATAREAD	(OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)

-@@ -298,6 +307,66 @@ struct omap_mcbsp_spi_cfg {

- 	omap_mcbsp_word_length		word_length;

- };

- 

-+/* Platform specific configuration */

-+struct omap_mcbsp_ops {

-+	void (*request)(unsigned int);

-+	void (*free)(unsigned int);

-+	int (*check)(unsigned int);

-+};

-+

-+struct omap_mcbsp_platform_data {

-+	u32 virt_base;

-+	u8 dma_rx_sync, dma_tx_sync;

-+	u16 rx_irq, tx_irq;

-+	struct omap_mcbsp_ops *ops;

-+	char const *clocks[MAX_MCBSP_CLOCKS];

-+};

-+

-+struct omap_mcbsp {

-+	struct device *dev;

-+	u32 io_base;

-+	u8 id;

-+	u8 free;

-+	omap_mcbsp_word_length rx_word_length;

-+	omap_mcbsp_word_length tx_word_length;

-+

-+	omap_mcbsp_io_type_t io_type; /* IRQ or poll */

-+	/* IRQ based TX/RX */

-+	int rx_irq;

-+	int tx_irq;

-+

-+	/* DMA stuff */

-+	u8 dma_rx_sync;

-+	short dma_rx_lch;

-+	u8 dma_tx_sync;

-+	short dma_tx_lch;

-+

-+	/* Completion queues */

-+	struct completion tx_irq_completion;

-+	struct completion rx_irq_completion;

-+	struct completion tx_dma_completion;

-+	struct completion rx_dma_completion;

-+

-+	/* Protect the field .free, while checking if the mcbsp is in use */

-+	spinlock_t lock;

-+	struct omap_mcbsp_platform_data *pdata;

-+	int nr_clocks;

-+	struct clk *clocks[MAX_MCBSP_CLOCKS];

-+};

-+

-+#define __mcbsp_clk_op(mcbsp, op)				\

-+	do {							\

-+		int i;						\

-+		for (i = 0; i < mcbsp->nr_clocks; i++)		\

-+			clk_##op(mcbsp->clocks[i]); 		\

-+	} while (0)

-+#define mcbsp_clk_enable(mcbsp)		__mcbsp_clk_op((mcbsp), enable)

-+#define mcbsp_clk_disable(mcbsp)	__mcbsp_clk_op((mcbsp), disable)

-+#define mcbsp_clk_put(mcbsp)		__mcbsp_clk_op((mcbsp), put)

-+

-+int omap_mcbsp_init(void);

-+void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,

-+					int size);

- void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);

- int omap_mcbsp_request(unsigned int id);

- void omap_mcbsp_free(unsigned int id);

--- 

-1.5.5.1.67.gbdb8.dirty

-

---

-To unsubscribe from this list: send the line "unsubscribe linux-omap" in

-the body of a message to majordomo@vger.kernel.org

-More majordomo info at  http://vger.kernel.org/majordomo-info.html

-

diff --git a/packages/linux/linux-omap2-git/beagleboard/00002-mcbsp-omap1.patch b/packages/linux/linux-omap2-git/beagleboard/00002-mcbsp-omap1.patch
deleted file mode 100644
index 76246a9fae..0000000000
--- a/packages/linux/linux-omap2-git/beagleboard/00002-mcbsp-omap1.patch
+++ /dev/null
@@ -1,204 +0,0 @@
-From: Eduardo Valentin <eduardo.valentin@indt.org.br>

-

-This patch adds support for mach-omap1 based on current

-mcbsp platform driver.

-

-Signed-off-by: Eduardo Valentin <eduardo.valentin@indt.org.br>

----

- arch/arm/mach-omap1/Makefile |    2 +

- arch/arm/mach-omap1/mcbsp.c  |  165 ++++++++++++++++++++++++++++++++++++++++++

- 2 files changed, 167 insertions(+), 0 deletions(-)

- create mode 100644 arch/arm/mach-omap1/mcbsp.c

-

-diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile

-index 6ebf23b..09246a7 100644

---- a/arch/arm/mach-omap1/Makefile

-+++ b/arch/arm/mach-omap1/Makefile

-@@ -5,6 +5,8 @@

- # Common support

- obj-y := io.o id.o clock.o irq.o mux.o serial.o devices.o

- 

-+obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o

-+

- obj-$(CONFIG_OMAP_MPU_TIMER)	+= time.o

- obj-$(CONFIG_OMAP_32K_TIMER)	+= timer32k.o

- 

-diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c

-new file mode 100644

-index 0000000..f30624a

---- /dev/null

-+++ b/arch/arm/mach-omap1/mcbsp.c

-@@ -0,0 +1,165 @@

-+/*

-+ * linux/arch/arm/mach-omap1/mcbsp.c

-+ *

-+ * Copyright (C) 2008 Instituto Nokia de Tecnologia

-+ * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>

-+ *

-+ * This program is free software; you can redistribute it and/or modify

-+ * it under the terms of the GNU General Public License version 2 as

-+ * published by the Free Software Foundation.

-+ *

-+ * Multichannel mode not supported.

-+ */

-+#include <linux/module.h>

-+#include <linux/init.h>

-+#include <linux/clk.h>

-+#include <linux/err.h>

-+#include <linux/io.h>

-+

-+#include <asm/arch/dma.h>

-+#include <asm/arch/mux.h>

-+#include <asm/arch/cpu.h>

-+#include <asm/arch/mcbsp.h>

-+#include <asm/arch/dsp_common.h>

-+

-+#define DPS_RSTCT2_PER_EN	(1 << 0)

-+#define DSP_RSTCT2_WD_PER_EN	(1 << 1)

-+

-+static int omap1_mcbsp_check(unsigned int id)

-+{

-+	/* REVISIT: Check correctly for number of registered McBSPs */

-+	if (cpu_is_omap730()) {

-+		if (id > OMAP_MAX_MCBSP_COUNT - 2) {

-+		       printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",

-+				id + 1);

-+		       return -ENODEV;

-+		}

-+		return 0;

-+	}

-+

-+	if (cpu_is_omap15xx() || cpu_is_omap16xx()) {

-+		if (id > OMAP_MAX_MCBSP_COUNT - 1) {

-+			printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",

-+				id + 1);

-+			return -ENODEV;

-+		}

-+		return 0;

-+	}

-+

-+	return -ENODEV;

-+}

-+

-+static void omap1_mcbsp_request(unsigned int id)

-+{

-+	/*

-+	 * On 1510, 1610 and 1710, McBSP1 and McBSP3

-+	 * are DSP public peripherals.

-+	 */

-+	if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {

-+		omap_dsp_request_mem();

-+		/*

-+		 * DSP external peripheral reset

-+		 * FIXME: This should be moved to dsp code

-+		 */

-+		__raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN |

-+				DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2);

-+	}

-+}

-+

-+static void omap1_mcbsp_free(unsigned int id)

-+{

-+	if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)

-+		omap_dsp_release_mem();

-+}

-+

-+static struct omap_mcbsp_ops omap1_mcbsp_ops = {

-+	.check		= omap1_mcbsp_check,

-+	.request	= omap1_mcbsp_request,

-+	.free		= omap1_mcbsp_free,

-+};

-+

-+static struct omap_mcbsp_platform_data omap1_mcbsp_pdata[] = {

-+#ifdef CONFIG_ARCH_OMAP730

-+	{

-+		.virt_base	= io_p2v(OMAP730_MCBSP1_BASE),

-+		.dma_rx_sync	= OMAP_DMA_MCBSP1_RX,

-+		.dma_tx_sync	= OMAP_DMA_MCBSP1_TX,

-+		.rx_irq		= INT_730_McBSP1RX,

-+		.tx_irq		= INT_730_McBSP1TX,

-+		.ops		= &omap1_mcbsp_ops,

-+	},

-+	{

-+		.virt_base	= io_p2v(OMAP730_MCBSP2_BASE),

-+		.dma_rx_sync	= OMAP_DMA_MCBSP3_RX,

-+		.dma_tx_sync	= OMAP_DMA_MCBSP3_TX,

-+		.rx_irq		= INT_730_McBSP2RX,

-+		.tx_irq		= INT_730_McBSP2TX

-+		.ops		= &omap1_mcbsp_ops,

-+	},

-+#endif

-+#ifdef CONFIG_ARCH_OMAP15XX

-+	{

-+		.virt_base	= OMAP1510_MCBSP1_BASE,

-+		.dma_rx_sync	= OMAP_DMA_MCBSP1_RX,

-+		.dma_tx_sync	= OMAP_DMA_MCBSP1_TX,

-+		.rx_irq		= INT_McBSP1RX,

-+		.tx_irq		= INT_McBSP1TX,

-+		.ops		= &omap1_mcbsp_ops,

-+		.clocks		= { "dsp_ck", "api_ck", "dspxor_ck" },

-+		},

-+	{

-+		.virt_base	= io_p2v(OMAP1510_MCBSP2_BASE),

-+		.dma_rx_sync	= OMAP_DMA_MCBSP2_RX,

-+		.dma_tx_sync	= OMAP_DMA_MCBSP2_TX,

-+		.rx_irq		= INT_1510_SPI_RX,

-+		.tx_irq		= INT_1510_SPI_TX,

-+		.ops		= &omap1_mcbsp_ops,

-+	},

-+	{

-+		.virt_base	= OMAP1510_MCBSP3_BASE,

-+		.dma_rx_sync	= OMAP_DMA_MCBSP3_RX,

-+		.dma_tx_sync	= OMAP_DMA_MCBSP3_TX,

-+		.rx_irq		= INT_McBSP3RX,

-+		.tx_irq		= INT_McBSP3TX,

-+		.ops		= &omap1_mcbsp_ops,

-+		.clocks		= { "dsp_ck", "api_ck", "dspxor_ck" },

-+	},

-+#endif

-+#ifdef CONFIG_ARCH_OMAP16XX

-+	{

-+		.virt_base	= OMAP1610_MCBSP1_BASE,

-+		.dma_rx_sync	= OMAP_DMA_MCBSP1_RX,

-+		.dma_tx_sync	= OMAP_DMA_MCBSP1_TX,

-+		.rx_irq		= INT_McBSP1RX,

-+		.tx_irq		= INT_McBSP1TX,

-+		.ops		= &omap1_mcbsp_ops,

-+		.clocks		= { "dsp_ck", "api_ck", "dspxor_ck" },

-+	},

-+	{

-+		.virt_base	= io_p2v(OMAP1610_MCBSP2_BASE),

-+		.dma_rx_sync	= OMAP_DMA_MCBSP2_RX,

-+		.dma_tx_sync	= OMAP_DMA_MCBSP2_TX,

-+		.rx_irq		= INT_1610_McBSP2_RX,

-+		.tx_irq		= INT_1610_McBSP2_TX,

-+		.ops		= &omap1_mcbsp_ops,

-+	},

-+	{

-+		.virt_base	= OMAP1610_MCBSP3_BASE,

-+		.dma_rx_sync	= OMAP_DMA_MCBSP3_RX,

-+		.dma_tx_sync	= OMAP_DMA_MCBSP3_TX,

-+		.rx_irq		= INT_McBSP3RX,

-+		.tx_irq		= INT_McBSP3TX,

-+		.ops		= &omap1_mcbsp_ops,

-+		.clocks		= { "dsp_ck", "api_ck", "dspxor_ck" },

-+	},

-+#endif

-+};

-+#define mcbsp_count		ARRAY_SIZE(omap1_mcbsp_pdata)

-+

-+int __init omap1_mcbsp_init(void)

-+{

-+	omap_mcbsp_register_board_cfg(omap1_mcbsp_pdata, mcbsp_count);

-+

-+	return omap_mcbsp_init();

-+}

-+arch_initcall(omap1_mcbsp_init);

--- 

-1.5.5.1.67.gbdb8.dirty

-

---

-To unsubscribe from this list: send the line "unsubscribe linux-omap" in

-the body of a message to majordomo@vger.kernel.org

-More majordomo info at  http://vger.kernel.org/majordomo-info.html

-

diff --git a/packages/linux/linux-omap2-git/beagleboard/00003-mcbsp-omap3-clock.patch b/packages/linux/linux-omap2-git/beagleboard/00003-mcbsp-omap3-clock.patch
deleted file mode 100644
index 6d1e7d3f71..0000000000
--- a/packages/linux/linux-omap2-git/beagleboard/00003-mcbsp-omap3-clock.patch
+++ /dev/null
@@ -1,123 +0,0 @@
-From: Eduardo Valentin <eduardo.valentin@indt.org.br>

-

-This patch fix the clock definition for mcbsps on clock34xx.h.

-Device identification must be done using .id field, not

-only name field.

-

-Signed-off-by: Eduardo Valentin <eduardo.valentin@indt.org.br>

----

- arch/arm/mach-omap2/clock34xx.h |   30 ++++++++++++++++++++----------

- 1 files changed, 20 insertions(+), 10 deletions(-)

-

-diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h

-index 85afe1e..3fea82e 100644

---- a/arch/arm/mach-omap2/clock34xx.h

-+++ b/arch/arm/mach-omap2/clock34xx.h

-@@ -1480,7 +1480,8 @@ static const struct clksel mcbsp_15_clksel[] = {

- };

- 

- static struct clk mcbsp5_fck = {

--	.name		= "mcbsp5_fck",

-+	.name		= "mcbsp_fck",

-+	.id		= 5,

- 	.init		= &omap2_init_clksel_parent,

- 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),

- 	.enable_bit	= OMAP3430_EN_MCBSP5_SHIFT,

-@@ -1493,7 +1494,8 @@ static struct clk mcbsp5_fck = {

- };

- 

- static struct clk mcbsp1_fck = {

--	.name		= "mcbsp1_fck",

-+	.name		= "mcbsp_fck",

-+	.id		= 1,

- 	.init		= &omap2_init_clksel_parent,

- 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),

- 	.enable_bit	= OMAP3430_EN_MCBSP1_SHIFT,

-@@ -1941,7 +1943,8 @@ static struct clk gpt10_ick = {

- };

- 

- static struct clk mcbsp5_ick = {

--	.name		= "mcbsp5_ick",

-+	.name		= "mcbsp_ick",

-+	.id		= 5,

- 	.parent		= &core_l4_ick,

- 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

- 	.enable_bit	= OMAP3430_EN_MCBSP5_SHIFT,

-@@ -1951,7 +1954,8 @@ static struct clk mcbsp5_ick = {

- };

- 

- static struct clk mcbsp1_ick = {

--	.name		= "mcbsp1_ick",

-+	.name		= "mcbsp_ick",

-+	.id		= 1,

- 	.parent		= &core_l4_ick,

- 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),

- 	.enable_bit	= OMAP3430_EN_MCBSP1_SHIFT,

-@@ -2754,7 +2758,8 @@ static struct clk gpt2_ick = {

- };

- 

- static struct clk mcbsp2_ick = {

--	.name		= "mcbsp2_ick",

-+	.name		= "mcbsp_ick",

-+	.id		= 2,

- 	.parent		= &per_l4_ick,

- 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),

- 	.enable_bit	= OMAP3430_EN_MCBSP2_SHIFT,

-@@ -2764,7 +2769,8 @@ static struct clk mcbsp2_ick = {

- };

- 

- static struct clk mcbsp3_ick = {

--	.name		= "mcbsp3_ick",

-+	.name		= "mcbsp_ick",

-+	.id		= 3,

- 	.parent		= &per_l4_ick,

- 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),

- 	.enable_bit	= OMAP3430_EN_MCBSP3_SHIFT,

-@@ -2774,7 +2780,8 @@ static struct clk mcbsp3_ick = {

- };

- 

- static struct clk mcbsp4_ick = {

--	.name		= "mcbsp4_ick",

-+	.name		= "mcbsp_ick",

-+	.id		= 4,

- 	.parent		= &per_l4_ick,

- 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),

- 	.enable_bit	= OMAP3430_EN_MCBSP4_SHIFT,

-@@ -2790,7 +2797,8 @@ static const struct clksel mcbsp_234_clksel[] = {

- };

- 

- static struct clk mcbsp2_fck = {

--	.name		= "mcbsp2_fck",

-+	.name		= "mcbsp_fck",

-+	.id		= 2,

- 	.init		= &omap2_init_clksel_parent,

- 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),

- 	.enable_bit	= OMAP3430_EN_MCBSP2_SHIFT,

-@@ -2803,7 +2811,8 @@ static struct clk mcbsp2_fck = {

- };

- 

- static struct clk mcbsp3_fck = {

--	.name		= "mcbsp3_fck",

-+	.name		= "mcbsp_fck",

-+	.id		= 3,

- 	.init		= &omap2_init_clksel_parent,

- 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),

- 	.enable_bit	= OMAP3430_EN_MCBSP3_SHIFT,

-@@ -2816,7 +2825,8 @@ static struct clk mcbsp3_fck = {

- };

- 

- static struct clk mcbsp4_fck = {

--	.name		= "mcbsp4_fck",

-+	.name		= "mcbsp_fck",

-+	.id		= 4,

- 	.init		= &omap2_init_clksel_parent,

- 	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),

- 	.enable_bit	= OMAP3430_EN_MCBSP4_SHIFT,

--- 

-1.5.5.1.67.gbdb8.dirty

-

---

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-the body of a message to majordomo@vger.kernel.org

-More majordomo info at  http://vger.kernel.org/majordomo-info.html

-

diff --git a/packages/linux/linux-omap2-git/beagleboard/00004-omap2-mcbsp.patch b/packages/linux/linux-omap2-git/beagleboard/00004-omap2-mcbsp.patch
deleted file mode 100644
index f31604d658..0000000000
--- a/packages/linux/linux-omap2-git/beagleboard/00004-omap2-mcbsp.patch
+++ /dev/null
@@ -1,144 +0,0 @@
-From: Eduardo Valentin <eduardo.valentin@indt.org.br>

-

-This patch adds support for mach-omap2 based on current

-mcbsp platform driver.

-

-Signed-off-by: Eduardo Valentin <eduardo.valentin@indt.org.br>

----

- arch/arm/mach-omap2/Makefile |    2 +

- arch/arm/mach-omap2/mcbsp.c  |  105 ++++++++++++++++++++++++++++++++++++++++++

- 2 files changed, 107 insertions(+), 0 deletions(-)

- create mode 100644 arch/arm/mach-omap2/mcbsp.c

-

-diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile

-index 552664c..84fa698 100644

---- a/arch/arm/mach-omap2/Makefile

-+++ b/arch/arm/mach-omap2/Makefile

-@@ -7,6 +7,8 @@ obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \

- 		devices.o serial.o gpmc.o timer-gp.o powerdomain.o \

- 		clockdomain.o

- 

-+obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o

-+

- # Functions loaded to SRAM

- obj-$(CONFIG_ARCH_OMAP2)		+= sram24xx.o

- 

-diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c

-new file mode 100644

-index 0000000..e2ee8f7

---- /dev/null

-+++ b/arch/arm/mach-omap2/mcbsp.c

-@@ -0,0 +1,105 @@

-+/*

-+ * linux/arch/arm/mach-omap2/mcbsp.c

-+ *

-+ * Copyright (C) 2008 Instituto Nokia de Tecnologia

-+ * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>

-+ *

-+ * This program is free software; you can redistribute it and/or modify

-+ * it under the terms of the GNU General Public License version 2 as

-+ * published by the Free Software Foundation.

-+ *

-+ * Multichannel mode not supported.

-+ */

-+#include <linux/module.h>

-+#include <linux/init.h>

-+#include <linux/clk.h>

-+#include <linux/err.h>

-+

-+#include <asm/arch/dma.h>

-+#include <asm/arch/mux.h>

-+#include <asm/arch/cpu.h>

-+#include <asm/arch/mcbsp.h>

-+

-+static void omap2_mcbsp2_mux_setup(void)

-+{

-+	omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);

-+	omap_cfg_reg(R14_24XX_MCBSP2_FSX);

-+	omap_cfg_reg(W15_24XX_MCBSP2_DR);

-+	omap_cfg_reg(V15_24XX_MCBSP2_DX);

-+	omap_cfg_reg(V14_24XX_GPIO117);

-+	/*

-+	 * TODO: Need to add MUX settings for OMAP 2430 SDP

-+	 */

-+}

-+

-+static void omap2_mcbsp_request(unsigned int id)

-+{

-+	if (cpu_is_omap2420() && (id == OMAP_MCBSP2))

-+		omap2_mcbsp2_mux_setup();

-+}

-+

-+static int omap2_mcbsp_check(unsigned int id)

-+{

-+	if (id > OMAP_MAX_MCBSP_COUNT - 1) {

-+		printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);

-+		return -ENODEV;

-+	}

-+	return 0;

-+}

-+

-+static struct omap_mcbsp_ops omap2_mcbsp_ops = {

-+	.request	= omap2_mcbsp_request,

-+	.check		= omap2_mcbsp_check,

-+};

-+

-+static struct omap_mcbsp_platform_data omap2_mcbsp_pdata[] = {

-+#ifdef CONFIG_ARCH_OMAP24XX

-+	{

-+		.virt_base	= IO_ADDRESS(OMAP24XX_MCBSP1_BASE),

-+		.dma_rx_sync	= OMAP24XX_DMA_MCBSP1_RX,

-+		.dma_tx_sync	= OMAP24XX_DMA_MCBSP1_TX,

-+		.rx_irq		= INT_24XX_MCBSP1_IRQ_RX,

-+		.tx_irq		= INT_24XX_MCBSP1_IRQ_TX,

-+		.ops		= &omap2_mcbsp_ops,

-+		.clocks		= { "mcbsp_ick", "mcbsp_fck" },

-+	},

-+	{

-+		.virt_base	= IO_ADDRESS(OMAP24XX_MCBSP2_BASE),

-+		.dma_rx_sync	= OMAP24XX_DMA_MCBSP2_RX,

-+		.dma_tx_sync	= OMAP24XX_DMA_MCBSP2_TX,

-+		.rx_irq		= INT_24XX_MCBSP2_IRQ_RX,

-+		.tx_irq		= INT_24XX_MCBSP2_IRQ_TX,

-+		.ops		= &omap2_mcbsp_ops,

-+		.clocks		= { "mcbsp_ick", "mcbsp_fck" },

-+	},

-+#endif

-+#ifdef CONFIG_ARCH_OMAP34XX

-+	{

-+		.virt_base	= IO_ADDRESS(OMAP34XX_MCBSP1_BASE),

-+		.dma_rx_sync	= OMAP24XX_DMA_MCBSP1_RX,

-+		.dma_tx_sync	= OMAP24XX_DMA_MCBSP1_TX,

-+		.rx_irq		= INT_24XX_MCBSP1_IRQ_RX,

-+		.tx_irq		= INT_24XX_MCBSP1_IRQ_TX,

-+		.ops		= &omap2_mcbsp_ops,

-+		.clocks		= { "mcbsp_ick", "mcbsp_fck" },

-+	},

-+	{

-+		.virt_base	= IO_ADDRESS(OMAP34XX_MCBSP2_BASE),

-+		.dma_rx_sync	= OMAP24XX_DMA_MCBSP2_RX,

-+		.dma_tx_sync	= OMAP24XX_DMA_MCBSP2_TX,

-+		.rx_irq		= INT_24XX_MCBSP2_IRQ_RX,

-+		.tx_irq		= INT_24XX_MCBSP2_IRQ_TX,

-+		.ops		= &omap2_mcbsp_ops,

-+		.clocks		= { "mcbsp_ick", "mcbsp_fck" },

-+	},

-+#endif

-+};

-+#define mcbsp_count		ARRAY_SIZE(omap2_mcbsp_pdata)

-+

-+int __init omap2_mcbsp_init(void)

-+{

-+	omap_mcbsp_register_board_cfg(omap2_mcbsp_pdata, mcbsp_count);

-+

-+	return omap_mcbsp_init();

-+}

-+arch_initcall(omap2_mcbsp_init);

--- 

-1.5.5.1.67.gbdb8.dirty

-

---

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-the body of a message to majordomo@vger.kernel.org

-More majordomo info at  http://vger.kernel.org/majordomo-info.html

-

diff --git a/packages/linux/linux-omap2-git/beagleboard/0001-omap3-cpuidle.patch b/packages/linux/linux-omap2-git/beagleboard/0001-omap3-cpuidle.patch
new file mode 100644
index 0000000000..28b1ef2214
--- /dev/null
+++ b/packages/linux/linux-omap2-git/beagleboard/0001-omap3-cpuidle.patch
@@ -0,0 +1,450 @@
+From: "Rajendra Nayak" <rnayak@ti.com>

+To: <linux-omap@vger.kernel.org>

+Subject: [PATCH 01/02] OMAP3 CPUidle driver

+Date: 	Tue, 10 Jun 2008 12:39:00 +0530

+

+This patch adds the OMAP3 cpuidle driver. Irq enable/disable is done in the core cpuidle driver

+before it queries the governor for the next state.

+

+Signed-off-by: Rajendra Nayak <rnayak@ti.com>   

+

+---

+ arch/arm/mach-omap2/Makefile      |    2 

+ arch/arm/mach-omap2/cpuidle34xx.c |  293 ++++++++++++++++++++++++++++++++++++++

+ arch/arm/mach-omap2/cpuidle34xx.h |   51 ++++++

+ arch/arm/mach-omap2/pm34xx.c      |    5 

+ drivers/cpuidle/cpuidle.c         |   10 +

+ 5 files changed, 359 insertions(+), 2 deletions(-)

+

+Index: linux-omap-2.6/arch/arm/mach-omap2/Makefile

+===================================================================

+--- linux-omap-2.6.orig/arch/arm/mach-omap2/Makefile	2008-06-09 20:15:33.855303920 +0530

++++ linux-omap-2.6/arch/arm/mach-omap2/Makefile	2008-06-09 20:15:39.569121361 +0530

+@@ -20,7 +20,7 @@ obj-y					+= pm.o

+ obj-$(CONFIG_ARCH_OMAP2)		+= pm24xx.o

+ obj-$(CONFIG_ARCH_OMAP2420)		+= sleep242x.o

+ obj-$(CONFIG_ARCH_OMAP2430)		+= sleep243x.o

+-obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o

++obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o cpuidle34xx.o

+ obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o

+ endif

+ 

+Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c

+===================================================================

+--- /dev/null	1970-01-01 00:00:00.000000000 +0000

++++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c	2008-06-10 11:41:27.644820323 +0530

+@@ -0,0 +1,293 @@

++/*

++ * linux/arch/arm/mach-omap2/cpuidle34xx.c

++ *

++ * OMAP3 CPU IDLE Routines

++ *

++ * Copyright (C) 2007-2008 Texas Instruments, Inc.

++ * Rajendra Nayak <rnayak@ti.com>

++ *

++ * Copyright (C) 2007 Texas Instruments, Inc.

++ * Karthik Dasu <karthik-dp@ti.com>

++ *

++ * Copyright (C) 2006 Nokia Corporation

++ * Tony Lindgren <tony@atomide.com>

++ *

++ * Copyright (C) 2005 Texas Instruments, Inc.

++ * Richard Woodruff <r-woodruff2@ti.com>

++ *

++ * This program is free software; you can redistribute it and/or modify

++ * it under the terms of the GNU General Public License version 2 as

++ * published by the Free Software Foundation.

++ */

++

++#include <linux/cpuidle.h>

++#include <asm/arch/pm.h>

++#include <asm/arch/prcm.h>

++#include <asm/arch/powerdomain.h>

++#include <asm/arch/clockdomain.h>

++#include <asm/arch/irqs.h>

++#include "cpuidle34xx.h"

++

++#ifdef CONFIG_CPU_IDLE

++

++struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];

++struct omap3_processor_cx current_cx_state;

++

++static int omap3_idle_bm_check(void)

++{

++	/* Check for omap3_fclks_active() here once available */

++	return 0;

++}

++

++/* omap3_enter_idle - Programs OMAP3 to enter the specified state.

++ * returns the total time during which the system was idle.

++ */

++static int omap3_enter_idle(struct cpuidle_device *dev,

++			struct cpuidle_state *state)

++{

++	struct omap3_processor_cx *cx = cpuidle_get_statedata(state);

++	struct timespec ts_preidle, ts_postidle, ts_idle;

++	struct powerdomain *mpu_pd, *core_pd, *per_pd, *neon_pd;

++	int neon_pwrst;

++

++	current_cx_state = *cx;

++

++	if (cx->type == OMAP3_STATE_C0) {

++		/* Do nothing for C0, not even a wfi */

++		return 0;

++	}

++

++	/* Used to keep track of the total time in idle */

++	getnstimeofday(&ts_preidle);

++

++	mpu_pd = pwrdm_lookup("mpu_pwrdm");

++	core_pd = pwrdm_lookup("core_pwrdm");

++	per_pd = pwrdm_lookup("per_pwrdm");

++	neon_pd = pwrdm_lookup("neon_pwrdm");

++

++	/* Reset previous power state registers */

++	pwrdm_clear_all_prev_pwrst(mpu_pd);

++	pwrdm_clear_all_prev_pwrst(neon_pd);

++	pwrdm_clear_all_prev_pwrst(core_pd);

++	pwrdm_clear_all_prev_pwrst(per_pd);

++

++	if (omap_irq_pending())

++		return 0;

++

++	neon_pwrst = pwrdm_read_pwrst(neon_pd);

++

++	/* Program MPU/NEON to target state */

++	if (cx->mpu_state < PWRDM_POWER_ON) {

++		if (neon_pwrst == PWRDM_POWER_ON) {

++                        if (cx->mpu_state == PWRDM_POWER_RET)

++                                pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET);

++                        else if (cx->mpu_state == PWRDM_POWER_OFF)

++                                pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_OFF);

++		}

++		pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);

++	}

++

++	/* Program CORE to target state */

++	if (cx->core_state < PWRDM_POWER_ON)

++		pwrdm_set_next_pwrst(core_pd, cx->core_state);

++

++	/* Execute ARM wfi */

++	omap_sram_idle();

++

++	/* Program MPU/NEON to ON */

++	if (cx->mpu_state < PWRDM_POWER_ON) {

++		if (neon_pwrst == PWRDM_POWER_ON)

++			pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_ON);

++		pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON);

++	}

++

++	if (cx->core_state < PWRDM_POWER_ON)

++		pwrdm_set_next_pwrst(core_pd, PWRDM_POWER_ON);

++

++	getnstimeofday(&ts_postidle);

++	ts_idle = timespec_sub(ts_postidle, ts_preidle);

++	return timespec_to_ns(&ts_idle);

++}

++

++/*

++ * omap3_enter_idle_bm - enter function for states with CPUIDLE_FLAG_CHECK_BM

++ *

++ * This function checks for all the pre-requisites needed for OMAP3 to enter

++ * CORE RET/OFF state. It then calls omap3_enter_idle to program the desired

++ * C state.

++ */

++static int omap3_enter_idle_bm(struct cpuidle_device *dev,

++			       struct cpuidle_state *state)

++{

++	struct cpuidle_state *new_state = NULL;

++	int i, j;

++

++	if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {

++

++		/* Find current state in list */

++		for (i = 0; i < OMAP3_MAX_STATES; i++)

++			if (state == &dev->states[i])

++				break;

++		BUG_ON(i == OMAP3_MAX_STATES);

++

++		/* Back up to non 'CHECK_BM' state */

++		for (j = i - 1;  j > 0; j--) {

++			struct cpuidle_state *s = &dev->states[j];

++

++			if (!(s->flags & CPUIDLE_FLAG_CHECK_BM)) {

++				new_state = s;

++				break;

++			}

++		}

++

++		pr_debug("%s: Bus activity: Entering %s (instead of %s)\n",

++			__FUNCTION__, new_state->name, state->name);

++	}

++

++	return omap3_enter_idle(dev, new_state ? : state);

++}

++

++DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);

++

++/* omap3_init_power_states - Initialises the OMAP3 specific C states.

++ * Below is the desciption of each C state.

++ *

++	C0 . System executing code

++	C1 . MPU WFI + Core active

++	C2 . MPU CSWR + Core active

++	C3 . MPU OFF + Core active

++	C4 . MPU CSWR + Core CSWR

++	C5 . MPU OFF + Core CSWR

++	C6 . MPU OFF + Core OFF

++ */

++void omap_init_power_states(void)

++{

++	/* C0 . System executing code */

++	omap3_power_states[0].valid = 1;

++	omap3_power_states[0].type = OMAP3_STATE_C0;

++	omap3_power_states[0].sleep_latency = 0;

++	omap3_power_states[0].wakeup_latency = 0;

++	omap3_power_states[0].threshold = 0;

++	omap3_power_states[0].mpu_state = PWRDM_POWER_ON;

++	omap3_power_states[0].core_state = PWRDM_POWER_ON;

++	omap3_power_states[0].flags = CPUIDLE_FLAG_TIME_VALID |

++				CPUIDLE_FLAG_SHALLOW;

++

++	/* C1 . MPU WFI + Core active */

++	omap3_power_states[1].valid = 1;

++	omap3_power_states[1].type = OMAP3_STATE_C1;

++	omap3_power_states[1].sleep_latency = 10;

++	omap3_power_states[1].wakeup_latency = 10;

++	omap3_power_states[1].threshold = 30;

++	omap3_power_states[1].mpu_state = PWRDM_POWER_ON;

++	omap3_power_states[1].core_state = PWRDM_POWER_ON;

++	omap3_power_states[1].flags = CPUIDLE_FLAG_TIME_VALID |

++				CPUIDLE_FLAG_SHALLOW;

++

++	/* C2 . MPU CSWR + Core active */

++	omap3_power_states[2].valid = 1;

++	omap3_power_states[2].type = OMAP3_STATE_C2;

++	omap3_power_states[2].sleep_latency = 50;

++	omap3_power_states[2].wakeup_latency = 50;

++	omap3_power_states[2].threshold = 300;

++	omap3_power_states[2].mpu_state = PWRDM_POWER_RET;

++	omap3_power_states[2].core_state = PWRDM_POWER_ON;

++	omap3_power_states[2].flags = CPUIDLE_FLAG_TIME_VALID |

++				CPUIDLE_FLAG_BALANCED;

++

++	/* C3 . MPU OFF + Core active */

++	omap3_power_states[3].valid = 0;

++	omap3_power_states[3].type = OMAP3_STATE_C3;

++	omap3_power_states[3].sleep_latency = 1500;

++	omap3_power_states[3].wakeup_latency = 1800;

++	omap3_power_states[3].threshold = 4000;

++	omap3_power_states[3].mpu_state = PWRDM_POWER_OFF;

++	omap3_power_states[3].core_state = PWRDM_POWER_RET;

++	omap3_power_states[3].flags = CPUIDLE_FLAG_TIME_VALID |

++				CPUIDLE_FLAG_BALANCED;

++

++	/* C4 . MPU CSWR + Core CSWR*/

++	omap3_power_states[4].valid = 1;

++	omap3_power_states[4].type = OMAP3_STATE_C4;

++	omap3_power_states[4].sleep_latency = 2500;

++	omap3_power_states[4].wakeup_latency = 7500;

++	omap3_power_states[4].threshold = 12000;

++	omap3_power_states[4].mpu_state = PWRDM_POWER_RET;

++	omap3_power_states[4].core_state = PWRDM_POWER_RET;

++	omap3_power_states[4].flags = CPUIDLE_FLAG_TIME_VALID |

++			CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;

++

++	/* C5 . MPU OFF + Core CSWR */

++	omap3_power_states[5].valid = 0;

++	omap3_power_states[5].type = OMAP3_STATE_C5;

++	omap3_power_states[5].sleep_latency = 3000;

++	omap3_power_states[5].wakeup_latency = 8500;

++	omap3_power_states[5].threshold = 15000;

++	omap3_power_states[5].mpu_state = PWRDM_POWER_OFF;

++	omap3_power_states[5].core_state = PWRDM_POWER_RET;

++	omap3_power_states[5].flags = CPUIDLE_FLAG_TIME_VALID |

++			CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;

++

++	/* C6 . MPU OFF + Core OFF */

++	omap3_power_states[6].valid = 0;

++	omap3_power_states[6].type = OMAP3_STATE_C6;

++	omap3_power_states[6].sleep_latency = 10000;

++	omap3_power_states[6].wakeup_latency = 30000;

++	omap3_power_states[6].threshold = 300000;

++	omap3_power_states[6].mpu_state = PWRDM_POWER_OFF;

++	omap3_power_states[6].core_state = PWRDM_POWER_OFF;

++	omap3_power_states[6].flags = CPUIDLE_FLAG_TIME_VALID |

++			CPUIDLE_FLAG_DEEP | CPUIDLE_FLAG_CHECK_BM;

++}

++

++struct cpuidle_driver omap3_idle_driver = {

++	.name = 	"omap3_idle",

++	.owner = 	THIS_MODULE,

++};

++/*

++ * omap3_idle_init - Init routine for OMAP3 idle.

++ * Registers the OMAP3 specific cpuidle driver with the cpuidle f/w

++ * with the valid set of states.

++ */

++int omap3_idle_init(void)

++{

++	int i, count = 0;

++	struct omap3_processor_cx *cx;

++	struct cpuidle_state *state;

++	struct cpuidle_device *dev;

++

++	omap_init_power_states();

++	cpuidle_register_driver(&omap3_idle_driver);

++

++	dev = &per_cpu(omap3_idle_dev, smp_processor_id());

++

++	for (i = 0; i < OMAP3_MAX_STATES; i++) {

++		cx = &omap3_power_states[i];

++		state = &dev->states[count];

++

++		if (!cx->valid)

++			continue;

++		cpuidle_set_statedata(state, cx);

++		state->exit_latency = cx->sleep_latency + cx->wakeup_latency;

++		state->target_residency = cx->threshold;

++		state->flags = cx->flags;

++		state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?

++			omap3_enter_idle_bm : omap3_enter_idle;

++		sprintf(state->name, "C%d", count+1);

++		count++;

++	}

++

++	if (!count)

++		return -EINVAL;

++	dev->state_count = count;

++

++	if (cpuidle_register_device(dev)) {

++		printk(KERN_ERR "%s: CPUidle register device failed\n",

++		       __FUNCTION__);

++		return -EIO;

++	}

++

++	return 0;

++}

++__initcall(omap3_idle_init);

++#endif /* CONFIG_CPU_IDLE */

+Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h

+===================================================================

+--- /dev/null	1970-01-01 00:00:00.000000000 +0000

++++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h	2008-06-09 20:15:39.569121361 +0530

+@@ -0,0 +1,51 @@

++/*

++ * linux/arch/arm/mach-omap2/cpuidle34xx.h

++ *

++ * OMAP3 cpuidle structure definitions

++ *

++ * Copyright (C) 2007-2008 Texas Instruments, Inc.

++ * Written by Rajendra Nayak <rnayak@ti.com>

++ *

++ * This program is free software; you can redistribute it and/or modify

++ * it under the terms of the GNU General Public License version 2 as

++ * published by the Free Software Foundation.

++ *

++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR

++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED

++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.

++ *

++ * History:

++ *

++ */

++

++#ifndef ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX

++#define ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX

++

++#define OMAP3_MAX_STATES 7

++#define OMAP3_STATE_C0 0 /* C0 - System executing code */

++#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */

++#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */

++#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */

++#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */

++#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */

++#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */

++

++extern void omap_sram_idle(void);

++extern int omap3_irq_pending(void);

++

++struct omap3_processor_cx {

++	u8 valid;

++	u8 type;

++	u32 sleep_latency;

++	u32 wakeup_latency;

++	u32 mpu_state;

++	u32 core_state;

++	u32 threshold;

++	u32 flags;

++};

++

++void omap_init_power_states(void);

++int omap3_idle_init(void);

++

++#endif /* ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX */

++

+Index: linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c

+===================================================================

+--- linux-omap-2.6.orig/arch/arm/mach-omap2/pm34xx.c	2008-06-09 20:15:33.855303920 +0530

++++ linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c	2008-06-09 20:16:20.976798343 +0530

+@@ -141,7 +141,7 @@ static irqreturn_t prcm_interrupt_handle

+ 	return IRQ_HANDLED;

+ }

+ 

+-static void omap_sram_idle(void)

++void omap_sram_idle(void)

+ {

+ 	/* Variable to tell what needs to be saved and restored

+ 	 * in omap_sram_idle*/

+@@ -156,6 +156,7 @@ static void omap_sram_idle(void)

+ 

+ 	mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);

+ 	switch (mpu_next_state) {

++	case PWRDM_POWER_ON:

+ 	case PWRDM_POWER_RET:

+ 		/* No need to save context */

+ 		save_state = 0;

+@@ -386,7 +387,9 @@ int __init omap3_pm_init(void)

+ 

+ 	prcm_setup_regs();

+ 

++#ifndef CONFIG_CPU_IDLE

+ 	pm_idle = omap3_pm_idle;

++#endif

+ 

+ err1:

+ 	return ret;

+Index: linux-omap-2.6/drivers/cpuidle/cpuidle.c

+===================================================================

+--- linux-omap-2.6.orig/drivers/cpuidle/cpuidle.c	2008-06-09 20:15:33.856303888 +0530

++++ linux-omap-2.6/drivers/cpuidle/cpuidle.c	2008-06-09 20:15:39.570121329 +0530

+@@ -58,6 +58,11 @@ static void cpuidle_idle_call(void)

+ 		return;

+ 	}

+ 

++#ifdef CONFIG_ARCH_OMAP3

++	local_irq_disable();

++	local_fiq_disable();

++#endif

++

+ 	/* ask the governor for the next state */

+ 	next_state = cpuidle_curr_governor->select(dev);

+ 	if (need_resched())

+@@ -70,6 +75,11 @@ static void cpuidle_idle_call(void)

+ 	target_state->time += (unsigned long long)dev->last_residency;

+ 	target_state->usage++;

+ 

++#ifdef CONFIG_ARCH_OMAP3

++	local_irq_enable();

++	local_fiq_enable();

++#endif

++

+ 	/* give the governor an opportunity to reflect on the outcome */

+ 	if (cpuidle_curr_governor->reflect)

+ 		cpuidle_curr_governor->reflect(dev);

+

+--

+To unsubscribe from this list: send the line "unsubscribe linux-omap" in

+the body of a message to majordomo@vger.kernel.org

+More majordomo info at  http://vger.kernel.org/majordomo-info.html

+

diff --git a/packages/linux/linux-omap2-git/beagleboard/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch b/packages/linux/linux-omap2-git/beagleboard/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch
new file mode 100644
index 0000000000..17329be29b
--- /dev/null
+++ b/packages/linux/linux-omap2-git/beagleboard/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch
@@ -0,0 +1,69 @@
+From 7a444ee080c5f1a62ac5042f1e7926622b3e1ce7 Mon Sep 17 00:00:00 2001
+From: Koen Kooi <koen@openembedded.org>
+Date: Fri, 30 May 2008 13:43:36 +0200
+Subject: [PATCH] ARM: OMAP: omap3beagle: add a platform device to hook up the GPIO leds to the leds-gpio driver
+
+omap3beagle: add a platform device to hook up the GPIO leds to the leds-gpio driver
+ * on revision A5 and earlier board the two leds can't be controlled seperately, should be fixed in rev. B and C boards.
+
+Signed-off-by: Koen Kooi <koen@openembedded.org>
+---
+ arch/arm/mach-omap2/board-omap3beagle.c |   28 ++++++++++++++++++++++++++++
+ 1 files changed, 28 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index c992cc7..83891fc 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -19,6 +19,7 @@
+ #include <linux/err.h>
+ #include <linux/clk.h>
+ #include <linux/io.h>
++#include <linux/leds.h>
+ 
+ #include <asm/hardware.h>
+ #include <asm/mach-types.h>
+@@ -72,6 +73,32 @@ static struct omap_lcd_config omap3_beagle_lcd_config __initdata = {
+ 	.ctrl_name	= "internal",
+ };
+ 
++struct gpio_led gpio_leds[] = {
++	{
++		.name = "beagleboard::led0",
++		.default_trigger = "none",
++		.gpio = 149,
++	},
++	{
++		.name = "beagleboard::led1",
++		.default_trigger = "none",
++		.gpio = 150,
++	},
++};
++
++static struct gpio_led_platform_data gpio_led_info = {
++	.leds = gpio_leds,
++	.num_leds = ARRAY_SIZE(gpio_leds),
++};
++
++static struct platform_device leds_gpio = {
++	.name = "leds-gpio",
++	.id   = -1,
++	.dev  = {
++		.platform_data = &gpio_led_info,
++	},
++};
++
+ static struct omap_board_config_kernel omap3_beagle_config[] __initdata = {
+ 	{ OMAP_TAG_UART,	&omap3_beagle_uart_config },
+ 	{ OMAP_TAG_MMC,		&omap3beagle_mmc_config },
+@@ -83,6 +110,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = {
+ #ifdef CONFIG_RTC_DRV_TWL4030
+ 	&omap3_beagle_twl4030rtc_device,
+ #endif
++	&leds_gpio,
+ };
+ 
+ static void __init omap3_beagle_init(void)
+-- 
+1.5.4.3
+
diff --git a/packages/linux/linux-omap2-git/beagleboard/0002-omap3-cpuidle.patch b/packages/linux/linux-omap2-git/beagleboard/0002-omap3-cpuidle.patch
new file mode 100644
index 0000000000..c17c690fe1
--- /dev/null
+++ b/packages/linux/linux-omap2-git/beagleboard/0002-omap3-cpuidle.patch
@@ -0,0 +1,88 @@
+From: "Rajendra Nayak" <rnayak@ti.com>

+To: <linux-omap@vger.kernel.org>

+Subject: [PATCH 02/02] Kconfig changes

+Date: 	Tue, 10 Jun 2008 12:39:02 +0530

+

+Updates the CPUidle Kconfig

+

+Signed-off-by: Rajendra Nayak <rnayak@ti.com>   

+

+---

+ arch/arm/Kconfig        |   10 ++++++++++

+ drivers/cpuidle/Kconfig |   28 ++++++++++++++++++++++------

+ 2 files changed, 32 insertions(+), 6 deletions(-)

+

+Index: linux-omap-2.6/arch/arm/Kconfig

+===================================================================

+--- linux-omap-2.6.orig/arch/arm/Kconfig	2008-06-10 11:43:10.790502713 +0530

++++ linux-omap-2.6/arch/arm/Kconfig	2008-06-10 11:43:38.701604549 +0530

+@@ -954,6 +954,16 @@ config ATAGS_PROC

+ 

+ endmenu

+ 

++if (ARCH_OMAP)

++

++menu "CPUIdle"

++

++source "drivers/cpuidle/Kconfig"

++

++endmenu

++

++endif

++

+ if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)

+ 

+ menu "CPU Frequency scaling"

+Index: linux-omap-2.6/drivers/cpuidle/Kconfig

+===================================================================

+--- linux-omap-2.6.orig/drivers/cpuidle/Kconfig	2008-06-10 11:43:10.790502713 +0530

++++ linux-omap-2.6/drivers/cpuidle/Kconfig	2008-06-10 12:06:36.139332151 +0530

+@@ -1,20 +1,36 @@

++menu "CPU idle PM support"

+ 

+ config CPU_IDLE

+ 	bool "CPU idle PM support"

+-	default ACPI

++	default n

+ 	help

+ 	  CPU idle is a generic framework for supporting software-controlled

+ 	  idle processor power management.  It includes modular cross-platform

+ 	  governors that can be swapped during runtime.

+ 

+-	  If you're using an ACPI-enabled platform, you should say Y here.

++	  If you're using a mobile platform that supports CPU idle PM (e.g.

++	  an ACPI-capable notebook), you should say Y here.

++

++if CPU_IDLE

++

++comment "Governors"

+ 

+ config CPU_IDLE_GOV_LADDER

+-	bool

++	bool "ladder"

+ 	depends on CPU_IDLE

+-	default y

++	default n

+ 

+ config CPU_IDLE_GOV_MENU

+-	bool

++	bool "menu"

+ 	depends on CPU_IDLE && NO_HZ

+-	default y

++	default n

++        help

++	  This cpuidle governor evaluates all available states and chooses the

++	  deepest state that meets all of the following constraints: BM activity,

++	  expected time until next timer interrupt, and last break event time

++	  delta.  It is designed to minimize power consumption.  Currently

++	  dynticks is required.

++

++endif   # CPU_IDLE

++

++endmenu

+

+--

+To unsubscribe from this list: send the line "unsubscribe linux-omap" in

+the body of a message to majordomo@vger.kernel.org

+More majordomo info at  http://vger.kernel.org/majordomo-info.html

+

diff --git a/packages/linux/linux-omap2-git/beagleboard/16bpp.patch b/packages/linux/linux-omap2-git/beagleboard/16bpp.patch
new file mode 100644
index 0000000000..f1e2181c82
--- /dev/null
+++ b/packages/linux/linux-omap2-git/beagleboard/16bpp.patch
@@ -0,0 +1,13 @@
+diff --git a/drivers/video/omap/lcd_omap3beagle.c b/drivers/video/omap/lcd_omap3beagle.c
+index 69d4e06..c1c4f4c 100644
+--- a/drivers/video/omap/lcd_omap3beagle.c
++++ b/drivers/video/omap/lcd_omap3beagle.c
+@@ -66,7 +66,7 @@ struct lcd_panel omap3beagle_panel = {
+ 	.name		= "omap3beagle",
+ 	.config		= OMAP_LCDC_PANEL_TFT,
+ 
+-	.bpp		= 24,
++	.bpp		= 16,
+ 	.data_lines	= 24,
+ 	.x_res		= LCD_XRES,
+ 	.y_res		= LCD_YRES,
diff --git a/packages/linux/linux-omap2-git/beagleboard/defconfig b/packages/linux/linux-omap2-git/beagleboard/defconfig
index 3d3562d9f5..d4c1e9300a 100644
--- a/packages/linux/linux-omap2-git/beagleboard/defconfig
+++ b/packages/linux/linux-omap2-git/beagleboard/defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.26-rc3-omap1
-# Tue May 20 19:38:20 2008
+# Linux kernel version: 2.6.26-rc7-omap1
+# Tue Jun 24 20:16:52 2008
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -31,6 +31,7 @@ CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
@@ -79,8 +80,9 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
 # CONFIG_MARKERS is not set
@@ -171,17 +173,16 @@ CONFIG_ARCH_OMAP3=y
 #
 # OMAP Feature Selections
 #
-CONFIG_OMAP_DEBUG_SRAM_PATCH=y
 # CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
 # CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
-# CONFIG_OMAP_RESET_CLOCKS is not set
+CONFIG_OMAP_SMARTREFLEX=y
+# CONFIG_OMAP_SMARTREFLEX_TESTING is not set
+CONFIG_OMAP_RESET_CLOCKS=y
 CONFIG_OMAP_BOOT_TAG=y
 CONFIG_OMAP_BOOT_REASON=y
 # CONFIG_OMAP_COMPONENT_VERSION is not set
 # CONFIG_OMAP_GPIO_SWITCH is not set
-CONFIG_OMAP_MUX=n
-# CONFIG_OMAP_MUX_DEBUG is not set
-CONFIG_OMAP_MUX_WARNINGS=n
+# CONFIG_OMAP_MUX is not set
 CONFIG_OMAP_MCBSP=y
 # CONFIG_OMAP_MMU_FWK is not set
 # CONFIG_OMAP_MBOX_FWK is not set
@@ -192,7 +193,6 @@ CONFIG_OMAP_DM_TIMER=y
 # CONFIG_OMAP_LL_DEBUG_UART1 is not set
 # CONFIG_OMAP_LL_DEBUG_UART2 is not set
 CONFIG_OMAP_LL_DEBUG_UART3=y
-CONFIG_OMAP_SERIAL_WAKE=y
 CONFIG_ARCH_OMAP34XX=y
 CONFIG_ARCH_OMAP3430=y
 
@@ -233,7 +233,7 @@ CONFIG_CPU_CP15_MMU=y
 # Processor Features
 #
 CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
+CONFIG_ARM_THUMBEE=y
 # CONFIG_CPU_ICACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_BPREDICT_DISABLE is not set
@@ -254,7 +254,7 @@ CONFIG_TICK_ONESHOT=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-# CONFIG_PREEMPT is not set
+CONFIG_PREEMPT=y
 CONFIG_HZ=128
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
@@ -273,7 +273,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
-# CONFIG_LEDS is not set
+CONFIG_LEDS=y
 CONFIG_ALIGNMENT_TRAP=y
 
 #
@@ -287,6 +287,21 @@ CONFIG_KEXEC=y
 CONFIG_ATAGS_PROC=y
 
 #
+# CPUIdle
+#
+
+#
+# CPU idle PM support
+#
+CONFIG_CPU_IDLE=y
+
+#
+# Governors
+#
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+
+#
 # CPU Frequency scaling
 #
 CONFIG_CPU_FREQ=y
@@ -473,7 +488,7 @@ CONFIG_MAC80211_RC_DEFAULT_PID=y
 CONFIG_MAC80211_RC_DEFAULT="pid"
 CONFIG_MAC80211_RC_PID=y
 # CONFIG_MAC80211_MESH is not set
-# CONFIG_MAC80211_LEDS is not set
+CONFIG_MAC80211_LEDS=y
 # CONFIG_MAC80211_DEBUG_PACKET_ALIGNMENT is not set
 # CONFIG_MAC80211_DEBUG is not set
 CONFIG_IEEE80211=y
@@ -514,7 +529,7 @@ CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
-CONFIG_FTL=y
+# CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
@@ -566,6 +581,7 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_OMAP2=y
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
@@ -853,22 +869,23 @@ CONFIG_I2C_OMAP=y
 # Miscellaneous I2C Chip support
 #
 # CONFIG_DS1682 is not set
-# CONFIG_SENSORS_EEPROM is not set
+CONFIG_SENSORS_EEPROM=y
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_ISP1301_OMAP is not set
 # CONFIG_TPS65010 is not set
-CONFIG_SENSORS_TLV320AIC23=y
+# CONFIG_SENSORS_TLV320AIC23 is not set
 CONFIG_TWL4030_CORE=y
 CONFIG_TWL4030_GPIO=y
-# CONFIG_TWL4030_MADC is not set
+CONFIG_TWL4030_MADC=m
 CONFIG_TWL4030_USB=y
 CONFIG_TWL4030_USB_HS_ULPI=y
 CONFIG_TWL4030_PWRBUTTON=y
-# CONFIG_TWL4030_POWEROFF is not set
+CONFIG_TWL4030_POWEROFF=y
 # CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_TSL2563 is not set
 # CONFIG_LP5521 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
@@ -912,8 +929,65 @@ CONFIG_HAVE_GPIO_LIB=y
 #
 # CONFIG_GPIO_MCP23S08 is not set
 # CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-# CONFIG_HWMON is not set
+CONFIG_POWER_SUPPLY=m
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_APM_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_TSC210X is not set
+CONFIG_SENSORS_OMAP34XX=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_NOWAYOUT=y
 
@@ -949,102 +1023,178 @@ CONFIG_SSB_POSSIBLE=y
 #
 # Multimedia core support
 #
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2_COMMON=y
-# CONFIG_VIDEO_ALLOW_V4L1 is not set
-# CONFIG_VIDEO_V4L1_COMPAT is not set
-# CONFIG_DVB_CORE is not set
-CONFIG_VIDEO_MEDIA=y
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+CONFIG_DVB_CORE=m
+CONFIG_VIDEO_MEDIA=m
 
 #
 # Multimedia drivers
 #
 CONFIG_MEDIA_ATTACH=y
-CONFIG_MEDIA_TUNER=y
+CONFIG_MEDIA_TUNER=m
 # CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
-CONFIG_MEDIA_TUNER_SIMPLE=y
-CONFIG_MEDIA_TUNER_TDA8290=y
-CONFIG_MEDIA_TUNER_TDA9887=y
-CONFIG_MEDIA_TUNER_TEA5761=y
-CONFIG_MEDIA_TUNER_TEA5767=y
-CONFIG_MEDIA_TUNER_MT20XX=y
-CONFIG_MEDIA_TUNER_XC2028=y
-CONFIG_MEDIA_TUNER_XC5000=y
-CONFIG_VIDEO_V4L2=y
-CONFIG_VIDEO_TVEEPROM=m
-CONFIG_VIDEO_TUNER=m
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_V4L1=m
 CONFIG_VIDEO_CAPTURE_DRIVERS=y
 # CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_TUNER_3036 is not set
+# CONFIG_VIDEO_AU0828 is not set
+CONFIG_V4L_USB_DRIVERS=y
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_VICAM is not set
+# CONFIG_USB_IBMCAM is not set
+# CONFIG_USB_KONICAWC is not set
+# CONFIG_USB_QUICKCAM_MESSENGER is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_VIDEO_OVCAMCHIP is not set
+# CONFIG_USB_W9968CF is not set
+# CONFIG_USB_OV511 is not set
+# CONFIG_USB_SE401 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_STV680 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_RADIO_TEA5761 is not set
+# CONFIG_USB_DSBR is not set
+# CONFIG_USB_SI470X is not set
+CONFIG_DVB_CAPTURE_DRIVERS=y
+# CONFIG_TTPCI_EEPROM is not set
 
 #
-# Encoders/decoders and other helper chips
+# Supported USB Adapters
 #
+CONFIG_DVB_USB=m
+# CONFIG_DVB_USB_DEBUG is not set
+CONFIG_DVB_USB_A800=m
+CONFIG_DVB_USB_DIBUSB_MB=m
+# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
+CONFIG_DVB_USB_DIBUSB_MC=m
+CONFIG_DVB_USB_DIB0700=m
+CONFIG_DVB_USB_UMT_010=m
+CONFIG_DVB_USB_CXUSB=m
+CONFIG_DVB_USB_M920X=m
+CONFIG_DVB_USB_GL861=m
+CONFIG_DVB_USB_AU6610=m
+CONFIG_DVB_USB_DIGITV=m
+CONFIG_DVB_USB_VP7045=m
+CONFIG_DVB_USB_VP702X=m
+CONFIG_DVB_USB_GP8PSK=m
+CONFIG_DVB_USB_NOVA_T_USB2=m
+CONFIG_DVB_USB_TTUSB2=m
+CONFIG_DVB_USB_DTT200U=m
+CONFIG_DVB_USB_OPERA1=m
+CONFIG_DVB_USB_AF9005=m
+CONFIG_DVB_USB_AF9005_REMOTE=m
+CONFIG_DVB_TTUSB_BUDGET=m
+CONFIG_DVB_TTUSB_DEC=m
+CONFIG_DVB_CINERGYT2=m
+# CONFIG_DVB_CINERGYT2_TUNING is not set
 
 #
-# Audio decoders
+# Supported FlexCopII (B2C2) Adapters
 #
-# CONFIG_VIDEO_TVAUDIO is not set
-# CONFIG_VIDEO_TDA7432 is not set
-# CONFIG_VIDEO_TDA9840 is not set
-# CONFIG_VIDEO_TDA9875 is not set
-# CONFIG_VIDEO_TEA6415C is not set
-# CONFIG_VIDEO_TEA6420 is not set
-CONFIG_VIDEO_MSP3400=m
-# CONFIG_VIDEO_CS5345 is not set
-CONFIG_VIDEO_CS53L32A=m
-# CONFIG_VIDEO_M52790 is not set
-# CONFIG_VIDEO_TLV320AIC23B is not set
-CONFIG_VIDEO_WM8775=m
-# CONFIG_VIDEO_WM8739 is not set
-# CONFIG_VIDEO_VP27SMPX is not set
+# CONFIG_DVB_B2C2_FLEXCOP is not set
 
 #
-# Video decoders
+# Supported DVB Frontends
 #
-# CONFIG_VIDEO_OV7670 is not set
-# CONFIG_VIDEO_TCM825X is not set
-# CONFIG_VIDEO_OV9640 is not set
-CONFIG_VIDEO_SAA711X=m
-# CONFIG_VIDEO_SAA717X is not set
-# CONFIG_VIDEO_TVP5150 is not set
 
 #
-# Video and audio decoders
+# Customise DVB Frontends
 #
-CONFIG_VIDEO_CX25840=m
+# CONFIG_DVB_FE_CUSTOMISE is not set
 
 #
-# MPEG video encoders
+# DVB-S (satellite) frontends
 #
-CONFIG_VIDEO_CX2341X=m
+CONFIG_DVB_CX24110=m
+CONFIG_DVB_CX24123=m
+CONFIG_DVB_MT312=m
+CONFIG_DVB_S5H1420=m
+CONFIG_DVB_STV0299=m
+CONFIG_DVB_TDA8083=m
+CONFIG_DVB_TDA10086=m
+CONFIG_DVB_VES1X93=m
+CONFIG_DVB_TUNER_ITD1000=m
+CONFIG_DVB_TDA826X=m
+CONFIG_DVB_TUA6100=m
 
 #
-# Video encoders
+# DVB-T (terrestrial) frontends
 #
-# CONFIG_VIDEO_SAA7127 is not set
+CONFIG_DVB_SP8870=m
+CONFIG_DVB_SP887X=m
+CONFIG_DVB_CX22700=m
+CONFIG_DVB_CX22702=m
+CONFIG_DVB_L64781=m
+CONFIG_DVB_TDA1004X=m
+CONFIG_DVB_NXT6000=m
+CONFIG_DVB_MT352=m
+CONFIG_DVB_ZL10353=m
+CONFIG_DVB_DIB3000MB=m
+CONFIG_DVB_DIB3000MC=m
+CONFIG_DVB_DIB7000M=m
+CONFIG_DVB_DIB7000P=m
+CONFIG_DVB_TDA10048=m
 
 #
-# Video improvement chips
+# DVB-C (cable) frontends
 #
-# CONFIG_VIDEO_UPD64031A is not set
-# CONFIG_VIDEO_UPD64083 is not set
-# CONFIG_VIDEO_VIVI is not set
-# CONFIG_VIDEO_SAA5246A is not set
-# CONFIG_VIDEO_SAA5249 is not set
-CONFIG_V4L_USB_DRIVERS=y
-CONFIG_VIDEO_PVRUSB2=m
-CONFIG_VIDEO_PVRUSB2_SYSFS=y
-# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
-# CONFIG_VIDEO_EM28XX is not set
-# CONFIG_VIDEO_USBVISION is not set
-# CONFIG_USB_ET61X251 is not set
-CONFIG_USB_SN9C102=m
-# CONFIG_USB_ZC0301 is not set
-# CONFIG_USB_ZR364XX is not set
-# CONFIG_USB_STKWEBCAM is not set
-# CONFIG_SOC_CAMERA is not set
-# CONFIG_RADIO_ADAPTERS is not set
+CONFIG_DVB_VES1820=m
+CONFIG_DVB_TDA10021=m
+CONFIG_DVB_TDA10023=m
+CONFIG_DVB_STV0297=m
+
+#
+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
+#
+CONFIG_DVB_NXT200X=m
+# CONFIG_DVB_OR51211 is not set
+# CONFIG_DVB_OR51132 is not set
+CONFIG_DVB_BCM3510=m
+CONFIG_DVB_LGDT330X=m
+CONFIG_DVB_S5H1409=m
+CONFIG_DVB_AU8522=m
+CONFIG_DVB_S5H1411=m
+
+#
+# Digital terrestrial only tuners/PLL
+#
+CONFIG_DVB_PLL=m
+CONFIG_DVB_TUNER_DIB0070=m
+
+#
+# SEC control devices for DVB-S
+#
+CONFIG_DVB_LNBP21=m
+# CONFIG_DVB_ISL6405 is not set
+CONFIG_DVB_ISL6421=m
 # CONFIG_DAB is not set
 
 #
@@ -1053,7 +1203,7 @@ CONFIG_USB_SN9C102=m
 # CONFIG_VGASTATE is not set
 # CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
+# CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FB_DDC is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
@@ -1101,7 +1251,10 @@ CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
 # CONFIG_FONTS is not set
 CONFIG_FONT_8x8=y
 CONFIG_FONT_8x16=y
-# CONFIG_LOGO is not set
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
 
 #
 # Sound
@@ -1114,15 +1267,15 @@ CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_TIMER=y
 CONFIG_SND_PCM=y
-CONFIG_SND_HWDEP=m
-CONFIG_SND_RAWMIDI=m
+CONFIG_SND_HWDEP=y
+CONFIG_SND_RAWMIDI=y
 CONFIG_SND_SEQUENCER=m
 # CONFIG_SND_SEQ_DUMMY is not set
 CONFIG_SND_OSSEMUL=y
 CONFIG_SND_MIXER_OSS=y
 CONFIG_SND_PCM_OSS=y
 CONFIG_SND_PCM_OSS_PLUGINS=y
-# CONFIG_SND_SEQUENCER_OSS is not set
+CONFIG_SND_SEQUENCER_OSS=y
 # CONFIG_SND_DYNAMIC_MINORS is not set
 CONFIG_SND_SUPPORT_OLD_API=y
 CONFIG_SND_VERBOSE_PROCFS=y
@@ -1154,9 +1307,9 @@ CONFIG_SND_VERBOSE_PROCFS=y
 #
 # USB devices
 #
-CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_USB_AUDIO=y
 CONFIG_SND_USB_CAIAQ=m
-# CONFIG_SND_USB_CAIAQ_INPUT is not set
+CONFIG_SND_USB_CAIAQ_INPUT=y
 
 #
 # System on Chip audio support
@@ -1171,6 +1324,9 @@ CONFIG_SND_SOC=y
 # SoC Audio for the Texas Instruments OMAP
 #
 CONFIG_SND_OMAP_SOC=y
+CONFIG_SND_OMAP_SOC_MCBSP=y
+CONFIG_SND_OMAP_SOC_OMAP3BEAGLE=y
+CONFIG_SND_SOC_TWL4030=y
 
 #
 # Open Sound System
@@ -1203,7 +1359,7 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
 CONFIG_USB_SUSPEND=y
-# CONFIG_USB_OTG is not set
+CONFIG_USB_OTG=y
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
@@ -1228,9 +1384,10 @@ CONFIG_USB_MUSB_SOC=y
 # OMAP 343x high speed USB support
 #
 # CONFIG_USB_MUSB_HOST is not set
-CONFIG_USB_MUSB_PERIPHERAL=y
-# CONFIG_USB_MUSB_OTG is not set
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+CONFIG_USB_MUSB_OTG=y
 CONFIG_USB_GADGET_MUSB_HDRC=y
+CONFIG_USB_MUSB_HDRC_HCD=y
 # CONFIG_MUSB_PIO_ONLY is not set
 CONFIG_USB_INVENTRA_DMA=y
 # CONFIG_USB_TI_CPPI_DMA is not set
@@ -1241,6 +1398,7 @@ CONFIG_USB_MUSB_LOGLEVEL=0
 #
 CONFIG_USB_ACM=m
 CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
 
 #
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1344,6 +1502,7 @@ CONFIG_USB_SISUSBVGA_CON=y
 # CONFIG_USB_TRANCEVIBRATOR is not set
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
 CONFIG_USB_GADGET=y
 # CONFIG_USB_GADGET_DEBUG is not set
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
@@ -1380,6 +1539,7 @@ CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_BLOCK=y
 CONFIG_MMC_BLOCK_BOUNCE=y
 CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
 
 #
 # MMC/SD Host Controller Drivers
@@ -1395,14 +1555,14 @@ CONFIG_LEDS_CLASS=y
 # CONFIG_LEDS_OMAP_DEBUG is not set
 # CONFIG_LEDS_OMAP is not set
 # CONFIG_LEDS_OMAP_PWM is not set
-CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_GPIO=y
 
 #
 # LED Triggers
 #
 CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=m
-CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
@@ -1434,6 +1594,7 @@ CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_DRV_M41T80 is not set
 CONFIG_RTC_DRV_TWL4030=y
 # CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
 
 #
 # SPI RTC drivers
@@ -1476,8 +1637,12 @@ CONFIG_EXT3_FS=y
 CONFIG_JBD=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_XFS_FS=m
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 CONFIG_DNOTIFY=y
@@ -1491,13 +1656,16 @@ CONFIG_QFMT_V2=y
 CONFIG_QUOTACTL=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
+CONFIG_FUSE_FS=m
 
 #
 # CD-ROM/DVD Filesystems
 #
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
 
 #
 # DOS/FAT/NT Filesystems
@@ -1530,7 +1698,23 @@ CONFIG_TMPFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS2_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
@@ -1641,7 +1825,9 @@ CONFIG_SCHED_DEBUG=y
 CONFIG_SCHEDSTATS=y
 CONFIG_TIMER_STATS=y
 # CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_DEBUG_SLAB is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_DEBUG_PREEMPT=y
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
@@ -1652,7 +1838,7 @@ CONFIG_DEBUG_MUTEXES=y
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
 # CONFIG_DEBUG_INFO is not set
 # CONFIG_DEBUG_VM is not set
 # CONFIG_DEBUG_WRITECOUNT is not set
@@ -1665,10 +1851,9 @@ CONFIG_FRAME_POINTER=y
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_SAMPLES is not set
 # CONFIG_DEBUG_USER is not set
-CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_ERRORS is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
-CONFIG_DEBUG_LL=y
-# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_LL is not set
 
 #
 # Security options
@@ -1772,8 +1957,10 @@ CONFIG_CRC_ITU_T=y
 CONFIG_CRC32=y
 CONFIG_CRC7=y
 CONFIG_LIBCRC32C=y
-CONFIG_ZLIB_INFLATE=m
-CONFIG_ZLIB_DEFLATE=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
diff --git a/packages/linux/linux-omap2-git/beagleboard/fix-dispc-clocks.patch b/packages/linux/linux-omap2-git/beagleboard/fix-dispc-clocks.patch
new file mode 100644
index 0000000000..aade27fd8a
--- /dev/null
+++ b/packages/linux/linux-omap2-git/beagleboard/fix-dispc-clocks.patch
@@ -0,0 +1,147 @@
+From linux-omap-owner@vger.kernel.org Sun Jun 22 10:11:39 2008

+Received: from localhost

+	([127.0.0.1] helo=dominion ident=koen)

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+	(envelope-from <linux-omap-owner@vger.kernel.org>)

+	id 1KAKfj-0008Qc-FC

+	for koen@localhost; Sun, 22 Jun 2008 10:11:39 +0200

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+	<rfc822;linux-omap@vger.kernel.org>); Sat, 21 Jun 2008 13:05:11 -0400

+Received: (qmail 20532 invoked by uid 526); 21 Jun 2008 17:05:10 -0000

+Date: 	Sat, 21 Jun 2008 11:05:10 -0600 (MDT)

+From: Paul Walmsley <paul@pwsan.com>

+To: "Gadiyar, Anand" <gadiyar@ti.com>,

+        "linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>

+cc: Dirk Behme <dirk.behme@googlemail.com>,

+        "jouni.hogander@nokia.com" <jouni.hogander@nokia.com>

+Subject: [PATCH] OMAP3 clock: fix omap2_clk_wait_ready for OMAP3430ES2 DSS

+In-Reply-To: <5A47E75E594F054BAF48C5E4FC4B92AB022BB66209@dbde02.ent.ti.com>

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+References: <5A47E75E594F054BAF48C5E4FC4B92AB022BE46296@dbde02.ent.ti.com>,<485CA347.909@googlemail.com> <5A47E75E594F054BAF48C5E4FC4B92AB022BB66209@dbde02.ent.ti.com>

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+X-OriginalArrivalTime: 21 Jun 2008 17:06:02.0187 (UTC) FILETIME=[157001B0:01C8D3C1]

+

+

+On OMAP3430ES2, DSS has both an initiator standby CM_IDLEST bit, and a

+target idle CM_IDLEST bit.  This is a departure from previous silicon,

+which only had an initiator standby bit.

+

+This means we need to test the target idle bit after enabling

+dss1_alwon_fclk.  Previous clock code has done the wrong thing since ES2

+came out: it's either tested the wrong bit, causing intermittent

+

+    Clock dss1_alwon_fck didn't enable in 100000 tries

+

+messages; or not tested anything at all, causing intermittent crashes 

+during DISPC initialization with:

+

+    Unhandled fault: external abort on non-linefetch (0x1028)

+

+This patch modifies omap2_clk_wait_ready() to wait for the DSS to become

+accessible after dss1_alwon_fclk is enabled.

+

+Thanks to Anand Gadiyar <gadiyar@ti.com> for identifying one of the

+problem patches.

+

+Signed-off-by: Paul Walmsley <paul@pwsan.com>

+---

+

+ arch/arm/mach-omap2/clock.c           |   30 ++++++++++++++++++++++++------

+ arch/arm/mach-omap2/cm-regbits-34xx.h |    4 +++-

+ 2 files changed, 27 insertions(+), 7 deletions(-)

+

+diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c

+index ed15868..1820f75 100644

+--- a/arch/arm/mach-omap2/clock.c

++++ b/arch/arm/mach-omap2/clock.c

+@@ -244,18 +244,36 @@ static void omap2_clk_wait_ready(struct clk *clk)

+ 	}

+ 

+ 	/* REVISIT: What are the appropriate exclusions for 34XX? */

+-	/* OMAP3: ignore DSS-mod clocks */

+-	if (cpu_is_omap34xx() &&

+-	    ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||

+-	     (((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(CORE_MOD, 0)) &&

+-	      clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))

+-		return;

++	if (cpu_is_omap34xx()) {

++

++		/* 3430ES1 DSS and SSI have no target idlest bits */

++		if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0) &&

++		    ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||

++		     ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&

++		      clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))

++			return;

++

++		/* Even for 3430ES2 DSS, only wait for dss1_alwon_fclk */

++		if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0) &&

++		    (reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) &&

++		    clk->enable_bit != OMAP3430_EN_DSS1_SHIFT)

++			return;

++

++	}

+ 

+ 	/* Check if both functional and interface clocks

+ 	 * are running. */

+ 	bit = 1 << clk->enable_bit;

+ 	if (!(__raw_readl((__force void __iomem *)other_reg) & bit))

+ 		return;

++

++	/* OMAP3430ES2 DSS is an unusual case */

++	if (cpu_is_omap34xx() &&

++	    (reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) &&

++	    clk->enable_bit == OMAP3430_EN_DSS1_SHIFT) {

++		bit = OMAP3430ES2_ST_DSS_IDLE;

++	}

++

+ 	st_reg = ((other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */

+ 

+ 	omap2_wait_clock_ready((__force void __iomem *)st_reg, bit, clk->name);

+diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h

+index 6ec66f4..946c552 100644

+--- a/arch/arm/mach-omap2/cm-regbits-34xx.h

++++ b/arch/arm/mach-omap2/cm-regbits-34xx.h

+@@ -500,7 +500,9 @@

+ #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT		0

+ 

+ /* CM_IDLEST_DSS */

+-#define OMAP3430_ST_DSS					(1 << 0)

++#define OMAP3430ES2_ST_DSS_IDLE				(1 << 1)

++#define OMAP3430ES2_ST_DSS_STDBY			(1 << 0)

++#define OMAP3430ES1_ST_DSS				(1 << 0)

+ 

+ /* CM_AUTOIDLE_DSS */

+ #define OMAP3430_AUTO_DSS				(1 << 0)

+--

+To unsubscribe from this list: send the line "unsubscribe linux-omap" in

+the body of a message to majordomo@vger.kernel.org

+More majordomo info at  http://vger.kernel.org/majordomo-info.html

+

diff --git a/packages/linux/linux-omap2-git/beagleboard/flash.patch b/packages/linux/linux-omap2-git/beagleboard/flash.patch
new file mode 100644
index 0000000000..4c76cd97bd
--- /dev/null
+++ b/packages/linux/linux-omap2-git/beagleboard/flash.patch
@@ -0,0 +1,558 @@
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index 13d0043..d582b8f 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -44,7 +44,8 @@ obj-$(CONFIG_MACH_OMAP3EVM)		+= board-omap3evm.o \
+ 					   board-omap3evm-flash.o
+ obj-$(CONFIG_MACH_OMAP3_BEAGLE)		+= board-omap3beagle.o \
+ 					   usb-musb.o usb-ehci.o \
+-					   hsmmc.o
++					   hsmmc.o \
++					   board-omap3beagle-flash.o
+ obj-$(CONFIG_MACH_OMAP_LDP)		+= board-ldp.o \
+ 					   hsmmc.o \
+ 					   usb-musb.o
+diff --git a/arch/arm/mach-omap2/board-omap3beagle-flash.c b/arch/arm/mach-omap2/board-omap3beagle-flash.c
+new file mode 100644
+index 0000000..5346df0
+--- /dev/null
++++ b/arch/arm/mach-omap2/board-omap3beagle-flash.c
+@@ -0,0 +1,119 @@
++/*
++ * board-omap3beagle-flash.c
++ * 
++ * Copyright (c) 2008 Texas Instruments
++ *
++ * Modified from board-omap3evm-flash.c
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++#include <linux/mtd/nand.h>
++#include <linux/types.h>
++#include <linux/io.h>
++
++#include <asm/mach/flash.h>
++#include <asm/arch/board.h>
++#include <asm/arch/gpmc.h>
++#include <asm/arch/nand.h>
++
++#define GPMC_CS0_BASE  0x60
++#define GPMC_CS_SIZE   0x30
++
++static struct mtd_partition omap3beagle_nand_partitions[] = {
++	/* All the partition sizes are listed in terms of NAND block size */
++	{
++		.name		= "X-Loader",
++		.offset		= 0,
++		.size		= 4*(64 * 2048),	
++		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
++	},
++	{
++		.name		= "U-Boot",
++		.offset		= MTDPART_OFS_APPEND,	/* Offset = 0x80000 */
++		.size		= 15*(64 * 2048),
++		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
++	},
++	{
++		.name		= "U-Boot Env",
++		.offset		= MTDPART_OFS_APPEND,	/* Offset = 0x260000 */
++		.size		= 1*(64 * 2048),
++	},
++	{
++		.name		= "Kernel",
++		.offset		= MTDPART_OFS_APPEND,	/* Offset = 0x280000 */
++		.size		= 32*(64 * 2048),
++	},
++	{
++		.name		= "File System",
++		.offset		= MTDPART_OFS_APPEND,	/* Offset = 0x680000 */
++		.size		= MTDPART_SIZ_FULL,
++	},
++};
++
++static struct omap_nand_platform_data omap3beagle_nand_data = {
++	.parts		= omap3beagle_nand_partitions,
++	.nr_parts	= ARRAY_SIZE(omap3beagle_nand_partitions),
++	.dma_channel	= -1,		/* disable DMA in OMAP NAND driver */
++	.nand_setup	= NULL,
++	.dev_ready	= NULL,
++};
++
++static struct resource omap3beagle_nand_resource = {
++	.flags		= IORESOURCE_MEM,
++};
++
++static struct platform_device omap3beagle_nand_device = {
++	.name		= "omap2-nand",
++	.id		= -1,
++	.dev		= {
++		.platform_data	= &omap3beagle_nand_data,
++	},
++	.num_resources	= 1,
++	.resource	= &omap3beagle_nand_resource,
++};
++
++
++void __init omap3beagle_flash_init(void)
++{
++	u8 cs = 0;
++	u8 nandcs = GPMC_CS_NUM + 1;
++
++	u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
++
++	/* find out the chip-select on which NAND exists */
++	while (cs < GPMC_CS_NUM) {
++		u32 ret = 0;
++		ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
++
++		if ((ret & 0xC00) == 0x800) {
++			printk(KERN_INFO "Found NAND on CS%d\n", cs);
++			if (nandcs > GPMC_CS_NUM)
++				nandcs = cs;
++		}
++		cs++;
++	}
++
++	if (nandcs > GPMC_CS_NUM) {
++		printk(KERN_INFO "NAND: Unable to find configuration "
++				 "in GPMC\n ");
++		return;
++	}
++
++	if (nandcs < GPMC_CS_NUM) {
++		omap3beagle_nand_data.cs = nandcs;
++		omap3beagle_nand_data.gpmc_cs_baseaddr = (void *)(gpmc_base_add +
++			GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
++		omap3beagle_nand_data.gpmc_baseaddr = (void *) (gpmc_base_add);
++
++		printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
++		if (platform_device_register(&omap3beagle_nand_device) < 0)
++			printk(KERN_ERR "Unable to register NAND device\n");
++	}
++}
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index c992cc7..99e042e 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -94,6 +94,7 @@ static void __init omap3_beagle_init(void)
+ 	hsmmc_init();
+ 	usb_musb_init();
+ 	usb_ehci_init();
++	omap3beagle_flash_init();
+ }
+ 
+ arch_initcall(omap3_beagle_i2c_init);
+diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
+index 3d5e432..02b9ced 100644
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -71,7 +71,7 @@ config MTD_NAND_AMS_DELTA
+ 
+ config MTD_NAND_OMAP2
+ 	tristate "NAND Flash device on OMAP 2420H4/2430SDP boards"
+-	depends on (ARM && ARCH_OMAP2 && MTD_NAND)
++	depends on ARM && MTD_NAND && (ARCH_OMAP2 || ARCH_OMAP3)
+ 	help
+           Support for NAND flash on Texas Instruments 2430SDP/2420H4 platforms.
+ 
+diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
+index 3b7307c..3aac1d2 100644
+--- a/drivers/mtd/nand/omap2.c
++++ b/drivers/mtd/nand/omap2.c
+@@ -111,15 +111,6 @@
+ static const char *part_probes[] = { "cmdlinepart", NULL };
+ #endif
+ 
+-static int hw_ecc = 1;
+-
+-/* new oob placement block for use with hardware ecc generation */
+-static struct nand_ecclayout omap_hw_eccoob = {
+-	.eccbytes = 12,
+-	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
+-	.oobfree = {{16, 32}, {33, 63} },
+-};
+-
+ struct omap_nand_info {
+ 	struct nand_hw_control		controller;
+ 	struct omap_nand_platform_data	*pdata;
+@@ -133,6 +124,13 @@ struct omap_nand_info {
+ 	void __iomem			*gpmc_cs_baseaddr;
+ 	void __iomem			*gpmc_baseaddr;
+ };
++
++/*
++ * omap_nand_wp - This function enable or disable the Write Protect feature on
++ * NAND device
++ * @mtd: MTD device structure
++ * @mode: WP ON/OFF
++ */
+ static void omap_nand_wp(struct mtd_info *mtd, int mode)
+ {
+ 	struct omap_nand_info *info = container_of(mtd,
+@@ -189,11 +187,11 @@ static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+ }
+ 
+ /*
+-* omap_read_buf - read data from NAND controller into buffer
+-* @mtd: MTD device structure
+-* @buf: buffer to store date
+-* @len: number of bytes to read
+-*/
++ * omap_read_buf - read data from NAND controller into buffer
++ * @mtd: MTD device structure
++ * @buf: buffer to store date
++ * @len: number of bytes to read
++ */
+ static void omap_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+ {
+ 	struct omap_nand_info *info = container_of(mtd,
+@@ -207,11 +205,11 @@ static void omap_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+ }
+ 
+ /*
+-* omap_write_buf - write buffer to NAND controller
+-* @mtd: MTD device structure
+-* @buf: data buffer
+-* @len: number of bytes to write
+-*/
++ * omap_write_buf - write buffer to NAND controller
++ * @mtd: MTD device structure
++ * @buf: data buffer
++ * @len: number of bytes to write
++ */
+ static void omap_write_buf(struct mtd_info *mtd, const u_char * buf, int len)
+ {
+ 	struct omap_nand_info *info = container_of(mtd,
+@@ -250,10 +248,16 @@ static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
+ 	return 0;
+ }
+ 
++#ifdef CONFIG_MTD_NAND_OMAP_HWECC
++/*
++ * omap_hwecc_init-Initialize the Hardware ECC for NAND flash in GPMC controller
++ * @mtd: MTD device structure
++ */
+ static void omap_hwecc_init(struct mtd_info *mtd)
+ {
+ 	struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
+ 							mtd);
++	register struct nand_chip *chip = mtd->priv;
+ 	unsigned long val = 0x0;
+ 
+ 	/* Read from ECC Control Register */
+@@ -264,16 +268,15 @@ static void omap_hwecc_init(struct mtd_info *mtd)
+ 
+ 	/* Read from ECC Size Config Register */
+ 	val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG);
+-	/* ECCSIZE1=512 | ECCSIZE0=8bytes | Select eccResultsize[0123] */
+-	val = ((0x000000FF<<22) | (0x00000003<<12) | (0x0000000F));
++	/* ECCSIZE1=512 | Select eccResultsize[0-3] */
++	val = ((((chip->ecc.size >> 1) - 1) << 22) | (0x0000000F));
+ 	__raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG);
+-
+-
+ }
+ 
+ /*
+- * This function will generate true ECC value, which can be used
++ * gen_true_ecc - This function will generate true ECC value, which can be used
+  * when correcting data read from NAND flash memory core
++ * @ecc_buf: buffer to store ecc code
+  */
+ static void gen_true_ecc(u8 *ecc_buf)
+ {
+@@ -289,8 +292,12 @@ static void gen_true_ecc(u8 *ecc_buf)
+ }
+ 
+ /*
+- * This function compares two ECC's and indicates if there is an error.
+- * If the error can be corrected it will be corrected to the buffer
++ * omap_compare_ecc - This function compares two ECC's and indicates if there
++ * is an error. If the error can be corrected it will be corrected to the
++ * buffer
++ * @ecc_data1:  ecc code from nand spare area
++ * @ecc_data2:  ecc code from hardware register obtained from hardware ecc
++ * @page_data:  page data
+  */
+ static int omap_compare_ecc(u8 *ecc_data1,	/* read from NAND memory */
+ 			    u8 *ecc_data2,	/* read from register */
+@@ -409,6 +416,14 @@ static int omap_compare_ecc(u8 *ecc_data1,	/* read from NAND memory */
+ 	}
+ }
+ 
++/*
++ * omap_correct_data - Compares the ecc read from nand spare area with ECC
++ * registers values and corrects one bit error if it has occured
++ * @mtd: MTD device structure
++ * @dat: page data
++ * @read_ecc: ecc read from nand flash
++ * @calc_ecc: ecc read from ECC registers
++ */
+ static int omap_correct_data(struct mtd_info *mtd, u_char * dat,
+ 				u_char * read_ecc, u_char * calc_ecc)
+ {
+@@ -436,65 +451,64 @@ static int omap_correct_data(struct mtd_info *mtd, u_char * dat,
+ }
+ 
+ /*
+-** Generate non-inverted ECC bytes.
+-**
+-** Using noninverted ECC can be considered ugly since writing a blank
+-** page ie. padding will clear the ECC bytes. This is no problem as long
+-** nobody is trying to write data on the seemingly unused page.
+-**
+-** Reading an erased page will produce an ECC mismatch between
+-** generated and read ECC bytes that has to be dealt with separately.
+-*/
++ * omap_calcuate_ecc - Generate non-inverted ECC bytes.
++ * Using noninverted ECC can be considered ugly since writing a blank
++ * page ie. padding will clear the ECC bytes. This is no problem as long
++ * nobody is trying to write data on the seemingly unused page. Reading
++ * an erased page will produce an ECC mismatch between generated and read
++ * ECC bytes that has to be dealt with separately.
++ * @mtd: MTD device structure
++ * @dat: The pointer to data on which ecc is computed
++ * @ecc_code: The ecc_code buffer
++ */
+ static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
+ 				u_char *ecc_code)
+ {
+ 	struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
+ 							mtd);
+ 	unsigned long val = 0x0;
+-	unsigned long reg, n;
+-
+-	/* Ex NAND_ECC_HW12_2048 */
+-	if ((info->nand.ecc.mode == NAND_ECC_HW) &&
+-		(info->nand.ecc.size  == 2048))
+-		n = 4;
+-	else
+-		n = 1;
++	unsigned long reg;
+ 
+ 	/* Start Reading from HW ECC1_Result = 0x200 */
+ 	reg = (unsigned long)(info->gpmc_baseaddr + GPMC_ECC1_RESULT);
+-	while (n--) {
+-		val = __raw_readl(reg);
+-		*ecc_code++ = val;		/* P128e, ..., P1e */
+-		*ecc_code++ = val >> 16;	/* P128o, ..., P1o */
+-		/* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
+-		*ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
+-		reg += 4;
+-	}
++	val = __raw_readl(reg);
++	*ecc_code++ = val;          /* P128e, ..., P1e */
++	*ecc_code++ = val >> 16;    /* P128o, ..., P1o */
++	/* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
++	*ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
++	reg += 4;
+ 
+ 	return 0;
+-} /* omap_calculate_ecc */
++}
+ 
++/*
++ * omap_enable_hwecc - This function enables the hardware ecc functionality
++ * @mtd: MTD device structure
++ * @mode: Read/Write mode
++ */
+ static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
+ {
+ 	struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
+ 							mtd);
++	register struct nand_chip *chip = mtd->priv;
++	unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
+ 	unsigned long val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONFIG);
+ 
+ 	switch (mode) {
+ 	case NAND_ECC_READ    :
+ 		__raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
+-		/* ECC 16 bit col) | ( CS 0 )  | ECC Enable */
+-		val = (1 << 7) | (0x0) | (0x1) ;
++		/* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
++		val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
+ 		break;
+ 	case NAND_ECC_READSYN :
+-		__raw_writel(0x100, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
+-		/* ECC 16 bit col) | ( CS 0 )  | ECC Enable */
+-		val = (1 << 7) | (0x0) | (0x1) ;
++		 __raw_writel(0x100, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
++		/* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
++		val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
+ 		break;
+ 	case NAND_ECC_WRITE   :
+ 		__raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
+-		/* ECC 16 bit col) | ( CS 0 )  | ECC Enable */
+-		val = (1 << 7) | (0x0) | (0x1) ;
++		/* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
++		val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
+ 		break;
+ 	default:
+ 		DEBUG(MTD_DEBUG_LEVEL0, "Error: Unrecognized Mode[%d]!\n",
+@@ -504,7 +518,38 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
+ 
+ 	__raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONFIG);
+ }
++#endif
+ 
++/*
++ * omap_wait - Wait function is called during Program and erase
++ * operations and the way it is called from MTD layer, we should wait
++ * till the NAND chip is ready after the programming/erase operation
++ * has completed.
++ * @mtd: MTD device structure
++ * @chip: NAND Chip structure
++ */
++static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
++{
++	register struct nand_chip *this = mtd->priv;
++	struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
++							mtd);
++	int status = 0;
++
++	this->IO_ADDR_W = (void *) info->gpmc_cs_baseaddr +
++						GPMC_CS_NAND_COMMAND;
++	this->IO_ADDR_R = (void *) info->gpmc_cs_baseaddr + GPMC_CS_NAND_DATA;
++
++	while (!(status & 0x40)) {
++		 __raw_writeb(NAND_CMD_STATUS & 0xFF, this->IO_ADDR_W);
++		status = __raw_readb(this->IO_ADDR_R);
++	}
++	return status;
++}
++
++/*
++ * omap_dev_ready - calls the platform specific dev_ready function
++ * @mtd: MTD device structure
++ */
+ static int omap_dev_ready(struct mtd_info *mtd)
+ {
+ 	struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
+@@ -534,7 +579,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
+ 	struct omap_nand_info		*info;
+ 	struct omap_nand_platform_data	*pdata;
+ 	int				err;
+-	unsigned long val;
++	unsigned long 			val;
+ 
+ 
+ 	pdata = pdev->dev.platform_data;
+@@ -568,15 +613,20 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	/* Enable RD PIN Monitoring Reg */
+-	val  = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1);
+-	val |= WR_RD_PIN_MONITORING;
+-	gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val);
++	if (pdata->dev_ready) {
++		val  = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1);
++		val |= WR_RD_PIN_MONITORING;
++		gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val);
++	}
+ 
+ 	val  = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG7);
+ 	val &= ~(0xf << 8);
+ 	val |=  (0xc & 0xf) << 8;
+ 	gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG7, val);
+ 
++	/* NAND write protect off */
++	omap_nand_wp(&info->mtd, NAND_WP_OFF);
++
+ 	if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
+ 				pdev->dev.driver->name)) {
+ 		err = -EBUSY;
+@@ -597,29 +647,39 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
+ 	info->nand.write_buf  = omap_write_buf;
+ 	info->nand.verify_buf = omap_verify_buf;
+ 
+-	info->nand.dev_ready  = omap_dev_ready;
+-	info->nand.chip_delay = 0;
+-
+-	/* Options */
+-	info->nand.options   = NAND_BUSWIDTH_16;
+-	info->nand.options  |= NAND_SKIP_BBTSCAN;
+-
+-	if (hw_ecc) {
+-		/* init HW ECC */
+-		omap_hwecc_init(&info->mtd);
+-
+-		info->nand.ecc.calculate = omap_calculate_ecc;
+-		info->nand.ecc.hwctl     = omap_enable_hwecc;
+-		info->nand.ecc.correct   = omap_correct_data;
+-		info->nand.ecc.mode      = NAND_ECC_HW;
+-		info->nand.ecc.bytes     = 12;
+-		info->nand.ecc.size      = 2048;
+-		info->nand.ecc.layout    = &omap_hw_eccoob;
+-
++	/*
++	* If RDY/BSY line is connected to OMAP then use the omap ready funcrtion
++	* and the generic nand_wait function which reads the status register
++	* after monitoring the RDY/BSY line.Otherwise use a standard chip delay
++	* which is slightly more than tR (AC Timing) of the NAND device and read
++	* status register until you get a failure or success
++	*/
++	if (pdata->dev_ready) {
++		info->nand.dev_ready = omap_dev_ready;
++		info->nand.chip_delay = 0;
+ 	} else {
+-		info->nand.ecc.mode = NAND_ECC_SOFT;
++		info->nand.waitfunc = omap_wait;
++		info->nand.chip_delay = 50;
+ 	}
+ 
++	info->nand.options  |= NAND_SKIP_BBTSCAN;
++	if ((gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1) & 0x3000)
++								== 0x1000)
++		info->nand.options  |= NAND_BUSWIDTH_16;
++
++#ifdef CONFIG_MTD_NAND_OMAP_HWECC
++	info->nand.ecc.bytes		= 3;
++	info->nand.ecc.size		= 512;
++	info->nand.ecc.calculate	= omap_calculate_ecc;
++	info->nand.ecc.hwctl		= omap_enable_hwecc;
++	info->nand.ecc.correct		= omap_correct_data;
++	info->nand.ecc.mode		= NAND_ECC_HW;
++
++	/* init HW ECC */
++	omap_hwecc_init(&info->mtd);
++#else
++	info->nand.ecc.mode = NAND_ECC_SOFT;
++#endif
+ 
+ 	/* DIP switches on some boards change between 8 and 16 bit
+ 	 * bus widths for flash.  Try the other width if the first try fails.
+@@ -636,14 +696,12 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
+ 	err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
+ 	if (err > 0)
+ 		add_mtd_partitions(&info->mtd, info->parts, err);
+-	else if (err < 0 && pdata->parts)
++	else if (err <= 0 && pdata->parts)
+ 		add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
+ 	else
+ #endif
+ 		add_mtd_device(&info->mtd);
+ 
+-	omap_nand_wp(&info->mtd, NAND_WP_OFF);
+-
+ 	platform_set_drvdata(pdev, &info->mtd);
+ 
+ 	return 0;
+diff --git a/include/asm-arm/arch-omap/board-omap3beagle.h b/include/asm-arm/arch-omap/board-omap3beagle.h
+index 46dff31..26ecfb8 100644
+--- a/include/asm-arm/arch-omap/board-omap3beagle.h
++++ b/include/asm-arm/arch-omap/board-omap3beagle.h
+@@ -29,5 +29,7 @@
+ #ifndef __ASM_ARCH_OMAP3_BEAGLE_H
+ #define __ASM_ARCH_OMAP3_BEAGLE_H
+ 
++extern void omap3beagle_flash_init(void);
++
+ #endif /* __ASM_ARCH_OMAP3_BEAGLE_H */
+ 
diff --git a/packages/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch b/packages/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch
new file mode 100644
index 0000000000..25e5aad9c9
--- /dev/null
+++ b/packages/linux/linux-omap2-git/beagleboard/omap3-dppl-divider.patch
@@ -0,0 +1,114 @@
+From linux-omap-owner@vger.kernel.org Tue Jun 24 09:24:30 2008
+Received: from localhost
+	([127.0.0.1] helo=dominion ident=koen)
+	by dominion.dominion.void with esmtp (Exim 4.63)
+	(envelope-from <linux-omap-owner@vger.kernel.org>)
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+	for koen@localhost; Tue, 24 Jun 2008 09:24:30 +0200
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+Date: 	Tue, 24 Jun 2008 01:12:35 -0600 (MDT)
+From: Paul Walmsley <paul@pwsan.com>
+To: linux-omap@vger.kernel.org
+Subject: [PATCH] OMAP3 clock: DPLL{1,2}_FCLK clksel can divide by 4
+Message-ID: <alpine.DEB.1.00.0806240111320.9741@utopia.booyaka.com>
+User-Agent: Alpine 1.00 (DEB 882 2007-12-20)
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+X-OriginalArrivalTime: 24 Jun 2008 07:13:04.0264 (UTC) FILETIME=[BE950880:01C8D5C9]
+
+
+OMAP34xx ES2 TRM Delta G to H states that the divider for DPLL1_FCLK and 
+DPLL2_FCLK can divide by 4 in addition to dividing by 1 and 2. Encode this 
+into the OMAP3 clock framework.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+
+ arch/arm/mach-omap2/clock34xx.h |   20 ++++++++++++++++----
+ 1 files changed, 16 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
+index b4dceea..9605744 100644
+--- a/arch/arm/mach-omap2/clock34xx.h
++++ b/arch/arm/mach-omap2/clock34xx.h
+@@ -1029,8 +1029,15 @@ static struct clk corex2_fck = {
+ 
+ /* DPLL power domain clock controls */
+ 
+-static const struct clksel div2_core_clksel[] = {
+-	{ .parent = &core_ck, .rates = div2_rates },
++static const struct clksel_rate div4_rates[] = {
++	{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
++	{ .div = 2, .val = 2, .flags = RATE_IN_343X },
++	{ .div = 4, .val = 4, .flags = RATE_IN_343X },
++	{ .div = 0 }
++};
++
++static const struct clksel div4_core_clksel[] = {
++	{ .parent = &core_ck, .rates = div4_rates },
+ 	{ .parent = NULL }
+ };
+ 
+@@ -1044,7 +1051,7 @@ static struct clk dpll1_fck = {
+ 	.init		= &omap2_init_clksel_parent,
+ 	.clksel_reg	= _OMAP34XX_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+ 	.clksel_mask	= OMAP3430_MPU_CLK_SRC_MASK,
+-	.clksel		= div2_core_clksel,
++	.clksel		= div4_core_clksel,
+ 	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ 				PARENT_CONTROLS_CLOCK,
+ 	.recalc		= &omap2_clksel_recalc,
+@@ -1119,7 +1126,7 @@ static struct clk dpll2_fck = {
+ 	.init		= &omap2_init_clksel_parent,
+ 	.clksel_reg	= _OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+ 	.clksel_mask	= OMAP3430_IVA2_CLK_SRC_MASK,
+-	.clksel		= div2_core_clksel,
++	.clksel		= div4_core_clksel,
+ 	.flags		= CLOCK_IN_OMAP343X | RATE_PROPAGATES |
+ 				PARENT_CONTROLS_CLOCK,
+ 	.recalc		= &omap2_clksel_recalc,
+@@ -1155,6 +1162,11 @@ static struct clk iva2_ck = {
+ 
+ /* Common interface clocks */
+ 
++static const struct clksel div2_core_clksel[] = {
++	{ .parent = &core_ck, .rates = div2_rates },
++	{ .parent = NULL }
++};
++
+ static struct clk l3_ick = {
+ 	.name		= "l3_ick",
+ 	.parent		= &core_ck,
+--
+To unsubscribe from this list: send the line "unsubscribe linux-omap" in
+the body of a message to majordomo@vger.kernel.org
+More majordomo info at  http://vger.kernel.org/majordomo-info.html
+
diff --git a/packages/linux/linux-omap2-git/beagleboard/omap3-jitter.patch b/packages/linux/linux-omap2-git/beagleboard/omap3-jitter.patch
new file mode 100644
index 0000000000..2e0dfd9f13
--- /dev/null
+++ b/packages/linux/linux-omap2-git/beagleboard/omap3-jitter.patch
@@ -0,0 +1,95 @@
+From linux-omap-owner@vger.kernel.org Tue Jun 24 09:24:30 2008
+Received: from localhost
+	([127.0.0.1] helo=dominion ident=koen)
+	by dominion.dominion.void with esmtp (Exim 4.63)
+	(envelope-from <linux-omap-owner@vger.kernel.org>)
+	id 1KB2tC-0005XT-Mj
+	for koen@localhost; Tue, 24 Jun 2008 09:24:30 +0200
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+	 Tue, 24 Jun 2008 09:20:48 +0200
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+Date: 	Tue, 24 Jun 2008 01:11:21 -0600 (MDT)
+From: Paul Walmsley <paul@pwsan.com>
+To: linux-omap@vger.kernel.org
+Subject: [PATCH] OMAP3 clock: fix DPLL jitter correction and rate
+ programming
+Message-ID: <alpine.DEB.1.00.0806240109440.9741@utopia.booyaka.com>
+User-Agent: Alpine 1.00 (DEB 882 2007-12-20)
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+
+
+Fix DPLL jitter correction programming.  Previously, 
+omap3_noncore_dpll_program() stored the FREQSEL jitter correction 
+parameter to the wrong register.  This caused jitter correction to be set 
+incorrectly and also caused the DPLL divider to be programmed incorrectly.
+
+Also, fix DPLL divider programming.  An off-by-one error existed in 
+omap3_noncore_dpll_program(), causing DPLLs to be programmed with a higher 
+divider than intended.
+
+Signed-off-by: Paul Walmsley <paul@pwsan.com>
+---
+
+ arch/arm/mach-omap2/clock34xx.c |   13 ++++++++-----
+ 1 files changed, 8 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
+index 408b51a..8fdf8f3 100644
+--- a/arch/arm/mach-omap2/clock34xx.c
++++ b/arch/arm/mach-omap2/clock34xx.c
+@@ -346,14 +346,17 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
+ 	/* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
+ 	_omap3_noncore_dpll_bypass(clk);
+ 
++	/* Set jitter correction */
++	v = __raw_readl(dd->control_reg);
++	v &= ~dd->freqsel_mask;
++	v |= freqsel << __ffs(dd->freqsel_mask);
++	__raw_writel(v, dd->control_reg);
++
++	/* Set DPLL multiplier, divider */
+ 	v = __raw_readl(dd->mult_div1_reg);
+ 	v &= ~(dd->mult_mask | dd->div1_mask);
+-
+-	/* Set mult (M), div1 (N), freqsel */
+ 	v |= m << __ffs(dd->mult_mask);
+-	v |= n << __ffs(dd->div1_mask);
+-	v |= freqsel << __ffs(dd->freqsel_mask);
+-
++	v |= (n - 1) << __ffs(dd->div1_mask);
+ 	__raw_writel(v, dd->mult_div1_reg);
+ 
+ 	/* We let the clock framework set the other output dividers later */
+--
+To unsubscribe from this list: send the line "unsubscribe linux-omap" in
+the body of a message to majordomo@vger.kernel.org
+More majordomo info at  http://vger.kernel.org/majordomo-info.html
+
diff --git a/packages/linux/linux-omap2-git/beagleboard/soc.patch b/packages/linux/linux-omap2-git/beagleboard/soc.patch
new file mode 100644
index 0000000000..bb97403f29
--- /dev/null
+++ b/packages/linux/linux-omap2-git/beagleboard/soc.patch
@@ -0,0 +1,1173 @@
+diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
+index 3903ab7..468536d 100644
+--- a/sound/soc/codecs/Kconfig
++++ b/sound/soc/codecs/Kconfig
+@@ -44,3 +44,7 @@ config SND_SOC_CS4270_VD33_ERRATA
+ config SND_SOC_TLV320AIC3X
+ 	tristate
+ 	depends on SND_SOC && I2C
++
++config SND_SOC_TWL4030
++	tristate
++	depends on SND_SOC && I2C
+diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
+index 4e1314c..d2c0b12 100644
+--- a/sound/soc/codecs/Makefile
++++ b/sound/soc/codecs/Makefile
+@@ -6,6 +6,7 @@ snd-soc-wm9712-objs := wm9712.o
+ snd-soc-wm9713-objs := wm9713.o
+ snd-soc-cs4270-objs := cs4270.o
+ snd-soc-tlv320aic3x-objs := tlv320aic3x.o
++snd-soc-twl4030-objs := twl4030.o
+ 
+ obj-$(CONFIG_SND_SOC_AC97_CODEC)	+= snd-soc-ac97.o
+ obj-$(CONFIG_SND_SOC_WM8731)	+= snd-soc-wm8731.o
+@@ -15,3 +16,4 @@ obj-$(CONFIG_SND_SOC_WM9712)	+= snd-soc-wm9712.o
+ obj-$(CONFIG_SND_SOC_WM9713)	+= snd-soc-wm9713.o
+ obj-$(CONFIG_SND_SOC_CS4270)	+= snd-soc-cs4270.o
+ obj-$(CONFIG_SND_SOC_TLV320AIC3X)	+= snd-soc-tlv320aic3x.o
++obj-$(CONFIG_SND_SOC_TWL4030)	+= snd-soc-twl4030.o
+diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
+new file mode 100644
+index 0000000..c9eee19
+--- /dev/null
++++ b/sound/soc/codecs/twl4030.c
+@@ -0,0 +1,595 @@
++/*
++ * ALSA SoC TWL4030 codec driver
++ *
++ * Author:      Steve Sakoman, <steve@sakoman.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/pm.h>
++#include <linux/i2c.h>
++#include <linux/platform_device.h>
++#include <linux/i2c/twl4030.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++#include <sound/initval.h>
++
++#include "twl4030.h"
++
++/*
++ * twl4030 register cache & default register settings
++ */
++static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
++	0x00, // this register not used
++	0x93, // REG_CODEC_MODE		(0x1)
++	0xc3, // REG_OPTION		(0x2)
++	0x00, // REG_UNKNOWN		(0x3)
++	0x00, // REG_MICBIAS_CTL	(0x4)
++	0x34, // REG_ANAMICL		(0x5)
++	0x14, // REG_ANAMICR		(0x6)
++	0x0a, // REG_AVADC_CTL		(0x7)
++	0x00, // REG_ADCMICSEL		(0x8)
++	0x00, // REG_DIGMIXING		(0x9)
++	0x0c, // REG_ATXL1PGA		(0xA)
++	0x0c, // REG_ATXR1PGA		(0xB)
++	0x00, // REG_AVTXL2PGA		(0xC)
++	0x00, // REG_AVTXR2PGA		(0xD)
++	0x01, // REG_AUDIO_IF		(0xE)
++	0x00, // REG_VOICE_IF		(0xF)
++	0x00, // REG_ARXR1PGA		(0x10)
++	0x00, // REG_ARXL1PGA		(0x11)
++	0x6c, // REG_ARXR2PGA		(0x12)
++	0x6c, // REG_ARXL2PGA		(0x13)
++	0x00, // REG_VRXPGA		(0x14)
++	0x00, // REG_VSTPGA		(0x15)
++	0x00, // REG_VRX2ARXPGA		(0x16)
++	0x0c, // REG_AVDAC_CTL		(0x17)
++	0x00, // REG_ARX2VTXPGA		(0x18)
++	0x00, // REG_ARXL1_APGA_CTL	(0x19)
++	0x00, // REG_ARXR1_APGA_CTL	(0x1A)
++	0x4b, // REG_ARXL2_APGA_CTL	(0x1B)
++	0x4b, // REG_ARXR2_APGA_CTL	(0x1C)
++	0x00, // REG_ATX2ARXPGA		(0x1D)
++	0x00, // REG_BT_IF		(0x1E)
++	0x00, // REG_BTPGA		(0x1F)
++	0x00, // REG_BTSTPGA		(0x20)
++	0x00, // REG_EAR_CTL		(0x21)
++	0x24, // REG_HS_SEL		(0x22)
++	0x0a, // REG_HS_GAIN_SET	(0x23)
++	0x00, // REG_HS_POPN_SET	(0x24)
++	0x00, // REG_PREDL_CTL		(0x25)
++	0x00, // REG_PREDR_CTL		(0x26)
++	0x00, // REG_PRECKL_CTL		(0x27)
++	0x00, // REG_PRECKR_CTL		(0x28)
++	0x00, // REG_HFL_CTL		(0x29)
++	0x00, // REG_HFR_CTL		(0x2A)
++	0x00, // REG_ALC_CTL		(0x2B)
++	0x00, // REG_ALC_SET1		(0x2C)
++	0x00, // REG_ALC_SET2		(0x2D)
++	0x00, // REG_BOOST_CTL		(0x2E)
++	0x01, // REG_SOFTVOL_CTL	(0x2F)
++	0x00, // REG_DTMF_FREQSEL	(0x30)
++	0x00, // REG_DTMF_TONEXT1H	(0x31)
++	0x00, // REG_DTMF_TONEXT1L	(0x32)
++	0x00, // REG_DTMF_TONEXT2H	(0x33)
++	0x00, // REG_DTMF_TONEXT2L	(0x34)
++	0x00, // REG_DTMF_TONOFF	(0x35)
++	0x00, // REG_DTMF_WANONOFF	(0x36)
++	0x00, // REG_I2S_RX_SCRAMBLE_H	(0x37)
++	0x00, // REG_I2S_RX_SCRAMBLE_M	(0x38)
++	0x00, // REG_I2S_RX_SCRAMBLE_L	(0x39)
++	0x16, // REG_APLL_CTL		(0x3A)
++	0x00, // REG_DTMF_CTL		(0x3B)
++	0x00, // REG_DTMF_PGA_CTL2	(0x3C)
++	0x00, // REG_DTMF_PGA_CTL1	(0x3D)
++	0x00, // REG_MISC_SET_1		(0x3E)
++	0x00, // REG_PCMBTMUX		(0x3F)
++	0x00, // REG_RX_PATH_SEL	(0x43)
++	0x00, // REG_VDL_APGA_CTL	(0x44)
++	0x00, // REG_VIBRA_CTL		(0x45)
++	0x00, // REG_VIBRA_SET		(0x46)
++	0x00, // REG_VIBRA_PWM_SET	(0x47)
++	0x00, // REG_ANAMIC_GAIN	(0x48)
++	0x00, // REG_MISC_SET_2		(0x49)
++};
++
++static void twl4030_dump_registers(void)
++{
++	int i = 0;
++	u8 data;
++
++	printk(KERN_INFO "TWL 4030 Register dump for Audio Module\n");
++
++	for (i = REG_CODEC_MODE; i <= REG_MISC_SET_2; i++) {
++		twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &data, i);
++		printk(KERN_INFO "Register[0x%02x]=0x%02x\n", i, data);
++	}
++}
++
++struct twl4030_priv {
++	unsigned int dummy;
++};
++
++/*
++ * read twl4030 register cache
++ */
++static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
++	unsigned int reg)
++{
++	u8 *cache = codec->reg_cache;
++
++	return cache[reg];
++}
++
++/*
++ * write twl4030 register cache
++ */
++static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
++						u8 reg, u8 value)
++{
++	u8 *cache = codec->reg_cache;
++
++	if (reg >= TWL4030_CACHEREGNUM)
++		return;
++	cache[reg] = value;
++}
++
++/*
++ * write to the twl4030 register space
++ */
++static int twl4030_write(struct snd_soc_codec *codec,
++			unsigned int reg, unsigned int value)
++{
++	twl4030_write_reg_cache(codec, reg, value);
++	return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
++}
++
++static void twl4030_init_chip(void)
++{
++	unsigned char byte;
++	int i;
++
++	twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
++		twl4030_reg[REG_CODEC_MODE] & 0xfd, REG_CODEC_MODE);
++
++	udelay(10); /* 10 ms delay for power settling */
++
++	for (i = REG_OPTION; i <= REG_MISC_SET_2; i++) {
++		twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, twl4030_reg[i], i);
++	}
++
++	twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
++		twl4030_reg[REG_CODEC_MODE], REG_CODEC_MODE);
++
++	udelay(10); /* 10 ms delay for power settling */
++
++	/* initiate offset cancellation */
++	twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
++		twl4030_reg[REG_ANAMICL] | 0x80, REG_ANAMICL);
++
++	/* wait for offset cancellation to complete */
++	twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, REG_ANAMICL);
++	while ((byte & 0x80) == 0x80)
++		twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, REG_ANAMICL);
++
++	twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
++		twl4030_reg[REG_MISC_SET_1] | 0x02, REG_MISC_SET_1);
++
++	twl4030_dump_registers();
++}
++
++static const struct snd_kcontrol_new twl4030_snd_controls[] = {
++	SOC_DOUBLE_R("Master Playback Volume",
++		 REG_ARXL2PGA, REG_ARXR2PGA,
++		0, 127, 0),
++	SOC_DOUBLE_R("Capture Volume",
++		 REG_ATXL1PGA, REG_ATXR1PGA,
++		0, 127, 0),
++};
++
++/* add non dapm controls */
++static int twl4030_add_controls(struct snd_soc_codec *codec)
++{
++	int err, i;
++
++	for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) {
++		err = snd_ctl_add(codec->card,
++				  snd_soc_cnew(&twl4030_snd_controls[i],
++						codec, NULL));
++		if (err < 0)
++			return err;
++	}
++
++	return 0;
++}
++
++#define TWL4030_PWR 0
++
++static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
++	SND_SOC_DAPM_INPUT("INL"),
++	SND_SOC_DAPM_INPUT("INR"),
++
++	SND_SOC_DAPM_OUTPUT("OUTL"),
++	SND_SOC_DAPM_OUTPUT("OUTR"),
++
++	SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
++	SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
++
++	SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0),
++	SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0),
++};
++
++static const char *intercon[][3] = {
++	/* outputs */
++	{"OUTL", NULL, "DACL"},
++	{"OUTR", NULL, "DACR"},
++
++	/* inputs */
++	{"ADCL", NULL, "INL"},
++	{"ADCR", NULL, "INR"},
++
++	/* terminator */
++	{NULL, NULL, NULL},
++};
++
++static int twl4030_add_widgets(struct snd_soc_codec *codec)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(twl4030_dapm_widgets); i++)
++		snd_soc_dapm_new_control(codec, &twl4030_dapm_widgets[i]);
++
++	/* set up audio path interconnects */
++	for (i = 0; intercon[i][0] != NULL; i++)
++		snd_soc_dapm_connect_input(codec, intercon[i][0],
++			intercon[i][1], intercon[i][2]);
++
++	snd_soc_dapm_new_widgets(codec);
++	return 0;
++}
++
++static int twl4030_dapm_event(struct snd_soc_codec *codec, int event)
++{
++
++	printk(KERN_INFO "TWL4030 Audio Codec dapm event\n");
++	switch (event) {
++	case SNDRV_CTL_POWER_D0: /* full On */
++		break;
++	case SNDRV_CTL_POWER_D1: /* partial On */
++	case SNDRV_CTL_POWER_D2: /* partial On */
++		break;
++	case SNDRV_CTL_POWER_D3hot: /* off, with power */
++		break;
++	case SNDRV_CTL_POWER_D3cold: /* off, without power */
++		break;
++	}
++	codec->dapm_state = event;
++
++	return 0;
++}
++
++static void twl4030_power_up (struct snd_soc_codec *codec, u8 mode)
++{
++	twl4030_write(codec, REG_CODEC_MODE, mode & ~CODECPDZ);
++	twl4030_write(codec, REG_CODEC_MODE, mode | CODECPDZ);
++	udelay(10);
++
++	u8 popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET) | (0x40);
++	twl4030_write(codec, REG_HS_POPN_SET, popn);
++
++	u8 hsgain = twl4030_read_reg_cache(codec, REG_HS_GAIN_SET) | (0x0a);
++	twl4030_write(codec, REG_HS_GAIN_SET, hsgain);
++
++	popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET) | (0x02);
++	twl4030_write(codec, REG_HS_POPN_SET, popn);
++}
++
++static void twl4030_power_down (struct snd_soc_codec *codec)
++{
++	u8 popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET) & ~(0x02);
++	twl4030_write(codec, REG_HS_POPN_SET, popn);
++
++	u8 hsgain = twl4030_read_reg_cache(codec, REG_HS_GAIN_SET) & ~(0x0f);
++	twl4030_write(codec, REG_HS_GAIN_SET, hsgain);
++
++	popn = twl4030_read_reg_cache(codec, REG_HS_POPN_SET) & ~(0x40);
++	twl4030_write(codec, REG_HS_POPN_SET, popn);
++
++	u8 mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE) & ~CODECPDZ;
++	twl4030_write(codec, REG_CODEC_MODE, mode);
++	udelay(10);
++}
++
++
++static int twl4030_hw_params(struct snd_pcm_substream *substream,
++			   struct snd_pcm_hw_params *params)
++{
++	struct snd_soc_pcm_runtime *rtd = substream->private_data;
++	struct snd_soc_device *socdev = rtd->socdev;
++	struct snd_soc_codec *codec = socdev->codec;
++	struct twl4030_priv *twl4030 = codec->private_data;
++
++	twl4030_power_down(codec);
++
++	u8 mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE) & ~CODECPDZ;
++
++	mode &= ~APLL_RATE;
++	switch (params_rate(params)) {
++	case 44100:
++		printk(KERN_INFO "TWL4030 hw params: set rate to 44.1khz\n");
++		mode |= APLL_RATE_44100;
++		break;
++	case 48000:
++		printk(KERN_INFO "TWL4030 hw params: set rate to 48khz\n");
++		mode |= APLL_RATE_48000;
++		break;
++	default:
++		printk(KERN_INFO "TWL4030 hw params: unknown rate %d\n", params_rate(params));
++		return -EINVAL;
++	}
++
++	/* bit size */
++	switch (params_format(params)) {
++	case SNDRV_PCM_FORMAT_S16_LE:
++		printk(KERN_INFO "TWL4030 hw params: set format to S16_LE\n");
++		break;
++	case SNDRV_PCM_FORMAT_S24_LE:
++		printk(KERN_INFO "TWL4030 hw params: set format to S24_LE\n");
++		break;
++	default:
++		printk(KERN_INFO "TWL4030 hw params: unknown format %d\n", params_format(params));
++		return -EINVAL;
++	}
++
++	/* change rate and turn codec back on */
++	twl4030_power_up(codec, mode);
++
++	return 0;
++}
++
++static int twl4030_mute(struct snd_soc_codec_dai *dai, int mute)
++{
++	struct snd_soc_codec *codec = dai->codec;
++
++	u8 ldac_reg = twl4030_read_reg_cache(codec, REG_ARXL2PGA);
++	u8 rdac_reg = twl4030_read_reg_cache(codec, REG_ARXR2PGA);
++
++	if (mute) {
++		printk(KERN_INFO "TWL4030 Audio Codec mute\n");
++		twl4030_write(codec, REG_ARXL2PGA, 0x00);
++		twl4030_write(codec, REG_ARXR2PGA, 0x00);
++		twl4030_write_reg_cache(codec, REG_ARXL2PGA, ldac_reg);
++		twl4030_write_reg_cache(codec, REG_ARXR2PGA, rdac_reg);
++	}
++	else {
++		printk(KERN_INFO "TWL4030 Audio Codec unmute: %02x/%02x\n", ldac_reg, rdac_reg);
++		twl4030_write(codec, REG_ARXL2PGA, ldac_reg);
++		twl4030_write(codec, REG_ARXR2PGA, rdac_reg);
++	}
++
++	return 0;
++}
++
++static int twl4030_set_dai_fmt(struct snd_soc_codec_dai *codec_dai,
++			     unsigned int fmt)
++{
++	struct snd_soc_codec *codec = codec_dai->codec;
++	struct twl4030_priv *twl4030 = codec->private_data;
++
++	/* get current format */
++	u8 format = twl4030_read_reg_cache(codec, REG_AUDIO_IF);
++
++	/* set master/slave audio interface */
++	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++	case SND_SOC_DAIFMT_CBM_CFM:
++		printk(KERN_INFO "TWL4030 set dai fmt: master\n");
++		format &= ~(AIF_SLAVE_EN);
++		format |= CLK256FS_EN;
++		break;
++	case SND_SOC_DAIFMT_CBS_CFS:
++		printk(KERN_INFO "TWL4030 set dai fmt: slave\n");
++		format &= ~(CLK256FS_EN);
++ 		format |= AIF_SLAVE_EN;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	/* interface format */
++	format &= ~AIF_FORMAT;
++	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++	case SND_SOC_DAIFMT_I2S:
++		printk(KERN_INFO "TWL4030 set dai fmt: i2s\n");
++		format |= AIF_FORMAT_CODEC;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	/* turn off codec before changing format */
++	twl4030_power_down(codec);
++
++	/* change format */
++	twl4030_write(codec, REG_AUDIO_IF, format);
++
++	u8 mode = twl4030_read_reg_cache(codec, REG_CODEC_MODE);
++	twl4030_power_up(codec, mode);
++
++	return 0;
++}
++
++#define TWL4030_RATES	 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000
++#define TWL4030_FORMATS	 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE
++
++struct snd_soc_codec_dai twl4030_dai = {
++	.name = "twl4030",
++	.playback = {
++		.stream_name = "Playback",
++		.channels_min = 2,
++		.channels_max = 2,
++		.rates = TWL4030_RATES,
++		.formats = TWL4030_FORMATS,},
++	.capture = {
++		.stream_name = "Capture",
++		.channels_min = 2,
++		.channels_max = 2,
++		.rates = TWL4030_RATES,
++		.formats = TWL4030_FORMATS,},
++	.ops = {
++		.hw_params = twl4030_hw_params,
++	},
++	.dai_ops = {
++		.digital_mute = twl4030_mute,
++		.set_fmt = twl4030_set_dai_fmt,
++	}
++};
++
++EXPORT_SYMBOL_GPL(twl4030_dai);
++
++static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
++{
++	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
++	struct snd_soc_codec *codec = socdev->codec;
++
++	printk(KERN_INFO "TWL4030 Audio Codec suspend\n");
++	twl4030_dapm_event(codec, SNDRV_CTL_POWER_D3cold);
++
++	return 0;
++}
++
++static int twl4030_resume(struct platform_device *pdev)
++{
++	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
++	struct snd_soc_codec *codec = socdev->codec;
++	int i;
++	u16 *cache = codec->reg_cache;
++
++	printk(KERN_INFO "TWL4030 Audio Codec resume\n");
++	/* Sync reg_cache with the hardware */
++	for (i = REG_CODEC_MODE; i <= REG_MISC_SET_2; i++) {
++		twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, cache[i], i);
++	}
++	twl4030_dapm_event(codec, SNDRV_CTL_POWER_D3hot);
++	twl4030_dapm_event(codec, codec->suspend_dapm_state);
++	return 0;
++}
++
++/*
++ * initialize the driver
++ * register the mixer and dsp interfaces with the kernel
++ */
++
++static int twl4030_init(struct snd_soc_device *socdev)
++{
++	struct snd_soc_codec *codec = socdev->codec;
++	int ret = 0;
++
++	printk(KERN_INFO "TWL4030 Audio Codec init \n");
++
++	twl4030_init_chip();
++
++	codec->name = "twl4030";
++	codec->owner = THIS_MODULE;
++	codec->read = twl4030_read_reg_cache;
++	codec->write = twl4030_write;
++	codec->dapm_event = twl4030_dapm_event;
++	codec->dai = &twl4030_dai;
++	codec->num_dai = 1;
++	codec->reg_cache_size = sizeof(twl4030_reg);
++	codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg), GFP_KERNEL);
++	if (codec->reg_cache == NULL)
++		return -ENOMEM;
++
++	/* register pcms */
++	ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
++	if (ret < 0) {
++		printk(KERN_ERR "twl4030: failed to create pcms\n");
++		goto pcm_err;
++	}
++
++	twl4030_add_controls(codec);
++	twl4030_add_widgets(codec);
++
++	ret = snd_soc_register_card(socdev);
++	if (ret < 0) {
++		printk(KERN_ERR "twl4030: failed to register card\n");
++		goto card_err;
++	}
++
++	return ret;
++
++card_err:
++	printk(KERN_INFO "TWL4030 Audio Codec init card error\n");
++	snd_soc_free_pcms(socdev);
++	snd_soc_dapm_free(socdev);
++pcm_err:
++	printk(KERN_INFO "TWL4030 Audio Codec init pcm error\n");
++	kfree(codec->reg_cache);
++	return ret;
++}
++
++static struct snd_soc_device *twl4030_socdev;
++
++static int twl4030_probe(struct platform_device *pdev)
++{
++	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
++	struct snd_soc_codec *codec;
++	struct twl4030_priv *twl4030;
++
++	printk(KERN_INFO "TWL4030 Audio Codec probe\n");
++
++	codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
++	if (codec == NULL)
++		return -ENOMEM;
++
++	twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
++	if (twl4030 == NULL) {
++		kfree(codec);
++		return -ENOMEM;
++	}
++
++	codec->private_data = twl4030;
++	socdev->codec = codec;
++	mutex_init(&codec->mutex);
++	INIT_LIST_HEAD(&codec->dapm_widgets);
++	INIT_LIST_HEAD(&codec->dapm_paths);
++
++	twl4030_socdev = socdev;
++	twl4030_init(socdev);
++
++	printk(KERN_INFO "TWL4030 Audio Codec probe exit\n");
++	return 0;
++}
++
++static int twl4030_remove(struct platform_device *pdev)
++{
++	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
++	struct snd_soc_codec *codec = socdev->codec;
++
++	printk(KERN_INFO "TWL4030 Audio Codec remove\n");
++	kfree(codec->private_data);
++	kfree(codec);
++
++	return 0;
++}
++
++struct snd_soc_codec_device soc_codec_dev_twl4030 = {
++	.probe = twl4030_probe,
++	.remove = twl4030_remove,
++	.suspend = twl4030_suspend,
++	.resume = twl4030_resume,
++};
++EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
++
++MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
++MODULE_AUTHOR("Steve Sakoman");
++MODULE_LICENSE("GPL");
+diff --git a/sound/soc/codecs/twl4030.h b/sound/soc/codecs/twl4030.h
+new file mode 100644
+index 0000000..af8eb43
+--- /dev/null
++++ b/sound/soc/codecs/twl4030.h
+@@ -0,0 +1,125 @@
++/*
++ * ALSA SoC TWL4030 codec driver
++ *
++ * Author:      Steve Sakoman, <steve@sakoman.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __TWL4030_AUDIO_H__
++#define __TWL4030_AUDIO_H__
++
++#define REG_CODEC_MODE		0x1
++#define REG_OPTION		0x2
++#define REG_UNKNOWN		0x3
++#define REG_MICBIAS_CTL		0x4
++#define REG_ANAMICL		0x5
++#define REG_ANAMICR		0x6
++#define REG_AVADC_CTL		0x7
++#define REG_ADCMICSEL		0x8
++#define REG_DIGMIXING		0x9
++#define REG_ATXL1PGA		0xA
++#define REG_ATXR1PGA		0xB
++#define REG_AVTXL2PGA		0xC
++#define REG_AVTXR2PGA		0xD
++#define REG_AUDIO_IF		0xE
++#define REG_VOICE_IF		0xF
++#define REG_ARXR1PGA		0x10
++#define REG_ARXL1PGA		0x11
++#define REG_ARXR2PGA		0x12
++#define REG_ARXL2PGA		0x13
++#define REG_VRXPGA		0x14
++#define REG_VSTPGA		0x15
++#define REG_VRX2ARXPGA		0x16
++#define REG_AVDAC_CTL		0x17
++#define REG_ARX2VTXPGA		0x18
++#define REG_ARXL1_APGA_CTL	0x19
++#define REG_ARXR1_APGA_CTL	0x1A
++#define REG_ARXL2_APGA_CTL	0x1B
++#define REG_ARXR2_APGA_CTL	0x1C
++#define REG_ATX2ARXPGA		0x1D
++#define REG_BT_IF		0x1E
++#define REG_BTPGA		0x1F
++#define REG_BTSTPGA		0x20
++#define REG_EAR_CTL		0x21
++#define REG_HS_SEL		0x22
++#define REG_HS_GAIN_SET		0x23
++#define REG_HS_POPN_SET		0x24
++#define REG_PREDL_CTL		0x25
++#define REG_PREDR_CTL		0x26
++#define REG_PRECKL_CTL		0x27
++#define REG_PRECKR_CTL		0x28
++#define REG_HFL_CTL		0x29
++#define REG_HFR_CTL		0x2A
++#define REG_ALC_CTL		0x2B
++#define REG_ALC_SET1		0x2C
++#define REG_ALC_SET2		0x2D
++#define REG_BOOST_CTL		0x2E
++#define REG_SOFTVOL_CTL		0x2F
++#define REG_DTMF_FREQSEL	0x30
++#define REG_DTMF_TONEXT1H	0x31
++#define REG_DTMF_TONEXT1L	0x32
++#define REG_DTMF_TONEXT2H	0x33
++#define REG_DTMF_TONEXT2L	0x34
++#define REG_DTMF_TONOFF		0x35
++#define REG_DTMF_WANONOFF	0x36
++#define REG_I2S_RX_SCRAMBLE_H	0x37
++#define REG_I2S_RX_SCRAMBLE_M	0x38
++#define REG_I2S_RX_SCRAMBLE_L	0x39
++#define REG_APLL_CTL		0x3A
++#define REG_DTMF_CTL		0x3B
++#define REG_DTMF_PGA_CTL2	0x3C
++#define REG_DTMF_PGA_CTL1	0x3D
++#define REG_MISC_SET_1		0x3E
++#define REG_PCMBTMUX		0x3F
++#define REG_RX_PATH_SEL		0x43
++#define REG_VDL_APGA_CTL	0x44
++#define REG_VIBRA_CTL		0x45
++#define REG_VIBRA_SET		0x46
++#define REG_VIBRA_PWM_SET	0x47
++#define REG_ANAMIC_GAIN		0x48
++#define REG_MISC_SET_2		0x49
++
++#define TWL4030_CACHEREGNUM	REG_MISC_SET_2 + 1
++
++/* Bitfield Definitions */
++
++/* CODEC_MODE Fields */
++
++#define APLL_RATE		0xF0
++#define APLL_RATE_8000		0x00
++#define APLL_RATE_11025		0x10
++#define APLL_RATE_12000		0x20
++#define APLL_RATE_16000		0x40
++#define APLL_RATE_22050		0x50
++#define APLL_RATE_24000		0x60
++#define APLL_RATE_32000		0x80
++#define APLL_RATE_44100		0x90
++#define APLL_RATE_48000		0xa0
++#define SEL_16K			0x04
++#define CODECPDZ		0x02
++#define OPT_MODE		0x01
++
++/* AUDIO_IF Fields */
++
++#define AIF_SLAVE_EN		0x80
++#define DATA_WIDTH		0x60
++#define DATA_WIDTH_16S_16W	0x00
++#define DATA_WIDTH_32S_16W	0x40
++#define DATA_WIDTH_32S_24W	0x60
++#define AIF_FORMAT		0x18
++#define AIF_FORMAT_CODEC	0x00
++#define AIF_FORMAT_LEFT		0x08
++#define AIF_FORMAT_RIGHT	0x10
++#define AIF_FORMAT_TDM		0x18
++#define AIF_TRI_EN		0x04
++#define CLK256FS_EN		0x02
++#define AIF_EN			0x01
++
++
++extern struct snd_soc_codec_dai twl4030_dai;
++extern struct snd_soc_codec_device soc_codec_dev_twl4030;
++
++#endif	/* End of __TWL4030_AUDIO_H__ */
+diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig
+index 0230d83..8703cea 100644
+--- a/sound/soc/omap/Kconfig
++++ b/sound/soc/omap/Kconfig
+@@ -16,4 +16,20 @@ config SND_OMAP_SOC_N810
+ 	help
+ 	  Say Y if you want to add support for SoC audio on Nokia N810.
+ 
++config SND_OMAP_SOC_OMAP3EVM
++	tristate "SoC Audio support for OMAP3 EVM"
++	depends on SND_OMAP_SOC && MACH_OMAP3EVM
++	select SND_OMAP_SOC_MCBSP
++	select SND_SOC_TWL4030
++	help
++	  Say Y if you want to add support for SoC audio on the OMAP3 EVM.
++
++config SND_OMAP_SOC_OMAP3BEAGLE
++	tristate "SoC Audio support for OMAP3 Beagle"
++	depends on SND_OMAP_SOC && MACH_OMAP3_BEAGLE
++	select SND_OMAP_SOC_MCBSP
++	select SND_SOC_TWL4030
++	help
++	  Say Y if you want to add support for SoC audio on the OMAP3 Beagle.
++
+ endmenu
+diff --git a/sound/soc/omap/Makefile b/sound/soc/omap/Makefile
+index d8d8d58..638a240 100644
+--- a/sound/soc/omap/Makefile
++++ b/sound/soc/omap/Makefile
+@@ -7,5 +7,10 @@ obj-$(CONFIG_SND_OMAP_SOC_MCBSP) += snd-soc-omap-mcbsp.o
+ 
+ # OMAP Machine Support
+ snd-soc-n810-objs := n810.o
++snd-soc-omap3evm-objs := omap3evm.o
++snd-soc-omap3beagle-objs := omap3beagle.o
+ 
+ obj-$(CONFIG_SND_OMAP_SOC_N810) += snd-soc-n810.o
++obj-$(CONFIG_SND_OMAP_SOC_OMAP3EVM) += snd-soc-omap3evm.o
++obj-$(CONFIG_SND_OMAP_SOC_OMAP3BEAGLE) += snd-soc-omap3beagle.o
++
+diff --git a/sound/soc/omap/omap3beagle.c b/sound/soc/omap/omap3beagle.c
+new file mode 100644
+index 0000000..fb79938
+--- /dev/null
++++ b/sound/soc/omap/omap3beagle.c
+@@ -0,0 +1,180 @@
++/*
++ * omap3beagle.c  --  SoC audio for OMAP3 Beagle
++ *
++ * Author: Steve Sakoman <steve@sakoman.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
++ * 02110-1301 USA
++ *
++ */
++
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++
++#include <asm/mach-types.h>
++#include <asm/arch/hardware.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/mcbsp.h>
++
++#include "omap-mcbsp.h"
++#include "omap-pcm.h"
++#include "../codecs/twl4030.h"
++
++static int omap3beagle_hw_params(struct snd_pcm_substream *substream,
++	struct snd_pcm_hw_params *params)
++{
++	struct snd_soc_pcm_runtime *rtd = substream->private_data;
++	struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
++	struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
++	int ret;
++
++	/* Set codec DAI configuration */
++	ret = codec_dai->dai_ops.set_fmt(codec_dai,
++					 SND_SOC_DAIFMT_I2S |
++					 SND_SOC_DAIFMT_NB_NF |
++					 SND_SOC_DAIFMT_CBM_CFM);
++	if (ret < 0) {
++	printk(KERN_INFO "can't set codec DAI configuration\n");
++		return ret;
++	}
++
++	/* Set cpu DAI configuration */
++	ret = cpu_dai->dai_ops.set_fmt(cpu_dai,
++				       SND_SOC_DAIFMT_I2S |
++				       SND_SOC_DAIFMT_NB_NF |
++				       SND_SOC_DAIFMT_CBM_CFM);
++	if (ret < 0) {
++	printk(KERN_INFO "can't set cpu DAI configuration\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static struct snd_soc_ops omap3beagle_ops = {
++	.hw_params = omap3beagle_hw_params,
++};
++
++static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
++	SND_SOC_DAPM_HP("Headphone Jack", NULL),
++	SND_SOC_DAPM_LINE("Line In", NULL),
++};
++
++static const char *audio_map[][3] = {
++	{"Headphone Jack", NULL, "HPLOUT"},
++	{"Headphone Jack", NULL, "HPROUT"},
++
++	{"Line In", NULL, "Line In"},
++	{"Line In", NULL, "Line In"},
++};
++
++static int omap3beagle_twl4030_init(struct snd_soc_codec *codec)
++{
++	int i;
++
++	printk(KERN_INFO "OMAP3 Beagle TWL4030 SoC init\n");
++
++	/* Add omap3beagle specific widgets */
++	for (i = 0; i < ARRAY_SIZE(twl4030_dapm_widgets); i++)
++		snd_soc_dapm_new_control(codec, &twl4030_dapm_widgets[i]);
++
++	/* Set up omap3beagle specific audio path audio_map */
++	for (i = 0; i < ARRAY_SIZE(audio_map); i++)
++		snd_soc_dapm_connect_input(codec, audio_map[i][0],
++			audio_map[i][1], audio_map[i][2]);
++
++	/* always connected */
++	snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1);
++	snd_soc_dapm_set_endpoint(codec, "Line In", 1);
++
++	snd_soc_dapm_sync_endpoints(codec);
++
++	return 0;
++}
++
++/* Digital audio interface glue - connects codec <--> CPU */
++static struct snd_soc_dai_link omap3beagle_dai = {
++	.name = "TWL4030",
++	.stream_name = "TWL4030",
++	.cpu_dai = &omap_mcbsp_dai[0],
++	.codec_dai = &twl4030_dai,
++	.init = omap3beagle_twl4030_init,
++	.ops = &omap3beagle_ops,
++};
++
++/* Audio machine driver */
++static struct snd_soc_machine snd_soc_machine_omap3beagle = {
++	.name = "omap3beagle",
++	.dai_link = &omap3beagle_dai,
++	.num_links = 1,
++};
++
++/* Audio subsystem */
++static struct snd_soc_device omap3beagle_snd_devdata = {
++	.machine = &snd_soc_machine_omap3beagle,
++	.platform = &omap_soc_platform,
++	.codec_dev = &soc_codec_dev_twl4030,
++};
++
++static struct platform_device *omap3beagle_snd_device;
++
++static int __init omap3beagle_soc_init(void)
++{
++	int ret;
++
++	printk(KERN_INFO "OMAP3 Beagle SoC init\n");
++	if (!machine_is_omap3_beagle()) {
++		printk(KERN_INFO "Not OMAP3 Beagle!\n");
++		return -ENODEV;
++	}
++
++	omap3beagle_snd_device = platform_device_alloc("soc-audio", -1);
++	if (!omap3beagle_snd_device) {
++		printk(KERN_INFO "Platform device allocation failed\n");	
++		return -ENOMEM;
++	}
++
++	platform_set_drvdata(omap3beagle_snd_device, &omap3beagle_snd_devdata);
++	omap3beagle_snd_devdata.dev = &omap3beagle_snd_device->dev;
++	*(unsigned int *)omap3beagle_dai.cpu_dai->private_data = 1; /* McBSP2 */
++
++	ret = platform_device_add(omap3beagle_snd_device);
++	if (ret)
++		goto err1;
++
++	return 0;
++
++err1:
++	printk(KERN_INFO "Unable to add platform device\n");		
++	platform_device_put(omap3beagle_snd_device);
++
++	return ret;
++}
++
++static void __exit omap3beagle_soc_exit(void)
++{
++	printk(KERN_INFO "OMAP3 Beagle SoC exit\n");
++	platform_device_unregister(omap3beagle_snd_device);
++}
++
++module_init(omap3beagle_soc_init);
++module_exit(omap3beagle_soc_exit);
++
++MODULE_AUTHOR("Steve Sakoman <steve@sakoman.com>");
++MODULE_DESCRIPTION("ALSA SoC OMAP3 Beagle");
++MODULE_LICENSE("GPL");
+diff --git a/sound/soc/omap/omap3evm.c b/sound/soc/omap/omap3evm.c
+new file mode 100644
+index 0000000..32d4f5d
+--- /dev/null
++++ b/sound/soc/omap/omap3evm.c
+@@ -0,0 +1,180 @@
++/*
++ * omap3evm.c  --  SoC audio for OMAP3 EVM
++ *
++ * Author: Steve Sakoman <steve@sakoman.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
++ * 02110-1301 USA
++ *
++ */
++
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++
++#include <asm/mach-types.h>
++#include <asm/arch/hardware.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/mcbsp.h>
++
++#include "omap-mcbsp.h"
++#include "omap-pcm.h"
++#include "../codecs/twl4030.h"
++
++static int omap3evm_hw_params(struct snd_pcm_substream *substream,
++	struct snd_pcm_hw_params *params)
++{
++	struct snd_soc_pcm_runtime *rtd = substream->private_data;
++	struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
++	struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
++	int ret;
++
++	/* Set codec DAI configuration */
++	ret = codec_dai->dai_ops.set_fmt(codec_dai,
++					 SND_SOC_DAIFMT_I2S |
++					 SND_SOC_DAIFMT_NB_NF |
++					 SND_SOC_DAIFMT_CBM_CFM);
++	if (ret < 0) {
++	printk(KERN_INFO "can't set codec DAI configuration\n");
++		return ret;
++	}
++
++	/* Set cpu DAI configuration */
++	ret = cpu_dai->dai_ops.set_fmt(cpu_dai,
++				       SND_SOC_DAIFMT_I2S |
++				       SND_SOC_DAIFMT_NB_NF |
++				       SND_SOC_DAIFMT_CBM_CFM);
++	if (ret < 0) {
++	printk(KERN_INFO "can't set cpu DAI configuration\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static struct snd_soc_ops omap3evm_ops = {
++	.hw_params = omap3evm_hw_params,
++};
++
++static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
++	SND_SOC_DAPM_HP("Headphone Jack", NULL),
++	SND_SOC_DAPM_LINE("Line In", NULL),
++};
++
++static const char *audio_map[][3] = {
++	{"Headphone Jack", NULL, "HPLOUT"},
++	{"Headphone Jack", NULL, "HPROUT"},
++
++	{"Line In", NULL, "Line In"},
++	{"Line In", NULL, "Line In"},
++};
++
++static int omap3evm_twl4030_init(struct snd_soc_codec *codec)
++{
++	int i;
++
++	printk(KERN_INFO "OMAP3 EVM TWL4030 SoC init\n");
++
++	/* Add omap3evm specific widgets */
++	for (i = 0; i < ARRAY_SIZE(twl4030_dapm_widgets); i++)
++		snd_soc_dapm_new_control(codec, &twl4030_dapm_widgets[i]);
++
++	/* Set up omap3evm specific audio path audio_map */
++	for (i = 0; i < ARRAY_SIZE(audio_map); i++)
++		snd_soc_dapm_connect_input(codec, audio_map[i][0],
++			audio_map[i][1], audio_map[i][2]);
++
++	/* always connected */
++	snd_soc_dapm_set_endpoint(codec, "Headphone Jack", 1);
++	snd_soc_dapm_set_endpoint(codec, "Line In", 1);
++
++	snd_soc_dapm_sync_endpoints(codec);
++
++	return 0;
++}
++
++/* Digital audio interface glue - connects codec <--> CPU */
++static struct snd_soc_dai_link omap3evm_dai = {
++	.name = "TWL4030",
++	.stream_name = "TWL4030",
++	.cpu_dai = &omap_mcbsp_dai[0],
++	.codec_dai = &twl4030_dai,
++	.init = omap3evm_twl4030_init,
++	.ops = &omap3evm_ops,
++};
++
++/* Audio machine driver */
++static struct snd_soc_machine snd_soc_machine_omap3evm = {
++	.name = "omap3evm",
++	.dai_link = &omap3evm_dai,
++	.num_links = 1,
++};
++
++/* Audio subsystem */
++static struct snd_soc_device omap3evm_snd_devdata = {
++	.machine = &snd_soc_machine_omap3evm,
++	.platform = &omap_soc_platform,
++	.codec_dev = &soc_codec_dev_twl4030,
++};
++
++static struct platform_device *omap3evm_snd_device;
++
++static int __init omap3evm_soc_init(void)
++{
++	int ret;
++
++	printk(KERN_INFO "OMAP3 EVM SoC init\n");
++	if (!machine_is_omap3evm()) {
++		printk(KERN_INFO "Not OMAP3 EVM!\n");
++		return -ENODEV;
++	}
++
++	omap3evm_snd_device = platform_device_alloc("soc-audio", -1);
++	if (!omap3evm_snd_device) {
++		printk(KERN_INFO "Platform device allocation failed\n");	
++		return -ENOMEM;
++	}
++
++	platform_set_drvdata(omap3evm_snd_device, &omap3evm_snd_devdata);
++	omap3evm_snd_devdata.dev = &omap3evm_snd_device->dev;
++	*(unsigned int *)omap3evm_dai.cpu_dai->private_data = 1; /* McBSP2 */
++
++	ret = platform_device_add(omap3evm_snd_device);
++	if (ret)
++		goto err1;
++
++	return 0;
++
++err1:
++	printk(KERN_INFO "Unable to add platform device\n");		
++	platform_device_put(omap3evm_snd_device);
++
++	return ret;
++}
++
++static void __exit omap3evm_soc_exit(void)
++{
++	printk(KERN_INFO "OMAP3 EVM SoC exit\n");
++	platform_device_unregister(omap3evm_snd_device);
++}
++
++module_init(omap3evm_soc_init);
++module_exit(omap3evm_soc_exit);
++
++MODULE_AUTHOR("Steve Sakoman <steve@sakoman.com>");
++MODULE_DESCRIPTION("ALSA SoC OMAP3 EVM");
++MODULE_LICENSE("GPL");
diff --git a/packages/linux/linux-omap2-git/beagleboard/timer-suppression.patch b/packages/linux/linux-omap2-git/beagleboard/timer-suppression.patch
new file mode 100644
index 0000000000..04362c96e3
--- /dev/null
+++ b/packages/linux/linux-omap2-git/beagleboard/timer-suppression.patch
@@ -0,0 +1,43 @@
+diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c
+index b854a89..26f5569 100644
+--- a/kernel/time/tick-sched.c
++++ b/kernel/time/tick-sched.c
+@@ -253,6 +253,16 @@ void tick_nohz_stop_sched_tick(void)
+ 
+ 	/* Schedule the tick, if we are at least one jiffie off */
+ 	if ((long)delta_jiffies >= 1) {
++		/*
++		 * calculate the expiry time for the next timer wheel
++		 * timer
++		 */
++		expires = ktime_add_ns(last_update, tick_period.tv64 *
++					delta_jiffies);
++
++		/* Skip reprogram of event if its not changed */
++		if(ts->tick_stopped && ktime_equal(expires, dev->next_event))
++		goto out2;
+ 
+ 		if (delta_jiffies > 1)
+ 			cpu_set(cpu, nohz_cpu_mask);
+@@ -304,12 +314,7 @@ void tick_nohz_stop_sched_tick(void)
+ 			goto out;
+ 		}
+ 
+-		/*
+-		 * calculate the expiry time for the next timer wheel
+-		 * timer
+-		 */
+-		expires = ktime_add_ns(last_update, tick_period.tv64 *
+-				       delta_jiffies);
++		/* Mark expiries */
+ 		ts->idle_expires = expires;
+ 
+ 		if (ts->nohz_mode == NOHZ_MODE_HIGHRES) {
+@@ -328,6 +333,7 @@ void tick_nohz_stop_sched_tick(void)
+ 		tick_do_update_jiffies64(ktime_get());
+ 		cpu_clear(cpu, nohz_cpu_mask);
+ 	}
++out2:	
+ 	raise_softirq_irqoff(TIMER_SOFTIRQ);
+ out:
+ 	ts->next_jiffies = next_jiffies;
diff --git a/packages/linux/linux-omap2-git/omap3evm/.mtn2git_empty b/packages/linux/linux-omap2-git/omap3evm/.mtn2git_empty
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/packages/linux/linux-omap2-git/omap3evm/.mtn2git_empty
diff --git a/packages/linux/linux-omap2-git/omap3evm/0001-ARM-OMAP-SmartReflex-driver.patch b/packages/linux/linux-omap2-git/omap3evm/0001-ARM-OMAP-SmartReflex-driver.patch
new file mode 100644
index 0000000000..550a4f58be
--- /dev/null
+++ b/packages/linux/linux-omap2-git/omap3evm/0001-ARM-OMAP-SmartReflex-driver.patch
@@ -0,0 +1,1002 @@
+From: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+To: linux-omap@vger.kernel.org
+Cc: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+Subject: [PATCH 1/3] ARM: OMAP: SmartReflex driver, reference source and header files
+Date: 	Mon,  2 Jun 2008 14:30:12 +0300
+
+The following patch set integrates TI's SmartReflex driver. SmartReflex is a
+module that adjusts OMAP3 VDD1 and VDD2 operating voltages around the nominal
+values of current operating point depending on silicon characteristics and
+operating conditions.
+
+The driver creates two sysfs entries into /sys/power/ named "sr_vdd1_autocomp"
+and "sr_vdd2_autocomp" which can be used to activate SmartReflex modules 1 and
+2.
+
+Use the following commands to enable SmartReflex:
+
+echo -n 1 > /sys/power/sr_vdd1_autocomp
+echo -n 1 > /sys/power/sr_vdd2_autocomp
+
+To disable:
+
+echo -n 0 > /sys/power/sr_vdd1_autocomp
+echo -n 0 > /sys/power/sr_vdd2_autocomp
+
+This particular patch adds the TI reference source and header files for
+SmartReflex. Only modifications include minor styling to pass checkpatch.pl
+test.
+
+Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+---
+ arch/arm/mach-omap2/smartreflex.c |  815 +++++++++++++++++++++++++++++++++++++
+ arch/arm/mach-omap2/smartreflex.h |  136 ++++++
+ 2 files changed, 951 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/mach-omap2/smartreflex.c
+ create mode 100644 arch/arm/mach-omap2/smartreflex.h
+
+diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
+new file mode 100644
+index 0000000..dae7460
+--- /dev/null
++++ b/arch/arm/mach-omap2/smartreflex.c
+@@ -0,0 +1,815 @@
++/*
++ * linux/arch/arm/mach-omap3/smartreflex.c
++ *
++ * OMAP34XX SmartReflex Voltage Control
++ *
++ * Copyright (C) 2007 Texas Instruments, Inc.
++ * Lesly A M <x0080970@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/sysfs.h>
++
++#include <asm/arch/prcm.h>
++#include <asm/arch/power_companion.h>
++#include <linux/io.h>
++
++#include "prcm-regs.h"
++#include "smartreflex.h"
++
++
++/* #define DEBUG_SR 1 */
++#ifdef DEBUG_SR
++#  define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__ ,\
++									## args)
++#else
++#  define DPRINTK(fmt, args...)
++#endif
++
++struct omap_sr{
++	int srid;
++	int is_sr_reset;
++	int is_autocomp_active;
++	struct clk *fck;
++	u32 req_opp_no;
++	u32 opp1_nvalue, opp2_nvalue, opp3_nvalue, opp4_nvalue, opp5_nvalue;
++	u32 senp_mod, senn_mod;
++	u32 srbase_addr;
++	u32 vpbase_addr;
++};
++
++static struct omap_sr sr1 = {
++	.srid = SR1,
++	.is_sr_reset = 1,
++	.is_autocomp_active = 0,
++	.srbase_addr = OMAP34XX_SR1_BASE,
++};
++
++static struct omap_sr sr2 = {
++	.srid = SR2,
++	.is_sr_reset = 1,
++	.is_autocomp_active = 0,
++	.srbase_addr = OMAP34XX_SR2_BASE,
++};
++
++static inline void sr_write_reg(struct omap_sr *sr, int offset, u32 value)
++{
++	omap_writel(value, sr->srbase_addr + offset);
++}
++
++static inline void sr_modify_reg(struct omap_sr *sr, int offset, u32 mask,
++								u32 value)
++{
++	u32 reg_val;
++
++	reg_val = omap_readl(sr->srbase_addr + offset);
++	reg_val &= ~mask;
++	reg_val |= value;
++
++	omap_writel(reg_val, sr->srbase_addr + offset);
++}
++
++static inline u32 sr_read_reg(struct omap_sr *sr, int offset)
++{
++	return omap_readl(sr->srbase_addr + offset);
++}
++
++
++#ifndef USE_EFUSE_VALUES
++static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen)
++{
++	u32 gn, rn, mul;
++
++	for (gn = 0; gn < GAIN_MAXLIMIT; gn++) {
++		mul = 1 << (gn + 8);
++		rn = mul / sensor;
++		if (rn < R_MAXLIMIT) {
++			*sengain = gn;
++			*rnsen = rn;
++		}
++	}
++}
++#endif
++
++static int sr_clk_enable(struct omap_sr *sr)
++{
++	if (clk_enable(sr->fck) != 0) {
++		printk(KERN_ERR "Could not enable sr%d_fck\n", sr->srid);
++		goto clk_enable_err;
++	}
++
++	/* set fclk- active , iclk- idle */
++	sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
++						SR_CLKACTIVITY_IOFF_FON);
++
++	return 0;
++
++clk_enable_err:
++	return -1;
++}
++
++static int sr_clk_disable(struct omap_sr *sr)
++{
++	/* set fclk, iclk- idle */
++	sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
++						SR_CLKACTIVITY_IOFF_FOFF);
++
++	clk_disable(sr->fck);
++	sr->is_sr_reset = 1;
++
++	return 0;
++}
++
++static void sr_set_nvalues(struct omap_sr *sr)
++{
++#ifdef USE_EFUSE_VALUES
++	u32 n1, n2;
++#else
++	u32 senpval, sennval;
++	u32 senpgain, senngain;
++	u32 rnsenp, rnsenn;
++#endif
++
++	if (sr->srid == SR1) {
++#ifdef USE_EFUSE_VALUES
++		/* Read values for VDD1 from EFUSE */
++#else
++		/* since E-Fuse Values are not available, calculating the
++		 * reciprocal of the SenN and SenP values for SR1
++		 */
++		sr->senp_mod = 0x03;        /* SenN-M5 enabled */
++		sr->senn_mod = 0x03;
++
++		/* for OPP5 */
++		senpval = 0x848 + 0x330;
++		sennval = 0xacd + 0x330;
++
++		cal_reciprocal(senpval, &senpgain, &rnsenp);
++		cal_reciprocal(sennval, &senngain, &rnsenn);
++
++		sr->opp5_nvalue =
++				((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
++				(senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
++				(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
++				(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
++
++		/* for OPP4 */
++		senpval = 0x727 + 0x2a0;
++		sennval = 0x964 + 0x2a0;
++
++		cal_reciprocal(senpval, &senpgain, &rnsenp);
++		cal_reciprocal(sennval, &senngain, &rnsenn);
++
++		sr->opp4_nvalue =
++				((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
++				(senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
++				(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
++				(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
++
++		/* for OPP3 */
++		senpval = 0x655 + 0x200;
++		sennval = 0x85b + 0x200;
++
++		cal_reciprocal(senpval, &senpgain, &rnsenp);
++		cal_reciprocal(sennval, &senngain, &rnsenn);
++
++		sr->opp3_nvalue =
++				((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
++				(senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
++				(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
++				(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
++
++		/* for OPP2 */
++		senpval = 0x3be + 0x1a0;
++		sennval = 0x506 + 0x1a0;
++
++		cal_reciprocal(senpval, &senpgain, &rnsenp);
++		cal_reciprocal(sennval, &senngain, &rnsenn);
++
++		sr->opp2_nvalue =
++				((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
++				(senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
++				(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
++				(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
++
++		/* for OPP1 */
++		senpval = 0x28c + 0x100;
++		sennval = 0x373 + 0x100;
++
++		cal_reciprocal(senpval, &senpgain, &rnsenp);
++		cal_reciprocal(sennval, &senngain, &rnsenn);
++
++		sr->opp1_nvalue =
++				((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
++				(senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
++				(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
++				(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
++
++		sr_clk_enable(sr);
++		sr_write_reg(sr, NVALUERECIPROCAL, sr->opp3_nvalue);
++		sr_clk_disable(sr);
++
++#endif
++	} else if (sr->srid == SR2) {
++#ifdef USE_EFUSE_VALUES
++		/* Read values for VDD2 from EFUSE */
++#else
++		/* since E-Fuse Values are not available, calculating the
++		 * reciprocal of the SenN and SenP values for SR2
++		 */
++		sr->senp_mod = 0x03;
++		sr->senn_mod = 0x03;
++
++		/* for OPP3 */
++		senpval = 0x579 + 0x200;
++		sennval = 0x76f + 0x200;
++
++		cal_reciprocal(senpval, &senpgain, &rnsenp);
++		cal_reciprocal(sennval, &senngain, &rnsenn);
++
++		sr->opp3_nvalue =
++				((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
++				(senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
++				(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
++				(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
++
++		/* for OPP2 */
++		senpval = 0x390 + 0x1c0;
++		sennval = 0x4f5 + 0x1c0;
++
++		cal_reciprocal(senpval, &senpgain, &rnsenp);
++		cal_reciprocal(sennval, &senngain, &rnsenn);
++
++		sr->opp2_nvalue =
++				((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
++				(senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
++				(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
++				(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
++
++		/* for OPP1 */
++		senpval = 0x25d;
++		sennval = 0x359;
++
++		cal_reciprocal(senpval, &senpgain, &rnsenp);
++		cal_reciprocal(sennval, &senngain, &rnsenn);
++
++		sr->opp1_nvalue =
++				((senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
++				(senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
++				(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
++				(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
++
++#endif
++	}
++
++}
++
++static void sr_configure_vp(int srid)
++{
++	u32 vpconfig;
++
++	if (srid == SR1) {
++		vpconfig = PRM_VP1_CONFIG_ERROROFFSET | PRM_VP1_CONFIG_ERRORGAIN
++			| PRM_VP1_CONFIG_INITVOLTAGE | PRM_VP1_CONFIG_TIMEOUTEN;
++
++		PRM_VP1_CONFIG = vpconfig;
++		PRM_VP1_VSTEPMIN = PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN |
++						PRM_VP1_VSTEPMIN_VSTEPMIN;
++
++		PRM_VP1_VSTEPMAX = PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX |
++						PRM_VP1_VSTEPMAX_VSTEPMAX;
++
++		PRM_VP1_VLIMITTO = PRM_VP1_VLIMITTO_VDDMAX |
++			PRM_VP1_VLIMITTO_VDDMIN | PRM_VP1_VLIMITTO_TIMEOUT;
++
++		PRM_VP1_CONFIG |= PRM_VP1_CONFIG_INITVDD;
++		PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_INITVDD;
++
++	} else if (srid == SR2) {
++		vpconfig = PRM_VP2_CONFIG_ERROROFFSET | PRM_VP2_CONFIG_ERRORGAIN
++			| PRM_VP2_CONFIG_INITVOLTAGE | PRM_VP2_CONFIG_TIMEOUTEN;
++
++		PRM_VP2_CONFIG = vpconfig;
++		PRM_VP2_VSTEPMIN = PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN |
++						PRM_VP2_VSTEPMIN_VSTEPMIN;
++
++		PRM_VP2_VSTEPMAX = PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX |
++						PRM_VP2_VSTEPMAX_VSTEPMAX;
++
++		PRM_VP2_VLIMITTO = PRM_VP2_VLIMITTO_VDDMAX |
++			PRM_VP2_VLIMITTO_VDDMIN | PRM_VP2_VLIMITTO_TIMEOUT;
++
++		PRM_VP2_CONFIG |= PRM_VP2_CONFIG_INITVDD;
++		PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_INITVDD;
++
++	}
++}
++
++static void sr_configure_vc(void)
++{
++	PRM_VC_SMPS_SA =
++		(R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA1_SHIFT) |
++		(R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA0_SHIFT);
++
++	PRM_VC_SMPS_VOL_RA = (R_VDD2_SR_CONTROL << PRM_VC_SMPS_VOLRA1_SHIFT) |
++				(R_VDD1_SR_CONTROL << PRM_VC_SMPS_VOLRA0_SHIFT);
++
++	PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL0_ON << PRM_VC_CMD_ON_SHIFT) |
++			(PRM_VC_CMD_VAL0_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
++			(PRM_VC_CMD_VAL0_RET << PRM_VC_CMD_RET_SHIFT) |
++			(PRM_VC_CMD_VAL0_OFF << PRM_VC_CMD_OFF_SHIFT);
++
++	PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL1_ON << PRM_VC_CMD_ON_SHIFT) |
++			(PRM_VC_CMD_VAL1_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
++			(PRM_VC_CMD_VAL1_RET << PRM_VC_CMD_RET_SHIFT) |
++			(PRM_VC_CMD_VAL1_OFF << PRM_VC_CMD_OFF_SHIFT);
++
++	PRM_VC_CH_CONF = PRM_VC_CH_CONF_CMD1 | PRM_VC_CH_CONF_RAV1;
++
++	PRM_VC_I2C_CFG = PRM_VC_I2C_CFG_MCODE | PRM_VC_I2C_CFG_HSEN
++							| PRM_VC_I2C_CFG_SREN;
++
++	/* Setup voltctrl and other setup times */
++#ifdef CONFIG_SYSOFFMODE
++	PRM_VOLTCTRL = PRM_VOLTCTRL_AUTO_OFF | PRM_VOLTCTRL_AUTO_RET;
++	PRM_CLKSETUP = PRM_CLKSETUP_DURATION;
++	PRM_VOLTSETUP1 = (PRM_VOLTSETUP_TIME2 << PRM_VOLTSETUP_TIME2_OFFSET) |
++			(PRM_VOLTSETUP_TIME1 << PRM_VOLTSETUP_TIME1_OFFSET);
++	PRM_VOLTOFFSET = PRM_VOLTOFFSET_DURATION;
++	PRM_VOLTSETUP2 = PRM_VOLTSETUP2_DURATION;
++#else
++	PRM_VOLTCTRL |= PRM_VOLTCTRL_AUTO_RET;
++#endif
++
++}
++
++
++static void sr_configure(struct omap_sr *sr)
++{
++	u32 sys_clk, sr_clk_length = 0;
++	u32 sr_config;
++	u32 senp_en , senn_en;
++
++	senp_en = sr->senp_mod;
++	senn_en = sr->senn_mod;
++
++	sys_clk = prcm_get_system_clock_speed();
++
++	switch (sys_clk) {
++	case 12000:
++		sr_clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
++		break;
++	case 13000:
++		sr_clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
++		break;
++	case 19200:
++		sr_clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
++		break;
++	case 26000:
++		sr_clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
++		break;
++	case 38400:
++		sr_clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
++		break;
++	default :
++		printk(KERN_ERR "Invalid sysclk value\n");
++		break;
++	}
++
++	DPRINTK(KERN_DEBUG "SR : sys clk %lu\n", sys_clk);
++	if (sr->srid == SR1) {
++		sr_config = SR1_SRCONFIG_ACCUMDATA |
++			(sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
++			SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
++			SRCONFIG_MINMAXAVG_EN |
++			(senn_en << SRCONFIG_SENNENABLE_SHIFT) |
++			(senp_en << SRCONFIG_SENPENABLE_SHIFT) |
++			SRCONFIG_DELAYCTRL;
++
++		sr_write_reg(sr, SRCONFIG, sr_config);
++
++		sr_write_reg(sr, AVGWEIGHT, SR1_AVGWEIGHT_SENPAVGWEIGHT |
++					SR1_AVGWEIGHT_SENNAVGWEIGHT);
++
++		sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
++			SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
++			(SR1_ERRWEIGHT | SR1_ERRMAXLIMIT | SR1_ERRMINLIMIT));
++
++	} else if (sr->srid == SR2) {
++		sr_config = SR2_SRCONFIG_ACCUMDATA |
++			(sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
++			SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
++			SRCONFIG_MINMAXAVG_EN |
++			(senn_en << SRCONFIG_SENNENABLE_SHIFT) |
++			(senp_en << SRCONFIG_SENPENABLE_SHIFT) |
++			SRCONFIG_DELAYCTRL;
++
++		sr_write_reg(sr, SRCONFIG, sr_config);
++
++		sr_write_reg(sr, AVGWEIGHT, SR2_AVGWEIGHT_SENPAVGWEIGHT |
++					SR2_AVGWEIGHT_SENNAVGWEIGHT);
++
++		sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
++			SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
++			(SR2_ERRWEIGHT | SR2_ERRMAXLIMIT | SR2_ERRMINLIMIT));
++
++	}
++	sr->is_sr_reset = 0;
++}
++
++static void sr_enable(struct omap_sr *sr, u32 target_opp_no)
++{
++	u32 nvalue_reciprocal, current_nvalue;
++
++	sr->req_opp_no = target_opp_no;
++
++	if (sr->srid == SR1) {
++		switch (target_opp_no) {
++		case 5:
++			nvalue_reciprocal = sr->opp5_nvalue;
++			break;
++		case 4:
++			nvalue_reciprocal = sr->opp4_nvalue;
++			break;
++		case 3:
++			nvalue_reciprocal = sr->opp3_nvalue;
++			break;
++		case 2:
++			nvalue_reciprocal = sr->opp2_nvalue;
++			break;
++		case 1:
++			nvalue_reciprocal = sr->opp1_nvalue;
++			break;
++		default:
++			nvalue_reciprocal = sr->opp3_nvalue;
++			break;
++		}
++	} else {
++		switch (target_opp_no) {
++		case 3:
++			nvalue_reciprocal = sr->opp3_nvalue;
++			break;
++		case 2:
++			nvalue_reciprocal = sr->opp2_nvalue;
++			break;
++		case 1:
++			nvalue_reciprocal = sr->opp1_nvalue;
++			break;
++		default:
++			nvalue_reciprocal = sr->opp3_nvalue;
++			break;
++		}
++	}
++
++	current_nvalue = sr_read_reg(sr, NVALUERECIPROCAL);
++
++	if (current_nvalue == nvalue_reciprocal) {
++		DPRINTK("System is already at the desired voltage level\n");
++		return;
++	}
++
++	sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
++
++	/* Enable the interrupt */
++	sr_modify_reg(sr, ERRCONFIG,
++			(ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST),
++			(ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST));
++
++	if (sr->srid == SR1) {
++		/* Enable VP1 */
++		PRM_VP1_CONFIG |= PRM_VP1_CONFIG_VPENABLE;
++	} else if (sr->srid == SR2) {
++		/* Enable VP2 */
++		PRM_VP2_CONFIG |= PRM_VP2_CONFIG_VPENABLE;
++	}
++
++	/* SRCONFIG - enable SR */
++	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
++
++}
++
++static void sr_disable(struct omap_sr *sr)
++{
++	sr->is_sr_reset = 1;
++
++	/* SRCONFIG - disable SR */
++	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, ~SRCONFIG_SRENABLE);
++
++	if (sr->srid == SR1) {
++		/* Enable VP1 */
++		PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
++	} else if (sr->srid == SR2) {
++		/* Enable VP2 */
++		PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
++	}
++}
++
++
++void sr_start_vddautocomap(int srid, u32 target_opp_no)
++{
++	struct omap_sr *sr = NULL;
++
++	if (srid == SR1)
++		sr = &sr1;
++	else if (srid == SR2)
++		sr = &sr2;
++
++	if (sr->is_sr_reset == 1) {
++		sr_clk_enable(sr);
++		sr_configure(sr);
++	}
++
++	if (sr->is_autocomp_active == 1)
++		DPRINTK(KERN_WARNING "SR%d: VDD autocomp is already active\n",
++									srid);
++
++	sr->is_autocomp_active = 1;
++	sr_enable(sr, target_opp_no);
++}
++EXPORT_SYMBOL(sr_start_vddautocomap);
++
++int sr_stop_vddautocomap(int srid)
++{
++	struct omap_sr *sr = NULL;
++
++	if (srid == SR1)
++		sr = &sr1;
++	else if (srid == SR2)
++		sr = &sr2;
++
++	if (sr->is_autocomp_active == 1) {
++		sr_disable(sr);
++		sr_clk_disable(sr);
++		sr->is_autocomp_active = 0;
++		return SR_TRUE;
++	} else {
++		DPRINTK(KERN_WARNING "SR%d: VDD autocomp is not active\n",
++								srid);
++		return SR_FALSE;
++	}
++
++}
++EXPORT_SYMBOL(sr_stop_vddautocomap);
++
++void enable_smartreflex(int srid)
++{
++	u32 target_opp_no = 0;
++	struct omap_sr *sr = NULL;
++
++	if (srid == SR1)
++		sr = &sr1;
++	else if (srid == SR2)
++		sr = &sr2;
++
++	if (sr->is_autocomp_active == 1) {
++		if (sr->is_sr_reset == 1) {
++			if (srid == SR1) {
++				/* Enable SR clks */
++				CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
++				target_opp_no = get_opp_no(current_vdd1_opp);
++
++			} else if (srid == SR2) {
++				/* Enable SR clks */
++				CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
++				target_opp_no = get_opp_no(current_vdd2_opp);
++			}
++
++			sr_configure(sr);
++
++			sr_enable(sr, target_opp_no);
++		}
++	}
++}
++
++void disable_smartreflex(int srid)
++{
++	struct omap_sr *sr = NULL;
++
++	if (srid == SR1)
++		sr = &sr1;
++	else if (srid == SR2)
++		sr = &sr2;
++
++	if (sr->is_autocomp_active == 1) {
++		if (srid == SR1) {
++			/* Enable SR clk */
++			CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
++
++		} else if (srid == SR2) {
++			/* Enable SR clk */
++			CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
++		}
++
++		if (sr->is_sr_reset == 0) {
++
++			sr->is_sr_reset = 1;
++			/* SRCONFIG - disable SR */
++			sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
++							~SRCONFIG_SRENABLE);
++
++			if (sr->srid == SR1) {
++				/* Disable SR clk */
++				CM_FCLKEN_WKUP &= ~SR1_CLK_ENABLE;
++				/* Enable VP1 */
++				PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
++
++			} else if (sr->srid == SR2) {
++				/* Disable SR clk */
++				CM_FCLKEN_WKUP &= ~SR2_CLK_ENABLE;
++				/* Enable VP2 */
++				PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
++			}
++		}
++	}
++}
++
++
++/* Voltage Scaling using SR VCBYPASS */
++int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
++{
++	int ret;
++	int sr_status = 0;
++	u32 vdd, target_opp_no;
++	u32 vc_bypass_value;
++	u32 reg_addr = 0;
++	u32 loop_cnt = 0, retries_cnt = 0;
++
++	vdd = get_vdd(target_opp);
++	target_opp_no = get_opp_no(target_opp);
++
++	if (vdd == PRCM_VDD1) {
++		sr_status = sr_stop_vddautocomap(SR1);
++
++		PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL_0 & ~PRM_VC_CMD_ON_MASK) |
++						(vsel << PRM_VC_CMD_ON_SHIFT);
++		reg_addr = R_VDD1_SR_CONTROL;
++
++	} else if (vdd == PRCM_VDD2) {
++		sr_status = sr_stop_vddautocomap(SR2);
++
++		PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL_1 & ~PRM_VC_CMD_ON_MASK) |
++						(vsel << PRM_VC_CMD_ON_SHIFT);
++		reg_addr = R_VDD2_SR_CONTROL;
++	}
++
++	vc_bypass_value = (vsel << PRM_VC_BYPASS_DATA_SHIFT) |
++			(reg_addr << PRM_VC_BYPASS_REGADDR_SHIFT) |
++			(R_SRI2C_SLAVE_ADDR << PRM_VC_BYPASS_SLAVEADDR_SHIFT);
++
++	PRM_VC_BYPASS_VAL = vc_bypass_value;
++
++	PRM_VC_BYPASS_VAL |= PRM_VC_BYPASS_VALID;
++
++	DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, PRM_VC_BYPASS_VAL);
++	DPRINTK("PRM_IRQST_MPU %X\n", PRM_IRQSTATUS_MPU);
++
++	while ((PRM_VC_BYPASS_VAL & PRM_VC_BYPASS_VALID) != 0x0) {
++		ret = loop_wait(&loop_cnt, &retries_cnt, 10);
++		if (ret != PRCM_PASS) {
++			printk(KERN_INFO "Loop count exceeded in check SR I2C"
++								"write\n");
++			return ret;
++		}
++	}
++
++	omap_udelay(T2_SMPS_UPDATE_DELAY);
++
++	if (sr_status) {
++		if (vdd == PRCM_VDD1)
++			sr_start_vddautocomap(SR1, target_opp_no);
++		else if (vdd == PRCM_VDD2)
++			sr_start_vddautocomap(SR2, target_opp_no);
++	}
++
++	return SR_PASS;
++}
++
++/* Sysfs interface to select SR VDD1 auto compensation */
++static ssize_t omap_sr_vdd1_autocomp_show(struct kset *subsys, char *buf)
++{
++	return sprintf(buf, "%d\n", sr1.is_autocomp_active);
++}
++
++static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys,
++				const char *buf, size_t n)
++{
++	u32 current_vdd1opp_no;
++	unsigned short value;
++
++	if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) {
++		printk(KERN_ERR "sr_vdd1_autocomp: Invalid value\n");
++		return -EINVAL;
++	}
++
++	current_vdd1opp_no = get_opp_no(current_vdd1_opp);
++
++	if (value == 0)
++		sr_stop_vddautocomap(SR1);
++	else
++		sr_start_vddautocomap(SR1, current_vdd1opp_no);
++
++	return n;
++}
++
++static struct subsys_attribute sr_vdd1_autocomp = {
++	.attr = {
++	.name = __stringify(sr_vdd1_autocomp),
++	.mode = 0644,
++	},
++	.show = omap_sr_vdd1_autocomp_show,
++	.store = omap_sr_vdd1_autocomp_store,
++};
++
++/* Sysfs interface to select SR VDD2 auto compensation */
++static ssize_t omap_sr_vdd2_autocomp_show(struct kset *subsys, char *buf)
++{
++	return sprintf(buf, "%d\n", sr2.is_autocomp_active);
++}
++
++static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys,
++				const char *buf, size_t n)
++{
++	u32 current_vdd2opp_no;
++	unsigned short value;
++
++	if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) {
++		printk(KERN_ERR "sr_vdd2_autocomp: Invalid value\n");
++		return -EINVAL;
++	}
++
++	current_vdd2opp_no = get_opp_no(current_vdd2_opp);
++
++	if (value == 0)
++		sr_stop_vddautocomap(SR2);
++	else
++		sr_start_vddautocomap(SR2, current_vdd2opp_no);
++
++	return n;
++}
++
++static struct subsys_attribute sr_vdd2_autocomp = {
++	.attr = {
++	.name = __stringify(sr_vdd2_autocomp),
++	.mode = 0644,
++	},
++	.show = omap_sr_vdd2_autocomp_show,
++	.store = omap_sr_vdd2_autocomp_store,
++};
++
++
++
++static int __init omap3_sr_init(void)
++{
++	int ret = 0;
++	u8 RdReg;
++
++#ifdef CONFIG_ARCH_OMAP34XX
++	sr1.fck = clk_get(NULL, "sr1_fck");
++	if (IS_ERR(sr1.fck))
++		printk(KERN_ERR "Could not get sr1_fck\n");
++
++	sr2.fck = clk_get(NULL, "sr2_fck");
++	if (IS_ERR(sr2.fck))
++		printk(KERN_ERR "Could not get sr2_fck\n");
++#endif /* #ifdef CONFIG_ARCH_OMAP34XX */
++
++	/* Call the VPConfig, VCConfig, set N Values. */
++	sr_set_nvalues(&sr1);
++	sr_configure_vp(SR1);
++
++	sr_set_nvalues(&sr2);
++	sr_configure_vp(SR2);
++
++	sr_configure_vc();
++
++	/* Enable SR on T2 */
++	ret = t2_in(PM_RECEIVER, &RdReg, R_DCDC_GLOBAL_CFG);
++	RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX;
++	ret |= t2_out(PM_RECEIVER, RdReg, R_DCDC_GLOBAL_CFG);
++
++
++	printk(KERN_INFO "SmartReflex driver initialized\n");
++
++	ret = subsys_create_file(&power_subsys, &sr_vdd1_autocomp);
++	if (ret)
++		printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
++
++	ret = subsys_create_file(&power_subsys, &sr_vdd2_autocomp);
++	if (ret)
++		printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
++
++	return 0;
++}
++
++arch_initcall(omap3_sr_init);
+diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
+new file mode 100644
+index 0000000..62907ef
+--- /dev/null
++++ b/arch/arm/mach-omap2/smartreflex.h
+@@ -0,0 +1,136 @@
++/*
++ * linux/arch/arm/mach-omap3/smartreflex.h
++ *
++ * Copyright (C) 2007 Texas Instruments, Inc.
++ * Lesly A M <x0080970@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++
++/* SR Modules */
++#define SR1		1
++#define SR2		2
++
++#define SR_FAIL		1
++#define SR_PASS		0
++
++#define SR_TRUE		1
++#define SR_FALSE	0
++
++#define GAIN_MAXLIMIT	16
++#define R_MAXLIMIT	256
++
++#define SR1_CLK_ENABLE	(0x1 << 6)
++#define SR2_CLK_ENABLE	(0x1 << 7)
++
++/* PRM_VP1_CONFIG */
++#define PRM_VP1_CONFIG_ERROROFFSET	(0x00 << 24)
++#define PRM_VP1_CONFIG_ERRORGAIN	(0x20 << 16)
++
++#define PRM_VP1_CONFIG_INITVOLTAGE	(0x30 << 8) /* 1.2 volt */
++#define PRM_VP1_CONFIG_TIMEOUTEN	(0x1 << 3)
++#define PRM_VP1_CONFIG_INITVDD		(0x1 << 2)
++#define PRM_VP1_CONFIG_FORCEUPDATE	(0x1 << 1)
++#define PRM_VP1_CONFIG_VPENABLE		(0x1 << 0)
++
++/* PRM_VP1_VSTEPMIN */
++#define PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN	(0x01F4 << 8)
++#define PRM_VP1_VSTEPMIN_VSTEPMIN		(0x01 << 0)
++
++/* PRM_VP1_VSTEPMAX */
++#define PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX	(0x01F4 << 8)
++#define PRM_VP1_VSTEPMAX_VSTEPMAX		(0x04 << 0)
++
++/* PRM_VP1_VLIMITTO */
++#define PRM_VP1_VLIMITTO_VDDMAX		(0x3C << 24)
++#define PRM_VP1_VLIMITTO_VDDMIN		(0x0 << 16)
++#define PRM_VP1_VLIMITTO_TIMEOUT	(0xFFFF << 0)
++
++/* PRM_VP2_CONFIG */
++#define PRM_VP2_CONFIG_ERROROFFSET	(0x00 << 24)
++#define PRM_VP2_CONFIG_ERRORGAIN	(0x20 << 16)
++
++#define PRM_VP2_CONFIG_INITVOLTAGE	(0x30 << 8) /* 1.2 volt */
++#define PRM_VP2_CONFIG_TIMEOUTEN	(0x1 << 3)
++#define PRM_VP2_CONFIG_INITVDD		(0x1 << 2)
++#define PRM_VP2_CONFIG_FORCEUPDATE	(0x1 << 1)
++#define PRM_VP2_CONFIG_VPENABLE		(0x1 << 0)
++
++/* PRM_VP2_VSTEPMIN */
++#define PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN	(0x01F4 << 8)
++#define PRM_VP2_VSTEPMIN_VSTEPMIN		(0x01 << 0)
++
++/* PRM_VP2_VSTEPMAX */
++#define PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX	(0x01F4 << 8)
++#define PRM_VP2_VSTEPMAX_VSTEPMAX		(0x04 << 0)
++
++/* PRM_VP2_VLIMITTO */
++#define PRM_VP2_VLIMITTO_VDDMAX		(0x2C << 24)
++#define PRM_VP2_VLIMITTO_VDDMIN		(0x0 << 16)
++#define PRM_VP2_VLIMITTO_TIMEOUT	(0xFFFF << 0)
++
++/* SRCONFIG */
++#define SR1_SRCONFIG_ACCUMDATA		(0x1F4 << 22)
++#define SR2_SRCONFIG_ACCUMDATA		(0x1F4 << 22)
++
++#define SRCLKLENGTH_12MHZ_SYSCLK	0x3C
++#define SRCLKLENGTH_13MHZ_SYSCLK	0x41
++#define SRCLKLENGTH_19MHZ_SYSCLK	0x60
++#define SRCLKLENGTH_26MHZ_SYSCLK	0x82
++#define SRCLKLENGTH_38MHZ_SYSCLK	0xC0
++
++#define SRCONFIG_SRCLKLENGTH_SHIFT	12
++#define SRCONFIG_SENNENABLE_SHIFT	5
++#define SRCONFIG_SENPENABLE_SHIFT	3
++
++#define SRCONFIG_SRENABLE		(0x01 << 11)
++#define SRCONFIG_SENENABLE		(0x01 << 10)
++#define SRCONFIG_ERRGEN_EN		(0x01 << 9)
++#define SRCONFIG_MINMAXAVG_EN		(0x01 << 8)
++
++#define SRCONFIG_DELAYCTRL		(0x01 << 2)
++#define SRCONFIG_CLKCTRL		(0x00 << 0)
++
++/* AVGWEIGHT */
++#define SR1_AVGWEIGHT_SENPAVGWEIGHT	(0x03 << 2)
++#define SR1_AVGWEIGHT_SENNAVGWEIGHT	(0x03 << 0)
++
++#define SR2_AVGWEIGHT_SENPAVGWEIGHT	(0x01 << 2)
++#define SR2_AVGWEIGHT_SENNAVGWEIGHT	(0x01 << 0)
++
++/* NVALUERECIPROCAL */
++#define NVALUERECIPROCAL_SENPGAIN_SHIFT	20
++#define NVALUERECIPROCAL_SENNGAIN_SHIFT	16
++#define NVALUERECIPROCAL_RNSENP_SHIFT	8
++#define NVALUERECIPROCAL_RNSENN_SHIFT	0
++
++/* ERRCONFIG */
++#define SR_CLKACTIVITY_MASK		(0x03 << 20)
++#define SR_ERRWEIGHT_MASK		(0x07 << 16)
++#define SR_ERRMAXLIMIT_MASK		(0xFF << 8)
++#define SR_ERRMINLIMIT_MASK		(0xFF << 0)
++
++#define SR_CLKACTIVITY_IOFF_FOFF	(0x00 << 20)
++#define SR_CLKACTIVITY_IOFF_FON		(0x02 << 20)
++
++#define ERRCONFIG_VPBOUNDINTEN		(0x1 << 31)
++#define ERRCONFIG_VPBOUNDINTST		(0x1 << 30)
++
++#define SR1_ERRWEIGHT			(0x07 << 16)
++#define SR1_ERRMAXLIMIT			(0x02 << 8)
++#define SR1_ERRMINLIMIT			(0xFA << 0)
++
++#define SR2_ERRWEIGHT			(0x07 << 16)
++#define SR2_ERRMAXLIMIT			(0x02 << 8)
++#define SR2_ERRMINLIMIT			(0xF9 << 0)
++
++extern u32 current_vdd1_opp;
++extern u32 current_vdd2_opp;
++extern struct kset power_subsys;
++
++extern inline int loop_wait(u32 *lcnt, u32 *rcnt, u32 delay);
++extern void omap_udelay(u32 udelay);
++
+-- 
+1.5.4.3
diff --git a/packages/linux/linux-omap2-git/omap3evm/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch b/packages/linux/linux-omap2-git/omap3evm/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch
new file mode 100644
index 0000000000..6e31ead2bd
--- /dev/null
+++ b/packages/linux/linux-omap2-git/omap3evm/0001-ASoC-OMAP-Add-basic-support-for-OMAP34xx-in-McBSP.patch
@@ -0,0 +1,55 @@
+From a1dbb6dd28e9815a307b87b8d96dcf371d6cfd58 Mon Sep 17 00:00:00 2001
+From: Jarkko Nikula <jarkko.nikula@nokia.com>
+Date: Mon, 19 May 2008 13:24:41 +0300
+Subject: [PATCH] ASoC: OMAP: Add basic support for OMAP34xx in McBSP DAI driver
+
+This adds support for OMAP34xx McBSP port 1 and 2.
+
+Signed-off-by: Jarkko Nikula <jarkko.nikula@nokia.com>
+---
+ sound/soc/omap/omap-mcbsp.c |   20 +++++++++++++++++++-
+ 1 files changed, 19 insertions(+), 1 deletions(-)
+
+diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
+index 40d87e6..8e6ec9d 100644
+--- a/sound/soc/omap/omap-mcbsp.c
++++ b/sound/soc/omap/omap-mcbsp.c
+@@ -99,6 +99,21 @@ static const unsigned long omap2420_mcbsp_port[][2] = {
+ static const int omap2420_dma_reqs[][2] = {};
+ static const unsigned long omap2420_mcbsp_port[][2] = {};
+ #endif
++#if defined(CONFIG_ARCH_OMAP34XX)
++static const int omap34xx_dma_reqs[][2] = {
++	{ OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
++	{ OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
++};
++static const unsigned long omap34xx_mcbsp_port[][2] = {
++	{ OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR2,
++	  OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR2 },
++	{ OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR2,
++	  OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR2 },
++};
++#else
++static const int omap34xx_dma_reqs[][2] = {};
++static const unsigned long omap34xx_mcbsp_port[][2] = {};
++#endif
+ 
+ static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream)
+ {
+@@ -169,9 +184,12 @@ static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
+ 	} else if (cpu_is_omap2420()) {
+ 		dma = omap2420_dma_reqs[bus_id][substream->stream];
+ 		port = omap2420_mcbsp_port[bus_id][substream->stream];
++	} else if (cpu_is_omap343x()) {
++		dma = omap34xx_dma_reqs[bus_id][substream->stream];
++		port = omap34xx_mcbsp_port[bus_id][substream->stream];
+ 	} else {
+ 		/*
+-		 * TODO: Add support for 2430 and 3430
++		 * TODO: Add support for 2430
+ 		 */
+ 		return -ENODEV;
+ 	}
+-- 
+1.5.5.1
+
diff --git a/packages/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch b/packages/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch
new file mode 100644
index 0000000000..28b1ef2214
--- /dev/null
+++ b/packages/linux/linux-omap2-git/omap3evm/0001-omap3-cpuidle.patch
@@ -0,0 +1,450 @@
+From: "Rajendra Nayak" <rnayak@ti.com>

+To: <linux-omap@vger.kernel.org>

+Subject: [PATCH 01/02] OMAP3 CPUidle driver

+Date: 	Tue, 10 Jun 2008 12:39:00 +0530

+

+This patch adds the OMAP3 cpuidle driver. Irq enable/disable is done in the core cpuidle driver

+before it queries the governor for the next state.

+

+Signed-off-by: Rajendra Nayak <rnayak@ti.com>   

+

+---

+ arch/arm/mach-omap2/Makefile      |    2 

+ arch/arm/mach-omap2/cpuidle34xx.c |  293 ++++++++++++++++++++++++++++++++++++++

+ arch/arm/mach-omap2/cpuidle34xx.h |   51 ++++++

+ arch/arm/mach-omap2/pm34xx.c      |    5 

+ drivers/cpuidle/cpuidle.c         |   10 +

+ 5 files changed, 359 insertions(+), 2 deletions(-)

+

+Index: linux-omap-2.6/arch/arm/mach-omap2/Makefile

+===================================================================

+--- linux-omap-2.6.orig/arch/arm/mach-omap2/Makefile	2008-06-09 20:15:33.855303920 +0530

++++ linux-omap-2.6/arch/arm/mach-omap2/Makefile	2008-06-09 20:15:39.569121361 +0530

+@@ -20,7 +20,7 @@ obj-y					+= pm.o

+ obj-$(CONFIG_ARCH_OMAP2)		+= pm24xx.o

+ obj-$(CONFIG_ARCH_OMAP2420)		+= sleep242x.o

+ obj-$(CONFIG_ARCH_OMAP2430)		+= sleep243x.o

+-obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o

++obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o cpuidle34xx.o

+ obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o

+ endif

+ 

+Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c

+===================================================================

+--- /dev/null	1970-01-01 00:00:00.000000000 +0000

++++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.c	2008-06-10 11:41:27.644820323 +0530

+@@ -0,0 +1,293 @@

++/*

++ * linux/arch/arm/mach-omap2/cpuidle34xx.c

++ *

++ * OMAP3 CPU IDLE Routines

++ *

++ * Copyright (C) 2007-2008 Texas Instruments, Inc.

++ * Rajendra Nayak <rnayak@ti.com>

++ *

++ * Copyright (C) 2007 Texas Instruments, Inc.

++ * Karthik Dasu <karthik-dp@ti.com>

++ *

++ * Copyright (C) 2006 Nokia Corporation

++ * Tony Lindgren <tony@atomide.com>

++ *

++ * Copyright (C) 2005 Texas Instruments, Inc.

++ * Richard Woodruff <r-woodruff2@ti.com>

++ *

++ * This program is free software; you can redistribute it and/or modify

++ * it under the terms of the GNU General Public License version 2 as

++ * published by the Free Software Foundation.

++ */

++

++#include <linux/cpuidle.h>

++#include <asm/arch/pm.h>

++#include <asm/arch/prcm.h>

++#include <asm/arch/powerdomain.h>

++#include <asm/arch/clockdomain.h>

++#include <asm/arch/irqs.h>

++#include "cpuidle34xx.h"

++

++#ifdef CONFIG_CPU_IDLE

++

++struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];

++struct omap3_processor_cx current_cx_state;

++

++static int omap3_idle_bm_check(void)

++{

++	/* Check for omap3_fclks_active() here once available */

++	return 0;

++}

++

++/* omap3_enter_idle - Programs OMAP3 to enter the specified state.

++ * returns the total time during which the system was idle.

++ */

++static int omap3_enter_idle(struct cpuidle_device *dev,

++			struct cpuidle_state *state)

++{

++	struct omap3_processor_cx *cx = cpuidle_get_statedata(state);

++	struct timespec ts_preidle, ts_postidle, ts_idle;

++	struct powerdomain *mpu_pd, *core_pd, *per_pd, *neon_pd;

++	int neon_pwrst;

++

++	current_cx_state = *cx;

++

++	if (cx->type == OMAP3_STATE_C0) {

++		/* Do nothing for C0, not even a wfi */

++		return 0;

++	}

++

++	/* Used to keep track of the total time in idle */

++	getnstimeofday(&ts_preidle);

++

++	mpu_pd = pwrdm_lookup("mpu_pwrdm");

++	core_pd = pwrdm_lookup("core_pwrdm");

++	per_pd = pwrdm_lookup("per_pwrdm");

++	neon_pd = pwrdm_lookup("neon_pwrdm");

++

++	/* Reset previous power state registers */

++	pwrdm_clear_all_prev_pwrst(mpu_pd);

++	pwrdm_clear_all_prev_pwrst(neon_pd);

++	pwrdm_clear_all_prev_pwrst(core_pd);

++	pwrdm_clear_all_prev_pwrst(per_pd);

++

++	if (omap_irq_pending())

++		return 0;

++

++	neon_pwrst = pwrdm_read_pwrst(neon_pd);

++

++	/* Program MPU/NEON to target state */

++	if (cx->mpu_state < PWRDM_POWER_ON) {

++		if (neon_pwrst == PWRDM_POWER_ON) {

++                        if (cx->mpu_state == PWRDM_POWER_RET)

++                                pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_RET);

++                        else if (cx->mpu_state == PWRDM_POWER_OFF)

++                                pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_OFF);

++		}

++		pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);

++	}

++

++	/* Program CORE to target state */

++	if (cx->core_state < PWRDM_POWER_ON)

++		pwrdm_set_next_pwrst(core_pd, cx->core_state);

++

++	/* Execute ARM wfi */

++	omap_sram_idle();

++

++	/* Program MPU/NEON to ON */

++	if (cx->mpu_state < PWRDM_POWER_ON) {

++		if (neon_pwrst == PWRDM_POWER_ON)

++			pwrdm_set_next_pwrst(neon_pd, PWRDM_POWER_ON);

++		pwrdm_set_next_pwrst(mpu_pd, PWRDM_POWER_ON);

++	}

++

++	if (cx->core_state < PWRDM_POWER_ON)

++		pwrdm_set_next_pwrst(core_pd, PWRDM_POWER_ON);

++

++	getnstimeofday(&ts_postidle);

++	ts_idle = timespec_sub(ts_postidle, ts_preidle);

++	return timespec_to_ns(&ts_idle);

++}

++

++/*

++ * omap3_enter_idle_bm - enter function for states with CPUIDLE_FLAG_CHECK_BM

++ *

++ * This function checks for all the pre-requisites needed for OMAP3 to enter

++ * CORE RET/OFF state. It then calls omap3_enter_idle to program the desired

++ * C state.

++ */

++static int omap3_enter_idle_bm(struct cpuidle_device *dev,

++			       struct cpuidle_state *state)

++{

++	struct cpuidle_state *new_state = NULL;

++	int i, j;

++

++	if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {

++

++		/* Find current state in list */

++		for (i = 0; i < OMAP3_MAX_STATES; i++)

++			if (state == &dev->states[i])

++				break;

++		BUG_ON(i == OMAP3_MAX_STATES);

++

++		/* Back up to non 'CHECK_BM' state */

++		for (j = i - 1;  j > 0; j--) {

++			struct cpuidle_state *s = &dev->states[j];

++

++			if (!(s->flags & CPUIDLE_FLAG_CHECK_BM)) {

++				new_state = s;

++				break;

++			}

++		}

++

++		pr_debug("%s: Bus activity: Entering %s (instead of %s)\n",

++			__FUNCTION__, new_state->name, state->name);

++	}

++

++	return omap3_enter_idle(dev, new_state ? : state);

++}

++

++DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);

++

++/* omap3_init_power_states - Initialises the OMAP3 specific C states.

++ * Below is the desciption of each C state.

++ *

++	C0 . System executing code

++	C1 . MPU WFI + Core active

++	C2 . MPU CSWR + Core active

++	C3 . MPU OFF + Core active

++	C4 . MPU CSWR + Core CSWR

++	C5 . MPU OFF + Core CSWR

++	C6 . MPU OFF + Core OFF

++ */

++void omap_init_power_states(void)

++{

++	/* C0 . System executing code */

++	omap3_power_states[0].valid = 1;

++	omap3_power_states[0].type = OMAP3_STATE_C0;

++	omap3_power_states[0].sleep_latency = 0;

++	omap3_power_states[0].wakeup_latency = 0;

++	omap3_power_states[0].threshold = 0;

++	omap3_power_states[0].mpu_state = PWRDM_POWER_ON;

++	omap3_power_states[0].core_state = PWRDM_POWER_ON;

++	omap3_power_states[0].flags = CPUIDLE_FLAG_TIME_VALID |

++				CPUIDLE_FLAG_SHALLOW;

++

++	/* C1 . MPU WFI + Core active */

++	omap3_power_states[1].valid = 1;

++	omap3_power_states[1].type = OMAP3_STATE_C1;

++	omap3_power_states[1].sleep_latency = 10;

++	omap3_power_states[1].wakeup_latency = 10;

++	omap3_power_states[1].threshold = 30;

++	omap3_power_states[1].mpu_state = PWRDM_POWER_ON;

++	omap3_power_states[1].core_state = PWRDM_POWER_ON;

++	omap3_power_states[1].flags = CPUIDLE_FLAG_TIME_VALID |

++				CPUIDLE_FLAG_SHALLOW;

++

++	/* C2 . MPU CSWR + Core active */

++	omap3_power_states[2].valid = 1;

++	omap3_power_states[2].type = OMAP3_STATE_C2;

++	omap3_power_states[2].sleep_latency = 50;

++	omap3_power_states[2].wakeup_latency = 50;

++	omap3_power_states[2].threshold = 300;

++	omap3_power_states[2].mpu_state = PWRDM_POWER_RET;

++	omap3_power_states[2].core_state = PWRDM_POWER_ON;

++	omap3_power_states[2].flags = CPUIDLE_FLAG_TIME_VALID |

++				CPUIDLE_FLAG_BALANCED;

++

++	/* C3 . MPU OFF + Core active */

++	omap3_power_states[3].valid = 0;

++	omap3_power_states[3].type = OMAP3_STATE_C3;

++	omap3_power_states[3].sleep_latency = 1500;

++	omap3_power_states[3].wakeup_latency = 1800;

++	omap3_power_states[3].threshold = 4000;

++	omap3_power_states[3].mpu_state = PWRDM_POWER_OFF;

++	omap3_power_states[3].core_state = PWRDM_POWER_RET;

++	omap3_power_states[3].flags = CPUIDLE_FLAG_TIME_VALID |

++				CPUIDLE_FLAG_BALANCED;

++

++	/* C4 . MPU CSWR + Core CSWR*/

++	omap3_power_states[4].valid = 1;

++	omap3_power_states[4].type = OMAP3_STATE_C4;

++	omap3_power_states[4].sleep_latency = 2500;

++	omap3_power_states[4].wakeup_latency = 7500;

++	omap3_power_states[4].threshold = 12000;

++	omap3_power_states[4].mpu_state = PWRDM_POWER_RET;

++	omap3_power_states[4].core_state = PWRDM_POWER_RET;

++	omap3_power_states[4].flags = CPUIDLE_FLAG_TIME_VALID |

++			CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;

++

++	/* C5 . MPU OFF + Core CSWR */

++	omap3_power_states[5].valid = 0;

++	omap3_power_states[5].type = OMAP3_STATE_C5;

++	omap3_power_states[5].sleep_latency = 3000;

++	omap3_power_states[5].wakeup_latency = 8500;

++	omap3_power_states[5].threshold = 15000;

++	omap3_power_states[5].mpu_state = PWRDM_POWER_OFF;

++	omap3_power_states[5].core_state = PWRDM_POWER_RET;

++	omap3_power_states[5].flags = CPUIDLE_FLAG_TIME_VALID |

++			CPUIDLE_FLAG_BALANCED | CPUIDLE_FLAG_CHECK_BM;

++

++	/* C6 . MPU OFF + Core OFF */

++	omap3_power_states[6].valid = 0;

++	omap3_power_states[6].type = OMAP3_STATE_C6;

++	omap3_power_states[6].sleep_latency = 10000;

++	omap3_power_states[6].wakeup_latency = 30000;

++	omap3_power_states[6].threshold = 300000;

++	omap3_power_states[6].mpu_state = PWRDM_POWER_OFF;

++	omap3_power_states[6].core_state = PWRDM_POWER_OFF;

++	omap3_power_states[6].flags = CPUIDLE_FLAG_TIME_VALID |

++			CPUIDLE_FLAG_DEEP | CPUIDLE_FLAG_CHECK_BM;

++}

++

++struct cpuidle_driver omap3_idle_driver = {

++	.name = 	"omap3_idle",

++	.owner = 	THIS_MODULE,

++};

++/*

++ * omap3_idle_init - Init routine for OMAP3 idle.

++ * Registers the OMAP3 specific cpuidle driver with the cpuidle f/w

++ * with the valid set of states.

++ */

++int omap3_idle_init(void)

++{

++	int i, count = 0;

++	struct omap3_processor_cx *cx;

++	struct cpuidle_state *state;

++	struct cpuidle_device *dev;

++

++	omap_init_power_states();

++	cpuidle_register_driver(&omap3_idle_driver);

++

++	dev = &per_cpu(omap3_idle_dev, smp_processor_id());

++

++	for (i = 0; i < OMAP3_MAX_STATES; i++) {

++		cx = &omap3_power_states[i];

++		state = &dev->states[count];

++

++		if (!cx->valid)

++			continue;

++		cpuidle_set_statedata(state, cx);

++		state->exit_latency = cx->sleep_latency + cx->wakeup_latency;

++		state->target_residency = cx->threshold;

++		state->flags = cx->flags;

++		state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?

++			omap3_enter_idle_bm : omap3_enter_idle;

++		sprintf(state->name, "C%d", count+1);

++		count++;

++	}

++

++	if (!count)

++		return -EINVAL;

++	dev->state_count = count;

++

++	if (cpuidle_register_device(dev)) {

++		printk(KERN_ERR "%s: CPUidle register device failed\n",

++		       __FUNCTION__);

++		return -EIO;

++	}

++

++	return 0;

++}

++__initcall(omap3_idle_init);

++#endif /* CONFIG_CPU_IDLE */

+Index: linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h

+===================================================================

+--- /dev/null	1970-01-01 00:00:00.000000000 +0000

++++ linux-omap-2.6/arch/arm/mach-omap2/cpuidle34xx.h	2008-06-09 20:15:39.569121361 +0530

+@@ -0,0 +1,51 @@

++/*

++ * linux/arch/arm/mach-omap2/cpuidle34xx.h

++ *

++ * OMAP3 cpuidle structure definitions

++ *

++ * Copyright (C) 2007-2008 Texas Instruments, Inc.

++ * Written by Rajendra Nayak <rnayak@ti.com>

++ *

++ * This program is free software; you can redistribute it and/or modify

++ * it under the terms of the GNU General Public License version 2 as

++ * published by the Free Software Foundation.

++ *

++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR

++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED

++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.

++ *

++ * History:

++ *

++ */

++

++#ifndef ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX

++#define ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX

++

++#define OMAP3_MAX_STATES 7

++#define OMAP3_STATE_C0 0 /* C0 - System executing code */

++#define OMAP3_STATE_C1 1 /* C1 - MPU WFI + Core active */

++#define OMAP3_STATE_C2 2 /* C2 - MPU CSWR + Core active */

++#define OMAP3_STATE_C3 3 /* C3 - MPU OFF + Core active */

++#define OMAP3_STATE_C4 4 /* C4 - MPU RET + Core RET */

++#define OMAP3_STATE_C5 5 /* C5 - MPU OFF + Core RET */

++#define OMAP3_STATE_C6 6 /* C6 - MPU OFF + Core OFF */

++

++extern void omap_sram_idle(void);

++extern int omap3_irq_pending(void);

++

++struct omap3_processor_cx {

++	u8 valid;

++	u8 type;

++	u32 sleep_latency;

++	u32 wakeup_latency;

++	u32 mpu_state;

++	u32 core_state;

++	u32 threshold;

++	u32 flags;

++};

++

++void omap_init_power_states(void);

++int omap3_idle_init(void);

++

++#endif /* ARCH_ARM_MACH_OMAP2_CPUIDLE_34XX */

++

+Index: linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c

+===================================================================

+--- linux-omap-2.6.orig/arch/arm/mach-omap2/pm34xx.c	2008-06-09 20:15:33.855303920 +0530

++++ linux-omap-2.6/arch/arm/mach-omap2/pm34xx.c	2008-06-09 20:16:20.976798343 +0530

+@@ -141,7 +141,7 @@ static irqreturn_t prcm_interrupt_handle

+ 	return IRQ_HANDLED;

+ }

+ 

+-static void omap_sram_idle(void)

++void omap_sram_idle(void)

+ {

+ 	/* Variable to tell what needs to be saved and restored

+ 	 * in omap_sram_idle*/

+@@ -156,6 +156,7 @@ static void omap_sram_idle(void)

+ 

+ 	mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);

+ 	switch (mpu_next_state) {

++	case PWRDM_POWER_ON:

+ 	case PWRDM_POWER_RET:

+ 		/* No need to save context */

+ 		save_state = 0;

+@@ -386,7 +387,9 @@ int __init omap3_pm_init(void)

+ 

+ 	prcm_setup_regs();

+ 

++#ifndef CONFIG_CPU_IDLE

+ 	pm_idle = omap3_pm_idle;

++#endif

+ 

+ err1:

+ 	return ret;

+Index: linux-omap-2.6/drivers/cpuidle/cpuidle.c

+===================================================================

+--- linux-omap-2.6.orig/drivers/cpuidle/cpuidle.c	2008-06-09 20:15:33.856303888 +0530

++++ linux-omap-2.6/drivers/cpuidle/cpuidle.c	2008-06-09 20:15:39.570121329 +0530

+@@ -58,6 +58,11 @@ static void cpuidle_idle_call(void)

+ 		return;

+ 	}

+ 

++#ifdef CONFIG_ARCH_OMAP3

++	local_irq_disable();

++	local_fiq_disable();

++#endif

++

+ 	/* ask the governor for the next state */

+ 	next_state = cpuidle_curr_governor->select(dev);

+ 	if (need_resched())

+@@ -70,6 +75,11 @@ static void cpuidle_idle_call(void)

+ 	target_state->time += (unsigned long long)dev->last_residency;

+ 	target_state->usage++;

+ 

++#ifdef CONFIG_ARCH_OMAP3

++	local_irq_enable();

++	local_fiq_enable();

++#endif

++

+ 	/* give the governor an opportunity to reflect on the outcome */

+ 	if (cpuidle_curr_governor->reflect)

+ 		cpuidle_curr_governor->reflect(dev);

+

+--

+To unsubscribe from this list: send the line "unsubscribe linux-omap" in

+the body of a message to majordomo@vger.kernel.org

+More majordomo info at  http://vger.kernel.org/majordomo-info.html

+

diff --git a/packages/linux/linux-omap2-git/omap3evm/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch b/packages/linux/linux-omap2-git/omap3evm/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch
new file mode 100644
index 0000000000..17329be29b
--- /dev/null
+++ b/packages/linux/linux-omap2-git/omap3evm/0001-omap3beagle-add-a-platform-device-to-hook-up-the-GP.patch
@@ -0,0 +1,69 @@
+From 7a444ee080c5f1a62ac5042f1e7926622b3e1ce7 Mon Sep 17 00:00:00 2001
+From: Koen Kooi <koen@openembedded.org>
+Date: Fri, 30 May 2008 13:43:36 +0200
+Subject: [PATCH] ARM: OMAP: omap3beagle: add a platform device to hook up the GPIO leds to the leds-gpio driver
+
+omap3beagle: add a platform device to hook up the GPIO leds to the leds-gpio driver
+ * on revision A5 and earlier board the two leds can't be controlled seperately, should be fixed in rev. B and C boards.
+
+Signed-off-by: Koen Kooi <koen@openembedded.org>
+---
+ arch/arm/mach-omap2/board-omap3beagle.c |   28 ++++++++++++++++++++++++++++
+ 1 files changed, 28 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
+index c992cc7..83891fc 100644
+--- a/arch/arm/mach-omap2/board-omap3beagle.c
++++ b/arch/arm/mach-omap2/board-omap3beagle.c
+@@ -19,6 +19,7 @@
+ #include <linux/err.h>
+ #include <linux/clk.h>
+ #include <linux/io.h>
++#include <linux/leds.h>
+ 
+ #include <asm/hardware.h>
+ #include <asm/mach-types.h>
+@@ -72,6 +73,32 @@ static struct omap_lcd_config omap3_beagle_lcd_config __initdata = {
+ 	.ctrl_name	= "internal",
+ };
+ 
++struct gpio_led gpio_leds[] = {
++	{
++		.name = "beagleboard::led0",
++		.default_trigger = "none",
++		.gpio = 149,
++	},
++	{
++		.name = "beagleboard::led1",
++		.default_trigger = "none",
++		.gpio = 150,
++	},
++};
++
++static struct gpio_led_platform_data gpio_led_info = {
++	.leds = gpio_leds,
++	.num_leds = ARRAY_SIZE(gpio_leds),
++};
++
++static struct platform_device leds_gpio = {
++	.name = "leds-gpio",
++	.id   = -1,
++	.dev  = {
++		.platform_data = &gpio_led_info,
++	},
++};
++
+ static struct omap_board_config_kernel omap3_beagle_config[] __initdata = {
+ 	{ OMAP_TAG_UART,	&omap3_beagle_uart_config },
+ 	{ OMAP_TAG_MMC,		&omap3beagle_mmc_config },
+@@ -83,6 +110,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = {
+ #ifdef CONFIG_RTC_DRV_TWL4030
+ 	&omap3_beagle_twl4030rtc_device,
+ #endif
++	&leds_gpio,
+ };
+ 
+ static void __init omap3_beagle_init(void)
+-- 
+1.5.4.3
+
diff --git a/packages/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch b/packages/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch
new file mode 100644
index 0000000000..8e609395a0
--- /dev/null
+++ b/packages/linux/linux-omap2-git/omap3evm/0002-ARM-OMAP-SmartReflex-driver.patch
@@ -0,0 +1,278 @@
+From: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+To: linux-omap@vger.kernel.org
+Cc: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+Subject: [PATCH 2/3] ARM: OMAP: SmartReflex driver: added required register and bit definitions.
+Date: 	Fri,  6 Jun 2008 12:49:48 +0300
+
+Added new register and bit definitions to enable Smartreflex driver integration.
+Also PRM_VC_SMPS_SA bit definitions' naming was changed to match the naming of
+other similar bit definitions.
+
+Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+---
+ arch/arm/mach-omap2/prm-regbits-34xx.h |   27 ++++++--
+ arch/arm/mach-omap2/smartreflex.h      |  124 ++++++++++++++++++++++++++++++-
+ include/asm-arm/arch-omap/control.h    |   19 +++++
+ include/asm-arm/arch-omap/omap34xx.h   |    2 +
+ 4 files changed, 163 insertions(+), 9 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
+index c6a7940..f82b5a7 100644
+--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
++++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
+@@ -435,10 +435,10 @@
+ /* PM_PWSTST_EMU specific bits */
+ 
+ /* PRM_VC_SMPS_SA */
+-#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT		16
+-#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK		(0x7f << 16)
+-#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT		0
+-#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK		(0x7f << 0)
++#define OMAP3430_SMPS_SA1_SHIFT				16
++#define OMAP3430_SMPS_SA1_MASK				(0x7f << 16)
++#define OMAP3430_SMPS_SA0_SHIFT				0
++#define OMAP3430_SMPS_SA0_MASK				(0x7f << 0)
+ 
+ /* PRM_VC_SMPS_VOL_RA */
+ #define OMAP3430_VOLRA1_SHIFT				16
+@@ -452,7 +452,7 @@
+ #define OMAP3430_CMDRA0_SHIFT				0
+ #define OMAP3430_CMDRA0_MASK				(0xff << 0)
+ 
+-/* PRM_VC_CMD_VAL_0 specific bits */
++/* PRM_VC_CMD_VAL */
+ #define OMAP3430_VC_CMD_ON_SHIFT			24
+ #define OMAP3430_VC_CMD_ON_MASK				(0xFF << 24)
+ #define OMAP3430_VC_CMD_ONLP_SHIFT			16
+@@ -462,7 +462,17 @@
+ #define OMAP3430_VC_CMD_OFF_SHIFT			0
+ #define OMAP3430_VC_CMD_OFF_MASK			(0xFF << 0)
+ 
++/* PRM_VC_CMD_VAL_0 specific bits */
++#define OMAP3430_VC_CMD_VAL0_ON				(0x3 << 4)
++#define OMAP3430_VC_CMD_VAL0_ONLP			(0x3 << 3)
++#define OMAP3430_VC_CMD_VAL0_RET			(0x3 << 3)
++#define OMAP3430_VC_CMD_VAL0_OFF			(0x3 << 3)
++
+ /* PRM_VC_CMD_VAL_1 specific bits */
++#define OMAP3430_VC_CMD_VAL1_ON				(0xB << 2)
++#define OMAP3430_VC_CMD_VAL1_ONLP			(0x3 << 3)
++#define OMAP3430_VC_CMD_VAL1_RET			(0x3 << 3)
++#define OMAP3430_VC_CMD_VAL1_OFF			(0x3 << 3)
+ 
+ /* PRM_VC_CH_CONF */
+ #define OMAP3430_CMD1					(1 << 20)
+@@ -521,6 +531,13 @@
+ #define OMAP3430_AUTO_RET				(1 << 1)
+ #define OMAP3430_AUTO_SLEEP				(1 << 0)
+ 
++/* Constants to define setup durations */
++#define OMAP3430_CLKSETUP_DURATION			0xff
++#define OMAP3430_VOLTSETUP_TIME2			0xfff
++#define OMAP3430_VOLTSETUP_TIME1			0xfff
++#define OMAP3430_VOLTOFFSET_DURATION			0xff
++#define OMAP3430_VOLTSETUP2_DURATION			0xff
++
+ /* PRM_SRAM_PCHARGE */
+ #define OMAP3430_PCHARGE_TIME_SHIFT			0
+ #define OMAP3430_PCHARGE_TIME_MASK			(0xff << 0)
+diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
+index 62907ef..2091a15 100644
+--- a/arch/arm/mach-omap2/smartreflex.h
++++ b/arch/arm/mach-omap2/smartreflex.h
+@@ -1,5 +1,10 @@
++#ifndef __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H
++#define __ARCH_ARM_MACH_OMAP3_SMARTREFLEX_H
+ /*
+- * linux/arch/arm/mach-omap3/smartreflex.h
++ * linux/arch/arm/mach-omap2/smartreflex.h
++ *
++ * Copyright (C) 2008 Nokia Corporation
++ * Kalle Jokiniemi
+  *
+  * Copyright (C) 2007 Texas Instruments, Inc.
+  * Lesly A M <x0080970@ti.com>
+@@ -9,6 +14,21 @@
+  * published by the Free Software Foundation.
+  */
+ 
++#define PHY_TO_OFF_PM_MASTER(p)		(p - 0x36)
++#define PHY_TO_OFF_PM_RECIEVER(p)	(p - 0x5b)
++#define PHY_TO_OFF_PM_INT(p)		(p - 0x2e)
++
++/* SMART REFLEX REG ADDRESS OFFSET */
++#define SRCONFIG	0x00
++#define SRSTATUS	0x04
++#define SENVAL		0x08
++#define SENMIN		0x0C
++#define SENMAX		0x10
++#define SENAVG		0x14
++#define AVGWEIGHT	0x18
++#define NVALUERECIPROCAL	0x1C
++#define SENERROR	0x20
++#define ERRCONFIG	0x24
+ 
+ /* SR Modules */
+ #define SR1		1
+@@ -127,10 +147,106 @@
+ #define SR2_ERRMAXLIMIT			(0x02 << 8)
+ #define SR2_ERRMINLIMIT			(0xF9 << 0)
+ 
++/* T2 SMART REFLEX */
++#define R_SRI2C_SLAVE_ADDR		0x12
++#define R_VDD1_SR_CONTROL		0x00
++#define R_VDD2_SR_CONTROL		0x01
++#define T2_SMPS_UPDATE_DELAY		360	/* In uSec */
++
++/* Vmode control */
++#define R_DCDC_GLOBAL_CFG	PHY_TO_OFF_PM_RECIEVER(0x61)
++
++#define R_VDD1_VSEL		PHY_TO_OFF_PM_RECIEVER(0xb9)
++#define R_VDD1_VMODE_CFG	PHY_TO_OFF_PM_RECIEVER(0xba)
++#define R_VDD1_VFLOOR		PHY_TO_OFF_PM_RECIEVER(0xbb)
++#define R_VDD1_VROOF		PHY_TO_OFF_PM_RECIEVER(0xbc)
++#define R_VDD1_STEP		PHY_TO_OFF_PM_RECIEVER(0xbd)
++
++#define R_VDD2_VSEL		PHY_TO_OFF_PM_RECIEVER(0xc7)
++#define R_VDD2_VMODE_CFG	PHY_TO_OFF_PM_RECIEVER(0xc8)
++#define R_VDD2_VFLOOR		PHY_TO_OFF_PM_RECIEVER(0xc9)
++#define R_VDD2_VROOF		PHY_TO_OFF_PM_RECIEVER(0xca)
++#define R_VDD2_STEP		PHY_TO_OFF_PM_RECIEVER(0xcb)
++
++/* R_DCDC_GLOBAL_CFG register, SMARTREFLEX_ENABLE valuws */
++#define DCDC_GLOBAL_CFG_ENABLE_SRFLX	0x08
++
++/* VDDs*/
++#define PRCM_VDD1	1
++#define PRCM_VDD2	2
++#define PRCM_MAX_SYSC_REGS 30
++
++/* XXX: These should be removed/moved from here once we have a working DVFS
++   implementation in place */
++#define AT_3430		1	/*3430 ES 1.0 */
++#define AT_3430_ES2	2	/*3430 ES 2.0 */
++
++#define ID_OPP			0xE2 	/*OPP*/
++
++/* DEVICE ID/DPLL ID/CLOCK ID: bits 28-31 for OMAP type */
++#define OMAP_TYPE_SHIFT		28
++#define OMAP_TYPE_MASK		0xF
++/* OPP ID: bits: 0-4 for OPP number */
++#define OPP_NO_POS		0
++#define OPP_NO_MASK		0x1F
++/* OPP ID: bits: 5-6 for VDD */
++#define VDD_NO_POS		5
++#define VDD_NO_MASK		0x3
++/* Other IDs: bits 20-27 for ID type */
++/* These IDs have bits 25,26,27 as 1 */
++#define OTHER_ID_TYPE_SHIFT		20
++#define OTHER_ID_TYPE_MASK		0xFF
++
++#define OTHER_ID_TYPE(X) ((X & OTHER_ID_TYPE_MASK) << OTHER_ID_TYPE_SHIFT)
++#define ID_OPP_NO(X)	 ((X & OPP_NO_MASK) << OPP_NO_POS)
++#define ID_VDD(X)	 ((X & VDD_NO_MASK) << VDD_NO_POS)
++#define OMAP(X)		 ((X >> OMAP_TYPE_SHIFT) & OMAP_TYPE_MASK)
++#define get_opp_no(X)	 ((X >> OPP_NO_POS) & OPP_NO_MASK)
++#define get_vdd(X)	 ((X >> VDD_NO_POS) & VDD_NO_MASK)
++
++/* VDD1 OPPs */
++#define PRCM_VDD1_OPP1		(OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
++					ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x1))
++#define PRCM_VDD1_OPP2		(OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
++					ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x2))
++#define PRCM_VDD1_OPP3		(OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
++					ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x3))
++#define PRCM_VDD1_OPP4		(OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
++					ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x4))
++#define PRCM_VDD1_OPP5		(OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
++					ID_VDD(PRCM_VDD1) | ID_OPP_NO(0x5))
++#define PRCM_NO_VDD1_OPPS	5
++
++
++/* VDD2 OPPs */
++#define PRCM_VDD2_OPP1		(OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
++					ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x1))
++#define PRCM_VDD2_OPP2		(OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
++					ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x2))
++#define PRCM_VDD2_OPP3		(OMAP(AT_3430_ES2) | OTHER_ID_TYPE(ID_OPP) | \
++					ID_VDD(PRCM_VDD2) | ID_OPP_NO(0x3))
++#define PRCM_NO_VDD2_OPPS	3
++/* XXX: end remove/move */
++
++
++/* XXX: find more appropriate place for these once DVFS is in place */
+ extern u32 current_vdd1_opp;
+ extern u32 current_vdd2_opp;
+-extern struct kset power_subsys;
+ 
+-extern inline int loop_wait(u32 *lcnt, u32 *rcnt, u32 delay);
+-extern void omap_udelay(u32 udelay);
++/*
++ * Smartreflex module enable/disable interface.
++ * NOTE: if smartreflex is not enabled from sysfs, these functions will not
++ * do anything.
++ */
++#if defined(CONFIG_ARCH_OMAP34XX) && defined(CONFIG_TWL4030_CORE)
++void enable_smartreflex(int srid);
++void disable_smartreflex(int srid);
++#else
++static inline void enable_smartreflex(int srid) {}
++static inline void disable_smartreflex(int srid) {}
++#endif
++
++
++#endif
++
+ 
+diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h
+index 12bc22a..6e64fe7 100644
+--- a/include/asm-arm/arch-omap/control.h
++++ b/include/asm-arm/arch-omap/control.h
+@@ -138,6 +138,15 @@
+ #define OMAP343X_CONTROL_TEST_KEY_11	(OMAP2_CONTROL_GENERAL + 0x00f4)
+ #define OMAP343X_CONTROL_TEST_KEY_12	(OMAP2_CONTROL_GENERAL + 0x00f8)
+ #define OMAP343X_CONTROL_TEST_KEY_13	(OMAP2_CONTROL_GENERAL + 0x00fc)
++#define OMAP343X_CONTROL_FUSE_OPP1_VDD1	(OMAP2_CONTROL_GENERAL + 0x0110)
++#define OMAP343X_CONTROL_FUSE_OPP2_VDD1	(OMAP2_CONTROL_GENERAL + 0x0114)
++#define OMAP343X_CONTROL_FUSE_OPP3_VDD1	(OMAP2_CONTROL_GENERAL + 0x0118)
++#define OMAP343X_CONTROL_FUSE_OPP4_VDD1	(OMAP2_CONTROL_GENERAL + 0x011c)
++#define OMAP343X_CONTROL_FUSE_OPP5_VDD1	(OMAP2_CONTROL_GENERAL + 0x0120)
++#define OMAP343X_CONTROL_FUSE_OPP1_VDD2	(OMAP2_CONTROL_GENERAL + 0x0124)
++#define OMAP343X_CONTROL_FUSE_OPP2_VDD2	(OMAP2_CONTROL_GENERAL + 0x0128)
++#define OMAP343X_CONTROL_FUSE_OPP3_VDD2	(OMAP2_CONTROL_GENERAL + 0x012c)
++#define OMAP343X_CONTROL_FUSE_SR	(OMAP2_CONTROL_GENERAL + 0x0130)
+ #define OMAP343X_CONTROL_IVA2_BOOTADDR	(OMAP2_CONTROL_GENERAL + 0x0190)
+ #define OMAP343X_CONTROL_IVA2_BOOTMOD	(OMAP2_CONTROL_GENERAL + 0x0194)
+ #define OMAP343X_CONTROL_TEMP_SENSOR	(OMAP2_CONTROL_GENERAL + 0x02b4)
+@@ -172,6 +181,16 @@
+ #define OMAP2_SYSBOOT_1_MASK		(1 << 1)
+ #define OMAP2_SYSBOOT_0_MASK		(1 << 0)
+ 
++/* CONTROL_FUSE_SR bits */
++#define OMAP343X_SR2_SENNENABLE_MASK	(0x3 << 10)
++#define OMAP343X_SR2_SENNENABLE_SHIFT	10
++#define OMAP343X_SR2_SENPENABLE_MASK	(0x3 << 8)
++#define OMAP343X_SR2_SENPENABLE_SHIFT	8
++#define OMAP343X_SR1_SENNENABLE_MASK	(0x3 << 2)
++#define OMAP343X_SR1_SENNENABLE_SHIFT	2
++#define OMAP343X_SR1_SENPENABLE_MASK	(0x3 << 0)
++#define OMAP343X_SR1_SENPENABLE_SHIFT	0
++
+ #ifndef __ASSEMBLY__
+ #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+ extern void __iomem *omap_ctrl_base_get(void);
+diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h
+index 6a0459a..3667fd6 100644
+--- a/include/asm-arm/arch-omap/omap34xx.h
++++ b/include/asm-arm/arch-omap/omap34xx.h
+@@ -54,6 +54,8 @@
+ #define OMAP34XX_HSUSB_OTG_BASE	(L4_34XX_BASE + 0xAB000)
+ #define OMAP34XX_HSUSB_HOST_BASE	(L4_34XX_BASE + 0x64000)
+ #define OMAP34XX_USBTLL_BASE	(L4_34XX_BASE + 0x62000)
++#define OMAP34XX_SR1_BASE	0x480C9000
++#define OMAP34XX_SR2_BASE	0x480CB000
+ 
+ 
+ #if defined(CONFIG_ARCH_OMAP3430)
+-- 
+1.5.4.3
diff --git a/packages/linux/linux-omap2-git/omap3evm/0002-omap3-cpuidle.patch b/packages/linux/linux-omap2-git/omap3evm/0002-omap3-cpuidle.patch
new file mode 100644
index 0000000000..c17c690fe1
--- /dev/null
+++ b/packages/linux/linux-omap2-git/omap3evm/0002-omap3-cpuidle.patch
@@ -0,0 +1,88 @@
+From: "Rajendra Nayak" <rnayak@ti.com>

+To: <linux-omap@vger.kernel.org>

+Subject: [PATCH 02/02] Kconfig changes

+Date: 	Tue, 10 Jun 2008 12:39:02 +0530

+

+Updates the CPUidle Kconfig

+

+Signed-off-by: Rajendra Nayak <rnayak@ti.com>   

+

+---

+ arch/arm/Kconfig        |   10 ++++++++++

+ drivers/cpuidle/Kconfig |   28 ++++++++++++++++++++++------

+ 2 files changed, 32 insertions(+), 6 deletions(-)

+

+Index: linux-omap-2.6/arch/arm/Kconfig

+===================================================================

+--- linux-omap-2.6.orig/arch/arm/Kconfig	2008-06-10 11:43:10.790502713 +0530

++++ linux-omap-2.6/arch/arm/Kconfig	2008-06-10 11:43:38.701604549 +0530

+@@ -954,6 +954,16 @@ config ATAGS_PROC

+ 

+ endmenu

+ 

++if (ARCH_OMAP)

++

++menu "CPUIdle"

++

++source "drivers/cpuidle/Kconfig"

++

++endmenu

++

++endif

++

+ if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)

+ 

+ menu "CPU Frequency scaling"

+Index: linux-omap-2.6/drivers/cpuidle/Kconfig

+===================================================================

+--- linux-omap-2.6.orig/drivers/cpuidle/Kconfig	2008-06-10 11:43:10.790502713 +0530

++++ linux-omap-2.6/drivers/cpuidle/Kconfig	2008-06-10 12:06:36.139332151 +0530

+@@ -1,20 +1,36 @@

++menu "CPU idle PM support"

+ 

+ config CPU_IDLE

+ 	bool "CPU idle PM support"

+-	default ACPI

++	default n

+ 	help

+ 	  CPU idle is a generic framework for supporting software-controlled

+ 	  idle processor power management.  It includes modular cross-platform

+ 	  governors that can be swapped during runtime.

+ 

+-	  If you're using an ACPI-enabled platform, you should say Y here.

++	  If you're using a mobile platform that supports CPU idle PM (e.g.

++	  an ACPI-capable notebook), you should say Y here.

++

++if CPU_IDLE

++

++comment "Governors"

+ 

+ config CPU_IDLE_GOV_LADDER

+-	bool

++	bool "ladder"

+ 	depends on CPU_IDLE

+-	default y

++	default n

+ 

+ config CPU_IDLE_GOV_MENU

+-	bool

++	bool "menu"

+ 	depends on CPU_IDLE && NO_HZ

+-	default y

++	default n

++        help

++	  This cpuidle governor evaluates all available states and chooses the

++	  deepest state that meets all of the following constraints: BM activity,

++	  expected time until next timer interrupt, and last break event time

++	  delta.  It is designed to minimize power consumption.  Currently

++	  dynticks is required.

++

++endif   # CPU_IDLE

++

++endmenu

+

+--

+To unsubscribe from this list: send the line "unsubscribe linux-omap" in

+the body of a message to majordomo@vger.kernel.org

+More majordomo info at  http://vger.kernel.org/majordomo-info.html

+

diff --git a/packages/linux/linux-omap2-git/omap3evm/0003-ARM-OMAP-SmartReflex-driver.patch b/packages/linux/linux-omap2-git/omap3evm/0003-ARM-OMAP-SmartReflex-driver.patch
new file mode 100644
index 0000000000..40d5790367
--- /dev/null
+++ b/packages/linux/linux-omap2-git/omap3evm/0003-ARM-OMAP-SmartReflex-driver.patch
@@ -0,0 +1,1001 @@
+From: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+To: linux-omap@vger.kernel.org
+Cc: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+Subject: [PATCH 3/3] ARM: OMAP: SmartReflex driver: integration to linux-omap
+Date: 	Fri,  6 Jun 2008 12:49:49 +0300
+Message-Id: <1212745789-13926-3-git-send-email-ext-kalle.jokiniemi@nokia.com>
+
+- Changed register accesses to use prm_{read,write}_mod_reg and
+  prm_{set,clear,rmw}_mod_reg_bits() functions instread of
+  "REG_X = REG_Y" type accesses.
+
+- Changed direct register clock enables/disables to clockframework calls.
+
+- replaced cpu-related #ifdefs with if (cpu_is_xxxx()) calls.
+
+- Added E-fuse support: Use silicon characteristics parameters from E-fuse
+
+- added smartreflex_disable/enable calls to pm34xx.c suspend function.
+
+- Added "SmartReflex support" entry into Kconfig under "System type->TI OMAP
+  Implementations". It depends on ARCH_OMAP34XX and TWL4030_CORE.
+
+- Added "SmartReflex testing support" Kconfig option for using hard coded
+  software parameters instead of E-fuse parameters.
+
+Signed-off-by: Kalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
+---
+ arch/arm/mach-omap2/Makefile      |    3 +
+ arch/arm/mach-omap2/pm34xx.c      |    9 +
+ arch/arm/mach-omap2/smartreflex.c |  531 +++++++++++++++++++++++--------------
+ arch/arm/mach-omap2/smartreflex.h |    9 +-
+ arch/arm/plat-omap/Kconfig        |   31 +++
+ 5 files changed, 385 insertions(+), 198 deletions(-)
+
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index 50c6657..f645b6e 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -25,6 +25,9 @@ obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o
+ obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
+ endif
+ 
++# SmartReflex driver
++obj-$(CONFIG_OMAP_SMARTREFLEX)		+= smartreflex.o
++
+ # Clock framework
+ obj-$(CONFIG_ARCH_OMAP2)		+= clock24xx.o
+ obj-$(CONFIG_ARCH_OMAP3)		+= clock34xx.o
+diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
+index 7e775cc..3da4f47 100644
+--- a/arch/arm/mach-omap2/pm34xx.c
++++ b/arch/arm/mach-omap2/pm34xx.c
+@@ -36,6 +36,7 @@
+ 
+ #include "prm.h"
+ #include "pm.h"
++#include "smartreflex.h"
+ 
+ struct power_state {
+ 	struct powerdomain *pwrdm;
+@@ -256,6 +257,10 @@ static int omap3_pm_suspend(void)
+ 	struct power_state *pwrst;
+ 	int state, ret = 0;
+ 
++	/* XXX Disable smartreflex before entering suspend */
++	disable_smartreflex(SR1);
++	disable_smartreflex(SR2);
++
+ 	/* Read current next_pwrsts */
+ 	list_for_each_entry(pwrst, &pwrst_list, node)
+ 		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
+@@ -287,6 +292,10 @@ restore:
+ 		printk(KERN_INFO "Successfully put all powerdomains "
+ 		       "to target state\n");
+ 
++	/* XXX Enable smartreflex after suspend */
++	enable_smartreflex(SR1);
++	enable_smartreflex(SR2);
++
+ 	return ret;
+ }
+ 
+diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
+index dae7460..0b10a5d 100644
+--- a/arch/arm/mach-omap2/smartreflex.c
++++ b/arch/arm/mach-omap2/smartreflex.c
+@@ -3,6 +3,9 @@
+  *
+  * OMAP34XX SmartReflex Voltage Control
+  *
++ * Copyright (C) 2008 Nokia Corporation
++ * Kalle Jokiniemi
++ *
+  * Copyright (C) 2007 Texas Instruments, Inc.
+  * Lesly A M <x0080970@ti.com>
+  *
+@@ -20,13 +23,16 @@
+ #include <linux/err.h>
+ #include <linux/clk.h>
+ #include <linux/sysfs.h>
+-
+-#include <asm/arch/prcm.h>
+-#include <asm/arch/power_companion.h>
++#include <linux/kobject.h>
++#include <linux/i2c/twl4030.h>
+ #include <linux/io.h>
+ 
+-#include "prcm-regs.h"
++#include <asm/arch/omap34xx.h>
++#include <asm/arch/control.h>
++
++#include "prm.h"
+ #include "smartreflex.h"
++#include "prm-regbits-34xx.h"
+ 
+ 
+ /* #define DEBUG_SR 1 */
+@@ -37,11 +43,16 @@
+ #  define DPRINTK(fmt, args...)
+ #endif
+ 
++/* XXX: These should be relocated where-ever the OPP implementation will be */
++u32 current_vdd1_opp;
++u32 current_vdd2_opp;
++
+ struct omap_sr{
+ 	int srid;
+ 	int is_sr_reset;
+ 	int is_autocomp_active;
+ 	struct clk *fck;
++	u32 clk_length;
+ 	u32 req_opp_no;
+ 	u32 opp1_nvalue, opp2_nvalue, opp3_nvalue, opp4_nvalue, opp5_nvalue;
+ 	u32 senp_mod, senn_mod;
+@@ -53,6 +64,7 @@ static struct omap_sr sr1 = {
+ 	.srid = SR1,
+ 	.is_sr_reset = 1,
+ 	.is_autocomp_active = 0,
++	.clk_length = 0,
+ 	.srbase_addr = OMAP34XX_SR1_BASE,
+ };
+ 
+@@ -60,6 +72,7 @@ static struct omap_sr sr2 = {
+ 	.srid = SR2,
+ 	.is_sr_reset = 1,
+ 	.is_autocomp_active = 0,
++	.clk_length = 0,
+ 	.srbase_addr = OMAP34XX_SR2_BASE,
+ };
+ 
+@@ -85,8 +98,6 @@ static inline u32 sr_read_reg(struct omap_sr *sr, int offset)
+ 	return omap_readl(sr->srbase_addr + offset);
+ }
+ 
+-
+-#ifndef USE_EFUSE_VALUES
+ static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen)
+ {
+ 	u32 gn, rn, mul;
+@@ -100,7 +111,21 @@ static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen)
+ 		}
+ 	}
+ }
+-#endif
++
++static void sr_clk_get(struct omap_sr *sr)
++{
++	if (sr->srid == SR1) {
++		sr->fck = clk_get(NULL, "sr1_fck");
++		if (IS_ERR(sr->fck))
++			printk(KERN_ERR "Could not get sr1_fck\n");
++
++	} else if (sr->srid == SR2) {
++		sr->fck = clk_get(NULL, "sr2_fck");
++		if (IS_ERR(sr->fck))
++			printk(KERN_ERR "Could not get sr2_fck\n");
++
++	}
++}
+ 
+ static int sr_clk_enable(struct omap_sr *sr)
+ {
+@@ -131,22 +156,86 @@ static int sr_clk_disable(struct omap_sr *sr)
+ 	return 0;
+ }
+ 
+-static void sr_set_nvalues(struct omap_sr *sr)
++static void sr_set_clk_length(struct omap_sr *sr)
++{
++	struct clk *osc_sys_ck;
++	u32 sys_clk = 0;
++
++	osc_sys_ck = clk_get(NULL, "osc_sys_ck");
++	sys_clk = clk_get_rate(osc_sys_ck);
++	clk_put(osc_sys_ck);
++
++	switch (sys_clk) {
++	case 12000000:
++		sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
++		break;
++	case 13000000:
++		sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
++		break;
++	case 19200000:
++		sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
++		break;
++	case 26000000:
++		sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
++		break;
++	case 38400000:
++		sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
++		break;
++	default :
++		printk(KERN_ERR "Invalid sysclk value: %d\n", sys_clk);
++		break;
++	}
++}
++
++static void sr_set_efuse_nvalues(struct omap_sr *sr)
++{
++	if (sr->srid == SR1) {
++		sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
++					OMAP343X_SR1_SENNENABLE_MASK) >>
++					OMAP343X_SR1_SENNENABLE_SHIFT;
++
++		sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
++					OMAP343X_SR1_SENPENABLE_MASK) >>
++					OMAP343X_SR1_SENPENABLE_SHIFT;
++
++		sr->opp5_nvalue = omap_ctrl_readl(
++					OMAP343X_CONTROL_FUSE_OPP5_VDD1);
++		sr->opp4_nvalue = omap_ctrl_readl(
++					OMAP343X_CONTROL_FUSE_OPP4_VDD1);
++		sr->opp3_nvalue = omap_ctrl_readl(
++					OMAP343X_CONTROL_FUSE_OPP3_VDD1);
++		sr->opp2_nvalue = omap_ctrl_readl(
++					OMAP343X_CONTROL_FUSE_OPP2_VDD1);
++		sr->opp1_nvalue = omap_ctrl_readl(
++					OMAP343X_CONTROL_FUSE_OPP1_VDD1);
++	} else if (sr->srid == SR2) {
++		sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
++					OMAP343X_SR2_SENNENABLE_MASK) >>
++					OMAP343X_SR2_SENNENABLE_SHIFT;
++
++		sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
++					OMAP343X_SR2_SENPENABLE_MASK) >>
++					OMAP343X_SR2_SENPENABLE_SHIFT;
++
++		sr->opp3_nvalue = omap_ctrl_readl(
++					OMAP343X_CONTROL_FUSE_OPP3_VDD2);
++		sr->opp2_nvalue = omap_ctrl_readl(
++					OMAP343X_CONTROL_FUSE_OPP2_VDD2);
++		sr->opp1_nvalue = omap_ctrl_readl(
++					OMAP343X_CONTROL_FUSE_OPP1_VDD2);
++	}
++}
++
++/* Hard coded nvalues for testing purposes, may cause device to hang! */
++static void sr_set_testing_nvalues(struct omap_sr *sr)
+ {
+-#ifdef USE_EFUSE_VALUES
+-	u32 n1, n2;
+-#else
+ 	u32 senpval, sennval;
+ 	u32 senpgain, senngain;
+ 	u32 rnsenp, rnsenn;
+-#endif
+ 
+ 	if (sr->srid == SR1) {
+-#ifdef USE_EFUSE_VALUES
+-		/* Read values for VDD1 from EFUSE */
+-#else
+-		/* since E-Fuse Values are not available, calculating the
+-		 * reciprocal of the SenN and SenP values for SR1
++		/* Calculating the reciprocal of the SenN and SenP values
++		 * for SR1
+ 		 */
+ 		sr->senp_mod = 0x03;        /* SenN-M5 enabled */
+ 		sr->senn_mod = 0x03;
+@@ -216,15 +305,16 @@ static void sr_set_nvalues(struct omap_sr *sr)
+ 				(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+ 				(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+ 
++		/* XXX The clocks are enabled in the startup and NVALUE is
++		 * set also there. Disabling this for now, but this could
++		 * be related to dynamic sleep during boot */
++#if 0
+ 		sr_clk_enable(sr);
+ 		sr_write_reg(sr, NVALUERECIPROCAL, sr->opp3_nvalue);
+ 		sr_clk_disable(sr);
+-
+ #endif
++
+ 	} else if (sr->srid == SR2) {
+-#ifdef USE_EFUSE_VALUES
+-		/* Read values for VDD2 from EFUSE */
+-#else
+ 		/* since E-Fuse Values are not available, calculating the
+ 		 * reciprocal of the SenN and SenP values for SR2
+ 		 */
+@@ -269,134 +359,163 @@ static void sr_set_nvalues(struct omap_sr *sr)
+ 				(senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+ 				(rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+ 				(rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT));
+-
+-#endif
+ 	}
+ 
+ }
+ 
++static void sr_set_nvalues(struct omap_sr *sr)
++{
++	if (SR_TESTING_NVALUES)
++		sr_set_testing_nvalues(sr);
++	else
++		sr_set_efuse_nvalues(sr);
++}
++
+ static void sr_configure_vp(int srid)
+ {
+ 	u32 vpconfig;
+ 
+ 	if (srid == SR1) {
+ 		vpconfig = PRM_VP1_CONFIG_ERROROFFSET | PRM_VP1_CONFIG_ERRORGAIN
+-			| PRM_VP1_CONFIG_INITVOLTAGE | PRM_VP1_CONFIG_TIMEOUTEN;
+-
+-		PRM_VP1_CONFIG = vpconfig;
+-		PRM_VP1_VSTEPMIN = PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN |
+-						PRM_VP1_VSTEPMIN_VSTEPMIN;
+-
+-		PRM_VP1_VSTEPMAX = PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX |
+-						PRM_VP1_VSTEPMAX_VSTEPMAX;
+-
+-		PRM_VP1_VLIMITTO = PRM_VP1_VLIMITTO_VDDMAX |
+-			PRM_VP1_VLIMITTO_VDDMIN | PRM_VP1_VLIMITTO_TIMEOUT;
+-
+-		PRM_VP1_CONFIG |= PRM_VP1_CONFIG_INITVDD;
+-		PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_INITVDD;
++					| PRM_VP1_CONFIG_INITVOLTAGE
++					| PRM_VP1_CONFIG_TIMEOUTEN;
++
++		prm_write_mod_reg(vpconfig, OMAP3430_GR_MOD,
++					OMAP3_PRM_VP1_CONFIG_OFFSET);
++		prm_write_mod_reg(PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN |
++					PRM_VP1_VSTEPMIN_VSTEPMIN,
++					OMAP3430_GR_MOD,
++					OMAP3_PRM_VP1_VSTEPMIN_OFFSET);
++
++		prm_write_mod_reg(PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX |
++					PRM_VP1_VSTEPMAX_VSTEPMAX,
++					OMAP3430_GR_MOD,
++					OMAP3_PRM_VP1_VSTEPMAX_OFFSET);
++
++		prm_write_mod_reg(PRM_VP1_VLIMITTO_VDDMAX |
++					PRM_VP1_VLIMITTO_VDDMIN |
++					PRM_VP1_VLIMITTO_TIMEOUT,
++					OMAP3430_GR_MOD,
++					OMAP3_PRM_VP1_VLIMITTO_OFFSET);
++
++		/* Trigger initVDD value copy to voltage processor */
++		prm_set_mod_reg_bits(PRM_VP1_CONFIG_INITVDD, OMAP3430_GR_MOD,
++					OMAP3_PRM_VP1_CONFIG_OFFSET);
++		/* Clear initVDD copy trigger bit */
++		prm_clear_mod_reg_bits(PRM_VP1_CONFIG_INITVDD, OMAP3430_GR_MOD,
++					OMAP3_PRM_VP1_CONFIG_OFFSET);
+ 
+ 	} else if (srid == SR2) {
+ 		vpconfig = PRM_VP2_CONFIG_ERROROFFSET | PRM_VP2_CONFIG_ERRORGAIN
+-			| PRM_VP2_CONFIG_INITVOLTAGE | PRM_VP2_CONFIG_TIMEOUTEN;
+-
+-		PRM_VP2_CONFIG = vpconfig;
+-		PRM_VP2_VSTEPMIN = PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN |
+-						PRM_VP2_VSTEPMIN_VSTEPMIN;
+-
+-		PRM_VP2_VSTEPMAX = PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX |
+-						PRM_VP2_VSTEPMAX_VSTEPMAX;
+-
+-		PRM_VP2_VLIMITTO = PRM_VP2_VLIMITTO_VDDMAX |
+-			PRM_VP2_VLIMITTO_VDDMIN | PRM_VP2_VLIMITTO_TIMEOUT;
+-
+-		PRM_VP2_CONFIG |= PRM_VP2_CONFIG_INITVDD;
+-		PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_INITVDD;
++					| PRM_VP2_CONFIG_INITVOLTAGE
++					| PRM_VP2_CONFIG_TIMEOUTEN;
++
++		prm_write_mod_reg(vpconfig, OMAP3430_GR_MOD,
++					OMAP3_PRM_VP2_CONFIG_OFFSET);
++		prm_write_mod_reg(PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN |
++					PRM_VP2_VSTEPMIN_VSTEPMIN,
++					OMAP3430_GR_MOD,
++					OMAP3_PRM_VP2_VSTEPMIN_OFFSET);
++
++		prm_write_mod_reg(PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX |
++					PRM_VP2_VSTEPMAX_VSTEPMAX,
++					OMAP3430_GR_MOD,
++					OMAP3_PRM_VP2_VSTEPMAX_OFFSET);
++
++		prm_write_mod_reg(PRM_VP2_VLIMITTO_VDDMAX |
++					PRM_VP2_VLIMITTO_VDDMIN |
++					PRM_VP2_VLIMITTO_TIMEOUT,
++					OMAP3430_GR_MOD,
++					OMAP3_PRM_VP2_VLIMITTO_OFFSET);
++
++		/* Trigger initVDD value copy to voltage processor */
++		prm_set_mod_reg_bits(PRM_VP2_CONFIG_INITVDD, OMAP3430_GR_MOD,
++					OMAP3_PRM_VP2_CONFIG_OFFSET);
++		/* Reset initVDD copy trigger bit */
++		prm_clear_mod_reg_bits(PRM_VP2_CONFIG_INITVDD, OMAP3430_GR_MOD,
++					OMAP3_PRM_VP2_CONFIG_OFFSET);
+ 
+ 	}
+ }
+ 
+ static void sr_configure_vc(void)
+ {
+-	PRM_VC_SMPS_SA =
+-		(R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA1_SHIFT) |
+-		(R_SRI2C_SLAVE_ADDR << PRM_VC_SMPS_SA0_SHIFT);
+-
+-	PRM_VC_SMPS_VOL_RA = (R_VDD2_SR_CONTROL << PRM_VC_SMPS_VOLRA1_SHIFT) |
+-				(R_VDD1_SR_CONTROL << PRM_VC_SMPS_VOLRA0_SHIFT);
+-
+-	PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL0_ON << PRM_VC_CMD_ON_SHIFT) |
+-			(PRM_VC_CMD_VAL0_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
+-			(PRM_VC_CMD_VAL0_RET << PRM_VC_CMD_RET_SHIFT) |
+-			(PRM_VC_CMD_VAL0_OFF << PRM_VC_CMD_OFF_SHIFT);
+-
+-	PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL1_ON << PRM_VC_CMD_ON_SHIFT) |
+-			(PRM_VC_CMD_VAL1_ONLP << PRM_VC_CMD_ONLP_SHIFT) |
+-			(PRM_VC_CMD_VAL1_RET << PRM_VC_CMD_RET_SHIFT) |
+-			(PRM_VC_CMD_VAL1_OFF << PRM_VC_CMD_OFF_SHIFT);
+-
+-	PRM_VC_CH_CONF = PRM_VC_CH_CONF_CMD1 | PRM_VC_CH_CONF_RAV1;
+-
+-	PRM_VC_I2C_CFG = PRM_VC_I2C_CFG_MCODE | PRM_VC_I2C_CFG_HSEN
+-							| PRM_VC_I2C_CFG_SREN;
++	prm_write_mod_reg((R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA1_SHIFT) |
++			(R_SRI2C_SLAVE_ADDR << OMAP3430_SMPS_SA0_SHIFT),
++			OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_SA_OFFSET);
++
++	prm_write_mod_reg((R_VDD2_SR_CONTROL << OMAP3430_VOLRA1_SHIFT) |
++			(R_VDD1_SR_CONTROL << OMAP3430_VOLRA0_SHIFT),
++			OMAP3430_GR_MOD, OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET);
++
++	prm_write_mod_reg((OMAP3430_VC_CMD_VAL0_ON <<
++		OMAP3430_VC_CMD_ON_SHIFT) |
++		(OMAP3430_VC_CMD_VAL0_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
++		(OMAP3430_VC_CMD_VAL0_RET << OMAP3430_VC_CMD_RET_SHIFT) |
++		(OMAP3430_VC_CMD_VAL0_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
++		OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
++
++	prm_write_mod_reg((OMAP3430_VC_CMD_VAL1_ON <<
++		OMAP3430_VC_CMD_ON_SHIFT) |
++		(OMAP3430_VC_CMD_VAL1_ONLP << OMAP3430_VC_CMD_ONLP_SHIFT) |
++		(OMAP3430_VC_CMD_VAL1_RET << OMAP3430_VC_CMD_RET_SHIFT) |
++		(OMAP3430_VC_CMD_VAL1_OFF << OMAP3430_VC_CMD_OFF_SHIFT),
++		OMAP3430_GR_MOD, OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
++
++	prm_write_mod_reg(OMAP3430_CMD1 | OMAP3430_RAV1,
++				OMAP3430_GR_MOD,
++				OMAP3_PRM_VC_CH_CONF_OFFSET);
++
++	prm_write_mod_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN | OMAP3430_SREN,
++				OMAP3430_GR_MOD,
++				OMAP3_PRM_VC_I2C_CFG_OFFSET);
+ 
+ 	/* Setup voltctrl and other setup times */
++	/* XXX CONFIG_SYSOFFMODE has not been implemented yet */
+ #ifdef CONFIG_SYSOFFMODE
+-	PRM_VOLTCTRL = PRM_VOLTCTRL_AUTO_OFF | PRM_VOLTCTRL_AUTO_RET;
+-	PRM_CLKSETUP = PRM_CLKSETUP_DURATION;
+-	PRM_VOLTSETUP1 = (PRM_VOLTSETUP_TIME2 << PRM_VOLTSETUP_TIME2_OFFSET) |
+-			(PRM_VOLTSETUP_TIME1 << PRM_VOLTSETUP_TIME1_OFFSET);
+-	PRM_VOLTOFFSET = PRM_VOLTOFFSET_DURATION;
+-	PRM_VOLTSETUP2 = PRM_VOLTSETUP2_DURATION;
++	prm_write_mod_reg(OMAP3430_AUTO_OFF | OMAP3430_AUTO_RET,
++			OMAP3430_GR_MOD,
++			OMAP3_PRM_VOLTCTRL_OFFSET);
++
++	prm_write_mod_reg(OMAP3430_CLKSETUP_DURATION, OMAP3430_GR_MOD,
++			OMAP3_PRM_CLKSETUP_OFFSET);
++	prm_write_mod_reg((OMAP3430_VOLTSETUP_TIME2 <<
++			OMAP3430_VOLTSETUP_TIME2_OFFSET) |
++			(OMAP3430_VOLTSETUP_TIME1 <<
++			OMAP3430_VOLTSETUP_TIME1_OFFSET),
++			OMAP3430_GR_MOD, OMAP3_PRM_VOLTSETUP1_OFFSET);
++
++	prm_write_mod_reg(OMAP3430_VOLTOFFSET_DURATION, OMAP3430_GR_MOD,
++			OMAP3_PRM_VOLTOFFSET_OFFSET);
++	prm_write_mod_reg(OMAP3430_VOLTSETUP2_DURATION, OMAP3430_GR_MOD,
++			OMAP3_PRM_VOLTSETUP2_OFFSET);
+ #else
+-	PRM_VOLTCTRL |= PRM_VOLTCTRL_AUTO_RET;
++	prm_set_mod_reg_bits(OMAP3430_AUTO_RET, OMAP3430_GR_MOD,
++			OMAP3_PRM_VOLTCTRL_OFFSET);
+ #endif
+ 
+ }
+ 
+-
+ static void sr_configure(struct omap_sr *sr)
+ {
+-	u32 sys_clk, sr_clk_length = 0;
+ 	u32 sr_config;
+ 	u32 senp_en , senn_en;
+ 
++	if (sr->clk_length == 0)
++		sr_set_clk_length(sr);
++
+ 	senp_en = sr->senp_mod;
+ 	senn_en = sr->senn_mod;
+-
+-	sys_clk = prcm_get_system_clock_speed();
+-
+-	switch (sys_clk) {
+-	case 12000:
+-		sr_clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
+-		break;
+-	case 13000:
+-		sr_clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
+-		break;
+-	case 19200:
+-		sr_clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
+-		break;
+-	case 26000:
+-		sr_clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
+-		break;
+-	case 38400:
+-		sr_clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
+-		break;
+-	default :
+-		printk(KERN_ERR "Invalid sysclk value\n");
+-		break;
+-	}
+-
+-	DPRINTK(KERN_DEBUG "SR : sys clk %lu\n", sys_clk);
+ 	if (sr->srid == SR1) {
+ 		sr_config = SR1_SRCONFIG_ACCUMDATA |
+-			(sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
++			(sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+ 			SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
+ 			SRCONFIG_MINMAXAVG_EN |
+ 			(senn_en << SRCONFIG_SENNENABLE_SHIFT) |
+ 			(senp_en << SRCONFIG_SENPENABLE_SHIFT) |
+ 			SRCONFIG_DELAYCTRL;
+-
++		DPRINTK(KERN_DEBUG "setting SRCONFIG1 to 0x%08lx\n",
++						(unsigned long int) sr_config);
+ 		sr_write_reg(sr, SRCONFIG, sr_config);
+ 
+ 		sr_write_reg(sr, AVGWEIGHT, SR1_AVGWEIGHT_SENPAVGWEIGHT |
+@@ -408,18 +527,18 @@ static void sr_configure(struct omap_sr *sr)
+ 
+ 	} else if (sr->srid == SR2) {
+ 		sr_config = SR2_SRCONFIG_ACCUMDATA |
+-			(sr_clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
++			(sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+ 			SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
+ 			SRCONFIG_MINMAXAVG_EN |
+ 			(senn_en << SRCONFIG_SENNENABLE_SHIFT) |
+ 			(senp_en << SRCONFIG_SENPENABLE_SHIFT) |
+ 			SRCONFIG_DELAYCTRL;
+ 
++		DPRINTK(KERN_DEBUG "setting SRCONFIG2 to 0x%08lx\n",
++						(unsigned long int) sr_config);
+ 		sr_write_reg(sr, SRCONFIG, sr_config);
+-
+ 		sr_write_reg(sr, AVGWEIGHT, SR2_AVGWEIGHT_SENPAVGWEIGHT |
+ 					SR2_AVGWEIGHT_SENNAVGWEIGHT);
+-
+ 		sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
+ 			SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
+ 			(SR2_ERRWEIGHT | SR2_ERRMAXLIMIT | SR2_ERRMINLIMIT));
+@@ -428,9 +547,9 @@ static void sr_configure(struct omap_sr *sr)
+ 	sr->is_sr_reset = 0;
+ }
+ 
+-static void sr_enable(struct omap_sr *sr, u32 target_opp_no)
++static int sr_enable(struct omap_sr *sr, u32 target_opp_no)
+ {
+-	u32 nvalue_reciprocal, current_nvalue;
++	u32 nvalue_reciprocal;
+ 
+ 	sr->req_opp_no = target_opp_no;
+ 
+@@ -472,11 +591,10 @@ static void sr_enable(struct omap_sr *sr, u32 target_opp_no)
+ 		}
+ 	}
+ 
+-	current_nvalue = sr_read_reg(sr, NVALUERECIPROCAL);
+-
+-	if (current_nvalue == nvalue_reciprocal) {
+-		DPRINTK("System is already at the desired voltage level\n");
+-		return;
++	if (nvalue_reciprocal == 0) {
++		printk(KERN_NOTICE "OPP%d doesn't support SmartReflex\n",
++								target_opp_no);
++		return SR_FALSE;
+ 	}
+ 
+ 	sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
+@@ -485,18 +603,19 @@ static void sr_enable(struct omap_sr *sr, u32 target_opp_no)
+ 	sr_modify_reg(sr, ERRCONFIG,
+ 			(ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST),
+ 			(ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST));
+-
+ 	if (sr->srid == SR1) {
+ 		/* Enable VP1 */
+-		PRM_VP1_CONFIG |= PRM_VP1_CONFIG_VPENABLE;
++		prm_set_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE, OMAP3430_GR_MOD,
++				OMAP3_PRM_VP1_CONFIG_OFFSET);
+ 	} else if (sr->srid == SR2) {
+ 		/* Enable VP2 */
+-		PRM_VP2_CONFIG |= PRM_VP2_CONFIG_VPENABLE;
++		prm_set_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE, OMAP3430_GR_MOD,
++				OMAP3_PRM_VP2_CONFIG_OFFSET);
+ 	}
+ 
+ 	/* SRCONFIG - enable SR */
+ 	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
+-
++	return SR_TRUE;
+ }
+ 
+ static void sr_disable(struct omap_sr *sr)
+@@ -507,11 +626,13 @@ static void sr_disable(struct omap_sr *sr)
+ 	sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, ~SRCONFIG_SRENABLE);
+ 
+ 	if (sr->srid == SR1) {
+-		/* Enable VP1 */
+-		PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
++		/* Disable VP1 */
++		prm_clear_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE, OMAP3430_GR_MOD,
++					OMAP3_PRM_VP1_CONFIG_OFFSET);
+ 	} else if (sr->srid == SR2) {
+-		/* Enable VP2 */
+-		PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
++		/* Disable VP2 */
++		prm_clear_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE, OMAP3430_GR_MOD,
++					OMAP3_PRM_VP2_CONFIG_OFFSET);
+ 	}
+ }
+ 
+@@ -535,7 +656,12 @@ void sr_start_vddautocomap(int srid, u32 target_opp_no)
+ 									srid);
+ 
+ 	sr->is_autocomp_active = 1;
+-	sr_enable(sr, target_opp_no);
++	if (!sr_enable(sr, target_opp_no)) {
++		printk(KERN_WARNING "SR%d: VDD autocomp not activated\n", srid);
++		sr->is_autocomp_active = 0;
++		if (sr->is_sr_reset == 1)
++			sr_clk_disable(sr);
++	}
+ }
+ EXPORT_SYMBOL(sr_start_vddautocomap);
+ 
+@@ -574,20 +700,18 @@ void enable_smartreflex(int srid)
+ 
+ 	if (sr->is_autocomp_active == 1) {
+ 		if (sr->is_sr_reset == 1) {
+-			if (srid == SR1) {
+-				/* Enable SR clks */
+-				CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
+-				target_opp_no = get_opp_no(current_vdd1_opp);
++			/* Enable SR clks */
++			sr_clk_enable(sr);
+ 
+-			} else if (srid == SR2) {
+-				/* Enable SR clks */
+-				CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
++			if (srid == SR1)
++				target_opp_no = get_opp_no(current_vdd1_opp);
++			else if (srid == SR2)
+ 				target_opp_no = get_opp_no(current_vdd2_opp);
+-			}
+ 
+ 			sr_configure(sr);
+ 
+-			sr_enable(sr, target_opp_no);
++			if (!sr_enable(sr, target_opp_no))
++				sr_clk_disable(sr);
+ 		}
+ 	}
+ }
+@@ -602,15 +726,6 @@ void disable_smartreflex(int srid)
+ 		sr = &sr2;
+ 
+ 	if (sr->is_autocomp_active == 1) {
+-		if (srid == SR1) {
+-			/* Enable SR clk */
+-			CM_FCLKEN_WKUP |= SR1_CLK_ENABLE;
+-
+-		} else if (srid == SR2) {
+-			/* Enable SR clk */
+-			CM_FCLKEN_WKUP |= SR2_CLK_ENABLE;
+-		}
+-
+ 		if (sr->is_sr_reset == 0) {
+ 
+ 			sr->is_sr_reset = 1;
+@@ -618,17 +733,18 @@ void disable_smartreflex(int srid)
+ 			sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
+ 							~SRCONFIG_SRENABLE);
+ 
++			/* Disable SR clk */
++			sr_clk_disable(sr);
+ 			if (sr->srid == SR1) {
+-				/* Disable SR clk */
+-				CM_FCLKEN_WKUP &= ~SR1_CLK_ENABLE;
+-				/* Enable VP1 */
+-				PRM_VP1_CONFIG &= ~PRM_VP1_CONFIG_VPENABLE;
+-
++				/* Disable VP1 */
++				prm_clear_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE,
++						OMAP3430_GR_MOD,
++						OMAP3_PRM_VP1_CONFIG_OFFSET);
+ 			} else if (sr->srid == SR2) {
+-				/* Disable SR clk */
+-				CM_FCLKEN_WKUP &= ~SR2_CLK_ENABLE;
+-				/* Enable VP2 */
+-				PRM_VP2_CONFIG &= ~PRM_VP2_CONFIG_VPENABLE;
++				/* Disable VP2 */
++				prm_clear_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE,
++						OMAP3430_GR_MOD,
++						OMAP3_PRM_VP2_CONFIG_OFFSET);
+ 			}
+ 		}
+ 	}
+@@ -638,7 +754,6 @@ void disable_smartreflex(int srid)
+ /* Voltage Scaling using SR VCBYPASS */
+ int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
+ {
+-	int ret;
+ 	int sr_status = 0;
+ 	u32 vdd, target_opp_no;
+ 	u32 vc_bypass_value;
+@@ -651,39 +766,53 @@ int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
+ 	if (vdd == PRCM_VDD1) {
+ 		sr_status = sr_stop_vddautocomap(SR1);
+ 
+-		PRM_VC_CMD_VAL_0 = (PRM_VC_CMD_VAL_0 & ~PRM_VC_CMD_ON_MASK) |
+-						(vsel << PRM_VC_CMD_ON_SHIFT);
++		prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK,
++					(vsel << OMAP3430_VC_CMD_ON_SHIFT),
++					OMAP3430_GR_MOD,
++					OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
+ 		reg_addr = R_VDD1_SR_CONTROL;
+ 
+ 	} else if (vdd == PRCM_VDD2) {
+ 		sr_status = sr_stop_vddautocomap(SR2);
+ 
+-		PRM_VC_CMD_VAL_1 = (PRM_VC_CMD_VAL_1 & ~PRM_VC_CMD_ON_MASK) |
+-						(vsel << PRM_VC_CMD_ON_SHIFT);
++		prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK,
++					(vsel << OMAP3430_VC_CMD_ON_SHIFT),
++					OMAP3430_GR_MOD,
++					OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
+ 		reg_addr = R_VDD2_SR_CONTROL;
+ 	}
+ 
+-	vc_bypass_value = (vsel << PRM_VC_BYPASS_DATA_SHIFT) |
+-			(reg_addr << PRM_VC_BYPASS_REGADDR_SHIFT) |
+-			(R_SRI2C_SLAVE_ADDR << PRM_VC_BYPASS_SLAVEADDR_SHIFT);
++	vc_bypass_value = (vsel << OMAP3430_DATA_SHIFT) |
++			(reg_addr << OMAP3430_REGADDR_SHIFT) |
++			(R_SRI2C_SLAVE_ADDR << OMAP3430_SLAVEADDR_SHIFT);
+ 
+-	PRM_VC_BYPASS_VAL = vc_bypass_value;
++	prm_write_mod_reg(vc_bypass_value, OMAP3430_GR_MOD,
++			OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
+ 
+-	PRM_VC_BYPASS_VAL |= PRM_VC_BYPASS_VALID;
++	vc_bypass_value = prm_set_mod_reg_bits(OMAP3430_VALID, OMAP3430_GR_MOD,
++					OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
+ 
+-	DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, PRM_VC_BYPASS_VAL);
+-	DPRINTK("PRM_IRQST_MPU %X\n", PRM_IRQSTATUS_MPU);
++	DPRINTK("%s : PRM_VC_BYPASS_VAL %X\n", __func__, vc_bypass_value);
++	DPRINTK("PRM_IRQST_MPU %X\n", prm_read_mod_reg(OCP_MOD,
++					OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
+ 
+-	while ((PRM_VC_BYPASS_VAL & PRM_VC_BYPASS_VALID) != 0x0) {
+-		ret = loop_wait(&loop_cnt, &retries_cnt, 10);
+-		if (ret != PRCM_PASS) {
++	while ((vc_bypass_value & OMAP3430_VALID) != 0x0) {
++		loop_cnt++;
++		if (retries_cnt > 10) {
+ 			printk(KERN_INFO "Loop count exceeded in check SR I2C"
+ 								"write\n");
+-			return ret;
++			return SR_FAIL;
++		}
++		if (loop_cnt > 50) {
++			retries_cnt++;
++			loop_cnt = 0;
++			udelay(10);
+ 		}
++		vc_bypass_value = prm_read_mod_reg(OMAP3430_GR_MOD,
++					OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
+ 	}
+ 
+-	omap_udelay(T2_SMPS_UPDATE_DELAY);
++	udelay(T2_SMPS_UPDATE_DELAY);
+ 
+ 	if (sr_status) {
+ 		if (vdd == PRCM_VDD1)
+@@ -696,13 +825,15 @@ int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel)
+ }
+ 
+ /* Sysfs interface to select SR VDD1 auto compensation */
+-static ssize_t omap_sr_vdd1_autocomp_show(struct kset *subsys, char *buf)
++static ssize_t omap_sr_vdd1_autocomp_show(struct kobject *kobj,
++					struct kobj_attribute *attr, char *buf)
+ {
+ 	return sprintf(buf, "%d\n", sr1.is_autocomp_active);
+ }
+ 
+-static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys,
+-				const char *buf, size_t n)
++static ssize_t omap_sr_vdd1_autocomp_store(struct kobject *kobj,
++					struct kobj_attribute *attr,
++					const char *buf, size_t n)
+ {
+ 	u32 current_vdd1opp_no;
+ 	unsigned short value;
+@@ -722,7 +853,7 @@ static ssize_t omap_sr_vdd1_autocomp_store(struct kset *subsys,
+ 	return n;
+ }
+ 
+-static struct subsys_attribute sr_vdd1_autocomp = {
++static struct kobj_attribute sr_vdd1_autocomp = {
+ 	.attr = {
+ 	.name = __stringify(sr_vdd1_autocomp),
+ 	.mode = 0644,
+@@ -732,13 +863,15 @@ static struct subsys_attribute sr_vdd1_autocomp = {
+ };
+ 
+ /* Sysfs interface to select SR VDD2 auto compensation */
+-static ssize_t omap_sr_vdd2_autocomp_show(struct kset *subsys, char *buf)
++static ssize_t omap_sr_vdd2_autocomp_show(struct kobject *kobj,
++					struct kobj_attribute *attr, char *buf)
+ {
+ 	return sprintf(buf, "%d\n", sr2.is_autocomp_active);
+ }
+ 
+-static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys,
+-				const char *buf, size_t n)
++static ssize_t omap_sr_vdd2_autocomp_store(struct kobject *kobj,
++					struct kobj_attribute *attr,
++					const char *buf, size_t n)
+ {
+ 	u32 current_vdd2opp_no;
+ 	unsigned short value;
+@@ -758,7 +891,7 @@ static ssize_t omap_sr_vdd2_autocomp_store(struct kset *subsys,
+ 	return n;
+ }
+ 
+-static struct subsys_attribute sr_vdd2_autocomp = {
++static struct kobj_attribute sr_vdd2_autocomp = {
+ 	.attr = {
+ 	.name = __stringify(sr_vdd2_autocomp),
+ 	.mode = 0644,
+@@ -774,15 +907,19 @@ static int __init omap3_sr_init(void)
+ 	int ret = 0;
+ 	u8 RdReg;
+ 
+-#ifdef CONFIG_ARCH_OMAP34XX
+-	sr1.fck = clk_get(NULL, "sr1_fck");
+-	if (IS_ERR(sr1.fck))
+-		printk(KERN_ERR "Could not get sr1_fck\n");
+-
+-	sr2.fck = clk_get(NULL, "sr2_fck");
+-	if (IS_ERR(sr2.fck))
+-		printk(KERN_ERR "Could not get sr2_fck\n");
+-#endif /* #ifdef CONFIG_ARCH_OMAP34XX */
++	if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
++		current_vdd1_opp = PRCM_VDD1_OPP3;
++		current_vdd2_opp = PRCM_VDD2_OPP3;
++	} else {
++		current_vdd1_opp = PRCM_VDD1_OPP1;
++		current_vdd2_opp = PRCM_VDD1_OPP1;
++	}
++	if (cpu_is_omap34xx()) {
++		sr_clk_get(&sr1);
++		sr_clk_get(&sr2);
++	}
++	sr_set_clk_length(&sr1);
++	sr_set_clk_length(&sr2);
+ 
+ 	/* Call the VPConfig, VCConfig, set N Values. */
+ 	sr_set_nvalues(&sr1);
+@@ -794,22 +931,24 @@ static int __init omap3_sr_init(void)
+ 	sr_configure_vc();
+ 
+ 	/* Enable SR on T2 */
+-	ret = t2_in(PM_RECEIVER, &RdReg, R_DCDC_GLOBAL_CFG);
+-	RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX;
+-	ret |= t2_out(PM_RECEIVER, RdReg, R_DCDC_GLOBAL_CFG);
++	ret = twl4030_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &RdReg,
++					R_DCDC_GLOBAL_CFG);
+ 
++	RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX;
++	ret |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, RdReg,
++					R_DCDC_GLOBAL_CFG);
+ 
+ 	printk(KERN_INFO "SmartReflex driver initialized\n");
+ 
+-	ret = subsys_create_file(&power_subsys, &sr_vdd1_autocomp);
++	ret = sysfs_create_file(power_kobj, &sr_vdd1_autocomp.attr);
+ 	if (ret)
+-		printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
++		printk(KERN_ERR "sysfs_create_file failed: %d\n", ret);
+ 
+-	ret = subsys_create_file(&power_subsys, &sr_vdd2_autocomp);
++	ret = sysfs_create_file(power_kobj, &sr_vdd2_autocomp.attr);
+ 	if (ret)
+-		printk(KERN_ERR "subsys_create_file failed: %d\n", ret);
++		printk(KERN_ERR "sysfs_create_file failed: %d\n", ret);
+ 
+ 	return 0;
+ }
+ 
+-arch_initcall(omap3_sr_init);
++late_initcall(omap3_sr_init);
+diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
+index 2091a15..194429e 100644
+--- a/arch/arm/mach-omap2/smartreflex.h
++++ b/arch/arm/mach-omap2/smartreflex.h
+@@ -233,12 +233,18 @@
+ extern u32 current_vdd1_opp;
+ extern u32 current_vdd2_opp;
+ 
++#ifdef CONFIG_OMAP_SMARTREFLEX_TESTING
++#define SR_TESTING_NVALUES 	1
++#else
++#define SR_TESTING_NVALUES 	0
++#endif
++
+ /*
+  * Smartreflex module enable/disable interface.
+  * NOTE: if smartreflex is not enabled from sysfs, these functions will not
+  * do anything.
+  */
+-#if defined(CONFIG_ARCH_OMAP34XX) && defined(CONFIG_TWL4030_CORE)
++#ifdef CONFIG_OMAP_SMARTREFLEX
+ void enable_smartreflex(int srid);
+ void disable_smartreflex(int srid);
+ #else
+@@ -246,7 +252,6 @@ static inline void enable_smartreflex(int srid) {}
+ static inline void disable_smartreflex(int srid) {}
+ #endif
+ 
+-
+ #endif
+ 
+ 
+diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
+index b085b07..960c13f 100644
+--- a/arch/arm/plat-omap/Kconfig
++++ b/arch/arm/plat-omap/Kconfig
+@@ -56,6 +56,37 @@ config OMAP_DEBUG_CLOCKDOMAIN
+ 	  for every clockdomain register write.  However, the
+ 	  extra detail costs some memory.
+ 
++config OMAP_SMARTREFLEX
++	bool "SmartReflex support"
++	depends on ARCH_OMAP34XX && TWL4030_CORE
++	help
++	  Say Y if you want to enable SmartReflex.
++
++	  SmartReflex can perform continuous dynamic voltage
++	  scaling around the nominal operating point voltage
++	  according to silicon characteristics and operating
++	  conditions. Enabling SmartReflex reduces power
++	  consumption.
++
++	  Please note, that by default SmartReflex is only
++	  initialized. To enable the automatic voltage
++	  compensation for VDD1 and VDD2, user must write 1 to
++	  /sys/power/sr_vddX_autocomp, where X is 1 or 2.
++
++config OMAP_SMARTREFLEX_TESTING
++	bool "Smartreflex testing support"
++	depends on OMAP_SMARTREFLEX
++	default n
++	help
++	  Say Y if you want to enable SmartReflex testing with SW hardcoded
++	  NVALUES intead of E-fuse NVALUES set in factory silicon testing.
++
++	  In some devices the E-fuse values have not been set, even though
++	  SmartReflex modules are included. Using these hardcoded values set
++	  in software, one can test the SmartReflex features without E-fuse.
++
++	  WARNING: Enabling this option may cause your device to hang!
++
+ config OMAP_RESET_CLOCKS
+ 	bool "Reset unused clocks during boot"
+ 	depends on ARCH_OMAP
+-- 
+1.5.4.3
diff --git a/packages/linux/linux-omap2-git/omap3evm/defconfig b/packages/linux/linux-omap2-git/omap3evm/defconfig
new file mode 100644
index 0000000000..f74cef90ee
--- /dev/null
+++ b/packages/linux/linux-omap2-git/omap3evm/defconfig
@@ -0,0 +1,1567 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.26-rc3-omap1
+# Wed May 21 07:38:41 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_DMA_ATTRS is not set
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_LSF=y
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+
+#
+# OMAP Feature Selections
+#
+CONFIG_OMAP_DEBUG_SRAM_PATCH=y
+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
+# CONFIG_OMAP_RESET_CLOCKS is not set
+CONFIG_OMAP_BOOT_TAG=y
+CONFIG_OMAP_BOOT_REASON=y
+# CONFIG_OMAP_COMPONENT_VERSION is not set
+# CONFIG_OMAP_GPIO_SWITCH is not set
+# CONFIG_OMAP_MUX is not set
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MMU_FWK is not set
+# CONFIG_OMAP_MBOX_FWK is not set
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_DM_TIMER=y
+# CONFIG_OMAP_LL_DEBUG_UART1 is not set
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+CONFIG_OMAP_LL_DEBUG_UART3=y
+CONFIG_ARCH_OMAP34XX=y
+CONFIG_ARCH_OMAP3430=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_OMAP_LDP is not set
+# CONFIG_MACH_OMAP_3430SDP is not set
+CONFIG_MACH_OMAP3EVM=y
+# CONFIG_MACH_OMAP3_BEAGLE is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_LOCKDOWN_TO_64K_L2 is not set
+# CONFIG_CPU_LOCKDOWN_TO_128K_L2 is not set
+CONFIG_CPU_LOCKDOWN_TO_256K_L2=y
+# CONFIG_CPU_L2CACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=128
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=" quiet "
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+# CONFIG_NEON is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_BRIDGE=m
+CONFIG_VLAN_8021Q=m
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIUSB is not set
+# CONFIG_BT_HCIBTUSB is not set
+CONFIG_BT_HCIBTSDIO=m
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIBRF6150 is not set
+# CONFIG_BT_HCIH4P is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+CONFIG_CFG80211=m
+CONFIG_NL80211=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_MAC80211=m
+
+#
+# Rate control algorithm selection
+#
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_NONE is not set
+
+#
+# Selecting 'y' for an algorithm will
+#
+
+#
+# build the algorithm into mac80211.
+#
+CONFIG_MAC80211_RC_DEFAULT="pid"
+CONFIG_MAC80211_RC_PID=y
+# CONFIG_MAC80211_MESH is not set
+# CONFIG_MAC80211_LEDS is not set
+# CONFIG_MAC80211_DEBUG_PACKET_ALIGNMENT is not set
+# CONFIG_MAC80211_DEBUG is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_OMAP_NOR=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+CONFIG_MTD_ONENAND=y
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+# CONFIG_MTD_ONENAND_GENERIC is not set
+CONFIG_MTD_ONENAND_OMAP2=y
+# CONFIG_MTD_ONENAND_OTP is not set
+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
+# CONFIG_MTD_ONENAND_SIM is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_EEPROM_93CX6=m
+# CONFIG_OMAP_STI is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+CONFIG_NETDEVICES_MULTIQUEUE=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+CONFIG_SMC911X=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+CONFIG_LIBERTAS=m
+# CONFIG_LIBERTAS_USB is not set
+CONFIG_LIBERTAS_SDIO=m
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8187 is not set
+CONFIG_P54_COMMON=m
+# CONFIG_P54_USB is not set
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_ZD1211RW is not set
+# CONFIG_RT2X00 is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=y
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC2102 is not set
+# CONFIG_TOUCHSCREEN_TSC210X is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_ISP1301_OMAP is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_TLV320AIC23 is not set
+CONFIG_TWL4030_CORE=y
+CONFIG_TWL4030_GPIO=y
+# CONFIG_TWL4030_MADC is not set
+CONFIG_TWL4030_USB=y
+CONFIG_TWL4030_USB_HS_ULPI=y
+# CONFIG_TWL4030_PWRBUTTON is not set
+# CONFIG_TWL4030_POWEROFF is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_LP5521 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+CONFIG_SPI_DEBUG=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+CONFIG_SPI_OMAP24XX=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_TSC2101 is not set
+# CONFIG_SPI_TSC2102 is not set
+# CONFIG_SPI_TSC210X is not set
+# CONFIG_SPI_TSC2301 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+CONFIG_HAVE_GPIO_LIB=y
+
+#
+# GPIO Support
+#
+# CONFIG_DEBUG_GPIO is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_FB_OMAP=y
+# CONFIG_FB_OMAP_LCDC_EXTERNAL is not set
+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
+CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE=2
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_LOGO is not set
+
+#
+# Sound
+#
+CONFIG_SOUND=y
+
+#
+# Advanced Linux Sound Architecture
+#
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+# CONFIG_SND_MIXER_OSS is not set
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_DEBUG=y
+CONFIG_SND_DEBUG_DETECT=y
+CONFIG_SND_PCM_XRUN_DEBUG=y
+
+#
+# Generic devices
+#
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+
+#
+# ALSA ARM devices
+#
+# CONFIG_SND_OMAP_AIC23 is not set
+# CONFIG_SND_OMAP_TSC2101 is not set
+# CONFIG_SND_SX1 is not set
+# CONFIG_SND_OMAP_TSC2102 is not set
+# CONFIG_SND_OMAP24XX_EAC is not set
+
+#
+# SPI devices
+#
+
+#
+# USB devices
+#
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_CAIAQ is not set
+
+#
+# System on Chip audio support
+#
+CONFIG_SND_SOC=y
+
+#
+# ALSA SoC audio for Freescale SOCs
+#
+
+#
+# SoC Audio for the Texas Instruments OMAP
+#
+CONFIG_SND_OMAP_SOC=y
+CONFIG_SND_OMAP_SOC_MCBSP=y
+CONFIG_SND_OMAP_SOC_OMAP3EVM=y
+CONFIG_SND_SOC_TWL4030=y
+
+#
+# Open Sound System
+#
+CONFIG_SOUND_PRIME=y
+# CONFIG_SOUND_MSNDCLAS is not set
+# CONFIG_SOUND_MSNDPIN is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_OMAP_EHCI_PHY_MODE=y
+# CONFIG_OMAP_EHCI_TLL_MODE is not set
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_ISP116X_HCD=y
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_SL811_HCD=y
+CONFIG_USB_R8A66597_HCD=y
+CONFIG_USB_MUSB_HDRC=m
+CONFIG_USB_MUSB_SOC=y
+
+#
+# OMAP 343x high speed USB support
+#
+CONFIG_USB_MUSB_HOST=y
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+# CONFIG_USB_MUSB_OTG is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+CONFIG_USB_MUSB_HDRC_HCD=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_USB_INVENTRA_DMA=y
+# CONFIG_USB_TI_CPPI_DMA is not set
+CONFIG_USB_MUSB_LOGLEVEL=0
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+CONFIG_USB_GADGET_OMAP=y
+CONFIG_USB_OMAP=m
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_USB_G_PRINTER=m
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=m
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_OMAP_HS=y
+# CONFIG_MMC_SPI is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+CONFIG_RTC_DRV_TWL4030=y
+# CONFIG_RTC_DRV_S35390A is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_UIO is not set
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_XFS_FS=m
+CONFIG_XFS_QUOTA=y
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+# CONFIG_NTFS_RW is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+CONFIG_HFSPLUS_FS=m
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_CRAMFS=m
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/packages/linux/linux-omap2-git/omap3evm/no-harry-potter.diff b/packages/linux/linux-omap2-git/omap3evm/no-harry-potter.diff
new file mode 100644
index 0000000000..2bb20ab9c0
--- /dev/null
+++ b/packages/linux/linux-omap2-git/omap3evm/no-harry-potter.diff
@@ -0,0 +1,11 @@
+--- /tmp/Makefile	2008-04-24 14:36:20.509598016 +0200
++++ git/arch/arm/Makefile	2008-04-24 14:36:31.949546584 +0200
+@@ -47,7 +47,7 @@
+ # Note that GCC does not numerically define an architecture version
+ # macro, but instead defines a whole series of macros which makes
+ # testing for a specific architecture or later rather impossible.
+-arch-$(CONFIG_CPU_32v7)		:=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7a,-march=armv5t -Wa$(comma)-march=armv7a)
++arch-$(CONFIG_CPU_32v7)		:=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
+ arch-$(CONFIG_CPU_32v6)		:=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
+ # Only override the compiler option if ARMv6. The ARMv6K extensions are
+ # always available in ARMv7